1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2018 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7 #include <linux/of_address.h> 8 #include <linux/platform_device.h> 9 #include <linux/bitfield.h> 10 #include <linux/seq_file.h> 11 #include <linux/debugfs.h> 12 #include <linux/regmap.h> 13 14 #define MSR_CLK_DUTY 0x0 15 #define MSR_CLK_REG0 0x4 16 #define MSR_CLK_REG1 0x8 17 #define MSR_CLK_REG2 0xc 18 19 #define MSR_DURATION GENMASK(15, 0) 20 #define MSR_ENABLE BIT(16) 21 #define MSR_CONT BIT(17) /* continuous measurement */ 22 #define MSR_INTR BIT(18) /* interrupts */ 23 #define MSR_RUN BIT(19) 24 #define MSR_CLK_SRC GENMASK(26, 20) 25 #define MSR_BUSY BIT(31) 26 27 #define MSR_VAL_MASK GENMASK(15, 0) 28 29 #define DIV_MIN 32 30 #define DIV_STEP 32 31 #define DIV_MAX 640 32 33 #define CLK_MSR_MAX 128 34 35 struct meson_msr_id { 36 struct meson_msr *priv; 37 unsigned int id; 38 const char *name; 39 }; 40 41 struct meson_msr { 42 struct regmap *regmap; 43 struct meson_msr_id msr_table[CLK_MSR_MAX]; 44 }; 45 46 #define CLK_MSR_ID(__id, __name) \ 47 [__id] = {.id = __id, .name = __name,} 48 49 static struct meson_msr_id clk_msr_m8[CLK_MSR_MAX] = { 50 CLK_MSR_ID(0, "ring_osc_out_ee0"), 51 CLK_MSR_ID(1, "ring_osc_out_ee1"), 52 CLK_MSR_ID(2, "ring_osc_out_ee2"), 53 CLK_MSR_ID(3, "a9_ring_osck"), 54 CLK_MSR_ID(6, "vid_pll"), 55 CLK_MSR_ID(7, "clk81"), 56 CLK_MSR_ID(8, "encp"), 57 CLK_MSR_ID(9, "encl"), 58 CLK_MSR_ID(11, "eth_rmii"), 59 CLK_MSR_ID(13, "amclk"), 60 CLK_MSR_ID(14, "fec_clk_0"), 61 CLK_MSR_ID(15, "fec_clk_1"), 62 CLK_MSR_ID(16, "fec_clk_2"), 63 CLK_MSR_ID(18, "a9_clk_div16"), 64 CLK_MSR_ID(19, "hdmi_sys"), 65 CLK_MSR_ID(20, "rtc_osc_clk_out"), 66 CLK_MSR_ID(21, "i2s_clk_in_src0"), 67 CLK_MSR_ID(22, "clk_rmii_from_pad"), 68 CLK_MSR_ID(23, "hdmi_ch0_tmds"), 69 CLK_MSR_ID(24, "lvds_fifo"), 70 CLK_MSR_ID(26, "sc_clk_int"), 71 CLK_MSR_ID(28, "sar_adc"), 72 CLK_MSR_ID(30, "mpll_clk_test_out"), 73 CLK_MSR_ID(31, "audac_clkpi"), 74 CLK_MSR_ID(32, "vdac"), 75 CLK_MSR_ID(33, "sdhc_rx"), 76 CLK_MSR_ID(34, "sdhc_sd"), 77 CLK_MSR_ID(35, "mali"), 78 CLK_MSR_ID(36, "hdmi_tx_pixel"), 79 CLK_MSR_ID(38, "vdin_meas"), 80 CLK_MSR_ID(39, "pcm_sclk"), 81 CLK_MSR_ID(40, "pcm_mclk"), 82 CLK_MSR_ID(41, "eth_rx_tx"), 83 CLK_MSR_ID(42, "pwm_d"), 84 CLK_MSR_ID(43, "pwm_c"), 85 CLK_MSR_ID(44, "pwm_b"), 86 CLK_MSR_ID(45, "pwm_a"), 87 CLK_MSR_ID(46, "pcm2_sclk"), 88 CLK_MSR_ID(47, "ddr_dpll_pt"), 89 CLK_MSR_ID(48, "pwm_f"), 90 CLK_MSR_ID(49, "pwm_e"), 91 CLK_MSR_ID(59, "hcodec"), 92 CLK_MSR_ID(60, "usb_32k_alt"), 93 CLK_MSR_ID(61, "gpio"), 94 CLK_MSR_ID(62, "vid2_pll"), 95 CLK_MSR_ID(63, "mipi_csi_cfg"), 96 }; 97 98 static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { 99 CLK_MSR_ID(0, "ring_osc_out_ee_0"), 100 CLK_MSR_ID(1, "ring_osc_out_ee_1"), 101 CLK_MSR_ID(2, "ring_osc_out_ee_2"), 102 CLK_MSR_ID(3, "a53_ring_osc"), 103 CLK_MSR_ID(4, "gp0_pll"), 104 CLK_MSR_ID(6, "enci"), 105 CLK_MSR_ID(7, "clk81"), 106 CLK_MSR_ID(8, "encp"), 107 CLK_MSR_ID(9, "encl"), 108 CLK_MSR_ID(10, "vdac"), 109 CLK_MSR_ID(11, "rgmii_tx"), 110 CLK_MSR_ID(12, "pdm"), 111 CLK_MSR_ID(13, "amclk"), 112 CLK_MSR_ID(14, "fec_0"), 113 CLK_MSR_ID(15, "fec_1"), 114 CLK_MSR_ID(16, "fec_2"), 115 CLK_MSR_ID(17, "sys_pll_div16"), 116 CLK_MSR_ID(18, "sys_cpu_div16"), 117 CLK_MSR_ID(19, "hdmitx_sys"), 118 CLK_MSR_ID(20, "rtc_osc_out"), 119 CLK_MSR_ID(21, "i2s_in_src0"), 120 CLK_MSR_ID(22, "eth_phy_ref"), 121 CLK_MSR_ID(23, "hdmi_todig"), 122 CLK_MSR_ID(26, "sc_int"), 123 CLK_MSR_ID(28, "sar_adc"), 124 CLK_MSR_ID(31, "mpll_test_out"), 125 CLK_MSR_ID(32, "vdec"), 126 CLK_MSR_ID(35, "mali"), 127 CLK_MSR_ID(36, "hdmi_tx_pixel"), 128 CLK_MSR_ID(37, "i958"), 129 CLK_MSR_ID(38, "vdin_meas"), 130 CLK_MSR_ID(39, "pcm_sclk"), 131 CLK_MSR_ID(40, "pcm_mclk"), 132 CLK_MSR_ID(41, "eth_rx_or_rmii"), 133 CLK_MSR_ID(42, "mp0_out"), 134 CLK_MSR_ID(43, "fclk_div5"), 135 CLK_MSR_ID(44, "pwm_b"), 136 CLK_MSR_ID(45, "pwm_a"), 137 CLK_MSR_ID(46, "vpu"), 138 CLK_MSR_ID(47, "ddr_dpll_pt"), 139 CLK_MSR_ID(48, "mp1_out"), 140 CLK_MSR_ID(49, "mp2_out"), 141 CLK_MSR_ID(50, "mp3_out"), 142 CLK_MSR_ID(51, "nand_core"), 143 CLK_MSR_ID(52, "sd_emmc_b"), 144 CLK_MSR_ID(53, "sd_emmc_a"), 145 CLK_MSR_ID(55, "vid_pll_div_out"), 146 CLK_MSR_ID(56, "cci"), 147 CLK_MSR_ID(57, "wave420l_c"), 148 CLK_MSR_ID(58, "wave420l_b"), 149 CLK_MSR_ID(59, "hcodec"), 150 CLK_MSR_ID(60, "alt_32k"), 151 CLK_MSR_ID(61, "gpio_msr"), 152 CLK_MSR_ID(62, "hevc"), 153 CLK_MSR_ID(66, "vid_lock"), 154 CLK_MSR_ID(70, "pwm_f"), 155 CLK_MSR_ID(71, "pwm_e"), 156 CLK_MSR_ID(72, "pwm_d"), 157 CLK_MSR_ID(73, "pwm_c"), 158 CLK_MSR_ID(75, "aoclkx2_int"), 159 CLK_MSR_ID(76, "aoclk_int"), 160 CLK_MSR_ID(77, "rng_ring_osc_0"), 161 CLK_MSR_ID(78, "rng_ring_osc_1"), 162 CLK_MSR_ID(79, "rng_ring_osc_2"), 163 CLK_MSR_ID(80, "rng_ring_osc_3"), 164 CLK_MSR_ID(81, "vapb"), 165 CLK_MSR_ID(82, "ge2d"), 166 }; 167 168 static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { 169 CLK_MSR_ID(0, "ring_osc_out_ee_0"), 170 CLK_MSR_ID(1, "ring_osc_out_ee_1"), 171 CLK_MSR_ID(2, "ring_osc_out_ee_2"), 172 CLK_MSR_ID(3, "a53_ring_osc"), 173 CLK_MSR_ID(4, "gp0_pll"), 174 CLK_MSR_ID(5, "gp1_pll"), 175 CLK_MSR_ID(7, "clk81"), 176 CLK_MSR_ID(9, "encl"), 177 CLK_MSR_ID(17, "sys_pll_div16"), 178 CLK_MSR_ID(18, "sys_cpu_div16"), 179 CLK_MSR_ID(20, "rtc_osc_out"), 180 CLK_MSR_ID(23, "mmc_clk"), 181 CLK_MSR_ID(28, "sar_adc"), 182 CLK_MSR_ID(31, "mpll_test_out"), 183 CLK_MSR_ID(40, "mod_eth_tx_clk"), 184 CLK_MSR_ID(41, "mod_eth_rx_clk_rmii"), 185 CLK_MSR_ID(42, "mp0_out"), 186 CLK_MSR_ID(43, "fclk_div5"), 187 CLK_MSR_ID(44, "pwm_b"), 188 CLK_MSR_ID(45, "pwm_a"), 189 CLK_MSR_ID(46, "vpu"), 190 CLK_MSR_ID(47, "ddr_dpll_pt"), 191 CLK_MSR_ID(48, "mp1_out"), 192 CLK_MSR_ID(49, "mp2_out"), 193 CLK_MSR_ID(50, "mp3_out"), 194 CLK_MSR_ID(51, "sd_emmm_c"), 195 CLK_MSR_ID(52, "sd_emmc_b"), 196 CLK_MSR_ID(61, "gpio_msr"), 197 CLK_MSR_ID(66, "audio_slv_lrclk_c"), 198 CLK_MSR_ID(67, "audio_slv_lrclk_b"), 199 CLK_MSR_ID(68, "audio_slv_lrclk_a"), 200 CLK_MSR_ID(69, "audio_slv_sclk_c"), 201 CLK_MSR_ID(70, "audio_slv_sclk_b"), 202 CLK_MSR_ID(71, "audio_slv_sclk_a"), 203 CLK_MSR_ID(72, "pwm_d"), 204 CLK_MSR_ID(73, "pwm_c"), 205 CLK_MSR_ID(74, "wifi_beacon"), 206 CLK_MSR_ID(75, "tdmin_lb_lrcl"), 207 CLK_MSR_ID(76, "tdmin_lb_sclk"), 208 CLK_MSR_ID(77, "rng_ring_osc_0"), 209 CLK_MSR_ID(78, "rng_ring_osc_1"), 210 CLK_MSR_ID(79, "rng_ring_osc_2"), 211 CLK_MSR_ID(80, "rng_ring_osc_3"), 212 CLK_MSR_ID(81, "vapb"), 213 CLK_MSR_ID(82, "ge2d"), 214 CLK_MSR_ID(84, "audio_resample"), 215 CLK_MSR_ID(85, "audio_pdm_sys"), 216 CLK_MSR_ID(86, "audio_spdifout"), 217 CLK_MSR_ID(87, "audio_spdifin"), 218 CLK_MSR_ID(88, "audio_lrclk_f"), 219 CLK_MSR_ID(89, "audio_lrclk_e"), 220 CLK_MSR_ID(90, "audio_lrclk_d"), 221 CLK_MSR_ID(91, "audio_lrclk_c"), 222 CLK_MSR_ID(92, "audio_lrclk_b"), 223 CLK_MSR_ID(93, "audio_lrclk_a"), 224 CLK_MSR_ID(94, "audio_sclk_f"), 225 CLK_MSR_ID(95, "audio_sclk_e"), 226 CLK_MSR_ID(96, "audio_sclk_d"), 227 CLK_MSR_ID(97, "audio_sclk_c"), 228 CLK_MSR_ID(98, "audio_sclk_b"), 229 CLK_MSR_ID(99, "audio_sclk_a"), 230 CLK_MSR_ID(100, "audio_mclk_f"), 231 CLK_MSR_ID(101, "audio_mclk_e"), 232 CLK_MSR_ID(102, "audio_mclk_d"), 233 CLK_MSR_ID(103, "audio_mclk_c"), 234 CLK_MSR_ID(104, "audio_mclk_b"), 235 CLK_MSR_ID(105, "audio_mclk_a"), 236 CLK_MSR_ID(106, "pcie_refclk_n"), 237 CLK_MSR_ID(107, "pcie_refclk_p"), 238 CLK_MSR_ID(108, "audio_locker_out"), 239 CLK_MSR_ID(109, "audio_locker_in"), 240 }; 241 242 static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { 243 CLK_MSR_ID(0, "ring_osc_out_ee_0"), 244 CLK_MSR_ID(1, "ring_osc_out_ee_1"), 245 CLK_MSR_ID(2, "ring_osc_out_ee_2"), 246 CLK_MSR_ID(3, "sys_cpu_ring_osc"), 247 CLK_MSR_ID(4, "gp0_pll"), 248 CLK_MSR_ID(6, "enci"), 249 CLK_MSR_ID(7, "clk81"), 250 CLK_MSR_ID(8, "encp"), 251 CLK_MSR_ID(9, "encl"), 252 CLK_MSR_ID(10, "vdac"), 253 CLK_MSR_ID(11, "eth_tx"), 254 CLK_MSR_ID(12, "hifi_pll"), 255 CLK_MSR_ID(13, "mod_tcon"), 256 CLK_MSR_ID(14, "fec_0"), 257 CLK_MSR_ID(15, "fec_1"), 258 CLK_MSR_ID(16, "fec_2"), 259 CLK_MSR_ID(17, "sys_pll_div16"), 260 CLK_MSR_ID(18, "sys_cpu_div16"), 261 CLK_MSR_ID(19, "lcd_an_ph2"), 262 CLK_MSR_ID(20, "rtc_osc_out"), 263 CLK_MSR_ID(21, "lcd_an_ph3"), 264 CLK_MSR_ID(22, "eth_phy_ref"), 265 CLK_MSR_ID(23, "mpll_50m"), 266 CLK_MSR_ID(24, "eth_125m"), 267 CLK_MSR_ID(25, "eth_rmii"), 268 CLK_MSR_ID(26, "sc_int"), 269 CLK_MSR_ID(27, "in_mac"), 270 CLK_MSR_ID(28, "sar_adc"), 271 CLK_MSR_ID(29, "pcie_inp"), 272 CLK_MSR_ID(30, "pcie_inn"), 273 CLK_MSR_ID(31, "mpll_test_out"), 274 CLK_MSR_ID(32, "vdec"), 275 CLK_MSR_ID(33, "sys_cpu_ring_osc_1"), 276 CLK_MSR_ID(34, "eth_mpll_50m"), 277 CLK_MSR_ID(35, "mali"), 278 CLK_MSR_ID(36, "hdmi_tx_pixel"), 279 CLK_MSR_ID(37, "cdac"), 280 CLK_MSR_ID(38, "vdin_meas"), 281 CLK_MSR_ID(39, "bt656"), 282 CLK_MSR_ID(41, "eth_rx_or_rmii"), 283 CLK_MSR_ID(42, "mp0_out"), 284 CLK_MSR_ID(43, "fclk_div5"), 285 CLK_MSR_ID(44, "pwm_b"), 286 CLK_MSR_ID(45, "pwm_a"), 287 CLK_MSR_ID(46, "vpu"), 288 CLK_MSR_ID(47, "ddr_dpll_pt"), 289 CLK_MSR_ID(48, "mp1_out"), 290 CLK_MSR_ID(49, "mp2_out"), 291 CLK_MSR_ID(50, "mp3_out"), 292 CLK_MSR_ID(51, "sd_emmc_c"), 293 CLK_MSR_ID(52, "sd_emmc_b"), 294 CLK_MSR_ID(53, "sd_emmc_a"), 295 CLK_MSR_ID(54, "vpu_clkc"), 296 CLK_MSR_ID(55, "vid_pll_div_out"), 297 CLK_MSR_ID(56, "wave420l_a"), 298 CLK_MSR_ID(57, "wave420l_c"), 299 CLK_MSR_ID(58, "wave420l_b"), 300 CLK_MSR_ID(59, "hcodec"), 301 CLK_MSR_ID(61, "gpio_msr"), 302 CLK_MSR_ID(62, "hevcb"), 303 CLK_MSR_ID(63, "dsi_meas"), 304 CLK_MSR_ID(64, "spicc_1"), 305 CLK_MSR_ID(65, "spicc_0"), 306 CLK_MSR_ID(66, "vid_lock"), 307 CLK_MSR_ID(67, "dsi_phy"), 308 CLK_MSR_ID(68, "hdcp22_esm"), 309 CLK_MSR_ID(69, "hdcp22_skp"), 310 CLK_MSR_ID(70, "pwm_f"), 311 CLK_MSR_ID(71, "pwm_e"), 312 CLK_MSR_ID(72, "pwm_d"), 313 CLK_MSR_ID(73, "pwm_c"), 314 CLK_MSR_ID(75, "hevcf"), 315 CLK_MSR_ID(77, "rng_ring_osc_0"), 316 CLK_MSR_ID(78, "rng_ring_osc_1"), 317 CLK_MSR_ID(79, "rng_ring_osc_2"), 318 CLK_MSR_ID(80, "rng_ring_osc_3"), 319 CLK_MSR_ID(81, "vapb"), 320 CLK_MSR_ID(82, "ge2d"), 321 CLK_MSR_ID(83, "co_rx"), 322 CLK_MSR_ID(84, "co_tx"), 323 CLK_MSR_ID(89, "hdmi_todig"), 324 CLK_MSR_ID(90, "hdmitx_sys"), 325 CLK_MSR_ID(94, "eth_phy_rx"), 326 CLK_MSR_ID(95, "eth_phy_pll"), 327 CLK_MSR_ID(96, "vpu_b"), 328 CLK_MSR_ID(97, "cpu_b_tmp"), 329 CLK_MSR_ID(98, "ts"), 330 CLK_MSR_ID(99, "ring_osc_out_ee_3"), 331 CLK_MSR_ID(100, "ring_osc_out_ee_4"), 332 CLK_MSR_ID(101, "ring_osc_out_ee_5"), 333 CLK_MSR_ID(102, "ring_osc_out_ee_6"), 334 CLK_MSR_ID(103, "ring_osc_out_ee_7"), 335 CLK_MSR_ID(104, "ring_osc_out_ee_8"), 336 CLK_MSR_ID(105, "ring_osc_out_ee_9"), 337 CLK_MSR_ID(106, "ephy_test"), 338 CLK_MSR_ID(107, "au_dac_g128x"), 339 CLK_MSR_ID(108, "audio_locker_out"), 340 CLK_MSR_ID(109, "audio_locker_in"), 341 CLK_MSR_ID(110, "audio_tdmout_c_sclk"), 342 CLK_MSR_ID(111, "audio_tdmout_b_sclk"), 343 CLK_MSR_ID(112, "audio_tdmout_a_sclk"), 344 CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), 345 CLK_MSR_ID(114, "audio_tdmin_c_sclk"), 346 CLK_MSR_ID(115, "audio_tdmin_b_sclk"), 347 CLK_MSR_ID(116, "audio_tdmin_a_sclk"), 348 CLK_MSR_ID(117, "audio_resample"), 349 CLK_MSR_ID(118, "audio_pdm_sys"), 350 CLK_MSR_ID(119, "audio_spdifout_b"), 351 CLK_MSR_ID(120, "audio_spdifout"), 352 CLK_MSR_ID(121, "audio_spdifin"), 353 CLK_MSR_ID(122, "audio_pdm_dclk"), 354 }; 355 356 static int meson_measure_id(struct meson_msr_id *clk_msr_id, 357 unsigned int duration) 358 { 359 struct meson_msr *priv = clk_msr_id->priv; 360 unsigned int val; 361 int ret; 362 363 regmap_write(priv->regmap, MSR_CLK_REG0, 0); 364 365 /* Set measurement duration */ 366 regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_DURATION, 367 FIELD_PREP(MSR_DURATION, duration - 1)); 368 369 /* Set ID */ 370 regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_CLK_SRC, 371 FIELD_PREP(MSR_CLK_SRC, clk_msr_id->id)); 372 373 /* Enable & Start */ 374 regmap_update_bits(priv->regmap, MSR_CLK_REG0, 375 MSR_RUN | MSR_ENABLE, 376 MSR_RUN | MSR_ENABLE); 377 378 ret = regmap_read_poll_timeout(priv->regmap, MSR_CLK_REG0, 379 val, !(val & MSR_BUSY), 10, 10000); 380 if (ret) 381 return ret; 382 383 /* Disable */ 384 regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_ENABLE, 0); 385 386 /* Get the value in multiple of gate time counts */ 387 regmap_read(priv->regmap, MSR_CLK_REG2, &val); 388 389 if (val >= MSR_VAL_MASK) 390 return -EINVAL; 391 392 return DIV_ROUND_CLOSEST_ULL((val & MSR_VAL_MASK) * 1000000ULL, 393 duration); 394 } 395 396 static int meson_measure_best_id(struct meson_msr_id *clk_msr_id, 397 unsigned int *precision) 398 { 399 unsigned int duration = DIV_MAX; 400 int ret; 401 402 /* Start from max duration and down to min duration */ 403 do { 404 ret = meson_measure_id(clk_msr_id, duration); 405 if (ret >= 0) 406 *precision = (2 * 1000000) / duration; 407 else 408 duration -= DIV_STEP; 409 } while (duration >= DIV_MIN && ret == -EINVAL); 410 411 return ret; 412 } 413 414 static int clk_msr_show(struct seq_file *s, void *data) 415 { 416 struct meson_msr_id *clk_msr_id = s->private; 417 unsigned int precision = 0; 418 int val; 419 420 val = meson_measure_best_id(clk_msr_id, &precision); 421 if (val < 0) 422 return val; 423 424 seq_printf(s, "%d\t+/-%dHz\n", val, precision); 425 426 return 0; 427 } 428 DEFINE_SHOW_ATTRIBUTE(clk_msr); 429 430 static int clk_msr_summary_show(struct seq_file *s, void *data) 431 { 432 struct meson_msr_id *msr_table = s->private; 433 unsigned int precision = 0; 434 int val, i; 435 436 seq_puts(s, " clock rate precision\n"); 437 seq_puts(s, "---------------------------------------------\n"); 438 439 for (i = 0 ; i < CLK_MSR_MAX ; ++i) { 440 if (!msr_table[i].name) 441 continue; 442 443 val = meson_measure_best_id(&msr_table[i], &precision); 444 if (val < 0) 445 return val; 446 447 seq_printf(s, " %-20s %10d +/-%dHz\n", 448 msr_table[i].name, val, precision); 449 } 450 451 return 0; 452 } 453 DEFINE_SHOW_ATTRIBUTE(clk_msr_summary); 454 455 static const struct regmap_config meson_clk_msr_regmap_config = { 456 .reg_bits = 32, 457 .val_bits = 32, 458 .reg_stride = 4, 459 .max_register = MSR_CLK_REG2, 460 }; 461 462 static int meson_msr_probe(struct platform_device *pdev) 463 { 464 const struct meson_msr_id *match_data; 465 struct meson_msr *priv; 466 struct resource *res; 467 struct dentry *root, *clks; 468 void __iomem *base; 469 int i; 470 471 priv = devm_kzalloc(&pdev->dev, sizeof(struct meson_msr), 472 GFP_KERNEL); 473 if (!priv) 474 return -ENOMEM; 475 476 match_data = device_get_match_data(&pdev->dev); 477 if (!match_data) { 478 dev_err(&pdev->dev, "failed to get match data\n"); 479 return -ENODEV; 480 } 481 482 memcpy(priv->msr_table, match_data, sizeof(priv->msr_table)); 483 484 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 485 base = devm_ioremap_resource(&pdev->dev, res); 486 if (IS_ERR(base)) { 487 dev_err(&pdev->dev, "io resource mapping failed\n"); 488 return PTR_ERR(base); 489 } 490 491 priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, 492 &meson_clk_msr_regmap_config); 493 if (IS_ERR(priv->regmap)) 494 return PTR_ERR(priv->regmap); 495 496 root = debugfs_create_dir("meson-clk-msr", NULL); 497 clks = debugfs_create_dir("clks", root); 498 499 debugfs_create_file("measure_summary", 0444, root, 500 priv->msr_table, &clk_msr_summary_fops); 501 502 for (i = 0 ; i < CLK_MSR_MAX ; ++i) { 503 if (!priv->msr_table[i].name) 504 continue; 505 506 priv->msr_table[i].priv = priv; 507 508 debugfs_create_file(priv->msr_table[i].name, 0444, clks, 509 &priv->msr_table[i], &clk_msr_fops); 510 } 511 512 return 0; 513 } 514 515 static const struct of_device_id meson_msr_match_table[] = { 516 { 517 .compatible = "amlogic,meson-gx-clk-measure", 518 .data = (void *)clk_msr_gx, 519 }, 520 { 521 .compatible = "amlogic,meson8-clk-measure", 522 .data = (void *)clk_msr_m8, 523 }, 524 { 525 .compatible = "amlogic,meson8b-clk-measure", 526 .data = (void *)clk_msr_m8, 527 }, 528 { 529 .compatible = "amlogic,meson-axg-clk-measure", 530 .data = (void *)clk_msr_axg, 531 }, 532 { 533 .compatible = "amlogic,meson-g12a-clk-measure", 534 .data = (void *)clk_msr_g12a, 535 }, 536 { /* sentinel */ } 537 }; 538 539 static struct platform_driver meson_msr_driver = { 540 .probe = meson_msr_probe, 541 .driver = { 542 .name = "meson_msr", 543 .of_match_table = meson_msr_match_table, 544 }, 545 }; 546 builtin_platform_driver(meson_msr_driver); 547