1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2018, Linaro Limited 4 5 #include <linux/irq.h> 6 #include <linux/kernel.h> 7 #include <linux/init.h> 8 #include <linux/slab.h> 9 #include <linux/interrupt.h> 10 #include <linux/platform_device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/slimbus.h> 14 #include <linux/delay.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/of.h> 17 #include <linux/io.h> 18 #include <linux/soc/qcom/qmi.h> 19 #include <net/sock.h> 20 #include "slimbus.h" 21 22 /* NGD (Non-ported Generic Device) registers */ 23 #define NGD_CFG 0x0 24 #define NGD_CFG_ENABLE BIT(0) 25 #define NGD_CFG_RX_MSGQ_EN BIT(1) 26 #define NGD_CFG_TX_MSGQ_EN BIT(2) 27 #define NGD_STATUS 0x4 28 #define NGD_LADDR BIT(1) 29 #define NGD_RX_MSGQ_CFG 0x8 30 #define NGD_INT_EN 0x10 31 #define NGD_INT_RECFG_DONE BIT(24) 32 #define NGD_INT_TX_NACKED_2 BIT(25) 33 #define NGD_INT_MSG_BUF_CONTE BIT(26) 34 #define NGD_INT_MSG_TX_INVAL BIT(27) 35 #define NGD_INT_IE_VE_CHG BIT(28) 36 #define NGD_INT_DEV_ERR BIT(29) 37 #define NGD_INT_RX_MSG_RCVD BIT(30) 38 #define NGD_INT_TX_MSG_SENT BIT(31) 39 #define NGD_INT_STAT 0x14 40 #define NGD_INT_CLR 0x18 41 #define DEF_NGD_INT_MASK (NGD_INT_TX_NACKED_2 | NGD_INT_MSG_BUF_CONTE | \ 42 NGD_INT_MSG_TX_INVAL | NGD_INT_IE_VE_CHG | \ 43 NGD_INT_DEV_ERR | NGD_INT_TX_MSG_SENT | \ 44 NGD_INT_RX_MSG_RCVD) 45 46 /* Slimbus QMI service */ 47 #define SLIMBUS_QMI_SVC_ID 0x0301 48 #define SLIMBUS_QMI_SVC_V1 1 49 #define SLIMBUS_QMI_INS_ID 0 50 #define SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01 0x0020 51 #define SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01 0x0020 52 #define SLIMBUS_QMI_POWER_REQ_V01 0x0021 53 #define SLIMBUS_QMI_POWER_RESP_V01 0x0021 54 #define SLIMBUS_QMI_CHECK_FRAMER_STATUS_REQ 0x0022 55 #define SLIMBUS_QMI_CHECK_FRAMER_STATUS_RESP 0x0022 56 #define SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN 14 57 #define SLIMBUS_QMI_POWER_RESP_MAX_MSG_LEN 7 58 #define SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN 14 59 #define SLIMBUS_QMI_SELECT_INSTANCE_RESP_MAX_MSG_LEN 7 60 #define SLIMBUS_QMI_CHECK_FRAMER_STAT_RESP_MAX_MSG_LEN 7 61 /* QMI response timeout of 500ms */ 62 #define SLIMBUS_QMI_RESP_TOUT 1000 63 64 /* User defined commands */ 65 #define SLIM_USR_MC_GENERIC_ACK 0x25 66 #define SLIM_USR_MC_MASTER_CAPABILITY 0x0 67 #define SLIM_USR_MC_REPORT_SATELLITE 0x1 68 #define SLIM_USR_MC_ADDR_QUERY 0xD 69 #define SLIM_USR_MC_ADDR_REPLY 0xE 70 #define SLIM_USR_MC_DEFINE_CHAN 0x20 71 #define SLIM_USR_MC_DEF_ACT_CHAN 0x21 72 #define SLIM_USR_MC_CHAN_CTRL 0x23 73 #define SLIM_USR_MC_RECONFIG_NOW 0x24 74 #define SLIM_USR_MC_REQ_BW 0x28 75 #define SLIM_USR_MC_CONNECT_SRC 0x2C 76 #define SLIM_USR_MC_CONNECT_SINK 0x2D 77 #define SLIM_USR_MC_DISCONNECT_PORT 0x2E 78 #define SLIM_USR_MC_REPEAT_CHANGE_VALUE 0x0 79 80 #define QCOM_SLIM_NGD_AUTOSUSPEND MSEC_PER_SEC 81 #define SLIM_RX_MSGQ_TIMEOUT_VAL 0x10000 82 83 #define SLIM_LA_MGR 0xFF 84 #define SLIM_ROOT_FREQ 24576000 85 #define LADDR_RETRY 5 86 87 /* Per spec.max 40 bytes per received message */ 88 #define SLIM_MSGQ_BUF_LEN 40 89 #define QCOM_SLIM_NGD_DESC_NUM 32 90 91 #define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \ 92 ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16)) 93 94 #define INIT_MX_RETRIES 10 95 #define DEF_RETRY_MS 10 96 #define SAT_MAGIC_LSB 0xD9 97 #define SAT_MAGIC_MSB 0xC5 98 #define SAT_MSG_VER 0x1 99 #define SAT_MSG_PROT 0x1 100 #define to_ngd(d) container_of(d, struct qcom_slim_ngd, dev) 101 102 struct ngd_reg_offset_data { 103 u32 offset, size; 104 }; 105 106 static const struct ngd_reg_offset_data ngd_v1_5_offset_info = { 107 .offset = 0x1000, 108 .size = 0x1000, 109 }; 110 111 enum qcom_slim_ngd_state { 112 QCOM_SLIM_NGD_CTRL_AWAKE, 113 QCOM_SLIM_NGD_CTRL_IDLE, 114 QCOM_SLIM_NGD_CTRL_ASLEEP, 115 QCOM_SLIM_NGD_CTRL_DOWN, 116 }; 117 118 struct qcom_slim_ngd_qmi { 119 struct qmi_handle qmi; 120 struct sockaddr_qrtr svc_info; 121 struct qmi_handle svc_event_hdl; 122 struct qmi_response_type_v01 resp; 123 struct qmi_handle *handle; 124 struct completion qmi_comp; 125 }; 126 127 struct qcom_slim_ngd_ctrl; 128 struct qcom_slim_ngd; 129 130 struct qcom_slim_ngd_dma_desc { 131 struct dma_async_tx_descriptor *desc; 132 struct qcom_slim_ngd_ctrl *ctrl; 133 struct completion *comp; 134 dma_cookie_t cookie; 135 dma_addr_t phys; 136 void *base; 137 }; 138 139 struct qcom_slim_ngd { 140 struct platform_device *pdev; 141 void __iomem *base; 142 int id; 143 }; 144 145 struct qcom_slim_ngd_ctrl { 146 struct slim_framer framer; 147 struct slim_controller ctrl; 148 struct qcom_slim_ngd_qmi qmi; 149 struct qcom_slim_ngd *ngd; 150 struct device *dev; 151 void __iomem *base; 152 struct dma_chan *dma_rx_channel; 153 struct dma_chan *dma_tx_channel; 154 struct qcom_slim_ngd_dma_desc rx_desc[QCOM_SLIM_NGD_DESC_NUM]; 155 struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM]; 156 struct completion reconf; 157 struct work_struct m_work; 158 struct workqueue_struct *mwq; 159 spinlock_t tx_buf_lock; 160 enum qcom_slim_ngd_state state; 161 dma_addr_t rx_phys_base; 162 dma_addr_t tx_phys_base; 163 void *rx_base; 164 void *tx_base; 165 int tx_tail; 166 int tx_head; 167 u32 ver; 168 }; 169 170 enum slimbus_mode_enum_type_v01 { 171 /* To force a 32 bit signed enum. Do not change or use*/ 172 SLIMBUS_MODE_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN, 173 SLIMBUS_MODE_SATELLITE_V01 = 1, 174 SLIMBUS_MODE_MASTER_V01 = 2, 175 SLIMBUS_MODE_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX, 176 }; 177 178 enum slimbus_pm_enum_type_v01 { 179 /* To force a 32 bit signed enum. Do not change or use*/ 180 SLIMBUS_PM_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN, 181 SLIMBUS_PM_INACTIVE_V01 = 1, 182 SLIMBUS_PM_ACTIVE_V01 = 2, 183 SLIMBUS_PM_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX, 184 }; 185 186 enum slimbus_resp_enum_type_v01 { 187 SLIMBUS_RESP_ENUM_TYPE_MIN_VAL_V01 = INT_MIN, 188 SLIMBUS_RESP_SYNCHRONOUS_V01 = 1, 189 SLIMBUS_RESP_ENUM_TYPE_MAX_VAL_V01 = INT_MAX, 190 }; 191 192 struct slimbus_select_inst_req_msg_v01 { 193 uint32_t instance; 194 uint8_t mode_valid; 195 enum slimbus_mode_enum_type_v01 mode; 196 }; 197 198 struct slimbus_select_inst_resp_msg_v01 { 199 struct qmi_response_type_v01 resp; 200 }; 201 202 struct slimbus_power_req_msg_v01 { 203 enum slimbus_pm_enum_type_v01 pm_req; 204 uint8_t resp_type_valid; 205 enum slimbus_resp_enum_type_v01 resp_type; 206 }; 207 208 struct slimbus_power_resp_msg_v01 { 209 struct qmi_response_type_v01 resp; 210 }; 211 212 static struct qmi_elem_info slimbus_select_inst_req_msg_v01_ei[] = { 213 { 214 .data_type = QMI_UNSIGNED_4_BYTE, 215 .elem_len = 1, 216 .elem_size = sizeof(uint32_t), 217 .array_type = NO_ARRAY, 218 .tlv_type = 0x01, 219 .offset = offsetof(struct slimbus_select_inst_req_msg_v01, 220 instance), 221 .ei_array = NULL, 222 }, 223 { 224 .data_type = QMI_OPT_FLAG, 225 .elem_len = 1, 226 .elem_size = sizeof(uint8_t), 227 .array_type = NO_ARRAY, 228 .tlv_type = 0x10, 229 .offset = offsetof(struct slimbus_select_inst_req_msg_v01, 230 mode_valid), 231 .ei_array = NULL, 232 }, 233 { 234 .data_type = QMI_UNSIGNED_4_BYTE, 235 .elem_len = 1, 236 .elem_size = sizeof(enum slimbus_mode_enum_type_v01), 237 .array_type = NO_ARRAY, 238 .tlv_type = 0x10, 239 .offset = offsetof(struct slimbus_select_inst_req_msg_v01, 240 mode), 241 .ei_array = NULL, 242 }, 243 { 244 .data_type = QMI_EOTI, 245 .elem_len = 0, 246 .elem_size = 0, 247 .array_type = NO_ARRAY, 248 .tlv_type = 0x00, 249 .offset = 0, 250 .ei_array = NULL, 251 }, 252 }; 253 254 static struct qmi_elem_info slimbus_select_inst_resp_msg_v01_ei[] = { 255 { 256 .data_type = QMI_STRUCT, 257 .elem_len = 1, 258 .elem_size = sizeof(struct qmi_response_type_v01), 259 .array_type = NO_ARRAY, 260 .tlv_type = 0x02, 261 .offset = offsetof(struct slimbus_select_inst_resp_msg_v01, 262 resp), 263 .ei_array = qmi_response_type_v01_ei, 264 }, 265 { 266 .data_type = QMI_EOTI, 267 .elem_len = 0, 268 .elem_size = 0, 269 .array_type = NO_ARRAY, 270 .tlv_type = 0x00, 271 .offset = 0, 272 .ei_array = NULL, 273 }, 274 }; 275 276 static struct qmi_elem_info slimbus_power_req_msg_v01_ei[] = { 277 { 278 .data_type = QMI_UNSIGNED_4_BYTE, 279 .elem_len = 1, 280 .elem_size = sizeof(enum slimbus_pm_enum_type_v01), 281 .array_type = NO_ARRAY, 282 .tlv_type = 0x01, 283 .offset = offsetof(struct slimbus_power_req_msg_v01, 284 pm_req), 285 .ei_array = NULL, 286 }, 287 { 288 .data_type = QMI_OPT_FLAG, 289 .elem_len = 1, 290 .elem_size = sizeof(uint8_t), 291 .array_type = NO_ARRAY, 292 .tlv_type = 0x10, 293 .offset = offsetof(struct slimbus_power_req_msg_v01, 294 resp_type_valid), 295 }, 296 { 297 .data_type = QMI_SIGNED_4_BYTE_ENUM, 298 .elem_len = 1, 299 .elem_size = sizeof(enum slimbus_resp_enum_type_v01), 300 .array_type = NO_ARRAY, 301 .tlv_type = 0x10, 302 .offset = offsetof(struct slimbus_power_req_msg_v01, 303 resp_type), 304 }, 305 { 306 .data_type = QMI_EOTI, 307 .elem_len = 0, 308 .elem_size = 0, 309 .array_type = NO_ARRAY, 310 .tlv_type = 0x00, 311 .offset = 0, 312 .ei_array = NULL, 313 }, 314 }; 315 316 static struct qmi_elem_info slimbus_power_resp_msg_v01_ei[] = { 317 { 318 .data_type = QMI_STRUCT, 319 .elem_len = 1, 320 .elem_size = sizeof(struct qmi_response_type_v01), 321 .array_type = NO_ARRAY, 322 .tlv_type = 0x02, 323 .offset = offsetof(struct slimbus_power_resp_msg_v01, resp), 324 .ei_array = qmi_response_type_v01_ei, 325 }, 326 { 327 .data_type = QMI_EOTI, 328 .elem_len = 0, 329 .elem_size = 0, 330 .array_type = NO_ARRAY, 331 .tlv_type = 0x00, 332 .offset = 0, 333 .ei_array = NULL, 334 }, 335 }; 336 337 static int qcom_slim_qmi_send_select_inst_req(struct qcom_slim_ngd_ctrl *ctrl, 338 struct slimbus_select_inst_req_msg_v01 *req) 339 { 340 struct slimbus_select_inst_resp_msg_v01 resp = { { 0, 0 } }; 341 struct qmi_txn txn; 342 int rc; 343 344 rc = qmi_txn_init(ctrl->qmi.handle, &txn, 345 slimbus_select_inst_resp_msg_v01_ei, &resp); 346 if (rc < 0) { 347 dev_err(ctrl->dev, "QMI TXN init fail: %d\n", rc); 348 return rc; 349 } 350 351 rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn, 352 SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01, 353 SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN, 354 slimbus_select_inst_req_msg_v01_ei, req); 355 if (rc < 0) { 356 dev_err(ctrl->dev, "QMI send req fail %d\n", rc); 357 qmi_txn_cancel(&txn); 358 return rc; 359 } 360 361 rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT); 362 if (rc < 0) { 363 dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc); 364 return rc; 365 } 366 /* Check the response */ 367 if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { 368 dev_err(ctrl->dev, "QMI request failed 0x%x\n", 369 resp.resp.result); 370 return -EREMOTEIO; 371 } 372 373 return 0; 374 } 375 376 static void qcom_slim_qmi_power_resp_cb(struct qmi_handle *handle, 377 struct sockaddr_qrtr *sq, 378 struct qmi_txn *txn, const void *data) 379 { 380 struct slimbus_power_resp_msg_v01 *resp; 381 382 resp = (struct slimbus_power_resp_msg_v01 *)data; 383 if (resp->resp.result != QMI_RESULT_SUCCESS_V01) 384 pr_err("QMI power request failed 0x%x\n", 385 resp->resp.result); 386 387 complete(&txn->completion); 388 } 389 390 static int qcom_slim_qmi_send_power_request(struct qcom_slim_ngd_ctrl *ctrl, 391 struct slimbus_power_req_msg_v01 *req) 392 { 393 struct slimbus_power_resp_msg_v01 resp = { { 0, 0 } }; 394 struct qmi_txn txn; 395 int rc; 396 397 rc = qmi_txn_init(ctrl->qmi.handle, &txn, 398 slimbus_power_resp_msg_v01_ei, &resp); 399 400 rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn, 401 SLIMBUS_QMI_POWER_REQ_V01, 402 SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN, 403 slimbus_power_req_msg_v01_ei, req); 404 if (rc < 0) { 405 dev_err(ctrl->dev, "QMI send req fail %d\n", rc); 406 qmi_txn_cancel(&txn); 407 return rc; 408 } 409 410 rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT); 411 if (rc < 0) { 412 dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc); 413 return rc; 414 } 415 416 /* Check the response */ 417 if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { 418 dev_err(ctrl->dev, "QMI request failed 0x%x\n", 419 resp.resp.result); 420 return -EREMOTEIO; 421 } 422 423 return 0; 424 } 425 426 static struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = { 427 { 428 .type = QMI_RESPONSE, 429 .msg_id = SLIMBUS_QMI_POWER_RESP_V01, 430 .ei = slimbus_power_resp_msg_v01_ei, 431 .decoded_size = sizeof(struct slimbus_power_resp_msg_v01), 432 .fn = qcom_slim_qmi_power_resp_cb, 433 }, 434 {} 435 }; 436 437 static int qcom_slim_qmi_init(struct qcom_slim_ngd_ctrl *ctrl, 438 bool apps_is_master) 439 { 440 struct slimbus_select_inst_req_msg_v01 req; 441 struct qmi_handle *handle; 442 int rc; 443 444 handle = devm_kzalloc(ctrl->dev, sizeof(*handle), GFP_KERNEL); 445 if (!handle) 446 return -ENOMEM; 447 448 rc = qmi_handle_init(handle, SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN, 449 NULL, qcom_slim_qmi_msg_handlers); 450 if (rc < 0) { 451 dev_err(ctrl->dev, "QMI client init failed: %d\n", rc); 452 goto qmi_handle_init_failed; 453 } 454 455 rc = kernel_connect(handle->sock, 456 (struct sockaddr *)&ctrl->qmi.svc_info, 457 sizeof(ctrl->qmi.svc_info), 0); 458 if (rc < 0) { 459 dev_err(ctrl->dev, "Remote Service connect failed: %d\n", rc); 460 goto qmi_connect_to_service_failed; 461 } 462 463 /* Instance is 0 based */ 464 req.instance = (ctrl->ngd->id >> 1); 465 req.mode_valid = 1; 466 467 /* Mode indicates the role of the ADSP */ 468 if (apps_is_master) 469 req.mode = SLIMBUS_MODE_SATELLITE_V01; 470 else 471 req.mode = SLIMBUS_MODE_MASTER_V01; 472 473 ctrl->qmi.handle = handle; 474 475 rc = qcom_slim_qmi_send_select_inst_req(ctrl, &req); 476 if (rc) { 477 dev_err(ctrl->dev, "failed to select h/w instance\n"); 478 goto qmi_select_instance_failed; 479 } 480 481 return 0; 482 483 qmi_select_instance_failed: 484 ctrl->qmi.handle = NULL; 485 qmi_connect_to_service_failed: 486 qmi_handle_release(handle); 487 qmi_handle_init_failed: 488 devm_kfree(ctrl->dev, handle); 489 return rc; 490 } 491 492 static void qcom_slim_qmi_exit(struct qcom_slim_ngd_ctrl *ctrl) 493 { 494 if (!ctrl->qmi.handle) 495 return; 496 497 qmi_handle_release(ctrl->qmi.handle); 498 devm_kfree(ctrl->dev, ctrl->qmi.handle); 499 ctrl->qmi.handle = NULL; 500 } 501 502 static int qcom_slim_qmi_power_request(struct qcom_slim_ngd_ctrl *ctrl, 503 bool active) 504 { 505 struct slimbus_power_req_msg_v01 req; 506 507 if (active) 508 req.pm_req = SLIMBUS_PM_ACTIVE_V01; 509 else 510 req.pm_req = SLIMBUS_PM_INACTIVE_V01; 511 512 req.resp_type_valid = 0; 513 514 return qcom_slim_qmi_send_power_request(ctrl, &req); 515 } 516 517 static u32 *qcom_slim_ngd_tx_msg_get(struct qcom_slim_ngd_ctrl *ctrl, int len, 518 struct completion *comp) 519 { 520 struct qcom_slim_ngd_dma_desc *desc; 521 unsigned long flags; 522 523 spin_lock_irqsave(&ctrl->tx_buf_lock, flags); 524 525 if ((ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM == ctrl->tx_head) { 526 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 527 return NULL; 528 } 529 desc = &ctrl->txdesc[ctrl->tx_tail]; 530 desc->base = ctrl->tx_base + ctrl->tx_tail * SLIM_MSGQ_BUF_LEN; 531 desc->comp = comp; 532 ctrl->tx_tail = (ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM; 533 534 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 535 536 return desc->base; 537 } 538 539 static void qcom_slim_ngd_tx_msg_dma_cb(void *args) 540 { 541 struct qcom_slim_ngd_dma_desc *desc = args; 542 struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl; 543 unsigned long flags; 544 545 spin_lock_irqsave(&ctrl->tx_buf_lock, flags); 546 547 if (desc->comp) { 548 complete(desc->comp); 549 desc->comp = NULL; 550 } 551 552 ctrl->tx_head = (ctrl->tx_head + 1) % QCOM_SLIM_NGD_DESC_NUM; 553 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 554 } 555 556 static int qcom_slim_ngd_tx_msg_post(struct qcom_slim_ngd_ctrl *ctrl, 557 void *buf, int len) 558 { 559 struct qcom_slim_ngd_dma_desc *desc; 560 unsigned long flags; 561 int index, offset; 562 563 spin_lock_irqsave(&ctrl->tx_buf_lock, flags); 564 offset = buf - ctrl->tx_base; 565 index = offset/SLIM_MSGQ_BUF_LEN; 566 567 desc = &ctrl->txdesc[index]; 568 desc->phys = ctrl->tx_phys_base + offset; 569 desc->base = ctrl->tx_base + offset; 570 desc->ctrl = ctrl; 571 len = (len + 3) & 0xfc; 572 573 desc->desc = dmaengine_prep_slave_single(ctrl->dma_tx_channel, 574 desc->phys, len, 575 DMA_MEM_TO_DEV, 576 DMA_PREP_INTERRUPT); 577 if (!desc->desc) { 578 dev_err(ctrl->dev, "unable to prepare channel\n"); 579 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 580 return -EINVAL; 581 } 582 583 desc->desc->callback = qcom_slim_ngd_tx_msg_dma_cb; 584 desc->desc->callback_param = desc; 585 desc->desc->cookie = dmaengine_submit(desc->desc); 586 dma_async_issue_pending(ctrl->dma_tx_channel); 587 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 588 589 return 0; 590 } 591 592 static void qcom_slim_ngd_rx(struct qcom_slim_ngd_ctrl *ctrl, u8 *buf) 593 { 594 u8 mc, mt, len; 595 596 mt = SLIM_HEADER_GET_MT(buf[0]); 597 len = SLIM_HEADER_GET_RL(buf[0]); 598 mc = SLIM_HEADER_GET_MC(buf[1]); 599 600 if (mc == SLIM_USR_MC_MASTER_CAPABILITY && 601 mt == SLIM_MSG_MT_SRC_REFERRED_USER) 602 queue_work(ctrl->mwq, &ctrl->m_work); 603 604 if (mc == SLIM_MSG_MC_REPLY_INFORMATION || 605 mc == SLIM_MSG_MC_REPLY_VALUE || (mc == SLIM_USR_MC_ADDR_REPLY && 606 mt == SLIM_MSG_MT_SRC_REFERRED_USER) || 607 (mc == SLIM_USR_MC_GENERIC_ACK && 608 mt == SLIM_MSG_MT_SRC_REFERRED_USER)) { 609 slim_msg_response(&ctrl->ctrl, &buf[4], buf[3], len - 4); 610 pm_runtime_mark_last_busy(ctrl->dev); 611 } 612 } 613 614 static void qcom_slim_ngd_rx_msgq_cb(void *args) 615 { 616 struct qcom_slim_ngd_dma_desc *desc = args; 617 struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl; 618 619 qcom_slim_ngd_rx(ctrl, (u8 *)desc->base); 620 /* Add descriptor back to the queue */ 621 desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel, 622 desc->phys, SLIM_MSGQ_BUF_LEN, 623 DMA_DEV_TO_MEM, 624 DMA_PREP_INTERRUPT); 625 if (!desc->desc) { 626 dev_err(ctrl->dev, "Unable to prepare rx channel\n"); 627 return; 628 } 629 630 desc->desc->callback = qcom_slim_ngd_rx_msgq_cb; 631 desc->desc->callback_param = desc; 632 desc->desc->cookie = dmaengine_submit(desc->desc); 633 dma_async_issue_pending(ctrl->dma_rx_channel); 634 } 635 636 static int qcom_slim_ngd_post_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl) 637 { 638 struct qcom_slim_ngd_dma_desc *desc; 639 int i; 640 641 for (i = 0; i < QCOM_SLIM_NGD_DESC_NUM; i++) { 642 desc = &ctrl->rx_desc[i]; 643 desc->phys = ctrl->rx_phys_base + i * SLIM_MSGQ_BUF_LEN; 644 desc->ctrl = ctrl; 645 desc->base = ctrl->rx_base + i * SLIM_MSGQ_BUF_LEN; 646 desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel, 647 desc->phys, SLIM_MSGQ_BUF_LEN, 648 DMA_DEV_TO_MEM, 649 DMA_PREP_INTERRUPT); 650 if (!desc->desc) { 651 dev_err(ctrl->dev, "Unable to prepare rx channel\n"); 652 return -EINVAL; 653 } 654 655 desc->desc->callback = qcom_slim_ngd_rx_msgq_cb; 656 desc->desc->callback_param = desc; 657 desc->desc->cookie = dmaengine_submit(desc->desc); 658 } 659 dma_async_issue_pending(ctrl->dma_rx_channel); 660 661 return 0; 662 } 663 664 static int qcom_slim_ngd_init_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl) 665 { 666 struct device *dev = ctrl->dev; 667 int ret, size; 668 669 ctrl->dma_rx_channel = dma_request_slave_channel(dev, "rx"); 670 if (!ctrl->dma_rx_channel) { 671 dev_err(dev, "Failed to request dma channels"); 672 return -EINVAL; 673 } 674 675 size = QCOM_SLIM_NGD_DESC_NUM * SLIM_MSGQ_BUF_LEN; 676 ctrl->rx_base = dma_alloc_coherent(dev, size, &ctrl->rx_phys_base, 677 GFP_KERNEL); 678 if (!ctrl->rx_base) { 679 dev_err(dev, "dma_alloc_coherent failed\n"); 680 ret = -ENOMEM; 681 goto rel_rx; 682 } 683 684 ret = qcom_slim_ngd_post_rx_msgq(ctrl); 685 if (ret) { 686 dev_err(dev, "post_rx_msgq() failed 0x%x\n", ret); 687 goto rx_post_err; 688 } 689 690 return 0; 691 692 rx_post_err: 693 dma_free_coherent(dev, size, ctrl->rx_base, ctrl->rx_phys_base); 694 rel_rx: 695 dma_release_channel(ctrl->dma_rx_channel); 696 return ret; 697 } 698 699 static int qcom_slim_ngd_init_tx_msgq(struct qcom_slim_ngd_ctrl *ctrl) 700 { 701 struct device *dev = ctrl->dev; 702 unsigned long flags; 703 int ret = 0; 704 int size; 705 706 ctrl->dma_tx_channel = dma_request_slave_channel(dev, "tx"); 707 if (!ctrl->dma_tx_channel) { 708 dev_err(dev, "Failed to request dma channels"); 709 return -EINVAL; 710 } 711 712 size = ((QCOM_SLIM_NGD_DESC_NUM + 1) * SLIM_MSGQ_BUF_LEN); 713 ctrl->tx_base = dma_alloc_coherent(dev, size, &ctrl->tx_phys_base, 714 GFP_KERNEL); 715 if (!ctrl->tx_base) { 716 dev_err(dev, "dma_alloc_coherent failed\n"); 717 ret = -EINVAL; 718 goto rel_tx; 719 } 720 721 spin_lock_irqsave(&ctrl->tx_buf_lock, flags); 722 ctrl->tx_tail = 0; 723 ctrl->tx_head = 0; 724 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 725 726 return 0; 727 rel_tx: 728 dma_release_channel(ctrl->dma_tx_channel); 729 return ret; 730 } 731 732 static int qcom_slim_ngd_init_dma(struct qcom_slim_ngd_ctrl *ctrl) 733 { 734 int ret = 0; 735 736 ret = qcom_slim_ngd_init_rx_msgq(ctrl); 737 if (ret) { 738 dev_err(ctrl->dev, "rx dma init failed\n"); 739 return ret; 740 } 741 742 ret = qcom_slim_ngd_init_tx_msgq(ctrl); 743 if (ret) 744 dev_err(ctrl->dev, "tx dma init failed\n"); 745 746 return ret; 747 } 748 749 static irqreturn_t qcom_slim_ngd_interrupt(int irq, void *d) 750 { 751 struct qcom_slim_ngd_ctrl *ctrl = d; 752 void __iomem *base = ctrl->ngd->base; 753 u32 stat = readl(base + NGD_INT_STAT); 754 755 if ((stat & NGD_INT_MSG_BUF_CONTE) || 756 (stat & NGD_INT_MSG_TX_INVAL) || (stat & NGD_INT_DEV_ERR) || 757 (stat & NGD_INT_TX_NACKED_2)) { 758 dev_err(ctrl->dev, "Error Interrupt received 0x%x\n", stat); 759 } 760 761 writel(stat, base + NGD_INT_CLR); 762 763 return IRQ_HANDLED; 764 } 765 766 static int qcom_slim_ngd_xfer_msg(struct slim_controller *sctrl, 767 struct slim_msg_txn *txn) 768 { 769 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(sctrl->dev); 770 DECLARE_COMPLETION_ONSTACK(tx_sent); 771 DECLARE_COMPLETION_ONSTACK(done); 772 int ret, timeout, i; 773 u8 wbuf[SLIM_MSGQ_BUF_LEN]; 774 u8 rbuf[SLIM_MSGQ_BUF_LEN]; 775 u32 *pbuf; 776 u8 *puc; 777 u8 la = txn->la; 778 bool usr_msg = false; 779 780 if (txn->mt == SLIM_MSG_MT_CORE && 781 (txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION && 782 txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW)) 783 return 0; 784 785 if (txn->dt == SLIM_MSG_DEST_ENUMADDR) 786 return -EPROTONOSUPPORT; 787 788 if (txn->msg->num_bytes > SLIM_MSGQ_BUF_LEN || 789 txn->rl > SLIM_MSGQ_BUF_LEN) { 790 dev_err(ctrl->dev, "msg exceeds HW limit\n"); 791 return -EINVAL; 792 } 793 794 pbuf = qcom_slim_ngd_tx_msg_get(ctrl, txn->rl, &tx_sent); 795 if (!pbuf) { 796 dev_err(ctrl->dev, "Message buffer unavailable\n"); 797 return -ENOMEM; 798 } 799 800 if (txn->mt == SLIM_MSG_MT_CORE && 801 (txn->mc == SLIM_MSG_MC_CONNECT_SOURCE || 802 txn->mc == SLIM_MSG_MC_CONNECT_SINK || 803 txn->mc == SLIM_MSG_MC_DISCONNECT_PORT)) { 804 txn->mt = SLIM_MSG_MT_DEST_REFERRED_USER; 805 switch (txn->mc) { 806 case SLIM_MSG_MC_CONNECT_SOURCE: 807 txn->mc = SLIM_USR_MC_CONNECT_SRC; 808 break; 809 case SLIM_MSG_MC_CONNECT_SINK: 810 txn->mc = SLIM_USR_MC_CONNECT_SINK; 811 break; 812 case SLIM_MSG_MC_DISCONNECT_PORT: 813 txn->mc = SLIM_USR_MC_DISCONNECT_PORT; 814 break; 815 default: 816 return -EINVAL; 817 } 818 819 usr_msg = true; 820 i = 0; 821 wbuf[i++] = txn->la; 822 la = SLIM_LA_MGR; 823 wbuf[i++] = txn->msg->wbuf[0]; 824 if (txn->mc != SLIM_USR_MC_DISCONNECT_PORT) 825 wbuf[i++] = txn->msg->wbuf[1]; 826 827 txn->comp = &done; 828 ret = slim_alloc_txn_tid(sctrl, txn); 829 if (ret) { 830 dev_err(ctrl->dev, "Unable to allocate TID\n"); 831 return ret; 832 } 833 834 wbuf[i++] = txn->tid; 835 836 txn->msg->num_bytes = i; 837 txn->msg->wbuf = wbuf; 838 txn->msg->rbuf = rbuf; 839 txn->rl = txn->msg->num_bytes + 4; 840 } 841 842 /* HW expects length field to be excluded */ 843 txn->rl--; 844 puc = (u8 *)pbuf; 845 *pbuf = 0; 846 if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) { 847 *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 0, 848 la); 849 puc += 3; 850 } else { 851 *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 1, 852 la); 853 puc += 2; 854 } 855 856 if (slim_tid_txn(txn->mt, txn->mc)) 857 *(puc++) = txn->tid; 858 859 if (slim_ec_txn(txn->mt, txn->mc)) { 860 *(puc++) = (txn->ec & 0xFF); 861 *(puc++) = (txn->ec >> 8) & 0xFF; 862 } 863 864 if (txn->msg && txn->msg->wbuf) 865 memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes); 866 867 ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl); 868 if (ret) 869 return ret; 870 871 timeout = wait_for_completion_timeout(&tx_sent, HZ); 872 if (!timeout) { 873 dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc, 874 txn->mt); 875 return -ETIMEDOUT; 876 } 877 878 if (usr_msg) { 879 timeout = wait_for_completion_timeout(&done, HZ); 880 if (!timeout) { 881 dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", 882 txn->mc, txn->mt); 883 return -ETIMEDOUT; 884 } 885 } 886 887 return 0; 888 } 889 890 static int qcom_slim_ngd_xfer_msg_sync(struct slim_controller *ctrl, 891 struct slim_msg_txn *txn) 892 { 893 DECLARE_COMPLETION_ONSTACK(done); 894 int ret, timeout; 895 896 pm_runtime_get_sync(ctrl->dev); 897 898 txn->comp = &done; 899 900 ret = qcom_slim_ngd_xfer_msg(ctrl, txn); 901 if (ret) 902 return ret; 903 904 timeout = wait_for_completion_timeout(&done, HZ); 905 if (!timeout) { 906 dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc, 907 txn->mt); 908 return -ETIMEDOUT; 909 } 910 return 0; 911 } 912 913 static int qcom_slim_ngd_enable_stream(struct slim_stream_runtime *rt) 914 { 915 struct slim_device *sdev = rt->dev; 916 struct slim_controller *ctrl = sdev->ctrl; 917 struct slim_val_inf msg = {0}; 918 u8 wbuf[SLIM_MSGQ_BUF_LEN]; 919 u8 rbuf[SLIM_MSGQ_BUF_LEN]; 920 struct slim_msg_txn txn = {0,}; 921 int i, ret; 922 923 txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER; 924 txn.dt = SLIM_MSG_DEST_LOGICALADDR; 925 txn.la = SLIM_LA_MGR; 926 txn.ec = 0; 927 txn.msg = &msg; 928 txn.msg->num_bytes = 0; 929 txn.msg->wbuf = wbuf; 930 txn.msg->rbuf = rbuf; 931 932 for (i = 0; i < rt->num_ports; i++) { 933 struct slim_port *port = &rt->ports[i]; 934 935 if (txn.msg->num_bytes == 0) { 936 int seg_interval = SLIM_SLOTS_PER_SUPERFRAME/rt->ratem; 937 int exp; 938 939 wbuf[txn.msg->num_bytes++] = sdev->laddr; 940 wbuf[txn.msg->num_bytes] = rt->bps >> 2 | 941 (port->ch.aux_fmt << 6); 942 943 /* Data channel segment interval not multiple of 3 */ 944 exp = seg_interval % 3; 945 if (exp) 946 wbuf[txn.msg->num_bytes] |= BIT(5); 947 948 txn.msg->num_bytes++; 949 wbuf[txn.msg->num_bytes++] = exp << 4 | rt->prot; 950 951 if (rt->prot == SLIM_PROTO_ISO) 952 wbuf[txn.msg->num_bytes++] = 953 port->ch.prrate | 954 SLIM_CHANNEL_CONTENT_FL; 955 else 956 wbuf[txn.msg->num_bytes++] = port->ch.prrate; 957 958 ret = slim_alloc_txn_tid(ctrl, &txn); 959 if (ret) { 960 dev_err(&sdev->dev, "Fail to allocate TID\n"); 961 return -ENXIO; 962 } 963 wbuf[txn.msg->num_bytes++] = txn.tid; 964 } 965 wbuf[txn.msg->num_bytes++] = port->ch.id; 966 } 967 968 txn.mc = SLIM_USR_MC_DEF_ACT_CHAN; 969 txn.rl = txn.msg->num_bytes + 4; 970 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn); 971 if (ret) { 972 slim_free_txn_tid(ctrl, &txn); 973 dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc, 974 txn.mt); 975 return ret; 976 } 977 978 txn.mc = SLIM_USR_MC_RECONFIG_NOW; 979 txn.msg->num_bytes = 2; 980 wbuf[1] = sdev->laddr; 981 txn.rl = txn.msg->num_bytes + 4; 982 983 ret = slim_alloc_txn_tid(ctrl, &txn); 984 if (ret) { 985 dev_err(ctrl->dev, "Fail to allocate TID\n"); 986 return ret; 987 } 988 989 wbuf[0] = txn.tid; 990 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn); 991 if (ret) { 992 slim_free_txn_tid(ctrl, &txn); 993 dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc, 994 txn.mt); 995 } 996 997 return ret; 998 } 999 1000 static int qcom_slim_ngd_get_laddr(struct slim_controller *ctrl, 1001 struct slim_eaddr *ea, u8 *laddr) 1002 { 1003 struct slim_val_inf msg = {0}; 1004 u8 failed_ea[6] = {0, 0, 0, 0, 0, 0}; 1005 struct slim_msg_txn txn; 1006 u8 wbuf[10] = {0}; 1007 u8 rbuf[10] = {0}; 1008 int ret; 1009 1010 txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER; 1011 txn.dt = SLIM_MSG_DEST_LOGICALADDR; 1012 txn.la = SLIM_LA_MGR; 1013 txn.ec = 0; 1014 1015 txn.mc = SLIM_USR_MC_ADDR_QUERY; 1016 txn.rl = 11; 1017 txn.msg = &msg; 1018 txn.msg->num_bytes = 7; 1019 txn.msg->wbuf = wbuf; 1020 txn.msg->rbuf = rbuf; 1021 1022 ret = slim_alloc_txn_tid(ctrl, &txn); 1023 if (ret < 0) 1024 return ret; 1025 1026 wbuf[0] = (u8)txn.tid; 1027 memcpy(&wbuf[1], ea, sizeof(*ea)); 1028 1029 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn); 1030 if (ret) { 1031 slim_free_txn_tid(ctrl, &txn); 1032 return ret; 1033 } 1034 1035 if (!memcmp(rbuf, failed_ea, 6)) 1036 return -ENXIO; 1037 1038 *laddr = rbuf[6]; 1039 1040 return ret; 1041 } 1042 1043 static int qcom_slim_ngd_exit_dma(struct qcom_slim_ngd_ctrl *ctrl) 1044 { 1045 if (ctrl->dma_rx_channel) { 1046 dmaengine_terminate_sync(ctrl->dma_rx_channel); 1047 dma_release_channel(ctrl->dma_rx_channel); 1048 } 1049 1050 if (ctrl->dma_tx_channel) { 1051 dmaengine_terminate_sync(ctrl->dma_tx_channel); 1052 dma_release_channel(ctrl->dma_tx_channel); 1053 } 1054 1055 ctrl->dma_tx_channel = ctrl->dma_rx_channel = NULL; 1056 1057 return 0; 1058 } 1059 1060 static void qcom_slim_ngd_setup(struct qcom_slim_ngd_ctrl *ctrl) 1061 { 1062 u32 cfg = readl_relaxed(ctrl->ngd->base); 1063 1064 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) 1065 qcom_slim_ngd_init_dma(ctrl); 1066 1067 /* By default enable message queues */ 1068 cfg |= NGD_CFG_RX_MSGQ_EN; 1069 cfg |= NGD_CFG_TX_MSGQ_EN; 1070 1071 /* Enable NGD if it's not already enabled*/ 1072 if (!(cfg & NGD_CFG_ENABLE)) 1073 cfg |= NGD_CFG_ENABLE; 1074 1075 writel_relaxed(cfg, ctrl->ngd->base); 1076 } 1077 1078 static int qcom_slim_ngd_power_up(struct qcom_slim_ngd_ctrl *ctrl) 1079 { 1080 enum qcom_slim_ngd_state cur_state = ctrl->state; 1081 struct qcom_slim_ngd *ngd = ctrl->ngd; 1082 u32 laddr, rx_msgq; 1083 int timeout, ret = 0; 1084 1085 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) { 1086 timeout = wait_for_completion_timeout(&ctrl->qmi.qmi_comp, HZ); 1087 if (!timeout) 1088 return -EREMOTEIO; 1089 } 1090 1091 if (ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP || 1092 ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) { 1093 ret = qcom_slim_qmi_power_request(ctrl, true); 1094 if (ret) { 1095 dev_err(ctrl->dev, "SLIM QMI power request failed:%d\n", 1096 ret); 1097 return ret; 1098 } 1099 } 1100 1101 ctrl->ver = readl_relaxed(ctrl->base); 1102 /* Version info in 16 MSbits */ 1103 ctrl->ver >>= 16; 1104 1105 laddr = readl_relaxed(ngd->base + NGD_STATUS); 1106 if (laddr & NGD_LADDR) { 1107 /* 1108 * external MDM restart case where ADSP itself was active framer 1109 * For example, modem restarted when playback was active 1110 */ 1111 if (cur_state == QCOM_SLIM_NGD_CTRL_AWAKE) { 1112 dev_info(ctrl->dev, "Subsys restart: ADSP active framer\n"); 1113 return 0; 1114 } 1115 return 0; 1116 } 1117 1118 writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN); 1119 rx_msgq = readl_relaxed(ngd->base + NGD_RX_MSGQ_CFG); 1120 1121 writel_relaxed(rx_msgq|SLIM_RX_MSGQ_TIMEOUT_VAL, 1122 ngd->base + NGD_RX_MSGQ_CFG); 1123 qcom_slim_ngd_setup(ctrl); 1124 1125 timeout = wait_for_completion_timeout(&ctrl->reconf, HZ); 1126 if (!timeout) { 1127 dev_err(ctrl->dev, "capability exchange timed-out\n"); 1128 return -ETIMEDOUT; 1129 } 1130 1131 return 0; 1132 } 1133 1134 static void qcom_slim_ngd_notify_slaves(struct qcom_slim_ngd_ctrl *ctrl) 1135 { 1136 struct slim_device *sbdev; 1137 struct device_node *node; 1138 1139 for_each_child_of_node(ctrl->ngd->pdev->dev.of_node, node) { 1140 sbdev = of_slim_get_device(&ctrl->ctrl, node); 1141 if (!sbdev) 1142 continue; 1143 1144 if (slim_get_logical_addr(sbdev)) 1145 dev_err(ctrl->dev, "Failed to get logical address\n"); 1146 } 1147 } 1148 1149 static void qcom_slim_ngd_master_worker(struct work_struct *work) 1150 { 1151 struct qcom_slim_ngd_ctrl *ctrl; 1152 struct slim_msg_txn txn; 1153 struct slim_val_inf msg = {0}; 1154 int retries = 0; 1155 u8 wbuf[8]; 1156 int ret = 0; 1157 1158 ctrl = container_of(work, struct qcom_slim_ngd_ctrl, m_work); 1159 txn.dt = SLIM_MSG_DEST_LOGICALADDR; 1160 txn.ec = 0; 1161 txn.mc = SLIM_USR_MC_REPORT_SATELLITE; 1162 txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER; 1163 txn.la = SLIM_LA_MGR; 1164 wbuf[0] = SAT_MAGIC_LSB; 1165 wbuf[1] = SAT_MAGIC_MSB; 1166 wbuf[2] = SAT_MSG_VER; 1167 wbuf[3] = SAT_MSG_PROT; 1168 txn.msg = &msg; 1169 txn.msg->wbuf = wbuf; 1170 txn.msg->num_bytes = 4; 1171 txn.rl = 8; 1172 1173 dev_info(ctrl->dev, "SLIM SAT: Rcvd master capability\n"); 1174 1175 capability_retry: 1176 ret = qcom_slim_ngd_xfer_msg(&ctrl->ctrl, &txn); 1177 if (!ret) { 1178 if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP) 1179 complete(&ctrl->reconf); 1180 else 1181 dev_err(ctrl->dev, "unexpected state:%d\n", 1182 ctrl->state); 1183 1184 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) 1185 qcom_slim_ngd_notify_slaves(ctrl); 1186 1187 } else if (ret == -EIO) { 1188 dev_err(ctrl->dev, "capability message NACKed, retrying\n"); 1189 if (retries < INIT_MX_RETRIES) { 1190 msleep(DEF_RETRY_MS); 1191 retries++; 1192 goto capability_retry; 1193 } 1194 } else { 1195 dev_err(ctrl->dev, "SLIM: capability TX failed:%d\n", ret); 1196 } 1197 } 1198 1199 static int qcom_slim_ngd_runtime_resume(struct device *dev) 1200 { 1201 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev); 1202 int ret = 0; 1203 1204 if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP) 1205 ret = qcom_slim_ngd_power_up(ctrl); 1206 if (ret) { 1207 /* Did SSR cause this power up failure */ 1208 if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN) 1209 ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP; 1210 else 1211 dev_err(ctrl->dev, "HW wakeup attempt during SSR\n"); 1212 } else { 1213 ctrl->state = QCOM_SLIM_NGD_CTRL_AWAKE; 1214 } 1215 1216 return 0; 1217 } 1218 1219 static int qcom_slim_ngd_enable(struct qcom_slim_ngd_ctrl *ctrl, bool enable) 1220 { 1221 if (enable) { 1222 int ret = qcom_slim_qmi_init(ctrl, false); 1223 1224 if (ret) { 1225 dev_err(ctrl->dev, "qmi init fail, ret:%d, state:%d\n", 1226 ret, ctrl->state); 1227 return ret; 1228 } 1229 /* controller state should be in sync with framework state */ 1230 complete(&ctrl->qmi.qmi_comp); 1231 if (!pm_runtime_enabled(ctrl->dev) || 1232 !pm_runtime_suspended(ctrl->dev)) 1233 qcom_slim_ngd_runtime_resume(ctrl->dev); 1234 else 1235 pm_runtime_resume(ctrl->dev); 1236 pm_runtime_mark_last_busy(ctrl->dev); 1237 pm_runtime_put(ctrl->dev); 1238 1239 ret = slim_register_controller(&ctrl->ctrl); 1240 if (ret) { 1241 dev_err(ctrl->dev, "error adding slim controller\n"); 1242 return ret; 1243 } 1244 1245 dev_info(ctrl->dev, "SLIM controller Registered\n"); 1246 } else { 1247 qcom_slim_qmi_exit(ctrl); 1248 slim_unregister_controller(&ctrl->ctrl); 1249 } 1250 1251 return 0; 1252 } 1253 1254 static int qcom_slim_ngd_qmi_new_server(struct qmi_handle *hdl, 1255 struct qmi_service *service) 1256 { 1257 struct qcom_slim_ngd_qmi *qmi = 1258 container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl); 1259 struct qcom_slim_ngd_ctrl *ctrl = 1260 container_of(qmi, struct qcom_slim_ngd_ctrl, qmi); 1261 1262 qmi->svc_info.sq_family = AF_QIPCRTR; 1263 qmi->svc_info.sq_node = service->node; 1264 qmi->svc_info.sq_port = service->port; 1265 1266 qcom_slim_ngd_enable(ctrl, true); 1267 1268 return 0; 1269 } 1270 1271 static void qcom_slim_ngd_qmi_del_server(struct qmi_handle *hdl, 1272 struct qmi_service *service) 1273 { 1274 struct qcom_slim_ngd_qmi *qmi = 1275 container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl); 1276 1277 qmi->svc_info.sq_node = 0; 1278 qmi->svc_info.sq_port = 0; 1279 } 1280 1281 static struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = { 1282 .new_server = qcom_slim_ngd_qmi_new_server, 1283 .del_server = qcom_slim_ngd_qmi_del_server, 1284 }; 1285 1286 static int qcom_slim_ngd_qmi_svc_event_init(struct qcom_slim_ngd_ctrl *ctrl) 1287 { 1288 struct qcom_slim_ngd_qmi *qmi = &ctrl->qmi; 1289 int ret; 1290 1291 ret = qmi_handle_init(&qmi->svc_event_hdl, 0, 1292 &qcom_slim_ngd_qmi_svc_event_ops, NULL); 1293 if (ret < 0) { 1294 dev_err(ctrl->dev, "qmi_handle_init failed: %d\n", ret); 1295 return ret; 1296 } 1297 1298 ret = qmi_add_lookup(&qmi->svc_event_hdl, SLIMBUS_QMI_SVC_ID, 1299 SLIMBUS_QMI_SVC_V1, SLIMBUS_QMI_INS_ID); 1300 if (ret < 0) { 1301 dev_err(ctrl->dev, "qmi_add_lookup failed: %d\n", ret); 1302 qmi_handle_release(&qmi->svc_event_hdl); 1303 } 1304 return ret; 1305 } 1306 1307 static void qcom_slim_ngd_qmi_svc_event_deinit(struct qcom_slim_ngd_qmi *qmi) 1308 { 1309 qmi_handle_release(&qmi->svc_event_hdl); 1310 } 1311 1312 static struct platform_driver qcom_slim_ngd_driver; 1313 #define QCOM_SLIM_NGD_DRV_NAME "qcom,slim-ngd" 1314 1315 static const struct of_device_id qcom_slim_ngd_dt_match[] = { 1316 { 1317 .compatible = "qcom,slim-ngd-v1.5.0", 1318 .data = &ngd_v1_5_offset_info, 1319 }, 1320 {} 1321 }; 1322 1323 MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match); 1324 1325 static int of_qcom_slim_ngd_register(struct device *parent, 1326 struct qcom_slim_ngd_ctrl *ctrl) 1327 { 1328 const struct ngd_reg_offset_data *data; 1329 struct qcom_slim_ngd *ngd; 1330 const struct of_device_id *match; 1331 struct device_node *node; 1332 u32 id; 1333 1334 match = of_match_node(qcom_slim_ngd_dt_match, parent->of_node); 1335 data = match->data; 1336 for_each_available_child_of_node(parent->of_node, node) { 1337 if (of_property_read_u32(node, "reg", &id)) 1338 continue; 1339 1340 ngd = kzalloc(sizeof(*ngd), GFP_KERNEL); 1341 if (!ngd) 1342 return -ENOMEM; 1343 1344 ngd->pdev = platform_device_alloc(QCOM_SLIM_NGD_DRV_NAME, id); 1345 ngd->id = id; 1346 ngd->pdev->dev.parent = parent; 1347 ngd->pdev->driver_override = QCOM_SLIM_NGD_DRV_NAME; 1348 ngd->pdev->dev.of_node = node; 1349 ctrl->ngd = ngd; 1350 platform_set_drvdata(ngd->pdev, ctrl); 1351 1352 platform_device_add(ngd->pdev); 1353 ngd->base = ctrl->base + ngd->id * data->offset + 1354 (ngd->id - 1) * data->size; 1355 ctrl->ngd = ngd; 1356 1357 return 0; 1358 } 1359 1360 return -ENODEV; 1361 } 1362 1363 static int qcom_slim_ngd_probe(struct platform_device *pdev) 1364 { 1365 struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev); 1366 struct device *dev = &pdev->dev; 1367 int ret; 1368 1369 ctrl->ctrl.dev = dev; 1370 1371 pm_runtime_use_autosuspend(dev); 1372 pm_runtime_set_autosuspend_delay(dev, QCOM_SLIM_NGD_AUTOSUSPEND); 1373 pm_runtime_set_suspended(dev); 1374 pm_runtime_enable(dev); 1375 pm_runtime_get_noresume(dev); 1376 ret = qcom_slim_ngd_qmi_svc_event_init(ctrl); 1377 if (ret) { 1378 dev_err(&pdev->dev, "QMI service registration failed:%d", ret); 1379 return ret; 1380 } 1381 1382 INIT_WORK(&ctrl->m_work, qcom_slim_ngd_master_worker); 1383 ctrl->mwq = create_singlethread_workqueue("ngd_master"); 1384 if (!ctrl->mwq) { 1385 dev_err(&pdev->dev, "Failed to start master worker\n"); 1386 ret = -ENOMEM; 1387 goto wq_err; 1388 } 1389 1390 return 0; 1391 wq_err: 1392 qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi); 1393 if (ctrl->mwq) 1394 destroy_workqueue(ctrl->mwq); 1395 1396 return ret; 1397 } 1398 1399 static int qcom_slim_ngd_ctrl_probe(struct platform_device *pdev) 1400 { 1401 struct device *dev = &pdev->dev; 1402 struct qcom_slim_ngd_ctrl *ctrl; 1403 struct resource *res; 1404 int ret; 1405 1406 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 1407 if (!ctrl) 1408 return -ENOMEM; 1409 1410 dev_set_drvdata(dev, ctrl); 1411 1412 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1413 ctrl->base = devm_ioremap_resource(dev, res); 1414 if (IS_ERR(ctrl->base)) 1415 return PTR_ERR(ctrl->base); 1416 1417 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1418 if (!res) { 1419 dev_err(&pdev->dev, "no slimbus IRQ resource\n"); 1420 return -ENODEV; 1421 } 1422 1423 ret = devm_request_irq(dev, res->start, qcom_slim_ngd_interrupt, 1424 IRQF_TRIGGER_HIGH, "slim-ngd", ctrl); 1425 if (ret) { 1426 dev_err(&pdev->dev, "request IRQ failed\n"); 1427 return ret; 1428 } 1429 1430 ctrl->dev = dev; 1431 ctrl->framer.rootfreq = SLIM_ROOT_FREQ >> 3; 1432 ctrl->framer.superfreq = 1433 ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8; 1434 1435 ctrl->ctrl.a_framer = &ctrl->framer; 1436 ctrl->ctrl.clkgear = SLIM_MAX_CLK_GEAR; 1437 ctrl->ctrl.get_laddr = qcom_slim_ngd_get_laddr; 1438 ctrl->ctrl.enable_stream = qcom_slim_ngd_enable_stream; 1439 ctrl->ctrl.xfer_msg = qcom_slim_ngd_xfer_msg; 1440 ctrl->ctrl.wakeup = NULL; 1441 ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN; 1442 1443 spin_lock_init(&ctrl->tx_buf_lock); 1444 init_completion(&ctrl->reconf); 1445 init_completion(&ctrl->qmi.qmi_comp); 1446 1447 platform_driver_register(&qcom_slim_ngd_driver); 1448 return of_qcom_slim_ngd_register(dev, ctrl); 1449 } 1450 1451 static int qcom_slim_ngd_ctrl_remove(struct platform_device *pdev) 1452 { 1453 platform_driver_unregister(&qcom_slim_ngd_driver); 1454 1455 return 0; 1456 } 1457 1458 static int qcom_slim_ngd_remove(struct platform_device *pdev) 1459 { 1460 struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev); 1461 1462 pm_runtime_disable(&pdev->dev); 1463 qcom_slim_ngd_enable(ctrl, false); 1464 qcom_slim_ngd_exit_dma(ctrl); 1465 qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi); 1466 if (ctrl->mwq) 1467 destroy_workqueue(ctrl->mwq); 1468 1469 kfree(ctrl->ngd); 1470 ctrl->ngd = NULL; 1471 return 0; 1472 } 1473 1474 static int __maybe_unused qcom_slim_ngd_runtime_idle(struct device *dev) 1475 { 1476 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev); 1477 1478 if (ctrl->state == QCOM_SLIM_NGD_CTRL_AWAKE) 1479 ctrl->state = QCOM_SLIM_NGD_CTRL_IDLE; 1480 pm_request_autosuspend(dev); 1481 return -EAGAIN; 1482 } 1483 1484 static int __maybe_unused qcom_slim_ngd_runtime_suspend(struct device *dev) 1485 { 1486 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev); 1487 int ret = 0; 1488 1489 ret = qcom_slim_qmi_power_request(ctrl, false); 1490 if (ret && ret != -EBUSY) 1491 dev_info(ctrl->dev, "slim resource not idle:%d\n", ret); 1492 if (!ret || ret == -ETIMEDOUT) 1493 ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP; 1494 1495 return ret; 1496 } 1497 1498 static const struct dev_pm_ops qcom_slim_ngd_dev_pm_ops = { 1499 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1500 pm_runtime_force_resume) 1501 SET_RUNTIME_PM_OPS( 1502 qcom_slim_ngd_runtime_suspend, 1503 qcom_slim_ngd_runtime_resume, 1504 qcom_slim_ngd_runtime_idle 1505 ) 1506 }; 1507 1508 static struct platform_driver qcom_slim_ngd_ctrl_driver = { 1509 .probe = qcom_slim_ngd_ctrl_probe, 1510 .remove = qcom_slim_ngd_ctrl_remove, 1511 .driver = { 1512 .name = "qcom,slim-ngd-ctrl", 1513 .of_match_table = qcom_slim_ngd_dt_match, 1514 }, 1515 }; 1516 1517 static struct platform_driver qcom_slim_ngd_driver = { 1518 .probe = qcom_slim_ngd_probe, 1519 .remove = qcom_slim_ngd_remove, 1520 .driver = { 1521 .name = QCOM_SLIM_NGD_DRV_NAME, 1522 .pm = &qcom_slim_ngd_dev_pm_ops, 1523 }, 1524 }; 1525 1526 module_platform_driver(qcom_slim_ngd_ctrl_driver); 1527 MODULE_LICENSE("GPL v2"); 1528 MODULE_DESCRIPTION("Qualcomm SLIMBus NGD controller"); 1529