1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2018, Linaro Limited
4 
5 #include <linux/irq.h>
6 #include <linux/kernel.h>
7 #include <linux/init.h>
8 #include <linux/slab.h>
9 #include <linux/interrupt.h>
10 #include <linux/platform_device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/slimbus.h>
14 #include <linux/delay.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/mutex.h>
17 #include <linux/notifier.h>
18 #include <linux/remoteproc/qcom_rproc.h>
19 #include <linux/of.h>
20 #include <linux/io.h>
21 #include <linux/soc/qcom/qmi.h>
22 #include <linux/soc/qcom/pdr.h>
23 #include <net/sock.h>
24 #include "slimbus.h"
25 
26 /* NGD (Non-ported Generic Device) registers */
27 #define	NGD_CFG			0x0
28 #define	NGD_CFG_ENABLE		BIT(0)
29 #define	NGD_CFG_RX_MSGQ_EN	BIT(1)
30 #define	NGD_CFG_TX_MSGQ_EN	BIT(2)
31 #define	NGD_STATUS		0x4
32 #define NGD_LADDR		BIT(1)
33 #define	NGD_RX_MSGQ_CFG		0x8
34 #define	NGD_INT_EN		0x10
35 #define	NGD_INT_RECFG_DONE	BIT(24)
36 #define	NGD_INT_TX_NACKED_2	BIT(25)
37 #define	NGD_INT_MSG_BUF_CONTE	BIT(26)
38 #define	NGD_INT_MSG_TX_INVAL	BIT(27)
39 #define	NGD_INT_IE_VE_CHG	BIT(28)
40 #define	NGD_INT_DEV_ERR		BIT(29)
41 #define	NGD_INT_RX_MSG_RCVD	BIT(30)
42 #define	NGD_INT_TX_MSG_SENT	BIT(31)
43 #define	NGD_INT_STAT		0x14
44 #define	NGD_INT_CLR		0x18
45 #define DEF_NGD_INT_MASK (NGD_INT_TX_NACKED_2 | NGD_INT_MSG_BUF_CONTE | \
46 				NGD_INT_MSG_TX_INVAL | NGD_INT_IE_VE_CHG | \
47 				NGD_INT_DEV_ERR | NGD_INT_TX_MSG_SENT | \
48 				NGD_INT_RX_MSG_RCVD)
49 
50 /* Slimbus QMI service */
51 #define SLIMBUS_QMI_SVC_ID	0x0301
52 #define SLIMBUS_QMI_SVC_V1	1
53 #define SLIMBUS_QMI_INS_ID	0
54 #define SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01	0x0020
55 #define SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01	0x0020
56 #define SLIMBUS_QMI_POWER_REQ_V01		0x0021
57 #define SLIMBUS_QMI_POWER_RESP_V01		0x0021
58 #define SLIMBUS_QMI_CHECK_FRAMER_STATUS_REQ	0x0022
59 #define SLIMBUS_QMI_CHECK_FRAMER_STATUS_RESP	0x0022
60 #define SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN	14
61 #define SLIMBUS_QMI_POWER_RESP_MAX_MSG_LEN	7
62 #define SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN	14
63 #define SLIMBUS_QMI_SELECT_INSTANCE_RESP_MAX_MSG_LEN	7
64 #define SLIMBUS_QMI_CHECK_FRAMER_STAT_RESP_MAX_MSG_LEN	7
65 /* QMI response timeout of 500ms */
66 #define SLIMBUS_QMI_RESP_TOUT	1000
67 
68 /* User defined commands */
69 #define SLIM_USR_MC_GENERIC_ACK	0x25
70 #define SLIM_USR_MC_MASTER_CAPABILITY	0x0
71 #define SLIM_USR_MC_REPORT_SATELLITE	0x1
72 #define SLIM_USR_MC_ADDR_QUERY		0xD
73 #define SLIM_USR_MC_ADDR_REPLY		0xE
74 #define SLIM_USR_MC_DEFINE_CHAN		0x20
75 #define SLIM_USR_MC_DEF_ACT_CHAN	0x21
76 #define SLIM_USR_MC_CHAN_CTRL		0x23
77 #define SLIM_USR_MC_RECONFIG_NOW	0x24
78 #define SLIM_USR_MC_REQ_BW		0x28
79 #define SLIM_USR_MC_CONNECT_SRC		0x2C
80 #define SLIM_USR_MC_CONNECT_SINK	0x2D
81 #define SLIM_USR_MC_DISCONNECT_PORT	0x2E
82 #define SLIM_USR_MC_REPEAT_CHANGE_VALUE	0x0
83 
84 #define QCOM_SLIM_NGD_AUTOSUSPEND	MSEC_PER_SEC
85 #define SLIM_RX_MSGQ_TIMEOUT_VAL	0x10000
86 
87 #define SLIM_LA_MGR	0xFF
88 #define SLIM_ROOT_FREQ	24576000
89 #define LADDR_RETRY	5
90 
91 /* Per spec.max 40 bytes per received message */
92 #define SLIM_MSGQ_BUF_LEN	40
93 #define QCOM_SLIM_NGD_DESC_NUM	32
94 
95 #define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
96 		((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
97 
98 #define INIT_MX_RETRIES 10
99 #define DEF_RETRY_MS	10
100 #define SAT_MAGIC_LSB	0xD9
101 #define SAT_MAGIC_MSB	0xC5
102 #define SAT_MSG_VER	0x1
103 #define SAT_MSG_PROT	0x1
104 #define to_ngd(d)	container_of(d, struct qcom_slim_ngd, dev)
105 
106 struct ngd_reg_offset_data {
107 	u32 offset, size;
108 };
109 
110 static const struct ngd_reg_offset_data ngd_v1_5_offset_info = {
111 	.offset = 0x1000,
112 	.size = 0x1000,
113 };
114 
115 enum qcom_slim_ngd_state {
116 	QCOM_SLIM_NGD_CTRL_AWAKE,
117 	QCOM_SLIM_NGD_CTRL_IDLE,
118 	QCOM_SLIM_NGD_CTRL_ASLEEP,
119 	QCOM_SLIM_NGD_CTRL_DOWN,
120 };
121 
122 struct qcom_slim_ngd_qmi {
123 	struct qmi_handle qmi;
124 	struct sockaddr_qrtr svc_info;
125 	struct qmi_handle svc_event_hdl;
126 	struct qmi_response_type_v01 resp;
127 	struct qmi_handle *handle;
128 	struct completion qmi_comp;
129 };
130 
131 struct qcom_slim_ngd_ctrl;
132 struct qcom_slim_ngd;
133 
134 struct qcom_slim_ngd_dma_desc {
135 	struct dma_async_tx_descriptor *desc;
136 	struct qcom_slim_ngd_ctrl *ctrl;
137 	struct completion *comp;
138 	dma_cookie_t cookie;
139 	dma_addr_t phys;
140 	void *base;
141 };
142 
143 struct qcom_slim_ngd {
144 	struct platform_device *pdev;
145 	void __iomem *base;
146 	int id;
147 };
148 
149 struct qcom_slim_ngd_ctrl {
150 	struct slim_framer framer;
151 	struct slim_controller ctrl;
152 	struct qcom_slim_ngd_qmi qmi;
153 	struct qcom_slim_ngd *ngd;
154 	struct device *dev;
155 	void __iomem *base;
156 	struct dma_chan *dma_rx_channel;
157 	struct dma_chan	*dma_tx_channel;
158 	struct qcom_slim_ngd_dma_desc rx_desc[QCOM_SLIM_NGD_DESC_NUM];
159 	struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM];
160 	struct completion reconf;
161 	struct work_struct m_work;
162 	struct work_struct ngd_up_work;
163 	struct workqueue_struct *mwq;
164 	struct completion qmi_up;
165 	spinlock_t tx_buf_lock;
166 	struct mutex tx_lock;
167 	struct mutex ssr_lock;
168 	struct notifier_block nb;
169 	void *notifier;
170 	struct pdr_handle *pdr;
171 	enum qcom_slim_ngd_state state;
172 	dma_addr_t rx_phys_base;
173 	dma_addr_t tx_phys_base;
174 	void *rx_base;
175 	void *tx_base;
176 	int tx_tail;
177 	int tx_head;
178 	u32 ver;
179 };
180 
181 enum slimbus_mode_enum_type_v01 {
182 	/* To force a 32 bit signed enum. Do not change or use*/
183 	SLIMBUS_MODE_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
184 	SLIMBUS_MODE_SATELLITE_V01 = 1,
185 	SLIMBUS_MODE_MASTER_V01 = 2,
186 	SLIMBUS_MODE_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
187 };
188 
189 enum slimbus_pm_enum_type_v01 {
190 	/* To force a 32 bit signed enum. Do not change or use*/
191 	SLIMBUS_PM_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN,
192 	SLIMBUS_PM_INACTIVE_V01 = 1,
193 	SLIMBUS_PM_ACTIVE_V01 = 2,
194 	SLIMBUS_PM_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX,
195 };
196 
197 enum slimbus_resp_enum_type_v01 {
198 	SLIMBUS_RESP_ENUM_TYPE_MIN_VAL_V01 = INT_MIN,
199 	SLIMBUS_RESP_SYNCHRONOUS_V01 = 1,
200 	SLIMBUS_RESP_ENUM_TYPE_MAX_VAL_V01 = INT_MAX,
201 };
202 
203 struct slimbus_select_inst_req_msg_v01 {
204 	uint32_t instance;
205 	uint8_t mode_valid;
206 	enum slimbus_mode_enum_type_v01 mode;
207 };
208 
209 struct slimbus_select_inst_resp_msg_v01 {
210 	struct qmi_response_type_v01 resp;
211 };
212 
213 struct slimbus_power_req_msg_v01 {
214 	enum slimbus_pm_enum_type_v01 pm_req;
215 	uint8_t resp_type_valid;
216 	enum slimbus_resp_enum_type_v01 resp_type;
217 };
218 
219 struct slimbus_power_resp_msg_v01 {
220 	struct qmi_response_type_v01 resp;
221 };
222 
223 static struct qmi_elem_info slimbus_select_inst_req_msg_v01_ei[] = {
224 	{
225 		.data_type  = QMI_UNSIGNED_4_BYTE,
226 		.elem_len   = 1,
227 		.elem_size  = sizeof(uint32_t),
228 		.array_type = NO_ARRAY,
229 		.tlv_type   = 0x01,
230 		.offset     = offsetof(struct slimbus_select_inst_req_msg_v01,
231 				       instance),
232 		.ei_array   = NULL,
233 	},
234 	{
235 		.data_type  = QMI_OPT_FLAG,
236 		.elem_len   = 1,
237 		.elem_size  = sizeof(uint8_t),
238 		.array_type = NO_ARRAY,
239 		.tlv_type   = 0x10,
240 		.offset     = offsetof(struct slimbus_select_inst_req_msg_v01,
241 				       mode_valid),
242 		.ei_array   = NULL,
243 	},
244 	{
245 		.data_type  = QMI_UNSIGNED_4_BYTE,
246 		.elem_len   = 1,
247 		.elem_size  = sizeof(enum slimbus_mode_enum_type_v01),
248 		.array_type = NO_ARRAY,
249 		.tlv_type   = 0x10,
250 		.offset     = offsetof(struct slimbus_select_inst_req_msg_v01,
251 				       mode),
252 		.ei_array   = NULL,
253 	},
254 	{
255 		.data_type  = QMI_EOTI,
256 		.elem_len   = 0,
257 		.elem_size  = 0,
258 		.array_type = NO_ARRAY,
259 		.tlv_type   = 0x00,
260 		.offset     = 0,
261 		.ei_array   = NULL,
262 	},
263 };
264 
265 static struct qmi_elem_info slimbus_select_inst_resp_msg_v01_ei[] = {
266 	{
267 		.data_type  = QMI_STRUCT,
268 		.elem_len   = 1,
269 		.elem_size  = sizeof(struct qmi_response_type_v01),
270 		.array_type = NO_ARRAY,
271 		.tlv_type   = 0x02,
272 		.offset     = offsetof(struct slimbus_select_inst_resp_msg_v01,
273 				       resp),
274 		.ei_array   = qmi_response_type_v01_ei,
275 	},
276 	{
277 		.data_type  = QMI_EOTI,
278 		.elem_len   = 0,
279 		.elem_size  = 0,
280 		.array_type = NO_ARRAY,
281 		.tlv_type   = 0x00,
282 		.offset     = 0,
283 		.ei_array   = NULL,
284 	},
285 };
286 
287 static struct qmi_elem_info slimbus_power_req_msg_v01_ei[] = {
288 	{
289 		.data_type  = QMI_UNSIGNED_4_BYTE,
290 		.elem_len   = 1,
291 		.elem_size  = sizeof(enum slimbus_pm_enum_type_v01),
292 		.array_type = NO_ARRAY,
293 		.tlv_type   = 0x01,
294 		.offset     = offsetof(struct slimbus_power_req_msg_v01,
295 				       pm_req),
296 		.ei_array   = NULL,
297 	},
298 	{
299 		.data_type  = QMI_OPT_FLAG,
300 		.elem_len   = 1,
301 		.elem_size  = sizeof(uint8_t),
302 		.array_type = NO_ARRAY,
303 		.tlv_type   = 0x10,
304 		.offset     = offsetof(struct slimbus_power_req_msg_v01,
305 				       resp_type_valid),
306 	},
307 	{
308 		.data_type  = QMI_SIGNED_4_BYTE_ENUM,
309 		.elem_len   = 1,
310 		.elem_size  = sizeof(enum slimbus_resp_enum_type_v01),
311 		.array_type = NO_ARRAY,
312 		.tlv_type   = 0x10,
313 		.offset     = offsetof(struct slimbus_power_req_msg_v01,
314 				       resp_type),
315 	},
316 	{
317 		.data_type  = QMI_EOTI,
318 		.elem_len   = 0,
319 		.elem_size  = 0,
320 		.array_type = NO_ARRAY,
321 		.tlv_type   = 0x00,
322 		.offset     = 0,
323 		.ei_array   = NULL,
324 	},
325 };
326 
327 static struct qmi_elem_info slimbus_power_resp_msg_v01_ei[] = {
328 	{
329 		.data_type  = QMI_STRUCT,
330 		.elem_len   = 1,
331 		.elem_size  = sizeof(struct qmi_response_type_v01),
332 		.array_type = NO_ARRAY,
333 		.tlv_type   = 0x02,
334 		.offset     = offsetof(struct slimbus_power_resp_msg_v01, resp),
335 		.ei_array   = qmi_response_type_v01_ei,
336 	},
337 	{
338 		.data_type  = QMI_EOTI,
339 		.elem_len   = 0,
340 		.elem_size  = 0,
341 		.array_type = NO_ARRAY,
342 		.tlv_type   = 0x00,
343 		.offset     = 0,
344 		.ei_array   = NULL,
345 	},
346 };
347 
348 static int qcom_slim_qmi_send_select_inst_req(struct qcom_slim_ngd_ctrl *ctrl,
349 				struct slimbus_select_inst_req_msg_v01 *req)
350 {
351 	struct slimbus_select_inst_resp_msg_v01 resp = { { 0, 0 } };
352 	struct qmi_txn txn;
353 	int rc;
354 
355 	rc = qmi_txn_init(ctrl->qmi.handle, &txn,
356 				slimbus_select_inst_resp_msg_v01_ei, &resp);
357 	if (rc < 0) {
358 		dev_err(ctrl->dev, "QMI TXN init fail: %d\n", rc);
359 		return rc;
360 	}
361 
362 	rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
363 				SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01,
364 				SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN,
365 				slimbus_select_inst_req_msg_v01_ei, req);
366 	if (rc < 0) {
367 		dev_err(ctrl->dev, "QMI send req fail %d\n", rc);
368 		qmi_txn_cancel(&txn);
369 		return rc;
370 	}
371 
372 	rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
373 	if (rc < 0) {
374 		dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc);
375 		return rc;
376 	}
377 	/* Check the response */
378 	if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
379 		dev_err(ctrl->dev, "QMI request failed 0x%x\n",
380 			resp.resp.result);
381 		return -EREMOTEIO;
382 	}
383 
384 	return 0;
385 }
386 
387 static void qcom_slim_qmi_power_resp_cb(struct qmi_handle *handle,
388 					struct sockaddr_qrtr *sq,
389 					struct qmi_txn *txn, const void *data)
390 {
391 	struct slimbus_power_resp_msg_v01 *resp;
392 
393 	resp = (struct slimbus_power_resp_msg_v01 *)data;
394 	if (resp->resp.result != QMI_RESULT_SUCCESS_V01)
395 		pr_err("QMI power request failed 0x%x\n",
396 				resp->resp.result);
397 
398 	complete(&txn->completion);
399 }
400 
401 static int qcom_slim_qmi_send_power_request(struct qcom_slim_ngd_ctrl *ctrl,
402 					struct slimbus_power_req_msg_v01 *req)
403 {
404 	struct slimbus_power_resp_msg_v01 resp = { { 0, 0 } };
405 	struct qmi_txn txn;
406 	int rc;
407 
408 	rc = qmi_txn_init(ctrl->qmi.handle, &txn,
409 				slimbus_power_resp_msg_v01_ei, &resp);
410 
411 	rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn,
412 				SLIMBUS_QMI_POWER_REQ_V01,
413 				SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
414 				slimbus_power_req_msg_v01_ei, req);
415 	if (rc < 0) {
416 		dev_err(ctrl->dev, "QMI send req fail %d\n", rc);
417 		qmi_txn_cancel(&txn);
418 		return rc;
419 	}
420 
421 	rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT);
422 	if (rc < 0) {
423 		dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc);
424 		return rc;
425 	}
426 
427 	/* Check the response */
428 	if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
429 		dev_err(ctrl->dev, "QMI request failed 0x%x\n",
430 			resp.resp.result);
431 		return -EREMOTEIO;
432 	}
433 
434 	return 0;
435 }
436 
437 static struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = {
438 	{
439 		.type = QMI_RESPONSE,
440 		.msg_id = SLIMBUS_QMI_POWER_RESP_V01,
441 		.ei = slimbus_power_resp_msg_v01_ei,
442 		.decoded_size = sizeof(struct slimbus_power_resp_msg_v01),
443 		.fn = qcom_slim_qmi_power_resp_cb,
444 	},
445 	{}
446 };
447 
448 static int qcom_slim_qmi_init(struct qcom_slim_ngd_ctrl *ctrl,
449 			      bool apps_is_master)
450 {
451 	struct slimbus_select_inst_req_msg_v01 req;
452 	struct qmi_handle *handle;
453 	int rc;
454 
455 	handle = devm_kzalloc(ctrl->dev, sizeof(*handle), GFP_KERNEL);
456 	if (!handle)
457 		return -ENOMEM;
458 
459 	rc = qmi_handle_init(handle, SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN,
460 				NULL, qcom_slim_qmi_msg_handlers);
461 	if (rc < 0) {
462 		dev_err(ctrl->dev, "QMI client init failed: %d\n", rc);
463 		goto qmi_handle_init_failed;
464 	}
465 
466 	rc = kernel_connect(handle->sock,
467 				(struct sockaddr *)&ctrl->qmi.svc_info,
468 				sizeof(ctrl->qmi.svc_info), 0);
469 	if (rc < 0) {
470 		dev_err(ctrl->dev, "Remote Service connect failed: %d\n", rc);
471 		goto qmi_connect_to_service_failed;
472 	}
473 
474 	/* Instance is 0 based */
475 	req.instance = (ctrl->ngd->id >> 1);
476 	req.mode_valid = 1;
477 
478 	/* Mode indicates the role of the ADSP */
479 	if (apps_is_master)
480 		req.mode = SLIMBUS_MODE_SATELLITE_V01;
481 	else
482 		req.mode = SLIMBUS_MODE_MASTER_V01;
483 
484 	ctrl->qmi.handle = handle;
485 
486 	rc = qcom_slim_qmi_send_select_inst_req(ctrl, &req);
487 	if (rc) {
488 		dev_err(ctrl->dev, "failed to select h/w instance\n");
489 		goto qmi_select_instance_failed;
490 	}
491 
492 	return 0;
493 
494 qmi_select_instance_failed:
495 	ctrl->qmi.handle = NULL;
496 qmi_connect_to_service_failed:
497 	qmi_handle_release(handle);
498 qmi_handle_init_failed:
499 	devm_kfree(ctrl->dev, handle);
500 	return rc;
501 }
502 
503 static void qcom_slim_qmi_exit(struct qcom_slim_ngd_ctrl *ctrl)
504 {
505 	if (!ctrl->qmi.handle)
506 		return;
507 
508 	qmi_handle_release(ctrl->qmi.handle);
509 	devm_kfree(ctrl->dev, ctrl->qmi.handle);
510 	ctrl->qmi.handle = NULL;
511 }
512 
513 static int qcom_slim_qmi_power_request(struct qcom_slim_ngd_ctrl *ctrl,
514 				       bool active)
515 {
516 	struct slimbus_power_req_msg_v01 req;
517 
518 	if (active)
519 		req.pm_req = SLIMBUS_PM_ACTIVE_V01;
520 	else
521 		req.pm_req = SLIMBUS_PM_INACTIVE_V01;
522 
523 	req.resp_type_valid = 0;
524 
525 	return qcom_slim_qmi_send_power_request(ctrl, &req);
526 }
527 
528 static u32 *qcom_slim_ngd_tx_msg_get(struct qcom_slim_ngd_ctrl *ctrl, int len,
529 				     struct completion *comp)
530 {
531 	struct qcom_slim_ngd_dma_desc *desc;
532 	unsigned long flags;
533 
534 	spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
535 
536 	if ((ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM == ctrl->tx_head) {
537 		spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
538 		return NULL;
539 	}
540 	desc  = &ctrl->txdesc[ctrl->tx_tail];
541 	desc->base = ctrl->tx_base + ctrl->tx_tail * SLIM_MSGQ_BUF_LEN;
542 	desc->comp = comp;
543 	ctrl->tx_tail = (ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM;
544 
545 	spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
546 
547 	return desc->base;
548 }
549 
550 static void qcom_slim_ngd_tx_msg_dma_cb(void *args)
551 {
552 	struct qcom_slim_ngd_dma_desc *desc = args;
553 	struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
554 	unsigned long flags;
555 
556 	spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
557 
558 	if (desc->comp) {
559 		complete(desc->comp);
560 		desc->comp = NULL;
561 	}
562 
563 	ctrl->tx_head = (ctrl->tx_head + 1) % QCOM_SLIM_NGD_DESC_NUM;
564 	spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
565 }
566 
567 static int qcom_slim_ngd_tx_msg_post(struct qcom_slim_ngd_ctrl *ctrl,
568 				     void *buf, int len)
569 {
570 	struct qcom_slim_ngd_dma_desc *desc;
571 	unsigned long flags;
572 	int index, offset;
573 
574 	spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
575 	offset = buf - ctrl->tx_base;
576 	index = offset/SLIM_MSGQ_BUF_LEN;
577 
578 	desc = &ctrl->txdesc[index];
579 	desc->phys = ctrl->tx_phys_base + offset;
580 	desc->base = ctrl->tx_base + offset;
581 	desc->ctrl = ctrl;
582 	len = (len + 3) & 0xfc;
583 
584 	desc->desc = dmaengine_prep_slave_single(ctrl->dma_tx_channel,
585 						desc->phys, len,
586 						DMA_MEM_TO_DEV,
587 						DMA_PREP_INTERRUPT);
588 	if (!desc->desc) {
589 		dev_err(ctrl->dev, "unable to prepare channel\n");
590 		spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
591 		return -EINVAL;
592 	}
593 
594 	desc->desc->callback = qcom_slim_ngd_tx_msg_dma_cb;
595 	desc->desc->callback_param = desc;
596 	desc->desc->cookie = dmaengine_submit(desc->desc);
597 	dma_async_issue_pending(ctrl->dma_tx_channel);
598 	spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
599 
600 	return 0;
601 }
602 
603 static void qcom_slim_ngd_rx(struct qcom_slim_ngd_ctrl *ctrl, u8 *buf)
604 {
605 	u8 mc, mt, len;
606 
607 	mt = SLIM_HEADER_GET_MT(buf[0]);
608 	len = SLIM_HEADER_GET_RL(buf[0]);
609 	mc = SLIM_HEADER_GET_MC(buf[1]);
610 
611 	if (mc == SLIM_USR_MC_MASTER_CAPABILITY &&
612 		mt == SLIM_MSG_MT_SRC_REFERRED_USER)
613 		queue_work(ctrl->mwq, &ctrl->m_work);
614 
615 	if (mc == SLIM_MSG_MC_REPLY_INFORMATION ||
616 	    mc == SLIM_MSG_MC_REPLY_VALUE || (mc == SLIM_USR_MC_ADDR_REPLY &&
617 	    mt == SLIM_MSG_MT_SRC_REFERRED_USER) ||
618 		(mc == SLIM_USR_MC_GENERIC_ACK &&
619 		 mt == SLIM_MSG_MT_SRC_REFERRED_USER)) {
620 		slim_msg_response(&ctrl->ctrl, &buf[4], buf[3], len - 4);
621 		pm_runtime_mark_last_busy(ctrl->dev);
622 	}
623 }
624 
625 static void qcom_slim_ngd_rx_msgq_cb(void *args)
626 {
627 	struct qcom_slim_ngd_dma_desc *desc = args;
628 	struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl;
629 
630 	qcom_slim_ngd_rx(ctrl, (u8 *)desc->base);
631 	/* Add descriptor back to the queue */
632 	desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
633 					desc->phys, SLIM_MSGQ_BUF_LEN,
634 					DMA_DEV_TO_MEM,
635 					DMA_PREP_INTERRUPT);
636 	if (!desc->desc) {
637 		dev_err(ctrl->dev, "Unable to prepare rx channel\n");
638 		return;
639 	}
640 
641 	desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
642 	desc->desc->callback_param = desc;
643 	desc->desc->cookie = dmaengine_submit(desc->desc);
644 	dma_async_issue_pending(ctrl->dma_rx_channel);
645 }
646 
647 static int qcom_slim_ngd_post_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
648 {
649 	struct qcom_slim_ngd_dma_desc *desc;
650 	int i;
651 
652 	for (i = 0; i < QCOM_SLIM_NGD_DESC_NUM; i++) {
653 		desc = &ctrl->rx_desc[i];
654 		desc->phys = ctrl->rx_phys_base + i * SLIM_MSGQ_BUF_LEN;
655 		desc->ctrl = ctrl;
656 		desc->base = ctrl->rx_base + i * SLIM_MSGQ_BUF_LEN;
657 		desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel,
658 						desc->phys, SLIM_MSGQ_BUF_LEN,
659 						DMA_DEV_TO_MEM,
660 						DMA_PREP_INTERRUPT);
661 		if (!desc->desc) {
662 			dev_err(ctrl->dev, "Unable to prepare rx channel\n");
663 			return -EINVAL;
664 		}
665 
666 		desc->desc->callback = qcom_slim_ngd_rx_msgq_cb;
667 		desc->desc->callback_param = desc;
668 		desc->desc->cookie = dmaengine_submit(desc->desc);
669 	}
670 	dma_async_issue_pending(ctrl->dma_rx_channel);
671 
672 	return 0;
673 }
674 
675 static int qcom_slim_ngd_init_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
676 {
677 	struct device *dev = ctrl->dev;
678 	int ret, size;
679 
680 	ctrl->dma_rx_channel = dma_request_chan(dev, "rx");
681 	if (IS_ERR(ctrl->dma_rx_channel)) {
682 		dev_err(dev, "Failed to request RX dma channel");
683 		ret = PTR_ERR(ctrl->dma_rx_channel);
684 		ctrl->dma_rx_channel = NULL;
685 		return ret;
686 	}
687 
688 	size = QCOM_SLIM_NGD_DESC_NUM * SLIM_MSGQ_BUF_LEN;
689 	ctrl->rx_base = dma_alloc_coherent(dev, size, &ctrl->rx_phys_base,
690 					   GFP_KERNEL);
691 	if (!ctrl->rx_base) {
692 		dev_err(dev, "dma_alloc_coherent failed\n");
693 		ret = -ENOMEM;
694 		goto rel_rx;
695 	}
696 
697 	ret = qcom_slim_ngd_post_rx_msgq(ctrl);
698 	if (ret) {
699 		dev_err(dev, "post_rx_msgq() failed 0x%x\n", ret);
700 		goto rx_post_err;
701 	}
702 
703 	return 0;
704 
705 rx_post_err:
706 	dma_free_coherent(dev, size, ctrl->rx_base, ctrl->rx_phys_base);
707 rel_rx:
708 	dma_release_channel(ctrl->dma_rx_channel);
709 	return ret;
710 }
711 
712 static int qcom_slim_ngd_init_tx_msgq(struct qcom_slim_ngd_ctrl *ctrl)
713 {
714 	struct device *dev = ctrl->dev;
715 	unsigned long flags;
716 	int ret = 0;
717 	int size;
718 
719 	ctrl->dma_tx_channel = dma_request_chan(dev, "tx");
720 	if (IS_ERR(ctrl->dma_tx_channel)) {
721 		dev_err(dev, "Failed to request TX dma channel");
722 		ret = PTR_ERR(ctrl->dma_tx_channel);
723 		ctrl->dma_tx_channel = NULL;
724 		return ret;
725 	}
726 
727 	size = ((QCOM_SLIM_NGD_DESC_NUM + 1) * SLIM_MSGQ_BUF_LEN);
728 	ctrl->tx_base = dma_alloc_coherent(dev, size, &ctrl->tx_phys_base,
729 					   GFP_KERNEL);
730 	if (!ctrl->tx_base) {
731 		dev_err(dev, "dma_alloc_coherent failed\n");
732 		ret = -EINVAL;
733 		goto rel_tx;
734 	}
735 
736 	spin_lock_irqsave(&ctrl->tx_buf_lock, flags);
737 	ctrl->tx_tail = 0;
738 	ctrl->tx_head = 0;
739 	spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags);
740 
741 	return 0;
742 rel_tx:
743 	dma_release_channel(ctrl->dma_tx_channel);
744 	return ret;
745 }
746 
747 static int qcom_slim_ngd_init_dma(struct qcom_slim_ngd_ctrl *ctrl)
748 {
749 	int ret = 0;
750 
751 	ret = qcom_slim_ngd_init_rx_msgq(ctrl);
752 	if (ret) {
753 		dev_err(ctrl->dev, "rx dma init failed\n");
754 		return ret;
755 	}
756 
757 	ret = qcom_slim_ngd_init_tx_msgq(ctrl);
758 	if (ret)
759 		dev_err(ctrl->dev, "tx dma init failed\n");
760 
761 	return ret;
762 }
763 
764 static irqreturn_t qcom_slim_ngd_interrupt(int irq, void *d)
765 {
766 	struct qcom_slim_ngd_ctrl *ctrl = d;
767 	void __iomem *base = ctrl->ngd->base;
768 	u32 stat = readl(base + NGD_INT_STAT);
769 
770 	if ((stat & NGD_INT_MSG_BUF_CONTE) ||
771 		(stat & NGD_INT_MSG_TX_INVAL) || (stat & NGD_INT_DEV_ERR) ||
772 		(stat & NGD_INT_TX_NACKED_2)) {
773 		dev_err(ctrl->dev, "Error Interrupt received 0x%x\n", stat);
774 	}
775 
776 	writel(stat, base + NGD_INT_CLR);
777 
778 	return IRQ_HANDLED;
779 }
780 
781 static int qcom_slim_ngd_xfer_msg(struct slim_controller *sctrl,
782 				  struct slim_msg_txn *txn)
783 {
784 	struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
785 	DECLARE_COMPLETION_ONSTACK(tx_sent);
786 	DECLARE_COMPLETION_ONSTACK(done);
787 	int ret, timeout, i;
788 	u8 wbuf[SLIM_MSGQ_BUF_LEN];
789 	u8 rbuf[SLIM_MSGQ_BUF_LEN];
790 	u32 *pbuf;
791 	u8 *puc;
792 	u8 la = txn->la;
793 	bool usr_msg = false;
794 
795 	if (txn->mt == SLIM_MSG_MT_CORE &&
796 		(txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION &&
797 		 txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW))
798 		return 0;
799 
800 	if (txn->dt == SLIM_MSG_DEST_ENUMADDR)
801 		return -EPROTONOSUPPORT;
802 
803 	if (txn->msg->num_bytes > SLIM_MSGQ_BUF_LEN ||
804 			txn->rl > SLIM_MSGQ_BUF_LEN) {
805 		dev_err(ctrl->dev, "msg exceeds HW limit\n");
806 		return -EINVAL;
807 	}
808 
809 	pbuf = qcom_slim_ngd_tx_msg_get(ctrl, txn->rl, &tx_sent);
810 	if (!pbuf) {
811 		dev_err(ctrl->dev, "Message buffer unavailable\n");
812 		return -ENOMEM;
813 	}
814 
815 	if (txn->mt == SLIM_MSG_MT_CORE &&
816 		(txn->mc == SLIM_MSG_MC_CONNECT_SOURCE ||
817 		txn->mc == SLIM_MSG_MC_CONNECT_SINK ||
818 		txn->mc == SLIM_MSG_MC_DISCONNECT_PORT)) {
819 		txn->mt = SLIM_MSG_MT_DEST_REFERRED_USER;
820 		switch (txn->mc) {
821 		case SLIM_MSG_MC_CONNECT_SOURCE:
822 			txn->mc = SLIM_USR_MC_CONNECT_SRC;
823 			break;
824 		case SLIM_MSG_MC_CONNECT_SINK:
825 			txn->mc = SLIM_USR_MC_CONNECT_SINK;
826 			break;
827 		case SLIM_MSG_MC_DISCONNECT_PORT:
828 			txn->mc = SLIM_USR_MC_DISCONNECT_PORT;
829 			break;
830 		default:
831 			return -EINVAL;
832 		}
833 
834 		usr_msg = true;
835 		i = 0;
836 		wbuf[i++] = txn->la;
837 		la = SLIM_LA_MGR;
838 		wbuf[i++] = txn->msg->wbuf[0];
839 		if (txn->mc != SLIM_USR_MC_DISCONNECT_PORT)
840 			wbuf[i++] = txn->msg->wbuf[1];
841 
842 		txn->comp = &done;
843 		ret = slim_alloc_txn_tid(sctrl, txn);
844 		if (ret) {
845 			dev_err(ctrl->dev, "Unable to allocate TID\n");
846 			return ret;
847 		}
848 
849 		wbuf[i++] = txn->tid;
850 
851 		txn->msg->num_bytes = i;
852 		txn->msg->wbuf = wbuf;
853 		txn->msg->rbuf = rbuf;
854 		txn->rl = txn->msg->num_bytes + 4;
855 	}
856 
857 	/* HW expects length field to be excluded */
858 	txn->rl--;
859 	puc = (u8 *)pbuf;
860 	*pbuf = 0;
861 	if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
862 		*pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 0,
863 				la);
864 		puc += 3;
865 	} else {
866 		*pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 1,
867 				la);
868 		puc += 2;
869 	}
870 
871 	if (slim_tid_txn(txn->mt, txn->mc))
872 		*(puc++) = txn->tid;
873 
874 	if (slim_ec_txn(txn->mt, txn->mc)) {
875 		*(puc++) = (txn->ec & 0xFF);
876 		*(puc++) = (txn->ec >> 8) & 0xFF;
877 	}
878 
879 	if (txn->msg && txn->msg->wbuf)
880 		memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
881 
882 	mutex_lock(&ctrl->tx_lock);
883 	ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl);
884 	if (ret) {
885 		mutex_unlock(&ctrl->tx_lock);
886 		return ret;
887 	}
888 
889 	timeout = wait_for_completion_timeout(&tx_sent, HZ);
890 	if (!timeout) {
891 		dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
892 					txn->mt);
893 		mutex_unlock(&ctrl->tx_lock);
894 		return -ETIMEDOUT;
895 	}
896 
897 	if (usr_msg) {
898 		timeout = wait_for_completion_timeout(&done, HZ);
899 		if (!timeout) {
900 			dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x",
901 				txn->mc, txn->mt);
902 			mutex_unlock(&ctrl->tx_lock);
903 			return -ETIMEDOUT;
904 		}
905 	}
906 
907 	mutex_unlock(&ctrl->tx_lock);
908 	return 0;
909 }
910 
911 static int qcom_slim_ngd_xfer_msg_sync(struct slim_controller *ctrl,
912 				       struct slim_msg_txn *txn)
913 {
914 	DECLARE_COMPLETION_ONSTACK(done);
915 	int ret, timeout;
916 
917 	pm_runtime_get_sync(ctrl->dev);
918 
919 	txn->comp = &done;
920 
921 	ret = qcom_slim_ngd_xfer_msg(ctrl, txn);
922 	if (ret)
923 		return ret;
924 
925 	timeout = wait_for_completion_timeout(&done, HZ);
926 	if (!timeout) {
927 		dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
928 				txn->mt);
929 		return -ETIMEDOUT;
930 	}
931 	return 0;
932 }
933 
934 static int qcom_slim_ngd_enable_stream(struct slim_stream_runtime *rt)
935 {
936 	struct slim_device *sdev = rt->dev;
937 	struct slim_controller *ctrl = sdev->ctrl;
938 	struct slim_val_inf msg =  {0};
939 	u8 wbuf[SLIM_MSGQ_BUF_LEN];
940 	u8 rbuf[SLIM_MSGQ_BUF_LEN];
941 	struct slim_msg_txn txn = {0,};
942 	int i, ret;
943 
944 	txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
945 	txn.dt = SLIM_MSG_DEST_LOGICALADDR;
946 	txn.la = SLIM_LA_MGR;
947 	txn.ec = 0;
948 	txn.msg = &msg;
949 	txn.msg->num_bytes = 0;
950 	txn.msg->wbuf = wbuf;
951 	txn.msg->rbuf = rbuf;
952 
953 	for (i = 0; i < rt->num_ports; i++) {
954 		struct slim_port *port = &rt->ports[i];
955 
956 		if (txn.msg->num_bytes == 0) {
957 			int seg_interval = SLIM_SLOTS_PER_SUPERFRAME/rt->ratem;
958 			int exp;
959 
960 			wbuf[txn.msg->num_bytes++] = sdev->laddr;
961 			wbuf[txn.msg->num_bytes] = rt->bps >> 2 |
962 						   (port->ch.aux_fmt << 6);
963 
964 			/* Data channel segment interval not multiple of 3 */
965 			exp = seg_interval % 3;
966 			if (exp)
967 				wbuf[txn.msg->num_bytes] |= BIT(5);
968 
969 			txn.msg->num_bytes++;
970 			wbuf[txn.msg->num_bytes++] = exp << 4 | rt->prot;
971 
972 			if (rt->prot == SLIM_PROTO_ISO)
973 				wbuf[txn.msg->num_bytes++] =
974 						port->ch.prrate |
975 						SLIM_CHANNEL_CONTENT_FL;
976 			else
977 				wbuf[txn.msg->num_bytes++] =  port->ch.prrate;
978 
979 			ret = slim_alloc_txn_tid(ctrl, &txn);
980 			if (ret) {
981 				dev_err(&sdev->dev, "Fail to allocate TID\n");
982 				return -ENXIO;
983 			}
984 			wbuf[txn.msg->num_bytes++] = txn.tid;
985 		}
986 		wbuf[txn.msg->num_bytes++] = port->ch.id;
987 	}
988 
989 	txn.mc = SLIM_USR_MC_DEF_ACT_CHAN;
990 	txn.rl = txn.msg->num_bytes + 4;
991 	ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
992 	if (ret) {
993 		slim_free_txn_tid(ctrl, &txn);
994 		dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc,
995 				txn.mt);
996 		return ret;
997 	}
998 
999 	txn.mc = SLIM_USR_MC_RECONFIG_NOW;
1000 	txn.msg->num_bytes = 2;
1001 	wbuf[1] = sdev->laddr;
1002 	txn.rl = txn.msg->num_bytes + 4;
1003 
1004 	ret = slim_alloc_txn_tid(ctrl, &txn);
1005 	if (ret) {
1006 		dev_err(ctrl->dev, "Fail to allocate TID\n");
1007 		return ret;
1008 	}
1009 
1010 	wbuf[0] = txn.tid;
1011 	ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
1012 	if (ret) {
1013 		slim_free_txn_tid(ctrl, &txn);
1014 		dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc,
1015 				txn.mt);
1016 	}
1017 
1018 	return ret;
1019 }
1020 
1021 static int qcom_slim_ngd_get_laddr(struct slim_controller *ctrl,
1022 				   struct slim_eaddr *ea, u8 *laddr)
1023 {
1024 	struct slim_val_inf msg =  {0};
1025 	u8 failed_ea[6] = {0, 0, 0, 0, 0, 0};
1026 	struct slim_msg_txn txn;
1027 	u8 wbuf[10] = {0};
1028 	u8 rbuf[10] = {0};
1029 	int ret;
1030 
1031 	txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER;
1032 	txn.dt = SLIM_MSG_DEST_LOGICALADDR;
1033 	txn.la = SLIM_LA_MGR;
1034 	txn.ec = 0;
1035 
1036 	txn.mc = SLIM_USR_MC_ADDR_QUERY;
1037 	txn.rl = 11;
1038 	txn.msg = &msg;
1039 	txn.msg->num_bytes = 7;
1040 	txn.msg->wbuf = wbuf;
1041 	txn.msg->rbuf = rbuf;
1042 
1043 	ret = slim_alloc_txn_tid(ctrl, &txn);
1044 	if (ret < 0)
1045 		return ret;
1046 
1047 	wbuf[0] = (u8)txn.tid;
1048 	memcpy(&wbuf[1], ea, sizeof(*ea));
1049 
1050 	ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn);
1051 	if (ret) {
1052 		slim_free_txn_tid(ctrl, &txn);
1053 		return ret;
1054 	}
1055 
1056 	if (!memcmp(rbuf, failed_ea, 6))
1057 		return -ENXIO;
1058 
1059 	*laddr = rbuf[6];
1060 
1061 	return ret;
1062 }
1063 
1064 static int qcom_slim_ngd_exit_dma(struct qcom_slim_ngd_ctrl *ctrl)
1065 {
1066 	if (ctrl->dma_rx_channel) {
1067 		dmaengine_terminate_sync(ctrl->dma_rx_channel);
1068 		dma_release_channel(ctrl->dma_rx_channel);
1069 	}
1070 
1071 	if (ctrl->dma_tx_channel) {
1072 		dmaengine_terminate_sync(ctrl->dma_tx_channel);
1073 		dma_release_channel(ctrl->dma_tx_channel);
1074 	}
1075 
1076 	ctrl->dma_tx_channel = ctrl->dma_rx_channel = NULL;
1077 
1078 	return 0;
1079 }
1080 
1081 static void qcom_slim_ngd_setup(struct qcom_slim_ngd_ctrl *ctrl)
1082 {
1083 	u32 cfg = readl_relaxed(ctrl->ngd->base);
1084 
1085 	if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN)
1086 		qcom_slim_ngd_init_dma(ctrl);
1087 
1088 	/* By default enable message queues */
1089 	cfg |= NGD_CFG_RX_MSGQ_EN;
1090 	cfg |= NGD_CFG_TX_MSGQ_EN;
1091 
1092 	/* Enable NGD if it's not already enabled*/
1093 	if (!(cfg & NGD_CFG_ENABLE))
1094 		cfg |= NGD_CFG_ENABLE;
1095 
1096 	writel_relaxed(cfg, ctrl->ngd->base);
1097 }
1098 
1099 static int qcom_slim_ngd_power_up(struct qcom_slim_ngd_ctrl *ctrl)
1100 {
1101 	enum qcom_slim_ngd_state cur_state = ctrl->state;
1102 	struct qcom_slim_ngd *ngd = ctrl->ngd;
1103 	u32 laddr, rx_msgq;
1104 	int timeout, ret = 0;
1105 
1106 	if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
1107 		timeout = wait_for_completion_timeout(&ctrl->qmi.qmi_comp, HZ);
1108 		if (!timeout)
1109 			return -EREMOTEIO;
1110 	}
1111 
1112 	if (ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP ||
1113 		ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) {
1114 		ret = qcom_slim_qmi_power_request(ctrl, true);
1115 		if (ret) {
1116 			dev_err(ctrl->dev, "SLIM QMI power request failed:%d\n",
1117 					ret);
1118 			return ret;
1119 		}
1120 	}
1121 
1122 	ctrl->ver = readl_relaxed(ctrl->base);
1123 	/* Version info in 16 MSbits */
1124 	ctrl->ver >>= 16;
1125 
1126 	laddr = readl_relaxed(ngd->base + NGD_STATUS);
1127 	if (laddr & NGD_LADDR) {
1128 		/*
1129 		 * external MDM restart case where ADSP itself was active framer
1130 		 * For example, modem restarted when playback was active
1131 		 */
1132 		if (cur_state == QCOM_SLIM_NGD_CTRL_AWAKE) {
1133 			dev_info(ctrl->dev, "Subsys restart: ADSP active framer\n");
1134 			return 0;
1135 		}
1136 		return 0;
1137 	}
1138 
1139 	writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN);
1140 	rx_msgq = readl_relaxed(ngd->base + NGD_RX_MSGQ_CFG);
1141 
1142 	writel_relaxed(rx_msgq|SLIM_RX_MSGQ_TIMEOUT_VAL,
1143 				ngd->base + NGD_RX_MSGQ_CFG);
1144 	qcom_slim_ngd_setup(ctrl);
1145 
1146 	timeout = wait_for_completion_timeout(&ctrl->reconf, HZ);
1147 	if (!timeout) {
1148 		dev_err(ctrl->dev, "capability exchange timed-out\n");
1149 		return -ETIMEDOUT;
1150 	}
1151 
1152 	return 0;
1153 }
1154 
1155 static void qcom_slim_ngd_notify_slaves(struct qcom_slim_ngd_ctrl *ctrl)
1156 {
1157 	struct slim_device *sbdev;
1158 	struct device_node *node;
1159 
1160 	for_each_child_of_node(ctrl->ngd->pdev->dev.of_node, node) {
1161 		sbdev = of_slim_get_device(&ctrl->ctrl, node);
1162 		if (!sbdev)
1163 			continue;
1164 
1165 		if (slim_get_logical_addr(sbdev))
1166 			dev_err(ctrl->dev, "Failed to get logical address\n");
1167 	}
1168 }
1169 
1170 static void qcom_slim_ngd_master_worker(struct work_struct *work)
1171 {
1172 	struct qcom_slim_ngd_ctrl *ctrl;
1173 	struct slim_msg_txn txn;
1174 	struct slim_val_inf msg = {0};
1175 	int retries = 0;
1176 	u8 wbuf[8];
1177 	int ret = 0;
1178 
1179 	ctrl = container_of(work, struct qcom_slim_ngd_ctrl, m_work);
1180 	txn.dt = SLIM_MSG_DEST_LOGICALADDR;
1181 	txn.ec = 0;
1182 	txn.mc = SLIM_USR_MC_REPORT_SATELLITE;
1183 	txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER;
1184 	txn.la = SLIM_LA_MGR;
1185 	wbuf[0] = SAT_MAGIC_LSB;
1186 	wbuf[1] = SAT_MAGIC_MSB;
1187 	wbuf[2] = SAT_MSG_VER;
1188 	wbuf[3] = SAT_MSG_PROT;
1189 	txn.msg = &msg;
1190 	txn.msg->wbuf = wbuf;
1191 	txn.msg->num_bytes = 4;
1192 	txn.rl = 8;
1193 
1194 	dev_info(ctrl->dev, "SLIM SAT: Rcvd master capability\n");
1195 
1196 capability_retry:
1197 	ret = qcom_slim_ngd_xfer_msg(&ctrl->ctrl, &txn);
1198 	if (!ret) {
1199 		if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
1200 			complete(&ctrl->reconf);
1201 		else
1202 			dev_err(ctrl->dev, "unexpected state:%d\n",
1203 						ctrl->state);
1204 
1205 		if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN)
1206 			qcom_slim_ngd_notify_slaves(ctrl);
1207 
1208 	} else if (ret == -EIO) {
1209 		dev_err(ctrl->dev, "capability message NACKed, retrying\n");
1210 		if (retries < INIT_MX_RETRIES) {
1211 			msleep(DEF_RETRY_MS);
1212 			retries++;
1213 			goto capability_retry;
1214 		}
1215 	} else {
1216 		dev_err(ctrl->dev, "SLIM: capability TX failed:%d\n", ret);
1217 	}
1218 }
1219 
1220 static int qcom_slim_ngd_update_device_status(struct device *dev, void *null)
1221 {
1222 	slim_report_absent(to_slim_device(dev));
1223 
1224 	return 0;
1225 }
1226 
1227 static int qcom_slim_ngd_runtime_resume(struct device *dev)
1228 {
1229 	struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1230 	int ret = 0;
1231 
1232 	if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP)
1233 		ret = qcom_slim_ngd_power_up(ctrl);
1234 	if (ret) {
1235 		/* Did SSR cause this power up failure */
1236 		if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN)
1237 			ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
1238 		else
1239 			dev_err(ctrl->dev, "HW wakeup attempt during SSR\n");
1240 	} else {
1241 		ctrl->state = QCOM_SLIM_NGD_CTRL_AWAKE;
1242 	}
1243 
1244 	return 0;
1245 }
1246 
1247 static int qcom_slim_ngd_enable(struct qcom_slim_ngd_ctrl *ctrl, bool enable)
1248 {
1249 	if (enable) {
1250 		int ret = qcom_slim_qmi_init(ctrl, false);
1251 
1252 		if (ret) {
1253 			dev_err(ctrl->dev, "qmi init fail, ret:%d, state:%d\n",
1254 				ret, ctrl->state);
1255 			return ret;
1256 		}
1257 		/* controller state should be in sync with framework state */
1258 		complete(&ctrl->qmi.qmi_comp);
1259 		if (!pm_runtime_enabled(ctrl->dev) ||
1260 				!pm_runtime_suspended(ctrl->dev))
1261 			qcom_slim_ngd_runtime_resume(ctrl->dev);
1262 		else
1263 			pm_runtime_resume(ctrl->dev);
1264 		pm_runtime_mark_last_busy(ctrl->dev);
1265 		pm_runtime_put(ctrl->dev);
1266 
1267 		ret = slim_register_controller(&ctrl->ctrl);
1268 		if (ret) {
1269 			dev_err(ctrl->dev, "error adding slim controller\n");
1270 			return ret;
1271 		}
1272 
1273 		dev_info(ctrl->dev, "SLIM controller Registered\n");
1274 	} else {
1275 		qcom_slim_qmi_exit(ctrl);
1276 		slim_unregister_controller(&ctrl->ctrl);
1277 	}
1278 
1279 	return 0;
1280 }
1281 
1282 static int qcom_slim_ngd_qmi_new_server(struct qmi_handle *hdl,
1283 					struct qmi_service *service)
1284 {
1285 	struct qcom_slim_ngd_qmi *qmi =
1286 		container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
1287 	struct qcom_slim_ngd_ctrl *ctrl =
1288 		container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
1289 
1290 	qmi->svc_info.sq_family = AF_QIPCRTR;
1291 	qmi->svc_info.sq_node = service->node;
1292 	qmi->svc_info.sq_port = service->port;
1293 
1294 	complete(&ctrl->qmi_up);
1295 
1296 	return 0;
1297 }
1298 
1299 static void qcom_slim_ngd_qmi_del_server(struct qmi_handle *hdl,
1300 					 struct qmi_service *service)
1301 {
1302 	struct qcom_slim_ngd_qmi *qmi =
1303 		container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl);
1304 	struct qcom_slim_ngd_ctrl *ctrl =
1305 		container_of(qmi, struct qcom_slim_ngd_ctrl, qmi);
1306 
1307 	reinit_completion(&ctrl->qmi_up);
1308 	qmi->svc_info.sq_node = 0;
1309 	qmi->svc_info.sq_port = 0;
1310 }
1311 
1312 static struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = {
1313 	.new_server = qcom_slim_ngd_qmi_new_server,
1314 	.del_server = qcom_slim_ngd_qmi_del_server,
1315 };
1316 
1317 static int qcom_slim_ngd_qmi_svc_event_init(struct qcom_slim_ngd_ctrl *ctrl)
1318 {
1319 	struct qcom_slim_ngd_qmi *qmi = &ctrl->qmi;
1320 	int ret;
1321 
1322 	ret = qmi_handle_init(&qmi->svc_event_hdl, 0,
1323 				&qcom_slim_ngd_qmi_svc_event_ops, NULL);
1324 	if (ret < 0) {
1325 		dev_err(ctrl->dev, "qmi_handle_init failed: %d\n", ret);
1326 		return ret;
1327 	}
1328 
1329 	ret = qmi_add_lookup(&qmi->svc_event_hdl, SLIMBUS_QMI_SVC_ID,
1330 			SLIMBUS_QMI_SVC_V1, SLIMBUS_QMI_INS_ID);
1331 	if (ret < 0) {
1332 		dev_err(ctrl->dev, "qmi_add_lookup failed: %d\n", ret);
1333 		qmi_handle_release(&qmi->svc_event_hdl);
1334 	}
1335 	return ret;
1336 }
1337 
1338 static void qcom_slim_ngd_qmi_svc_event_deinit(struct qcom_slim_ngd_qmi *qmi)
1339 {
1340 	qmi_handle_release(&qmi->svc_event_hdl);
1341 }
1342 
1343 static struct platform_driver qcom_slim_ngd_driver;
1344 #define QCOM_SLIM_NGD_DRV_NAME	"qcom,slim-ngd"
1345 
1346 static const struct of_device_id qcom_slim_ngd_dt_match[] = {
1347 	{
1348 		.compatible = "qcom,slim-ngd-v1.5.0",
1349 		.data = &ngd_v1_5_offset_info,
1350 	},{
1351 		.compatible = "qcom,slim-ngd-v2.1.0",
1352 		.data = &ngd_v1_5_offset_info,
1353 	},
1354 	{}
1355 };
1356 
1357 MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match);
1358 
1359 static void qcom_slim_ngd_down(struct qcom_slim_ngd_ctrl *ctrl)
1360 {
1361 	mutex_lock(&ctrl->ssr_lock);
1362 	device_for_each_child(ctrl->ctrl.dev, NULL,
1363 			      qcom_slim_ngd_update_device_status);
1364 	qcom_slim_ngd_enable(ctrl, false);
1365 	mutex_unlock(&ctrl->ssr_lock);
1366 }
1367 
1368 static void qcom_slim_ngd_up_worker(struct work_struct *work)
1369 {
1370 	struct qcom_slim_ngd_ctrl *ctrl;
1371 
1372 	ctrl = container_of(work, struct qcom_slim_ngd_ctrl, ngd_up_work);
1373 
1374 	/* Make sure qmi service is up before continuing */
1375 	wait_for_completion_interruptible(&ctrl->qmi_up);
1376 
1377 	mutex_lock(&ctrl->ssr_lock);
1378 	qcom_slim_ngd_enable(ctrl, true);
1379 	mutex_unlock(&ctrl->ssr_lock);
1380 }
1381 
1382 static int qcom_slim_ngd_ssr_pdr_notify(struct qcom_slim_ngd_ctrl *ctrl,
1383 					unsigned long action)
1384 {
1385 	switch (action) {
1386 	case QCOM_SSR_BEFORE_SHUTDOWN:
1387 	case SERVREG_SERVICE_STATE_DOWN:
1388 		/* Make sure the last dma xfer is finished */
1389 		mutex_lock(&ctrl->tx_lock);
1390 		if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN) {
1391 			pm_runtime_get_noresume(ctrl->dev);
1392 			ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN;
1393 			qcom_slim_ngd_down(ctrl);
1394 			qcom_slim_ngd_exit_dma(ctrl);
1395 		}
1396 		mutex_unlock(&ctrl->tx_lock);
1397 		break;
1398 	case QCOM_SSR_AFTER_POWERUP:
1399 	case SERVREG_SERVICE_STATE_UP:
1400 		schedule_work(&ctrl->ngd_up_work);
1401 		break;
1402 	default:
1403 		break;
1404 	}
1405 
1406 	return NOTIFY_OK;
1407 }
1408 
1409 static int qcom_slim_ngd_ssr_notify(struct notifier_block *nb,
1410 				    unsigned long action,
1411 				    void *data)
1412 {
1413 	struct qcom_slim_ngd_ctrl *ctrl = container_of(nb,
1414 					       struct qcom_slim_ngd_ctrl, nb);
1415 
1416 	return qcom_slim_ngd_ssr_pdr_notify(ctrl, action);
1417 }
1418 
1419 static void slim_pd_status(int state, char *svc_path, void *priv)
1420 {
1421 	struct qcom_slim_ngd_ctrl *ctrl = (struct qcom_slim_ngd_ctrl *)priv;
1422 
1423 	qcom_slim_ngd_ssr_pdr_notify(ctrl, state);
1424 }
1425 static int of_qcom_slim_ngd_register(struct device *parent,
1426 				     struct qcom_slim_ngd_ctrl *ctrl)
1427 {
1428 	const struct ngd_reg_offset_data *data;
1429 	struct qcom_slim_ngd *ngd;
1430 	const struct of_device_id *match;
1431 	struct device_node *node;
1432 	u32 id;
1433 
1434 	match = of_match_node(qcom_slim_ngd_dt_match, parent->of_node);
1435 	data = match->data;
1436 	for_each_available_child_of_node(parent->of_node, node) {
1437 		if (of_property_read_u32(node, "reg", &id))
1438 			continue;
1439 
1440 		ngd = kzalloc(sizeof(*ngd), GFP_KERNEL);
1441 		if (!ngd) {
1442 			of_node_put(node);
1443 			return -ENOMEM;
1444 		}
1445 
1446 		ngd->pdev = platform_device_alloc(QCOM_SLIM_NGD_DRV_NAME, id);
1447 		if (!ngd->pdev) {
1448 			kfree(ngd);
1449 			of_node_put(node);
1450 			return -ENOMEM;
1451 		}
1452 		ngd->id = id;
1453 		ngd->pdev->dev.parent = parent;
1454 		ngd->pdev->driver_override = QCOM_SLIM_NGD_DRV_NAME;
1455 		ngd->pdev->dev.of_node = node;
1456 		ctrl->ngd = ngd;
1457 
1458 		platform_device_add(ngd->pdev);
1459 		ngd->base = ctrl->base + ngd->id * data->offset +
1460 					(ngd->id - 1) * data->size;
1461 
1462 		return 0;
1463 	}
1464 
1465 	return -ENODEV;
1466 }
1467 
1468 static int qcom_slim_ngd_probe(struct platform_device *pdev)
1469 {
1470 	struct device *dev = &pdev->dev;
1471 	struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev->parent);
1472 	int ret;
1473 
1474 	ctrl->ctrl.dev = dev;
1475 
1476 	platform_set_drvdata(pdev, ctrl);
1477 	pm_runtime_use_autosuspend(dev);
1478 	pm_runtime_set_autosuspend_delay(dev, QCOM_SLIM_NGD_AUTOSUSPEND);
1479 	pm_runtime_set_suspended(dev);
1480 	pm_runtime_enable(dev);
1481 	pm_runtime_get_noresume(dev);
1482 	ret = qcom_slim_ngd_qmi_svc_event_init(ctrl);
1483 	if (ret) {
1484 		dev_err(&pdev->dev, "QMI service registration failed:%d", ret);
1485 		return ret;
1486 	}
1487 
1488 	INIT_WORK(&ctrl->m_work, qcom_slim_ngd_master_worker);
1489 	INIT_WORK(&ctrl->ngd_up_work, qcom_slim_ngd_up_worker);
1490 	ctrl->mwq = create_singlethread_workqueue("ngd_master");
1491 	if (!ctrl->mwq) {
1492 		dev_err(&pdev->dev, "Failed to start master worker\n");
1493 		ret = -ENOMEM;
1494 		goto wq_err;
1495 	}
1496 
1497 	return 0;
1498 wq_err:
1499 	qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
1500 	if (ctrl->mwq)
1501 		destroy_workqueue(ctrl->mwq);
1502 
1503 	return ret;
1504 }
1505 
1506 static int qcom_slim_ngd_ctrl_probe(struct platform_device *pdev)
1507 {
1508 	struct device *dev = &pdev->dev;
1509 	struct qcom_slim_ngd_ctrl *ctrl;
1510 	struct resource *res;
1511 	int ret;
1512 	struct pdr_service *pds;
1513 
1514 	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1515 	if (!ctrl)
1516 		return -ENOMEM;
1517 
1518 	dev_set_drvdata(dev, ctrl);
1519 
1520 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1521 	ctrl->base = devm_ioremap_resource(dev, res);
1522 	if (IS_ERR(ctrl->base))
1523 		return PTR_ERR(ctrl->base);
1524 
1525 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1526 	if (!res) {
1527 		dev_err(&pdev->dev, "no slimbus IRQ resource\n");
1528 		return -ENODEV;
1529 	}
1530 
1531 	ret = devm_request_irq(dev, res->start, qcom_slim_ngd_interrupt,
1532 			       IRQF_TRIGGER_HIGH, "slim-ngd", ctrl);
1533 	if (ret) {
1534 		dev_err(&pdev->dev, "request IRQ failed\n");
1535 		return ret;
1536 	}
1537 
1538 	ctrl->nb.notifier_call = qcom_slim_ngd_ssr_notify;
1539 	ctrl->notifier = qcom_register_ssr_notifier("lpass", &ctrl->nb);
1540 	if (IS_ERR(ctrl->notifier))
1541 		return PTR_ERR(ctrl->notifier);
1542 
1543 	ctrl->dev = dev;
1544 	ctrl->framer.rootfreq = SLIM_ROOT_FREQ >> 3;
1545 	ctrl->framer.superfreq =
1546 		ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
1547 
1548 	ctrl->ctrl.a_framer = &ctrl->framer;
1549 	ctrl->ctrl.clkgear = SLIM_MAX_CLK_GEAR;
1550 	ctrl->ctrl.get_laddr = qcom_slim_ngd_get_laddr;
1551 	ctrl->ctrl.enable_stream = qcom_slim_ngd_enable_stream;
1552 	ctrl->ctrl.xfer_msg = qcom_slim_ngd_xfer_msg;
1553 	ctrl->ctrl.wakeup = NULL;
1554 	ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN;
1555 
1556 	mutex_init(&ctrl->tx_lock);
1557 	mutex_init(&ctrl->ssr_lock);
1558 	spin_lock_init(&ctrl->tx_buf_lock);
1559 	init_completion(&ctrl->reconf);
1560 	init_completion(&ctrl->qmi.qmi_comp);
1561 	init_completion(&ctrl->qmi_up);
1562 
1563 	ctrl->pdr = pdr_handle_alloc(slim_pd_status, ctrl);
1564 	if (IS_ERR(ctrl->pdr)) {
1565 		dev_err(dev, "Failed to init PDR handle\n");
1566 		return PTR_ERR(ctrl->pdr);
1567 	}
1568 
1569 	pds = pdr_add_lookup(ctrl->pdr, "avs/audio", "msm/adsp/audio_pd");
1570 	if (IS_ERR(pds) && PTR_ERR(pds) != -EALREADY) {
1571 		dev_err(dev, "pdr add lookup failed: %d\n", ret);
1572 		return PTR_ERR(pds);
1573 	}
1574 
1575 	platform_driver_register(&qcom_slim_ngd_driver);
1576 	return of_qcom_slim_ngd_register(dev, ctrl);
1577 }
1578 
1579 static int qcom_slim_ngd_ctrl_remove(struct platform_device *pdev)
1580 {
1581 	platform_driver_unregister(&qcom_slim_ngd_driver);
1582 
1583 	return 0;
1584 }
1585 
1586 static int qcom_slim_ngd_remove(struct platform_device *pdev)
1587 {
1588 	struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev);
1589 
1590 	pm_runtime_disable(&pdev->dev);
1591 	pdr_handle_release(ctrl->pdr);
1592 	qcom_unregister_ssr_notifier(ctrl->notifier, &ctrl->nb);
1593 	qcom_slim_ngd_enable(ctrl, false);
1594 	qcom_slim_ngd_exit_dma(ctrl);
1595 	qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi);
1596 	if (ctrl->mwq)
1597 		destroy_workqueue(ctrl->mwq);
1598 
1599 	kfree(ctrl->ngd);
1600 	ctrl->ngd = NULL;
1601 	return 0;
1602 }
1603 
1604 static int __maybe_unused qcom_slim_ngd_runtime_idle(struct device *dev)
1605 {
1606 	struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1607 
1608 	if (ctrl->state == QCOM_SLIM_NGD_CTRL_AWAKE)
1609 		ctrl->state = QCOM_SLIM_NGD_CTRL_IDLE;
1610 	pm_request_autosuspend(dev);
1611 	return -EAGAIN;
1612 }
1613 
1614 static int __maybe_unused qcom_slim_ngd_runtime_suspend(struct device *dev)
1615 {
1616 	struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev);
1617 	int ret = 0;
1618 
1619 	ret = qcom_slim_qmi_power_request(ctrl, false);
1620 	if (ret && ret != -EBUSY)
1621 		dev_info(ctrl->dev, "slim resource not idle:%d\n", ret);
1622 	if (!ret || ret == -ETIMEDOUT)
1623 		ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP;
1624 
1625 	return ret;
1626 }
1627 
1628 static const struct dev_pm_ops qcom_slim_ngd_dev_pm_ops = {
1629 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1630 				pm_runtime_force_resume)
1631 	SET_RUNTIME_PM_OPS(
1632 		qcom_slim_ngd_runtime_suspend,
1633 		qcom_slim_ngd_runtime_resume,
1634 		qcom_slim_ngd_runtime_idle
1635 	)
1636 };
1637 
1638 static struct platform_driver qcom_slim_ngd_ctrl_driver = {
1639 	.probe = qcom_slim_ngd_ctrl_probe,
1640 	.remove = qcom_slim_ngd_ctrl_remove,
1641 	.driver	= {
1642 		.name = "qcom,slim-ngd-ctrl",
1643 		.of_match_table = qcom_slim_ngd_dt_match,
1644 	},
1645 };
1646 
1647 static struct platform_driver qcom_slim_ngd_driver = {
1648 	.probe = qcom_slim_ngd_probe,
1649 	.remove = qcom_slim_ngd_remove,
1650 	.driver	= {
1651 		.name = QCOM_SLIM_NGD_DRV_NAME,
1652 		.pm = &qcom_slim_ngd_dev_pm_ops,
1653 	},
1654 };
1655 
1656 module_platform_driver(qcom_slim_ngd_ctrl_driver);
1657 MODULE_LICENSE("GPL v2");
1658 MODULE_DESCRIPTION("Qualcomm SLIMBus NGD controller");
1659