1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2018, Linaro Limited 4 5 #include <linux/irq.h> 6 #include <linux/kernel.h> 7 #include <linux/init.h> 8 #include <linux/slab.h> 9 #include <linux/interrupt.h> 10 #include <linux/platform_device.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/slimbus.h> 14 #include <linux/delay.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/mutex.h> 17 #include <linux/notifier.h> 18 #include <linux/remoteproc/qcom_rproc.h> 19 #include <linux/of.h> 20 #include <linux/io.h> 21 #include <linux/soc/qcom/qmi.h> 22 #include <net/sock.h> 23 #include "slimbus.h" 24 25 /* NGD (Non-ported Generic Device) registers */ 26 #define NGD_CFG 0x0 27 #define NGD_CFG_ENABLE BIT(0) 28 #define NGD_CFG_RX_MSGQ_EN BIT(1) 29 #define NGD_CFG_TX_MSGQ_EN BIT(2) 30 #define NGD_STATUS 0x4 31 #define NGD_LADDR BIT(1) 32 #define NGD_RX_MSGQ_CFG 0x8 33 #define NGD_INT_EN 0x10 34 #define NGD_INT_RECFG_DONE BIT(24) 35 #define NGD_INT_TX_NACKED_2 BIT(25) 36 #define NGD_INT_MSG_BUF_CONTE BIT(26) 37 #define NGD_INT_MSG_TX_INVAL BIT(27) 38 #define NGD_INT_IE_VE_CHG BIT(28) 39 #define NGD_INT_DEV_ERR BIT(29) 40 #define NGD_INT_RX_MSG_RCVD BIT(30) 41 #define NGD_INT_TX_MSG_SENT BIT(31) 42 #define NGD_INT_STAT 0x14 43 #define NGD_INT_CLR 0x18 44 #define DEF_NGD_INT_MASK (NGD_INT_TX_NACKED_2 | NGD_INT_MSG_BUF_CONTE | \ 45 NGD_INT_MSG_TX_INVAL | NGD_INT_IE_VE_CHG | \ 46 NGD_INT_DEV_ERR | NGD_INT_TX_MSG_SENT | \ 47 NGD_INT_RX_MSG_RCVD) 48 49 /* Slimbus QMI service */ 50 #define SLIMBUS_QMI_SVC_ID 0x0301 51 #define SLIMBUS_QMI_SVC_V1 1 52 #define SLIMBUS_QMI_INS_ID 0 53 #define SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01 0x0020 54 #define SLIMBUS_QMI_SELECT_INSTANCE_RESP_V01 0x0020 55 #define SLIMBUS_QMI_POWER_REQ_V01 0x0021 56 #define SLIMBUS_QMI_POWER_RESP_V01 0x0021 57 #define SLIMBUS_QMI_CHECK_FRAMER_STATUS_REQ 0x0022 58 #define SLIMBUS_QMI_CHECK_FRAMER_STATUS_RESP 0x0022 59 #define SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN 14 60 #define SLIMBUS_QMI_POWER_RESP_MAX_MSG_LEN 7 61 #define SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN 14 62 #define SLIMBUS_QMI_SELECT_INSTANCE_RESP_MAX_MSG_LEN 7 63 #define SLIMBUS_QMI_CHECK_FRAMER_STAT_RESP_MAX_MSG_LEN 7 64 /* QMI response timeout of 500ms */ 65 #define SLIMBUS_QMI_RESP_TOUT 1000 66 67 /* User defined commands */ 68 #define SLIM_USR_MC_GENERIC_ACK 0x25 69 #define SLIM_USR_MC_MASTER_CAPABILITY 0x0 70 #define SLIM_USR_MC_REPORT_SATELLITE 0x1 71 #define SLIM_USR_MC_ADDR_QUERY 0xD 72 #define SLIM_USR_MC_ADDR_REPLY 0xE 73 #define SLIM_USR_MC_DEFINE_CHAN 0x20 74 #define SLIM_USR_MC_DEF_ACT_CHAN 0x21 75 #define SLIM_USR_MC_CHAN_CTRL 0x23 76 #define SLIM_USR_MC_RECONFIG_NOW 0x24 77 #define SLIM_USR_MC_REQ_BW 0x28 78 #define SLIM_USR_MC_CONNECT_SRC 0x2C 79 #define SLIM_USR_MC_CONNECT_SINK 0x2D 80 #define SLIM_USR_MC_DISCONNECT_PORT 0x2E 81 #define SLIM_USR_MC_REPEAT_CHANGE_VALUE 0x0 82 83 #define QCOM_SLIM_NGD_AUTOSUSPEND MSEC_PER_SEC 84 #define SLIM_RX_MSGQ_TIMEOUT_VAL 0x10000 85 86 #define SLIM_LA_MGR 0xFF 87 #define SLIM_ROOT_FREQ 24576000 88 #define LADDR_RETRY 5 89 90 /* Per spec.max 40 bytes per received message */ 91 #define SLIM_MSGQ_BUF_LEN 40 92 #define QCOM_SLIM_NGD_DESC_NUM 32 93 94 #define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \ 95 ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16)) 96 97 #define INIT_MX_RETRIES 10 98 #define DEF_RETRY_MS 10 99 #define SAT_MAGIC_LSB 0xD9 100 #define SAT_MAGIC_MSB 0xC5 101 #define SAT_MSG_VER 0x1 102 #define SAT_MSG_PROT 0x1 103 #define to_ngd(d) container_of(d, struct qcom_slim_ngd, dev) 104 105 struct ngd_reg_offset_data { 106 u32 offset, size; 107 }; 108 109 static const struct ngd_reg_offset_data ngd_v1_5_offset_info = { 110 .offset = 0x1000, 111 .size = 0x1000, 112 }; 113 114 enum qcom_slim_ngd_state { 115 QCOM_SLIM_NGD_CTRL_AWAKE, 116 QCOM_SLIM_NGD_CTRL_IDLE, 117 QCOM_SLIM_NGD_CTRL_ASLEEP, 118 QCOM_SLIM_NGD_CTRL_DOWN, 119 }; 120 121 struct qcom_slim_ngd_qmi { 122 struct qmi_handle qmi; 123 struct sockaddr_qrtr svc_info; 124 struct qmi_handle svc_event_hdl; 125 struct qmi_response_type_v01 resp; 126 struct qmi_handle *handle; 127 struct completion qmi_comp; 128 }; 129 130 struct qcom_slim_ngd_ctrl; 131 struct qcom_slim_ngd; 132 133 struct qcom_slim_ngd_dma_desc { 134 struct dma_async_tx_descriptor *desc; 135 struct qcom_slim_ngd_ctrl *ctrl; 136 struct completion *comp; 137 dma_cookie_t cookie; 138 dma_addr_t phys; 139 void *base; 140 }; 141 142 struct qcom_slim_ngd { 143 struct platform_device *pdev; 144 void __iomem *base; 145 int id; 146 }; 147 148 struct qcom_slim_ngd_ctrl { 149 struct slim_framer framer; 150 struct slim_controller ctrl; 151 struct qcom_slim_ngd_qmi qmi; 152 struct qcom_slim_ngd *ngd; 153 struct device *dev; 154 void __iomem *base; 155 struct dma_chan *dma_rx_channel; 156 struct dma_chan *dma_tx_channel; 157 struct qcom_slim_ngd_dma_desc rx_desc[QCOM_SLIM_NGD_DESC_NUM]; 158 struct qcom_slim_ngd_dma_desc txdesc[QCOM_SLIM_NGD_DESC_NUM]; 159 struct completion reconf; 160 struct work_struct m_work; 161 struct work_struct ngd_up_work; 162 struct workqueue_struct *mwq; 163 struct completion qmi_up; 164 spinlock_t tx_buf_lock; 165 struct mutex tx_lock; 166 struct mutex ssr_lock; 167 struct notifier_block nb; 168 void *notifier; 169 enum qcom_slim_ngd_state state; 170 dma_addr_t rx_phys_base; 171 dma_addr_t tx_phys_base; 172 void *rx_base; 173 void *tx_base; 174 int tx_tail; 175 int tx_head; 176 u32 ver; 177 }; 178 179 enum slimbus_mode_enum_type_v01 { 180 /* To force a 32 bit signed enum. Do not change or use*/ 181 SLIMBUS_MODE_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN, 182 SLIMBUS_MODE_SATELLITE_V01 = 1, 183 SLIMBUS_MODE_MASTER_V01 = 2, 184 SLIMBUS_MODE_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX, 185 }; 186 187 enum slimbus_pm_enum_type_v01 { 188 /* To force a 32 bit signed enum. Do not change or use*/ 189 SLIMBUS_PM_ENUM_TYPE_MIN_ENUM_VAL_V01 = INT_MIN, 190 SLIMBUS_PM_INACTIVE_V01 = 1, 191 SLIMBUS_PM_ACTIVE_V01 = 2, 192 SLIMBUS_PM_ENUM_TYPE_MAX_ENUM_VAL_V01 = INT_MAX, 193 }; 194 195 enum slimbus_resp_enum_type_v01 { 196 SLIMBUS_RESP_ENUM_TYPE_MIN_VAL_V01 = INT_MIN, 197 SLIMBUS_RESP_SYNCHRONOUS_V01 = 1, 198 SLIMBUS_RESP_ENUM_TYPE_MAX_VAL_V01 = INT_MAX, 199 }; 200 201 struct slimbus_select_inst_req_msg_v01 { 202 uint32_t instance; 203 uint8_t mode_valid; 204 enum slimbus_mode_enum_type_v01 mode; 205 }; 206 207 struct slimbus_select_inst_resp_msg_v01 { 208 struct qmi_response_type_v01 resp; 209 }; 210 211 struct slimbus_power_req_msg_v01 { 212 enum slimbus_pm_enum_type_v01 pm_req; 213 uint8_t resp_type_valid; 214 enum slimbus_resp_enum_type_v01 resp_type; 215 }; 216 217 struct slimbus_power_resp_msg_v01 { 218 struct qmi_response_type_v01 resp; 219 }; 220 221 static struct qmi_elem_info slimbus_select_inst_req_msg_v01_ei[] = { 222 { 223 .data_type = QMI_UNSIGNED_4_BYTE, 224 .elem_len = 1, 225 .elem_size = sizeof(uint32_t), 226 .array_type = NO_ARRAY, 227 .tlv_type = 0x01, 228 .offset = offsetof(struct slimbus_select_inst_req_msg_v01, 229 instance), 230 .ei_array = NULL, 231 }, 232 { 233 .data_type = QMI_OPT_FLAG, 234 .elem_len = 1, 235 .elem_size = sizeof(uint8_t), 236 .array_type = NO_ARRAY, 237 .tlv_type = 0x10, 238 .offset = offsetof(struct slimbus_select_inst_req_msg_v01, 239 mode_valid), 240 .ei_array = NULL, 241 }, 242 { 243 .data_type = QMI_UNSIGNED_4_BYTE, 244 .elem_len = 1, 245 .elem_size = sizeof(enum slimbus_mode_enum_type_v01), 246 .array_type = NO_ARRAY, 247 .tlv_type = 0x10, 248 .offset = offsetof(struct slimbus_select_inst_req_msg_v01, 249 mode), 250 .ei_array = NULL, 251 }, 252 { 253 .data_type = QMI_EOTI, 254 .elem_len = 0, 255 .elem_size = 0, 256 .array_type = NO_ARRAY, 257 .tlv_type = 0x00, 258 .offset = 0, 259 .ei_array = NULL, 260 }, 261 }; 262 263 static struct qmi_elem_info slimbus_select_inst_resp_msg_v01_ei[] = { 264 { 265 .data_type = QMI_STRUCT, 266 .elem_len = 1, 267 .elem_size = sizeof(struct qmi_response_type_v01), 268 .array_type = NO_ARRAY, 269 .tlv_type = 0x02, 270 .offset = offsetof(struct slimbus_select_inst_resp_msg_v01, 271 resp), 272 .ei_array = qmi_response_type_v01_ei, 273 }, 274 { 275 .data_type = QMI_EOTI, 276 .elem_len = 0, 277 .elem_size = 0, 278 .array_type = NO_ARRAY, 279 .tlv_type = 0x00, 280 .offset = 0, 281 .ei_array = NULL, 282 }, 283 }; 284 285 static struct qmi_elem_info slimbus_power_req_msg_v01_ei[] = { 286 { 287 .data_type = QMI_UNSIGNED_4_BYTE, 288 .elem_len = 1, 289 .elem_size = sizeof(enum slimbus_pm_enum_type_v01), 290 .array_type = NO_ARRAY, 291 .tlv_type = 0x01, 292 .offset = offsetof(struct slimbus_power_req_msg_v01, 293 pm_req), 294 .ei_array = NULL, 295 }, 296 { 297 .data_type = QMI_OPT_FLAG, 298 .elem_len = 1, 299 .elem_size = sizeof(uint8_t), 300 .array_type = NO_ARRAY, 301 .tlv_type = 0x10, 302 .offset = offsetof(struct slimbus_power_req_msg_v01, 303 resp_type_valid), 304 }, 305 { 306 .data_type = QMI_SIGNED_4_BYTE_ENUM, 307 .elem_len = 1, 308 .elem_size = sizeof(enum slimbus_resp_enum_type_v01), 309 .array_type = NO_ARRAY, 310 .tlv_type = 0x10, 311 .offset = offsetof(struct slimbus_power_req_msg_v01, 312 resp_type), 313 }, 314 { 315 .data_type = QMI_EOTI, 316 .elem_len = 0, 317 .elem_size = 0, 318 .array_type = NO_ARRAY, 319 .tlv_type = 0x00, 320 .offset = 0, 321 .ei_array = NULL, 322 }, 323 }; 324 325 static struct qmi_elem_info slimbus_power_resp_msg_v01_ei[] = { 326 { 327 .data_type = QMI_STRUCT, 328 .elem_len = 1, 329 .elem_size = sizeof(struct qmi_response_type_v01), 330 .array_type = NO_ARRAY, 331 .tlv_type = 0x02, 332 .offset = offsetof(struct slimbus_power_resp_msg_v01, resp), 333 .ei_array = qmi_response_type_v01_ei, 334 }, 335 { 336 .data_type = QMI_EOTI, 337 .elem_len = 0, 338 .elem_size = 0, 339 .array_type = NO_ARRAY, 340 .tlv_type = 0x00, 341 .offset = 0, 342 .ei_array = NULL, 343 }, 344 }; 345 346 static int qcom_slim_qmi_send_select_inst_req(struct qcom_slim_ngd_ctrl *ctrl, 347 struct slimbus_select_inst_req_msg_v01 *req) 348 { 349 struct slimbus_select_inst_resp_msg_v01 resp = { { 0, 0 } }; 350 struct qmi_txn txn; 351 int rc; 352 353 rc = qmi_txn_init(ctrl->qmi.handle, &txn, 354 slimbus_select_inst_resp_msg_v01_ei, &resp); 355 if (rc < 0) { 356 dev_err(ctrl->dev, "QMI TXN init fail: %d\n", rc); 357 return rc; 358 } 359 360 rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn, 361 SLIMBUS_QMI_SELECT_INSTANCE_REQ_V01, 362 SLIMBUS_QMI_SELECT_INSTANCE_REQ_MAX_MSG_LEN, 363 slimbus_select_inst_req_msg_v01_ei, req); 364 if (rc < 0) { 365 dev_err(ctrl->dev, "QMI send req fail %d\n", rc); 366 qmi_txn_cancel(&txn); 367 return rc; 368 } 369 370 rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT); 371 if (rc < 0) { 372 dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc); 373 return rc; 374 } 375 /* Check the response */ 376 if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { 377 dev_err(ctrl->dev, "QMI request failed 0x%x\n", 378 resp.resp.result); 379 return -EREMOTEIO; 380 } 381 382 return 0; 383 } 384 385 static void qcom_slim_qmi_power_resp_cb(struct qmi_handle *handle, 386 struct sockaddr_qrtr *sq, 387 struct qmi_txn *txn, const void *data) 388 { 389 struct slimbus_power_resp_msg_v01 *resp; 390 391 resp = (struct slimbus_power_resp_msg_v01 *)data; 392 if (resp->resp.result != QMI_RESULT_SUCCESS_V01) 393 pr_err("QMI power request failed 0x%x\n", 394 resp->resp.result); 395 396 complete(&txn->completion); 397 } 398 399 static int qcom_slim_qmi_send_power_request(struct qcom_slim_ngd_ctrl *ctrl, 400 struct slimbus_power_req_msg_v01 *req) 401 { 402 struct slimbus_power_resp_msg_v01 resp = { { 0, 0 } }; 403 struct qmi_txn txn; 404 int rc; 405 406 rc = qmi_txn_init(ctrl->qmi.handle, &txn, 407 slimbus_power_resp_msg_v01_ei, &resp); 408 409 rc = qmi_send_request(ctrl->qmi.handle, NULL, &txn, 410 SLIMBUS_QMI_POWER_REQ_V01, 411 SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN, 412 slimbus_power_req_msg_v01_ei, req); 413 if (rc < 0) { 414 dev_err(ctrl->dev, "QMI send req fail %d\n", rc); 415 qmi_txn_cancel(&txn); 416 return rc; 417 } 418 419 rc = qmi_txn_wait(&txn, SLIMBUS_QMI_RESP_TOUT); 420 if (rc < 0) { 421 dev_err(ctrl->dev, "QMI TXN wait fail: %d\n", rc); 422 return rc; 423 } 424 425 /* Check the response */ 426 if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { 427 dev_err(ctrl->dev, "QMI request failed 0x%x\n", 428 resp.resp.result); 429 return -EREMOTEIO; 430 } 431 432 return 0; 433 } 434 435 static struct qmi_msg_handler qcom_slim_qmi_msg_handlers[] = { 436 { 437 .type = QMI_RESPONSE, 438 .msg_id = SLIMBUS_QMI_POWER_RESP_V01, 439 .ei = slimbus_power_resp_msg_v01_ei, 440 .decoded_size = sizeof(struct slimbus_power_resp_msg_v01), 441 .fn = qcom_slim_qmi_power_resp_cb, 442 }, 443 {} 444 }; 445 446 static int qcom_slim_qmi_init(struct qcom_slim_ngd_ctrl *ctrl, 447 bool apps_is_master) 448 { 449 struct slimbus_select_inst_req_msg_v01 req; 450 struct qmi_handle *handle; 451 int rc; 452 453 handle = devm_kzalloc(ctrl->dev, sizeof(*handle), GFP_KERNEL); 454 if (!handle) 455 return -ENOMEM; 456 457 rc = qmi_handle_init(handle, SLIMBUS_QMI_POWER_REQ_MAX_MSG_LEN, 458 NULL, qcom_slim_qmi_msg_handlers); 459 if (rc < 0) { 460 dev_err(ctrl->dev, "QMI client init failed: %d\n", rc); 461 goto qmi_handle_init_failed; 462 } 463 464 rc = kernel_connect(handle->sock, 465 (struct sockaddr *)&ctrl->qmi.svc_info, 466 sizeof(ctrl->qmi.svc_info), 0); 467 if (rc < 0) { 468 dev_err(ctrl->dev, "Remote Service connect failed: %d\n", rc); 469 goto qmi_connect_to_service_failed; 470 } 471 472 /* Instance is 0 based */ 473 req.instance = (ctrl->ngd->id >> 1); 474 req.mode_valid = 1; 475 476 /* Mode indicates the role of the ADSP */ 477 if (apps_is_master) 478 req.mode = SLIMBUS_MODE_SATELLITE_V01; 479 else 480 req.mode = SLIMBUS_MODE_MASTER_V01; 481 482 ctrl->qmi.handle = handle; 483 484 rc = qcom_slim_qmi_send_select_inst_req(ctrl, &req); 485 if (rc) { 486 dev_err(ctrl->dev, "failed to select h/w instance\n"); 487 goto qmi_select_instance_failed; 488 } 489 490 return 0; 491 492 qmi_select_instance_failed: 493 ctrl->qmi.handle = NULL; 494 qmi_connect_to_service_failed: 495 qmi_handle_release(handle); 496 qmi_handle_init_failed: 497 devm_kfree(ctrl->dev, handle); 498 return rc; 499 } 500 501 static void qcom_slim_qmi_exit(struct qcom_slim_ngd_ctrl *ctrl) 502 { 503 if (!ctrl->qmi.handle) 504 return; 505 506 qmi_handle_release(ctrl->qmi.handle); 507 devm_kfree(ctrl->dev, ctrl->qmi.handle); 508 ctrl->qmi.handle = NULL; 509 } 510 511 static int qcom_slim_qmi_power_request(struct qcom_slim_ngd_ctrl *ctrl, 512 bool active) 513 { 514 struct slimbus_power_req_msg_v01 req; 515 516 if (active) 517 req.pm_req = SLIMBUS_PM_ACTIVE_V01; 518 else 519 req.pm_req = SLIMBUS_PM_INACTIVE_V01; 520 521 req.resp_type_valid = 0; 522 523 return qcom_slim_qmi_send_power_request(ctrl, &req); 524 } 525 526 static u32 *qcom_slim_ngd_tx_msg_get(struct qcom_slim_ngd_ctrl *ctrl, int len, 527 struct completion *comp) 528 { 529 struct qcom_slim_ngd_dma_desc *desc; 530 unsigned long flags; 531 532 spin_lock_irqsave(&ctrl->tx_buf_lock, flags); 533 534 if ((ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM == ctrl->tx_head) { 535 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 536 return NULL; 537 } 538 desc = &ctrl->txdesc[ctrl->tx_tail]; 539 desc->base = ctrl->tx_base + ctrl->tx_tail * SLIM_MSGQ_BUF_LEN; 540 desc->comp = comp; 541 ctrl->tx_tail = (ctrl->tx_tail + 1) % QCOM_SLIM_NGD_DESC_NUM; 542 543 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 544 545 return desc->base; 546 } 547 548 static void qcom_slim_ngd_tx_msg_dma_cb(void *args) 549 { 550 struct qcom_slim_ngd_dma_desc *desc = args; 551 struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl; 552 unsigned long flags; 553 554 spin_lock_irqsave(&ctrl->tx_buf_lock, flags); 555 556 if (desc->comp) { 557 complete(desc->comp); 558 desc->comp = NULL; 559 } 560 561 ctrl->tx_head = (ctrl->tx_head + 1) % QCOM_SLIM_NGD_DESC_NUM; 562 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 563 } 564 565 static int qcom_slim_ngd_tx_msg_post(struct qcom_slim_ngd_ctrl *ctrl, 566 void *buf, int len) 567 { 568 struct qcom_slim_ngd_dma_desc *desc; 569 unsigned long flags; 570 int index, offset; 571 572 spin_lock_irqsave(&ctrl->tx_buf_lock, flags); 573 offset = buf - ctrl->tx_base; 574 index = offset/SLIM_MSGQ_BUF_LEN; 575 576 desc = &ctrl->txdesc[index]; 577 desc->phys = ctrl->tx_phys_base + offset; 578 desc->base = ctrl->tx_base + offset; 579 desc->ctrl = ctrl; 580 len = (len + 3) & 0xfc; 581 582 desc->desc = dmaengine_prep_slave_single(ctrl->dma_tx_channel, 583 desc->phys, len, 584 DMA_MEM_TO_DEV, 585 DMA_PREP_INTERRUPT); 586 if (!desc->desc) { 587 dev_err(ctrl->dev, "unable to prepare channel\n"); 588 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 589 return -EINVAL; 590 } 591 592 desc->desc->callback = qcom_slim_ngd_tx_msg_dma_cb; 593 desc->desc->callback_param = desc; 594 desc->desc->cookie = dmaengine_submit(desc->desc); 595 dma_async_issue_pending(ctrl->dma_tx_channel); 596 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 597 598 return 0; 599 } 600 601 static void qcom_slim_ngd_rx(struct qcom_slim_ngd_ctrl *ctrl, u8 *buf) 602 { 603 u8 mc, mt, len; 604 605 mt = SLIM_HEADER_GET_MT(buf[0]); 606 len = SLIM_HEADER_GET_RL(buf[0]); 607 mc = SLIM_HEADER_GET_MC(buf[1]); 608 609 if (mc == SLIM_USR_MC_MASTER_CAPABILITY && 610 mt == SLIM_MSG_MT_SRC_REFERRED_USER) 611 queue_work(ctrl->mwq, &ctrl->m_work); 612 613 if (mc == SLIM_MSG_MC_REPLY_INFORMATION || 614 mc == SLIM_MSG_MC_REPLY_VALUE || (mc == SLIM_USR_MC_ADDR_REPLY && 615 mt == SLIM_MSG_MT_SRC_REFERRED_USER) || 616 (mc == SLIM_USR_MC_GENERIC_ACK && 617 mt == SLIM_MSG_MT_SRC_REFERRED_USER)) { 618 slim_msg_response(&ctrl->ctrl, &buf[4], buf[3], len - 4); 619 pm_runtime_mark_last_busy(ctrl->dev); 620 } 621 } 622 623 static void qcom_slim_ngd_rx_msgq_cb(void *args) 624 { 625 struct qcom_slim_ngd_dma_desc *desc = args; 626 struct qcom_slim_ngd_ctrl *ctrl = desc->ctrl; 627 628 qcom_slim_ngd_rx(ctrl, (u8 *)desc->base); 629 /* Add descriptor back to the queue */ 630 desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel, 631 desc->phys, SLIM_MSGQ_BUF_LEN, 632 DMA_DEV_TO_MEM, 633 DMA_PREP_INTERRUPT); 634 if (!desc->desc) { 635 dev_err(ctrl->dev, "Unable to prepare rx channel\n"); 636 return; 637 } 638 639 desc->desc->callback = qcom_slim_ngd_rx_msgq_cb; 640 desc->desc->callback_param = desc; 641 desc->desc->cookie = dmaengine_submit(desc->desc); 642 dma_async_issue_pending(ctrl->dma_rx_channel); 643 } 644 645 static int qcom_slim_ngd_post_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl) 646 { 647 struct qcom_slim_ngd_dma_desc *desc; 648 int i; 649 650 for (i = 0; i < QCOM_SLIM_NGD_DESC_NUM; i++) { 651 desc = &ctrl->rx_desc[i]; 652 desc->phys = ctrl->rx_phys_base + i * SLIM_MSGQ_BUF_LEN; 653 desc->ctrl = ctrl; 654 desc->base = ctrl->rx_base + i * SLIM_MSGQ_BUF_LEN; 655 desc->desc = dmaengine_prep_slave_single(ctrl->dma_rx_channel, 656 desc->phys, SLIM_MSGQ_BUF_LEN, 657 DMA_DEV_TO_MEM, 658 DMA_PREP_INTERRUPT); 659 if (!desc->desc) { 660 dev_err(ctrl->dev, "Unable to prepare rx channel\n"); 661 return -EINVAL; 662 } 663 664 desc->desc->callback = qcom_slim_ngd_rx_msgq_cb; 665 desc->desc->callback_param = desc; 666 desc->desc->cookie = dmaengine_submit(desc->desc); 667 } 668 dma_async_issue_pending(ctrl->dma_rx_channel); 669 670 return 0; 671 } 672 673 static int qcom_slim_ngd_init_rx_msgq(struct qcom_slim_ngd_ctrl *ctrl) 674 { 675 struct device *dev = ctrl->dev; 676 int ret, size; 677 678 ctrl->dma_rx_channel = dma_request_chan(dev, "rx"); 679 if (IS_ERR(ctrl->dma_rx_channel)) { 680 dev_err(dev, "Failed to request RX dma channel"); 681 ret = PTR_ERR(ctrl->dma_rx_channel); 682 ctrl->dma_rx_channel = NULL; 683 return ret; 684 } 685 686 size = QCOM_SLIM_NGD_DESC_NUM * SLIM_MSGQ_BUF_LEN; 687 ctrl->rx_base = dma_alloc_coherent(dev, size, &ctrl->rx_phys_base, 688 GFP_KERNEL); 689 if (!ctrl->rx_base) { 690 dev_err(dev, "dma_alloc_coherent failed\n"); 691 ret = -ENOMEM; 692 goto rel_rx; 693 } 694 695 ret = qcom_slim_ngd_post_rx_msgq(ctrl); 696 if (ret) { 697 dev_err(dev, "post_rx_msgq() failed 0x%x\n", ret); 698 goto rx_post_err; 699 } 700 701 return 0; 702 703 rx_post_err: 704 dma_free_coherent(dev, size, ctrl->rx_base, ctrl->rx_phys_base); 705 rel_rx: 706 dma_release_channel(ctrl->dma_rx_channel); 707 return ret; 708 } 709 710 static int qcom_slim_ngd_init_tx_msgq(struct qcom_slim_ngd_ctrl *ctrl) 711 { 712 struct device *dev = ctrl->dev; 713 unsigned long flags; 714 int ret = 0; 715 int size; 716 717 ctrl->dma_tx_channel = dma_request_chan(dev, "tx"); 718 if (IS_ERR(ctrl->dma_tx_channel)) { 719 dev_err(dev, "Failed to request TX dma channel"); 720 ret = PTR_ERR(ctrl->dma_tx_channel); 721 ctrl->dma_tx_channel = NULL; 722 return ret; 723 } 724 725 size = ((QCOM_SLIM_NGD_DESC_NUM + 1) * SLIM_MSGQ_BUF_LEN); 726 ctrl->tx_base = dma_alloc_coherent(dev, size, &ctrl->tx_phys_base, 727 GFP_KERNEL); 728 if (!ctrl->tx_base) { 729 dev_err(dev, "dma_alloc_coherent failed\n"); 730 ret = -EINVAL; 731 goto rel_tx; 732 } 733 734 spin_lock_irqsave(&ctrl->tx_buf_lock, flags); 735 ctrl->tx_tail = 0; 736 ctrl->tx_head = 0; 737 spin_unlock_irqrestore(&ctrl->tx_buf_lock, flags); 738 739 return 0; 740 rel_tx: 741 dma_release_channel(ctrl->dma_tx_channel); 742 return ret; 743 } 744 745 static int qcom_slim_ngd_init_dma(struct qcom_slim_ngd_ctrl *ctrl) 746 { 747 int ret = 0; 748 749 ret = qcom_slim_ngd_init_rx_msgq(ctrl); 750 if (ret) { 751 dev_err(ctrl->dev, "rx dma init failed\n"); 752 return ret; 753 } 754 755 ret = qcom_slim_ngd_init_tx_msgq(ctrl); 756 if (ret) 757 dev_err(ctrl->dev, "tx dma init failed\n"); 758 759 return ret; 760 } 761 762 static irqreturn_t qcom_slim_ngd_interrupt(int irq, void *d) 763 { 764 struct qcom_slim_ngd_ctrl *ctrl = d; 765 void __iomem *base = ctrl->ngd->base; 766 u32 stat = readl(base + NGD_INT_STAT); 767 768 if ((stat & NGD_INT_MSG_BUF_CONTE) || 769 (stat & NGD_INT_MSG_TX_INVAL) || (stat & NGD_INT_DEV_ERR) || 770 (stat & NGD_INT_TX_NACKED_2)) { 771 dev_err(ctrl->dev, "Error Interrupt received 0x%x\n", stat); 772 } 773 774 writel(stat, base + NGD_INT_CLR); 775 776 return IRQ_HANDLED; 777 } 778 779 static int qcom_slim_ngd_xfer_msg(struct slim_controller *sctrl, 780 struct slim_msg_txn *txn) 781 { 782 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(sctrl->dev); 783 DECLARE_COMPLETION_ONSTACK(tx_sent); 784 DECLARE_COMPLETION_ONSTACK(done); 785 int ret, timeout, i; 786 u8 wbuf[SLIM_MSGQ_BUF_LEN]; 787 u8 rbuf[SLIM_MSGQ_BUF_LEN]; 788 u32 *pbuf; 789 u8 *puc; 790 u8 la = txn->la; 791 bool usr_msg = false; 792 793 if (txn->mt == SLIM_MSG_MT_CORE && 794 (txn->mc >= SLIM_MSG_MC_BEGIN_RECONFIGURATION && 795 txn->mc <= SLIM_MSG_MC_RECONFIGURE_NOW)) 796 return 0; 797 798 if (txn->dt == SLIM_MSG_DEST_ENUMADDR) 799 return -EPROTONOSUPPORT; 800 801 if (txn->msg->num_bytes > SLIM_MSGQ_BUF_LEN || 802 txn->rl > SLIM_MSGQ_BUF_LEN) { 803 dev_err(ctrl->dev, "msg exceeds HW limit\n"); 804 return -EINVAL; 805 } 806 807 pbuf = qcom_slim_ngd_tx_msg_get(ctrl, txn->rl, &tx_sent); 808 if (!pbuf) { 809 dev_err(ctrl->dev, "Message buffer unavailable\n"); 810 return -ENOMEM; 811 } 812 813 if (txn->mt == SLIM_MSG_MT_CORE && 814 (txn->mc == SLIM_MSG_MC_CONNECT_SOURCE || 815 txn->mc == SLIM_MSG_MC_CONNECT_SINK || 816 txn->mc == SLIM_MSG_MC_DISCONNECT_PORT)) { 817 txn->mt = SLIM_MSG_MT_DEST_REFERRED_USER; 818 switch (txn->mc) { 819 case SLIM_MSG_MC_CONNECT_SOURCE: 820 txn->mc = SLIM_USR_MC_CONNECT_SRC; 821 break; 822 case SLIM_MSG_MC_CONNECT_SINK: 823 txn->mc = SLIM_USR_MC_CONNECT_SINK; 824 break; 825 case SLIM_MSG_MC_DISCONNECT_PORT: 826 txn->mc = SLIM_USR_MC_DISCONNECT_PORT; 827 break; 828 default: 829 return -EINVAL; 830 } 831 832 usr_msg = true; 833 i = 0; 834 wbuf[i++] = txn->la; 835 la = SLIM_LA_MGR; 836 wbuf[i++] = txn->msg->wbuf[0]; 837 if (txn->mc != SLIM_USR_MC_DISCONNECT_PORT) 838 wbuf[i++] = txn->msg->wbuf[1]; 839 840 txn->comp = &done; 841 ret = slim_alloc_txn_tid(sctrl, txn); 842 if (ret) { 843 dev_err(ctrl->dev, "Unable to allocate TID\n"); 844 return ret; 845 } 846 847 wbuf[i++] = txn->tid; 848 849 txn->msg->num_bytes = i; 850 txn->msg->wbuf = wbuf; 851 txn->msg->rbuf = rbuf; 852 txn->rl = txn->msg->num_bytes + 4; 853 } 854 855 /* HW expects length field to be excluded */ 856 txn->rl--; 857 puc = (u8 *)pbuf; 858 *pbuf = 0; 859 if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) { 860 *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 0, 861 la); 862 puc += 3; 863 } else { 864 *pbuf = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, txn->mc, 1, 865 la); 866 puc += 2; 867 } 868 869 if (slim_tid_txn(txn->mt, txn->mc)) 870 *(puc++) = txn->tid; 871 872 if (slim_ec_txn(txn->mt, txn->mc)) { 873 *(puc++) = (txn->ec & 0xFF); 874 *(puc++) = (txn->ec >> 8) & 0xFF; 875 } 876 877 if (txn->msg && txn->msg->wbuf) 878 memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes); 879 880 mutex_lock(&ctrl->tx_lock); 881 ret = qcom_slim_ngd_tx_msg_post(ctrl, pbuf, txn->rl); 882 if (ret) { 883 mutex_unlock(&ctrl->tx_lock); 884 return ret; 885 } 886 887 timeout = wait_for_completion_timeout(&tx_sent, HZ); 888 if (!timeout) { 889 dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc, 890 txn->mt); 891 mutex_unlock(&ctrl->tx_lock); 892 return -ETIMEDOUT; 893 } 894 895 if (usr_msg) { 896 timeout = wait_for_completion_timeout(&done, HZ); 897 if (!timeout) { 898 dev_err(sctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", 899 txn->mc, txn->mt); 900 mutex_unlock(&ctrl->tx_lock); 901 return -ETIMEDOUT; 902 } 903 } 904 905 mutex_unlock(&ctrl->tx_lock); 906 return 0; 907 } 908 909 static int qcom_slim_ngd_xfer_msg_sync(struct slim_controller *ctrl, 910 struct slim_msg_txn *txn) 911 { 912 DECLARE_COMPLETION_ONSTACK(done); 913 int ret, timeout; 914 915 pm_runtime_get_sync(ctrl->dev); 916 917 txn->comp = &done; 918 919 ret = qcom_slim_ngd_xfer_msg(ctrl, txn); 920 if (ret) 921 return ret; 922 923 timeout = wait_for_completion_timeout(&done, HZ); 924 if (!timeout) { 925 dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc, 926 txn->mt); 927 return -ETIMEDOUT; 928 } 929 return 0; 930 } 931 932 static int qcom_slim_ngd_enable_stream(struct slim_stream_runtime *rt) 933 { 934 struct slim_device *sdev = rt->dev; 935 struct slim_controller *ctrl = sdev->ctrl; 936 struct slim_val_inf msg = {0}; 937 u8 wbuf[SLIM_MSGQ_BUF_LEN]; 938 u8 rbuf[SLIM_MSGQ_BUF_LEN]; 939 struct slim_msg_txn txn = {0,}; 940 int i, ret; 941 942 txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER; 943 txn.dt = SLIM_MSG_DEST_LOGICALADDR; 944 txn.la = SLIM_LA_MGR; 945 txn.ec = 0; 946 txn.msg = &msg; 947 txn.msg->num_bytes = 0; 948 txn.msg->wbuf = wbuf; 949 txn.msg->rbuf = rbuf; 950 951 for (i = 0; i < rt->num_ports; i++) { 952 struct slim_port *port = &rt->ports[i]; 953 954 if (txn.msg->num_bytes == 0) { 955 int seg_interval = SLIM_SLOTS_PER_SUPERFRAME/rt->ratem; 956 int exp; 957 958 wbuf[txn.msg->num_bytes++] = sdev->laddr; 959 wbuf[txn.msg->num_bytes] = rt->bps >> 2 | 960 (port->ch.aux_fmt << 6); 961 962 /* Data channel segment interval not multiple of 3 */ 963 exp = seg_interval % 3; 964 if (exp) 965 wbuf[txn.msg->num_bytes] |= BIT(5); 966 967 txn.msg->num_bytes++; 968 wbuf[txn.msg->num_bytes++] = exp << 4 | rt->prot; 969 970 if (rt->prot == SLIM_PROTO_ISO) 971 wbuf[txn.msg->num_bytes++] = 972 port->ch.prrate | 973 SLIM_CHANNEL_CONTENT_FL; 974 else 975 wbuf[txn.msg->num_bytes++] = port->ch.prrate; 976 977 ret = slim_alloc_txn_tid(ctrl, &txn); 978 if (ret) { 979 dev_err(&sdev->dev, "Fail to allocate TID\n"); 980 return -ENXIO; 981 } 982 wbuf[txn.msg->num_bytes++] = txn.tid; 983 } 984 wbuf[txn.msg->num_bytes++] = port->ch.id; 985 } 986 987 txn.mc = SLIM_USR_MC_DEF_ACT_CHAN; 988 txn.rl = txn.msg->num_bytes + 4; 989 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn); 990 if (ret) { 991 slim_free_txn_tid(ctrl, &txn); 992 dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc, 993 txn.mt); 994 return ret; 995 } 996 997 txn.mc = SLIM_USR_MC_RECONFIG_NOW; 998 txn.msg->num_bytes = 2; 999 wbuf[1] = sdev->laddr; 1000 txn.rl = txn.msg->num_bytes + 4; 1001 1002 ret = slim_alloc_txn_tid(ctrl, &txn); 1003 if (ret) { 1004 dev_err(ctrl->dev, "Fail to allocate TID\n"); 1005 return ret; 1006 } 1007 1008 wbuf[0] = txn.tid; 1009 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn); 1010 if (ret) { 1011 slim_free_txn_tid(ctrl, &txn); 1012 dev_err(&sdev->dev, "TX timed out:MC:0x%x,mt:0x%x", txn.mc, 1013 txn.mt); 1014 } 1015 1016 return ret; 1017 } 1018 1019 static int qcom_slim_ngd_get_laddr(struct slim_controller *ctrl, 1020 struct slim_eaddr *ea, u8 *laddr) 1021 { 1022 struct slim_val_inf msg = {0}; 1023 u8 failed_ea[6] = {0, 0, 0, 0, 0, 0}; 1024 struct slim_msg_txn txn; 1025 u8 wbuf[10] = {0}; 1026 u8 rbuf[10] = {0}; 1027 int ret; 1028 1029 txn.mt = SLIM_MSG_MT_DEST_REFERRED_USER; 1030 txn.dt = SLIM_MSG_DEST_LOGICALADDR; 1031 txn.la = SLIM_LA_MGR; 1032 txn.ec = 0; 1033 1034 txn.mc = SLIM_USR_MC_ADDR_QUERY; 1035 txn.rl = 11; 1036 txn.msg = &msg; 1037 txn.msg->num_bytes = 7; 1038 txn.msg->wbuf = wbuf; 1039 txn.msg->rbuf = rbuf; 1040 1041 ret = slim_alloc_txn_tid(ctrl, &txn); 1042 if (ret < 0) 1043 return ret; 1044 1045 wbuf[0] = (u8)txn.tid; 1046 memcpy(&wbuf[1], ea, sizeof(*ea)); 1047 1048 ret = qcom_slim_ngd_xfer_msg_sync(ctrl, &txn); 1049 if (ret) { 1050 slim_free_txn_tid(ctrl, &txn); 1051 return ret; 1052 } 1053 1054 if (!memcmp(rbuf, failed_ea, 6)) 1055 return -ENXIO; 1056 1057 *laddr = rbuf[6]; 1058 1059 return ret; 1060 } 1061 1062 static int qcom_slim_ngd_exit_dma(struct qcom_slim_ngd_ctrl *ctrl) 1063 { 1064 if (ctrl->dma_rx_channel) { 1065 dmaengine_terminate_sync(ctrl->dma_rx_channel); 1066 dma_release_channel(ctrl->dma_rx_channel); 1067 } 1068 1069 if (ctrl->dma_tx_channel) { 1070 dmaengine_terminate_sync(ctrl->dma_tx_channel); 1071 dma_release_channel(ctrl->dma_tx_channel); 1072 } 1073 1074 ctrl->dma_tx_channel = ctrl->dma_rx_channel = NULL; 1075 1076 return 0; 1077 } 1078 1079 static void qcom_slim_ngd_setup(struct qcom_slim_ngd_ctrl *ctrl) 1080 { 1081 u32 cfg = readl_relaxed(ctrl->ngd->base); 1082 1083 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) 1084 qcom_slim_ngd_init_dma(ctrl); 1085 1086 /* By default enable message queues */ 1087 cfg |= NGD_CFG_RX_MSGQ_EN; 1088 cfg |= NGD_CFG_TX_MSGQ_EN; 1089 1090 /* Enable NGD if it's not already enabled*/ 1091 if (!(cfg & NGD_CFG_ENABLE)) 1092 cfg |= NGD_CFG_ENABLE; 1093 1094 writel_relaxed(cfg, ctrl->ngd->base); 1095 } 1096 1097 static int qcom_slim_ngd_power_up(struct qcom_slim_ngd_ctrl *ctrl) 1098 { 1099 enum qcom_slim_ngd_state cur_state = ctrl->state; 1100 struct qcom_slim_ngd *ngd = ctrl->ngd; 1101 u32 laddr, rx_msgq; 1102 int timeout, ret = 0; 1103 1104 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) { 1105 timeout = wait_for_completion_timeout(&ctrl->qmi.qmi_comp, HZ); 1106 if (!timeout) 1107 return -EREMOTEIO; 1108 } 1109 1110 if (ctrl->state == QCOM_SLIM_NGD_CTRL_ASLEEP || 1111 ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) { 1112 ret = qcom_slim_qmi_power_request(ctrl, true); 1113 if (ret) { 1114 dev_err(ctrl->dev, "SLIM QMI power request failed:%d\n", 1115 ret); 1116 return ret; 1117 } 1118 } 1119 1120 ctrl->ver = readl_relaxed(ctrl->base); 1121 /* Version info in 16 MSbits */ 1122 ctrl->ver >>= 16; 1123 1124 laddr = readl_relaxed(ngd->base + NGD_STATUS); 1125 if (laddr & NGD_LADDR) { 1126 /* 1127 * external MDM restart case where ADSP itself was active framer 1128 * For example, modem restarted when playback was active 1129 */ 1130 if (cur_state == QCOM_SLIM_NGD_CTRL_AWAKE) { 1131 dev_info(ctrl->dev, "Subsys restart: ADSP active framer\n"); 1132 return 0; 1133 } 1134 return 0; 1135 } 1136 1137 writel_relaxed(DEF_NGD_INT_MASK, ngd->base + NGD_INT_EN); 1138 rx_msgq = readl_relaxed(ngd->base + NGD_RX_MSGQ_CFG); 1139 1140 writel_relaxed(rx_msgq|SLIM_RX_MSGQ_TIMEOUT_VAL, 1141 ngd->base + NGD_RX_MSGQ_CFG); 1142 qcom_slim_ngd_setup(ctrl); 1143 1144 timeout = wait_for_completion_timeout(&ctrl->reconf, HZ); 1145 if (!timeout) { 1146 dev_err(ctrl->dev, "capability exchange timed-out\n"); 1147 return -ETIMEDOUT; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static void qcom_slim_ngd_notify_slaves(struct qcom_slim_ngd_ctrl *ctrl) 1154 { 1155 struct slim_device *sbdev; 1156 struct device_node *node; 1157 1158 for_each_child_of_node(ctrl->ngd->pdev->dev.of_node, node) { 1159 sbdev = of_slim_get_device(&ctrl->ctrl, node); 1160 if (!sbdev) 1161 continue; 1162 1163 if (slim_get_logical_addr(sbdev)) 1164 dev_err(ctrl->dev, "Failed to get logical address\n"); 1165 } 1166 } 1167 1168 static void qcom_slim_ngd_master_worker(struct work_struct *work) 1169 { 1170 struct qcom_slim_ngd_ctrl *ctrl; 1171 struct slim_msg_txn txn; 1172 struct slim_val_inf msg = {0}; 1173 int retries = 0; 1174 u8 wbuf[8]; 1175 int ret = 0; 1176 1177 ctrl = container_of(work, struct qcom_slim_ngd_ctrl, m_work); 1178 txn.dt = SLIM_MSG_DEST_LOGICALADDR; 1179 txn.ec = 0; 1180 txn.mc = SLIM_USR_MC_REPORT_SATELLITE; 1181 txn.mt = SLIM_MSG_MT_SRC_REFERRED_USER; 1182 txn.la = SLIM_LA_MGR; 1183 wbuf[0] = SAT_MAGIC_LSB; 1184 wbuf[1] = SAT_MAGIC_MSB; 1185 wbuf[2] = SAT_MSG_VER; 1186 wbuf[3] = SAT_MSG_PROT; 1187 txn.msg = &msg; 1188 txn.msg->wbuf = wbuf; 1189 txn.msg->num_bytes = 4; 1190 txn.rl = 8; 1191 1192 dev_info(ctrl->dev, "SLIM SAT: Rcvd master capability\n"); 1193 1194 capability_retry: 1195 ret = qcom_slim_ngd_xfer_msg(&ctrl->ctrl, &txn); 1196 if (!ret) { 1197 if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP) 1198 complete(&ctrl->reconf); 1199 else 1200 dev_err(ctrl->dev, "unexpected state:%d\n", 1201 ctrl->state); 1202 1203 if (ctrl->state == QCOM_SLIM_NGD_CTRL_DOWN) 1204 qcom_slim_ngd_notify_slaves(ctrl); 1205 1206 } else if (ret == -EIO) { 1207 dev_err(ctrl->dev, "capability message NACKed, retrying\n"); 1208 if (retries < INIT_MX_RETRIES) { 1209 msleep(DEF_RETRY_MS); 1210 retries++; 1211 goto capability_retry; 1212 } 1213 } else { 1214 dev_err(ctrl->dev, "SLIM: capability TX failed:%d\n", ret); 1215 } 1216 } 1217 1218 static int qcom_slim_ngd_update_device_status(struct device *dev, void *null) 1219 { 1220 slim_report_absent(to_slim_device(dev)); 1221 1222 return 0; 1223 } 1224 1225 static int qcom_slim_ngd_runtime_resume(struct device *dev) 1226 { 1227 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev); 1228 int ret = 0; 1229 1230 if (ctrl->state >= QCOM_SLIM_NGD_CTRL_ASLEEP) 1231 ret = qcom_slim_ngd_power_up(ctrl); 1232 if (ret) { 1233 /* Did SSR cause this power up failure */ 1234 if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN) 1235 ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP; 1236 else 1237 dev_err(ctrl->dev, "HW wakeup attempt during SSR\n"); 1238 } else { 1239 ctrl->state = QCOM_SLIM_NGD_CTRL_AWAKE; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static int qcom_slim_ngd_enable(struct qcom_slim_ngd_ctrl *ctrl, bool enable) 1246 { 1247 if (enable) { 1248 int ret = qcom_slim_qmi_init(ctrl, false); 1249 1250 if (ret) { 1251 dev_err(ctrl->dev, "qmi init fail, ret:%d, state:%d\n", 1252 ret, ctrl->state); 1253 return ret; 1254 } 1255 /* controller state should be in sync with framework state */ 1256 complete(&ctrl->qmi.qmi_comp); 1257 if (!pm_runtime_enabled(ctrl->dev) || 1258 !pm_runtime_suspended(ctrl->dev)) 1259 qcom_slim_ngd_runtime_resume(ctrl->dev); 1260 else 1261 pm_runtime_resume(ctrl->dev); 1262 pm_runtime_mark_last_busy(ctrl->dev); 1263 pm_runtime_put(ctrl->dev); 1264 1265 ret = slim_register_controller(&ctrl->ctrl); 1266 if (ret) { 1267 dev_err(ctrl->dev, "error adding slim controller\n"); 1268 return ret; 1269 } 1270 1271 dev_info(ctrl->dev, "SLIM controller Registered\n"); 1272 } else { 1273 qcom_slim_qmi_exit(ctrl); 1274 slim_unregister_controller(&ctrl->ctrl); 1275 } 1276 1277 return 0; 1278 } 1279 1280 static int qcom_slim_ngd_qmi_new_server(struct qmi_handle *hdl, 1281 struct qmi_service *service) 1282 { 1283 struct qcom_slim_ngd_qmi *qmi = 1284 container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl); 1285 struct qcom_slim_ngd_ctrl *ctrl = 1286 container_of(qmi, struct qcom_slim_ngd_ctrl, qmi); 1287 1288 qmi->svc_info.sq_family = AF_QIPCRTR; 1289 qmi->svc_info.sq_node = service->node; 1290 qmi->svc_info.sq_port = service->port; 1291 1292 complete(&ctrl->qmi_up); 1293 1294 return 0; 1295 } 1296 1297 static void qcom_slim_ngd_qmi_del_server(struct qmi_handle *hdl, 1298 struct qmi_service *service) 1299 { 1300 struct qcom_slim_ngd_qmi *qmi = 1301 container_of(hdl, struct qcom_slim_ngd_qmi, svc_event_hdl); 1302 struct qcom_slim_ngd_ctrl *ctrl = 1303 container_of(qmi, struct qcom_slim_ngd_ctrl, qmi); 1304 1305 reinit_completion(&ctrl->qmi_up); 1306 qmi->svc_info.sq_node = 0; 1307 qmi->svc_info.sq_port = 0; 1308 } 1309 1310 static struct qmi_ops qcom_slim_ngd_qmi_svc_event_ops = { 1311 .new_server = qcom_slim_ngd_qmi_new_server, 1312 .del_server = qcom_slim_ngd_qmi_del_server, 1313 }; 1314 1315 static int qcom_slim_ngd_qmi_svc_event_init(struct qcom_slim_ngd_ctrl *ctrl) 1316 { 1317 struct qcom_slim_ngd_qmi *qmi = &ctrl->qmi; 1318 int ret; 1319 1320 ret = qmi_handle_init(&qmi->svc_event_hdl, 0, 1321 &qcom_slim_ngd_qmi_svc_event_ops, NULL); 1322 if (ret < 0) { 1323 dev_err(ctrl->dev, "qmi_handle_init failed: %d\n", ret); 1324 return ret; 1325 } 1326 1327 ret = qmi_add_lookup(&qmi->svc_event_hdl, SLIMBUS_QMI_SVC_ID, 1328 SLIMBUS_QMI_SVC_V1, SLIMBUS_QMI_INS_ID); 1329 if (ret < 0) { 1330 dev_err(ctrl->dev, "qmi_add_lookup failed: %d\n", ret); 1331 qmi_handle_release(&qmi->svc_event_hdl); 1332 } 1333 return ret; 1334 } 1335 1336 static void qcom_slim_ngd_qmi_svc_event_deinit(struct qcom_slim_ngd_qmi *qmi) 1337 { 1338 qmi_handle_release(&qmi->svc_event_hdl); 1339 } 1340 1341 static struct platform_driver qcom_slim_ngd_driver; 1342 #define QCOM_SLIM_NGD_DRV_NAME "qcom,slim-ngd" 1343 1344 static const struct of_device_id qcom_slim_ngd_dt_match[] = { 1345 { 1346 .compatible = "qcom,slim-ngd-v1.5.0", 1347 .data = &ngd_v1_5_offset_info, 1348 },{ 1349 .compatible = "qcom,slim-ngd-v2.1.0", 1350 .data = &ngd_v1_5_offset_info, 1351 }, 1352 {} 1353 }; 1354 1355 MODULE_DEVICE_TABLE(of, qcom_slim_ngd_dt_match); 1356 1357 static void qcom_slim_ngd_down(struct qcom_slim_ngd_ctrl *ctrl) 1358 { 1359 mutex_lock(&ctrl->ssr_lock); 1360 device_for_each_child(ctrl->ctrl.dev, NULL, 1361 qcom_slim_ngd_update_device_status); 1362 qcom_slim_ngd_enable(ctrl, false); 1363 mutex_unlock(&ctrl->ssr_lock); 1364 } 1365 1366 static void qcom_slim_ngd_up_worker(struct work_struct *work) 1367 { 1368 struct qcom_slim_ngd_ctrl *ctrl; 1369 1370 ctrl = container_of(work, struct qcom_slim_ngd_ctrl, ngd_up_work); 1371 1372 /* Make sure qmi service is up before continuing */ 1373 wait_for_completion_interruptible(&ctrl->qmi_up); 1374 1375 mutex_lock(&ctrl->ssr_lock); 1376 qcom_slim_ngd_enable(ctrl, true); 1377 mutex_unlock(&ctrl->ssr_lock); 1378 } 1379 1380 static int qcom_slim_ngd_ssr_pdr_notify(struct qcom_slim_ngd_ctrl *ctrl, 1381 unsigned long action) 1382 { 1383 switch (action) { 1384 case QCOM_SSR_BEFORE_SHUTDOWN: 1385 /* Make sure the last dma xfer is finished */ 1386 mutex_lock(&ctrl->tx_lock); 1387 if (ctrl->state != QCOM_SLIM_NGD_CTRL_DOWN) { 1388 pm_runtime_get_noresume(ctrl->dev); 1389 ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN; 1390 qcom_slim_ngd_down(ctrl); 1391 qcom_slim_ngd_exit_dma(ctrl); 1392 } 1393 mutex_unlock(&ctrl->tx_lock); 1394 break; 1395 case QCOM_SSR_AFTER_POWERUP: 1396 schedule_work(&ctrl->ngd_up_work); 1397 break; 1398 default: 1399 break; 1400 } 1401 1402 return NOTIFY_OK; 1403 } 1404 1405 static int qcom_slim_ngd_ssr_notify(struct notifier_block *nb, 1406 unsigned long action, 1407 void *data) 1408 { 1409 struct qcom_slim_ngd_ctrl *ctrl = container_of(nb, 1410 struct qcom_slim_ngd_ctrl, nb); 1411 1412 return qcom_slim_ngd_ssr_pdr_notify(ctrl, action); 1413 } 1414 1415 static int of_qcom_slim_ngd_register(struct device *parent, 1416 struct qcom_slim_ngd_ctrl *ctrl) 1417 { 1418 const struct ngd_reg_offset_data *data; 1419 struct qcom_slim_ngd *ngd; 1420 const struct of_device_id *match; 1421 struct device_node *node; 1422 u32 id; 1423 1424 match = of_match_node(qcom_slim_ngd_dt_match, parent->of_node); 1425 data = match->data; 1426 for_each_available_child_of_node(parent->of_node, node) { 1427 if (of_property_read_u32(node, "reg", &id)) 1428 continue; 1429 1430 ngd = kzalloc(sizeof(*ngd), GFP_KERNEL); 1431 if (!ngd) { 1432 of_node_put(node); 1433 return -ENOMEM; 1434 } 1435 1436 ngd->pdev = platform_device_alloc(QCOM_SLIM_NGD_DRV_NAME, id); 1437 if (!ngd->pdev) { 1438 kfree(ngd); 1439 of_node_put(node); 1440 return -ENOMEM; 1441 } 1442 ngd->id = id; 1443 ngd->pdev->dev.parent = parent; 1444 ngd->pdev->driver_override = QCOM_SLIM_NGD_DRV_NAME; 1445 ngd->pdev->dev.of_node = node; 1446 ctrl->ngd = ngd; 1447 1448 platform_device_add(ngd->pdev); 1449 ngd->base = ctrl->base + ngd->id * data->offset + 1450 (ngd->id - 1) * data->size; 1451 1452 return 0; 1453 } 1454 1455 return -ENODEV; 1456 } 1457 1458 static int qcom_slim_ngd_probe(struct platform_device *pdev) 1459 { 1460 struct device *dev = &pdev->dev; 1461 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev->parent); 1462 int ret; 1463 1464 ctrl->ctrl.dev = dev; 1465 1466 platform_set_drvdata(pdev, ctrl); 1467 pm_runtime_use_autosuspend(dev); 1468 pm_runtime_set_autosuspend_delay(dev, QCOM_SLIM_NGD_AUTOSUSPEND); 1469 pm_runtime_set_suspended(dev); 1470 pm_runtime_enable(dev); 1471 pm_runtime_get_noresume(dev); 1472 ret = qcom_slim_ngd_qmi_svc_event_init(ctrl); 1473 if (ret) { 1474 dev_err(&pdev->dev, "QMI service registration failed:%d", ret); 1475 return ret; 1476 } 1477 1478 INIT_WORK(&ctrl->m_work, qcom_slim_ngd_master_worker); 1479 INIT_WORK(&ctrl->ngd_up_work, qcom_slim_ngd_up_worker); 1480 ctrl->mwq = create_singlethread_workqueue("ngd_master"); 1481 if (!ctrl->mwq) { 1482 dev_err(&pdev->dev, "Failed to start master worker\n"); 1483 ret = -ENOMEM; 1484 goto wq_err; 1485 } 1486 1487 return 0; 1488 wq_err: 1489 qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi); 1490 if (ctrl->mwq) 1491 destroy_workqueue(ctrl->mwq); 1492 1493 return ret; 1494 } 1495 1496 static int qcom_slim_ngd_ctrl_probe(struct platform_device *pdev) 1497 { 1498 struct device *dev = &pdev->dev; 1499 struct qcom_slim_ngd_ctrl *ctrl; 1500 struct resource *res; 1501 int ret; 1502 1503 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 1504 if (!ctrl) 1505 return -ENOMEM; 1506 1507 dev_set_drvdata(dev, ctrl); 1508 1509 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1510 ctrl->base = devm_ioremap_resource(dev, res); 1511 if (IS_ERR(ctrl->base)) 1512 return PTR_ERR(ctrl->base); 1513 1514 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1515 if (!res) { 1516 dev_err(&pdev->dev, "no slimbus IRQ resource\n"); 1517 return -ENODEV; 1518 } 1519 1520 ret = devm_request_irq(dev, res->start, qcom_slim_ngd_interrupt, 1521 IRQF_TRIGGER_HIGH, "slim-ngd", ctrl); 1522 if (ret) { 1523 dev_err(&pdev->dev, "request IRQ failed\n"); 1524 return ret; 1525 } 1526 1527 ctrl->nb.notifier_call = qcom_slim_ngd_ssr_notify; 1528 ctrl->notifier = qcom_register_ssr_notifier("lpass", &ctrl->nb); 1529 if (IS_ERR(ctrl->notifier)) 1530 return PTR_ERR(ctrl->notifier); 1531 1532 ctrl->dev = dev; 1533 ctrl->framer.rootfreq = SLIM_ROOT_FREQ >> 3; 1534 ctrl->framer.superfreq = 1535 ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8; 1536 1537 ctrl->ctrl.a_framer = &ctrl->framer; 1538 ctrl->ctrl.clkgear = SLIM_MAX_CLK_GEAR; 1539 ctrl->ctrl.get_laddr = qcom_slim_ngd_get_laddr; 1540 ctrl->ctrl.enable_stream = qcom_slim_ngd_enable_stream; 1541 ctrl->ctrl.xfer_msg = qcom_slim_ngd_xfer_msg; 1542 ctrl->ctrl.wakeup = NULL; 1543 ctrl->state = QCOM_SLIM_NGD_CTRL_DOWN; 1544 1545 mutex_init(&ctrl->tx_lock); 1546 mutex_init(&ctrl->ssr_lock); 1547 spin_lock_init(&ctrl->tx_buf_lock); 1548 init_completion(&ctrl->reconf); 1549 init_completion(&ctrl->qmi.qmi_comp); 1550 init_completion(&ctrl->qmi_up); 1551 1552 platform_driver_register(&qcom_slim_ngd_driver); 1553 return of_qcom_slim_ngd_register(dev, ctrl); 1554 } 1555 1556 static int qcom_slim_ngd_ctrl_remove(struct platform_device *pdev) 1557 { 1558 platform_driver_unregister(&qcom_slim_ngd_driver); 1559 1560 return 0; 1561 } 1562 1563 static int qcom_slim_ngd_remove(struct platform_device *pdev) 1564 { 1565 struct qcom_slim_ngd_ctrl *ctrl = platform_get_drvdata(pdev); 1566 1567 pm_runtime_disable(&pdev->dev); 1568 qcom_unregister_ssr_notifier(ctrl->notifier, &ctrl->nb); 1569 qcom_slim_ngd_enable(ctrl, false); 1570 qcom_slim_ngd_exit_dma(ctrl); 1571 qcom_slim_ngd_qmi_svc_event_deinit(&ctrl->qmi); 1572 if (ctrl->mwq) 1573 destroy_workqueue(ctrl->mwq); 1574 1575 kfree(ctrl->ngd); 1576 ctrl->ngd = NULL; 1577 return 0; 1578 } 1579 1580 static int __maybe_unused qcom_slim_ngd_runtime_idle(struct device *dev) 1581 { 1582 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev); 1583 1584 if (ctrl->state == QCOM_SLIM_NGD_CTRL_AWAKE) 1585 ctrl->state = QCOM_SLIM_NGD_CTRL_IDLE; 1586 pm_request_autosuspend(dev); 1587 return -EAGAIN; 1588 } 1589 1590 static int __maybe_unused qcom_slim_ngd_runtime_suspend(struct device *dev) 1591 { 1592 struct qcom_slim_ngd_ctrl *ctrl = dev_get_drvdata(dev); 1593 int ret = 0; 1594 1595 ret = qcom_slim_qmi_power_request(ctrl, false); 1596 if (ret && ret != -EBUSY) 1597 dev_info(ctrl->dev, "slim resource not idle:%d\n", ret); 1598 if (!ret || ret == -ETIMEDOUT) 1599 ctrl->state = QCOM_SLIM_NGD_CTRL_ASLEEP; 1600 1601 return ret; 1602 } 1603 1604 static const struct dev_pm_ops qcom_slim_ngd_dev_pm_ops = { 1605 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1606 pm_runtime_force_resume) 1607 SET_RUNTIME_PM_OPS( 1608 qcom_slim_ngd_runtime_suspend, 1609 qcom_slim_ngd_runtime_resume, 1610 qcom_slim_ngd_runtime_idle 1611 ) 1612 }; 1613 1614 static struct platform_driver qcom_slim_ngd_ctrl_driver = { 1615 .probe = qcom_slim_ngd_ctrl_probe, 1616 .remove = qcom_slim_ngd_ctrl_remove, 1617 .driver = { 1618 .name = "qcom,slim-ngd-ctrl", 1619 .of_match_table = qcom_slim_ngd_dt_match, 1620 }, 1621 }; 1622 1623 static struct platform_driver qcom_slim_ngd_driver = { 1624 .probe = qcom_slim_ngd_probe, 1625 .remove = qcom_slim_ngd_remove, 1626 .driver = { 1627 .name = QCOM_SLIM_NGD_DRV_NAME, 1628 .pm = &qcom_slim_ngd_dev_pm_ops, 1629 }, 1630 }; 1631 1632 module_platform_driver(qcom_slim_ngd_ctrl_driver); 1633 MODULE_LICENSE("GPL v2"); 1634 MODULE_DESCRIPTION("Qualcomm SLIMBus NGD controller"); 1635