1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2011-2017, The Linux Foundation 4 */ 5 6 #include <linux/irq.h> 7 #include <linux/kernel.h> 8 #include <linux/init.h> 9 #include <linux/slab.h> 10 #include <linux/io.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <linux/delay.h> 14 #include <linux/clk.h> 15 #include <linux/of.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/pm_runtime.h> 18 #include "slimbus.h" 19 20 /* Manager registers */ 21 #define MGR_CFG 0x200 22 #define MGR_STATUS 0x204 23 #define MGR_INT_EN 0x210 24 #define MGR_INT_STAT 0x214 25 #define MGR_INT_CLR 0x218 26 #define MGR_TX_MSG 0x230 27 #define MGR_RX_MSG 0x270 28 #define MGR_IE_STAT 0x2F0 29 #define MGR_VE_STAT 0x300 30 #define MGR_CFG_ENABLE 1 31 32 /* Framer registers */ 33 #define FRM_CFG 0x400 34 #define FRM_STAT 0x404 35 #define FRM_INT_EN 0x410 36 #define FRM_INT_STAT 0x414 37 #define FRM_INT_CLR 0x418 38 #define FRM_WAKEUP 0x41C 39 #define FRM_CLKCTL_DONE 0x420 40 #define FRM_IE_STAT 0x430 41 #define FRM_VE_STAT 0x440 42 43 /* Interface registers */ 44 #define INTF_CFG 0x600 45 #define INTF_STAT 0x604 46 #define INTF_INT_EN 0x610 47 #define INTF_INT_STAT 0x614 48 #define INTF_INT_CLR 0x618 49 #define INTF_IE_STAT 0x630 50 #define INTF_VE_STAT 0x640 51 52 /* Interrupt status bits */ 53 #define MGR_INT_TX_NACKED_2 BIT(25) 54 #define MGR_INT_MSG_BUF_CONTE BIT(26) 55 #define MGR_INT_RX_MSG_RCVD BIT(30) 56 #define MGR_INT_TX_MSG_SENT BIT(31) 57 58 /* Framer config register settings */ 59 #define FRM_ACTIVE 1 60 #define CLK_GEAR 7 61 #define ROOT_FREQ 11 62 #define REF_CLK_GEAR 15 63 #define INTR_WAKE 19 64 65 #define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \ 66 ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16)) 67 68 #define SLIM_ROOT_FREQ 24576000 69 #define QCOM_SLIM_AUTOSUSPEND 1000 70 71 /* MAX message size over control channel */ 72 #define SLIM_MSGQ_BUF_LEN 40 73 #define QCOM_TX_MSGS 2 74 #define QCOM_RX_MSGS 8 75 #define QCOM_BUF_ALLOC_RETRIES 10 76 77 #define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r)) 78 79 /* V2 Component registers */ 80 #define CFG_PORT_V2(r) ((r ## _V2)) 81 #define COMP_CFG_V2 4 82 #define COMP_TRUST_CFG_V2 0x3000 83 84 /* V1 Component registers */ 85 #define CFG_PORT_V1(r) ((r ## _V1)) 86 #define COMP_CFG_V1 0 87 #define COMP_TRUST_CFG_V1 0x14 88 89 /* Resource group info for manager, and non-ported generic device-components */ 90 #define EE_MGR_RSC_GRP (1 << 10) 91 #define EE_NGD_2 (2 << 6) 92 #define EE_NGD_1 0 93 94 struct slim_ctrl_buf { 95 void *base; 96 phys_addr_t phy; 97 spinlock_t lock; 98 int head; 99 int tail; 100 int sl_sz; 101 int n; 102 }; 103 104 struct qcom_slim_ctrl { 105 struct slim_controller ctrl; 106 struct slim_framer framer; 107 struct device *dev; 108 void __iomem *base; 109 void __iomem *slew_reg; 110 111 struct slim_ctrl_buf rx; 112 struct slim_ctrl_buf tx; 113 114 struct completion **wr_comp; 115 int irq; 116 struct workqueue_struct *rxwq; 117 struct work_struct wd; 118 struct clk *rclk; 119 struct clk *hclk; 120 }; 121 122 static void qcom_slim_queue_tx(struct qcom_slim_ctrl *ctrl, void *buf, 123 u8 len, u32 tx_reg) 124 { 125 int count = (len + 3) >> 2; 126 127 __iowrite32_copy(ctrl->base + tx_reg, buf, count); 128 129 /* Ensure Oder of subsequent writes */ 130 mb(); 131 } 132 133 static void *slim_alloc_rxbuf(struct qcom_slim_ctrl *ctrl) 134 { 135 unsigned long flags; 136 int idx; 137 138 spin_lock_irqsave(&ctrl->rx.lock, flags); 139 if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) { 140 spin_unlock_irqrestore(&ctrl->rx.lock, flags); 141 dev_err(ctrl->dev, "RX QUEUE full!"); 142 return NULL; 143 } 144 idx = ctrl->rx.tail; 145 ctrl->rx.tail = (ctrl->rx.tail + 1) % ctrl->rx.n; 146 spin_unlock_irqrestore(&ctrl->rx.lock, flags); 147 148 return ctrl->rx.base + (idx * ctrl->rx.sl_sz); 149 } 150 151 void slim_ack_txn(struct qcom_slim_ctrl *ctrl, int err) 152 { 153 struct completion *comp; 154 unsigned long flags; 155 int idx; 156 157 spin_lock_irqsave(&ctrl->tx.lock, flags); 158 idx = ctrl->tx.head; 159 ctrl->tx.head = (ctrl->tx.head + 1) % ctrl->tx.n; 160 spin_unlock_irqrestore(&ctrl->tx.lock, flags); 161 162 comp = ctrl->wr_comp[idx]; 163 ctrl->wr_comp[idx] = NULL; 164 165 complete(comp); 166 } 167 168 static irqreturn_t qcom_slim_handle_tx_irq(struct qcom_slim_ctrl *ctrl, 169 u32 stat) 170 { 171 int err = 0; 172 173 if (stat & MGR_INT_TX_MSG_SENT) 174 writel_relaxed(MGR_INT_TX_MSG_SENT, 175 ctrl->base + MGR_INT_CLR); 176 177 if (stat & MGR_INT_TX_NACKED_2) { 178 u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS); 179 u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT); 180 u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT); 181 u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG); 182 u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT); 183 u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT); 184 u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT); 185 u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT); 186 u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT); 187 188 writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR); 189 190 dev_err(ctrl->dev, "TX Nack MGR:int:0x%x, stat:0x%x\n", 191 stat, mgr_stat); 192 dev_err(ctrl->dev, "TX Nack MGR:ie:0x%x\n", mgr_ie_stat); 193 dev_err(ctrl->dev, "TX Nack FRM:int:0x%x, stat:0x%x\n", 194 frm_intr_stat, frm_stat); 195 dev_err(ctrl->dev, "TX Nack FRM:cfg:0x%x, ie:0x%x\n", 196 frm_cfg, frm_ie_stat); 197 dev_err(ctrl->dev, "TX Nack INTF:intr:0x%x, stat:0x%x\n", 198 intf_intr_stat, intf_stat); 199 dev_err(ctrl->dev, "TX Nack INTF:ie:0x%x\n", 200 intf_ie_stat); 201 err = -ENOTCONN; 202 } 203 204 slim_ack_txn(ctrl, err); 205 206 return IRQ_HANDLED; 207 } 208 209 static irqreturn_t qcom_slim_handle_rx_irq(struct qcom_slim_ctrl *ctrl, 210 u32 stat) 211 { 212 u32 *rx_buf, pkt[10]; 213 bool q_rx = false; 214 u8 mc, mt, len; 215 216 pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG); 217 mt = SLIM_HEADER_GET_MT(pkt[0]); 218 len = SLIM_HEADER_GET_RL(pkt[0]); 219 mc = SLIM_HEADER_GET_MC(pkt[0]>>8); 220 221 /* 222 * this message cannot be handled by ISR, so 223 * let work-queue handle it 224 */ 225 if (mt == SLIM_MSG_MT_CORE && mc == SLIM_MSG_MC_REPORT_PRESENT) { 226 rx_buf = (u32 *)slim_alloc_rxbuf(ctrl); 227 if (!rx_buf) { 228 dev_err(ctrl->dev, "dropping RX:0x%x due to RX full\n", 229 pkt[0]); 230 goto rx_ret_irq; 231 } 232 rx_buf[0] = pkt[0]; 233 234 } else { 235 rx_buf = pkt; 236 } 237 238 __ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4, 239 DIV_ROUND_UP(len, 4)); 240 241 switch (mc) { 242 243 case SLIM_MSG_MC_REPORT_PRESENT: 244 q_rx = true; 245 break; 246 case SLIM_MSG_MC_REPLY_INFORMATION: 247 case SLIM_MSG_MC_REPLY_VALUE: 248 slim_msg_response(&ctrl->ctrl, (u8 *)(rx_buf + 1), 249 (u8)(*rx_buf >> 24), (len - 4)); 250 break; 251 default: 252 dev_err(ctrl->dev, "unsupported MC,%x MT:%x\n", 253 mc, mt); 254 break; 255 } 256 rx_ret_irq: 257 writel(MGR_INT_RX_MSG_RCVD, ctrl->base + 258 MGR_INT_CLR); 259 if (q_rx) 260 queue_work(ctrl->rxwq, &ctrl->wd); 261 262 return IRQ_HANDLED; 263 } 264 265 static irqreturn_t qcom_slim_interrupt(int irq, void *d) 266 { 267 struct qcom_slim_ctrl *ctrl = d; 268 u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT); 269 int ret = IRQ_NONE; 270 271 if (stat & MGR_INT_TX_MSG_SENT || stat & MGR_INT_TX_NACKED_2) 272 ret = qcom_slim_handle_tx_irq(ctrl, stat); 273 274 if (stat & MGR_INT_RX_MSG_RCVD) 275 ret = qcom_slim_handle_rx_irq(ctrl, stat); 276 277 return ret; 278 } 279 280 static int qcom_clk_pause_wakeup(struct slim_controller *sctrl) 281 { 282 struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); 283 284 clk_prepare_enable(ctrl->hclk); 285 clk_prepare_enable(ctrl->rclk); 286 enable_irq(ctrl->irq); 287 288 writel_relaxed(1, ctrl->base + FRM_WAKEUP); 289 /* Make sure framer wakeup write goes through before ISR fires */ 290 mb(); 291 /* 292 * HW Workaround: Currently, slave is reporting lost-sync messages 293 * after SLIMbus comes out of clock pause. 294 * Transaction with slave fail before slave reports that message 295 * Give some time for that report to come 296 * SLIMbus wakes up in clock gear 10 at 24.576MHz. With each superframe 297 * being 250 usecs, we wait for 5-10 superframes here to ensure 298 * we get the message 299 */ 300 usleep_range(1250, 2500); 301 return 0; 302 } 303 304 void *slim_alloc_txbuf(struct qcom_slim_ctrl *ctrl, struct slim_msg_txn *txn, 305 struct completion *done) 306 { 307 unsigned long flags; 308 int idx; 309 310 spin_lock_irqsave(&ctrl->tx.lock, flags); 311 if (((ctrl->tx.head + 1) % ctrl->tx.n) == ctrl->tx.tail) { 312 spin_unlock_irqrestore(&ctrl->tx.lock, flags); 313 dev_err(ctrl->dev, "controller TX buf unavailable"); 314 return NULL; 315 } 316 idx = ctrl->tx.tail; 317 ctrl->wr_comp[idx] = done; 318 ctrl->tx.tail = (ctrl->tx.tail + 1) % ctrl->tx.n; 319 320 spin_unlock_irqrestore(&ctrl->tx.lock, flags); 321 322 return ctrl->tx.base + (idx * ctrl->tx.sl_sz); 323 } 324 325 326 static int qcom_xfer_msg(struct slim_controller *sctrl, 327 struct slim_msg_txn *txn) 328 { 329 struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); 330 DECLARE_COMPLETION_ONSTACK(done); 331 void *pbuf = slim_alloc_txbuf(ctrl, txn, &done); 332 unsigned long ms = txn->rl + HZ; 333 u8 *puc; 334 int ret = 0, timeout, retries = QCOM_BUF_ALLOC_RETRIES; 335 u8 la = txn->la; 336 u32 *head; 337 /* HW expects length field to be excluded */ 338 txn->rl--; 339 340 /* spin till buffer is made available */ 341 if (!pbuf) { 342 while (retries--) { 343 usleep_range(10000, 15000); 344 pbuf = slim_alloc_txbuf(ctrl, txn, &done); 345 if (pbuf) 346 break; 347 } 348 } 349 350 if (!retries && !pbuf) 351 return -ENOMEM; 352 353 puc = (u8 *)pbuf; 354 head = (u32 *)pbuf; 355 356 if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) { 357 *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, 358 txn->mc, 0, la); 359 puc += 3; 360 } else { 361 *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, 362 txn->mc, 1, la); 363 puc += 2; 364 } 365 366 if (slim_tid_txn(txn->mt, txn->mc)) 367 *(puc++) = txn->tid; 368 369 if (slim_ec_txn(txn->mt, txn->mc)) { 370 *(puc++) = (txn->ec & 0xFF); 371 *(puc++) = (txn->ec >> 8) & 0xFF; 372 } 373 374 if (txn->msg && txn->msg->wbuf) 375 memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes); 376 377 qcom_slim_queue_tx(ctrl, head, txn->rl, MGR_TX_MSG); 378 timeout = wait_for_completion_timeout(&done, msecs_to_jiffies(ms)); 379 380 if (!timeout) { 381 dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc, 382 txn->mt); 383 ret = -ETIMEDOUT; 384 } 385 386 return ret; 387 388 } 389 390 static int qcom_set_laddr(struct slim_controller *sctrl, 391 struct slim_eaddr *ead, u8 laddr) 392 { 393 struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); 394 struct { 395 __be16 manf_id; 396 __be16 prod_code; 397 u8 dev_index; 398 u8 instance; 399 u8 laddr; 400 } __packed p; 401 struct slim_val_inf msg = {0}; 402 DEFINE_SLIM_EDEST_TXN(txn, SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS, 403 10, laddr, &msg); 404 int ret; 405 406 p.manf_id = cpu_to_be16(ead->manf_id); 407 p.prod_code = cpu_to_be16(ead->prod_code); 408 p.dev_index = ead->dev_index; 409 p.instance = ead->instance; 410 p.laddr = laddr; 411 412 msg.wbuf = (void *)&p; 413 msg.num_bytes = 7; 414 ret = slim_do_transfer(&ctrl->ctrl, &txn); 415 416 if (ret) 417 dev_err(ctrl->dev, "set LA:0x%x failed:ret:%d\n", 418 laddr, ret); 419 return ret; 420 } 421 422 static int slim_get_current_rxbuf(struct qcom_slim_ctrl *ctrl, void *buf) 423 { 424 unsigned long flags; 425 426 spin_lock_irqsave(&ctrl->rx.lock, flags); 427 if (ctrl->rx.tail == ctrl->rx.head) { 428 spin_unlock_irqrestore(&ctrl->rx.lock, flags); 429 return -ENODATA; 430 } 431 memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz), 432 ctrl->rx.sl_sz); 433 434 ctrl->rx.head = (ctrl->rx.head + 1) % ctrl->rx.n; 435 spin_unlock_irqrestore(&ctrl->rx.lock, flags); 436 437 return 0; 438 } 439 440 static void qcom_slim_rxwq(struct work_struct *work) 441 { 442 u8 buf[SLIM_MSGQ_BUF_LEN]; 443 u8 mc, mt, len; 444 int ret; 445 struct qcom_slim_ctrl *ctrl = container_of(work, struct qcom_slim_ctrl, 446 wd); 447 448 while ((slim_get_current_rxbuf(ctrl, buf)) != -ENODATA) { 449 len = SLIM_HEADER_GET_RL(buf[0]); 450 mt = SLIM_HEADER_GET_MT(buf[0]); 451 mc = SLIM_HEADER_GET_MC(buf[1]); 452 if (mt == SLIM_MSG_MT_CORE && 453 mc == SLIM_MSG_MC_REPORT_PRESENT) { 454 struct slim_eaddr ea; 455 u8 laddr; 456 457 ea.manf_id = be16_to_cpup((__be16 *)&buf[2]); 458 ea.prod_code = be16_to_cpup((__be16 *)&buf[4]); 459 ea.dev_index = buf[6]; 460 ea.instance = buf[7]; 461 462 ret = slim_device_report_present(&ctrl->ctrl, &ea, 463 &laddr); 464 if (ret < 0) 465 dev_err(ctrl->dev, "assign laddr failed:%d\n", 466 ret); 467 } else { 468 dev_err(ctrl->dev, "unexpected message:mc:%x, mt:%x\n", 469 mc, mt); 470 } 471 } 472 } 473 474 static void qcom_slim_prg_slew(struct platform_device *pdev, 475 struct qcom_slim_ctrl *ctrl) 476 { 477 struct resource *slew_mem; 478 479 if (!ctrl->slew_reg) { 480 /* SLEW RATE register for this SLIMbus */ 481 slew_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, 482 "slew"); 483 ctrl->slew_reg = devm_ioremap(&pdev->dev, slew_mem->start, 484 resource_size(slew_mem)); 485 if (!ctrl->slew_reg) 486 return; 487 } 488 489 writel_relaxed(1, ctrl->slew_reg); 490 /* Make sure SLIMbus-slew rate enabling goes through */ 491 wmb(); 492 } 493 494 static int qcom_slim_probe(struct platform_device *pdev) 495 { 496 struct qcom_slim_ctrl *ctrl; 497 struct slim_controller *sctrl; 498 struct resource *slim_mem; 499 int ret, ver; 500 501 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); 502 if (!ctrl) 503 return -ENOMEM; 504 505 ctrl->hclk = devm_clk_get(&pdev->dev, "iface"); 506 if (IS_ERR(ctrl->hclk)) 507 return PTR_ERR(ctrl->hclk); 508 509 ctrl->rclk = devm_clk_get(&pdev->dev, "core"); 510 if (IS_ERR(ctrl->rclk)) 511 return PTR_ERR(ctrl->rclk); 512 513 ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ); 514 if (ret) { 515 dev_err(&pdev->dev, "ref-clock set-rate failed:%d\n", ret); 516 return ret; 517 } 518 519 ctrl->irq = platform_get_irq(pdev, 0); 520 if (!ctrl->irq) { 521 dev_err(&pdev->dev, "no slimbus IRQ\n"); 522 return -ENODEV; 523 } 524 525 sctrl = &ctrl->ctrl; 526 sctrl->dev = &pdev->dev; 527 ctrl->dev = &pdev->dev; 528 platform_set_drvdata(pdev, ctrl); 529 dev_set_drvdata(ctrl->dev, ctrl); 530 531 slim_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); 532 ctrl->base = devm_ioremap_resource(ctrl->dev, slim_mem); 533 if (!ctrl->base) { 534 dev_err(&pdev->dev, "IOremap failed\n"); 535 return -ENOMEM; 536 } 537 538 sctrl->set_laddr = qcom_set_laddr; 539 sctrl->xfer_msg = qcom_xfer_msg; 540 sctrl->wakeup = qcom_clk_pause_wakeup; 541 ctrl->tx.n = QCOM_TX_MSGS; 542 ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN; 543 ctrl->rx.n = QCOM_RX_MSGS; 544 ctrl->rx.sl_sz = SLIM_MSGQ_BUF_LEN; 545 ctrl->wr_comp = kzalloc(sizeof(struct completion *) * QCOM_TX_MSGS, 546 GFP_KERNEL); 547 if (!ctrl->wr_comp) 548 return -ENOMEM; 549 550 spin_lock_init(&ctrl->rx.lock); 551 spin_lock_init(&ctrl->tx.lock); 552 INIT_WORK(&ctrl->wd, qcom_slim_rxwq); 553 ctrl->rxwq = create_singlethread_workqueue("qcom_slim_rx"); 554 if (!ctrl->rxwq) { 555 dev_err(ctrl->dev, "Failed to start Rx WQ\n"); 556 return -ENOMEM; 557 } 558 559 ctrl->framer.rootfreq = SLIM_ROOT_FREQ / 8; 560 ctrl->framer.superfreq = 561 ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8; 562 sctrl->a_framer = &ctrl->framer; 563 sctrl->clkgear = SLIM_MAX_CLK_GEAR; 564 565 qcom_slim_prg_slew(pdev, ctrl); 566 567 ret = devm_request_irq(&pdev->dev, ctrl->irq, qcom_slim_interrupt, 568 IRQF_TRIGGER_HIGH, "qcom_slim_irq", ctrl); 569 if (ret) { 570 dev_err(&pdev->dev, "request IRQ failed\n"); 571 goto err_request_irq_failed; 572 } 573 574 ret = clk_prepare_enable(ctrl->hclk); 575 if (ret) 576 goto err_hclk_enable_failed; 577 578 ret = clk_prepare_enable(ctrl->rclk); 579 if (ret) 580 goto err_rclk_enable_failed; 581 582 ctrl->tx.base = dmam_alloc_coherent(&pdev->dev, 583 (ctrl->tx.sl_sz * ctrl->tx.n), 584 &ctrl->tx.phy, GFP_KERNEL); 585 if (!ctrl->tx.base) { 586 ret = -ENOMEM; 587 goto err; 588 } 589 590 ctrl->rx.base = dmam_alloc_coherent(&pdev->dev, 591 (ctrl->rx.sl_sz * ctrl->rx.n), 592 &ctrl->rx.phy, GFP_KERNEL); 593 if (!ctrl->rx.base) { 594 ret = -ENOMEM; 595 goto err; 596 } 597 598 /* Register with framework before enabling frame, clock */ 599 ret = slim_register_controller(&ctrl->ctrl); 600 if (ret) { 601 dev_err(ctrl->dev, "error adding controller\n"); 602 goto err; 603 } 604 605 ver = readl_relaxed(ctrl->base); 606 /* Version info in 16 MSbits */ 607 ver >>= 16; 608 /* Component register initialization */ 609 writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver)); 610 writel((EE_MGR_RSC_GRP | EE_NGD_2 | EE_NGD_1), 611 ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver)); 612 613 writel((MGR_INT_TX_NACKED_2 | 614 MGR_INT_MSG_BUF_CONTE | MGR_INT_RX_MSG_RCVD | 615 MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN); 616 writel(1, ctrl->base + MGR_CFG); 617 /* Framer register initialization */ 618 writel((1 << INTR_WAKE) | (0xA << REF_CLK_GEAR) | 619 (0xA << CLK_GEAR) | (1 << ROOT_FREQ) | (1 << FRM_ACTIVE) | 1, 620 ctrl->base + FRM_CFG); 621 writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG); 622 writel(1, ctrl->base + INTF_CFG); 623 writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver)); 624 625 pm_runtime_use_autosuspend(&pdev->dev); 626 pm_runtime_set_autosuspend_delay(&pdev->dev, QCOM_SLIM_AUTOSUSPEND); 627 pm_runtime_set_active(&pdev->dev); 628 pm_runtime_mark_last_busy(&pdev->dev); 629 pm_runtime_enable(&pdev->dev); 630 631 dev_dbg(ctrl->dev, "QCOM SB controller is up:ver:0x%x!\n", ver); 632 return 0; 633 634 err: 635 clk_disable_unprepare(ctrl->rclk); 636 err_rclk_enable_failed: 637 clk_disable_unprepare(ctrl->hclk); 638 err_hclk_enable_failed: 639 err_request_irq_failed: 640 destroy_workqueue(ctrl->rxwq); 641 return ret; 642 } 643 644 static int qcom_slim_remove(struct platform_device *pdev) 645 { 646 struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev); 647 648 pm_runtime_disable(&pdev->dev); 649 slim_unregister_controller(&ctrl->ctrl); 650 destroy_workqueue(ctrl->rxwq); 651 return 0; 652 } 653 654 /* 655 * If PM_RUNTIME is not defined, these 2 functions become helper 656 * functions to be called from system suspend/resume. 657 */ 658 #ifdef CONFIG_PM 659 static int qcom_slim_runtime_suspend(struct device *device) 660 { 661 struct platform_device *pdev = to_platform_device(device); 662 struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev); 663 int ret; 664 665 dev_dbg(device, "pm_runtime: suspending...\n"); 666 ret = slim_ctrl_clk_pause(&ctrl->ctrl, false, SLIM_CLK_UNSPECIFIED); 667 if (ret) { 668 dev_err(device, "clk pause not entered:%d", ret); 669 } else { 670 disable_irq(ctrl->irq); 671 clk_disable_unprepare(ctrl->hclk); 672 clk_disable_unprepare(ctrl->rclk); 673 } 674 return ret; 675 } 676 677 static int qcom_slim_runtime_resume(struct device *device) 678 { 679 struct platform_device *pdev = to_platform_device(device); 680 struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev); 681 int ret = 0; 682 683 dev_dbg(device, "pm_runtime: resuming...\n"); 684 ret = slim_ctrl_clk_pause(&ctrl->ctrl, true, 0); 685 if (ret) 686 dev_err(device, "clk pause not exited:%d", ret); 687 return ret; 688 } 689 #endif 690 691 #ifdef CONFIG_PM_SLEEP 692 static int qcom_slim_suspend(struct device *dev) 693 { 694 int ret = 0; 695 696 if (!pm_runtime_enabled(dev) || 697 (!pm_runtime_suspended(dev))) { 698 dev_dbg(dev, "system suspend"); 699 ret = qcom_slim_runtime_suspend(dev); 700 } 701 702 return ret; 703 } 704 705 static int qcom_slim_resume(struct device *dev) 706 { 707 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) { 708 int ret; 709 710 dev_dbg(dev, "system resume"); 711 ret = qcom_slim_runtime_resume(dev); 712 if (!ret) { 713 pm_runtime_mark_last_busy(dev); 714 pm_request_autosuspend(dev); 715 } 716 return ret; 717 718 } 719 return 0; 720 } 721 #endif /* CONFIG_PM_SLEEP */ 722 723 static const struct dev_pm_ops qcom_slim_dev_pm_ops = { 724 SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume) 725 SET_RUNTIME_PM_OPS( 726 qcom_slim_runtime_suspend, 727 qcom_slim_runtime_resume, 728 NULL 729 ) 730 }; 731 732 static const struct of_device_id qcom_slim_dt_match[] = { 733 { .compatible = "qcom,slim", }, 734 { .compatible = "qcom,apq8064-slim", }, 735 {} 736 }; 737 738 static struct platform_driver qcom_slim_driver = { 739 .probe = qcom_slim_probe, 740 .remove = qcom_slim_remove, 741 .driver = { 742 .name = "qcom_slim_ctrl", 743 .of_match_table = qcom_slim_dt_match, 744 .pm = &qcom_slim_dev_pm_ops, 745 }, 746 }; 747 module_platform_driver(qcom_slim_driver); 748 749 MODULE_LICENSE("GPL v2"); 750 MODULE_DESCRIPTION("Qualcomm SLIMbus Controller"); 751