1 /* 2 * Shared interrupt handling code for IPR and INTC2 types of IRQs. 3 * 4 * Copyright (C) 2007, 2008 Magnus Damm 5 * Copyright (C) 2009, 2010 Paul Mundt 6 * 7 * Based on intc2.c and ipr.c 8 * 9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi 10 * Copyright (C) 2000 Kazumoto Kojima 11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) 12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> 13 * Copyright (C) 2005, 2006 Paul Mundt 14 * 15 * This file is subject to the terms and conditions of the GNU General Public 16 * License. See the file "COPYING" in the main directory of this archive 17 * for more details. 18 */ 19 #define pr_fmt(fmt) "intc: " fmt 20 21 #include <linux/init.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/slab.h> 25 #include <linux/interrupt.h> 26 #include <linux/sh_intc.h> 27 #include <linux/sysdev.h> 28 #include <linux/list.h> 29 #include <linux/spinlock.h> 30 #include <linux/radix-tree.h> 31 #include "internals.h" 32 33 LIST_HEAD(intc_list); 34 DEFINE_RAW_SPINLOCK(intc_big_lock); 35 unsigned int nr_intc_controllers; 36 37 /* 38 * Default priority level 39 * - this needs to be at least 2 for 5-bit priorities on 7780 40 */ 41 static unsigned int default_prio_level = 2; /* 2 - 16 */ 42 static unsigned int intc_prio_level[NR_IRQS]; /* for now */ 43 44 unsigned int intc_get_dfl_prio_level(void) 45 { 46 return default_prio_level; 47 } 48 49 unsigned int intc_get_prio_level(unsigned int irq) 50 { 51 return intc_prio_level[irq]; 52 } 53 54 void intc_set_prio_level(unsigned int irq, unsigned int level) 55 { 56 unsigned long flags; 57 58 raw_spin_lock_irqsave(&intc_big_lock, flags); 59 intc_prio_level[irq] = level; 60 raw_spin_unlock_irqrestore(&intc_big_lock, flags); 61 } 62 63 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc) 64 { 65 generic_handle_irq((unsigned int)get_irq_data(irq)); 66 } 67 68 static void __init intc_register_irq(struct intc_desc *desc, 69 struct intc_desc_int *d, 70 intc_enum enum_id, 71 unsigned int irq) 72 { 73 struct intc_handle_int *hp; 74 struct irq_data *irq_data; 75 unsigned int data[2], primary; 76 unsigned long flags; 77 78 /* 79 * Register the IRQ position with the global IRQ map, then insert 80 * it in to the radix tree. 81 */ 82 irq_reserve_irq(irq); 83 84 raw_spin_lock_irqsave(&intc_big_lock, flags); 85 radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq)); 86 raw_spin_unlock_irqrestore(&intc_big_lock, flags); 87 88 /* 89 * Prefer single interrupt source bitmap over other combinations: 90 * 91 * 1. bitmap, single interrupt source 92 * 2. priority, single interrupt source 93 * 3. bitmap, multiple interrupt sources (groups) 94 * 4. priority, multiple interrupt sources (groups) 95 */ 96 data[0] = intc_get_mask_handle(desc, d, enum_id, 0); 97 data[1] = intc_get_prio_handle(desc, d, enum_id, 0); 98 99 primary = 0; 100 if (!data[0] && data[1]) 101 primary = 1; 102 103 if (!data[0] && !data[1]) 104 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n", 105 irq, irq2evt(irq)); 106 107 data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1); 108 data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1); 109 110 if (!data[primary]) 111 primary ^= 1; 112 113 BUG_ON(!data[primary]); /* must have primary masking method */ 114 115 irq_data = irq_get_irq_data(irq); 116 117 disable_irq_nosync(irq); 118 set_irq_chip_and_handler_name(irq, &d->chip, 119 handle_level_irq, "level"); 120 set_irq_chip_data(irq, (void *)data[primary]); 121 122 /* 123 * set priority level 124 */ 125 intc_set_prio_level(irq, intc_get_dfl_prio_level()); 126 127 /* enable secondary masking method if present */ 128 if (data[!primary]) 129 _intc_enable(irq_data, data[!primary]); 130 131 /* add irq to d->prio list if priority is available */ 132 if (data[1]) { 133 hp = d->prio + d->nr_prio; 134 hp->irq = irq; 135 hp->handle = data[1]; 136 137 if (primary) { 138 /* 139 * only secondary priority should access registers, so 140 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority() 141 */ 142 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0); 143 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0); 144 } 145 d->nr_prio++; 146 } 147 148 /* add irq to d->sense list if sense is available */ 149 data[0] = intc_get_sense_handle(desc, d, enum_id); 150 if (data[0]) { 151 (d->sense + d->nr_sense)->irq = irq; 152 (d->sense + d->nr_sense)->handle = data[0]; 153 d->nr_sense++; 154 } 155 156 /* irq should be disabled by default */ 157 d->chip.irq_mask(irq_data); 158 159 intc_set_ack_handle(irq, desc, d, enum_id); 160 intc_set_dist_handle(irq, desc, d, enum_id); 161 162 activate_irq(irq); 163 } 164 165 static unsigned int __init save_reg(struct intc_desc_int *d, 166 unsigned int cnt, 167 unsigned long value, 168 unsigned int smp) 169 { 170 if (value) { 171 value = intc_phys_to_virt(d, value); 172 173 d->reg[cnt] = value; 174 #ifdef CONFIG_SMP 175 d->smp[cnt] = smp; 176 #endif 177 return 1; 178 } 179 180 return 0; 181 } 182 183 int __init register_intc_controller(struct intc_desc *desc) 184 { 185 unsigned int i, k, smp; 186 struct intc_hw_desc *hw = &desc->hw; 187 struct intc_desc_int *d; 188 struct resource *res; 189 190 pr_info("Registered controller '%s' with %u IRQs\n", 191 desc->name, hw->nr_vectors); 192 193 d = kzalloc(sizeof(*d), GFP_NOWAIT); 194 if (!d) 195 goto err0; 196 197 INIT_LIST_HEAD(&d->list); 198 list_add_tail(&d->list, &intc_list); 199 200 raw_spin_lock_init(&d->lock); 201 INIT_RADIX_TREE(&d->tree, GFP_ATOMIC); 202 203 d->index = nr_intc_controllers; 204 205 if (desc->num_resources) { 206 d->nr_windows = desc->num_resources; 207 d->window = kzalloc(d->nr_windows * sizeof(*d->window), 208 GFP_NOWAIT); 209 if (!d->window) 210 goto err1; 211 212 for (k = 0; k < d->nr_windows; k++) { 213 res = desc->resource + k; 214 WARN_ON(resource_type(res) != IORESOURCE_MEM); 215 d->window[k].phys = res->start; 216 d->window[k].size = resource_size(res); 217 d->window[k].virt = ioremap_nocache(res->start, 218 resource_size(res)); 219 if (!d->window[k].virt) 220 goto err2; 221 } 222 } 223 224 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; 225 #ifdef CONFIG_INTC_BALANCING 226 if (d->nr_reg) 227 d->nr_reg += hw->nr_mask_regs; 228 #endif 229 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0; 230 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0; 231 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0; 232 d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0; 233 234 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); 235 if (!d->reg) 236 goto err2; 237 238 #ifdef CONFIG_SMP 239 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT); 240 if (!d->smp) 241 goto err3; 242 #endif 243 k = 0; 244 245 if (hw->mask_regs) { 246 for (i = 0; i < hw->nr_mask_regs; i++) { 247 smp = IS_SMP(hw->mask_regs[i]); 248 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); 249 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); 250 #ifdef CONFIG_INTC_BALANCING 251 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0); 252 #endif 253 } 254 } 255 256 if (hw->prio_regs) { 257 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio), 258 GFP_NOWAIT); 259 if (!d->prio) 260 goto err4; 261 262 for (i = 0; i < hw->nr_prio_regs; i++) { 263 smp = IS_SMP(hw->prio_regs[i]); 264 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp); 265 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp); 266 } 267 } 268 269 if (hw->sense_regs) { 270 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense), 271 GFP_NOWAIT); 272 if (!d->sense) 273 goto err5; 274 275 for (i = 0; i < hw->nr_sense_regs; i++) 276 k += save_reg(d, k, hw->sense_regs[i].reg, 0); 277 } 278 279 if (hw->subgroups) 280 for (i = 0; i < hw->nr_subgroups; i++) 281 if (hw->subgroups[i].reg) 282 k+= save_reg(d, k, hw->subgroups[i].reg, 0); 283 284 memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip)); 285 d->chip.name = desc->name; 286 287 if (hw->ack_regs) 288 for (i = 0; i < hw->nr_ack_regs; i++) 289 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0); 290 else 291 d->chip.irq_mask_ack = d->chip.irq_disable; 292 293 /* disable bits matching force_disable before registering irqs */ 294 if (desc->force_disable) 295 intc_enable_disable_enum(desc, d, desc->force_disable, 0); 296 297 /* disable bits matching force_enable before registering irqs */ 298 if (desc->force_enable) 299 intc_enable_disable_enum(desc, d, desc->force_enable, 0); 300 301 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ 302 303 /* register the vectors one by one */ 304 for (i = 0; i < hw->nr_vectors; i++) { 305 struct intc_vect *vect = hw->vectors + i; 306 unsigned int irq = evt2irq(vect->vect); 307 int res; 308 309 if (!vect->enum_id) 310 continue; 311 312 res = irq_alloc_desc_at(irq, numa_node_id()); 313 if (res != irq && res != -EEXIST) { 314 pr_err("can't get irq_desc for %d\n", irq); 315 continue; 316 } 317 318 intc_irq_xlate_set(irq, vect->enum_id, d); 319 intc_register_irq(desc, d, vect->enum_id, irq); 320 321 for (k = i + 1; k < hw->nr_vectors; k++) { 322 struct intc_vect *vect2 = hw->vectors + k; 323 unsigned int irq2 = evt2irq(vect2->vect); 324 325 if (vect->enum_id != vect2->enum_id) 326 continue; 327 328 /* 329 * In the case of multi-evt handling and sparse 330 * IRQ support, each vector still needs to have 331 * its own backing irq_desc. 332 */ 333 res = irq_alloc_desc_at(irq2, numa_node_id()); 334 if (res != irq2 && res != -EEXIST) { 335 pr_err("can't get irq_desc for %d\n", irq2); 336 continue; 337 } 338 339 vect2->enum_id = 0; 340 341 /* redirect this interrupts to the first one */ 342 set_irq_chip(irq2, &dummy_irq_chip); 343 set_irq_chained_handler(irq2, intc_redirect_irq); 344 set_irq_data(irq2, (void *)irq); 345 } 346 } 347 348 intc_subgroup_init(desc, d); 349 350 /* enable bits matching force_enable after registering irqs */ 351 if (desc->force_enable) 352 intc_enable_disable_enum(desc, d, desc->force_enable, 1); 353 354 nr_intc_controllers++; 355 356 return 0; 357 err5: 358 kfree(d->prio); 359 err4: 360 #ifdef CONFIG_SMP 361 kfree(d->smp); 362 err3: 363 #endif 364 kfree(d->reg); 365 err2: 366 for (k = 0; k < d->nr_windows; k++) 367 if (d->window[k].virt) 368 iounmap(d->window[k].virt); 369 370 kfree(d->window); 371 err1: 372 kfree(d); 373 err0: 374 pr_err("unable to allocate INTC memory\n"); 375 376 return -ENOMEM; 377 } 378 379 static ssize_t 380 show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf) 381 { 382 struct intc_desc_int *d; 383 384 d = container_of(dev, struct intc_desc_int, sysdev); 385 386 return sprintf(buf, "%s\n", d->chip.name); 387 } 388 389 static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL); 390 391 static int intc_suspend(struct sys_device *dev, pm_message_t state) 392 { 393 struct intc_desc_int *d; 394 struct irq_data *data; 395 struct irq_desc *desc; 396 struct irq_chip *chip; 397 int irq; 398 399 /* get intc controller associated with this sysdev */ 400 d = container_of(dev, struct intc_desc_int, sysdev); 401 402 switch (state.event) { 403 case PM_EVENT_ON: 404 if (d->state.event != PM_EVENT_FREEZE) 405 break; 406 407 for_each_active_irq(irq) { 408 desc = irq_to_desc(irq); 409 data = irq_get_irq_data(irq); 410 chip = irq_data_get_irq_chip(data); 411 412 /* 413 * This will catch the redirect and VIRQ cases 414 * due to the dummy_irq_chip being inserted. 415 */ 416 if (chip != &d->chip) 417 continue; 418 if (desc->status & IRQ_DISABLED) 419 chip->irq_disable(data); 420 else 421 chip->irq_enable(data); 422 } 423 break; 424 case PM_EVENT_FREEZE: 425 /* nothing has to be done */ 426 break; 427 case PM_EVENT_SUSPEND: 428 /* enable wakeup irqs belonging to this intc controller */ 429 for_each_active_irq(irq) { 430 desc = irq_to_desc(irq); 431 data = irq_get_irq_data(irq); 432 chip = irq_data_get_irq_chip(data); 433 434 if (chip != &d->chip) 435 continue; 436 if ((desc->status & IRQ_WAKEUP)) 437 chip->irq_enable(data); 438 } 439 break; 440 } 441 442 d->state = state; 443 444 return 0; 445 } 446 447 static int intc_resume(struct sys_device *dev) 448 { 449 return intc_suspend(dev, PMSG_ON); 450 } 451 452 struct sysdev_class intc_sysdev_class = { 453 .name = "intc", 454 .suspend = intc_suspend, 455 .resume = intc_resume, 456 }; 457 458 /* register this intc as sysdev to allow suspend/resume */ 459 static int __init register_intc_sysdevs(void) 460 { 461 struct intc_desc_int *d; 462 int error; 463 464 error = sysdev_class_register(&intc_sysdev_class); 465 if (!error) { 466 list_for_each_entry(d, &intc_list, list) { 467 d->sysdev.id = d->index; 468 d->sysdev.cls = &intc_sysdev_class; 469 error = sysdev_register(&d->sysdev); 470 if (error == 0) 471 error = sysdev_create_file(&d->sysdev, 472 &attr_name); 473 if (error) 474 break; 475 } 476 } 477 478 if (error) 479 pr_err("sysdev registration error\n"); 480 481 return error; 482 } 483 device_initcall(register_intc_sysdevs); 484