1 /* 2 * Shared interrupt handling code for IPR and INTC2 types of IRQs. 3 * 4 * Copyright (C) 2007, 2008 Magnus Damm 5 * Copyright (C) 2009 - 2012 Paul Mundt 6 * 7 * Based on intc2.c and ipr.c 8 * 9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi 10 * Copyright (C) 2000 Kazumoto Kojima 11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) 12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> 13 * Copyright (C) 2005, 2006 Paul Mundt 14 * 15 * This file is subject to the terms and conditions of the GNU General Public 16 * License. See the file "COPYING" in the main directory of this archive 17 * for more details. 18 */ 19 #define pr_fmt(fmt) "intc: " fmt 20 21 #include <linux/init.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/slab.h> 25 #include <linux/stat.h> 26 #include <linux/interrupt.h> 27 #include <linux/sh_intc.h> 28 #include <linux/irqdomain.h> 29 #include <linux/device.h> 30 #include <linux/syscore_ops.h> 31 #include <linux/list.h> 32 #include <linux/spinlock.h> 33 #include <linux/radix-tree.h> 34 #include <linux/export.h> 35 #include <linux/sort.h> 36 #include "internals.h" 37 38 LIST_HEAD(intc_list); 39 DEFINE_RAW_SPINLOCK(intc_big_lock); 40 static unsigned int nr_intc_controllers; 41 42 /* 43 * Default priority level 44 * - this needs to be at least 2 for 5-bit priorities on 7780 45 */ 46 static unsigned int default_prio_level = 2; /* 2 - 16 */ 47 static unsigned int intc_prio_level[INTC_NR_IRQS]; /* for now */ 48 49 unsigned int intc_get_dfl_prio_level(void) 50 { 51 return default_prio_level; 52 } 53 54 unsigned int intc_get_prio_level(unsigned int irq) 55 { 56 return intc_prio_level[irq]; 57 } 58 59 void intc_set_prio_level(unsigned int irq, unsigned int level) 60 { 61 unsigned long flags; 62 63 raw_spin_lock_irqsave(&intc_big_lock, flags); 64 intc_prio_level[irq] = level; 65 raw_spin_unlock_irqrestore(&intc_big_lock, flags); 66 } 67 68 static void intc_redirect_irq(struct irq_desc *desc) 69 { 70 generic_handle_irq((unsigned int)irq_desc_get_handler_data(desc)); 71 } 72 73 static void __init intc_register_irq(struct intc_desc *desc, 74 struct intc_desc_int *d, 75 intc_enum enum_id, 76 unsigned int irq) 77 { 78 struct intc_handle_int *hp; 79 struct irq_data *irq_data; 80 unsigned int data[2], primary; 81 unsigned long flags; 82 83 raw_spin_lock_irqsave(&intc_big_lock, flags); 84 radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq)); 85 raw_spin_unlock_irqrestore(&intc_big_lock, flags); 86 87 /* 88 * Prefer single interrupt source bitmap over other combinations: 89 * 90 * 1. bitmap, single interrupt source 91 * 2. priority, single interrupt source 92 * 3. bitmap, multiple interrupt sources (groups) 93 * 4. priority, multiple interrupt sources (groups) 94 */ 95 data[0] = intc_get_mask_handle(desc, d, enum_id, 0); 96 data[1] = intc_get_prio_handle(desc, d, enum_id, 0); 97 98 primary = 0; 99 if (!data[0] && data[1]) 100 primary = 1; 101 102 if (!data[0] && !data[1]) 103 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n", 104 irq, irq2evt(irq)); 105 106 data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1); 107 data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1); 108 109 if (!data[primary]) 110 primary ^= 1; 111 112 BUG_ON(!data[primary]); /* must have primary masking method */ 113 114 irq_data = irq_get_irq_data(irq); 115 116 disable_irq_nosync(irq); 117 irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq, 118 "level"); 119 irq_set_chip_data(irq, (void *)data[primary]); 120 121 /* 122 * set priority level 123 */ 124 intc_set_prio_level(irq, intc_get_dfl_prio_level()); 125 126 /* enable secondary masking method if present */ 127 if (data[!primary]) 128 _intc_enable(irq_data, data[!primary]); 129 130 /* add irq to d->prio list if priority is available */ 131 if (data[1]) { 132 hp = d->prio + d->nr_prio; 133 hp->irq = irq; 134 hp->handle = data[1]; 135 136 if (primary) { 137 /* 138 * only secondary priority should access registers, so 139 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority() 140 */ 141 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0); 142 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0); 143 } 144 d->nr_prio++; 145 } 146 147 /* add irq to d->sense list if sense is available */ 148 data[0] = intc_get_sense_handle(desc, d, enum_id); 149 if (data[0]) { 150 (d->sense + d->nr_sense)->irq = irq; 151 (d->sense + d->nr_sense)->handle = data[0]; 152 d->nr_sense++; 153 } 154 155 /* irq should be disabled by default */ 156 d->chip.irq_mask(irq_data); 157 158 intc_set_ack_handle(irq, desc, d, enum_id); 159 intc_set_dist_handle(irq, desc, d, enum_id); 160 161 activate_irq(irq); 162 } 163 164 static unsigned int __init save_reg(struct intc_desc_int *d, 165 unsigned int cnt, 166 unsigned long value, 167 unsigned int smp) 168 { 169 if (value) { 170 value = intc_phys_to_virt(d, value); 171 172 d->reg[cnt] = value; 173 #ifdef CONFIG_SMP 174 d->smp[cnt] = smp; 175 #endif 176 return 1; 177 } 178 179 return 0; 180 } 181 182 int __init register_intc_controller(struct intc_desc *desc) 183 { 184 unsigned int i, k, smp; 185 struct intc_hw_desc *hw = &desc->hw; 186 struct intc_desc_int *d; 187 struct resource *res; 188 189 pr_info("Registered controller '%s' with %u IRQs\n", 190 desc->name, hw->nr_vectors); 191 192 d = kzalloc(sizeof(*d), GFP_NOWAIT); 193 if (!d) 194 goto err0; 195 196 INIT_LIST_HEAD(&d->list); 197 list_add_tail(&d->list, &intc_list); 198 199 raw_spin_lock_init(&d->lock); 200 INIT_RADIX_TREE(&d->tree, GFP_ATOMIC); 201 202 d->index = nr_intc_controllers; 203 204 if (desc->num_resources) { 205 d->nr_windows = desc->num_resources; 206 d->window = kzalloc(d->nr_windows * sizeof(*d->window), 207 GFP_NOWAIT); 208 if (!d->window) 209 goto err1; 210 211 for (k = 0; k < d->nr_windows; k++) { 212 res = desc->resource + k; 213 WARN_ON(resource_type(res) != IORESOURCE_MEM); 214 d->window[k].phys = res->start; 215 d->window[k].size = resource_size(res); 216 d->window[k].virt = ioremap_nocache(res->start, 217 resource_size(res)); 218 if (!d->window[k].virt) 219 goto err2; 220 } 221 } 222 223 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; 224 #ifdef CONFIG_INTC_BALANCING 225 if (d->nr_reg) 226 d->nr_reg += hw->nr_mask_regs; 227 #endif 228 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0; 229 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0; 230 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0; 231 d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0; 232 233 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); 234 if (!d->reg) 235 goto err2; 236 237 #ifdef CONFIG_SMP 238 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT); 239 if (!d->smp) 240 goto err3; 241 #endif 242 k = 0; 243 244 if (hw->mask_regs) { 245 for (i = 0; i < hw->nr_mask_regs; i++) { 246 smp = IS_SMP(hw->mask_regs[i]); 247 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); 248 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); 249 #ifdef CONFIG_INTC_BALANCING 250 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0); 251 #endif 252 } 253 } 254 255 if (hw->prio_regs) { 256 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio), 257 GFP_NOWAIT); 258 if (!d->prio) 259 goto err4; 260 261 for (i = 0; i < hw->nr_prio_regs; i++) { 262 smp = IS_SMP(hw->prio_regs[i]); 263 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp); 264 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp); 265 } 266 267 sort(d->prio, hw->nr_prio_regs, sizeof(*d->prio), 268 intc_handle_int_cmp, NULL); 269 } 270 271 if (hw->sense_regs) { 272 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense), 273 GFP_NOWAIT); 274 if (!d->sense) 275 goto err5; 276 277 for (i = 0; i < hw->nr_sense_regs; i++) 278 k += save_reg(d, k, hw->sense_regs[i].reg, 0); 279 280 sort(d->sense, hw->nr_sense_regs, sizeof(*d->sense), 281 intc_handle_int_cmp, NULL); 282 } 283 284 if (hw->subgroups) 285 for (i = 0; i < hw->nr_subgroups; i++) 286 if (hw->subgroups[i].reg) 287 k+= save_reg(d, k, hw->subgroups[i].reg, 0); 288 289 memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip)); 290 d->chip.name = desc->name; 291 292 if (hw->ack_regs) 293 for (i = 0; i < hw->nr_ack_regs; i++) 294 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0); 295 else 296 d->chip.irq_mask_ack = d->chip.irq_disable; 297 298 /* disable bits matching force_disable before registering irqs */ 299 if (desc->force_disable) 300 intc_enable_disable_enum(desc, d, desc->force_disable, 0); 301 302 /* disable bits matching force_enable before registering irqs */ 303 if (desc->force_enable) 304 intc_enable_disable_enum(desc, d, desc->force_enable, 0); 305 306 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ 307 308 intc_irq_domain_init(d, hw); 309 310 /* register the vectors one by one */ 311 for (i = 0; i < hw->nr_vectors; i++) { 312 struct intc_vect *vect = hw->vectors + i; 313 unsigned int irq = evt2irq(vect->vect); 314 int res; 315 316 if (!vect->enum_id) 317 continue; 318 319 res = irq_create_identity_mapping(d->domain, irq); 320 if (unlikely(res)) { 321 if (res == -EEXIST) { 322 res = irq_domain_associate(d->domain, irq, irq); 323 if (unlikely(res)) { 324 pr_err("domain association failure\n"); 325 continue; 326 } 327 } else { 328 pr_err("can't identity map IRQ %d\n", irq); 329 continue; 330 } 331 } 332 333 intc_irq_xlate_set(irq, vect->enum_id, d); 334 intc_register_irq(desc, d, vect->enum_id, irq); 335 336 for (k = i + 1; k < hw->nr_vectors; k++) { 337 struct intc_vect *vect2 = hw->vectors + k; 338 unsigned int irq2 = evt2irq(vect2->vect); 339 340 if (vect->enum_id != vect2->enum_id) 341 continue; 342 343 /* 344 * In the case of multi-evt handling and sparse 345 * IRQ support, each vector still needs to have 346 * its own backing irq_desc. 347 */ 348 res = irq_create_identity_mapping(d->domain, irq2); 349 if (unlikely(res)) { 350 if (res == -EEXIST) { 351 res = irq_domain_associate(d->domain, 352 irq2, irq2); 353 if (unlikely(res)) { 354 pr_err("domain association " 355 "failure\n"); 356 continue; 357 } 358 } else { 359 pr_err("can't identity map IRQ %d\n", 360 irq); 361 continue; 362 } 363 } 364 365 vect2->enum_id = 0; 366 367 /* redirect this interrupts to the first one */ 368 irq_set_chip(irq2, &dummy_irq_chip); 369 irq_set_chained_handler_and_data(irq2, 370 intc_redirect_irq, 371 (void *)irq); 372 } 373 } 374 375 intc_subgroup_init(desc, d); 376 377 /* enable bits matching force_enable after registering irqs */ 378 if (desc->force_enable) 379 intc_enable_disable_enum(desc, d, desc->force_enable, 1); 380 381 d->skip_suspend = desc->skip_syscore_suspend; 382 383 nr_intc_controllers++; 384 385 return 0; 386 err5: 387 kfree(d->prio); 388 err4: 389 #ifdef CONFIG_SMP 390 kfree(d->smp); 391 err3: 392 #endif 393 kfree(d->reg); 394 err2: 395 for (k = 0; k < d->nr_windows; k++) 396 if (d->window[k].virt) 397 iounmap(d->window[k].virt); 398 399 kfree(d->window); 400 err1: 401 kfree(d); 402 err0: 403 pr_err("unable to allocate INTC memory\n"); 404 405 return -ENOMEM; 406 } 407 408 static int intc_suspend(void) 409 { 410 struct intc_desc_int *d; 411 412 list_for_each_entry(d, &intc_list, list) { 413 int irq; 414 415 if (d->skip_suspend) 416 continue; 417 418 /* enable wakeup irqs belonging to this intc controller */ 419 for_each_active_irq(irq) { 420 struct irq_data *data; 421 struct irq_chip *chip; 422 423 data = irq_get_irq_data(irq); 424 chip = irq_data_get_irq_chip(data); 425 if (chip != &d->chip) 426 continue; 427 if (irqd_is_wakeup_set(data)) 428 chip->irq_enable(data); 429 } 430 } 431 return 0; 432 } 433 434 static void intc_resume(void) 435 { 436 struct intc_desc_int *d; 437 438 list_for_each_entry(d, &intc_list, list) { 439 int irq; 440 441 if (d->skip_suspend) 442 continue; 443 444 for_each_active_irq(irq) { 445 struct irq_data *data; 446 struct irq_chip *chip; 447 448 data = irq_get_irq_data(irq); 449 chip = irq_data_get_irq_chip(data); 450 /* 451 * This will catch the redirect and VIRQ cases 452 * due to the dummy_irq_chip being inserted. 453 */ 454 if (chip != &d->chip) 455 continue; 456 if (irqd_irq_disabled(data)) 457 chip->irq_disable(data); 458 else 459 chip->irq_enable(data); 460 } 461 } 462 } 463 464 struct syscore_ops intc_syscore_ops = { 465 .suspend = intc_suspend, 466 .resume = intc_resume, 467 }; 468 469 struct bus_type intc_subsys = { 470 .name = "intc", 471 .dev_name = "intc", 472 }; 473 474 static ssize_t 475 show_intc_name(struct device *dev, struct device_attribute *attr, char *buf) 476 { 477 struct intc_desc_int *d; 478 479 d = container_of(dev, struct intc_desc_int, dev); 480 481 return sprintf(buf, "%s\n", d->chip.name); 482 } 483 484 static DEVICE_ATTR(name, S_IRUGO, show_intc_name, NULL); 485 486 static int __init register_intc_devs(void) 487 { 488 struct intc_desc_int *d; 489 int error; 490 491 register_syscore_ops(&intc_syscore_ops); 492 493 error = subsys_system_register(&intc_subsys, NULL); 494 if (!error) { 495 list_for_each_entry(d, &intc_list, list) { 496 d->dev.id = d->index; 497 d->dev.bus = &intc_subsys; 498 error = device_register(&d->dev); 499 if (error == 0) 500 error = device_create_file(&d->dev, 501 &dev_attr_name); 502 if (error) 503 break; 504 } 505 } 506 507 if (error) 508 pr_err("device registration error\n"); 509 510 return error; 511 } 512 device_initcall(register_intc_devs); 513