1 /* 2 * Shared interrupt handling code for IPR and INTC2 types of IRQs. 3 * 4 * Copyright (C) 2007, 2008 Magnus Damm 5 * Copyright (C) 2009, 2010 Paul Mundt 6 * 7 * Based on intc2.c and ipr.c 8 * 9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi 10 * Copyright (C) 2000 Kazumoto Kojima 11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) 12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> 13 * Copyright (C) 2005, 2006 Paul Mundt 14 * 15 * This file is subject to the terms and conditions of the GNU General Public 16 * License. See the file "COPYING" in the main directory of this archive 17 * for more details. 18 */ 19 #define pr_fmt(fmt) "intc: " fmt 20 21 #include <linux/init.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/slab.h> 25 #include <linux/stat.h> 26 #include <linux/interrupt.h> 27 #include <linux/sh_intc.h> 28 #include <linux/device.h> 29 #include <linux/syscore_ops.h> 30 #include <linux/list.h> 31 #include <linux/spinlock.h> 32 #include <linux/radix-tree.h> 33 #include <linux/export.h> 34 #include "internals.h" 35 36 LIST_HEAD(intc_list); 37 DEFINE_RAW_SPINLOCK(intc_big_lock); 38 unsigned int nr_intc_controllers; 39 40 /* 41 * Default priority level 42 * - this needs to be at least 2 for 5-bit priorities on 7780 43 */ 44 static unsigned int default_prio_level = 2; /* 2 - 16 */ 45 static unsigned int intc_prio_level[INTC_NR_IRQS]; /* for now */ 46 47 unsigned int intc_get_dfl_prio_level(void) 48 { 49 return default_prio_level; 50 } 51 52 unsigned int intc_get_prio_level(unsigned int irq) 53 { 54 return intc_prio_level[irq]; 55 } 56 57 void intc_set_prio_level(unsigned int irq, unsigned int level) 58 { 59 unsigned long flags; 60 61 raw_spin_lock_irqsave(&intc_big_lock, flags); 62 intc_prio_level[irq] = level; 63 raw_spin_unlock_irqrestore(&intc_big_lock, flags); 64 } 65 66 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc) 67 { 68 generic_handle_irq((unsigned int)irq_get_handler_data(irq)); 69 } 70 71 static void __init intc_register_irq(struct intc_desc *desc, 72 struct intc_desc_int *d, 73 intc_enum enum_id, 74 unsigned int irq) 75 { 76 struct intc_handle_int *hp; 77 struct irq_data *irq_data; 78 unsigned int data[2], primary; 79 unsigned long flags; 80 81 /* 82 * Register the IRQ position with the global IRQ map, then insert 83 * it in to the radix tree. 84 */ 85 irq_reserve_irq(irq); 86 87 raw_spin_lock_irqsave(&intc_big_lock, flags); 88 radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq)); 89 raw_spin_unlock_irqrestore(&intc_big_lock, flags); 90 91 /* 92 * Prefer single interrupt source bitmap over other combinations: 93 * 94 * 1. bitmap, single interrupt source 95 * 2. priority, single interrupt source 96 * 3. bitmap, multiple interrupt sources (groups) 97 * 4. priority, multiple interrupt sources (groups) 98 */ 99 data[0] = intc_get_mask_handle(desc, d, enum_id, 0); 100 data[1] = intc_get_prio_handle(desc, d, enum_id, 0); 101 102 primary = 0; 103 if (!data[0] && data[1]) 104 primary = 1; 105 106 if (!data[0] && !data[1]) 107 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n", 108 irq, irq2evt(irq)); 109 110 data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1); 111 data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1); 112 113 if (!data[primary]) 114 primary ^= 1; 115 116 BUG_ON(!data[primary]); /* must have primary masking method */ 117 118 irq_data = irq_get_irq_data(irq); 119 120 disable_irq_nosync(irq); 121 irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq, 122 "level"); 123 irq_set_chip_data(irq, (void *)data[primary]); 124 125 /* 126 * set priority level 127 */ 128 intc_set_prio_level(irq, intc_get_dfl_prio_level()); 129 130 /* enable secondary masking method if present */ 131 if (data[!primary]) 132 _intc_enable(irq_data, data[!primary]); 133 134 /* add irq to d->prio list if priority is available */ 135 if (data[1]) { 136 hp = d->prio + d->nr_prio; 137 hp->irq = irq; 138 hp->handle = data[1]; 139 140 if (primary) { 141 /* 142 * only secondary priority should access registers, so 143 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority() 144 */ 145 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0); 146 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0); 147 } 148 d->nr_prio++; 149 } 150 151 /* add irq to d->sense list if sense is available */ 152 data[0] = intc_get_sense_handle(desc, d, enum_id); 153 if (data[0]) { 154 (d->sense + d->nr_sense)->irq = irq; 155 (d->sense + d->nr_sense)->handle = data[0]; 156 d->nr_sense++; 157 } 158 159 /* irq should be disabled by default */ 160 d->chip.irq_mask(irq_data); 161 162 intc_set_ack_handle(irq, desc, d, enum_id); 163 intc_set_dist_handle(irq, desc, d, enum_id); 164 165 activate_irq(irq); 166 } 167 168 static unsigned int __init save_reg(struct intc_desc_int *d, 169 unsigned int cnt, 170 unsigned long value, 171 unsigned int smp) 172 { 173 if (value) { 174 value = intc_phys_to_virt(d, value); 175 176 d->reg[cnt] = value; 177 #ifdef CONFIG_SMP 178 d->smp[cnt] = smp; 179 #endif 180 return 1; 181 } 182 183 return 0; 184 } 185 186 int __init register_intc_controller(struct intc_desc *desc) 187 { 188 unsigned int i, k, smp; 189 struct intc_hw_desc *hw = &desc->hw; 190 struct intc_desc_int *d; 191 struct resource *res; 192 193 pr_info("Registered controller '%s' with %u IRQs\n", 194 desc->name, hw->nr_vectors); 195 196 d = kzalloc(sizeof(*d), GFP_NOWAIT); 197 if (!d) 198 goto err0; 199 200 INIT_LIST_HEAD(&d->list); 201 list_add_tail(&d->list, &intc_list); 202 203 raw_spin_lock_init(&d->lock); 204 INIT_RADIX_TREE(&d->tree, GFP_ATOMIC); 205 206 d->index = nr_intc_controllers; 207 208 if (desc->num_resources) { 209 d->nr_windows = desc->num_resources; 210 d->window = kzalloc(d->nr_windows * sizeof(*d->window), 211 GFP_NOWAIT); 212 if (!d->window) 213 goto err1; 214 215 for (k = 0; k < d->nr_windows; k++) { 216 res = desc->resource + k; 217 WARN_ON(resource_type(res) != IORESOURCE_MEM); 218 d->window[k].phys = res->start; 219 d->window[k].size = resource_size(res); 220 d->window[k].virt = ioremap_nocache(res->start, 221 resource_size(res)); 222 if (!d->window[k].virt) 223 goto err2; 224 } 225 } 226 227 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; 228 #ifdef CONFIG_INTC_BALANCING 229 if (d->nr_reg) 230 d->nr_reg += hw->nr_mask_regs; 231 #endif 232 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0; 233 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0; 234 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0; 235 d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0; 236 237 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); 238 if (!d->reg) 239 goto err2; 240 241 #ifdef CONFIG_SMP 242 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT); 243 if (!d->smp) 244 goto err3; 245 #endif 246 k = 0; 247 248 if (hw->mask_regs) { 249 for (i = 0; i < hw->nr_mask_regs; i++) { 250 smp = IS_SMP(hw->mask_regs[i]); 251 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); 252 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); 253 #ifdef CONFIG_INTC_BALANCING 254 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0); 255 #endif 256 } 257 } 258 259 if (hw->prio_regs) { 260 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio), 261 GFP_NOWAIT); 262 if (!d->prio) 263 goto err4; 264 265 for (i = 0; i < hw->nr_prio_regs; i++) { 266 smp = IS_SMP(hw->prio_regs[i]); 267 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp); 268 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp); 269 } 270 } 271 272 if (hw->sense_regs) { 273 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense), 274 GFP_NOWAIT); 275 if (!d->sense) 276 goto err5; 277 278 for (i = 0; i < hw->nr_sense_regs; i++) 279 k += save_reg(d, k, hw->sense_regs[i].reg, 0); 280 } 281 282 if (hw->subgroups) 283 for (i = 0; i < hw->nr_subgroups; i++) 284 if (hw->subgroups[i].reg) 285 k+= save_reg(d, k, hw->subgroups[i].reg, 0); 286 287 memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip)); 288 d->chip.name = desc->name; 289 290 if (hw->ack_regs) 291 for (i = 0; i < hw->nr_ack_regs; i++) 292 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0); 293 else 294 d->chip.irq_mask_ack = d->chip.irq_disable; 295 296 /* disable bits matching force_disable before registering irqs */ 297 if (desc->force_disable) 298 intc_enable_disable_enum(desc, d, desc->force_disable, 0); 299 300 /* disable bits matching force_enable before registering irqs */ 301 if (desc->force_enable) 302 intc_enable_disable_enum(desc, d, desc->force_enable, 0); 303 304 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ 305 306 /* register the vectors one by one */ 307 for (i = 0; i < hw->nr_vectors; i++) { 308 struct intc_vect *vect = hw->vectors + i; 309 unsigned int irq = evt2irq(vect->vect); 310 int res; 311 312 if (!vect->enum_id) 313 continue; 314 315 res = irq_alloc_desc_at(irq, numa_node_id()); 316 if (res != irq && res != -EEXIST) { 317 pr_err("can't get irq_desc for %d\n", irq); 318 continue; 319 } 320 321 intc_irq_xlate_set(irq, vect->enum_id, d); 322 intc_register_irq(desc, d, vect->enum_id, irq); 323 324 for (k = i + 1; k < hw->nr_vectors; k++) { 325 struct intc_vect *vect2 = hw->vectors + k; 326 unsigned int irq2 = evt2irq(vect2->vect); 327 328 if (vect->enum_id != vect2->enum_id) 329 continue; 330 331 /* 332 * In the case of multi-evt handling and sparse 333 * IRQ support, each vector still needs to have 334 * its own backing irq_desc. 335 */ 336 res = irq_alloc_desc_at(irq2, numa_node_id()); 337 if (res != irq2 && res != -EEXIST) { 338 pr_err("can't get irq_desc for %d\n", irq2); 339 continue; 340 } 341 342 vect2->enum_id = 0; 343 344 /* redirect this interrupts to the first one */ 345 irq_set_chip(irq2, &dummy_irq_chip); 346 irq_set_chained_handler(irq2, intc_redirect_irq); 347 irq_set_handler_data(irq2, (void *)irq); 348 } 349 } 350 351 intc_subgroup_init(desc, d); 352 353 /* enable bits matching force_enable after registering irqs */ 354 if (desc->force_enable) 355 intc_enable_disable_enum(desc, d, desc->force_enable, 1); 356 357 d->skip_suspend = desc->skip_syscore_suspend; 358 359 nr_intc_controllers++; 360 361 return 0; 362 err5: 363 kfree(d->prio); 364 err4: 365 #ifdef CONFIG_SMP 366 kfree(d->smp); 367 err3: 368 #endif 369 kfree(d->reg); 370 err2: 371 for (k = 0; k < d->nr_windows; k++) 372 if (d->window[k].virt) 373 iounmap(d->window[k].virt); 374 375 kfree(d->window); 376 err1: 377 kfree(d); 378 err0: 379 pr_err("unable to allocate INTC memory\n"); 380 381 return -ENOMEM; 382 } 383 384 static int intc_suspend(void) 385 { 386 struct intc_desc_int *d; 387 388 list_for_each_entry(d, &intc_list, list) { 389 int irq; 390 391 if (d->skip_suspend) 392 continue; 393 394 /* enable wakeup irqs belonging to this intc controller */ 395 for_each_active_irq(irq) { 396 struct irq_data *data; 397 struct irq_chip *chip; 398 399 data = irq_get_irq_data(irq); 400 chip = irq_data_get_irq_chip(data); 401 if (chip != &d->chip) 402 continue; 403 if (irqd_is_wakeup_set(data)) 404 chip->irq_enable(data); 405 } 406 } 407 return 0; 408 } 409 410 static void intc_resume(void) 411 { 412 struct intc_desc_int *d; 413 414 list_for_each_entry(d, &intc_list, list) { 415 int irq; 416 417 if (d->skip_suspend) 418 continue; 419 420 for_each_active_irq(irq) { 421 struct irq_data *data; 422 struct irq_chip *chip; 423 424 data = irq_get_irq_data(irq); 425 chip = irq_data_get_irq_chip(data); 426 /* 427 * This will catch the redirect and VIRQ cases 428 * due to the dummy_irq_chip being inserted. 429 */ 430 if (chip != &d->chip) 431 continue; 432 if (irqd_irq_disabled(data)) 433 chip->irq_disable(data); 434 else 435 chip->irq_enable(data); 436 } 437 } 438 } 439 440 struct syscore_ops intc_syscore_ops = { 441 .suspend = intc_suspend, 442 .resume = intc_resume, 443 }; 444 445 struct bus_type intc_subsys = { 446 .name = "intc", 447 .dev_name = "intc", 448 }; 449 450 static ssize_t 451 show_intc_name(struct device *dev, struct device_attribute *attr, char *buf) 452 { 453 struct intc_desc_int *d; 454 455 d = container_of(dev, struct intc_desc_int, dev); 456 457 return sprintf(buf, "%s\n", d->chip.name); 458 } 459 460 static DEVICE_ATTR(name, S_IRUGO, show_intc_name, NULL); 461 462 static int __init register_intc_devs(void) 463 { 464 struct intc_desc_int *d; 465 int error; 466 467 register_syscore_ops(&intc_syscore_ops); 468 469 error = subsys_system_register(&intc_subsys, NULL); 470 if (!error) { 471 list_for_each_entry(d, &intc_list, list) { 472 d->dev.id = d->index; 473 d->dev.bus = &intc_subsys; 474 error = device_register(&d->dev); 475 if (error == 0) 476 error = device_create_file(&d->dev, 477 &dev_attr_name); 478 if (error) 479 break; 480 } 481 } 482 483 if (error) 484 pr_err("device registration error\n"); 485 486 return error; 487 } 488 device_initcall(register_intc_devs); 489