1 /* 2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family 3 * of PCI-SCSI IO processors. 4 * 5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 6 * Copyright (c) 2003-2005 Matthew Wilcox <matthew@wil.cx> 7 * 8 * This driver is derived from the Linux sym53c8xx driver. 9 * Copyright (C) 1998-2000 Gerard Roudier 10 * 11 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 12 * a port of the FreeBSD ncr driver to Linux-1.2.13. 13 * 14 * The original ncr driver has been written for 386bsd and FreeBSD by 15 * Wolfgang Stanglmeier <wolf@cologne.de> 16 * Stefan Esser <se@mi.Uni-Koeln.de> 17 * Copyright (C) 1994 Wolfgang Stanglmeier 18 * 19 * Other major contributions: 20 * 21 * NVRAM detection and reading. 22 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 23 * 24 *----------------------------------------------------------------------------- 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 */ 40 41 #include <linux/slab.h> 42 #include <asm/param.h> /* for timeouts in units of HZ */ 43 44 #include "sym_glue.h" 45 #include "sym_nvram.h" 46 47 #if 0 48 #define SYM_DEBUG_GENERIC_SUPPORT 49 #endif 50 51 /* 52 * Needed function prototypes. 53 */ 54 static void sym_int_ma (struct sym_hcb *np); 55 static void sym_int_sir(struct sym_hcb *); 56 static struct sym_ccb *sym_alloc_ccb(struct sym_hcb *np); 57 static struct sym_ccb *sym_ccb_from_dsa(struct sym_hcb *np, u32 dsa); 58 static void sym_alloc_lcb_tags (struct sym_hcb *np, u_char tn, u_char ln); 59 static void sym_complete_error (struct sym_hcb *np, struct sym_ccb *cp); 60 static void sym_complete_ok (struct sym_hcb *np, struct sym_ccb *cp); 61 static int sym_compute_residual(struct sym_hcb *np, struct sym_ccb *cp); 62 63 /* 64 * Print a buffer in hexadecimal format with a ".\n" at end. 65 */ 66 static void sym_printl_hex(u_char *p, int n) 67 { 68 while (n-- > 0) 69 printf (" %x", *p++); 70 printf (".\n"); 71 } 72 73 static void sym_print_msg(struct sym_ccb *cp, char *label, u_char *msg) 74 { 75 if (label) 76 sym_print_addr(cp->cmd, "%s: ", label); 77 else 78 sym_print_addr(cp->cmd, ""); 79 80 spi_print_msg(msg); 81 printf("\n"); 82 } 83 84 static void sym_print_nego_msg(struct sym_hcb *np, int target, char *label, u_char *msg) 85 { 86 struct sym_tcb *tp = &np->target[target]; 87 dev_info(&tp->starget->dev, "%s: ", label); 88 89 spi_print_msg(msg); 90 printf("\n"); 91 } 92 93 /* 94 * Print something that tells about extended errors. 95 */ 96 void sym_print_xerr(struct scsi_cmnd *cmd, int x_status) 97 { 98 if (x_status & XE_PARITY_ERR) { 99 sym_print_addr(cmd, "unrecovered SCSI parity error.\n"); 100 } 101 if (x_status & XE_EXTRA_DATA) { 102 sym_print_addr(cmd, "extraneous data discarded.\n"); 103 } 104 if (x_status & XE_BAD_PHASE) { 105 sym_print_addr(cmd, "illegal scsi phase (4/5).\n"); 106 } 107 if (x_status & XE_SODL_UNRUN) { 108 sym_print_addr(cmd, "ODD transfer in DATA OUT phase.\n"); 109 } 110 if (x_status & XE_SWIDE_OVRUN) { 111 sym_print_addr(cmd, "ODD transfer in DATA IN phase.\n"); 112 } 113 } 114 115 /* 116 * Return a string for SCSI BUS mode. 117 */ 118 static char *sym_scsi_bus_mode(int mode) 119 { 120 switch(mode) { 121 case SMODE_HVD: return "HVD"; 122 case SMODE_SE: return "SE"; 123 case SMODE_LVD: return "LVD"; 124 } 125 return "??"; 126 } 127 128 /* 129 * Soft reset the chip. 130 * 131 * Raising SRST when the chip is running may cause 132 * problems on dual function chips (see below). 133 * On the other hand, LVD devices need some delay 134 * to settle and report actual BUS mode in STEST4. 135 */ 136 static void sym_chip_reset (struct sym_hcb *np) 137 { 138 OUTB(np, nc_istat, SRST); 139 INB(np, nc_mbox1); 140 udelay(10); 141 OUTB(np, nc_istat, 0); 142 INB(np, nc_mbox1); 143 udelay(2000); /* For BUS MODE to settle */ 144 } 145 146 /* 147 * Really soft reset the chip.:) 148 * 149 * Some 896 and 876 chip revisions may hang-up if we set 150 * the SRST (soft reset) bit at the wrong time when SCRIPTS 151 * are running. 152 * So, we need to abort the current operation prior to 153 * soft resetting the chip. 154 */ 155 static void sym_soft_reset (struct sym_hcb *np) 156 { 157 u_char istat = 0; 158 int i; 159 160 if (!(np->features & FE_ISTAT1) || !(INB(np, nc_istat1) & SCRUN)) 161 goto do_chip_reset; 162 163 OUTB(np, nc_istat, CABRT); 164 for (i = 100000 ; i ; --i) { 165 istat = INB(np, nc_istat); 166 if (istat & SIP) { 167 INW(np, nc_sist); 168 } 169 else if (istat & DIP) { 170 if (INB(np, nc_dstat) & ABRT) 171 break; 172 } 173 udelay(5); 174 } 175 OUTB(np, nc_istat, 0); 176 if (!i) 177 printf("%s: unable to abort current chip operation, " 178 "ISTAT=0x%02x.\n", sym_name(np), istat); 179 do_chip_reset: 180 sym_chip_reset(np); 181 } 182 183 /* 184 * Start reset process. 185 * 186 * The interrupt handler will reinitialize the chip. 187 */ 188 static void sym_start_reset(struct sym_hcb *np) 189 { 190 sym_reset_scsi_bus(np, 1); 191 } 192 193 int sym_reset_scsi_bus(struct sym_hcb *np, int enab_int) 194 { 195 u32 term; 196 int retv = 0; 197 198 sym_soft_reset(np); /* Soft reset the chip */ 199 if (enab_int) 200 OUTW(np, nc_sien, RST); 201 /* 202 * Enable Tolerant, reset IRQD if present and 203 * properly set IRQ mode, prior to resetting the bus. 204 */ 205 OUTB(np, nc_stest3, TE); 206 OUTB(np, nc_dcntl, (np->rv_dcntl & IRQM)); 207 OUTB(np, nc_scntl1, CRST); 208 INB(np, nc_mbox1); 209 udelay(200); 210 211 if (!SYM_SETUP_SCSI_BUS_CHECK) 212 goto out; 213 /* 214 * Check for no terminators or SCSI bus shorts to ground. 215 * Read SCSI data bus, data parity bits and control signals. 216 * We are expecting RESET to be TRUE and other signals to be 217 * FALSE. 218 */ 219 term = INB(np, nc_sstat0); 220 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */ 221 term |= ((INB(np, nc_sstat2) & 0x01) << 26) | /* sdp1 */ 222 ((INW(np, nc_sbdl) & 0xff) << 9) | /* d7-0 */ 223 ((INW(np, nc_sbdl) & 0xff00) << 10) | /* d15-8 */ 224 INB(np, nc_sbcl); /* req ack bsy sel atn msg cd io */ 225 226 if (!np->maxwide) 227 term &= 0x3ffff; 228 229 if (term != (2<<7)) { 230 printf("%s: suspicious SCSI data while resetting the BUS.\n", 231 sym_name(np)); 232 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = " 233 "0x%lx, expecting 0x%lx\n", 234 sym_name(np), 235 (np->features & FE_WIDE) ? "dp1,d15-8," : "", 236 (u_long)term, (u_long)(2<<7)); 237 if (SYM_SETUP_SCSI_BUS_CHECK == 1) 238 retv = 1; 239 } 240 out: 241 OUTB(np, nc_scntl1, 0); 242 return retv; 243 } 244 245 /* 246 * Select SCSI clock frequency 247 */ 248 static void sym_selectclock(struct sym_hcb *np, u_char scntl3) 249 { 250 /* 251 * If multiplier not present or not selected, leave here. 252 */ 253 if (np->multiplier <= 1) { 254 OUTB(np, nc_scntl3, scntl3); 255 return; 256 } 257 258 if (sym_verbose >= 2) 259 printf ("%s: enabling clock multiplier\n", sym_name(np)); 260 261 OUTB(np, nc_stest1, DBLEN); /* Enable clock multiplier */ 262 /* 263 * Wait for the LCKFRQ bit to be set if supported by the chip. 264 * Otherwise wait 50 micro-seconds (at least). 265 */ 266 if (np->features & FE_LCKFRQ) { 267 int i = 20; 268 while (!(INB(np, nc_stest4) & LCKFRQ) && --i > 0) 269 udelay(20); 270 if (!i) 271 printf("%s: the chip cannot lock the frequency\n", 272 sym_name(np)); 273 } else { 274 INB(np, nc_mbox1); 275 udelay(50+10); 276 } 277 OUTB(np, nc_stest3, HSC); /* Halt the scsi clock */ 278 OUTB(np, nc_scntl3, scntl3); 279 OUTB(np, nc_stest1, (DBLEN|DBLSEL));/* Select clock multiplier */ 280 OUTB(np, nc_stest3, 0x00); /* Restart scsi clock */ 281 } 282 283 284 /* 285 * Determine the chip's clock frequency. 286 * 287 * This is essential for the negotiation of the synchronous 288 * transfer rate. 289 * 290 * Note: we have to return the correct value. 291 * THERE IS NO SAFE DEFAULT VALUE. 292 * 293 * Most NCR/SYMBIOS boards are delivered with a 40 Mhz clock. 294 * 53C860 and 53C875 rev. 1 support fast20 transfers but 295 * do not have a clock doubler and so are provided with a 296 * 80 MHz clock. All other fast20 boards incorporate a doubler 297 * and so should be delivered with a 40 MHz clock. 298 * The recent fast40 chips (895/896/895A/1010) use a 40 Mhz base 299 * clock and provide a clock quadrupler (160 Mhz). 300 */ 301 302 /* 303 * calculate SCSI clock frequency (in KHz) 304 */ 305 static unsigned getfreq (struct sym_hcb *np, int gen) 306 { 307 unsigned int ms = 0; 308 unsigned int f; 309 310 /* 311 * Measure GEN timer delay in order 312 * to calculate SCSI clock frequency 313 * 314 * This code will never execute too 315 * many loop iterations (if DELAY is 316 * reasonably correct). It could get 317 * too low a delay (too high a freq.) 318 * if the CPU is slow executing the 319 * loop for some reason (an NMI, for 320 * example). For this reason we will 321 * if multiple measurements are to be 322 * performed trust the higher delay 323 * (lower frequency returned). 324 */ 325 OUTW(np, nc_sien, 0); /* mask all scsi interrupts */ 326 INW(np, nc_sist); /* clear pending scsi interrupt */ 327 OUTB(np, nc_dien, 0); /* mask all dma interrupts */ 328 INW(np, nc_sist); /* another one, just to be sure :) */ 329 /* 330 * The C1010-33 core does not report GEN in SIST, 331 * if this interrupt is masked in SIEN. 332 * I don't know yet if the C1010-66 behaves the same way. 333 */ 334 if (np->features & FE_C10) { 335 OUTW(np, nc_sien, GEN); 336 OUTB(np, nc_istat1, SIRQD); 337 } 338 OUTB(np, nc_scntl3, 4); /* set pre-scaler to divide by 3 */ 339 OUTB(np, nc_stime1, 0); /* disable general purpose timer */ 340 OUTB(np, nc_stime1, gen); /* set to nominal delay of 1<<gen * 125us */ 341 while (!(INW(np, nc_sist) & GEN) && ms++ < 100000) 342 udelay(1000/4); /* count in 1/4 of ms */ 343 OUTB(np, nc_stime1, 0); /* disable general purpose timer */ 344 /* 345 * Undo C1010-33 specific settings. 346 */ 347 if (np->features & FE_C10) { 348 OUTW(np, nc_sien, 0); 349 OUTB(np, nc_istat1, 0); 350 } 351 /* 352 * set prescaler to divide by whatever 0 means 353 * 0 ought to choose divide by 2, but appears 354 * to set divide by 3.5 mode in my 53c810 ... 355 */ 356 OUTB(np, nc_scntl3, 0); 357 358 /* 359 * adjust for prescaler, and convert into KHz 360 */ 361 f = ms ? ((1 << gen) * (4340*4)) / ms : 0; 362 363 /* 364 * The C1010-33 result is biased by a factor 365 * of 2/3 compared to earlier chips. 366 */ 367 if (np->features & FE_C10) 368 f = (f * 2) / 3; 369 370 if (sym_verbose >= 2) 371 printf ("%s: Delay (GEN=%d): %u msec, %u KHz\n", 372 sym_name(np), gen, ms/4, f); 373 374 return f; 375 } 376 377 static unsigned sym_getfreq (struct sym_hcb *np) 378 { 379 u_int f1, f2; 380 int gen = 8; 381 382 getfreq (np, gen); /* throw away first result */ 383 f1 = getfreq (np, gen); 384 f2 = getfreq (np, gen); 385 if (f1 > f2) f1 = f2; /* trust lower result */ 386 return f1; 387 } 388 389 /* 390 * Get/probe chip SCSI clock frequency 391 */ 392 static void sym_getclock (struct sym_hcb *np, int mult) 393 { 394 unsigned char scntl3 = np->sv_scntl3; 395 unsigned char stest1 = np->sv_stest1; 396 unsigned f1; 397 398 np->multiplier = 1; 399 f1 = 40000; 400 /* 401 * True with 875/895/896/895A with clock multiplier selected 402 */ 403 if (mult > 1 && (stest1 & (DBLEN+DBLSEL)) == DBLEN+DBLSEL) { 404 if (sym_verbose >= 2) 405 printf ("%s: clock multiplier found\n", sym_name(np)); 406 np->multiplier = mult; 407 } 408 409 /* 410 * If multiplier not found or scntl3 not 7,5,3, 411 * reset chip and get frequency from general purpose timer. 412 * Otherwise trust scntl3 BIOS setting. 413 */ 414 if (np->multiplier != mult || (scntl3 & 7) < 3 || !(scntl3 & 1)) { 415 OUTB(np, nc_stest1, 0); /* make sure doubler is OFF */ 416 f1 = sym_getfreq (np); 417 418 if (sym_verbose) 419 printf ("%s: chip clock is %uKHz\n", sym_name(np), f1); 420 421 if (f1 < 45000) f1 = 40000; 422 else if (f1 < 55000) f1 = 50000; 423 else f1 = 80000; 424 425 if (f1 < 80000 && mult > 1) { 426 if (sym_verbose >= 2) 427 printf ("%s: clock multiplier assumed\n", 428 sym_name(np)); 429 np->multiplier = mult; 430 } 431 } else { 432 if ((scntl3 & 7) == 3) f1 = 40000; 433 else if ((scntl3 & 7) == 5) f1 = 80000; 434 else f1 = 160000; 435 436 f1 /= np->multiplier; 437 } 438 439 /* 440 * Compute controller synchronous parameters. 441 */ 442 f1 *= np->multiplier; 443 np->clock_khz = f1; 444 } 445 446 /* 447 * Get/probe PCI clock frequency 448 */ 449 static int sym_getpciclock (struct sym_hcb *np) 450 { 451 int f = 0; 452 453 /* 454 * For now, we only need to know about the actual 455 * PCI BUS clock frequency for C1010-66 chips. 456 */ 457 #if 1 458 if (np->features & FE_66MHZ) { 459 #else 460 if (1) { 461 #endif 462 OUTB(np, nc_stest1, SCLK); /* Use the PCI clock as SCSI clock */ 463 f = sym_getfreq(np); 464 OUTB(np, nc_stest1, 0); 465 } 466 np->pciclk_khz = f; 467 468 return f; 469 } 470 471 /* 472 * SYMBIOS chip clock divisor table. 473 * 474 * Divisors are multiplied by 10,000,000 in order to make 475 * calculations more simple. 476 */ 477 #define _5M 5000000 478 static const u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M}; 479 480 /* 481 * Get clock factor and sync divisor for a given 482 * synchronous factor period. 483 */ 484 static int 485 sym_getsync(struct sym_hcb *np, u_char dt, u_char sfac, u_char *divp, u_char *fakp) 486 { 487 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */ 488 int div = np->clock_divn; /* Number of divisors supported */ 489 u32 fak; /* Sync factor in sxfer */ 490 u32 per; /* Period in tenths of ns */ 491 u32 kpc; /* (per * clk) */ 492 int ret; 493 494 /* 495 * Compute the synchronous period in tenths of nano-seconds 496 */ 497 if (dt && sfac <= 9) per = 125; 498 else if (sfac <= 10) per = 250; 499 else if (sfac == 11) per = 303; 500 else if (sfac == 12) per = 500; 501 else per = 40 * sfac; 502 ret = per; 503 504 kpc = per * clk; 505 if (dt) 506 kpc <<= 1; 507 508 /* 509 * For earliest C10 revision 0, we cannot use extra 510 * clocks for the setting of the SCSI clocking. 511 * Note that this limits the lowest sync data transfer 512 * to 5 Mega-transfers per second and may result in 513 * using higher clock divisors. 514 */ 515 #if 1 516 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) { 517 /* 518 * Look for the lowest clock divisor that allows an 519 * output speed not faster than the period. 520 */ 521 while (div > 0) { 522 --div; 523 if (kpc > (div_10M[div] << 2)) { 524 ++div; 525 break; 526 } 527 } 528 fak = 0; /* No extra clocks */ 529 if (div == np->clock_divn) { /* Are we too fast ? */ 530 ret = -1; 531 } 532 *divp = div; 533 *fakp = fak; 534 return ret; 535 } 536 #endif 537 538 /* 539 * Look for the greatest clock divisor that allows an 540 * input speed faster than the period. 541 */ 542 while (div-- > 0) 543 if (kpc >= (div_10M[div] << 2)) break; 544 545 /* 546 * Calculate the lowest clock factor that allows an output 547 * speed not faster than the period, and the max output speed. 548 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT. 549 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT. 550 */ 551 if (dt) { 552 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2; 553 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */ 554 } else { 555 fak = (kpc - 1) / div_10M[div] + 1 - 4; 556 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */ 557 } 558 559 /* 560 * Check against our hardware limits, or bugs :). 561 */ 562 if (fak > 2) { 563 fak = 2; 564 ret = -1; 565 } 566 567 /* 568 * Compute and return sync parameters. 569 */ 570 *divp = div; 571 *fakp = fak; 572 573 return ret; 574 } 575 576 /* 577 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64, 578 * 128 transfers. All chips support at least 16 transfers 579 * bursts. The 825A, 875 and 895 chips support bursts of up 580 * to 128 transfers and the 895A and 896 support bursts of up 581 * to 64 transfers. All other chips support up to 16 582 * transfers bursts. 583 * 584 * For PCI 32 bit data transfers each transfer is a DWORD. 585 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers. 586 * 587 * We use log base 2 (burst length) as internal code, with 588 * value 0 meaning "burst disabled". 589 */ 590 591 /* 592 * Burst length from burst code. 593 */ 594 #define burst_length(bc) (!(bc))? 0 : 1 << (bc) 595 596 /* 597 * Burst code from io register bits. 598 */ 599 #define burst_code(dmode, ctest4, ctest5) \ 600 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1 601 602 /* 603 * Set initial io register bits from burst code. 604 */ 605 static __inline void sym_init_burst(struct sym_hcb *np, u_char bc) 606 { 607 np->rv_ctest4 &= ~0x80; 608 np->rv_dmode &= ~(0x3 << 6); 609 np->rv_ctest5 &= ~0x4; 610 611 if (!bc) { 612 np->rv_ctest4 |= 0x80; 613 } 614 else { 615 --bc; 616 np->rv_dmode |= ((bc & 0x3) << 6); 617 np->rv_ctest5 |= (bc & 0x4); 618 } 619 } 620 621 /* 622 * Save initial settings of some IO registers. 623 * Assumed to have been set by BIOS. 624 * We cannot reset the chip prior to reading the 625 * IO registers, since informations will be lost. 626 * Since the SCRIPTS processor may be running, this 627 * is not safe on paper, but it seems to work quite 628 * well. :) 629 */ 630 static void sym_save_initial_setting (struct sym_hcb *np) 631 { 632 np->sv_scntl0 = INB(np, nc_scntl0) & 0x0a; 633 np->sv_scntl3 = INB(np, nc_scntl3) & 0x07; 634 np->sv_dmode = INB(np, nc_dmode) & 0xce; 635 np->sv_dcntl = INB(np, nc_dcntl) & 0xa8; 636 np->sv_ctest3 = INB(np, nc_ctest3) & 0x01; 637 np->sv_ctest4 = INB(np, nc_ctest4) & 0x80; 638 np->sv_gpcntl = INB(np, nc_gpcntl); 639 np->sv_stest1 = INB(np, nc_stest1); 640 np->sv_stest2 = INB(np, nc_stest2) & 0x20; 641 np->sv_stest4 = INB(np, nc_stest4); 642 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */ 643 np->sv_scntl4 = INB(np, nc_scntl4); 644 np->sv_ctest5 = INB(np, nc_ctest5) & 0x04; 645 } 646 else 647 np->sv_ctest5 = INB(np, nc_ctest5) & 0x24; 648 } 649 650 /* 651 * Set SCSI BUS mode. 652 * - LVD capable chips (895/895A/896/1010) report the current BUS mode 653 * through the STEST4 IO register. 654 * - For previous generation chips (825/825A/875), the user has to tell us 655 * how to check against HVD, since a 100% safe algorithm is not possible. 656 */ 657 static void sym_set_bus_mode(struct sym_hcb *np, struct sym_nvram *nvram) 658 { 659 if (np->scsi_mode) 660 return; 661 662 np->scsi_mode = SMODE_SE; 663 if (np->features & (FE_ULTRA2|FE_ULTRA3)) 664 np->scsi_mode = (np->sv_stest4 & SMODE); 665 else if (np->features & FE_DIFF) { 666 if (SYM_SETUP_SCSI_DIFF == 1) { 667 if (np->sv_scntl3) { 668 if (np->sv_stest2 & 0x20) 669 np->scsi_mode = SMODE_HVD; 670 } else if (nvram->type == SYM_SYMBIOS_NVRAM) { 671 if (!(INB(np, nc_gpreg) & 0x08)) 672 np->scsi_mode = SMODE_HVD; 673 } 674 } else if (SYM_SETUP_SCSI_DIFF == 2) 675 np->scsi_mode = SMODE_HVD; 676 } 677 if (np->scsi_mode == SMODE_HVD) 678 np->rv_stest2 |= 0x20; 679 } 680 681 /* 682 * Prepare io register values used by sym_start_up() 683 * according to selected and supported features. 684 */ 685 static int sym_prepare_setting(struct Scsi_Host *shost, struct sym_hcb *np, struct sym_nvram *nvram) 686 { 687 struct sym_data *sym_data = shost_priv(shost); 688 struct pci_dev *pdev = sym_data->pdev; 689 u_char burst_max; 690 u32 period; 691 int i; 692 693 np->maxwide = (np->features & FE_WIDE) ? 1 : 0; 694 695 /* 696 * Guess the frequency of the chip's clock. 697 */ 698 if (np->features & (FE_ULTRA3 | FE_ULTRA2)) 699 np->clock_khz = 160000; 700 else if (np->features & FE_ULTRA) 701 np->clock_khz = 80000; 702 else 703 np->clock_khz = 40000; 704 705 /* 706 * Get the clock multiplier factor. 707 */ 708 if (np->features & FE_QUAD) 709 np->multiplier = 4; 710 else if (np->features & FE_DBLR) 711 np->multiplier = 2; 712 else 713 np->multiplier = 1; 714 715 /* 716 * Measure SCSI clock frequency for chips 717 * it may vary from assumed one. 718 */ 719 if (np->features & FE_VARCLK) 720 sym_getclock(np, np->multiplier); 721 722 /* 723 * Divisor to be used for async (timer pre-scaler). 724 */ 725 i = np->clock_divn - 1; 726 while (--i >= 0) { 727 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) { 728 ++i; 729 break; 730 } 731 } 732 np->rv_scntl3 = i+1; 733 734 /* 735 * The C1010 uses hardwired divisors for async. 736 * So, we just throw away, the async. divisor.:-) 737 */ 738 if (np->features & FE_C10) 739 np->rv_scntl3 = 0; 740 741 /* 742 * Minimum synchronous period factor supported by the chip. 743 * Btw, 'period' is in tenths of nanoseconds. 744 */ 745 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz; 746 747 if (period <= 250) np->minsync = 10; 748 else if (period <= 303) np->minsync = 11; 749 else if (period <= 500) np->minsync = 12; 750 else np->minsync = (period + 40 - 1) / 40; 751 752 /* 753 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2). 754 */ 755 if (np->minsync < 25 && 756 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3))) 757 np->minsync = 25; 758 else if (np->minsync < 12 && 759 !(np->features & (FE_ULTRA2|FE_ULTRA3))) 760 np->minsync = 12; 761 762 /* 763 * Maximum synchronous period factor supported by the chip. 764 */ 765 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz); 766 np->maxsync = period > 2540 ? 254 : period / 10; 767 768 /* 769 * If chip is a C1010, guess the sync limits in DT mode. 770 */ 771 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) { 772 if (np->clock_khz == 160000) { 773 np->minsync_dt = 9; 774 np->maxsync_dt = 50; 775 np->maxoffs_dt = nvram->type ? 62 : 31; 776 } 777 } 778 779 /* 780 * 64 bit addressing (895A/896/1010) ? 781 */ 782 if (np->features & FE_DAC) { 783 if (!use_dac(np)) 784 np->rv_ccntl1 |= (DDAC); 785 else if (SYM_CONF_DMA_ADDRESSING_MODE == 1) 786 np->rv_ccntl1 |= (XTIMOD | EXTIBMV); 787 else if (SYM_CONF_DMA_ADDRESSING_MODE == 2) 788 np->rv_ccntl1 |= (0 | EXTIBMV); 789 } 790 791 /* 792 * Phase mismatch handled by SCRIPTS (895A/896/1010) ? 793 */ 794 if (np->features & FE_NOPM) 795 np->rv_ccntl0 |= (ENPMJ); 796 797 /* 798 * C1010-33 Errata: Part Number:609-039638 (rev. 1) is fixed. 799 * In dual channel mode, contention occurs if internal cycles 800 * are used. Disable internal cycles. 801 */ 802 if (pdev->device == PCI_DEVICE_ID_LSI_53C1010_33 && 803 pdev->revision < 0x1) 804 np->rv_ccntl0 |= DILS; 805 806 /* 807 * Select burst length (dwords) 808 */ 809 burst_max = SYM_SETUP_BURST_ORDER; 810 if (burst_max == 255) 811 burst_max = burst_code(np->sv_dmode, np->sv_ctest4, 812 np->sv_ctest5); 813 if (burst_max > 7) 814 burst_max = 7; 815 if (burst_max > np->maxburst) 816 burst_max = np->maxburst; 817 818 /* 819 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2. 820 * This chip and the 860 Rev 1 may wrongly use PCI cache line 821 * based transactions on LOAD/STORE instructions. So we have 822 * to prevent these chips from using such PCI transactions in 823 * this driver. The generic ncr driver that does not use 824 * LOAD/STORE instructions does not need this work-around. 825 */ 826 if ((pdev->device == PCI_DEVICE_ID_NCR_53C810 && 827 pdev->revision >= 0x10 && pdev->revision <= 0x11) || 828 (pdev->device == PCI_DEVICE_ID_NCR_53C860 && 829 pdev->revision <= 0x1)) 830 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP); 831 832 /* 833 * Select all supported special features. 834 * If we are using on-board RAM for scripts, prefetch (PFEN) 835 * does not help, but burst op fetch (BOF) does. 836 * Disabling PFEN makes sure BOF will be used. 837 */ 838 if (np->features & FE_ERL) 839 np->rv_dmode |= ERL; /* Enable Read Line */ 840 if (np->features & FE_BOF) 841 np->rv_dmode |= BOF; /* Burst Opcode Fetch */ 842 if (np->features & FE_ERMP) 843 np->rv_dmode |= ERMP; /* Enable Read Multiple */ 844 #if 1 845 if ((np->features & FE_PFEN) && !np->ram_ba) 846 #else 847 if (np->features & FE_PFEN) 848 #endif 849 np->rv_dcntl |= PFEN; /* Prefetch Enable */ 850 if (np->features & FE_CLSE) 851 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */ 852 if (np->features & FE_WRIE) 853 np->rv_ctest3 |= WRIE; /* Write and Invalidate */ 854 if (np->features & FE_DFS) 855 np->rv_ctest5 |= DFS; /* Dma Fifo Size */ 856 857 /* 858 * Select some other 859 */ 860 np->rv_ctest4 |= MPEE; /* Master parity checking */ 861 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */ 862 863 /* 864 * Get parity checking, host ID and verbose mode from NVRAM 865 */ 866 np->myaddr = 255; 867 np->scsi_mode = 0; 868 sym_nvram_setup_host(shost, np, nvram); 869 870 /* 871 * Get SCSI addr of host adapter (set by bios?). 872 */ 873 if (np->myaddr == 255) { 874 np->myaddr = INB(np, nc_scid) & 0x07; 875 if (!np->myaddr) 876 np->myaddr = SYM_SETUP_HOST_ID; 877 } 878 879 /* 880 * Prepare initial io register bits for burst length 881 */ 882 sym_init_burst(np, burst_max); 883 884 sym_set_bus_mode(np, nvram); 885 886 /* 887 * Set LED support from SCRIPTS. 888 * Ignore this feature for boards known to use a 889 * specific GPIO wiring and for the 895A, 896 890 * and 1010 that drive the LED directly. 891 */ 892 if ((SYM_SETUP_SCSI_LED || 893 (nvram->type == SYM_SYMBIOS_NVRAM || 894 (nvram->type == SYM_TEKRAM_NVRAM && 895 pdev->device == PCI_DEVICE_ID_NCR_53C895))) && 896 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01)) 897 np->features |= FE_LED0; 898 899 /* 900 * Set irq mode. 901 */ 902 switch(SYM_SETUP_IRQ_MODE & 3) { 903 case 2: 904 np->rv_dcntl |= IRQM; 905 break; 906 case 1: 907 np->rv_dcntl |= (np->sv_dcntl & IRQM); 908 break; 909 default: 910 break; 911 } 912 913 /* 914 * Configure targets according to driver setup. 915 * If NVRAM present get targets setup from NVRAM. 916 */ 917 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 918 struct sym_tcb *tp = &np->target[i]; 919 920 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 921 tp->usrtags = SYM_SETUP_MAX_TAG; 922 tp->usr_width = np->maxwide; 923 tp->usr_period = 9; 924 925 sym_nvram_setup_target(tp, i, nvram); 926 927 if (!tp->usrtags) 928 tp->usrflags &= ~SYM_TAGS_ENABLED; 929 } 930 931 /* 932 * Let user know about the settings. 933 */ 934 printf("%s: %s, ID %d, Fast-%d, %s, %s\n", sym_name(np), 935 sym_nvram_type(nvram), np->myaddr, 936 (np->features & FE_ULTRA3) ? 80 : 937 (np->features & FE_ULTRA2) ? 40 : 938 (np->features & FE_ULTRA) ? 20 : 10, 939 sym_scsi_bus_mode(np->scsi_mode), 940 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity"); 941 /* 942 * Tell him more on demand. 943 */ 944 if (sym_verbose) { 945 printf("%s: %s IRQ line driver%s\n", 946 sym_name(np), 947 np->rv_dcntl & IRQM ? "totem pole" : "open drain", 948 np->ram_ba ? ", using on-chip SRAM" : ""); 949 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name); 950 if (np->features & FE_NOPM) 951 printf("%s: handling phase mismatch from SCRIPTS.\n", 952 sym_name(np)); 953 } 954 /* 955 * And still more. 956 */ 957 if (sym_verbose >= 2) { 958 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 959 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 960 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl, 961 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5); 962 963 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = " 964 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n", 965 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl, 966 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5); 967 } 968 969 return 0; 970 } 971 972 /* 973 * Test the pci bus snoop logic :-( 974 * 975 * Has to be called with interrupts disabled. 976 */ 977 #ifdef CONFIG_SCSI_SYM53C8XX_MMIO 978 static int sym_regtest(struct sym_hcb *np) 979 { 980 register volatile u32 data; 981 /* 982 * chip registers may NOT be cached. 983 * write 0xffffffff to a read only register area, 984 * and try to read it back. 985 */ 986 data = 0xffffffff; 987 OUTL(np, nc_dstat, data); 988 data = INL(np, nc_dstat); 989 #if 1 990 if (data == 0xffffffff) { 991 #else 992 if ((data & 0xe2f0fffd) != 0x02000080) { 993 #endif 994 printf ("CACHE TEST FAILED: reg dstat-sstat2 readback %x.\n", 995 (unsigned) data); 996 return 0x10; 997 } 998 return 0; 999 } 1000 #else 1001 static inline int sym_regtest(struct sym_hcb *np) 1002 { 1003 return 0; 1004 } 1005 #endif 1006 1007 static int sym_snooptest(struct sym_hcb *np) 1008 { 1009 u32 sym_rd, sym_wr, sym_bk, host_rd, host_wr, pc, dstat; 1010 int i, err; 1011 1012 err = sym_regtest(np); 1013 if (err) 1014 return err; 1015 restart_test: 1016 /* 1017 * Enable Master Parity Checking as we intend 1018 * to enable it for normal operations. 1019 */ 1020 OUTB(np, nc_ctest4, (np->rv_ctest4 & MPEE)); 1021 /* 1022 * init 1023 */ 1024 pc = SCRIPTZ_BA(np, snooptest); 1025 host_wr = 1; 1026 sym_wr = 2; 1027 /* 1028 * Set memory and register. 1029 */ 1030 np->scratch = cpu_to_scr(host_wr); 1031 OUTL(np, nc_temp, sym_wr); 1032 /* 1033 * Start script (exchange values) 1034 */ 1035 OUTL(np, nc_dsa, np->hcb_ba); 1036 OUTL_DSP(np, pc); 1037 /* 1038 * Wait 'til done (with timeout) 1039 */ 1040 for (i=0; i<SYM_SNOOP_TIMEOUT; i++) 1041 if (INB(np, nc_istat) & (INTF|SIP|DIP)) 1042 break; 1043 if (i>=SYM_SNOOP_TIMEOUT) { 1044 printf ("CACHE TEST FAILED: timeout.\n"); 1045 return (0x20); 1046 } 1047 /* 1048 * Check for fatal DMA errors. 1049 */ 1050 dstat = INB(np, nc_dstat); 1051 #if 1 /* Band aiding for broken hardwares that fail PCI parity */ 1052 if ((dstat & MDPE) && (np->rv_ctest4 & MPEE)) { 1053 printf ("%s: PCI DATA PARITY ERROR DETECTED - " 1054 "DISABLING MASTER DATA PARITY CHECKING.\n", 1055 sym_name(np)); 1056 np->rv_ctest4 &= ~MPEE; 1057 goto restart_test; 1058 } 1059 #endif 1060 if (dstat & (MDPE|BF|IID)) { 1061 printf ("CACHE TEST FAILED: DMA error (dstat=0x%02x).", dstat); 1062 return (0x80); 1063 } 1064 /* 1065 * Save termination position. 1066 */ 1067 pc = INL(np, nc_dsp); 1068 /* 1069 * Read memory and register. 1070 */ 1071 host_rd = scr_to_cpu(np->scratch); 1072 sym_rd = INL(np, nc_scratcha); 1073 sym_bk = INL(np, nc_temp); 1074 /* 1075 * Check termination position. 1076 */ 1077 if (pc != SCRIPTZ_BA(np, snoopend)+8) { 1078 printf ("CACHE TEST FAILED: script execution failed.\n"); 1079 printf ("start=%08lx, pc=%08lx, end=%08lx\n", 1080 (u_long) SCRIPTZ_BA(np, snooptest), (u_long) pc, 1081 (u_long) SCRIPTZ_BA(np, snoopend) +8); 1082 return (0x40); 1083 } 1084 /* 1085 * Show results. 1086 */ 1087 if (host_wr != sym_rd) { 1088 printf ("CACHE TEST FAILED: host wrote %d, chip read %d.\n", 1089 (int) host_wr, (int) sym_rd); 1090 err |= 1; 1091 } 1092 if (host_rd != sym_wr) { 1093 printf ("CACHE TEST FAILED: chip wrote %d, host read %d.\n", 1094 (int) sym_wr, (int) host_rd); 1095 err |= 2; 1096 } 1097 if (sym_bk != sym_wr) { 1098 printf ("CACHE TEST FAILED: chip wrote %d, read back %d.\n", 1099 (int) sym_wr, (int) sym_bk); 1100 err |= 4; 1101 } 1102 1103 return err; 1104 } 1105 1106 /* 1107 * log message for real hard errors 1108 * 1109 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sx/s3/s4) @ name (dsp:dbc). 1110 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf. 1111 * 1112 * exception register: 1113 * ds: dstat 1114 * si: sist 1115 * 1116 * SCSI bus lines: 1117 * so: control lines as driven by chip. 1118 * si: control lines as seen by chip. 1119 * sd: scsi data lines as seen by chip. 1120 * 1121 * wide/fastmode: 1122 * sx: sxfer (see the manual) 1123 * s3: scntl3 (see the manual) 1124 * s4: scntl4 (see the manual) 1125 * 1126 * current script command: 1127 * dsp: script address (relative to start of script). 1128 * dbc: first word of script command. 1129 * 1130 * First 24 register of the chip: 1131 * r0..rf 1132 */ 1133 static void sym_log_hard_error(struct Scsi_Host *shost, u_short sist, u_char dstat) 1134 { 1135 struct sym_hcb *np = sym_get_hcb(shost); 1136 u32 dsp; 1137 int script_ofs; 1138 int script_size; 1139 char *script_name; 1140 u_char *script_base; 1141 int i; 1142 1143 dsp = INL(np, nc_dsp); 1144 1145 if (dsp > np->scripta_ba && 1146 dsp <= np->scripta_ba + np->scripta_sz) { 1147 script_ofs = dsp - np->scripta_ba; 1148 script_size = np->scripta_sz; 1149 script_base = (u_char *) np->scripta0; 1150 script_name = "scripta"; 1151 } 1152 else if (np->scriptb_ba < dsp && 1153 dsp <= np->scriptb_ba + np->scriptb_sz) { 1154 script_ofs = dsp - np->scriptb_ba; 1155 script_size = np->scriptb_sz; 1156 script_base = (u_char *) np->scriptb0; 1157 script_name = "scriptb"; 1158 } else { 1159 script_ofs = dsp; 1160 script_size = 0; 1161 script_base = NULL; 1162 script_name = "mem"; 1163 } 1164 1165 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x/%x) @ (%s %x:%08x).\n", 1166 sym_name(np), (unsigned)INB(np, nc_sdid)&0x0f, dstat, sist, 1167 (unsigned)INB(np, nc_socl), (unsigned)INB(np, nc_sbcl), 1168 (unsigned)INB(np, nc_sbdl), (unsigned)INB(np, nc_sxfer), 1169 (unsigned)INB(np, nc_scntl3), 1170 (np->features & FE_C10) ? (unsigned)INB(np, nc_scntl4) : 0, 1171 script_name, script_ofs, (unsigned)INL(np, nc_dbc)); 1172 1173 if (((script_ofs & 3) == 0) && 1174 (unsigned)script_ofs < script_size) { 1175 printf ("%s: script cmd = %08x\n", sym_name(np), 1176 scr_to_cpu((int) *(u32 *)(script_base + script_ofs))); 1177 } 1178 1179 printf("%s: regdump:", sym_name(np)); 1180 for (i = 0; i < 24; i++) 1181 printf(" %02x", (unsigned)INB_OFF(np, i)); 1182 printf(".\n"); 1183 1184 /* 1185 * PCI BUS error. 1186 */ 1187 if (dstat & (MDPE|BF)) 1188 sym_log_bus_error(shost); 1189 } 1190 1191 void sym_dump_registers(struct Scsi_Host *shost) 1192 { 1193 struct sym_hcb *np = sym_get_hcb(shost); 1194 u_short sist; 1195 u_char dstat; 1196 1197 sist = INW(np, nc_sist); 1198 dstat = INB(np, nc_dstat); 1199 sym_log_hard_error(shost, sist, dstat); 1200 } 1201 1202 static struct sym_chip sym_dev_table[] = { 1203 {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, 64, 1204 FE_ERL} 1205 , 1206 #ifdef SYM_DEBUG_GENERIC_SUPPORT 1207 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, 1, 1208 FE_BOF} 1209 , 1210 #else 1211 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, 1, 1212 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} 1213 , 1214 #endif 1215 {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, 64, 1216 FE_BOF|FE_ERL} 1217 , 1218 {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 6, 8, 4, 64, 1219 FE_WIDE|FE_BOF|FE_ERL|FE_DIFF} 1220 , 1221 {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, 2, 1222 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} 1223 , 1224 {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, 1, 1225 FE_ULTRA|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} 1226 , 1227 {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, 2, 1228 FE_WIDE|FE_ULTRA|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1229 FE_RAM|FE_DIFF|FE_VARCLK} 1230 , 1231 {PCI_DEVICE_ID_NCR_53C875, 0xff, "875", 6, 16, 5, 2, 1232 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1233 FE_RAM|FE_DIFF|FE_VARCLK} 1234 , 1235 {PCI_DEVICE_ID_NCR_53C875J, 0xff, "875J", 6, 16, 5, 2, 1236 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1237 FE_RAM|FE_DIFF|FE_VARCLK} 1238 , 1239 {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, 2, 1240 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1241 FE_RAM|FE_DIFF|FE_VARCLK} 1242 , 1243 #ifdef SYM_DEBUG_GENERIC_SUPPORT 1244 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, 2, 1245 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS| 1246 FE_RAM|FE_LCKFRQ} 1247 , 1248 #else 1249 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, 2, 1250 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1251 FE_RAM|FE_LCKFRQ} 1252 , 1253 #endif 1254 {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, 4, 1255 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1256 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 1257 , 1258 {PCI_DEVICE_ID_LSI_53C895A, 0xff, "895a", 6, 31, 7, 4, 1259 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1260 FE_RAM|FE_RAM8K|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 1261 , 1262 {PCI_DEVICE_ID_LSI_53C875A, 0xff, "875a", 6, 31, 7, 4, 1263 FE_WIDE|FE_ULTRA|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1264 FE_RAM|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_LCKFRQ} 1265 , 1266 {PCI_DEVICE_ID_LSI_53C1010_33, 0x00, "1010-33", 6, 31, 7, 8, 1267 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 1268 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 1269 FE_C10} 1270 , 1271 {PCI_DEVICE_ID_LSI_53C1010_33, 0xff, "1010-33", 6, 31, 7, 8, 1272 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 1273 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_CRC| 1274 FE_C10|FE_U3EN} 1275 , 1276 {PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010-66", 6, 31, 7, 8, 1277 FE_WIDE|FE_ULTRA3|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFBC|FE_LDSTR|FE_PFEN| 1278 FE_RAM|FE_RAM8K|FE_64BIT|FE_DAC|FE_IO256|FE_NOPM|FE_LEDC|FE_66MHZ|FE_CRC| 1279 FE_C10|FE_U3EN} 1280 , 1281 {PCI_DEVICE_ID_LSI_53C1510, 0xff, "1510d", 6, 31, 7, 4, 1282 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| 1283 FE_RAM|FE_IO256|FE_LEDC} 1284 }; 1285 1286 #define sym_num_devs (ARRAY_SIZE(sym_dev_table)) 1287 1288 /* 1289 * Look up the chip table. 1290 * 1291 * Return a pointer to the chip entry if found, 1292 * zero otherwise. 1293 */ 1294 struct sym_chip * 1295 sym_lookup_chip_table (u_short device_id, u_char revision) 1296 { 1297 struct sym_chip *chip; 1298 int i; 1299 1300 for (i = 0; i < sym_num_devs; i++) { 1301 chip = &sym_dev_table[i]; 1302 if (device_id != chip->device_id) 1303 continue; 1304 if (revision > chip->revision_id) 1305 continue; 1306 return chip; 1307 } 1308 1309 return NULL; 1310 } 1311 1312 #if SYM_CONF_DMA_ADDRESSING_MODE == 2 1313 /* 1314 * Lookup the 64 bit DMA segments map. 1315 * This is only used if the direct mapping 1316 * has been unsuccessful. 1317 */ 1318 int sym_lookup_dmap(struct sym_hcb *np, u32 h, int s) 1319 { 1320 int i; 1321 1322 if (!use_dac(np)) 1323 goto weird; 1324 1325 /* Look up existing mappings */ 1326 for (i = SYM_DMAP_SIZE-1; i > 0; i--) { 1327 if (h == np->dmap_bah[i]) 1328 return i; 1329 } 1330 /* If direct mapping is free, get it */ 1331 if (!np->dmap_bah[s]) 1332 goto new; 1333 /* Collision -> lookup free mappings */ 1334 for (s = SYM_DMAP_SIZE-1; s > 0; s--) { 1335 if (!np->dmap_bah[s]) 1336 goto new; 1337 } 1338 weird: 1339 panic("sym: ran out of 64 bit DMA segment registers"); 1340 return -1; 1341 new: 1342 np->dmap_bah[s] = h; 1343 np->dmap_dirty = 1; 1344 return s; 1345 } 1346 1347 /* 1348 * Update IO registers scratch C..R so they will be 1349 * in sync. with queued CCB expectations. 1350 */ 1351 static void sym_update_dmap_regs(struct sym_hcb *np) 1352 { 1353 int o, i; 1354 1355 if (!np->dmap_dirty) 1356 return; 1357 o = offsetof(struct sym_reg, nc_scrx[0]); 1358 for (i = 0; i < SYM_DMAP_SIZE; i++) { 1359 OUTL_OFF(np, o, np->dmap_bah[i]); 1360 o += 4; 1361 } 1362 np->dmap_dirty = 0; 1363 } 1364 #endif 1365 1366 /* Enforce all the fiddly SPI rules and the chip limitations */ 1367 static void sym_check_goals(struct sym_hcb *np, struct scsi_target *starget, 1368 struct sym_trans *goal) 1369 { 1370 if (!spi_support_wide(starget)) 1371 goal->width = 0; 1372 1373 if (!spi_support_sync(starget)) { 1374 goal->iu = 0; 1375 goal->dt = 0; 1376 goal->qas = 0; 1377 goal->offset = 0; 1378 return; 1379 } 1380 1381 if (spi_support_dt(starget)) { 1382 if (spi_support_dt_only(starget)) 1383 goal->dt = 1; 1384 1385 if (goal->offset == 0) 1386 goal->dt = 0; 1387 } else { 1388 goal->dt = 0; 1389 } 1390 1391 /* Some targets fail to properly negotiate DT in SE mode */ 1392 if ((np->scsi_mode != SMODE_LVD) || !(np->features & FE_U3EN)) 1393 goal->dt = 0; 1394 1395 if (goal->dt) { 1396 /* all DT transfers must be wide */ 1397 goal->width = 1; 1398 if (goal->offset > np->maxoffs_dt) 1399 goal->offset = np->maxoffs_dt; 1400 if (goal->period < np->minsync_dt) 1401 goal->period = np->minsync_dt; 1402 if (goal->period > np->maxsync_dt) 1403 goal->period = np->maxsync_dt; 1404 } else { 1405 goal->iu = goal->qas = 0; 1406 if (goal->offset > np->maxoffs) 1407 goal->offset = np->maxoffs; 1408 if (goal->period < np->minsync) 1409 goal->period = np->minsync; 1410 if (goal->period > np->maxsync) 1411 goal->period = np->maxsync; 1412 } 1413 } 1414 1415 /* 1416 * Prepare the next negotiation message if needed. 1417 * 1418 * Fill in the part of message buffer that contains the 1419 * negotiation and the nego_status field of the CCB. 1420 * Returns the size of the message in bytes. 1421 */ 1422 static int sym_prepare_nego(struct sym_hcb *np, struct sym_ccb *cp, u_char *msgptr) 1423 { 1424 struct sym_tcb *tp = &np->target[cp->target]; 1425 struct scsi_target *starget = tp->starget; 1426 struct sym_trans *goal = &tp->tgoal; 1427 int msglen = 0; 1428 int nego; 1429 1430 sym_check_goals(np, starget, goal); 1431 1432 /* 1433 * Many devices implement PPR in a buggy way, so only use it if we 1434 * really want to. 1435 */ 1436 if (goal->offset && 1437 (goal->iu || goal->dt || goal->qas || (goal->period < 0xa))) { 1438 nego = NS_PPR; 1439 } else if (spi_width(starget) != goal->width) { 1440 nego = NS_WIDE; 1441 } else if (spi_period(starget) != goal->period || 1442 spi_offset(starget) != goal->offset) { 1443 nego = NS_SYNC; 1444 } else { 1445 goal->check_nego = 0; 1446 nego = 0; 1447 } 1448 1449 switch (nego) { 1450 case NS_SYNC: 1451 msglen += spi_populate_sync_msg(msgptr + msglen, goal->period, 1452 goal->offset); 1453 break; 1454 case NS_WIDE: 1455 msglen += spi_populate_width_msg(msgptr + msglen, goal->width); 1456 break; 1457 case NS_PPR: 1458 msglen += spi_populate_ppr_msg(msgptr + msglen, goal->period, 1459 goal->offset, goal->width, 1460 (goal->iu ? PPR_OPT_IU : 0) | 1461 (goal->dt ? PPR_OPT_DT : 0) | 1462 (goal->qas ? PPR_OPT_QAS : 0)); 1463 break; 1464 } 1465 1466 cp->nego_status = nego; 1467 1468 if (nego) { 1469 tp->nego_cp = cp; /* Keep track a nego will be performed */ 1470 if (DEBUG_FLAGS & DEBUG_NEGO) { 1471 sym_print_nego_msg(np, cp->target, 1472 nego == NS_SYNC ? "sync msgout" : 1473 nego == NS_WIDE ? "wide msgout" : 1474 "ppr msgout", msgptr); 1475 } 1476 } 1477 1478 return msglen; 1479 } 1480 1481 /* 1482 * Insert a job into the start queue. 1483 */ 1484 void sym_put_start_queue(struct sym_hcb *np, struct sym_ccb *cp) 1485 { 1486 u_short qidx; 1487 1488 #ifdef SYM_CONF_IARB_SUPPORT 1489 /* 1490 * If the previously queued CCB is not yet done, 1491 * set the IARB hint. The SCRIPTS will go with IARB 1492 * for this job when starting the previous one. 1493 * We leave devices a chance to win arbitration by 1494 * not using more than 'iarb_max' consecutive 1495 * immediate arbitrations. 1496 */ 1497 if (np->last_cp && np->iarb_count < np->iarb_max) { 1498 np->last_cp->host_flags |= HF_HINT_IARB; 1499 ++np->iarb_count; 1500 } 1501 else 1502 np->iarb_count = 0; 1503 np->last_cp = cp; 1504 #endif 1505 1506 #if SYM_CONF_DMA_ADDRESSING_MODE == 2 1507 /* 1508 * Make SCRIPTS aware of the 64 bit DMA 1509 * segment registers not being up-to-date. 1510 */ 1511 if (np->dmap_dirty) 1512 cp->host_xflags |= HX_DMAP_DIRTY; 1513 #endif 1514 1515 /* 1516 * Insert first the idle task and then our job. 1517 * The MBs should ensure proper ordering. 1518 */ 1519 qidx = np->squeueput + 2; 1520 if (qidx >= MAX_QUEUE*2) qidx = 0; 1521 1522 np->squeue [qidx] = cpu_to_scr(np->idletask_ba); 1523 MEMORY_WRITE_BARRIER(); 1524 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba); 1525 1526 np->squeueput = qidx; 1527 1528 if (DEBUG_FLAGS & DEBUG_QUEUE) 1529 scmd_printk(KERN_DEBUG, cp->cmd, "queuepos=%d\n", 1530 np->squeueput); 1531 1532 /* 1533 * Script processor may be waiting for reselect. 1534 * Wake it up. 1535 */ 1536 MEMORY_WRITE_BARRIER(); 1537 OUTB(np, nc_istat, SIGP|np->istat_sem); 1538 } 1539 1540 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 1541 /* 1542 * Start next ready-to-start CCBs. 1543 */ 1544 void sym_start_next_ccbs(struct sym_hcb *np, struct sym_lcb *lp, int maxn) 1545 { 1546 SYM_QUEHEAD *qp; 1547 struct sym_ccb *cp; 1548 1549 /* 1550 * Paranoia, as usual. :-) 1551 */ 1552 assert(!lp->started_tags || !lp->started_no_tag); 1553 1554 /* 1555 * Try to start as many commands as asked by caller. 1556 * Prevent from having both tagged and untagged 1557 * commands queued to the device at the same time. 1558 */ 1559 while (maxn--) { 1560 qp = sym_remque_head(&lp->waiting_ccbq); 1561 if (!qp) 1562 break; 1563 cp = sym_que_entry(qp, struct sym_ccb, link2_ccbq); 1564 if (cp->tag != NO_TAG) { 1565 if (lp->started_no_tag || 1566 lp->started_tags >= lp->started_max) { 1567 sym_insque_head(qp, &lp->waiting_ccbq); 1568 break; 1569 } 1570 lp->itlq_tbl[cp->tag] = cpu_to_scr(cp->ccb_ba); 1571 lp->head.resel_sa = 1572 cpu_to_scr(SCRIPTA_BA(np, resel_tag)); 1573 ++lp->started_tags; 1574 } else { 1575 if (lp->started_no_tag || lp->started_tags) { 1576 sym_insque_head(qp, &lp->waiting_ccbq); 1577 break; 1578 } 1579 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba); 1580 lp->head.resel_sa = 1581 cpu_to_scr(SCRIPTA_BA(np, resel_no_tag)); 1582 ++lp->started_no_tag; 1583 } 1584 cp->started = 1; 1585 sym_insque_tail(qp, &lp->started_ccbq); 1586 sym_put_start_queue(np, cp); 1587 } 1588 } 1589 #endif /* SYM_OPT_HANDLE_DEVICE_QUEUEING */ 1590 1591 /* 1592 * The chip may have completed jobs. Look at the DONE QUEUE. 1593 * 1594 * On paper, memory read barriers may be needed here to 1595 * prevent out of order LOADs by the CPU from having 1596 * prefetched stale data prior to DMA having occurred. 1597 */ 1598 static int sym_wakeup_done (struct sym_hcb *np) 1599 { 1600 struct sym_ccb *cp; 1601 int i, n; 1602 u32 dsa; 1603 1604 n = 0; 1605 i = np->dqueueget; 1606 1607 /* MEMORY_READ_BARRIER(); */ 1608 while (1) { 1609 dsa = scr_to_cpu(np->dqueue[i]); 1610 if (!dsa) 1611 break; 1612 np->dqueue[i] = 0; 1613 if ((i = i+2) >= MAX_QUEUE*2) 1614 i = 0; 1615 1616 cp = sym_ccb_from_dsa(np, dsa); 1617 if (cp) { 1618 MEMORY_READ_BARRIER(); 1619 sym_complete_ok (np, cp); 1620 ++n; 1621 } 1622 else 1623 printf ("%s: bad DSA (%x) in done queue.\n", 1624 sym_name(np), (u_int) dsa); 1625 } 1626 np->dqueueget = i; 1627 1628 return n; 1629 } 1630 1631 /* 1632 * Complete all CCBs queued to the COMP queue. 1633 * 1634 * These CCBs are assumed: 1635 * - Not to be referenced either by devices or 1636 * SCRIPTS-related queues and datas. 1637 * - To have to be completed with an error condition 1638 * or requeued. 1639 * 1640 * The device queue freeze count is incremented 1641 * for each CCB that does not prevent this. 1642 * This function is called when all CCBs involved 1643 * in error handling/recovery have been reaped. 1644 */ 1645 static void sym_flush_comp_queue(struct sym_hcb *np, int cam_status) 1646 { 1647 SYM_QUEHEAD *qp; 1648 struct sym_ccb *cp; 1649 1650 while ((qp = sym_remque_head(&np->comp_ccbq)) != NULL) { 1651 struct scsi_cmnd *cmd; 1652 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 1653 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 1654 /* Leave quiet CCBs waiting for resources */ 1655 if (cp->host_status == HS_WAIT) 1656 continue; 1657 cmd = cp->cmd; 1658 if (cam_status) 1659 sym_set_cam_status(cmd, cam_status); 1660 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 1661 if (sym_get_cam_status(cmd) == DID_SOFT_ERROR) { 1662 struct sym_tcb *tp = &np->target[cp->target]; 1663 struct sym_lcb *lp = sym_lp(tp, cp->lun); 1664 if (lp) { 1665 sym_remque(&cp->link2_ccbq); 1666 sym_insque_tail(&cp->link2_ccbq, 1667 &lp->waiting_ccbq); 1668 if (cp->started) { 1669 if (cp->tag != NO_TAG) 1670 --lp->started_tags; 1671 else 1672 --lp->started_no_tag; 1673 } 1674 } 1675 cp->started = 0; 1676 continue; 1677 } 1678 #endif 1679 sym_free_ccb(np, cp); 1680 sym_xpt_done(np, cmd); 1681 } 1682 } 1683 1684 /* 1685 * Complete all active CCBs with error. 1686 * Used on CHIP/SCSI RESET. 1687 */ 1688 static void sym_flush_busy_queue (struct sym_hcb *np, int cam_status) 1689 { 1690 /* 1691 * Move all active CCBs to the COMP queue 1692 * and flush this queue. 1693 */ 1694 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq); 1695 sym_que_init(&np->busy_ccbq); 1696 sym_flush_comp_queue(np, cam_status); 1697 } 1698 1699 /* 1700 * Start chip. 1701 * 1702 * 'reason' means: 1703 * 0: initialisation. 1704 * 1: SCSI BUS RESET delivered or received. 1705 * 2: SCSI BUS MODE changed. 1706 */ 1707 void sym_start_up(struct Scsi_Host *shost, int reason) 1708 { 1709 struct sym_data *sym_data = shost_priv(shost); 1710 struct pci_dev *pdev = sym_data->pdev; 1711 struct sym_hcb *np = sym_data->ncb; 1712 int i; 1713 u32 phys; 1714 1715 /* 1716 * Reset chip if asked, otherwise just clear fifos. 1717 */ 1718 if (reason == 1) 1719 sym_soft_reset(np); 1720 else { 1721 OUTB(np, nc_stest3, TE|CSF); 1722 OUTONB(np, nc_ctest3, CLF); 1723 } 1724 1725 /* 1726 * Clear Start Queue 1727 */ 1728 phys = np->squeue_ba; 1729 for (i = 0; i < MAX_QUEUE*2; i += 2) { 1730 np->squeue[i] = cpu_to_scr(np->idletask_ba); 1731 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4); 1732 } 1733 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 1734 1735 /* 1736 * Start at first entry. 1737 */ 1738 np->squeueput = 0; 1739 1740 /* 1741 * Clear Done Queue 1742 */ 1743 phys = np->dqueue_ba; 1744 for (i = 0; i < MAX_QUEUE*2; i += 2) { 1745 np->dqueue[i] = 0; 1746 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4); 1747 } 1748 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys); 1749 1750 /* 1751 * Start at first entry. 1752 */ 1753 np->dqueueget = 0; 1754 1755 /* 1756 * Install patches in scripts. 1757 * This also let point to first position the start 1758 * and done queue pointers used from SCRIPTS. 1759 */ 1760 np->fw_patch(shost); 1761 1762 /* 1763 * Wakeup all pending jobs. 1764 */ 1765 sym_flush_busy_queue(np, DID_RESET); 1766 1767 /* 1768 * Init chip. 1769 */ 1770 OUTB(np, nc_istat, 0x00); /* Remove Reset, abort */ 1771 INB(np, nc_mbox1); 1772 udelay(2000); /* The 895 needs time for the bus mode to settle */ 1773 1774 OUTB(np, nc_scntl0, np->rv_scntl0 | 0xc0); 1775 /* full arb., ena parity, par->ATN */ 1776 OUTB(np, nc_scntl1, 0x00); /* odd parity, and remove CRST!! */ 1777 1778 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */ 1779 1780 OUTB(np, nc_scid , RRE|np->myaddr); /* Adapter SCSI address */ 1781 OUTW(np, nc_respid, 1ul<<np->myaddr); /* Id to respond to */ 1782 OUTB(np, nc_istat , SIGP ); /* Signal Process */ 1783 OUTB(np, nc_dmode , np->rv_dmode); /* Burst length, dma mode */ 1784 OUTB(np, nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */ 1785 1786 OUTB(np, nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */ 1787 OUTB(np, nc_ctest3, np->rv_ctest3); /* Write and invalidate */ 1788 OUTB(np, nc_ctest4, np->rv_ctest4); /* Master parity checking */ 1789 1790 /* Extended Sreq/Sack filtering not supported on the C10 */ 1791 if (np->features & FE_C10) 1792 OUTB(np, nc_stest2, np->rv_stest2); 1793 else 1794 OUTB(np, nc_stest2, EXT|np->rv_stest2); 1795 1796 OUTB(np, nc_stest3, TE); /* TolerANT enable */ 1797 OUTB(np, nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */ 1798 1799 /* 1800 * For now, disable AIP generation on C1010-66. 1801 */ 1802 if (pdev->device == PCI_DEVICE_ID_LSI_53C1010_66) 1803 OUTB(np, nc_aipcntl1, DISAIP); 1804 1805 /* 1806 * C10101 rev. 0 errata. 1807 * Errant SGE's when in narrow. Write bits 4 & 5 of 1808 * STEST1 register to disable SGE. We probably should do 1809 * that from SCRIPTS for each selection/reselection, but 1810 * I just don't want. :) 1811 */ 1812 if (pdev->device == PCI_DEVICE_ID_LSI_53C1010_33 && 1813 pdev->revision < 1) 1814 OUTB(np, nc_stest1, INB(np, nc_stest1) | 0x30); 1815 1816 /* 1817 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2. 1818 * Disable overlapped arbitration for some dual function devices, 1819 * regardless revision id (kind of post-chip-design feature. ;-)) 1820 */ 1821 if (pdev->device == PCI_DEVICE_ID_NCR_53C875) 1822 OUTB(np, nc_ctest0, (1<<5)); 1823 else if (pdev->device == PCI_DEVICE_ID_NCR_53C896) 1824 np->rv_ccntl0 |= DPR; 1825 1826 /* 1827 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing 1828 * and/or hardware phase mismatch, since only such chips 1829 * seem to support those IO registers. 1830 */ 1831 if (np->features & (FE_DAC|FE_NOPM)) { 1832 OUTB(np, nc_ccntl0, np->rv_ccntl0); 1833 OUTB(np, nc_ccntl1, np->rv_ccntl1); 1834 } 1835 1836 #if SYM_CONF_DMA_ADDRESSING_MODE == 2 1837 /* 1838 * Set up scratch C and DRS IO registers to map the 32 bit 1839 * DMA address range our data structures are located in. 1840 */ 1841 if (use_dac(np)) { 1842 np->dmap_bah[0] = 0; /* ??? */ 1843 OUTL(np, nc_scrx[0], np->dmap_bah[0]); 1844 OUTL(np, nc_drs, np->dmap_bah[0]); 1845 } 1846 #endif 1847 1848 /* 1849 * If phase mismatch handled by scripts (895A/896/1010), 1850 * set PM jump addresses. 1851 */ 1852 if (np->features & FE_NOPM) { 1853 OUTL(np, nc_pmjad1, SCRIPTB_BA(np, pm_handle)); 1854 OUTL(np, nc_pmjad2, SCRIPTB_BA(np, pm_handle)); 1855 } 1856 1857 /* 1858 * Enable GPIO0 pin for writing if LED support from SCRIPTS. 1859 * Also set GPIO5 and clear GPIO6 if hardware LED control. 1860 */ 1861 if (np->features & FE_LED0) 1862 OUTB(np, nc_gpcntl, INB(np, nc_gpcntl) & ~0x01); 1863 else if (np->features & FE_LEDC) 1864 OUTB(np, nc_gpcntl, (INB(np, nc_gpcntl) & ~0x41) | 0x20); 1865 1866 /* 1867 * enable ints 1868 */ 1869 OUTW(np, nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR); 1870 OUTB(np, nc_dien , MDPE|BF|SSI|SIR|IID); 1871 1872 /* 1873 * For 895/6 enable SBMC interrupt and save current SCSI bus mode. 1874 * Try to eat the spurious SBMC interrupt that may occur when 1875 * we reset the chip but not the SCSI BUS (at initialization). 1876 */ 1877 if (np->features & (FE_ULTRA2|FE_ULTRA3)) { 1878 OUTONW(np, nc_sien, SBMC); 1879 if (reason == 0) { 1880 INB(np, nc_mbox1); 1881 mdelay(100); 1882 INW(np, nc_sist); 1883 } 1884 np->scsi_mode = INB(np, nc_stest4) & SMODE; 1885 } 1886 1887 /* 1888 * Fill in target structure. 1889 * Reinitialize usrsync. 1890 * Reinitialize usrwide. 1891 * Prepare sync negotiation according to actual SCSI bus mode. 1892 */ 1893 for (i=0;i<SYM_CONF_MAX_TARGET;i++) { 1894 struct sym_tcb *tp = &np->target[i]; 1895 1896 tp->to_reset = 0; 1897 tp->head.sval = 0; 1898 tp->head.wval = np->rv_scntl3; 1899 tp->head.uval = 0; 1900 } 1901 1902 /* 1903 * Download SCSI SCRIPTS to on-chip RAM if present, 1904 * and start script processor. 1905 * We do the download preferently from the CPU. 1906 * For platforms that may not support PCI memory mapping, 1907 * we use simple SCRIPTS that performs MEMORY MOVEs. 1908 */ 1909 phys = SCRIPTA_BA(np, init); 1910 if (np->ram_ba) { 1911 if (sym_verbose >= 2) 1912 printf("%s: Downloading SCSI SCRIPTS.\n", sym_name(np)); 1913 memcpy_toio(np->s.ramaddr, np->scripta0, np->scripta_sz); 1914 if (np->features & FE_RAM8K) { 1915 memcpy_toio(np->s.ramaddr + 4096, np->scriptb0, np->scriptb_sz); 1916 phys = scr_to_cpu(np->scr_ram_seg); 1917 OUTL(np, nc_mmws, phys); 1918 OUTL(np, nc_mmrs, phys); 1919 OUTL(np, nc_sfs, phys); 1920 phys = SCRIPTB_BA(np, start64); 1921 } 1922 } 1923 1924 np->istat_sem = 0; 1925 1926 OUTL(np, nc_dsa, np->hcb_ba); 1927 OUTL_DSP(np, phys); 1928 1929 /* 1930 * Notify the XPT about the RESET condition. 1931 */ 1932 if (reason != 0) 1933 sym_xpt_async_bus_reset(np); 1934 } 1935 1936 /* 1937 * Switch trans mode for current job and its target. 1938 */ 1939 static void sym_settrans(struct sym_hcb *np, int target, u_char opts, u_char ofs, 1940 u_char per, u_char wide, u_char div, u_char fak) 1941 { 1942 SYM_QUEHEAD *qp; 1943 u_char sval, wval, uval; 1944 struct sym_tcb *tp = &np->target[target]; 1945 1946 assert(target == (INB(np, nc_sdid) & 0x0f)); 1947 1948 sval = tp->head.sval; 1949 wval = tp->head.wval; 1950 uval = tp->head.uval; 1951 1952 #if 0 1953 printf("XXXX sval=%x wval=%x uval=%x (%x)\n", 1954 sval, wval, uval, np->rv_scntl3); 1955 #endif 1956 /* 1957 * Set the offset. 1958 */ 1959 if (!(np->features & FE_C10)) 1960 sval = (sval & ~0x1f) | ofs; 1961 else 1962 sval = (sval & ~0x3f) | ofs; 1963 1964 /* 1965 * Set the sync divisor and extra clock factor. 1966 */ 1967 if (ofs != 0) { 1968 wval = (wval & ~0x70) | ((div+1) << 4); 1969 if (!(np->features & FE_C10)) 1970 sval = (sval & ~0xe0) | (fak << 5); 1971 else { 1972 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT); 1973 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT); 1974 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT); 1975 } 1976 } 1977 1978 /* 1979 * Set the bus width. 1980 */ 1981 wval = wval & ~EWS; 1982 if (wide != 0) 1983 wval |= EWS; 1984 1985 /* 1986 * Set misc. ultra enable bits. 1987 */ 1988 if (np->features & FE_C10) { 1989 uval = uval & ~(U3EN|AIPCKEN); 1990 if (opts) { 1991 assert(np->features & FE_U3EN); 1992 uval |= U3EN; 1993 } 1994 } else { 1995 wval = wval & ~ULTRA; 1996 if (per <= 12) wval |= ULTRA; 1997 } 1998 1999 /* 2000 * Stop there if sync parameters are unchanged. 2001 */ 2002 if (tp->head.sval == sval && 2003 tp->head.wval == wval && 2004 tp->head.uval == uval) 2005 return; 2006 tp->head.sval = sval; 2007 tp->head.wval = wval; 2008 tp->head.uval = uval; 2009 2010 /* 2011 * Disable extended Sreq/Sack filtering if per < 50. 2012 * Not supported on the C1010. 2013 */ 2014 if (per < 50 && !(np->features & FE_C10)) 2015 OUTOFFB(np, nc_stest2, EXT); 2016 2017 /* 2018 * set actual value and sync_status 2019 */ 2020 OUTB(np, nc_sxfer, tp->head.sval); 2021 OUTB(np, nc_scntl3, tp->head.wval); 2022 2023 if (np->features & FE_C10) { 2024 OUTB(np, nc_scntl4, tp->head.uval); 2025 } 2026 2027 /* 2028 * patch ALL busy ccbs of this target. 2029 */ 2030 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 2031 struct sym_ccb *cp; 2032 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 2033 if (cp->target != target) 2034 continue; 2035 cp->phys.select.sel_scntl3 = tp->head.wval; 2036 cp->phys.select.sel_sxfer = tp->head.sval; 2037 if (np->features & FE_C10) { 2038 cp->phys.select.sel_scntl4 = tp->head.uval; 2039 } 2040 } 2041 } 2042 2043 /* 2044 * We received a WDTR. 2045 * Let everything be aware of the changes. 2046 */ 2047 static void sym_setwide(struct sym_hcb *np, int target, u_char wide) 2048 { 2049 struct sym_tcb *tp = &np->target[target]; 2050 struct scsi_target *starget = tp->starget; 2051 2052 if (spi_width(starget) == wide) 2053 return; 2054 2055 sym_settrans(np, target, 0, 0, 0, wide, 0, 0); 2056 2057 tp->tgoal.width = wide; 2058 spi_offset(starget) = 0; 2059 spi_period(starget) = 0; 2060 spi_width(starget) = wide; 2061 spi_iu(starget) = 0; 2062 spi_dt(starget) = 0; 2063 spi_qas(starget) = 0; 2064 2065 if (sym_verbose >= 3) 2066 spi_display_xfer_agreement(starget); 2067 } 2068 2069 /* 2070 * We received a SDTR. 2071 * Let everything be aware of the changes. 2072 */ 2073 static void 2074 sym_setsync(struct sym_hcb *np, int target, 2075 u_char ofs, u_char per, u_char div, u_char fak) 2076 { 2077 struct sym_tcb *tp = &np->target[target]; 2078 struct scsi_target *starget = tp->starget; 2079 u_char wide = (tp->head.wval & EWS) ? BUS_16_BIT : BUS_8_BIT; 2080 2081 sym_settrans(np, target, 0, ofs, per, wide, div, fak); 2082 2083 spi_period(starget) = per; 2084 spi_offset(starget) = ofs; 2085 spi_iu(starget) = spi_dt(starget) = spi_qas(starget) = 0; 2086 2087 if (!tp->tgoal.dt && !tp->tgoal.iu && !tp->tgoal.qas) { 2088 tp->tgoal.period = per; 2089 tp->tgoal.offset = ofs; 2090 tp->tgoal.check_nego = 0; 2091 } 2092 2093 spi_display_xfer_agreement(starget); 2094 } 2095 2096 /* 2097 * We received a PPR. 2098 * Let everything be aware of the changes. 2099 */ 2100 static void 2101 sym_setpprot(struct sym_hcb *np, int target, u_char opts, u_char ofs, 2102 u_char per, u_char wide, u_char div, u_char fak) 2103 { 2104 struct sym_tcb *tp = &np->target[target]; 2105 struct scsi_target *starget = tp->starget; 2106 2107 sym_settrans(np, target, opts, ofs, per, wide, div, fak); 2108 2109 spi_width(starget) = tp->tgoal.width = wide; 2110 spi_period(starget) = tp->tgoal.period = per; 2111 spi_offset(starget) = tp->tgoal.offset = ofs; 2112 spi_iu(starget) = tp->tgoal.iu = !!(opts & PPR_OPT_IU); 2113 spi_dt(starget) = tp->tgoal.dt = !!(opts & PPR_OPT_DT); 2114 spi_qas(starget) = tp->tgoal.qas = !!(opts & PPR_OPT_QAS); 2115 tp->tgoal.check_nego = 0; 2116 2117 spi_display_xfer_agreement(starget); 2118 } 2119 2120 /* 2121 * generic recovery from scsi interrupt 2122 * 2123 * The doc says that when the chip gets an SCSI interrupt, 2124 * it tries to stop in an orderly fashion, by completing 2125 * an instruction fetch that had started or by flushing 2126 * the DMA fifo for a write to memory that was executing. 2127 * Such a fashion is not enough to know if the instruction 2128 * that was just before the current DSP value has been 2129 * executed or not. 2130 * 2131 * There are some small SCRIPTS sections that deal with 2132 * the start queue and the done queue that may break any 2133 * assomption from the C code if we are interrupted 2134 * inside, so we reset if this happens. Btw, since these 2135 * SCRIPTS sections are executed while the SCRIPTS hasn't 2136 * started SCSI operations, it is very unlikely to happen. 2137 * 2138 * All the driver data structures are supposed to be 2139 * allocated from the same 4 GB memory window, so there 2140 * is a 1 to 1 relationship between DSA and driver data 2141 * structures. Since we are careful :) to invalidate the 2142 * DSA when we complete a command or when the SCRIPTS 2143 * pushes a DSA into a queue, we can trust it when it 2144 * points to a CCB. 2145 */ 2146 static void sym_recover_scsi_int (struct sym_hcb *np, u_char hsts) 2147 { 2148 u32 dsp = INL(np, nc_dsp); 2149 u32 dsa = INL(np, nc_dsa); 2150 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa); 2151 2152 /* 2153 * If we haven't been interrupted inside the SCRIPTS 2154 * critical pathes, we can safely restart the SCRIPTS 2155 * and trust the DSA value if it matches a CCB. 2156 */ 2157 if ((!(dsp > SCRIPTA_BA(np, getjob_begin) && 2158 dsp < SCRIPTA_BA(np, getjob_end) + 1)) && 2159 (!(dsp > SCRIPTA_BA(np, ungetjob) && 2160 dsp < SCRIPTA_BA(np, reselect) + 1)) && 2161 (!(dsp > SCRIPTB_BA(np, sel_for_abort) && 2162 dsp < SCRIPTB_BA(np, sel_for_abort_1) + 1)) && 2163 (!(dsp > SCRIPTA_BA(np, done) && 2164 dsp < SCRIPTA_BA(np, done_end) + 1))) { 2165 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 2166 OUTB(np, nc_stest3, TE|CSF); /* clear scsi fifo */ 2167 /* 2168 * If we have a CCB, let the SCRIPTS call us back for 2169 * the handling of the error with SCRATCHA filled with 2170 * STARTPOS. This way, we will be able to freeze the 2171 * device queue and requeue awaiting IOs. 2172 */ 2173 if (cp) { 2174 cp->host_status = hsts; 2175 OUTL_DSP(np, SCRIPTA_BA(np, complete_error)); 2176 } 2177 /* 2178 * Otherwise just restart the SCRIPTS. 2179 */ 2180 else { 2181 OUTL(np, nc_dsa, 0xffffff); 2182 OUTL_DSP(np, SCRIPTA_BA(np, start)); 2183 } 2184 } 2185 else 2186 goto reset_all; 2187 2188 return; 2189 2190 reset_all: 2191 sym_start_reset(np); 2192 } 2193 2194 /* 2195 * chip exception handler for selection timeout 2196 */ 2197 static void sym_int_sto (struct sym_hcb *np) 2198 { 2199 u32 dsp = INL(np, nc_dsp); 2200 2201 if (DEBUG_FLAGS & DEBUG_TINY) printf ("T"); 2202 2203 if (dsp == SCRIPTA_BA(np, wf_sel_done) + 8) 2204 sym_recover_scsi_int(np, HS_SEL_TIMEOUT); 2205 else 2206 sym_start_reset(np); 2207 } 2208 2209 /* 2210 * chip exception handler for unexpected disconnect 2211 */ 2212 static void sym_int_udc (struct sym_hcb *np) 2213 { 2214 printf ("%s: unexpected disconnect\n", sym_name(np)); 2215 sym_recover_scsi_int(np, HS_UNEXPECTED); 2216 } 2217 2218 /* 2219 * chip exception handler for SCSI bus mode change 2220 * 2221 * spi2-r12 11.2.3 says a transceiver mode change must 2222 * generate a reset event and a device that detects a reset 2223 * event shall initiate a hard reset. It says also that a 2224 * device that detects a mode change shall set data transfer 2225 * mode to eight bit asynchronous, etc... 2226 * So, just reinitializing all except chip should be enough. 2227 */ 2228 static void sym_int_sbmc(struct Scsi_Host *shost) 2229 { 2230 struct sym_hcb *np = sym_get_hcb(shost); 2231 u_char scsi_mode = INB(np, nc_stest4) & SMODE; 2232 2233 /* 2234 * Notify user. 2235 */ 2236 printf("%s: SCSI BUS mode change from %s to %s.\n", sym_name(np), 2237 sym_scsi_bus_mode(np->scsi_mode), sym_scsi_bus_mode(scsi_mode)); 2238 2239 /* 2240 * Should suspend command processing for a few seconds and 2241 * reinitialize all except the chip. 2242 */ 2243 sym_start_up(shost, 2); 2244 } 2245 2246 /* 2247 * chip exception handler for SCSI parity error. 2248 * 2249 * When the chip detects a SCSI parity error and is 2250 * currently executing a (CH)MOV instruction, it does 2251 * not interrupt immediately, but tries to finish the 2252 * transfer of the current scatter entry before 2253 * interrupting. The following situations may occur: 2254 * 2255 * - The complete scatter entry has been transferred 2256 * without the device having changed phase. 2257 * The chip will then interrupt with the DSP pointing 2258 * to the instruction that follows the MOV. 2259 * 2260 * - A phase mismatch occurs before the MOV finished 2261 * and phase errors are to be handled by the C code. 2262 * The chip will then interrupt with both PAR and MA 2263 * conditions set. 2264 * 2265 * - A phase mismatch occurs before the MOV finished and 2266 * phase errors are to be handled by SCRIPTS. 2267 * The chip will load the DSP with the phase mismatch 2268 * JUMP address and interrupt the host processor. 2269 */ 2270 static void sym_int_par (struct sym_hcb *np, u_short sist) 2271 { 2272 u_char hsts = INB(np, HS_PRT); 2273 u32 dsp = INL(np, nc_dsp); 2274 u32 dbc = INL(np, nc_dbc); 2275 u32 dsa = INL(np, nc_dsa); 2276 u_char sbcl = INB(np, nc_sbcl); 2277 u_char cmd = dbc >> 24; 2278 int phase = cmd & 7; 2279 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa); 2280 2281 printf("%s: SCSI parity error detected: SCR1=%d DBC=%x SBCL=%x\n", 2282 sym_name(np), hsts, dbc, sbcl); 2283 2284 /* 2285 * Check that the chip is connected to the SCSI BUS. 2286 */ 2287 if (!(INB(np, nc_scntl1) & ISCON)) { 2288 sym_recover_scsi_int(np, HS_UNEXPECTED); 2289 return; 2290 } 2291 2292 /* 2293 * If the nexus is not clearly identified, reset the bus. 2294 * We will try to do better later. 2295 */ 2296 if (!cp) 2297 goto reset_all; 2298 2299 /* 2300 * Check instruction was a MOV, direction was INPUT and 2301 * ATN is asserted. 2302 */ 2303 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8)) 2304 goto reset_all; 2305 2306 /* 2307 * Keep track of the parity error. 2308 */ 2309 OUTONB(np, HF_PRT, HF_EXT_ERR); 2310 cp->xerr_status |= XE_PARITY_ERR; 2311 2312 /* 2313 * Prepare the message to send to the device. 2314 */ 2315 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR; 2316 2317 /* 2318 * If the old phase was DATA IN phase, we have to deal with 2319 * the 3 situations described above. 2320 * For other input phases (MSG IN and STATUS), the device 2321 * must resend the whole thing that failed parity checking 2322 * or signal error. So, jumping to dispatcher should be OK. 2323 */ 2324 if (phase == 1 || phase == 5) { 2325 /* Phase mismatch handled by SCRIPTS */ 2326 if (dsp == SCRIPTB_BA(np, pm_handle)) 2327 OUTL_DSP(np, dsp); 2328 /* Phase mismatch handled by the C code */ 2329 else if (sist & MA) 2330 sym_int_ma (np); 2331 /* No phase mismatch occurred */ 2332 else { 2333 sym_set_script_dp (np, cp, dsp); 2334 OUTL_DSP(np, SCRIPTA_BA(np, dispatch)); 2335 } 2336 } 2337 else if (phase == 7) /* We definitely cannot handle parity errors */ 2338 #if 1 /* in message-in phase due to the relection */ 2339 goto reset_all; /* path and various message anticipations. */ 2340 #else 2341 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 2342 #endif 2343 else 2344 OUTL_DSP(np, SCRIPTA_BA(np, dispatch)); 2345 return; 2346 2347 reset_all: 2348 sym_start_reset(np); 2349 return; 2350 } 2351 2352 /* 2353 * chip exception handler for phase errors. 2354 * 2355 * We have to construct a new transfer descriptor, 2356 * to transfer the rest of the current block. 2357 */ 2358 static void sym_int_ma (struct sym_hcb *np) 2359 { 2360 u32 dbc; 2361 u32 rest; 2362 u32 dsp; 2363 u32 dsa; 2364 u32 nxtdsp; 2365 u32 *vdsp; 2366 u32 oadr, olen; 2367 u32 *tblp; 2368 u32 newcmd; 2369 u_int delta; 2370 u_char cmd; 2371 u_char hflags, hflags0; 2372 struct sym_pmc *pm; 2373 struct sym_ccb *cp; 2374 2375 dsp = INL(np, nc_dsp); 2376 dbc = INL(np, nc_dbc); 2377 dsa = INL(np, nc_dsa); 2378 2379 cmd = dbc >> 24; 2380 rest = dbc & 0xffffff; 2381 delta = 0; 2382 2383 /* 2384 * locate matching cp if any. 2385 */ 2386 cp = sym_ccb_from_dsa(np, dsa); 2387 2388 /* 2389 * Donnot take into account dma fifo and various buffers in 2390 * INPUT phase since the chip flushes everything before 2391 * raising the MA interrupt for interrupted INPUT phases. 2392 * For DATA IN phase, we will check for the SWIDE later. 2393 */ 2394 if ((cmd & 7) != 1 && (cmd & 7) != 5) { 2395 u_char ss0, ss2; 2396 2397 if (np->features & FE_DFBC) 2398 delta = INW(np, nc_dfbc); 2399 else { 2400 u32 dfifo; 2401 2402 /* 2403 * Read DFIFO, CTEST[4-6] using 1 PCI bus ownership. 2404 */ 2405 dfifo = INL(np, nc_dfifo); 2406 2407 /* 2408 * Calculate remaining bytes in DMA fifo. 2409 * (CTEST5 = dfifo >> 16) 2410 */ 2411 if (dfifo & (DFS << 16)) 2412 delta = ((((dfifo >> 8) & 0x300) | 2413 (dfifo & 0xff)) - rest) & 0x3ff; 2414 else 2415 delta = ((dfifo & 0xff) - rest) & 0x7f; 2416 } 2417 2418 /* 2419 * The data in the dma fifo has not been transfered to 2420 * the target -> add the amount to the rest 2421 * and clear the data. 2422 * Check the sstat2 register in case of wide transfer. 2423 */ 2424 rest += delta; 2425 ss0 = INB(np, nc_sstat0); 2426 if (ss0 & OLF) rest++; 2427 if (!(np->features & FE_C10)) 2428 if (ss0 & ORF) rest++; 2429 if (cp && (cp->phys.select.sel_scntl3 & EWS)) { 2430 ss2 = INB(np, nc_sstat2); 2431 if (ss2 & OLF1) rest++; 2432 if (!(np->features & FE_C10)) 2433 if (ss2 & ORF1) rest++; 2434 } 2435 2436 /* 2437 * Clear fifos. 2438 */ 2439 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* dma fifo */ 2440 OUTB(np, nc_stest3, TE|CSF); /* scsi fifo */ 2441 } 2442 2443 /* 2444 * log the information 2445 */ 2446 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_PHASE)) 2447 printf ("P%x%x RL=%d D=%d ", cmd&7, INB(np, nc_sbcl)&7, 2448 (unsigned) rest, (unsigned) delta); 2449 2450 /* 2451 * try to find the interrupted script command, 2452 * and the address at which to continue. 2453 */ 2454 vdsp = NULL; 2455 nxtdsp = 0; 2456 if (dsp > np->scripta_ba && 2457 dsp <= np->scripta_ba + np->scripta_sz) { 2458 vdsp = (u32 *)((char*)np->scripta0 + (dsp-np->scripta_ba-8)); 2459 nxtdsp = dsp; 2460 } 2461 else if (dsp > np->scriptb_ba && 2462 dsp <= np->scriptb_ba + np->scriptb_sz) { 2463 vdsp = (u32 *)((char*)np->scriptb0 + (dsp-np->scriptb_ba-8)); 2464 nxtdsp = dsp; 2465 } 2466 2467 /* 2468 * log the information 2469 */ 2470 if (DEBUG_FLAGS & DEBUG_PHASE) { 2471 printf ("\nCP=%p DSP=%x NXT=%x VDSP=%p CMD=%x ", 2472 cp, (unsigned)dsp, (unsigned)nxtdsp, vdsp, cmd); 2473 } 2474 2475 if (!vdsp) { 2476 printf ("%s: interrupted SCRIPT address not found.\n", 2477 sym_name (np)); 2478 goto reset_all; 2479 } 2480 2481 if (!cp) { 2482 printf ("%s: SCSI phase error fixup: CCB already dequeued.\n", 2483 sym_name (np)); 2484 goto reset_all; 2485 } 2486 2487 /* 2488 * get old startaddress and old length. 2489 */ 2490 oadr = scr_to_cpu(vdsp[1]); 2491 2492 if (cmd & 0x10) { /* Table indirect */ 2493 tblp = (u32 *) ((char*) &cp->phys + oadr); 2494 olen = scr_to_cpu(tblp[0]); 2495 oadr = scr_to_cpu(tblp[1]); 2496 } else { 2497 tblp = (u32 *) 0; 2498 olen = scr_to_cpu(vdsp[0]) & 0xffffff; 2499 } 2500 2501 if (DEBUG_FLAGS & DEBUG_PHASE) { 2502 printf ("OCMD=%x\nTBLP=%p OLEN=%x OADR=%x\n", 2503 (unsigned) (scr_to_cpu(vdsp[0]) >> 24), 2504 tblp, 2505 (unsigned) olen, 2506 (unsigned) oadr); 2507 } 2508 2509 /* 2510 * check cmd against assumed interrupted script command. 2511 * If dt data phase, the MOVE instruction hasn't bit 4 of 2512 * the phase. 2513 */ 2514 if (((cmd & 2) ? cmd : (cmd & ~4)) != (scr_to_cpu(vdsp[0]) >> 24)) { 2515 sym_print_addr(cp->cmd, 2516 "internal error: cmd=%02x != %02x=(vdsp[0] >> 24)\n", 2517 cmd, scr_to_cpu(vdsp[0]) >> 24); 2518 2519 goto reset_all; 2520 } 2521 2522 /* 2523 * if old phase not dataphase, leave here. 2524 */ 2525 if (cmd & 2) { 2526 sym_print_addr(cp->cmd, 2527 "phase change %x-%x %d@%08x resid=%d.\n", 2528 cmd&7, INB(np, nc_sbcl)&7, (unsigned)olen, 2529 (unsigned)oadr, (unsigned)rest); 2530 goto unexpected_phase; 2531 } 2532 2533 /* 2534 * Choose the correct PM save area. 2535 * 2536 * Look at the PM_SAVE SCRIPT if you want to understand 2537 * this stuff. The equivalent code is implemented in 2538 * SCRIPTS for the 895A, 896 and 1010 that are able to 2539 * handle PM from the SCRIPTS processor. 2540 */ 2541 hflags0 = INB(np, HF_PRT); 2542 hflags = hflags0; 2543 2544 if (hflags & (HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED)) { 2545 if (hflags & HF_IN_PM0) 2546 nxtdsp = scr_to_cpu(cp->phys.pm0.ret); 2547 else if (hflags & HF_IN_PM1) 2548 nxtdsp = scr_to_cpu(cp->phys.pm1.ret); 2549 2550 if (hflags & HF_DP_SAVED) 2551 hflags ^= HF_ACT_PM; 2552 } 2553 2554 if (!(hflags & HF_ACT_PM)) { 2555 pm = &cp->phys.pm0; 2556 newcmd = SCRIPTA_BA(np, pm0_data); 2557 } 2558 else { 2559 pm = &cp->phys.pm1; 2560 newcmd = SCRIPTA_BA(np, pm1_data); 2561 } 2562 2563 hflags &= ~(HF_IN_PM0 | HF_IN_PM1 | HF_DP_SAVED); 2564 if (hflags != hflags0) 2565 OUTB(np, HF_PRT, hflags); 2566 2567 /* 2568 * fillin the phase mismatch context 2569 */ 2570 pm->sg.addr = cpu_to_scr(oadr + olen - rest); 2571 pm->sg.size = cpu_to_scr(rest); 2572 pm->ret = cpu_to_scr(nxtdsp); 2573 2574 /* 2575 * If we have a SWIDE, 2576 * - prepare the address to write the SWIDE from SCRIPTS, 2577 * - compute the SCRIPTS address to restart from, 2578 * - move current data pointer context by one byte. 2579 */ 2580 nxtdsp = SCRIPTA_BA(np, dispatch); 2581 if ((cmd & 7) == 1 && cp && (cp->phys.select.sel_scntl3 & EWS) && 2582 (INB(np, nc_scntl2) & WSR)) { 2583 u32 tmp; 2584 2585 /* 2586 * Set up the table indirect for the MOVE 2587 * of the residual byte and adjust the data 2588 * pointer context. 2589 */ 2590 tmp = scr_to_cpu(pm->sg.addr); 2591 cp->phys.wresid.addr = cpu_to_scr(tmp); 2592 pm->sg.addr = cpu_to_scr(tmp + 1); 2593 tmp = scr_to_cpu(pm->sg.size); 2594 cp->phys.wresid.size = cpu_to_scr((tmp&0xff000000) | 1); 2595 pm->sg.size = cpu_to_scr(tmp - 1); 2596 2597 /* 2598 * If only the residual byte is to be moved, 2599 * no PM context is needed. 2600 */ 2601 if ((tmp&0xffffff) == 1) 2602 newcmd = pm->ret; 2603 2604 /* 2605 * Prepare the address of SCRIPTS that will 2606 * move the residual byte to memory. 2607 */ 2608 nxtdsp = SCRIPTB_BA(np, wsr_ma_helper); 2609 } 2610 2611 if (DEBUG_FLAGS & DEBUG_PHASE) { 2612 sym_print_addr(cp->cmd, "PM %x %x %x / %x %x %x.\n", 2613 hflags0, hflags, newcmd, 2614 (unsigned)scr_to_cpu(pm->sg.addr), 2615 (unsigned)scr_to_cpu(pm->sg.size), 2616 (unsigned)scr_to_cpu(pm->ret)); 2617 } 2618 2619 /* 2620 * Restart the SCRIPTS processor. 2621 */ 2622 sym_set_script_dp (np, cp, newcmd); 2623 OUTL_DSP(np, nxtdsp); 2624 return; 2625 2626 /* 2627 * Unexpected phase changes that occurs when the current phase 2628 * is not a DATA IN or DATA OUT phase are due to error conditions. 2629 * Such event may only happen when the SCRIPTS is using a 2630 * multibyte SCSI MOVE. 2631 * 2632 * Phase change Some possible cause 2633 * 2634 * COMMAND --> MSG IN SCSI parity error detected by target. 2635 * COMMAND --> STATUS Bad command or refused by target. 2636 * MSG OUT --> MSG IN Message rejected by target. 2637 * MSG OUT --> COMMAND Bogus target that discards extended 2638 * negotiation messages. 2639 * 2640 * The code below does not care of the new phase and so 2641 * trusts the target. Why to annoy it ? 2642 * If the interrupted phase is COMMAND phase, we restart at 2643 * dispatcher. 2644 * If a target does not get all the messages after selection, 2645 * the code assumes blindly that the target discards extended 2646 * messages and clears the negotiation status. 2647 * If the target does not want all our response to negotiation, 2648 * we force a SIR_NEGO_PROTO interrupt (it is a hack that avoids 2649 * bloat for such a should_not_happen situation). 2650 * In all other situation, we reset the BUS. 2651 * Are these assumptions reasonnable ? (Wait and see ...) 2652 */ 2653 unexpected_phase: 2654 dsp -= 8; 2655 nxtdsp = 0; 2656 2657 switch (cmd & 7) { 2658 case 2: /* COMMAND phase */ 2659 nxtdsp = SCRIPTA_BA(np, dispatch); 2660 break; 2661 #if 0 2662 case 3: /* STATUS phase */ 2663 nxtdsp = SCRIPTA_BA(np, dispatch); 2664 break; 2665 #endif 2666 case 6: /* MSG OUT phase */ 2667 /* 2668 * If the device may want to use untagged when we want 2669 * tagged, we prepare an IDENTIFY without disc. granted, 2670 * since we will not be able to handle reselect. 2671 * Otherwise, we just don't care. 2672 */ 2673 if (dsp == SCRIPTA_BA(np, send_ident)) { 2674 if (cp->tag != NO_TAG && olen - rest <= 3) { 2675 cp->host_status = HS_BUSY; 2676 np->msgout[0] = IDENTIFY(0, cp->lun); 2677 nxtdsp = SCRIPTB_BA(np, ident_break_atn); 2678 } 2679 else 2680 nxtdsp = SCRIPTB_BA(np, ident_break); 2681 } 2682 else if (dsp == SCRIPTB_BA(np, send_wdtr) || 2683 dsp == SCRIPTB_BA(np, send_sdtr) || 2684 dsp == SCRIPTB_BA(np, send_ppr)) { 2685 nxtdsp = SCRIPTB_BA(np, nego_bad_phase); 2686 if (dsp == SCRIPTB_BA(np, send_ppr)) { 2687 struct scsi_device *dev = cp->cmd->device; 2688 dev->ppr = 0; 2689 } 2690 } 2691 break; 2692 #if 0 2693 case 7: /* MSG IN phase */ 2694 nxtdsp = SCRIPTA_BA(np, clrack); 2695 break; 2696 #endif 2697 } 2698 2699 if (nxtdsp) { 2700 OUTL_DSP(np, nxtdsp); 2701 return; 2702 } 2703 2704 reset_all: 2705 sym_start_reset(np); 2706 } 2707 2708 /* 2709 * chip interrupt handler 2710 * 2711 * In normal situations, interrupt conditions occur one at 2712 * a time. But when something bad happens on the SCSI BUS, 2713 * the chip may raise several interrupt flags before 2714 * stopping and interrupting the CPU. The additionnal 2715 * interrupt flags are stacked in some extra registers 2716 * after the SIP and/or DIP flag has been raised in the 2717 * ISTAT. After the CPU has read the interrupt condition 2718 * flag from SIST or DSTAT, the chip unstacks the other 2719 * interrupt flags and sets the corresponding bits in 2720 * SIST or DSTAT. Since the chip starts stacking once the 2721 * SIP or DIP flag is set, there is a small window of time 2722 * where the stacking does not occur. 2723 * 2724 * Typically, multiple interrupt conditions may happen in 2725 * the following situations: 2726 * 2727 * - SCSI parity error + Phase mismatch (PAR|MA) 2728 * When an parity error is detected in input phase 2729 * and the device switches to msg-in phase inside a 2730 * block MOV. 2731 * - SCSI parity error + Unexpected disconnect (PAR|UDC) 2732 * When a stupid device does not want to handle the 2733 * recovery of an SCSI parity error. 2734 * - Some combinations of STO, PAR, UDC, ... 2735 * When using non compliant SCSI stuff, when user is 2736 * doing non compliant hot tampering on the BUS, when 2737 * something really bad happens to a device, etc ... 2738 * 2739 * The heuristic suggested by SYMBIOS to handle 2740 * multiple interrupts is to try unstacking all 2741 * interrupts conditions and to handle them on some 2742 * priority based on error severity. 2743 * This will work when the unstacking has been 2744 * successful, but we cannot be 100 % sure of that, 2745 * since the CPU may have been faster to unstack than 2746 * the chip is able to stack. Hmmm ... But it seems that 2747 * such a situation is very unlikely to happen. 2748 * 2749 * If this happen, for example STO caught by the CPU 2750 * then UDC happenning before the CPU have restarted 2751 * the SCRIPTS, the driver may wrongly complete the 2752 * same command on UDC, since the SCRIPTS didn't restart 2753 * and the DSA still points to the same command. 2754 * We avoid this situation by setting the DSA to an 2755 * invalid value when the CCB is completed and before 2756 * restarting the SCRIPTS. 2757 * 2758 * Another issue is that we need some section of our 2759 * recovery procedures to be somehow uninterruptible but 2760 * the SCRIPTS processor does not provides such a 2761 * feature. For this reason, we handle recovery preferently 2762 * from the C code and check against some SCRIPTS critical 2763 * sections from the C code. 2764 * 2765 * Hopefully, the interrupt handling of the driver is now 2766 * able to resist to weird BUS error conditions, but donnot 2767 * ask me for any guarantee that it will never fail. :-) 2768 * Use at your own decision and risk. 2769 */ 2770 2771 irqreturn_t sym_interrupt(struct Scsi_Host *shost) 2772 { 2773 struct sym_data *sym_data = shost_priv(shost); 2774 struct sym_hcb *np = sym_data->ncb; 2775 struct pci_dev *pdev = sym_data->pdev; 2776 u_char istat, istatc; 2777 u_char dstat; 2778 u_short sist; 2779 2780 /* 2781 * interrupt on the fly ? 2782 * (SCRIPTS may still be running) 2783 * 2784 * A `dummy read' is needed to ensure that the 2785 * clear of the INTF flag reaches the device 2786 * and that posted writes are flushed to memory 2787 * before the scanning of the DONE queue. 2788 * Note that SCRIPTS also (dummy) read to memory 2789 * prior to deliver the INTF interrupt condition. 2790 */ 2791 istat = INB(np, nc_istat); 2792 if (istat & INTF) { 2793 OUTB(np, nc_istat, (istat & SIGP) | INTF | np->istat_sem); 2794 istat |= INB(np, nc_istat); /* DUMMY READ */ 2795 if (DEBUG_FLAGS & DEBUG_TINY) printf ("F "); 2796 sym_wakeup_done(np); 2797 } 2798 2799 if (!(istat & (SIP|DIP))) 2800 return (istat & INTF) ? IRQ_HANDLED : IRQ_NONE; 2801 2802 #if 0 /* We should never get this one */ 2803 if (istat & CABRT) 2804 OUTB(np, nc_istat, CABRT); 2805 #endif 2806 2807 /* 2808 * PAR and MA interrupts may occur at the same time, 2809 * and we need to know of both in order to handle 2810 * this situation properly. We try to unstack SCSI 2811 * interrupts for that reason. BTW, I dislike a LOT 2812 * such a loop inside the interrupt routine. 2813 * Even if DMA interrupt stacking is very unlikely to 2814 * happen, we also try unstacking these ones, since 2815 * this has no performance impact. 2816 */ 2817 sist = 0; 2818 dstat = 0; 2819 istatc = istat; 2820 do { 2821 if (istatc & SIP) 2822 sist |= INW(np, nc_sist); 2823 if (istatc & DIP) 2824 dstat |= INB(np, nc_dstat); 2825 istatc = INB(np, nc_istat); 2826 istat |= istatc; 2827 2828 /* Prevent deadlock waiting on a condition that may 2829 * never clear. */ 2830 if (unlikely(sist == 0xffff && dstat == 0xff)) { 2831 if (pci_channel_offline(pdev)) 2832 return IRQ_NONE; 2833 } 2834 } while (istatc & (SIP|DIP)); 2835 2836 if (DEBUG_FLAGS & DEBUG_TINY) 2837 printf ("<%d|%x:%x|%x:%x>", 2838 (int)INB(np, nc_scr0), 2839 dstat,sist, 2840 (unsigned)INL(np, nc_dsp), 2841 (unsigned)INL(np, nc_dbc)); 2842 /* 2843 * On paper, a memory read barrier may be needed here to 2844 * prevent out of order LOADs by the CPU from having 2845 * prefetched stale data prior to DMA having occurred. 2846 * And since we are paranoid ... :) 2847 */ 2848 MEMORY_READ_BARRIER(); 2849 2850 /* 2851 * First, interrupts we want to service cleanly. 2852 * 2853 * Phase mismatch (MA) is the most frequent interrupt 2854 * for chip earlier than the 896 and so we have to service 2855 * it as quickly as possible. 2856 * A SCSI parity error (PAR) may be combined with a phase 2857 * mismatch condition (MA). 2858 * Programmed interrupts (SIR) are used to call the C code 2859 * from SCRIPTS. 2860 * The single step interrupt (SSI) is not used in this 2861 * driver. 2862 */ 2863 if (!(sist & (STO|GEN|HTH|SGE|UDC|SBMC|RST)) && 2864 !(dstat & (MDPE|BF|ABRT|IID))) { 2865 if (sist & PAR) sym_int_par (np, sist); 2866 else if (sist & MA) sym_int_ma (np); 2867 else if (dstat & SIR) sym_int_sir(np); 2868 else if (dstat & SSI) OUTONB_STD(); 2869 else goto unknown_int; 2870 return IRQ_HANDLED; 2871 } 2872 2873 /* 2874 * Now, interrupts that donnot happen in normal 2875 * situations and that we may need to recover from. 2876 * 2877 * On SCSI RESET (RST), we reset everything. 2878 * On SCSI BUS MODE CHANGE (SBMC), we complete all 2879 * active CCBs with RESET status, prepare all devices 2880 * for negotiating again and restart the SCRIPTS. 2881 * On STO and UDC, we complete the CCB with the corres- 2882 * ponding status and restart the SCRIPTS. 2883 */ 2884 if (sist & RST) { 2885 printf("%s: SCSI BUS reset detected.\n", sym_name(np)); 2886 sym_start_up(shost, 1); 2887 return IRQ_HANDLED; 2888 } 2889 2890 OUTB(np, nc_ctest3, np->rv_ctest3 | CLF); /* clear dma fifo */ 2891 OUTB(np, nc_stest3, TE|CSF); /* clear scsi fifo */ 2892 2893 if (!(sist & (GEN|HTH|SGE)) && 2894 !(dstat & (MDPE|BF|ABRT|IID))) { 2895 if (sist & SBMC) sym_int_sbmc(shost); 2896 else if (sist & STO) sym_int_sto (np); 2897 else if (sist & UDC) sym_int_udc (np); 2898 else goto unknown_int; 2899 return IRQ_HANDLED; 2900 } 2901 2902 /* 2903 * Now, interrupts we are not able to recover cleanly. 2904 * 2905 * Log message for hard errors. 2906 * Reset everything. 2907 */ 2908 2909 sym_log_hard_error(shost, sist, dstat); 2910 2911 if ((sist & (GEN|HTH|SGE)) || 2912 (dstat & (MDPE|BF|ABRT|IID))) { 2913 sym_start_reset(np); 2914 return IRQ_HANDLED; 2915 } 2916 2917 unknown_int: 2918 /* 2919 * We just miss the cause of the interrupt. :( 2920 * Print a message. The timeout will do the real work. 2921 */ 2922 printf( "%s: unknown interrupt(s) ignored, " 2923 "ISTAT=0x%x DSTAT=0x%x SIST=0x%x\n", 2924 sym_name(np), istat, dstat, sist); 2925 return IRQ_NONE; 2926 } 2927 2928 /* 2929 * Dequeue from the START queue all CCBs that match 2930 * a given target/lun/task condition (-1 means all), 2931 * and move them from the BUSY queue to the COMP queue 2932 * with DID_SOFT_ERROR status condition. 2933 * This function is used during error handling/recovery. 2934 * It is called with SCRIPTS not running. 2935 */ 2936 static int 2937 sym_dequeue_from_squeue(struct sym_hcb *np, int i, int target, int lun, int task) 2938 { 2939 int j; 2940 struct sym_ccb *cp; 2941 2942 /* 2943 * Make sure the starting index is within range. 2944 */ 2945 assert((i >= 0) && (i < 2*MAX_QUEUE)); 2946 2947 /* 2948 * Walk until end of START queue and dequeue every job 2949 * that matches the target/lun/task condition. 2950 */ 2951 j = i; 2952 while (i != np->squeueput) { 2953 cp = sym_ccb_from_dsa(np, scr_to_cpu(np->squeue[i])); 2954 assert(cp); 2955 #ifdef SYM_CONF_IARB_SUPPORT 2956 /* Forget hints for IARB, they may be no longer relevant */ 2957 cp->host_flags &= ~HF_HINT_IARB; 2958 #endif 2959 if ((target == -1 || cp->target == target) && 2960 (lun == -1 || cp->lun == lun) && 2961 (task == -1 || cp->tag == task)) { 2962 sym_set_cam_status(cp->cmd, DID_SOFT_ERROR); 2963 sym_remque(&cp->link_ccbq); 2964 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 2965 } 2966 else { 2967 if (i != j) 2968 np->squeue[j] = np->squeue[i]; 2969 if ((j += 2) >= MAX_QUEUE*2) j = 0; 2970 } 2971 if ((i += 2) >= MAX_QUEUE*2) i = 0; 2972 } 2973 if (i != j) /* Copy back the idle task if needed */ 2974 np->squeue[j] = np->squeue[i]; 2975 np->squeueput = j; /* Update our current start queue pointer */ 2976 2977 return (i - j) / 2; 2978 } 2979 2980 /* 2981 * chip handler for bad SCSI status condition 2982 * 2983 * In case of bad SCSI status, we unqueue all the tasks 2984 * currently queued to the controller but not yet started 2985 * and then restart the SCRIPTS processor immediately. 2986 * 2987 * QUEUE FULL and BUSY conditions are handled the same way. 2988 * Basically all the not yet started tasks are requeued in 2989 * device queue and the queue is frozen until a completion. 2990 * 2991 * For CHECK CONDITION and COMMAND TERMINATED status, we use 2992 * the CCB of the failed command to prepare a REQUEST SENSE 2993 * SCSI command and queue it to the controller queue. 2994 * 2995 * SCRATCHA is assumed to have been loaded with STARTPOS 2996 * before the SCRIPTS called the C code. 2997 */ 2998 static void sym_sir_bad_scsi_status(struct sym_hcb *np, int num, struct sym_ccb *cp) 2999 { 3000 u32 startp; 3001 u_char s_status = cp->ssss_status; 3002 u_char h_flags = cp->host_flags; 3003 int msglen; 3004 int i; 3005 3006 /* 3007 * Compute the index of the next job to start from SCRIPTS. 3008 */ 3009 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4; 3010 3011 /* 3012 * The last CCB queued used for IARB hint may be 3013 * no longer relevant. Forget it. 3014 */ 3015 #ifdef SYM_CONF_IARB_SUPPORT 3016 if (np->last_cp) 3017 np->last_cp = 0; 3018 #endif 3019 3020 /* 3021 * Now deal with the SCSI status. 3022 */ 3023 switch(s_status) { 3024 case S_BUSY: 3025 case S_QUEUE_FULL: 3026 if (sym_verbose >= 2) { 3027 sym_print_addr(cp->cmd, "%s\n", 3028 s_status == S_BUSY ? "BUSY" : "QUEUE FULL\n"); 3029 } 3030 default: /* S_INT, S_INT_COND_MET, S_CONFLICT */ 3031 sym_complete_error (np, cp); 3032 break; 3033 case S_TERMINATED: 3034 case S_CHECK_COND: 3035 /* 3036 * If we get an SCSI error when requesting sense, give up. 3037 */ 3038 if (h_flags & HF_SENSE) { 3039 sym_complete_error (np, cp); 3040 break; 3041 } 3042 3043 /* 3044 * Dequeue all queued CCBs for that device not yet started, 3045 * and restart the SCRIPTS processor immediately. 3046 */ 3047 sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 3048 OUTL_DSP(np, SCRIPTA_BA(np, start)); 3049 3050 /* 3051 * Save some info of the actual IO. 3052 * Compute the data residual. 3053 */ 3054 cp->sv_scsi_status = cp->ssss_status; 3055 cp->sv_xerr_status = cp->xerr_status; 3056 cp->sv_resid = sym_compute_residual(np, cp); 3057 3058 /* 3059 * Prepare all needed data structures for 3060 * requesting sense data. 3061 */ 3062 3063 cp->scsi_smsg2[0] = IDENTIFY(0, cp->lun); 3064 msglen = 1; 3065 3066 /* 3067 * If we are currently using anything different from 3068 * async. 8 bit data transfers with that target, 3069 * start a negotiation, since the device may want 3070 * to report us a UNIT ATTENTION condition due to 3071 * a cause we currently ignore, and we donnot want 3072 * to be stuck with WIDE and/or SYNC data transfer. 3073 * 3074 * cp->nego_status is filled by sym_prepare_nego(). 3075 */ 3076 cp->nego_status = 0; 3077 msglen += sym_prepare_nego(np, cp, &cp->scsi_smsg2[msglen]); 3078 /* 3079 * Message table indirect structure. 3080 */ 3081 cp->phys.smsg.addr = CCB_BA(cp, scsi_smsg2); 3082 cp->phys.smsg.size = cpu_to_scr(msglen); 3083 3084 /* 3085 * sense command 3086 */ 3087 cp->phys.cmd.addr = CCB_BA(cp, sensecmd); 3088 cp->phys.cmd.size = cpu_to_scr(6); 3089 3090 /* 3091 * patch requested size into sense command 3092 */ 3093 cp->sensecmd[0] = REQUEST_SENSE; 3094 cp->sensecmd[1] = 0; 3095 if (cp->cmd->device->scsi_level <= SCSI_2 && cp->lun <= 7) 3096 cp->sensecmd[1] = cp->lun << 5; 3097 cp->sensecmd[4] = SYM_SNS_BBUF_LEN; 3098 cp->data_len = SYM_SNS_BBUF_LEN; 3099 3100 /* 3101 * sense data 3102 */ 3103 memset(cp->sns_bbuf, 0, SYM_SNS_BBUF_LEN); 3104 cp->phys.sense.addr = CCB_BA(cp, sns_bbuf); 3105 cp->phys.sense.size = cpu_to_scr(SYM_SNS_BBUF_LEN); 3106 3107 /* 3108 * requeue the command. 3109 */ 3110 startp = SCRIPTB_BA(np, sdata_in); 3111 3112 cp->phys.head.savep = cpu_to_scr(startp); 3113 cp->phys.head.lastp = cpu_to_scr(startp); 3114 cp->startp = cpu_to_scr(startp); 3115 cp->goalp = cpu_to_scr(startp + 16); 3116 3117 cp->host_xflags = 0; 3118 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 3119 cp->ssss_status = S_ILLEGAL; 3120 cp->host_flags = (HF_SENSE|HF_DATA_IN); 3121 cp->xerr_status = 0; 3122 cp->extra_bytes = 0; 3123 3124 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, select)); 3125 3126 /* 3127 * Requeue the command. 3128 */ 3129 sym_put_start_queue(np, cp); 3130 3131 /* 3132 * Give back to upper layer everything we have dequeued. 3133 */ 3134 sym_flush_comp_queue(np, 0); 3135 break; 3136 } 3137 } 3138 3139 /* 3140 * After a device has accepted some management message 3141 * as BUS DEVICE RESET, ABORT TASK, etc ..., or when 3142 * a device signals a UNIT ATTENTION condition, some 3143 * tasks are thrown away by the device. We are required 3144 * to reflect that on our tasks list since the device 3145 * will never complete these tasks. 3146 * 3147 * This function move from the BUSY queue to the COMP 3148 * queue all disconnected CCBs for a given target that 3149 * match the following criteria: 3150 * - lun=-1 means any logical UNIT otherwise a given one. 3151 * - task=-1 means any task, otherwise a given one. 3152 */ 3153 int sym_clear_tasks(struct sym_hcb *np, int cam_status, int target, int lun, int task) 3154 { 3155 SYM_QUEHEAD qtmp, *qp; 3156 int i = 0; 3157 struct sym_ccb *cp; 3158 3159 /* 3160 * Move the entire BUSY queue to our temporary queue. 3161 */ 3162 sym_que_init(&qtmp); 3163 sym_que_splice(&np->busy_ccbq, &qtmp); 3164 sym_que_init(&np->busy_ccbq); 3165 3166 /* 3167 * Put all CCBs that matches our criteria into 3168 * the COMP queue and put back other ones into 3169 * the BUSY queue. 3170 */ 3171 while ((qp = sym_remque_head(&qtmp)) != NULL) { 3172 struct scsi_cmnd *cmd; 3173 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3174 cmd = cp->cmd; 3175 if (cp->host_status != HS_DISCONNECT || 3176 cp->target != target || 3177 (lun != -1 && cp->lun != lun) || 3178 (task != -1 && 3179 (cp->tag != NO_TAG && cp->scsi_smsg[2] != task))) { 3180 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 3181 continue; 3182 } 3183 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 3184 3185 /* Preserve the software timeout condition */ 3186 if (sym_get_cam_status(cmd) != DID_TIME_OUT) 3187 sym_set_cam_status(cmd, cam_status); 3188 ++i; 3189 #if 0 3190 printf("XXXX TASK @%p CLEARED\n", cp); 3191 #endif 3192 } 3193 return i; 3194 } 3195 3196 /* 3197 * chip handler for TASKS recovery 3198 * 3199 * We cannot safely abort a command, while the SCRIPTS 3200 * processor is running, since we just would be in race 3201 * with it. 3202 * 3203 * As long as we have tasks to abort, we keep the SEM 3204 * bit set in the ISTAT. When this bit is set, the 3205 * SCRIPTS processor interrupts (SIR_SCRIPT_STOPPED) 3206 * each time it enters the scheduler. 3207 * 3208 * If we have to reset a target, clear tasks of a unit, 3209 * or to perform the abort of a disconnected job, we 3210 * restart the SCRIPTS for selecting the target. Once 3211 * selected, the SCRIPTS interrupts (SIR_TARGET_SELECTED). 3212 * If it loses arbitration, the SCRIPTS will interrupt again 3213 * the next time it will enter its scheduler, and so on ... 3214 * 3215 * On SIR_TARGET_SELECTED, we scan for the more 3216 * appropriate thing to do: 3217 * 3218 * - If nothing, we just sent a M_ABORT message to the 3219 * target to get rid of the useless SCSI bus ownership. 3220 * According to the specs, no tasks shall be affected. 3221 * - If the target is to be reset, we send it a M_RESET 3222 * message. 3223 * - If a logical UNIT is to be cleared , we send the 3224 * IDENTIFY(lun) + M_ABORT. 3225 * - If an untagged task is to be aborted, we send the 3226 * IDENTIFY(lun) + M_ABORT. 3227 * - If a tagged task is to be aborted, we send the 3228 * IDENTIFY(lun) + task attributes + M_ABORT_TAG. 3229 * 3230 * Once our 'kiss of death' :) message has been accepted 3231 * by the target, the SCRIPTS interrupts again 3232 * (SIR_ABORT_SENT). On this interrupt, we complete 3233 * all the CCBs that should have been aborted by the 3234 * target according to our message. 3235 */ 3236 static void sym_sir_task_recovery(struct sym_hcb *np, int num) 3237 { 3238 SYM_QUEHEAD *qp; 3239 struct sym_ccb *cp; 3240 struct sym_tcb *tp = NULL; /* gcc isn't quite smart enough yet */ 3241 struct scsi_target *starget; 3242 int target=-1, lun=-1, task; 3243 int i, k; 3244 3245 switch(num) { 3246 /* 3247 * The SCRIPTS processor stopped before starting 3248 * the next command in order to allow us to perform 3249 * some task recovery. 3250 */ 3251 case SIR_SCRIPT_STOPPED: 3252 /* 3253 * Do we have any target to reset or unit to clear ? 3254 */ 3255 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 3256 tp = &np->target[i]; 3257 if (tp->to_reset || 3258 (tp->lun0p && tp->lun0p->to_clear)) { 3259 target = i; 3260 break; 3261 } 3262 if (!tp->lunmp) 3263 continue; 3264 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 3265 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 3266 target = i; 3267 break; 3268 } 3269 } 3270 if (target != -1) 3271 break; 3272 } 3273 3274 /* 3275 * If not, walk the busy queue for any 3276 * disconnected CCB to be aborted. 3277 */ 3278 if (target == -1) { 3279 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3280 cp = sym_que_entry(qp,struct sym_ccb,link_ccbq); 3281 if (cp->host_status != HS_DISCONNECT) 3282 continue; 3283 if (cp->to_abort) { 3284 target = cp->target; 3285 break; 3286 } 3287 } 3288 } 3289 3290 /* 3291 * If some target is to be selected, 3292 * prepare and start the selection. 3293 */ 3294 if (target != -1) { 3295 tp = &np->target[target]; 3296 np->abrt_sel.sel_id = target; 3297 np->abrt_sel.sel_scntl3 = tp->head.wval; 3298 np->abrt_sel.sel_sxfer = tp->head.sval; 3299 OUTL(np, nc_dsa, np->hcb_ba); 3300 OUTL_DSP(np, SCRIPTB_BA(np, sel_for_abort)); 3301 return; 3302 } 3303 3304 /* 3305 * Now look for a CCB to abort that haven't started yet. 3306 * Btw, the SCRIPTS processor is still stopped, so 3307 * we are not in race. 3308 */ 3309 i = 0; 3310 cp = NULL; 3311 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3312 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3313 if (cp->host_status != HS_BUSY && 3314 cp->host_status != HS_NEGOTIATE) 3315 continue; 3316 if (!cp->to_abort) 3317 continue; 3318 #ifdef SYM_CONF_IARB_SUPPORT 3319 /* 3320 * If we are using IMMEDIATE ARBITRATION, we donnot 3321 * want to cancel the last queued CCB, since the 3322 * SCRIPTS may have anticipated the selection. 3323 */ 3324 if (cp == np->last_cp) { 3325 cp->to_abort = 0; 3326 continue; 3327 } 3328 #endif 3329 i = 1; /* Means we have found some */ 3330 break; 3331 } 3332 if (!i) { 3333 /* 3334 * We are done, so we donnot need 3335 * to synchronize with the SCRIPTS anylonger. 3336 * Remove the SEM flag from the ISTAT. 3337 */ 3338 np->istat_sem = 0; 3339 OUTB(np, nc_istat, SIGP); 3340 break; 3341 } 3342 /* 3343 * Compute index of next position in the start 3344 * queue the SCRIPTS intends to start and dequeue 3345 * all CCBs for that device that haven't been started. 3346 */ 3347 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4; 3348 i = sym_dequeue_from_squeue(np, i, cp->target, cp->lun, -1); 3349 3350 /* 3351 * Make sure at least our IO to abort has been dequeued. 3352 */ 3353 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 3354 assert(i && sym_get_cam_status(cp->cmd) == DID_SOFT_ERROR); 3355 #else 3356 sym_remque(&cp->link_ccbq); 3357 sym_insque_tail(&cp->link_ccbq, &np->comp_ccbq); 3358 #endif 3359 /* 3360 * Keep track in cam status of the reason of the abort. 3361 */ 3362 if (cp->to_abort == 2) 3363 sym_set_cam_status(cp->cmd, DID_TIME_OUT); 3364 else 3365 sym_set_cam_status(cp->cmd, DID_ABORT); 3366 3367 /* 3368 * Complete with error everything that we have dequeued. 3369 */ 3370 sym_flush_comp_queue(np, 0); 3371 break; 3372 /* 3373 * The SCRIPTS processor has selected a target 3374 * we may have some manual recovery to perform for. 3375 */ 3376 case SIR_TARGET_SELECTED: 3377 target = INB(np, nc_sdid) & 0xf; 3378 tp = &np->target[target]; 3379 3380 np->abrt_tbl.addr = cpu_to_scr(vtobus(np->abrt_msg)); 3381 3382 /* 3383 * If the target is to be reset, prepare a 3384 * M_RESET message and clear the to_reset flag 3385 * since we donnot expect this operation to fail. 3386 */ 3387 if (tp->to_reset) { 3388 np->abrt_msg[0] = M_RESET; 3389 np->abrt_tbl.size = 1; 3390 tp->to_reset = 0; 3391 break; 3392 } 3393 3394 /* 3395 * Otherwise, look for some logical unit to be cleared. 3396 */ 3397 if (tp->lun0p && tp->lun0p->to_clear) 3398 lun = 0; 3399 else if (tp->lunmp) { 3400 for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { 3401 if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { 3402 lun = k; 3403 break; 3404 } 3405 } 3406 } 3407 3408 /* 3409 * If a logical unit is to be cleared, prepare 3410 * an IDENTIFY(lun) + ABORT MESSAGE. 3411 */ 3412 if (lun != -1) { 3413 struct sym_lcb *lp = sym_lp(tp, lun); 3414 lp->to_clear = 0; /* We don't expect to fail here */ 3415 np->abrt_msg[0] = IDENTIFY(0, lun); 3416 np->abrt_msg[1] = M_ABORT; 3417 np->abrt_tbl.size = 2; 3418 break; 3419 } 3420 3421 /* 3422 * Otherwise, look for some disconnected job to 3423 * abort for this target. 3424 */ 3425 i = 0; 3426 cp = NULL; 3427 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 3428 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 3429 if (cp->host_status != HS_DISCONNECT) 3430 continue; 3431 if (cp->target != target) 3432 continue; 3433 if (!cp->to_abort) 3434 continue; 3435 i = 1; /* Means we have some */ 3436 break; 3437 } 3438 3439 /* 3440 * If we have none, probably since the device has 3441 * completed the command before we won abitration, 3442 * send a M_ABORT message without IDENTIFY. 3443 * According to the specs, the device must just 3444 * disconnect the BUS and not abort any task. 3445 */ 3446 if (!i) { 3447 np->abrt_msg[0] = M_ABORT; 3448 np->abrt_tbl.size = 1; 3449 break; 3450 } 3451 3452 /* 3453 * We have some task to abort. 3454 * Set the IDENTIFY(lun) 3455 */ 3456 np->abrt_msg[0] = IDENTIFY(0, cp->lun); 3457 3458 /* 3459 * If we want to abort an untagged command, we 3460 * will send a IDENTIFY + M_ABORT. 3461 * Otherwise (tagged command), we will send 3462 * a IDENTITFY + task attributes + ABORT TAG. 3463 */ 3464 if (cp->tag == NO_TAG) { 3465 np->abrt_msg[1] = M_ABORT; 3466 np->abrt_tbl.size = 2; 3467 } else { 3468 np->abrt_msg[1] = cp->scsi_smsg[1]; 3469 np->abrt_msg[2] = cp->scsi_smsg[2]; 3470 np->abrt_msg[3] = M_ABORT_TAG; 3471 np->abrt_tbl.size = 4; 3472 } 3473 /* 3474 * Keep track of software timeout condition, since the 3475 * peripheral driver may not count retries on abort 3476 * conditions not due to timeout. 3477 */ 3478 if (cp->to_abort == 2) 3479 sym_set_cam_status(cp->cmd, DID_TIME_OUT); 3480 cp->to_abort = 0; /* We donnot expect to fail here */ 3481 break; 3482 3483 /* 3484 * The target has accepted our message and switched 3485 * to BUS FREE phase as we expected. 3486 */ 3487 case SIR_ABORT_SENT: 3488 target = INB(np, nc_sdid) & 0xf; 3489 tp = &np->target[target]; 3490 starget = tp->starget; 3491 3492 /* 3493 ** If we didn't abort anything, leave here. 3494 */ 3495 if (np->abrt_msg[0] == M_ABORT) 3496 break; 3497 3498 /* 3499 * If we sent a M_RESET, then a hardware reset has 3500 * been performed by the target. 3501 * - Reset everything to async 8 bit 3502 * - Tell ourself to negotiate next time :-) 3503 * - Prepare to clear all disconnected CCBs for 3504 * this target from our task list (lun=task=-1) 3505 */ 3506 lun = -1; 3507 task = -1; 3508 if (np->abrt_msg[0] == M_RESET) { 3509 tp->head.sval = 0; 3510 tp->head.wval = np->rv_scntl3; 3511 tp->head.uval = 0; 3512 spi_period(starget) = 0; 3513 spi_offset(starget) = 0; 3514 spi_width(starget) = 0; 3515 spi_iu(starget) = 0; 3516 spi_dt(starget) = 0; 3517 spi_qas(starget) = 0; 3518 tp->tgoal.check_nego = 1; 3519 } 3520 3521 /* 3522 * Otherwise, check for the LUN and TASK(s) 3523 * concerned by the cancelation. 3524 * If it is not ABORT_TAG then it is CLEAR_QUEUE 3525 * or an ABORT message :-) 3526 */ 3527 else { 3528 lun = np->abrt_msg[0] & 0x3f; 3529 if (np->abrt_msg[1] == M_ABORT_TAG) 3530 task = np->abrt_msg[2]; 3531 } 3532 3533 /* 3534 * Complete all the CCBs the device should have 3535 * aborted due to our 'kiss of death' message. 3536 */ 3537 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4; 3538 sym_dequeue_from_squeue(np, i, target, lun, -1); 3539 sym_clear_tasks(np, DID_ABORT, target, lun, task); 3540 sym_flush_comp_queue(np, 0); 3541 3542 /* 3543 * If we sent a BDR, make upper layer aware of that. 3544 */ 3545 if (np->abrt_msg[0] == M_RESET) 3546 starget_printk(KERN_NOTICE, starget, 3547 "has been reset\n"); 3548 break; 3549 } 3550 3551 /* 3552 * Print to the log the message we intend to send. 3553 */ 3554 if (num == SIR_TARGET_SELECTED) { 3555 dev_info(&tp->starget->dev, "control msgout:"); 3556 sym_printl_hex(np->abrt_msg, np->abrt_tbl.size); 3557 np->abrt_tbl.size = cpu_to_scr(np->abrt_tbl.size); 3558 } 3559 3560 /* 3561 * Let the SCRIPTS processor continue. 3562 */ 3563 OUTONB_STD(); 3564 } 3565 3566 /* 3567 * Gerard's alchemy:) that deals with with the data 3568 * pointer for both MDP and the residual calculation. 3569 * 3570 * I didn't want to bloat the code by more than 200 3571 * lines for the handling of both MDP and the residual. 3572 * This has been achieved by using a data pointer 3573 * representation consisting in an index in the data 3574 * array (dp_sg) and a negative offset (dp_ofs) that 3575 * have the following meaning: 3576 * 3577 * - dp_sg = SYM_CONF_MAX_SG 3578 * we are at the end of the data script. 3579 * - dp_sg < SYM_CONF_MAX_SG 3580 * dp_sg points to the next entry of the scatter array 3581 * we want to transfer. 3582 * - dp_ofs < 0 3583 * dp_ofs represents the residual of bytes of the 3584 * previous entry scatter entry we will send first. 3585 * - dp_ofs = 0 3586 * no residual to send first. 3587 * 3588 * The function sym_evaluate_dp() accepts an arbitray 3589 * offset (basically from the MDP message) and returns 3590 * the corresponding values of dp_sg and dp_ofs. 3591 */ 3592 3593 static int sym_evaluate_dp(struct sym_hcb *np, struct sym_ccb *cp, u32 scr, int *ofs) 3594 { 3595 u32 dp_scr; 3596 int dp_ofs, dp_sg, dp_sgmin; 3597 int tmp; 3598 struct sym_pmc *pm; 3599 3600 /* 3601 * Compute the resulted data pointer in term of a script 3602 * address within some DATA script and a signed byte offset. 3603 */ 3604 dp_scr = scr; 3605 dp_ofs = *ofs; 3606 if (dp_scr == SCRIPTA_BA(np, pm0_data)) 3607 pm = &cp->phys.pm0; 3608 else if (dp_scr == SCRIPTA_BA(np, pm1_data)) 3609 pm = &cp->phys.pm1; 3610 else 3611 pm = NULL; 3612 3613 if (pm) { 3614 dp_scr = scr_to_cpu(pm->ret); 3615 dp_ofs -= scr_to_cpu(pm->sg.size) & 0x00ffffff; 3616 } 3617 3618 /* 3619 * If we are auto-sensing, then we are done. 3620 */ 3621 if (cp->host_flags & HF_SENSE) { 3622 *ofs = dp_ofs; 3623 return 0; 3624 } 3625 3626 /* 3627 * Deduce the index of the sg entry. 3628 * Keep track of the index of the first valid entry. 3629 * If result is dp_sg = SYM_CONF_MAX_SG, then we are at the 3630 * end of the data. 3631 */ 3632 tmp = scr_to_cpu(cp->goalp); 3633 dp_sg = SYM_CONF_MAX_SG; 3634 if (dp_scr != tmp) 3635 dp_sg -= (tmp - 8 - (int)dp_scr) / (2*4); 3636 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 3637 3638 /* 3639 * Move to the sg entry the data pointer belongs to. 3640 * 3641 * If we are inside the data area, we expect result to be: 3642 * 3643 * Either, 3644 * dp_ofs = 0 and dp_sg is the index of the sg entry 3645 * the data pointer belongs to (or the end of the data) 3646 * Or, 3647 * dp_ofs < 0 and dp_sg is the index of the sg entry 3648 * the data pointer belongs to + 1. 3649 */ 3650 if (dp_ofs < 0) { 3651 int n; 3652 while (dp_sg > dp_sgmin) { 3653 --dp_sg; 3654 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 3655 n = dp_ofs + (tmp & 0xffffff); 3656 if (n > 0) { 3657 ++dp_sg; 3658 break; 3659 } 3660 dp_ofs = n; 3661 } 3662 } 3663 else if (dp_ofs > 0) { 3664 while (dp_sg < SYM_CONF_MAX_SG) { 3665 tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 3666 dp_ofs -= (tmp & 0xffffff); 3667 ++dp_sg; 3668 if (dp_ofs <= 0) 3669 break; 3670 } 3671 } 3672 3673 /* 3674 * Make sure the data pointer is inside the data area. 3675 * If not, return some error. 3676 */ 3677 if (dp_sg < dp_sgmin || (dp_sg == dp_sgmin && dp_ofs < 0)) 3678 goto out_err; 3679 else if (dp_sg > SYM_CONF_MAX_SG || 3680 (dp_sg == SYM_CONF_MAX_SG && dp_ofs > 0)) 3681 goto out_err; 3682 3683 /* 3684 * Save the extreme pointer if needed. 3685 */ 3686 if (dp_sg > cp->ext_sg || 3687 (dp_sg == cp->ext_sg && dp_ofs > cp->ext_ofs)) { 3688 cp->ext_sg = dp_sg; 3689 cp->ext_ofs = dp_ofs; 3690 } 3691 3692 /* 3693 * Return data. 3694 */ 3695 *ofs = dp_ofs; 3696 return dp_sg; 3697 3698 out_err: 3699 return -1; 3700 } 3701 3702 /* 3703 * chip handler for MODIFY DATA POINTER MESSAGE 3704 * 3705 * We also call this function on IGNORE WIDE RESIDUE 3706 * messages that do not match a SWIDE full condition. 3707 * Btw, we assume in that situation that such a message 3708 * is equivalent to a MODIFY DATA POINTER (offset=-1). 3709 */ 3710 3711 static void sym_modify_dp(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp, int ofs) 3712 { 3713 int dp_ofs = ofs; 3714 u32 dp_scr = sym_get_script_dp (np, cp); 3715 u32 dp_ret; 3716 u32 tmp; 3717 u_char hflags; 3718 int dp_sg; 3719 struct sym_pmc *pm; 3720 3721 /* 3722 * Not supported for auto-sense. 3723 */ 3724 if (cp->host_flags & HF_SENSE) 3725 goto out_reject; 3726 3727 /* 3728 * Apply our alchemy:) (see comments in sym_evaluate_dp()), 3729 * to the resulted data pointer. 3730 */ 3731 dp_sg = sym_evaluate_dp(np, cp, dp_scr, &dp_ofs); 3732 if (dp_sg < 0) 3733 goto out_reject; 3734 3735 /* 3736 * And our alchemy:) allows to easily calculate the data 3737 * script address we want to return for the next data phase. 3738 */ 3739 dp_ret = cpu_to_scr(cp->goalp); 3740 dp_ret = dp_ret - 8 - (SYM_CONF_MAX_SG - dp_sg) * (2*4); 3741 3742 /* 3743 * If offset / scatter entry is zero we donnot need 3744 * a context for the new current data pointer. 3745 */ 3746 if (dp_ofs == 0) { 3747 dp_scr = dp_ret; 3748 goto out_ok; 3749 } 3750 3751 /* 3752 * Get a context for the new current data pointer. 3753 */ 3754 hflags = INB(np, HF_PRT); 3755 3756 if (hflags & HF_DP_SAVED) 3757 hflags ^= HF_ACT_PM; 3758 3759 if (!(hflags & HF_ACT_PM)) { 3760 pm = &cp->phys.pm0; 3761 dp_scr = SCRIPTA_BA(np, pm0_data); 3762 } 3763 else { 3764 pm = &cp->phys.pm1; 3765 dp_scr = SCRIPTA_BA(np, pm1_data); 3766 } 3767 3768 hflags &= ~(HF_DP_SAVED); 3769 3770 OUTB(np, HF_PRT, hflags); 3771 3772 /* 3773 * Set up the new current data pointer. 3774 * ofs < 0 there, and for the next data phase, we 3775 * want to transfer part of the data of the sg entry 3776 * corresponding to index dp_sg-1 prior to returning 3777 * to the main data script. 3778 */ 3779 pm->ret = cpu_to_scr(dp_ret); 3780 tmp = scr_to_cpu(cp->phys.data[dp_sg-1].addr); 3781 tmp += scr_to_cpu(cp->phys.data[dp_sg-1].size) + dp_ofs; 3782 pm->sg.addr = cpu_to_scr(tmp); 3783 pm->sg.size = cpu_to_scr(-dp_ofs); 3784 3785 out_ok: 3786 sym_set_script_dp (np, cp, dp_scr); 3787 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 3788 return; 3789 3790 out_reject: 3791 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad)); 3792 } 3793 3794 3795 /* 3796 * chip calculation of the data residual. 3797 * 3798 * As I used to say, the requirement of data residual 3799 * in SCSI is broken, useless and cannot be achieved 3800 * without huge complexity. 3801 * But most OSes and even the official CAM require it. 3802 * When stupidity happens to be so widely spread inside 3803 * a community, it gets hard to convince. 3804 * 3805 * Anyway, I don't care, since I am not going to use 3806 * any software that considers this data residual as 3807 * a relevant information. :) 3808 */ 3809 3810 int sym_compute_residual(struct sym_hcb *np, struct sym_ccb *cp) 3811 { 3812 int dp_sg, dp_sgmin, resid = 0; 3813 int dp_ofs = 0; 3814 3815 /* 3816 * Check for some data lost or just thrown away. 3817 * We are not required to be quite accurate in this 3818 * situation. Btw, if we are odd for output and the 3819 * device claims some more data, it may well happen 3820 * than our residual be zero. :-) 3821 */ 3822 if (cp->xerr_status & (XE_EXTRA_DATA|XE_SODL_UNRUN|XE_SWIDE_OVRUN)) { 3823 if (cp->xerr_status & XE_EXTRA_DATA) 3824 resid -= cp->extra_bytes; 3825 if (cp->xerr_status & XE_SODL_UNRUN) 3826 ++resid; 3827 if (cp->xerr_status & XE_SWIDE_OVRUN) 3828 --resid; 3829 } 3830 3831 /* 3832 * If all data has been transferred, 3833 * there is no residual. 3834 */ 3835 if (cp->phys.head.lastp == cp->goalp) 3836 return resid; 3837 3838 /* 3839 * If no data transfer occurs, or if the data 3840 * pointer is weird, return full residual. 3841 */ 3842 if (cp->startp == cp->phys.head.lastp || 3843 sym_evaluate_dp(np, cp, scr_to_cpu(cp->phys.head.lastp), 3844 &dp_ofs) < 0) { 3845 return cp->data_len - cp->odd_byte_adjustment; 3846 } 3847 3848 /* 3849 * If we were auto-sensing, then we are done. 3850 */ 3851 if (cp->host_flags & HF_SENSE) { 3852 return -dp_ofs; 3853 } 3854 3855 /* 3856 * We are now full comfortable in the computation 3857 * of the data residual (2's complement). 3858 */ 3859 dp_sgmin = SYM_CONF_MAX_SG - cp->segments; 3860 resid = -cp->ext_ofs; 3861 for (dp_sg = cp->ext_sg; dp_sg < SYM_CONF_MAX_SG; ++dp_sg) { 3862 u_int tmp = scr_to_cpu(cp->phys.data[dp_sg].size); 3863 resid += (tmp & 0xffffff); 3864 } 3865 3866 resid -= cp->odd_byte_adjustment; 3867 3868 /* 3869 * Hopefully, the result is not too wrong. 3870 */ 3871 return resid; 3872 } 3873 3874 /* 3875 * Negotiation for WIDE and SYNCHRONOUS DATA TRANSFER. 3876 * 3877 * When we try to negotiate, we append the negotiation message 3878 * to the identify and (maybe) simple tag message. 3879 * The host status field is set to HS_NEGOTIATE to mark this 3880 * situation. 3881 * 3882 * If the target doesn't answer this message immediately 3883 * (as required by the standard), the SIR_NEGO_FAILED interrupt 3884 * will be raised eventually. 3885 * The handler removes the HS_NEGOTIATE status, and sets the 3886 * negotiated value to the default (async / nowide). 3887 * 3888 * If we receive a matching answer immediately, we check it 3889 * for validity, and set the values. 3890 * 3891 * If we receive a Reject message immediately, we assume the 3892 * negotiation has failed, and fall back to standard values. 3893 * 3894 * If we receive a negotiation message while not in HS_NEGOTIATE 3895 * state, it's a target initiated negotiation. We prepare a 3896 * (hopefully) valid answer, set our parameters, and send back 3897 * this answer to the target. 3898 * 3899 * If the target doesn't fetch the answer (no message out phase), 3900 * we assume the negotiation has failed, and fall back to default 3901 * settings (SIR_NEGO_PROTO interrupt). 3902 * 3903 * When we set the values, we adjust them in all ccbs belonging 3904 * to this target, in the controller's register, and in the "phys" 3905 * field of the controller's struct sym_hcb. 3906 */ 3907 3908 /* 3909 * chip handler for SYNCHRONOUS DATA TRANSFER REQUEST (SDTR) message. 3910 */ 3911 static int 3912 sym_sync_nego_check(struct sym_hcb *np, int req, struct sym_ccb *cp) 3913 { 3914 int target = cp->target; 3915 u_char chg, ofs, per, fak, div; 3916 3917 if (DEBUG_FLAGS & DEBUG_NEGO) { 3918 sym_print_nego_msg(np, target, "sync msgin", np->msgin); 3919 } 3920 3921 /* 3922 * Get requested values. 3923 */ 3924 chg = 0; 3925 per = np->msgin[3]; 3926 ofs = np->msgin[4]; 3927 3928 /* 3929 * Check values against our limits. 3930 */ 3931 if (ofs) { 3932 if (ofs > np->maxoffs) 3933 {chg = 1; ofs = np->maxoffs;} 3934 } 3935 3936 if (ofs) { 3937 if (per < np->minsync) 3938 {chg = 1; per = np->minsync;} 3939 } 3940 3941 /* 3942 * Get new chip synchronous parameters value. 3943 */ 3944 div = fak = 0; 3945 if (ofs && sym_getsync(np, 0, per, &div, &fak) < 0) 3946 goto reject_it; 3947 3948 if (DEBUG_FLAGS & DEBUG_NEGO) { 3949 sym_print_addr(cp->cmd, 3950 "sdtr: ofs=%d per=%d div=%d fak=%d chg=%d.\n", 3951 ofs, per, div, fak, chg); 3952 } 3953 3954 /* 3955 * If it was an answer we want to change, 3956 * then it isn't acceptable. Reject it. 3957 */ 3958 if (!req && chg) 3959 goto reject_it; 3960 3961 /* 3962 * Apply new values. 3963 */ 3964 sym_setsync (np, target, ofs, per, div, fak); 3965 3966 /* 3967 * It was an answer. We are done. 3968 */ 3969 if (!req) 3970 return 0; 3971 3972 /* 3973 * It was a request. Prepare an answer message. 3974 */ 3975 spi_populate_sync_msg(np->msgout, per, ofs); 3976 3977 if (DEBUG_FLAGS & DEBUG_NEGO) { 3978 sym_print_nego_msg(np, target, "sync msgout", np->msgout); 3979 } 3980 3981 np->msgin [0] = M_NOOP; 3982 3983 return 0; 3984 3985 reject_it: 3986 sym_setsync (np, target, 0, 0, 0, 0); 3987 return -1; 3988 } 3989 3990 static void sym_sync_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp) 3991 { 3992 int req = 1; 3993 int result; 3994 3995 /* 3996 * Request or answer ? 3997 */ 3998 if (INB(np, HS_PRT) == HS_NEGOTIATE) { 3999 OUTB(np, HS_PRT, HS_BUSY); 4000 if (cp->nego_status && cp->nego_status != NS_SYNC) 4001 goto reject_it; 4002 req = 0; 4003 } 4004 4005 /* 4006 * Check and apply new values. 4007 */ 4008 result = sym_sync_nego_check(np, req, cp); 4009 if (result) /* Not acceptable, reject it */ 4010 goto reject_it; 4011 if (req) { /* Was a request, send response. */ 4012 cp->nego_status = NS_SYNC; 4013 OUTL_DSP(np, SCRIPTB_BA(np, sdtr_resp)); 4014 } 4015 else /* Was a response, we are done. */ 4016 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 4017 return; 4018 4019 reject_it: 4020 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad)); 4021 } 4022 4023 /* 4024 * chip handler for PARALLEL PROTOCOL REQUEST (PPR) message. 4025 */ 4026 static int 4027 sym_ppr_nego_check(struct sym_hcb *np, int req, int target) 4028 { 4029 struct sym_tcb *tp = &np->target[target]; 4030 unsigned char fak, div; 4031 int dt, chg = 0; 4032 4033 unsigned char per = np->msgin[3]; 4034 unsigned char ofs = np->msgin[5]; 4035 unsigned char wide = np->msgin[6]; 4036 unsigned char opts = np->msgin[7] & PPR_OPT_MASK; 4037 4038 if (DEBUG_FLAGS & DEBUG_NEGO) { 4039 sym_print_nego_msg(np, target, "ppr msgin", np->msgin); 4040 } 4041 4042 /* 4043 * Check values against our limits. 4044 */ 4045 if (wide > np->maxwide) { 4046 chg = 1; 4047 wide = np->maxwide; 4048 } 4049 if (!wide || !(np->features & FE_U3EN)) 4050 opts = 0; 4051 4052 if (opts != (np->msgin[7] & PPR_OPT_MASK)) 4053 chg = 1; 4054 4055 dt = opts & PPR_OPT_DT; 4056 4057 if (ofs) { 4058 unsigned char maxoffs = dt ? np->maxoffs_dt : np->maxoffs; 4059 if (ofs > maxoffs) { 4060 chg = 1; 4061 ofs = maxoffs; 4062 } 4063 } 4064 4065 if (ofs) { 4066 unsigned char minsync = dt ? np->minsync_dt : np->minsync; 4067 if (per < minsync) { 4068 chg = 1; 4069 per = minsync; 4070 } 4071 } 4072 4073 /* 4074 * Get new chip synchronous parameters value. 4075 */ 4076 div = fak = 0; 4077 if (ofs && sym_getsync(np, dt, per, &div, &fak) < 0) 4078 goto reject_it; 4079 4080 /* 4081 * If it was an answer we want to change, 4082 * then it isn't acceptable. Reject it. 4083 */ 4084 if (!req && chg) 4085 goto reject_it; 4086 4087 /* 4088 * Apply new values. 4089 */ 4090 sym_setpprot(np, target, opts, ofs, per, wide, div, fak); 4091 4092 /* 4093 * It was an answer. We are done. 4094 */ 4095 if (!req) 4096 return 0; 4097 4098 /* 4099 * It was a request. Prepare an answer message. 4100 */ 4101 spi_populate_ppr_msg(np->msgout, per, ofs, wide, opts); 4102 4103 if (DEBUG_FLAGS & DEBUG_NEGO) { 4104 sym_print_nego_msg(np, target, "ppr msgout", np->msgout); 4105 } 4106 4107 np->msgin [0] = M_NOOP; 4108 4109 return 0; 4110 4111 reject_it: 4112 sym_setpprot (np, target, 0, 0, 0, 0, 0, 0); 4113 /* 4114 * If it is a device response that should result in 4115 * ST, we may want to try a legacy negotiation later. 4116 */ 4117 if (!req && !opts) { 4118 tp->tgoal.period = per; 4119 tp->tgoal.offset = ofs; 4120 tp->tgoal.width = wide; 4121 tp->tgoal.iu = tp->tgoal.dt = tp->tgoal.qas = 0; 4122 tp->tgoal.check_nego = 1; 4123 } 4124 return -1; 4125 } 4126 4127 static void sym_ppr_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp) 4128 { 4129 int req = 1; 4130 int result; 4131 4132 /* 4133 * Request or answer ? 4134 */ 4135 if (INB(np, HS_PRT) == HS_NEGOTIATE) { 4136 OUTB(np, HS_PRT, HS_BUSY); 4137 if (cp->nego_status && cp->nego_status != NS_PPR) 4138 goto reject_it; 4139 req = 0; 4140 } 4141 4142 /* 4143 * Check and apply new values. 4144 */ 4145 result = sym_ppr_nego_check(np, req, cp->target); 4146 if (result) /* Not acceptable, reject it */ 4147 goto reject_it; 4148 if (req) { /* Was a request, send response. */ 4149 cp->nego_status = NS_PPR; 4150 OUTL_DSP(np, SCRIPTB_BA(np, ppr_resp)); 4151 } 4152 else /* Was a response, we are done. */ 4153 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 4154 return; 4155 4156 reject_it: 4157 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad)); 4158 } 4159 4160 /* 4161 * chip handler for WIDE DATA TRANSFER REQUEST (WDTR) message. 4162 */ 4163 static int 4164 sym_wide_nego_check(struct sym_hcb *np, int req, struct sym_ccb *cp) 4165 { 4166 int target = cp->target; 4167 u_char chg, wide; 4168 4169 if (DEBUG_FLAGS & DEBUG_NEGO) { 4170 sym_print_nego_msg(np, target, "wide msgin", np->msgin); 4171 } 4172 4173 /* 4174 * Get requested values. 4175 */ 4176 chg = 0; 4177 wide = np->msgin[3]; 4178 4179 /* 4180 * Check values against our limits. 4181 */ 4182 if (wide > np->maxwide) { 4183 chg = 1; 4184 wide = np->maxwide; 4185 } 4186 4187 if (DEBUG_FLAGS & DEBUG_NEGO) { 4188 sym_print_addr(cp->cmd, "wdtr: wide=%d chg=%d.\n", 4189 wide, chg); 4190 } 4191 4192 /* 4193 * If it was an answer we want to change, 4194 * then it isn't acceptable. Reject it. 4195 */ 4196 if (!req && chg) 4197 goto reject_it; 4198 4199 /* 4200 * Apply new values. 4201 */ 4202 sym_setwide (np, target, wide); 4203 4204 /* 4205 * It was an answer. We are done. 4206 */ 4207 if (!req) 4208 return 0; 4209 4210 /* 4211 * It was a request. Prepare an answer message. 4212 */ 4213 spi_populate_width_msg(np->msgout, wide); 4214 4215 np->msgin [0] = M_NOOP; 4216 4217 if (DEBUG_FLAGS & DEBUG_NEGO) { 4218 sym_print_nego_msg(np, target, "wide msgout", np->msgout); 4219 } 4220 4221 return 0; 4222 4223 reject_it: 4224 return -1; 4225 } 4226 4227 static void sym_wide_nego(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp) 4228 { 4229 int req = 1; 4230 int result; 4231 4232 /* 4233 * Request or answer ? 4234 */ 4235 if (INB(np, HS_PRT) == HS_NEGOTIATE) { 4236 OUTB(np, HS_PRT, HS_BUSY); 4237 if (cp->nego_status && cp->nego_status != NS_WIDE) 4238 goto reject_it; 4239 req = 0; 4240 } 4241 4242 /* 4243 * Check and apply new values. 4244 */ 4245 result = sym_wide_nego_check(np, req, cp); 4246 if (result) /* Not acceptable, reject it */ 4247 goto reject_it; 4248 if (req) { /* Was a request, send response. */ 4249 cp->nego_status = NS_WIDE; 4250 OUTL_DSP(np, SCRIPTB_BA(np, wdtr_resp)); 4251 } else { /* Was a response. */ 4252 /* 4253 * Negotiate for SYNC immediately after WIDE response. 4254 * This allows to negotiate for both WIDE and SYNC on 4255 * a single SCSI command (Suggested by Justin Gibbs). 4256 */ 4257 if (tp->tgoal.offset) { 4258 spi_populate_sync_msg(np->msgout, tp->tgoal.period, 4259 tp->tgoal.offset); 4260 4261 if (DEBUG_FLAGS & DEBUG_NEGO) { 4262 sym_print_nego_msg(np, cp->target, 4263 "sync msgout", np->msgout); 4264 } 4265 4266 cp->nego_status = NS_SYNC; 4267 OUTB(np, HS_PRT, HS_NEGOTIATE); 4268 OUTL_DSP(np, SCRIPTB_BA(np, sdtr_resp)); 4269 return; 4270 } else 4271 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 4272 } 4273 4274 return; 4275 4276 reject_it: 4277 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad)); 4278 } 4279 4280 /* 4281 * Reset DT, SYNC or WIDE to default settings. 4282 * 4283 * Called when a negotiation does not succeed either 4284 * on rejection or on protocol error. 4285 * 4286 * A target that understands a PPR message should never 4287 * reject it, and messing with it is very unlikely. 4288 * So, if a PPR makes problems, we may just want to 4289 * try a legacy negotiation later. 4290 */ 4291 static void sym_nego_default(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp) 4292 { 4293 switch (cp->nego_status) { 4294 case NS_PPR: 4295 #if 0 4296 sym_setpprot (np, cp->target, 0, 0, 0, 0, 0, 0); 4297 #else 4298 if (tp->tgoal.period < np->minsync) 4299 tp->tgoal.period = np->minsync; 4300 if (tp->tgoal.offset > np->maxoffs) 4301 tp->tgoal.offset = np->maxoffs; 4302 tp->tgoal.iu = tp->tgoal.dt = tp->tgoal.qas = 0; 4303 tp->tgoal.check_nego = 1; 4304 #endif 4305 break; 4306 case NS_SYNC: 4307 sym_setsync (np, cp->target, 0, 0, 0, 0); 4308 break; 4309 case NS_WIDE: 4310 sym_setwide (np, cp->target, 0); 4311 break; 4312 } 4313 np->msgin [0] = M_NOOP; 4314 np->msgout[0] = M_NOOP; 4315 cp->nego_status = 0; 4316 } 4317 4318 /* 4319 * chip handler for MESSAGE REJECT received in response to 4320 * PPR, WIDE or SYNCHRONOUS negotiation. 4321 */ 4322 static void sym_nego_rejected(struct sym_hcb *np, struct sym_tcb *tp, struct sym_ccb *cp) 4323 { 4324 sym_nego_default(np, tp, cp); 4325 OUTB(np, HS_PRT, HS_BUSY); 4326 } 4327 4328 /* 4329 * chip exception handler for programmed interrupts. 4330 */ 4331 static void sym_int_sir(struct sym_hcb *np) 4332 { 4333 u_char num = INB(np, nc_dsps); 4334 u32 dsa = INL(np, nc_dsa); 4335 struct sym_ccb *cp = sym_ccb_from_dsa(np, dsa); 4336 u_char target = INB(np, nc_sdid) & 0x0f; 4337 struct sym_tcb *tp = &np->target[target]; 4338 int tmp; 4339 4340 if (DEBUG_FLAGS & DEBUG_TINY) printf ("I#%d", num); 4341 4342 switch (num) { 4343 #if SYM_CONF_DMA_ADDRESSING_MODE == 2 4344 /* 4345 * SCRIPTS tell us that we may have to update 4346 * 64 bit DMA segment registers. 4347 */ 4348 case SIR_DMAP_DIRTY: 4349 sym_update_dmap_regs(np); 4350 goto out; 4351 #endif 4352 /* 4353 * Command has been completed with error condition 4354 * or has been auto-sensed. 4355 */ 4356 case SIR_COMPLETE_ERROR: 4357 sym_complete_error(np, cp); 4358 return; 4359 /* 4360 * The C code is currently trying to recover from something. 4361 * Typically, user want to abort some command. 4362 */ 4363 case SIR_SCRIPT_STOPPED: 4364 case SIR_TARGET_SELECTED: 4365 case SIR_ABORT_SENT: 4366 sym_sir_task_recovery(np, num); 4367 return; 4368 /* 4369 * The device didn't go to MSG OUT phase after having 4370 * been selected with ATN. We do not want to handle that. 4371 */ 4372 case SIR_SEL_ATN_NO_MSG_OUT: 4373 scmd_printk(KERN_WARNING, cp->cmd, 4374 "No MSG OUT phase after selection with ATN\n"); 4375 goto out_stuck; 4376 /* 4377 * The device didn't switch to MSG IN phase after 4378 * having reselected the initiator. 4379 */ 4380 case SIR_RESEL_NO_MSG_IN: 4381 scmd_printk(KERN_WARNING, cp->cmd, 4382 "No MSG IN phase after reselection\n"); 4383 goto out_stuck; 4384 /* 4385 * After reselection, the device sent a message that wasn't 4386 * an IDENTIFY. 4387 */ 4388 case SIR_RESEL_NO_IDENTIFY: 4389 scmd_printk(KERN_WARNING, cp->cmd, 4390 "No IDENTIFY after reselection\n"); 4391 goto out_stuck; 4392 /* 4393 * The device reselected a LUN we do not know about. 4394 */ 4395 case SIR_RESEL_BAD_LUN: 4396 np->msgout[0] = M_RESET; 4397 goto out; 4398 /* 4399 * The device reselected for an untagged nexus and we 4400 * haven't any. 4401 */ 4402 case SIR_RESEL_BAD_I_T_L: 4403 np->msgout[0] = M_ABORT; 4404 goto out; 4405 /* 4406 * The device reselected for a tagged nexus that we do not have. 4407 */ 4408 case SIR_RESEL_BAD_I_T_L_Q: 4409 np->msgout[0] = M_ABORT_TAG; 4410 goto out; 4411 /* 4412 * The SCRIPTS let us know that the device has grabbed 4413 * our message and will abort the job. 4414 */ 4415 case SIR_RESEL_ABORTED: 4416 np->lastmsg = np->msgout[0]; 4417 np->msgout[0] = M_NOOP; 4418 scmd_printk(KERN_WARNING, cp->cmd, 4419 "message %x sent on bad reselection\n", np->lastmsg); 4420 goto out; 4421 /* 4422 * The SCRIPTS let us know that a message has been 4423 * successfully sent to the device. 4424 */ 4425 case SIR_MSG_OUT_DONE: 4426 np->lastmsg = np->msgout[0]; 4427 np->msgout[0] = M_NOOP; 4428 /* Should we really care of that */ 4429 if (np->lastmsg == M_PARITY || np->lastmsg == M_ID_ERROR) { 4430 if (cp) { 4431 cp->xerr_status &= ~XE_PARITY_ERR; 4432 if (!cp->xerr_status) 4433 OUTOFFB(np, HF_PRT, HF_EXT_ERR); 4434 } 4435 } 4436 goto out; 4437 /* 4438 * The device didn't send a GOOD SCSI status. 4439 * We may have some work to do prior to allow 4440 * the SCRIPTS processor to continue. 4441 */ 4442 case SIR_BAD_SCSI_STATUS: 4443 if (!cp) 4444 goto out; 4445 sym_sir_bad_scsi_status(np, num, cp); 4446 return; 4447 /* 4448 * We are asked by the SCRIPTS to prepare a 4449 * REJECT message. 4450 */ 4451 case SIR_REJECT_TO_SEND: 4452 sym_print_msg(cp, "M_REJECT to send for ", np->msgin); 4453 np->msgout[0] = M_REJECT; 4454 goto out; 4455 /* 4456 * We have been ODD at the end of a DATA IN 4457 * transfer and the device didn't send a 4458 * IGNORE WIDE RESIDUE message. 4459 * It is a data overrun condition. 4460 */ 4461 case SIR_SWIDE_OVERRUN: 4462 if (cp) { 4463 OUTONB(np, HF_PRT, HF_EXT_ERR); 4464 cp->xerr_status |= XE_SWIDE_OVRUN; 4465 } 4466 goto out; 4467 /* 4468 * We have been ODD at the end of a DATA OUT 4469 * transfer. 4470 * It is a data underrun condition. 4471 */ 4472 case SIR_SODL_UNDERRUN: 4473 if (cp) { 4474 OUTONB(np, HF_PRT, HF_EXT_ERR); 4475 cp->xerr_status |= XE_SODL_UNRUN; 4476 } 4477 goto out; 4478 /* 4479 * The device wants us to tranfer more data than 4480 * expected or in the wrong direction. 4481 * The number of extra bytes is in scratcha. 4482 * It is a data overrun condition. 4483 */ 4484 case SIR_DATA_OVERRUN: 4485 if (cp) { 4486 OUTONB(np, HF_PRT, HF_EXT_ERR); 4487 cp->xerr_status |= XE_EXTRA_DATA; 4488 cp->extra_bytes += INL(np, nc_scratcha); 4489 } 4490 goto out; 4491 /* 4492 * The device switched to an illegal phase (4/5). 4493 */ 4494 case SIR_BAD_PHASE: 4495 if (cp) { 4496 OUTONB(np, HF_PRT, HF_EXT_ERR); 4497 cp->xerr_status |= XE_BAD_PHASE; 4498 } 4499 goto out; 4500 /* 4501 * We received a message. 4502 */ 4503 case SIR_MSG_RECEIVED: 4504 if (!cp) 4505 goto out_stuck; 4506 switch (np->msgin [0]) { 4507 /* 4508 * We received an extended message. 4509 * We handle MODIFY DATA POINTER, SDTR, WDTR 4510 * and reject all other extended messages. 4511 */ 4512 case M_EXTENDED: 4513 switch (np->msgin [2]) { 4514 case M_X_MODIFY_DP: 4515 if (DEBUG_FLAGS & DEBUG_POINTER) 4516 sym_print_msg(cp, NULL, np->msgin); 4517 tmp = (np->msgin[3]<<24) + (np->msgin[4]<<16) + 4518 (np->msgin[5]<<8) + (np->msgin[6]); 4519 sym_modify_dp(np, tp, cp, tmp); 4520 return; 4521 case M_X_SYNC_REQ: 4522 sym_sync_nego(np, tp, cp); 4523 return; 4524 case M_X_PPR_REQ: 4525 sym_ppr_nego(np, tp, cp); 4526 return; 4527 case M_X_WIDE_REQ: 4528 sym_wide_nego(np, tp, cp); 4529 return; 4530 default: 4531 goto out_reject; 4532 } 4533 break; 4534 /* 4535 * We received a 1/2 byte message not handled from SCRIPTS. 4536 * We are only expecting MESSAGE REJECT and IGNORE WIDE 4537 * RESIDUE messages that haven't been anticipated by 4538 * SCRIPTS on SWIDE full condition. Unanticipated IGNORE 4539 * WIDE RESIDUE messages are aliased as MODIFY DP (-1). 4540 */ 4541 case M_IGN_RESIDUE: 4542 if (DEBUG_FLAGS & DEBUG_POINTER) 4543 sym_print_msg(cp, NULL, np->msgin); 4544 if (cp->host_flags & HF_SENSE) 4545 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 4546 else 4547 sym_modify_dp(np, tp, cp, -1); 4548 return; 4549 case M_REJECT: 4550 if (INB(np, HS_PRT) == HS_NEGOTIATE) 4551 sym_nego_rejected(np, tp, cp); 4552 else { 4553 sym_print_addr(cp->cmd, 4554 "M_REJECT received (%x:%x).\n", 4555 scr_to_cpu(np->lastmsg), np->msgout[0]); 4556 } 4557 goto out_clrack; 4558 break; 4559 default: 4560 goto out_reject; 4561 } 4562 break; 4563 /* 4564 * We received an unknown message. 4565 * Ignore all MSG IN phases and reject it. 4566 */ 4567 case SIR_MSG_WEIRD: 4568 sym_print_msg(cp, "WEIRD message received", np->msgin); 4569 OUTL_DSP(np, SCRIPTB_BA(np, msg_weird)); 4570 return; 4571 /* 4572 * Negotiation failed. 4573 * Target does not send us the reply. 4574 * Remove the HS_NEGOTIATE status. 4575 */ 4576 case SIR_NEGO_FAILED: 4577 OUTB(np, HS_PRT, HS_BUSY); 4578 /* 4579 * Negotiation failed. 4580 * Target does not want answer message. 4581 */ 4582 case SIR_NEGO_PROTO: 4583 sym_nego_default(np, tp, cp); 4584 goto out; 4585 } 4586 4587 out: 4588 OUTONB_STD(); 4589 return; 4590 out_reject: 4591 OUTL_DSP(np, SCRIPTB_BA(np, msg_bad)); 4592 return; 4593 out_clrack: 4594 OUTL_DSP(np, SCRIPTA_BA(np, clrack)); 4595 return; 4596 out_stuck: 4597 return; 4598 } 4599 4600 /* 4601 * Acquire a control block 4602 */ 4603 struct sym_ccb *sym_get_ccb (struct sym_hcb *np, struct scsi_cmnd *cmd, u_char tag_order) 4604 { 4605 u_char tn = cmd->device->id; 4606 u_char ln = cmd->device->lun; 4607 struct sym_tcb *tp = &np->target[tn]; 4608 struct sym_lcb *lp = sym_lp(tp, ln); 4609 u_short tag = NO_TAG; 4610 SYM_QUEHEAD *qp; 4611 struct sym_ccb *cp = NULL; 4612 4613 /* 4614 * Look for a free CCB 4615 */ 4616 if (sym_que_empty(&np->free_ccbq)) 4617 sym_alloc_ccb(np); 4618 qp = sym_remque_head(&np->free_ccbq); 4619 if (!qp) 4620 goto out; 4621 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 4622 4623 { 4624 /* 4625 * If we have been asked for a tagged command. 4626 */ 4627 if (tag_order) { 4628 /* 4629 * Debugging purpose. 4630 */ 4631 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 4632 if (lp->busy_itl != 0) 4633 goto out_free; 4634 #endif 4635 /* 4636 * Allocate resources for tags if not yet. 4637 */ 4638 if (!lp->cb_tags) { 4639 sym_alloc_lcb_tags(np, tn, ln); 4640 if (!lp->cb_tags) 4641 goto out_free; 4642 } 4643 /* 4644 * Get a tag for this SCSI IO and set up 4645 * the CCB bus address for reselection, 4646 * and count it for this LUN. 4647 * Toggle reselect path to tagged. 4648 */ 4649 if (lp->busy_itlq < SYM_CONF_MAX_TASK) { 4650 tag = lp->cb_tags[lp->ia_tag]; 4651 if (++lp->ia_tag == SYM_CONF_MAX_TASK) 4652 lp->ia_tag = 0; 4653 ++lp->busy_itlq; 4654 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 4655 lp->itlq_tbl[tag] = cpu_to_scr(cp->ccb_ba); 4656 lp->head.resel_sa = 4657 cpu_to_scr(SCRIPTA_BA(np, resel_tag)); 4658 #endif 4659 #ifdef SYM_OPT_LIMIT_COMMAND_REORDERING 4660 cp->tags_si = lp->tags_si; 4661 ++lp->tags_sum[cp->tags_si]; 4662 ++lp->tags_since; 4663 #endif 4664 } 4665 else 4666 goto out_free; 4667 } 4668 /* 4669 * This command will not be tagged. 4670 * If we already have either a tagged or untagged 4671 * one, refuse to overlap this untagged one. 4672 */ 4673 else { 4674 /* 4675 * Debugging purpose. 4676 */ 4677 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 4678 if (lp->busy_itl != 0 || lp->busy_itlq != 0) 4679 goto out_free; 4680 #endif 4681 /* 4682 * Count this nexus for this LUN. 4683 * Set up the CCB bus address for reselection. 4684 * Toggle reselect path to untagged. 4685 */ 4686 ++lp->busy_itl; 4687 #ifndef SYM_OPT_HANDLE_DEVICE_QUEUEING 4688 if (lp->busy_itl == 1) { 4689 lp->head.itl_task_sa = cpu_to_scr(cp->ccb_ba); 4690 lp->head.resel_sa = 4691 cpu_to_scr(SCRIPTA_BA(np, resel_no_tag)); 4692 } 4693 else 4694 goto out_free; 4695 #endif 4696 } 4697 } 4698 /* 4699 * Put the CCB into the busy queue. 4700 */ 4701 sym_insque_tail(&cp->link_ccbq, &np->busy_ccbq); 4702 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 4703 if (lp) { 4704 sym_remque(&cp->link2_ccbq); 4705 sym_insque_tail(&cp->link2_ccbq, &lp->waiting_ccbq); 4706 } 4707 4708 #endif 4709 cp->to_abort = 0; 4710 cp->odd_byte_adjustment = 0; 4711 cp->tag = tag; 4712 cp->order = tag_order; 4713 cp->target = tn; 4714 cp->lun = ln; 4715 4716 if (DEBUG_FLAGS & DEBUG_TAGS) { 4717 sym_print_addr(cmd, "ccb @%p using tag %d.\n", cp, tag); 4718 } 4719 4720 out: 4721 return cp; 4722 out_free: 4723 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 4724 return NULL; 4725 } 4726 4727 /* 4728 * Release one control block 4729 */ 4730 void sym_free_ccb (struct sym_hcb *np, struct sym_ccb *cp) 4731 { 4732 struct sym_tcb *tp = &np->target[cp->target]; 4733 struct sym_lcb *lp = sym_lp(tp, cp->lun); 4734 4735 if (DEBUG_FLAGS & DEBUG_TAGS) { 4736 sym_print_addr(cp->cmd, "ccb @%p freeing tag %d.\n", 4737 cp, cp->tag); 4738 } 4739 4740 /* 4741 * If LCB available, 4742 */ 4743 if (lp) { 4744 /* 4745 * If tagged, release the tag, set the relect path 4746 */ 4747 if (cp->tag != NO_TAG) { 4748 #ifdef SYM_OPT_LIMIT_COMMAND_REORDERING 4749 --lp->tags_sum[cp->tags_si]; 4750 #endif 4751 /* 4752 * Free the tag value. 4753 */ 4754 lp->cb_tags[lp->if_tag] = cp->tag; 4755 if (++lp->if_tag == SYM_CONF_MAX_TASK) 4756 lp->if_tag = 0; 4757 /* 4758 * Make the reselect path invalid, 4759 * and uncount this CCB. 4760 */ 4761 lp->itlq_tbl[cp->tag] = cpu_to_scr(np->bad_itlq_ba); 4762 --lp->busy_itlq; 4763 } else { /* Untagged */ 4764 /* 4765 * Make the reselect path invalid, 4766 * and uncount this CCB. 4767 */ 4768 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 4769 --lp->busy_itl; 4770 } 4771 /* 4772 * If no JOB active, make the LUN reselect path invalid. 4773 */ 4774 if (lp->busy_itlq == 0 && lp->busy_itl == 0) 4775 lp->head.resel_sa = 4776 cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun)); 4777 } 4778 4779 /* 4780 * We donnot queue more than 1 ccb per target 4781 * with negotiation at any time. If this ccb was 4782 * used for negotiation, clear this info in the tcb. 4783 */ 4784 if (cp == tp->nego_cp) 4785 tp->nego_cp = NULL; 4786 4787 #ifdef SYM_CONF_IARB_SUPPORT 4788 /* 4789 * If we just complete the last queued CCB, 4790 * clear this info that is no longer relevant. 4791 */ 4792 if (cp == np->last_cp) 4793 np->last_cp = 0; 4794 #endif 4795 4796 /* 4797 * Make this CCB available. 4798 */ 4799 cp->cmd = NULL; 4800 cp->host_status = HS_IDLE; 4801 sym_remque(&cp->link_ccbq); 4802 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 4803 4804 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 4805 if (lp) { 4806 sym_remque(&cp->link2_ccbq); 4807 sym_insque_tail(&cp->link2_ccbq, &np->dummy_ccbq); 4808 if (cp->started) { 4809 if (cp->tag != NO_TAG) 4810 --lp->started_tags; 4811 else 4812 --lp->started_no_tag; 4813 } 4814 } 4815 cp->started = 0; 4816 #endif 4817 } 4818 4819 /* 4820 * Allocate a CCB from memory and initialize its fixed part. 4821 */ 4822 static struct sym_ccb *sym_alloc_ccb(struct sym_hcb *np) 4823 { 4824 struct sym_ccb *cp = NULL; 4825 int hcode; 4826 4827 /* 4828 * Prevent from allocating more CCBs than we can 4829 * queue to the controller. 4830 */ 4831 if (np->actccbs >= SYM_CONF_MAX_START) 4832 return NULL; 4833 4834 /* 4835 * Allocate memory for this CCB. 4836 */ 4837 cp = sym_calloc_dma(sizeof(struct sym_ccb), "CCB"); 4838 if (!cp) 4839 goto out_free; 4840 4841 /* 4842 * Count it. 4843 */ 4844 np->actccbs++; 4845 4846 /* 4847 * Compute the bus address of this ccb. 4848 */ 4849 cp->ccb_ba = vtobus(cp); 4850 4851 /* 4852 * Insert this ccb into the hashed list. 4853 */ 4854 hcode = CCB_HASH_CODE(cp->ccb_ba); 4855 cp->link_ccbh = np->ccbh[hcode]; 4856 np->ccbh[hcode] = cp; 4857 4858 /* 4859 * Initialyze the start and restart actions. 4860 */ 4861 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, idle)); 4862 cp->phys.head.go.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l)); 4863 4864 /* 4865 * Initilialyze some other fields. 4866 */ 4867 cp->phys.smsg_ext.addr = cpu_to_scr(HCB_BA(np, msgin[2])); 4868 4869 /* 4870 * Chain into free ccb queue. 4871 */ 4872 sym_insque_head(&cp->link_ccbq, &np->free_ccbq); 4873 4874 /* 4875 * Chain into optionnal lists. 4876 */ 4877 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 4878 sym_insque_head(&cp->link2_ccbq, &np->dummy_ccbq); 4879 #endif 4880 return cp; 4881 out_free: 4882 if (cp) 4883 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 4884 return NULL; 4885 } 4886 4887 /* 4888 * Look up a CCB from a DSA value. 4889 */ 4890 static struct sym_ccb *sym_ccb_from_dsa(struct sym_hcb *np, u32 dsa) 4891 { 4892 int hcode; 4893 struct sym_ccb *cp; 4894 4895 hcode = CCB_HASH_CODE(dsa); 4896 cp = np->ccbh[hcode]; 4897 while (cp) { 4898 if (cp->ccb_ba == dsa) 4899 break; 4900 cp = cp->link_ccbh; 4901 } 4902 4903 return cp; 4904 } 4905 4906 /* 4907 * Target control block initialisation. 4908 * Nothing important to do at the moment. 4909 */ 4910 static void sym_init_tcb (struct sym_hcb *np, u_char tn) 4911 { 4912 #if 0 /* Hmmm... this checking looks paranoid. */ 4913 /* 4914 * Check some alignments required by the chip. 4915 */ 4916 assert (((offsetof(struct sym_reg, nc_sxfer) ^ 4917 offsetof(struct sym_tcb, head.sval)) &3) == 0); 4918 assert (((offsetof(struct sym_reg, nc_scntl3) ^ 4919 offsetof(struct sym_tcb, head.wval)) &3) == 0); 4920 #endif 4921 } 4922 4923 /* 4924 * Lun control block allocation and initialization. 4925 */ 4926 struct sym_lcb *sym_alloc_lcb (struct sym_hcb *np, u_char tn, u_char ln) 4927 { 4928 struct sym_tcb *tp = &np->target[tn]; 4929 struct sym_lcb *lp = NULL; 4930 4931 /* 4932 * Initialize the target control block if not yet. 4933 */ 4934 sym_init_tcb (np, tn); 4935 4936 /* 4937 * Allocate the LCB bus address array. 4938 * Compute the bus address of this table. 4939 */ 4940 if (ln && !tp->luntbl) { 4941 int i; 4942 4943 tp->luntbl = sym_calloc_dma(256, "LUNTBL"); 4944 if (!tp->luntbl) 4945 goto fail; 4946 for (i = 0 ; i < 64 ; i++) 4947 tp->luntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 4948 tp->head.luntbl_sa = cpu_to_scr(vtobus(tp->luntbl)); 4949 } 4950 4951 /* 4952 * Allocate the table of pointers for LUN(s) > 0, if needed. 4953 */ 4954 if (ln && !tp->lunmp) { 4955 tp->lunmp = kcalloc(SYM_CONF_MAX_LUN, sizeof(struct sym_lcb *), 4956 GFP_KERNEL); 4957 if (!tp->lunmp) 4958 goto fail; 4959 } 4960 4961 /* 4962 * Allocate the lcb. 4963 * Make it available to the chip. 4964 */ 4965 lp = sym_calloc_dma(sizeof(struct sym_lcb), "LCB"); 4966 if (!lp) 4967 goto fail; 4968 if (ln) { 4969 tp->lunmp[ln] = lp; 4970 tp->luntbl[ln] = cpu_to_scr(vtobus(lp)); 4971 } 4972 else { 4973 tp->lun0p = lp; 4974 tp->head.lun0_sa = cpu_to_scr(vtobus(lp)); 4975 } 4976 4977 /* 4978 * Let the itl task point to error handling. 4979 */ 4980 lp->head.itl_task_sa = cpu_to_scr(np->bad_itl_ba); 4981 4982 /* 4983 * Set the reselect pattern to our default. :) 4984 */ 4985 lp->head.resel_sa = cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun)); 4986 4987 /* 4988 * Set user capabilities. 4989 */ 4990 lp->user_flags = tp->usrflags & (SYM_DISC_ENABLED | SYM_TAGS_ENABLED); 4991 4992 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 4993 /* 4994 * Initialize device queueing. 4995 */ 4996 sym_que_init(&lp->waiting_ccbq); 4997 sym_que_init(&lp->started_ccbq); 4998 lp->started_max = SYM_CONF_MAX_TASK; 4999 lp->started_limit = SYM_CONF_MAX_TASK; 5000 #endif 5001 5002 fail: 5003 return lp; 5004 } 5005 5006 /* 5007 * Allocate LCB resources for tagged command queuing. 5008 */ 5009 static void sym_alloc_lcb_tags (struct sym_hcb *np, u_char tn, u_char ln) 5010 { 5011 struct sym_tcb *tp = &np->target[tn]; 5012 struct sym_lcb *lp = sym_lp(tp, ln); 5013 int i; 5014 5015 /* 5016 * Allocate the task table and and the tag allocation 5017 * circular buffer. We want both or none. 5018 */ 5019 lp->itlq_tbl = sym_calloc_dma(SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 5020 if (!lp->itlq_tbl) 5021 goto fail; 5022 lp->cb_tags = kcalloc(SYM_CONF_MAX_TASK, 1, GFP_ATOMIC); 5023 if (!lp->cb_tags) { 5024 sym_mfree_dma(lp->itlq_tbl, SYM_CONF_MAX_TASK*4, "ITLQ_TBL"); 5025 lp->itlq_tbl = NULL; 5026 goto fail; 5027 } 5028 5029 /* 5030 * Initialize the task table with invalid entries. 5031 */ 5032 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 5033 lp->itlq_tbl[i] = cpu_to_scr(np->notask_ba); 5034 5035 /* 5036 * Fill up the tag buffer with tag numbers. 5037 */ 5038 for (i = 0 ; i < SYM_CONF_MAX_TASK ; i++) 5039 lp->cb_tags[i] = i; 5040 5041 /* 5042 * Make the task table available to SCRIPTS, 5043 * And accept tagged commands now. 5044 */ 5045 lp->head.itlq_tbl_sa = cpu_to_scr(vtobus(lp->itlq_tbl)); 5046 5047 return; 5048 fail: 5049 return; 5050 } 5051 5052 /* 5053 * Queue a SCSI IO to the controller. 5054 */ 5055 int sym_queue_scsiio(struct sym_hcb *np, struct scsi_cmnd *cmd, struct sym_ccb *cp) 5056 { 5057 struct scsi_device *sdev = cmd->device; 5058 struct sym_tcb *tp; 5059 struct sym_lcb *lp; 5060 u_char *msgptr; 5061 u_int msglen; 5062 int can_disconnect; 5063 5064 /* 5065 * Keep track of the IO in our CCB. 5066 */ 5067 cp->cmd = cmd; 5068 5069 /* 5070 * Retrieve the target descriptor. 5071 */ 5072 tp = &np->target[cp->target]; 5073 5074 /* 5075 * Retrieve the lun descriptor. 5076 */ 5077 lp = sym_lp(tp, sdev->lun); 5078 5079 can_disconnect = (cp->tag != NO_TAG) || 5080 (lp && (lp->curr_flags & SYM_DISC_ENABLED)); 5081 5082 msgptr = cp->scsi_smsg; 5083 msglen = 0; 5084 msgptr[msglen++] = IDENTIFY(can_disconnect, sdev->lun); 5085 5086 /* 5087 * Build the tag message if present. 5088 */ 5089 if (cp->tag != NO_TAG) { 5090 u_char order = cp->order; 5091 5092 switch(order) { 5093 case M_ORDERED_TAG: 5094 break; 5095 case M_HEAD_TAG: 5096 break; 5097 default: 5098 order = M_SIMPLE_TAG; 5099 } 5100 #ifdef SYM_OPT_LIMIT_COMMAND_REORDERING 5101 /* 5102 * Avoid too much reordering of SCSI commands. 5103 * The algorithm tries to prevent completion of any 5104 * tagged command from being delayed against more 5105 * than 3 times the max number of queued commands. 5106 */ 5107 if (lp && lp->tags_since > 3*SYM_CONF_MAX_TAG) { 5108 lp->tags_si = !(lp->tags_si); 5109 if (lp->tags_sum[lp->tags_si]) { 5110 order = M_ORDERED_TAG; 5111 if ((DEBUG_FLAGS & DEBUG_TAGS)||sym_verbose>1) { 5112 sym_print_addr(cmd, 5113 "ordered tag forced.\n"); 5114 } 5115 } 5116 lp->tags_since = 0; 5117 } 5118 #endif 5119 msgptr[msglen++] = order; 5120 5121 /* 5122 * For less than 128 tags, actual tags are numbered 5123 * 1,3,5,..2*MAXTAGS+1,since we may have to deal 5124 * with devices that have problems with #TAG 0 or too 5125 * great #TAG numbers. For more tags (up to 256), 5126 * we use directly our tag number. 5127 */ 5128 #if SYM_CONF_MAX_TASK > (512/4) 5129 msgptr[msglen++] = cp->tag; 5130 #else 5131 msgptr[msglen++] = (cp->tag << 1) + 1; 5132 #endif 5133 } 5134 5135 /* 5136 * Build a negotiation message if needed. 5137 * (nego_status is filled by sym_prepare_nego()) 5138 */ 5139 cp->nego_status = 0; 5140 if (tp->tgoal.check_nego && !tp->nego_cp && lp) { 5141 msglen += sym_prepare_nego(np, cp, msgptr + msglen); 5142 } 5143 5144 /* 5145 * Startqueue 5146 */ 5147 cp->phys.head.go.start = cpu_to_scr(SCRIPTA_BA(np, select)); 5148 cp->phys.head.go.restart = cpu_to_scr(SCRIPTA_BA(np, resel_dsa)); 5149 5150 /* 5151 * select 5152 */ 5153 cp->phys.select.sel_id = cp->target; 5154 cp->phys.select.sel_scntl3 = tp->head.wval; 5155 cp->phys.select.sel_sxfer = tp->head.sval; 5156 cp->phys.select.sel_scntl4 = tp->head.uval; 5157 5158 /* 5159 * message 5160 */ 5161 cp->phys.smsg.addr = CCB_BA(cp, scsi_smsg); 5162 cp->phys.smsg.size = cpu_to_scr(msglen); 5163 5164 /* 5165 * status 5166 */ 5167 cp->host_xflags = 0; 5168 cp->host_status = cp->nego_status ? HS_NEGOTIATE : HS_BUSY; 5169 cp->ssss_status = S_ILLEGAL; 5170 cp->xerr_status = 0; 5171 cp->host_flags = 0; 5172 cp->extra_bytes = 0; 5173 5174 /* 5175 * extreme data pointer. 5176 * shall be positive, so -1 is lower than lowest.:) 5177 */ 5178 cp->ext_sg = -1; 5179 cp->ext_ofs = 0; 5180 5181 /* 5182 * Build the CDB and DATA descriptor block 5183 * and start the IO. 5184 */ 5185 return sym_setup_data_and_start(np, cmd, cp); 5186 } 5187 5188 /* 5189 * Reset a SCSI target (all LUNs of this target). 5190 */ 5191 int sym_reset_scsi_target(struct sym_hcb *np, int target) 5192 { 5193 struct sym_tcb *tp; 5194 5195 if (target == np->myaddr || (u_int)target >= SYM_CONF_MAX_TARGET) 5196 return -1; 5197 5198 tp = &np->target[target]; 5199 tp->to_reset = 1; 5200 5201 np->istat_sem = SEM; 5202 OUTB(np, nc_istat, SIGP|SEM); 5203 5204 return 0; 5205 } 5206 5207 /* 5208 * Abort a SCSI IO. 5209 */ 5210 static int sym_abort_ccb(struct sym_hcb *np, struct sym_ccb *cp, int timed_out) 5211 { 5212 /* 5213 * Check that the IO is active. 5214 */ 5215 if (!cp || !cp->host_status || cp->host_status == HS_WAIT) 5216 return -1; 5217 5218 /* 5219 * If a previous abort didn't succeed in time, 5220 * perform a BUS reset. 5221 */ 5222 if (cp->to_abort) { 5223 sym_reset_scsi_bus(np, 1); 5224 return 0; 5225 } 5226 5227 /* 5228 * Mark the CCB for abort and allow time for. 5229 */ 5230 cp->to_abort = timed_out ? 2 : 1; 5231 5232 /* 5233 * Tell the SCRIPTS processor to stop and synchronize with us. 5234 */ 5235 np->istat_sem = SEM; 5236 OUTB(np, nc_istat, SIGP|SEM); 5237 return 0; 5238 } 5239 5240 int sym_abort_scsiio(struct sym_hcb *np, struct scsi_cmnd *cmd, int timed_out) 5241 { 5242 struct sym_ccb *cp; 5243 SYM_QUEHEAD *qp; 5244 5245 /* 5246 * Look up our CCB control block. 5247 */ 5248 cp = NULL; 5249 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) { 5250 struct sym_ccb *cp2 = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5251 if (cp2->cmd == cmd) { 5252 cp = cp2; 5253 break; 5254 } 5255 } 5256 5257 return sym_abort_ccb(np, cp, timed_out); 5258 } 5259 5260 /* 5261 * Complete execution of a SCSI command with extended 5262 * error, SCSI status error, or having been auto-sensed. 5263 * 5264 * The SCRIPTS processor is not running there, so we 5265 * can safely access IO registers and remove JOBs from 5266 * the START queue. 5267 * SCRATCHA is assumed to have been loaded with STARTPOS 5268 * before the SCRIPTS called the C code. 5269 */ 5270 void sym_complete_error(struct sym_hcb *np, struct sym_ccb *cp) 5271 { 5272 struct scsi_device *sdev; 5273 struct scsi_cmnd *cmd; 5274 struct sym_tcb *tp; 5275 struct sym_lcb *lp; 5276 int resid; 5277 int i; 5278 5279 /* 5280 * Paranoid check. :) 5281 */ 5282 if (!cp || !cp->cmd) 5283 return; 5284 5285 cmd = cp->cmd; 5286 sdev = cmd->device; 5287 if (DEBUG_FLAGS & (DEBUG_TINY|DEBUG_RESULT)) { 5288 dev_info(&sdev->sdev_gendev, "CCB=%p STAT=%x/%x/%x\n", cp, 5289 cp->host_status, cp->ssss_status, cp->host_flags); 5290 } 5291 5292 /* 5293 * Get target and lun pointers. 5294 */ 5295 tp = &np->target[cp->target]; 5296 lp = sym_lp(tp, sdev->lun); 5297 5298 /* 5299 * Check for extended errors. 5300 */ 5301 if (cp->xerr_status) { 5302 if (sym_verbose) 5303 sym_print_xerr(cmd, cp->xerr_status); 5304 if (cp->host_status == HS_COMPLETE) 5305 cp->host_status = HS_COMP_ERR; 5306 } 5307 5308 /* 5309 * Calculate the residual. 5310 */ 5311 resid = sym_compute_residual(np, cp); 5312 5313 if (!SYM_SETUP_RESIDUAL_SUPPORT) {/* If user does not want residuals */ 5314 resid = 0; /* throw them away. :) */ 5315 cp->sv_resid = 0; 5316 } 5317 #ifdef DEBUG_2_0_X 5318 if (resid) 5319 printf("XXXX RESID= %d - 0x%x\n", resid, resid); 5320 #endif 5321 5322 /* 5323 * Dequeue all queued CCBs for that device 5324 * not yet started by SCRIPTS. 5325 */ 5326 i = (INL(np, nc_scratcha) - np->squeue_ba) / 4; 5327 i = sym_dequeue_from_squeue(np, i, cp->target, sdev->lun, -1); 5328 5329 /* 5330 * Restart the SCRIPTS processor. 5331 */ 5332 OUTL_DSP(np, SCRIPTA_BA(np, start)); 5333 5334 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5335 if (cp->host_status == HS_COMPLETE && 5336 cp->ssss_status == S_QUEUE_FULL) { 5337 if (!lp || lp->started_tags - i < 2) 5338 goto weirdness; 5339 /* 5340 * Decrease queue depth as needed. 5341 */ 5342 lp->started_max = lp->started_tags - i - 1; 5343 lp->num_sgood = 0; 5344 5345 if (sym_verbose >= 2) { 5346 sym_print_addr(cmd, " queue depth is now %d\n", 5347 lp->started_max); 5348 } 5349 5350 /* 5351 * Repair the CCB. 5352 */ 5353 cp->host_status = HS_BUSY; 5354 cp->ssss_status = S_ILLEGAL; 5355 5356 /* 5357 * Let's requeue it to device. 5358 */ 5359 sym_set_cam_status(cmd, DID_SOFT_ERROR); 5360 goto finish; 5361 } 5362 weirdness: 5363 #endif 5364 /* 5365 * Build result in CAM ccb. 5366 */ 5367 sym_set_cam_result_error(np, cp, resid); 5368 5369 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5370 finish: 5371 #endif 5372 /* 5373 * Add this one to the COMP queue. 5374 */ 5375 sym_remque(&cp->link_ccbq); 5376 sym_insque_head(&cp->link_ccbq, &np->comp_ccbq); 5377 5378 /* 5379 * Complete all those commands with either error 5380 * or requeue condition. 5381 */ 5382 sym_flush_comp_queue(np, 0); 5383 5384 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5385 /* 5386 * Donnot start more than 1 command after an error. 5387 */ 5388 sym_start_next_ccbs(np, lp, 1); 5389 #endif 5390 } 5391 5392 /* 5393 * Complete execution of a successful SCSI command. 5394 * 5395 * Only successful commands go to the DONE queue, 5396 * since we need to have the SCRIPTS processor 5397 * stopped on any error condition. 5398 * The SCRIPTS processor is running while we are 5399 * completing successful commands. 5400 */ 5401 void sym_complete_ok (struct sym_hcb *np, struct sym_ccb *cp) 5402 { 5403 struct sym_tcb *tp; 5404 struct sym_lcb *lp; 5405 struct scsi_cmnd *cmd; 5406 int resid; 5407 5408 /* 5409 * Paranoid check. :) 5410 */ 5411 if (!cp || !cp->cmd) 5412 return; 5413 assert (cp->host_status == HS_COMPLETE); 5414 5415 /* 5416 * Get user command. 5417 */ 5418 cmd = cp->cmd; 5419 5420 /* 5421 * Get target and lun pointers. 5422 */ 5423 tp = &np->target[cp->target]; 5424 lp = sym_lp(tp, cp->lun); 5425 5426 /* 5427 * If all data have been transferred, given than no 5428 * extended error did occur, there is no residual. 5429 */ 5430 resid = 0; 5431 if (cp->phys.head.lastp != cp->goalp) 5432 resid = sym_compute_residual(np, cp); 5433 5434 /* 5435 * Wrong transfer residuals may be worse than just always 5436 * returning zero. User can disable this feature in 5437 * sym53c8xx.h. Residual support is enabled by default. 5438 */ 5439 if (!SYM_SETUP_RESIDUAL_SUPPORT) 5440 resid = 0; 5441 #ifdef DEBUG_2_0_X 5442 if (resid) 5443 printf("XXXX RESID= %d - 0x%x\n", resid, resid); 5444 #endif 5445 5446 /* 5447 * Build result in CAM ccb. 5448 */ 5449 sym_set_cam_result_ok(cp, cmd, resid); 5450 5451 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5452 /* 5453 * If max number of started ccbs had been reduced, 5454 * increase it if 200 good status received. 5455 */ 5456 if (lp && lp->started_max < lp->started_limit) { 5457 ++lp->num_sgood; 5458 if (lp->num_sgood >= 200) { 5459 lp->num_sgood = 0; 5460 ++lp->started_max; 5461 if (sym_verbose >= 2) { 5462 sym_print_addr(cmd, " queue depth is now %d\n", 5463 lp->started_max); 5464 } 5465 } 5466 } 5467 #endif 5468 5469 /* 5470 * Free our CCB. 5471 */ 5472 sym_free_ccb (np, cp); 5473 5474 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5475 /* 5476 * Requeue a couple of awaiting scsi commands. 5477 */ 5478 if (!sym_que_empty(&lp->waiting_ccbq)) 5479 sym_start_next_ccbs(np, lp, 2); 5480 #endif 5481 /* 5482 * Complete the command. 5483 */ 5484 sym_xpt_done(np, cmd); 5485 } 5486 5487 /* 5488 * Soft-attach the controller. 5489 */ 5490 int sym_hcb_attach(struct Scsi_Host *shost, struct sym_fw *fw, struct sym_nvram *nvram) 5491 { 5492 struct sym_hcb *np = sym_get_hcb(shost); 5493 int i; 5494 5495 /* 5496 * Get some info about the firmware. 5497 */ 5498 np->scripta_sz = fw->a_size; 5499 np->scriptb_sz = fw->b_size; 5500 np->scriptz_sz = fw->z_size; 5501 np->fw_setup = fw->setup; 5502 np->fw_patch = fw->patch; 5503 np->fw_name = fw->name; 5504 5505 /* 5506 * Save setting of some IO registers, so we will 5507 * be able to probe specific implementations. 5508 */ 5509 sym_save_initial_setting (np); 5510 5511 /* 5512 * Reset the chip now, since it has been reported 5513 * that SCSI clock calibration may not work properly 5514 * if the chip is currently active. 5515 */ 5516 sym_chip_reset(np); 5517 5518 /* 5519 * Prepare controller and devices settings, according 5520 * to chip features, user set-up and driver set-up. 5521 */ 5522 sym_prepare_setting(shost, np, nvram); 5523 5524 /* 5525 * Check the PCI clock frequency. 5526 * Must be performed after prepare_setting since it destroys 5527 * STEST1 that is used to probe for the clock doubler. 5528 */ 5529 i = sym_getpciclock(np); 5530 if (i > 37000 && !(np->features & FE_66MHZ)) 5531 printf("%s: PCI BUS clock seems too high: %u KHz.\n", 5532 sym_name(np), i); 5533 5534 /* 5535 * Allocate the start queue. 5536 */ 5537 np->squeue = sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"SQUEUE"); 5538 if (!np->squeue) 5539 goto attach_failed; 5540 np->squeue_ba = vtobus(np->squeue); 5541 5542 /* 5543 * Allocate the done queue. 5544 */ 5545 np->dqueue = sym_calloc_dma(sizeof(u32)*(MAX_QUEUE*2),"DQUEUE"); 5546 if (!np->dqueue) 5547 goto attach_failed; 5548 np->dqueue_ba = vtobus(np->dqueue); 5549 5550 /* 5551 * Allocate the target bus address array. 5552 */ 5553 np->targtbl = sym_calloc_dma(256, "TARGTBL"); 5554 if (!np->targtbl) 5555 goto attach_failed; 5556 np->targtbl_ba = vtobus(np->targtbl); 5557 5558 /* 5559 * Allocate SCRIPTS areas. 5560 */ 5561 np->scripta0 = sym_calloc_dma(np->scripta_sz, "SCRIPTA0"); 5562 np->scriptb0 = sym_calloc_dma(np->scriptb_sz, "SCRIPTB0"); 5563 np->scriptz0 = sym_calloc_dma(np->scriptz_sz, "SCRIPTZ0"); 5564 if (!np->scripta0 || !np->scriptb0 || !np->scriptz0) 5565 goto attach_failed; 5566 5567 /* 5568 * Allocate the array of lists of CCBs hashed by DSA. 5569 */ 5570 np->ccbh = kcalloc(CCB_HASH_SIZE, sizeof(struct sym_ccb **), GFP_KERNEL); 5571 if (!np->ccbh) 5572 goto attach_failed; 5573 5574 /* 5575 * Initialyze the CCB free and busy queues. 5576 */ 5577 sym_que_init(&np->free_ccbq); 5578 sym_que_init(&np->busy_ccbq); 5579 sym_que_init(&np->comp_ccbq); 5580 5581 /* 5582 * Initialization for optional handling 5583 * of device queueing. 5584 */ 5585 #ifdef SYM_OPT_HANDLE_DEVICE_QUEUEING 5586 sym_que_init(&np->dummy_ccbq); 5587 #endif 5588 /* 5589 * Allocate some CCB. We need at least ONE. 5590 */ 5591 if (!sym_alloc_ccb(np)) 5592 goto attach_failed; 5593 5594 /* 5595 * Calculate BUS addresses where we are going 5596 * to load the SCRIPTS. 5597 */ 5598 np->scripta_ba = vtobus(np->scripta0); 5599 np->scriptb_ba = vtobus(np->scriptb0); 5600 np->scriptz_ba = vtobus(np->scriptz0); 5601 5602 if (np->ram_ba) { 5603 np->scripta_ba = np->ram_ba; 5604 if (np->features & FE_RAM8K) { 5605 np->scriptb_ba = np->scripta_ba + 4096; 5606 #if 0 /* May get useful for 64 BIT PCI addressing */ 5607 np->scr_ram_seg = cpu_to_scr(np->scripta_ba >> 32); 5608 #endif 5609 } 5610 } 5611 5612 /* 5613 * Copy scripts to controller instance. 5614 */ 5615 memcpy(np->scripta0, fw->a_base, np->scripta_sz); 5616 memcpy(np->scriptb0, fw->b_base, np->scriptb_sz); 5617 memcpy(np->scriptz0, fw->z_base, np->scriptz_sz); 5618 5619 /* 5620 * Setup variable parts in scripts and compute 5621 * scripts bus addresses used from the C code. 5622 */ 5623 np->fw_setup(np, fw); 5624 5625 /* 5626 * Bind SCRIPTS with physical addresses usable by the 5627 * SCRIPTS processor (as seen from the BUS = BUS addresses). 5628 */ 5629 sym_fw_bind_script(np, (u32 *) np->scripta0, np->scripta_sz); 5630 sym_fw_bind_script(np, (u32 *) np->scriptb0, np->scriptb_sz); 5631 sym_fw_bind_script(np, (u32 *) np->scriptz0, np->scriptz_sz); 5632 5633 #ifdef SYM_CONF_IARB_SUPPORT 5634 /* 5635 * If user wants IARB to be set when we win arbitration 5636 * and have other jobs, compute the max number of consecutive 5637 * settings of IARB hints before we leave devices a chance to 5638 * arbitrate for reselection. 5639 */ 5640 #ifdef SYM_SETUP_IARB_MAX 5641 np->iarb_max = SYM_SETUP_IARB_MAX; 5642 #else 5643 np->iarb_max = 4; 5644 #endif 5645 #endif 5646 5647 /* 5648 * Prepare the idle and invalid task actions. 5649 */ 5650 np->idletask.start = cpu_to_scr(SCRIPTA_BA(np, idle)); 5651 np->idletask.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l)); 5652 np->idletask_ba = vtobus(&np->idletask); 5653 5654 np->notask.start = cpu_to_scr(SCRIPTA_BA(np, idle)); 5655 np->notask.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l)); 5656 np->notask_ba = vtobus(&np->notask); 5657 5658 np->bad_itl.start = cpu_to_scr(SCRIPTA_BA(np, idle)); 5659 np->bad_itl.restart = cpu_to_scr(SCRIPTB_BA(np, bad_i_t_l)); 5660 np->bad_itl_ba = vtobus(&np->bad_itl); 5661 5662 np->bad_itlq.start = cpu_to_scr(SCRIPTA_BA(np, idle)); 5663 np->bad_itlq.restart = cpu_to_scr(SCRIPTB_BA(np,bad_i_t_l_q)); 5664 np->bad_itlq_ba = vtobus(&np->bad_itlq); 5665 5666 /* 5667 * Allocate and prepare the lun JUMP table that is used 5668 * for a target prior the probing of devices (bad lun table). 5669 * A private table will be allocated for the target on the 5670 * first INQUIRY response received. 5671 */ 5672 np->badluntbl = sym_calloc_dma(256, "BADLUNTBL"); 5673 if (!np->badluntbl) 5674 goto attach_failed; 5675 5676 np->badlun_sa = cpu_to_scr(SCRIPTB_BA(np, resel_bad_lun)); 5677 for (i = 0 ; i < 64 ; i++) /* 64 luns/target, no less */ 5678 np->badluntbl[i] = cpu_to_scr(vtobus(&np->badlun_sa)); 5679 5680 /* 5681 * Prepare the bus address array that contains the bus 5682 * address of each target control block. 5683 * For now, assume all logical units are wrong. :) 5684 */ 5685 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) { 5686 np->targtbl[i] = cpu_to_scr(vtobus(&np->target[i])); 5687 np->target[i].head.luntbl_sa = 5688 cpu_to_scr(vtobus(np->badluntbl)); 5689 np->target[i].head.lun0_sa = 5690 cpu_to_scr(vtobus(&np->badlun_sa)); 5691 } 5692 5693 /* 5694 * Now check the cache handling of the pci chipset. 5695 */ 5696 if (sym_snooptest (np)) { 5697 printf("%s: CACHE INCORRECTLY CONFIGURED.\n", sym_name(np)); 5698 goto attach_failed; 5699 } 5700 5701 /* 5702 * Sigh! we are done. 5703 */ 5704 return 0; 5705 5706 attach_failed: 5707 return -ENXIO; 5708 } 5709 5710 /* 5711 * Free everything that has been allocated for this device. 5712 */ 5713 void sym_hcb_free(struct sym_hcb *np) 5714 { 5715 SYM_QUEHEAD *qp; 5716 struct sym_ccb *cp; 5717 struct sym_tcb *tp; 5718 int target; 5719 5720 if (np->scriptz0) 5721 sym_mfree_dma(np->scriptz0, np->scriptz_sz, "SCRIPTZ0"); 5722 if (np->scriptb0) 5723 sym_mfree_dma(np->scriptb0, np->scriptb_sz, "SCRIPTB0"); 5724 if (np->scripta0) 5725 sym_mfree_dma(np->scripta0, np->scripta_sz, "SCRIPTA0"); 5726 if (np->squeue) 5727 sym_mfree_dma(np->squeue, sizeof(u32)*(MAX_QUEUE*2), "SQUEUE"); 5728 if (np->dqueue) 5729 sym_mfree_dma(np->dqueue, sizeof(u32)*(MAX_QUEUE*2), "DQUEUE"); 5730 5731 if (np->actccbs) { 5732 while ((qp = sym_remque_head(&np->free_ccbq)) != NULL) { 5733 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq); 5734 sym_mfree_dma(cp, sizeof(*cp), "CCB"); 5735 } 5736 } 5737 kfree(np->ccbh); 5738 5739 if (np->badluntbl) 5740 sym_mfree_dma(np->badluntbl, 256,"BADLUNTBL"); 5741 5742 for (target = 0; target < SYM_CONF_MAX_TARGET ; target++) { 5743 tp = &np->target[target]; 5744 if (tp->luntbl) 5745 sym_mfree_dma(tp->luntbl, 256, "LUNTBL"); 5746 #if SYM_CONF_MAX_LUN > 1 5747 kfree(tp->lunmp); 5748 #endif 5749 } 5750 if (np->targtbl) 5751 sym_mfree_dma(np->targtbl, 256, "TARGTBL"); 5752 } 5753