1 /* 2 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl) 3 * 4 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net) 5 * 6 * VME support added by Sam Creasey 7 * 8 * TODO: modify this driver to support multiple Sun3 SCSI VME boards 9 * 10 * Adapted from mac_scsinew.c: 11 */ 12 /* 13 * Generic Macintosh NCR5380 driver 14 * 15 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov> 16 * 17 * derived in part from: 18 */ 19 /* 20 * Generic Generic NCR5380 driver 21 * 22 * Copyright 1995, Russell King 23 */ 24 25 #include <linux/types.h> 26 #include <linux/delay.h> 27 #include <linux/module.h> 28 #include <linux/ioport.h> 29 #include <linux/init.h> 30 #include <linux/blkdev.h> 31 #include <linux/platform_device.h> 32 33 #include <asm/io.h> 34 #include <asm/dvma.h> 35 36 #include <scsi/scsi_host.h> 37 #include "sun3_scsi.h" 38 39 /* Definitions for the core NCR5380 driver. */ 40 41 #define REAL_DMA 42 /* #define SUPPORT_TAGS */ 43 /* minimum number of bytes to do dma on */ 44 #define DMA_MIN_SIZE 129 45 46 /* #define MAX_TAGS 32 */ 47 48 #define NCR5380_implementation_fields /* none */ 49 50 #define NCR5380_read(reg) sun3scsi_read(reg) 51 #define NCR5380_write(reg, value) sun3scsi_write(reg, value) 52 53 #define NCR5380_queue_command sun3scsi_queue_command 54 #define NCR5380_bus_reset sun3scsi_bus_reset 55 #define NCR5380_abort sun3scsi_abort 56 #define NCR5380_info sun3scsi_info 57 58 #define NCR5380_dma_read_setup(instance, data, count) \ 59 sun3scsi_dma_setup(instance, data, count, 0) 60 #define NCR5380_dma_write_setup(instance, data, count) \ 61 sun3scsi_dma_setup(instance, data, count, 1) 62 #define NCR5380_dma_residual(instance) \ 63 sun3scsi_dma_residual(instance) 64 #define NCR5380_dma_xfer_len(instance, cmd, phase) \ 65 sun3scsi_dma_xfer_len(cmd->SCp.this_residual, cmd, !((phase) & SR_IO)) 66 67 #define NCR5380_acquire_dma_irq(instance) (1) 68 #define NCR5380_release_dma_irq(instance) 69 70 #include "NCR5380.h" 71 72 73 extern int sun3_map_test(unsigned long, char *); 74 75 static int setup_can_queue = -1; 76 module_param(setup_can_queue, int, 0); 77 static int setup_cmd_per_lun = -1; 78 module_param(setup_cmd_per_lun, int, 0); 79 static int setup_sg_tablesize = -1; 80 module_param(setup_sg_tablesize, int, 0); 81 #ifdef SUPPORT_TAGS 82 static int setup_use_tagged_queuing = -1; 83 module_param(setup_use_tagged_queuing, int, 0); 84 #endif 85 static int setup_hostid = -1; 86 module_param(setup_hostid, int, 0); 87 88 /* ms to wait after hitting dma regs */ 89 #define SUN3_DMA_DELAY 10 90 91 /* dvma buffer to allocate -- 32k should hopefully be more than sufficient */ 92 #define SUN3_DVMA_BUFSIZE 0xe000 93 94 static struct scsi_cmnd *sun3_dma_setup_done; 95 static unsigned char *sun3_scsi_regp; 96 static volatile struct sun3_dma_regs *dregs; 97 static struct sun3_udc_regs *udc_regs; 98 static unsigned char *sun3_dma_orig_addr; 99 static unsigned long sun3_dma_orig_count; 100 static int sun3_dma_active; 101 static unsigned long last_residual; 102 103 /* 104 * NCR 5380 register access functions 105 */ 106 107 static inline unsigned char sun3scsi_read(int reg) 108 { 109 return in_8(sun3_scsi_regp + reg); 110 } 111 112 static inline void sun3scsi_write(int reg, int value) 113 { 114 out_8(sun3_scsi_regp + reg, value); 115 } 116 117 #ifndef SUN3_SCSI_VME 118 /* dma controller register access functions */ 119 120 static inline unsigned short sun3_udc_read(unsigned char reg) 121 { 122 unsigned short ret; 123 124 dregs->udc_addr = UDC_CSR; 125 udelay(SUN3_DMA_DELAY); 126 ret = dregs->udc_data; 127 udelay(SUN3_DMA_DELAY); 128 129 return ret; 130 } 131 132 static inline void sun3_udc_write(unsigned short val, unsigned char reg) 133 { 134 dregs->udc_addr = reg; 135 udelay(SUN3_DMA_DELAY); 136 dregs->udc_data = val; 137 udelay(SUN3_DMA_DELAY); 138 } 139 #endif 140 141 // safe bits for the CSR 142 #define CSR_GOOD 0x060f 143 144 static irqreturn_t scsi_sun3_intr(int irq, void *dev) 145 { 146 struct Scsi_Host *instance = dev; 147 unsigned short csr = dregs->csr; 148 int handled = 0; 149 150 #ifdef SUN3_SCSI_VME 151 dregs->csr &= ~CSR_DMA_ENABLE; 152 #endif 153 154 if(csr & ~CSR_GOOD) { 155 if (csr & CSR_DMA_BUSERR) 156 shost_printk(KERN_ERR, instance, "bus error in DMA\n"); 157 if (csr & CSR_DMA_CONFLICT) 158 shost_printk(KERN_ERR, instance, "DMA conflict\n"); 159 handled = 1; 160 } 161 162 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { 163 NCR5380_intr(irq, dev); 164 handled = 1; 165 } 166 167 return IRQ_RETVAL(handled); 168 } 169 170 /* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */ 171 static unsigned long sun3scsi_dma_setup(struct Scsi_Host *instance, 172 void *data, unsigned long count, int write_flag) 173 { 174 void *addr; 175 176 if(sun3_dma_orig_addr != NULL) 177 dvma_unmap(sun3_dma_orig_addr); 178 179 #ifdef SUN3_SCSI_VME 180 addr = (void *)dvma_map_vme((unsigned long) data, count); 181 #else 182 addr = (void *)dvma_map((unsigned long) data, count); 183 #endif 184 185 sun3_dma_orig_addr = addr; 186 sun3_dma_orig_count = count; 187 188 #ifndef SUN3_SCSI_VME 189 dregs->fifo_count = 0; 190 sun3_udc_write(UDC_RESET, UDC_CSR); 191 192 /* reset fifo */ 193 dregs->csr &= ~CSR_FIFO; 194 dregs->csr |= CSR_FIFO; 195 #endif 196 197 /* set direction */ 198 if(write_flag) 199 dregs->csr |= CSR_SEND; 200 else 201 dregs->csr &= ~CSR_SEND; 202 203 #ifdef SUN3_SCSI_VME 204 dregs->csr |= CSR_PACK_ENABLE; 205 206 dregs->dma_addr_hi = ((unsigned long)addr >> 16); 207 dregs->dma_addr_lo = ((unsigned long)addr & 0xffff); 208 209 dregs->dma_count_hi = 0; 210 dregs->dma_count_lo = 0; 211 dregs->fifo_count_hi = 0; 212 dregs->fifo_count = 0; 213 #else 214 /* byte count for fifo */ 215 dregs->fifo_count = count; 216 217 sun3_udc_write(UDC_RESET, UDC_CSR); 218 219 /* reset fifo */ 220 dregs->csr &= ~CSR_FIFO; 221 dregs->csr |= CSR_FIFO; 222 223 if(dregs->fifo_count != count) { 224 shost_printk(KERN_ERR, instance, "FIFO mismatch %04x not %04x\n", 225 dregs->fifo_count, (unsigned int) count); 226 NCR5380_dprint(NDEBUG_DMA, instance); 227 } 228 229 /* setup udc */ 230 udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8); 231 udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff); 232 udc_regs->count = count/2; /* count in words */ 233 udc_regs->mode_hi = UDC_MODE_HIWORD; 234 if(write_flag) { 235 if(count & 1) 236 udc_regs->count++; 237 udc_regs->mode_lo = UDC_MODE_LSEND; 238 udc_regs->rsel = UDC_RSEL_SEND; 239 } else { 240 udc_regs->mode_lo = UDC_MODE_LRECV; 241 udc_regs->rsel = UDC_RSEL_RECV; 242 } 243 244 /* announce location of regs block */ 245 sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8), 246 UDC_CHN_HI); 247 248 sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO); 249 250 /* set dma master on */ 251 sun3_udc_write(0xd, UDC_MODE); 252 253 /* interrupt enable */ 254 sun3_udc_write(UDC_INT_ENABLE, UDC_CSR); 255 #endif 256 257 return count; 258 259 } 260 261 static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance) 262 { 263 return last_residual; 264 } 265 266 static inline unsigned long sun3scsi_dma_xfer_len(unsigned long wanted, 267 struct scsi_cmnd *cmd, 268 int write_flag) 269 { 270 if (cmd->request->cmd_type == REQ_TYPE_FS) 271 return wanted; 272 else 273 return 0; 274 } 275 276 static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data) 277 { 278 #ifdef SUN3_SCSI_VME 279 unsigned short csr; 280 281 csr = dregs->csr; 282 283 dregs->dma_count_hi = (sun3_dma_orig_count >> 16); 284 dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff); 285 286 dregs->fifo_count_hi = (sun3_dma_orig_count >> 16); 287 dregs->fifo_count = (sun3_dma_orig_count & 0xffff); 288 289 /* if(!(csr & CSR_DMA_ENABLE)) 290 * dregs->csr |= CSR_DMA_ENABLE; 291 */ 292 #else 293 sun3_udc_write(UDC_CHN_START, UDC_CSR); 294 #endif 295 296 return 0; 297 } 298 299 /* clean up after our dma is done */ 300 static int sun3scsi_dma_finish(int write_flag) 301 { 302 unsigned short __maybe_unused count; 303 unsigned short fifo; 304 int ret = 0; 305 306 sun3_dma_active = 0; 307 308 #ifdef SUN3_SCSI_VME 309 dregs->csr &= ~CSR_DMA_ENABLE; 310 311 fifo = dregs->fifo_count; 312 if (write_flag) { 313 if ((fifo > 0) && (fifo < sun3_dma_orig_count)) 314 fifo++; 315 } 316 317 last_residual = fifo; 318 /* empty bytes from the fifo which didn't make it */ 319 if ((!write_flag) && (dregs->csr & CSR_LEFT)) { 320 unsigned char *vaddr; 321 322 vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr); 323 324 vaddr += (sun3_dma_orig_count - fifo); 325 vaddr--; 326 327 switch (dregs->csr & CSR_LEFT) { 328 case CSR_LEFT_3: 329 *vaddr = (dregs->bpack_lo & 0xff00) >> 8; 330 vaddr--; 331 332 case CSR_LEFT_2: 333 *vaddr = (dregs->bpack_hi & 0x00ff); 334 vaddr--; 335 336 case CSR_LEFT_1: 337 *vaddr = (dregs->bpack_hi & 0xff00) >> 8; 338 break; 339 } 340 } 341 #else 342 // check to empty the fifo on a read 343 if(!write_flag) { 344 int tmo = 20000; /* .2 sec */ 345 346 while(1) { 347 if(dregs->csr & CSR_FIFO_EMPTY) 348 break; 349 350 if(--tmo <= 0) { 351 printk("sun3scsi: fifo failed to empty!\n"); 352 return 1; 353 } 354 udelay(10); 355 } 356 } 357 358 dregs->udc_addr = 0x32; 359 udelay(SUN3_DMA_DELAY); 360 count = 2 * dregs->udc_data; 361 udelay(SUN3_DMA_DELAY); 362 363 fifo = dregs->fifo_count; 364 last_residual = fifo; 365 366 /* empty bytes from the fifo which didn't make it */ 367 if((!write_flag) && (count - fifo) == 2) { 368 unsigned short data; 369 unsigned char *vaddr; 370 371 data = dregs->fifo_data; 372 vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr); 373 374 vaddr += (sun3_dma_orig_count - fifo); 375 376 vaddr[-2] = (data & 0xff00) >> 8; 377 vaddr[-1] = (data & 0xff); 378 } 379 #endif 380 381 dvma_unmap(sun3_dma_orig_addr); 382 sun3_dma_orig_addr = NULL; 383 384 #ifdef SUN3_SCSI_VME 385 dregs->dma_addr_hi = 0; 386 dregs->dma_addr_lo = 0; 387 dregs->dma_count_hi = 0; 388 dregs->dma_count_lo = 0; 389 390 dregs->fifo_count = 0; 391 dregs->fifo_count_hi = 0; 392 393 dregs->csr &= ~CSR_SEND; 394 /* dregs->csr |= CSR_DMA_ENABLE; */ 395 #else 396 sun3_udc_write(UDC_RESET, UDC_CSR); 397 dregs->fifo_count = 0; 398 dregs->csr &= ~CSR_SEND; 399 400 /* reset fifo */ 401 dregs->csr &= ~CSR_FIFO; 402 dregs->csr |= CSR_FIFO; 403 #endif 404 405 sun3_dma_setup_done = NULL; 406 407 return ret; 408 409 } 410 411 #include "atari_NCR5380.c" 412 413 #ifdef SUN3_SCSI_VME 414 #define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI" 415 #define DRV_MODULE_NAME "sun3_scsi_vme" 416 #else 417 #define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI" 418 #define DRV_MODULE_NAME "sun3_scsi" 419 #endif 420 421 #define PFX DRV_MODULE_NAME ": " 422 423 static struct scsi_host_template sun3_scsi_template = { 424 .module = THIS_MODULE, 425 .proc_name = DRV_MODULE_NAME, 426 .name = SUN3_SCSI_NAME, 427 .info = sun3scsi_info, 428 .queuecommand = sun3scsi_queue_command, 429 .eh_abort_handler = sun3scsi_abort, 430 .eh_bus_reset_handler = sun3scsi_bus_reset, 431 .can_queue = 16, 432 .this_id = 7, 433 .sg_tablesize = SG_NONE, 434 .cmd_per_lun = 2, 435 .use_clustering = DISABLE_CLUSTERING, 436 .cmd_size = NCR5380_CMD_SIZE, 437 }; 438 439 static int __init sun3_scsi_probe(struct platform_device *pdev) 440 { 441 struct Scsi_Host *instance; 442 int error; 443 struct resource *irq, *mem; 444 unsigned char *ioaddr; 445 int host_flags = 0; 446 #ifdef SUN3_SCSI_VME 447 int i; 448 #endif 449 450 if (setup_can_queue > 0) 451 sun3_scsi_template.can_queue = setup_can_queue; 452 if (setup_cmd_per_lun > 0) 453 sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun; 454 if (setup_sg_tablesize >= 0) 455 sun3_scsi_template.sg_tablesize = setup_sg_tablesize; 456 if (setup_hostid >= 0) 457 sun3_scsi_template.this_id = setup_hostid & 7; 458 459 #ifdef SUN3_SCSI_VME 460 ioaddr = NULL; 461 for (i = 0; i < 2; i++) { 462 unsigned char x; 463 464 irq = platform_get_resource(pdev, IORESOURCE_IRQ, i); 465 mem = platform_get_resource(pdev, IORESOURCE_MEM, i); 466 if (!irq || !mem) 467 break; 468 469 ioaddr = sun3_ioremap(mem->start, resource_size(mem), 470 SUN3_PAGE_TYPE_VME16); 471 dregs = (struct sun3_dma_regs *)(ioaddr + 8); 472 473 if (sun3_map_test((unsigned long)dregs, &x)) { 474 unsigned short oldcsr; 475 476 oldcsr = dregs->csr; 477 dregs->csr = 0; 478 udelay(SUN3_DMA_DELAY); 479 if (dregs->csr == 0x1400) 480 break; 481 482 dregs->csr = oldcsr; 483 } 484 485 iounmap(ioaddr); 486 ioaddr = NULL; 487 } 488 if (!ioaddr) 489 return -ENODEV; 490 #else 491 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 492 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 493 if (!irq || !mem) 494 return -ENODEV; 495 496 ioaddr = ioremap(mem->start, resource_size(mem)); 497 dregs = (struct sun3_dma_regs *)(ioaddr + 8); 498 499 udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs)); 500 if (!udc_regs) { 501 pr_err(PFX "couldn't allocate DVMA memory!\n"); 502 iounmap(ioaddr); 503 return -ENOMEM; 504 } 505 #endif 506 507 sun3_scsi_regp = ioaddr; 508 509 instance = scsi_host_alloc(&sun3_scsi_template, 510 sizeof(struct NCR5380_hostdata)); 511 if (!instance) { 512 error = -ENOMEM; 513 goto fail_alloc; 514 } 515 516 instance->io_port = (unsigned long)ioaddr; 517 instance->irq = irq->start; 518 519 #ifdef SUPPORT_TAGS 520 host_flags |= setup_use_tagged_queuing > 0 ? FLAG_TAGGED_QUEUING : 0; 521 #endif 522 523 error = NCR5380_init(instance, host_flags); 524 if (error) 525 goto fail_init; 526 527 error = request_irq(instance->irq, scsi_sun3_intr, 0, 528 "NCR5380", instance); 529 if (error) { 530 #ifdef REAL_DMA 531 pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n", 532 instance->host_no, instance->irq); 533 goto fail_irq; 534 #else 535 pr_warn(PFX "scsi%d: IRQ %d not free, interrupts disabled\n", 536 instance->host_no, instance->irq); 537 instance->irq = NO_IRQ; 538 #endif 539 } 540 541 dregs->csr = 0; 542 udelay(SUN3_DMA_DELAY); 543 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR; 544 udelay(SUN3_DMA_DELAY); 545 dregs->fifo_count = 0; 546 #ifdef SUN3_SCSI_VME 547 dregs->fifo_count_hi = 0; 548 dregs->dma_addr_hi = 0; 549 dregs->dma_addr_lo = 0; 550 dregs->dma_count_hi = 0; 551 dregs->dma_count_lo = 0; 552 553 dregs->ivect = VME_DATA24 | (instance->irq & 0xff); 554 #endif 555 556 NCR5380_maybe_reset_bus(instance); 557 558 error = scsi_add_host(instance, NULL); 559 if (error) 560 goto fail_host; 561 562 platform_set_drvdata(pdev, instance); 563 564 scsi_scan_host(instance); 565 return 0; 566 567 fail_host: 568 if (instance->irq != NO_IRQ) 569 free_irq(instance->irq, instance); 570 fail_irq: 571 NCR5380_exit(instance); 572 fail_init: 573 scsi_host_put(instance); 574 fail_alloc: 575 if (udc_regs) 576 dvma_free(udc_regs); 577 iounmap(sun3_scsi_regp); 578 return error; 579 } 580 581 static int __exit sun3_scsi_remove(struct platform_device *pdev) 582 { 583 struct Scsi_Host *instance = platform_get_drvdata(pdev); 584 585 scsi_remove_host(instance); 586 if (instance->irq != NO_IRQ) 587 free_irq(instance->irq, instance); 588 NCR5380_exit(instance); 589 scsi_host_put(instance); 590 if (udc_regs) 591 dvma_free(udc_regs); 592 iounmap(sun3_scsi_regp); 593 return 0; 594 } 595 596 static struct platform_driver sun3_scsi_driver = { 597 .remove = __exit_p(sun3_scsi_remove), 598 .driver = { 599 .name = DRV_MODULE_NAME, 600 }, 601 }; 602 603 module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe); 604 605 MODULE_ALIAS("platform:" DRV_MODULE_NAME); 606 MODULE_LICENSE("GPL"); 607