1 /* 2 * SuperTrak EX Series Storage Controller driver for Linux 3 * 4 * Copyright (C) 2005, 2006 Promise Technology Inc. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Written By: 12 * Ed Lin <promise_linux@promise.com> 13 * 14 */ 15 16 #include <linux/init.h> 17 #include <linux/errno.h> 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/time.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/interrupt.h> 24 #include <linux/types.h> 25 #include <linux/module.h> 26 #include <linux/spinlock.h> 27 #include <asm/io.h> 28 #include <asm/irq.h> 29 #include <asm/byteorder.h> 30 #include <scsi/scsi.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_host.h> 34 #include <scsi/scsi_tcq.h> 35 #include <scsi/scsi_dbg.h> 36 37 #define DRV_NAME "stex" 38 #define ST_DRIVER_VERSION "3.6.0000.1" 39 #define ST_VER_MAJOR 3 40 #define ST_VER_MINOR 6 41 #define ST_OEM 0 42 #define ST_BUILD_VER 1 43 44 enum { 45 /* MU register offset */ 46 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */ 47 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */ 48 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */ 49 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */ 50 IDBL = 0x20, /* MU_INBOUND_DOORBELL */ 51 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */ 52 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */ 53 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */ 54 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */ 55 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */ 56 57 /* MU register value */ 58 MU_INBOUND_DOORBELL_HANDSHAKE = 1, 59 MU_INBOUND_DOORBELL_REQHEADCHANGED = 2, 60 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4, 61 MU_INBOUND_DOORBELL_HMUSTOPPED = 8, 62 MU_INBOUND_DOORBELL_RESET = 16, 63 64 MU_OUTBOUND_DOORBELL_HANDSHAKE = 1, 65 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2, 66 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4, 67 MU_OUTBOUND_DOORBELL_BUSCHANGE = 8, 68 MU_OUTBOUND_DOORBELL_HASEVENT = 16, 69 70 /* MU status code */ 71 MU_STATE_STARTING = 1, 72 MU_STATE_FMU_READY_FOR_HANDSHAKE = 2, 73 MU_STATE_SEND_HANDSHAKE_FRAME = 3, 74 MU_STATE_STARTED = 4, 75 MU_STATE_RESETTING = 5, 76 77 MU_MAX_DELAY = 120, 78 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55, 79 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000, 80 MU_HARD_RESET_WAIT = 30000, 81 HMU_PARTNER_TYPE = 2, 82 83 /* firmware returned values */ 84 SRB_STATUS_SUCCESS = 0x01, 85 SRB_STATUS_ERROR = 0x04, 86 SRB_STATUS_BUSY = 0x05, 87 SRB_STATUS_INVALID_REQUEST = 0x06, 88 SRB_STATUS_SELECTION_TIMEOUT = 0x0A, 89 SRB_SEE_SENSE = 0x80, 90 91 /* task attribute */ 92 TASK_ATTRIBUTE_SIMPLE = 0x0, 93 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, 94 TASK_ATTRIBUTE_ORDERED = 0x2, 95 TASK_ATTRIBUTE_ACA = 0x4, 96 97 /* request count, etc. */ 98 MU_MAX_REQUEST = 32, 99 100 /* one message wasted, use MU_MAX_REQUEST+1 101 to handle MU_MAX_REQUEST messages */ 102 MU_REQ_COUNT = (MU_MAX_REQUEST + 1), 103 MU_STATUS_COUNT = (MU_MAX_REQUEST + 1), 104 105 STEX_CDB_LENGTH = MAX_COMMAND_SIZE, 106 REQ_VARIABLE_LEN = 1024, 107 STATUS_VAR_LEN = 128, 108 ST_CAN_QUEUE = MU_MAX_REQUEST, 109 ST_CMD_PER_LUN = MU_MAX_REQUEST, 110 ST_MAX_SG = 32, 111 112 /* sg flags */ 113 SG_CF_EOT = 0x80, /* end of table */ 114 SG_CF_64B = 0x40, /* 64 bit item */ 115 SG_CF_HOST = 0x20, /* sg in host memory */ 116 117 st_shasta = 0, 118 st_vsc = 1, 119 st_vsc1 = 2, 120 st_yosemite = 3, 121 122 PASSTHRU_REQ_TYPE = 0x00000001, 123 PASSTHRU_REQ_NO_WAKEUP = 0x00000100, 124 ST_INTERNAL_TIMEOUT = 30, 125 126 ST_TO_CMD = 0, 127 ST_FROM_CMD = 1, 128 129 /* vendor specific commands of Promise */ 130 MGT_CMD = 0xd8, 131 SINBAND_MGT_CMD = 0xd9, 132 ARRAY_CMD = 0xe0, 133 CONTROLLER_CMD = 0xe1, 134 DEBUGGING_CMD = 0xe2, 135 PASSTHRU_CMD = 0xe3, 136 137 PASSTHRU_GET_ADAPTER = 0x05, 138 PASSTHRU_GET_DRVVER = 0x10, 139 140 CTLR_CONFIG_CMD = 0x03, 141 CTLR_SHUTDOWN = 0x0d, 142 143 CTLR_POWER_STATE_CHANGE = 0x0e, 144 CTLR_POWER_SAVING = 0x01, 145 146 PASSTHRU_SIGNATURE = 0x4e415041, 147 MGT_CMD_SIGNATURE = 0xba, 148 149 INQUIRY_EVPD = 0x01, 150 151 ST_ADDITIONAL_MEM = 0x200000, 152 }; 153 154 /* SCSI inquiry data */ 155 typedef struct st_inq { 156 u8 DeviceType :5; 157 u8 DeviceTypeQualifier :3; 158 u8 DeviceTypeModifier :7; 159 u8 RemovableMedia :1; 160 u8 Versions; 161 u8 ResponseDataFormat :4; 162 u8 HiSupport :1; 163 u8 NormACA :1; 164 u8 ReservedBit :1; 165 u8 AERC :1; 166 u8 AdditionalLength; 167 u8 Reserved[2]; 168 u8 SoftReset :1; 169 u8 CommandQueue :1; 170 u8 Reserved2 :1; 171 u8 LinkedCommands :1; 172 u8 Synchronous :1; 173 u8 Wide16Bit :1; 174 u8 Wide32Bit :1; 175 u8 RelativeAddressing :1; 176 u8 VendorId[8]; 177 u8 ProductId[16]; 178 u8 ProductRevisionLevel[4]; 179 u8 VendorSpecific[20]; 180 u8 Reserved3[40]; 181 } ST_INQ; 182 183 struct st_sgitem { 184 u8 ctrl; /* SG_CF_xxx */ 185 u8 reserved[3]; 186 __le32 count; 187 __le32 addr; 188 __le32 addr_hi; 189 }; 190 191 struct st_sgtable { 192 __le16 sg_count; 193 __le16 max_sg_count; 194 __le32 sz_in_byte; 195 struct st_sgitem table[ST_MAX_SG]; 196 }; 197 198 struct handshake_frame { 199 __le32 rb_phy; /* request payload queue physical address */ 200 __le32 rb_phy_hi; 201 __le16 req_sz; /* size of each request payload */ 202 __le16 req_cnt; /* count of reqs the buffer can hold */ 203 __le16 status_sz; /* size of each status payload */ 204 __le16 status_cnt; /* count of status the buffer can hold */ 205 __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */ 206 __le32 hosttime_hi; 207 u8 partner_type; /* who sends this frame */ 208 u8 reserved0[7]; 209 __le32 partner_ver_major; 210 __le32 partner_ver_minor; 211 __le32 partner_ver_oem; 212 __le32 partner_ver_build; 213 __le32 extra_offset; /* NEW */ 214 __le32 extra_size; /* NEW */ 215 u32 reserved1[2]; 216 }; 217 218 struct req_msg { 219 __le16 tag; 220 u8 lun; 221 u8 target; 222 u8 task_attr; 223 u8 task_manage; 224 u8 prd_entry; 225 u8 payload_sz; /* payload size in 4-byte, not used */ 226 u8 cdb[STEX_CDB_LENGTH]; 227 u8 variable[REQ_VARIABLE_LEN]; 228 }; 229 230 struct status_msg { 231 __le16 tag; 232 u8 lun; 233 u8 target; 234 u8 srb_status; 235 u8 scsi_status; 236 u8 reserved; 237 u8 payload_sz; /* payload size in 4-byte */ 238 u8 variable[STATUS_VAR_LEN]; 239 }; 240 241 struct ver_info { 242 u32 major; 243 u32 minor; 244 u32 oem; 245 u32 build; 246 u32 reserved[2]; 247 }; 248 249 struct st_frame { 250 u32 base[6]; 251 u32 rom_addr; 252 253 struct ver_info drv_ver; 254 struct ver_info bios_ver; 255 256 u32 bus; 257 u32 slot; 258 u32 irq_level; 259 u32 irq_vec; 260 u32 id; 261 u32 subid; 262 263 u32 dimm_size; 264 u8 dimm_type; 265 u8 reserved[3]; 266 267 u32 channel; 268 u32 reserved1; 269 }; 270 271 struct st_drvver { 272 u32 major; 273 u32 minor; 274 u32 oem; 275 u32 build; 276 u32 signature[2]; 277 u8 console_id; 278 u8 host_no; 279 u8 reserved0[2]; 280 u32 reserved[3]; 281 }; 282 283 #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg)) 284 #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg)) 285 #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE) 286 #define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ)) 287 #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE) 288 289 struct st_ccb { 290 struct req_msg *req; 291 struct scsi_cmnd *cmd; 292 293 void *sense_buffer; 294 unsigned int sense_bufflen; 295 int sg_count; 296 297 u32 req_type; 298 u8 srb_status; 299 u8 scsi_status; 300 }; 301 302 struct st_hba { 303 void __iomem *mmio_base; /* iomapped PCI memory space */ 304 void *dma_mem; 305 dma_addr_t dma_handle; 306 size_t dma_size; 307 308 struct Scsi_Host *host; 309 struct pci_dev *pdev; 310 311 u32 req_head; 312 u32 req_tail; 313 u32 status_head; 314 u32 status_tail; 315 316 struct status_msg *status_buffer; 317 void *copy_buffer; /* temp buffer for driver-handled commands */ 318 struct st_ccb ccb[MU_MAX_REQUEST]; 319 struct st_ccb *wait_ccb; 320 wait_queue_head_t waitq; 321 322 unsigned int mu_status; 323 int out_req_cnt; 324 325 unsigned int cardtype; 326 }; 327 328 static const char console_inq_page[] = 329 { 330 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30, 331 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */ 332 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */ 333 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */ 334 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */ 335 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */ 336 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */ 337 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20 338 }; 339 340 MODULE_AUTHOR("Ed Lin"); 341 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers"); 342 MODULE_LICENSE("GPL"); 343 MODULE_VERSION(ST_DRIVER_VERSION); 344 345 static void stex_gettime(__le32 *time) 346 { 347 struct timeval tv; 348 do_gettimeofday(&tv); 349 350 *time = cpu_to_le32(tv.tv_sec & 0xffffffff); 351 *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16); 352 } 353 354 static struct status_msg *stex_get_status(struct st_hba *hba) 355 { 356 struct status_msg *status = 357 hba->status_buffer + hba->status_tail; 358 359 ++hba->status_tail; 360 hba->status_tail %= MU_STATUS_COUNT; 361 362 return status; 363 } 364 365 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq) 366 { 367 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; 368 369 cmd->sense_buffer[0] = 0x70; /* fixed format, current */ 370 cmd->sense_buffer[2] = sk; 371 cmd->sense_buffer[7] = 18 - 8; /* additional sense length */ 372 cmd->sense_buffer[12] = asc; 373 cmd->sense_buffer[13] = ascq; 374 } 375 376 static void stex_invalid_field(struct scsi_cmnd *cmd, 377 void (*done)(struct scsi_cmnd *)) 378 { 379 /* "Invalid field in cbd" */ 380 stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0); 381 done(cmd); 382 } 383 384 static struct req_msg *stex_alloc_req(struct st_hba *hba) 385 { 386 struct req_msg *req = ((struct req_msg *)hba->dma_mem) + 387 hba->req_head; 388 389 ++hba->req_head; 390 hba->req_head %= MU_REQ_COUNT; 391 392 return req; 393 } 394 395 static int stex_map_sg(struct st_hba *hba, 396 struct req_msg *req, struct st_ccb *ccb) 397 { 398 struct scsi_cmnd *cmd; 399 struct scatterlist *sg; 400 struct st_sgtable *dst; 401 int i, nseg; 402 403 cmd = ccb->cmd; 404 dst = (struct st_sgtable *)req->variable; 405 dst->max_sg_count = cpu_to_le16(ST_MAX_SG); 406 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); 407 408 nseg = scsi_dma_map(cmd); 409 if (nseg < 0) 410 return -EIO; 411 if (nseg) { 412 ccb->sg_count = nseg; 413 dst->sg_count = cpu_to_le16((u16)nseg); 414 415 scsi_for_each_sg(cmd, sg, nseg, i) { 416 dst->table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); 417 dst->table[i].addr = 418 cpu_to_le32(sg_dma_address(sg) & 0xffffffff); 419 dst->table[i].addr_hi = 420 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16); 421 dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST; 422 } 423 dst->table[--i].ctrl |= SG_CF_EOT; 424 } 425 426 return 0; 427 } 428 429 static void stex_internal_copy(struct scsi_cmnd *cmd, 430 const void *src, size_t *count, int sg_count, int direction) 431 { 432 size_t lcount; 433 size_t len; 434 void *s, *d, *base = NULL; 435 size_t offset; 436 437 if (*count > scsi_bufflen(cmd)) 438 *count = scsi_bufflen(cmd); 439 lcount = *count; 440 while (lcount) { 441 len = lcount; 442 s = (void *)src; 443 444 offset = *count - lcount; 445 s += offset; 446 base = scsi_kmap_atomic_sg(scsi_sglist(cmd), 447 sg_count, &offset, &len); 448 if (!base) { 449 *count -= lcount; 450 return; 451 } 452 d = base + offset; 453 454 if (direction == ST_TO_CMD) 455 memcpy(d, s, len); 456 else 457 memcpy(s, d, len); 458 459 lcount -= len; 460 scsi_kunmap_atomic_sg(base); 461 } 462 } 463 464 static int stex_direct_copy(struct scsi_cmnd *cmd, 465 const void *src, size_t count) 466 { 467 size_t cp_len = count; 468 int n_elem = 0; 469 470 n_elem = scsi_dma_map(cmd); 471 if (n_elem < 0) 472 return 0; 473 474 stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD); 475 476 scsi_dma_unmap(cmd); 477 478 return cp_len == count; 479 } 480 481 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb) 482 { 483 struct st_frame *p; 484 size_t count = sizeof(struct st_frame); 485 486 p = hba->copy_buffer; 487 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD); 488 memset(p->base, 0, sizeof(u32)*6); 489 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0); 490 p->rom_addr = 0; 491 492 p->drv_ver.major = ST_VER_MAJOR; 493 p->drv_ver.minor = ST_VER_MINOR; 494 p->drv_ver.oem = ST_OEM; 495 p->drv_ver.build = ST_BUILD_VER; 496 497 p->bus = hba->pdev->bus->number; 498 p->slot = hba->pdev->devfn; 499 p->irq_level = 0; 500 p->irq_vec = hba->pdev->irq; 501 p->id = hba->pdev->vendor << 16 | hba->pdev->device; 502 p->subid = 503 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device; 504 505 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD); 506 } 507 508 static void 509 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) 510 { 511 req->tag = cpu_to_le16(tag); 512 req->task_attr = TASK_ATTRIBUTE_SIMPLE; 513 req->task_manage = 0; /* not supported yet */ 514 515 hba->ccb[tag].req = req; 516 hba->out_req_cnt++; 517 518 writel(hba->req_head, hba->mmio_base + IMR0); 519 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); 520 readl(hba->mmio_base + IDBL); /* flush */ 521 } 522 523 static int 524 stex_slave_alloc(struct scsi_device *sdev) 525 { 526 /* Cheat: usually extracted from Inquiry data */ 527 sdev->tagged_supported = 1; 528 529 scsi_activate_tcq(sdev, sdev->host->can_queue); 530 531 return 0; 532 } 533 534 static int 535 stex_slave_config(struct scsi_device *sdev) 536 { 537 sdev->use_10_for_rw = 1; 538 sdev->use_10_for_ms = 1; 539 sdev->timeout = 60 * HZ; 540 sdev->tagged_supported = 1; 541 542 return 0; 543 } 544 545 static void 546 stex_slave_destroy(struct scsi_device *sdev) 547 { 548 scsi_deactivate_tcq(sdev, 1); 549 } 550 551 static int 552 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *)) 553 { 554 struct st_hba *hba; 555 struct Scsi_Host *host; 556 unsigned int id,lun; 557 struct req_msg *req; 558 u16 tag; 559 host = cmd->device->host; 560 id = cmd->device->id; 561 lun = cmd->device->lun; 562 hba = (struct st_hba *) &host->hostdata[0]; 563 564 switch (cmd->cmnd[0]) { 565 case MODE_SENSE_10: 566 { 567 static char ms10_caching_page[12] = 568 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 }; 569 unsigned char page; 570 page = cmd->cmnd[2] & 0x3f; 571 if (page == 0x8 || page == 0x3f) { 572 stex_direct_copy(cmd, ms10_caching_page, 573 sizeof(ms10_caching_page)); 574 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 575 done(cmd); 576 } else 577 stex_invalid_field(cmd, done); 578 return 0; 579 } 580 case REPORT_LUNS: 581 /* 582 * The shasta firmware does not report actual luns in the 583 * target, so fail the command to force sequential lun scan. 584 * Also, the console device does not support this command. 585 */ 586 if (hba->cardtype == st_shasta || id == host->max_id - 1) { 587 stex_invalid_field(cmd, done); 588 return 0; 589 } 590 break; 591 case TEST_UNIT_READY: 592 if (id == host->max_id - 1) { 593 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 594 done(cmd); 595 return 0; 596 } 597 break; 598 case INQUIRY: 599 if (id != host->max_id - 1) 600 break; 601 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) { 602 stex_direct_copy(cmd, console_inq_page, 603 sizeof(console_inq_page)); 604 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 605 done(cmd); 606 } else 607 stex_invalid_field(cmd, done); 608 return 0; 609 case PASSTHRU_CMD: 610 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) { 611 struct st_drvver ver; 612 ver.major = ST_VER_MAJOR; 613 ver.minor = ST_VER_MINOR; 614 ver.oem = ST_OEM; 615 ver.build = ST_BUILD_VER; 616 ver.signature[0] = PASSTHRU_SIGNATURE; 617 ver.console_id = host->max_id - 1; 618 ver.host_no = hba->host->host_no; 619 cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ? 620 DID_OK << 16 | COMMAND_COMPLETE << 8 : 621 DID_ERROR << 16 | COMMAND_COMPLETE << 8; 622 done(cmd); 623 return 0; 624 } 625 default: 626 break; 627 } 628 629 cmd->scsi_done = done; 630 631 tag = cmd->request->tag; 632 633 if (unlikely(tag >= host->can_queue)) 634 return SCSI_MLQUEUE_HOST_BUSY; 635 636 req = stex_alloc_req(hba); 637 638 req->lun = lun; 639 req->target = id; 640 641 /* cdb */ 642 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH); 643 644 hba->ccb[tag].cmd = cmd; 645 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE; 646 hba->ccb[tag].sense_buffer = cmd->sense_buffer; 647 hba->ccb[tag].req_type = 0; 648 649 if (cmd->sc_data_direction != DMA_NONE) 650 stex_map_sg(hba, req, &hba->ccb[tag]); 651 652 stex_send_cmd(hba, req, tag); 653 return 0; 654 } 655 656 static void stex_scsi_done(struct st_ccb *ccb) 657 { 658 struct scsi_cmnd *cmd = ccb->cmd; 659 int result; 660 661 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) { 662 result = ccb->scsi_status; 663 switch (ccb->scsi_status) { 664 case SAM_STAT_GOOD: 665 result |= DID_OK << 16 | COMMAND_COMPLETE << 8; 666 break; 667 case SAM_STAT_CHECK_CONDITION: 668 result |= DRIVER_SENSE << 24; 669 break; 670 case SAM_STAT_BUSY: 671 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; 672 break; 673 default: 674 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8; 675 break; 676 } 677 } 678 else if (ccb->srb_status & SRB_SEE_SENSE) 679 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION; 680 else switch (ccb->srb_status) { 681 case SRB_STATUS_SELECTION_TIMEOUT: 682 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8; 683 break; 684 case SRB_STATUS_BUSY: 685 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; 686 break; 687 case SRB_STATUS_INVALID_REQUEST: 688 case SRB_STATUS_ERROR: 689 default: 690 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8; 691 break; 692 } 693 694 cmd->result = result; 695 cmd->scsi_done(cmd); 696 } 697 698 static void stex_copy_data(struct st_ccb *ccb, 699 struct status_msg *resp, unsigned int variable) 700 { 701 size_t count = variable; 702 if (resp->scsi_status != SAM_STAT_GOOD) { 703 if (ccb->sense_buffer != NULL) 704 memcpy(ccb->sense_buffer, resp->variable, 705 min(variable, ccb->sense_bufflen)); 706 return; 707 } 708 709 if (ccb->cmd == NULL) 710 return; 711 stex_internal_copy(ccb->cmd, 712 resp->variable, &count, ccb->sg_count, ST_TO_CMD); 713 } 714 715 static void stex_ys_commands(struct st_hba *hba, 716 struct st_ccb *ccb, struct status_msg *resp) 717 { 718 size_t count; 719 720 if (ccb->cmd->cmnd[0] == MGT_CMD && 721 resp->scsi_status != SAM_STAT_CHECK_CONDITION) { 722 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) - 723 le32_to_cpu(*(__le32 *)&resp->variable[0])); 724 return; 725 } 726 727 if (resp->srb_status != 0) 728 return; 729 730 /* determine inquiry command status by DeviceTypeQualifier */ 731 if (ccb->cmd->cmnd[0] == INQUIRY && 732 resp->scsi_status == SAM_STAT_GOOD) { 733 ST_INQ *inq_data; 734 735 count = STEX_EXTRA_SIZE; 736 stex_internal_copy(ccb->cmd, hba->copy_buffer, 737 &count, ccb->sg_count, ST_FROM_CMD); 738 inq_data = (ST_INQ *)hba->copy_buffer; 739 if (inq_data->DeviceTypeQualifier != 0) 740 ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT; 741 else 742 ccb->srb_status = SRB_STATUS_SUCCESS; 743 } 744 } 745 746 static void stex_mu_intr(struct st_hba *hba, u32 doorbell) 747 { 748 void __iomem *base = hba->mmio_base; 749 struct status_msg *resp; 750 struct st_ccb *ccb; 751 unsigned int size; 752 u16 tag; 753 754 if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)) 755 return; 756 757 /* status payloads */ 758 hba->status_head = readl(base + OMR1); 759 if (unlikely(hba->status_head >= MU_STATUS_COUNT)) { 760 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n", 761 pci_name(hba->pdev)); 762 return; 763 } 764 765 /* 766 * it's not a valid status payload if: 767 * 1. there are no pending requests(e.g. during init stage) 768 * 2. there are some pending requests, but the controller is in 769 * reset status, and its type is not st_yosemite 770 * firmware of st_yosemite in reset status will return pending requests 771 * to driver, so we allow it to pass 772 */ 773 if (unlikely(hba->out_req_cnt <= 0 || 774 (hba->mu_status == MU_STATE_RESETTING && 775 hba->cardtype != st_yosemite))) { 776 hba->status_tail = hba->status_head; 777 goto update_status; 778 } 779 780 while (hba->status_tail != hba->status_head) { 781 resp = stex_get_status(hba); 782 tag = le16_to_cpu(resp->tag); 783 if (unlikely(tag >= hba->host->can_queue)) { 784 printk(KERN_WARNING DRV_NAME 785 "(%s): invalid tag\n", pci_name(hba->pdev)); 786 continue; 787 } 788 789 ccb = &hba->ccb[tag]; 790 if (hba->wait_ccb == ccb) 791 hba->wait_ccb = NULL; 792 if (unlikely(ccb->req == NULL)) { 793 printk(KERN_WARNING DRV_NAME 794 "(%s): lagging req\n", pci_name(hba->pdev)); 795 hba->out_req_cnt--; 796 continue; 797 } 798 799 size = resp->payload_sz * sizeof(u32); /* payload size */ 800 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || 801 size > sizeof(*resp))) { 802 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n", 803 pci_name(hba->pdev)); 804 } else { 805 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */ 806 if (size) 807 stex_copy_data(ccb, resp, size); 808 } 809 810 ccb->srb_status = resp->srb_status; 811 ccb->scsi_status = resp->scsi_status; 812 813 if (likely(ccb->cmd != NULL)) { 814 if (hba->cardtype == st_yosemite) 815 stex_ys_commands(hba, ccb, resp); 816 817 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD && 818 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER)) 819 stex_controller_info(hba, ccb); 820 821 scsi_dma_unmap(ccb->cmd); 822 stex_scsi_done(ccb); 823 hba->out_req_cnt--; 824 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) { 825 hba->out_req_cnt--; 826 if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) { 827 ccb->req_type = 0; 828 continue; 829 } 830 ccb->req_type = 0; 831 if (waitqueue_active(&hba->waitq)) 832 wake_up(&hba->waitq); 833 } 834 } 835 836 update_status: 837 writel(hba->status_head, base + IMR1); 838 readl(base + IMR1); /* flush */ 839 } 840 841 static irqreturn_t stex_intr(int irq, void *__hba) 842 { 843 struct st_hba *hba = __hba; 844 void __iomem *base = hba->mmio_base; 845 u32 data; 846 unsigned long flags; 847 int handled = 0; 848 849 spin_lock_irqsave(hba->host->host_lock, flags); 850 851 data = readl(base + ODBL); 852 853 if (data && data != 0xffffffff) { 854 /* clear the interrupt */ 855 writel(data, base + ODBL); 856 readl(base + ODBL); /* flush */ 857 stex_mu_intr(hba, data); 858 handled = 1; 859 } 860 861 spin_unlock_irqrestore(hba->host->host_lock, flags); 862 863 return IRQ_RETVAL(handled); 864 } 865 866 static int stex_handshake(struct st_hba *hba) 867 { 868 void __iomem *base = hba->mmio_base; 869 struct handshake_frame *h; 870 dma_addr_t status_phys; 871 u32 data; 872 unsigned long before; 873 874 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 875 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 876 readl(base + IDBL); 877 before = jiffies; 878 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 879 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 880 printk(KERN_ERR DRV_NAME 881 "(%s): no handshake signature\n", 882 pci_name(hba->pdev)); 883 return -1; 884 } 885 rmb(); 886 msleep(1); 887 } 888 } 889 890 udelay(10); 891 892 data = readl(base + OMR1); 893 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) { 894 data &= 0x0000ffff; 895 if (hba->host->can_queue > data) 896 hba->host->can_queue = data; 897 } 898 899 h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE); 900 h->rb_phy = cpu_to_le32(hba->dma_handle); 901 h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16); 902 h->req_sz = cpu_to_le16(sizeof(struct req_msg)); 903 h->req_cnt = cpu_to_le16(MU_REQ_COUNT); 904 h->status_sz = cpu_to_le16(sizeof(struct status_msg)); 905 h->status_cnt = cpu_to_le16(MU_STATUS_COUNT); 906 stex_gettime(&h->hosttime); 907 h->partner_type = HMU_PARTNER_TYPE; 908 if (hba->dma_size > STEX_BUFFER_SIZE) { 909 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE); 910 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM); 911 } else 912 h->extra_offset = h->extra_size = 0; 913 914 status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE; 915 writel(status_phys, base + IMR0); 916 readl(base + IMR0); 917 writel((status_phys >> 16) >> 16, base + IMR1); 918 readl(base + IMR1); 919 920 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */ 921 readl(base + OMR0); 922 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 923 readl(base + IDBL); /* flush */ 924 925 udelay(10); 926 before = jiffies; 927 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 928 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 929 printk(KERN_ERR DRV_NAME 930 "(%s): no signature after handshake frame\n", 931 pci_name(hba->pdev)); 932 return -1; 933 } 934 rmb(); 935 msleep(1); 936 } 937 938 writel(0, base + IMR0); 939 readl(base + IMR0); 940 writel(0, base + OMR0); 941 readl(base + OMR0); 942 writel(0, base + IMR1); 943 readl(base + IMR1); 944 writel(0, base + OMR1); 945 readl(base + OMR1); /* flush */ 946 hba->mu_status = MU_STATE_STARTED; 947 return 0; 948 } 949 950 static int stex_abort(struct scsi_cmnd *cmd) 951 { 952 struct Scsi_Host *host = cmd->device->host; 953 struct st_hba *hba = (struct st_hba *)host->hostdata; 954 u16 tag = cmd->request->tag; 955 void __iomem *base; 956 u32 data; 957 int result = SUCCESS; 958 unsigned long flags; 959 960 printk(KERN_INFO DRV_NAME 961 "(%s): aborting command\n", pci_name(hba->pdev)); 962 scsi_print_command(cmd); 963 964 base = hba->mmio_base; 965 spin_lock_irqsave(host->host_lock, flags); 966 if (tag < host->can_queue && hba->ccb[tag].cmd == cmd) 967 hba->wait_ccb = &hba->ccb[tag]; 968 else { 969 for (tag = 0; tag < host->can_queue; tag++) 970 if (hba->ccb[tag].cmd == cmd) { 971 hba->wait_ccb = &hba->ccb[tag]; 972 break; 973 } 974 if (tag >= host->can_queue) 975 goto out; 976 } 977 978 data = readl(base + ODBL); 979 if (data == 0 || data == 0xffffffff) 980 goto fail_out; 981 982 writel(data, base + ODBL); 983 readl(base + ODBL); /* flush */ 984 985 stex_mu_intr(hba, data); 986 987 if (hba->wait_ccb == NULL) { 988 printk(KERN_WARNING DRV_NAME 989 "(%s): lost interrupt\n", pci_name(hba->pdev)); 990 goto out; 991 } 992 993 fail_out: 994 scsi_dma_unmap(cmd); 995 hba->wait_ccb->req = NULL; /* nullify the req's future return */ 996 hba->wait_ccb = NULL; 997 result = FAILED; 998 out: 999 spin_unlock_irqrestore(host->host_lock, flags); 1000 return result; 1001 } 1002 1003 static void stex_hard_reset(struct st_hba *hba) 1004 { 1005 struct pci_bus *bus; 1006 int i; 1007 u16 pci_cmd; 1008 u8 pci_bctl; 1009 1010 for (i = 0; i < 16; i++) 1011 pci_read_config_dword(hba->pdev, i * 4, 1012 &hba->pdev->saved_config_space[i]); 1013 1014 /* Reset secondary bus. Our controller(MU/ATU) is the only device on 1015 secondary bus. Consult Intel 80331/3 developer's manual for detail */ 1016 bus = hba->pdev->bus; 1017 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); 1018 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; 1019 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1020 1021 /* 1022 * 1 ms may be enough for 8-port controllers. But 16-port controllers 1023 * require more time to finish bus reset. Use 100 ms here for safety 1024 */ 1025 msleep(100); 1026 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; 1027 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1028 1029 for (i = 0; i < MU_HARD_RESET_WAIT; i++) { 1030 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd); 1031 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER)) 1032 break; 1033 msleep(1); 1034 } 1035 1036 ssleep(5); 1037 for (i = 0; i < 16; i++) 1038 pci_write_config_dword(hba->pdev, i * 4, 1039 hba->pdev->saved_config_space[i]); 1040 } 1041 1042 static int stex_reset(struct scsi_cmnd *cmd) 1043 { 1044 struct st_hba *hba; 1045 unsigned long flags; 1046 unsigned long before; 1047 hba = (struct st_hba *) &cmd->device->host->hostdata[0]; 1048 1049 printk(KERN_INFO DRV_NAME 1050 "(%s): resetting host\n", pci_name(hba->pdev)); 1051 scsi_print_command(cmd); 1052 1053 hba->mu_status = MU_STATE_RESETTING; 1054 1055 if (hba->cardtype == st_shasta) 1056 stex_hard_reset(hba); 1057 1058 if (hba->cardtype != st_yosemite) { 1059 if (stex_handshake(hba)) { 1060 printk(KERN_WARNING DRV_NAME 1061 "(%s): resetting: handshake failed\n", 1062 pci_name(hba->pdev)); 1063 return FAILED; 1064 } 1065 spin_lock_irqsave(hba->host->host_lock, flags); 1066 hba->req_head = 0; 1067 hba->req_tail = 0; 1068 hba->status_head = 0; 1069 hba->status_tail = 0; 1070 hba->out_req_cnt = 0; 1071 spin_unlock_irqrestore(hba->host->host_lock, flags); 1072 return SUCCESS; 1073 } 1074 1075 /* st_yosemite */ 1076 writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL); 1077 readl(hba->mmio_base + IDBL); /* flush */ 1078 before = jiffies; 1079 while (hba->out_req_cnt > 0) { 1080 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { 1081 printk(KERN_WARNING DRV_NAME 1082 "(%s): reset timeout\n", pci_name(hba->pdev)); 1083 return FAILED; 1084 } 1085 msleep(1); 1086 } 1087 1088 hba->mu_status = MU_STATE_STARTED; 1089 return SUCCESS; 1090 } 1091 1092 static int stex_biosparam(struct scsi_device *sdev, 1093 struct block_device *bdev, sector_t capacity, int geom[]) 1094 { 1095 int heads = 255, sectors = 63; 1096 1097 if (capacity < 0x200000) { 1098 heads = 64; 1099 sectors = 32; 1100 } 1101 1102 sector_div(capacity, heads * sectors); 1103 1104 geom[0] = heads; 1105 geom[1] = sectors; 1106 geom[2] = capacity; 1107 1108 return 0; 1109 } 1110 1111 static struct scsi_host_template driver_template = { 1112 .module = THIS_MODULE, 1113 .name = DRV_NAME, 1114 .proc_name = DRV_NAME, 1115 .bios_param = stex_biosparam, 1116 .queuecommand = stex_queuecommand, 1117 .slave_alloc = stex_slave_alloc, 1118 .slave_configure = stex_slave_config, 1119 .slave_destroy = stex_slave_destroy, 1120 .eh_abort_handler = stex_abort, 1121 .eh_host_reset_handler = stex_reset, 1122 .can_queue = ST_CAN_QUEUE, 1123 .this_id = -1, 1124 .sg_tablesize = ST_MAX_SG, 1125 .cmd_per_lun = ST_CMD_PER_LUN, 1126 }; 1127 1128 static int stex_set_dma_mask(struct pci_dev * pdev) 1129 { 1130 int ret; 1131 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) 1132 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) 1133 return 0; 1134 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1135 if (!ret) 1136 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1137 return ret; 1138 } 1139 1140 static int __devinit 1141 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1142 { 1143 struct st_hba *hba; 1144 struct Scsi_Host *host; 1145 int err; 1146 1147 err = pci_enable_device(pdev); 1148 if (err) 1149 return err; 1150 1151 pci_set_master(pdev); 1152 1153 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba)); 1154 1155 if (!host) { 1156 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n", 1157 pci_name(pdev)); 1158 err = -ENOMEM; 1159 goto out_disable; 1160 } 1161 1162 hba = (struct st_hba *)host->hostdata; 1163 memset(hba, 0, sizeof(struct st_hba)); 1164 1165 err = pci_request_regions(pdev, DRV_NAME); 1166 if (err < 0) { 1167 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n", 1168 pci_name(pdev)); 1169 goto out_scsi_host_put; 1170 } 1171 1172 hba->mmio_base = ioremap_nocache(pci_resource_start(pdev, 0), 1173 pci_resource_len(pdev, 0)); 1174 if ( !hba->mmio_base) { 1175 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n", 1176 pci_name(pdev)); 1177 err = -ENOMEM; 1178 goto out_release_regions; 1179 } 1180 1181 err = stex_set_dma_mask(pdev); 1182 if (err) { 1183 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n", 1184 pci_name(pdev)); 1185 goto out_iounmap; 1186 } 1187 1188 hba->cardtype = (unsigned int) id->driver_data; 1189 if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1) 1190 hba->cardtype = st_vsc1; 1191 hba->dma_size = (hba->cardtype == st_vsc1) ? 1192 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE); 1193 hba->dma_mem = dma_alloc_coherent(&pdev->dev, 1194 hba->dma_size, &hba->dma_handle, GFP_KERNEL); 1195 if (!hba->dma_mem) { 1196 err = -ENOMEM; 1197 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n", 1198 pci_name(pdev)); 1199 goto out_iounmap; 1200 } 1201 1202 hba->status_buffer = 1203 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE); 1204 hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE; 1205 hba->mu_status = MU_STATE_STARTING; 1206 1207 if (hba->cardtype == st_shasta) { 1208 host->max_lun = 8; 1209 host->max_id = 16 + 1; 1210 } else if (hba->cardtype == st_yosemite) { 1211 host->max_lun = 128; 1212 host->max_id = 1 + 1; 1213 } else { 1214 /* st_vsc and st_vsc1 */ 1215 host->max_lun = 1; 1216 host->max_id = 128 + 1; 1217 } 1218 host->max_channel = 0; 1219 host->unique_id = host->host_no; 1220 host->max_cmd_len = STEX_CDB_LENGTH; 1221 1222 hba->host = host; 1223 hba->pdev = pdev; 1224 init_waitqueue_head(&hba->waitq); 1225 1226 err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba); 1227 if (err) { 1228 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n", 1229 pci_name(pdev)); 1230 goto out_pci_free; 1231 } 1232 1233 err = stex_handshake(hba); 1234 if (err) 1235 goto out_free_irq; 1236 1237 err = scsi_init_shared_tag_map(host, host->can_queue); 1238 if (err) { 1239 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n", 1240 pci_name(pdev)); 1241 goto out_free_irq; 1242 } 1243 1244 pci_set_drvdata(pdev, hba); 1245 1246 err = scsi_add_host(host, &pdev->dev); 1247 if (err) { 1248 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n", 1249 pci_name(pdev)); 1250 goto out_free_irq; 1251 } 1252 1253 scsi_scan_host(host); 1254 1255 return 0; 1256 1257 out_free_irq: 1258 free_irq(pdev->irq, hba); 1259 out_pci_free: 1260 dma_free_coherent(&pdev->dev, hba->dma_size, 1261 hba->dma_mem, hba->dma_handle); 1262 out_iounmap: 1263 iounmap(hba->mmio_base); 1264 out_release_regions: 1265 pci_release_regions(pdev); 1266 out_scsi_host_put: 1267 scsi_host_put(host); 1268 out_disable: 1269 pci_disable_device(pdev); 1270 1271 return err; 1272 } 1273 1274 static void stex_hba_stop(struct st_hba *hba) 1275 { 1276 struct req_msg *req; 1277 unsigned long flags; 1278 unsigned long before; 1279 u16 tag = 0; 1280 1281 spin_lock_irqsave(hba->host->host_lock, flags); 1282 req = stex_alloc_req(hba); 1283 memset(req->cdb, 0, STEX_CDB_LENGTH); 1284 1285 if (hba->cardtype == st_yosemite) { 1286 req->cdb[0] = MGT_CMD; 1287 req->cdb[1] = MGT_CMD_SIGNATURE; 1288 req->cdb[2] = CTLR_CONFIG_CMD; 1289 req->cdb[3] = CTLR_SHUTDOWN; 1290 } else { 1291 req->cdb[0] = CONTROLLER_CMD; 1292 req->cdb[1] = CTLR_POWER_STATE_CHANGE; 1293 req->cdb[2] = CTLR_POWER_SAVING; 1294 } 1295 1296 hba->ccb[tag].cmd = NULL; 1297 hba->ccb[tag].sg_count = 0; 1298 hba->ccb[tag].sense_bufflen = 0; 1299 hba->ccb[tag].sense_buffer = NULL; 1300 hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE; 1301 1302 stex_send_cmd(hba, req, tag); 1303 spin_unlock_irqrestore(hba->host->host_lock, flags); 1304 1305 before = jiffies; 1306 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) { 1307 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) 1308 return; 1309 msleep(10); 1310 } 1311 } 1312 1313 static void stex_hba_free(struct st_hba *hba) 1314 { 1315 free_irq(hba->pdev->irq, hba); 1316 1317 iounmap(hba->mmio_base); 1318 1319 pci_release_regions(hba->pdev); 1320 1321 dma_free_coherent(&hba->pdev->dev, hba->dma_size, 1322 hba->dma_mem, hba->dma_handle); 1323 } 1324 1325 static void stex_remove(struct pci_dev *pdev) 1326 { 1327 struct st_hba *hba = pci_get_drvdata(pdev); 1328 1329 scsi_remove_host(hba->host); 1330 1331 pci_set_drvdata(pdev, NULL); 1332 1333 stex_hba_stop(hba); 1334 1335 stex_hba_free(hba); 1336 1337 scsi_host_put(hba->host); 1338 1339 pci_disable_device(pdev); 1340 } 1341 1342 static void stex_shutdown(struct pci_dev *pdev) 1343 { 1344 struct st_hba *hba = pci_get_drvdata(pdev); 1345 1346 stex_hba_stop(hba); 1347 } 1348 1349 static struct pci_device_id stex_pci_tbl[] = { 1350 /* st_shasta */ 1351 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1352 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */ 1353 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1354 st_shasta }, /* SuperTrak EX12350 */ 1355 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1356 st_shasta }, /* SuperTrak EX4350 */ 1357 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1358 st_shasta }, /* SuperTrak EX24350 */ 1359 1360 /* st_vsc */ 1361 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc }, 1362 1363 /* st_yosemite */ 1364 { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0, 1365 st_yosemite }, /* SuperTrak EX4650 */ 1366 { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0, 1367 st_yosemite }, /* SuperTrak EX4650o */ 1368 { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0, 1369 st_yosemite }, /* SuperTrak EX8650EL */ 1370 { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0, 1371 st_yosemite }, /* SuperTrak EX8650 */ 1372 { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0, 1373 st_yosemite }, /* SuperTrak EX8654 */ 1374 { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1375 st_yosemite }, /* generic st_yosemite */ 1376 { } /* terminate list */ 1377 }; 1378 MODULE_DEVICE_TABLE(pci, stex_pci_tbl); 1379 1380 static struct pci_driver stex_pci_driver = { 1381 .name = DRV_NAME, 1382 .id_table = stex_pci_tbl, 1383 .probe = stex_probe, 1384 .remove = __devexit_p(stex_remove), 1385 .shutdown = stex_shutdown, 1386 }; 1387 1388 static int __init stex_init(void) 1389 { 1390 printk(KERN_INFO DRV_NAME 1391 ": Promise SuperTrak EX Driver version: %s\n", 1392 ST_DRIVER_VERSION); 1393 1394 return pci_register_driver(&stex_pci_driver); 1395 } 1396 1397 static void __exit stex_exit(void) 1398 { 1399 pci_unregister_driver(&stex_pci_driver); 1400 } 1401 1402 module_init(stex_init); 1403 module_exit(stex_exit); 1404