1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * SuperTrak EX Series Storage Controller driver for Linux 4 * 5 * Copyright (C) 2005-2015 Promise Technology Inc. 6 * 7 * Written By: 8 * Ed Lin <promise_linux@promise.com> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/errno.h> 13 #include <linux/kernel.h> 14 #include <linux/delay.h> 15 #include <linux/slab.h> 16 #include <linux/time.h> 17 #include <linux/pci.h> 18 #include <linux/blkdev.h> 19 #include <linux/interrupt.h> 20 #include <linux/types.h> 21 #include <linux/module.h> 22 #include <linux/spinlock.h> 23 #include <linux/ktime.h> 24 #include <linux/reboot.h> 25 #include <asm/io.h> 26 #include <asm/irq.h> 27 #include <asm/byteorder.h> 28 #include <scsi/scsi.h> 29 #include <scsi/scsi_device.h> 30 #include <scsi/scsi_cmnd.h> 31 #include <scsi/scsi_host.h> 32 #include <scsi/scsi_tcq.h> 33 #include <scsi/scsi_dbg.h> 34 #include <scsi/scsi_eh.h> 35 36 #define DRV_NAME "stex" 37 #define ST_DRIVER_VERSION "6.02.0000.01" 38 #define ST_VER_MAJOR 6 39 #define ST_VER_MINOR 02 40 #define ST_OEM 0000 41 #define ST_BUILD_VER 01 42 43 enum { 44 /* MU register offset */ 45 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */ 46 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */ 47 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */ 48 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */ 49 IDBL = 0x20, /* MU_INBOUND_DOORBELL */ 50 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */ 51 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */ 52 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */ 53 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */ 54 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */ 55 56 YIOA_STATUS = 0x00, 57 YH2I_INT = 0x20, 58 YINT_EN = 0x34, 59 YI2H_INT = 0x9c, 60 YI2H_INT_C = 0xa0, 61 YH2I_REQ = 0xc0, 62 YH2I_REQ_HI = 0xc4, 63 PSCRATCH0 = 0xb0, 64 PSCRATCH1 = 0xb4, 65 PSCRATCH2 = 0xb8, 66 PSCRATCH3 = 0xbc, 67 PSCRATCH4 = 0xc8, 68 MAILBOX_BASE = 0x1000, 69 MAILBOX_HNDSHK_STS = 0x0, 70 71 /* MU register value */ 72 MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0), 73 MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1), 74 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2), 75 MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3), 76 MU_INBOUND_DOORBELL_RESET = (1 << 4), 77 78 MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0), 79 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1), 80 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2), 81 MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3), 82 MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4), 83 MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27), 84 85 /* MU status code */ 86 MU_STATE_STARTING = 1, 87 MU_STATE_STARTED = 2, 88 MU_STATE_RESETTING = 3, 89 MU_STATE_FAILED = 4, 90 MU_STATE_STOP = 5, 91 MU_STATE_NOCONNECT = 6, 92 93 MU_MAX_DELAY = 50, 94 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55, 95 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000, 96 MU_HARD_RESET_WAIT = 30000, 97 HMU_PARTNER_TYPE = 2, 98 99 /* firmware returned values */ 100 SRB_STATUS_SUCCESS = 0x01, 101 SRB_STATUS_ERROR = 0x04, 102 SRB_STATUS_BUSY = 0x05, 103 SRB_STATUS_INVALID_REQUEST = 0x06, 104 SRB_STATUS_SELECTION_TIMEOUT = 0x0A, 105 SRB_SEE_SENSE = 0x80, 106 107 /* task attribute */ 108 TASK_ATTRIBUTE_SIMPLE = 0x0, 109 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, 110 TASK_ATTRIBUTE_ORDERED = 0x2, 111 TASK_ATTRIBUTE_ACA = 0x4, 112 113 SS_STS_NORMAL = 0x80000000, 114 SS_STS_DONE = 0x40000000, 115 SS_STS_HANDSHAKE = 0x20000000, 116 117 SS_HEAD_HANDSHAKE = 0x80, 118 119 SS_H2I_INT_RESET = 0x100, 120 121 SS_I2H_REQUEST_RESET = 0x2000, 122 123 SS_MU_OPERATIONAL = 0x80000000, 124 125 STEX_CDB_LENGTH = 16, 126 STATUS_VAR_LEN = 128, 127 128 /* sg flags */ 129 SG_CF_EOT = 0x80, /* end of table */ 130 SG_CF_64B = 0x40, /* 64 bit item */ 131 SG_CF_HOST = 0x20, /* sg in host memory */ 132 MSG_DATA_DIR_ND = 0, 133 MSG_DATA_DIR_IN = 1, 134 MSG_DATA_DIR_OUT = 2, 135 136 st_shasta = 0, 137 st_vsc = 1, 138 st_yosemite = 2, 139 st_seq = 3, 140 st_yel = 4, 141 st_P3 = 5, 142 143 PASSTHRU_REQ_TYPE = 0x00000001, 144 PASSTHRU_REQ_NO_WAKEUP = 0x00000100, 145 ST_INTERNAL_TIMEOUT = 180, 146 147 ST_TO_CMD = 0, 148 ST_FROM_CMD = 1, 149 150 /* vendor specific commands of Promise */ 151 MGT_CMD = 0xd8, 152 SINBAND_MGT_CMD = 0xd9, 153 ARRAY_CMD = 0xe0, 154 CONTROLLER_CMD = 0xe1, 155 DEBUGGING_CMD = 0xe2, 156 PASSTHRU_CMD = 0xe3, 157 158 PASSTHRU_GET_ADAPTER = 0x05, 159 PASSTHRU_GET_DRVVER = 0x10, 160 161 CTLR_CONFIG_CMD = 0x03, 162 CTLR_SHUTDOWN = 0x0d, 163 164 CTLR_POWER_STATE_CHANGE = 0x0e, 165 CTLR_POWER_SAVING = 0x01, 166 167 PASSTHRU_SIGNATURE = 0x4e415041, 168 MGT_CMD_SIGNATURE = 0xba, 169 170 INQUIRY_EVPD = 0x01, 171 172 ST_ADDITIONAL_MEM = 0x200000, 173 ST_ADDITIONAL_MEM_MIN = 0x80000, 174 PMIC_SHUTDOWN = 0x0D, 175 PMIC_REUMSE = 0x10, 176 ST_IGNORED = -1, 177 ST_NOTHANDLED = 7, 178 ST_S3 = 3, 179 ST_S4 = 4, 180 ST_S5 = 5, 181 ST_S6 = 6, 182 }; 183 184 struct st_sgitem { 185 u8 ctrl; /* SG_CF_xxx */ 186 u8 reserved[3]; 187 __le32 count; 188 __le64 addr; 189 }; 190 191 struct st_ss_sgitem { 192 __le32 addr; 193 __le32 addr_hi; 194 __le32 count; 195 }; 196 197 struct st_sgtable { 198 __le16 sg_count; 199 __le16 max_sg_count; 200 __le32 sz_in_byte; 201 }; 202 203 struct st_msg_header { 204 __le64 handle; 205 u8 flag; 206 u8 channel; 207 __le16 timeout; 208 u32 reserved; 209 }; 210 211 struct handshake_frame { 212 __le64 rb_phy; /* request payload queue physical address */ 213 __le16 req_sz; /* size of each request payload */ 214 __le16 req_cnt; /* count of reqs the buffer can hold */ 215 __le16 status_sz; /* size of each status payload */ 216 __le16 status_cnt; /* count of status the buffer can hold */ 217 __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */ 218 u8 partner_type; /* who sends this frame */ 219 u8 reserved0[7]; 220 __le32 partner_ver_major; 221 __le32 partner_ver_minor; 222 __le32 partner_ver_oem; 223 __le32 partner_ver_build; 224 __le32 extra_offset; /* NEW */ 225 __le32 extra_size; /* NEW */ 226 __le32 scratch_size; 227 u32 reserved1; 228 }; 229 230 struct req_msg { 231 __le16 tag; 232 u8 lun; 233 u8 target; 234 u8 task_attr; 235 u8 task_manage; 236 u8 data_dir; 237 u8 payload_sz; /* payload size in 4-byte, not used */ 238 u8 cdb[STEX_CDB_LENGTH]; 239 u32 variable[]; 240 }; 241 242 struct status_msg { 243 __le16 tag; 244 u8 lun; 245 u8 target; 246 u8 srb_status; 247 u8 scsi_status; 248 u8 reserved; 249 u8 payload_sz; /* payload size in 4-byte */ 250 u8 variable[STATUS_VAR_LEN]; 251 }; 252 253 struct ver_info { 254 u32 major; 255 u32 minor; 256 u32 oem; 257 u32 build; 258 u32 reserved[2]; 259 }; 260 261 struct st_frame { 262 u32 base[6]; 263 u32 rom_addr; 264 265 struct ver_info drv_ver; 266 struct ver_info bios_ver; 267 268 u32 bus; 269 u32 slot; 270 u32 irq_level; 271 u32 irq_vec; 272 u32 id; 273 u32 subid; 274 275 u32 dimm_size; 276 u8 dimm_type; 277 u8 reserved[3]; 278 279 u32 channel; 280 u32 reserved1; 281 }; 282 283 struct st_drvver { 284 u32 major; 285 u32 minor; 286 u32 oem; 287 u32 build; 288 u32 signature[2]; 289 u8 console_id; 290 u8 host_no; 291 u8 reserved0[2]; 292 u32 reserved[3]; 293 }; 294 295 struct st_ccb { 296 struct req_msg *req; 297 struct scsi_cmnd *cmd; 298 299 void *sense_buffer; 300 unsigned int sense_bufflen; 301 int sg_count; 302 303 u32 req_type; 304 u8 srb_status; 305 u8 scsi_status; 306 u8 reserved[2]; 307 }; 308 309 struct st_hba { 310 void __iomem *mmio_base; /* iomapped PCI memory space */ 311 void *dma_mem; 312 dma_addr_t dma_handle; 313 size_t dma_size; 314 315 struct Scsi_Host *host; 316 struct pci_dev *pdev; 317 318 struct req_msg * (*alloc_rq) (struct st_hba *); 319 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *); 320 void (*send) (struct st_hba *, struct req_msg *, u16); 321 322 u32 req_head; 323 u32 req_tail; 324 u32 status_head; 325 u32 status_tail; 326 327 struct status_msg *status_buffer; 328 void *copy_buffer; /* temp buffer for driver-handled commands */ 329 struct st_ccb *ccb; 330 struct st_ccb *wait_ccb; 331 __le32 *scratch; 332 333 char work_q_name[20]; 334 struct workqueue_struct *work_q; 335 struct work_struct reset_work; 336 wait_queue_head_t reset_waitq; 337 unsigned int mu_status; 338 unsigned int cardtype; 339 int msi_enabled; 340 int out_req_cnt; 341 u32 extra_offset; 342 u16 rq_count; 343 u16 rq_size; 344 u16 sts_count; 345 u8 supports_pm; 346 int msi_lock; 347 }; 348 349 struct st_card_info { 350 struct req_msg * (*alloc_rq) (struct st_hba *); 351 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *); 352 void (*send) (struct st_hba *, struct req_msg *, u16); 353 unsigned int max_id; 354 unsigned int max_lun; 355 unsigned int max_channel; 356 u16 rq_count; 357 u16 rq_size; 358 u16 sts_count; 359 }; 360 361 static int S6flag; 362 static int stex_halt(struct notifier_block *nb, ulong event, void *buf); 363 static struct notifier_block stex_notifier = { 364 stex_halt, NULL, 0 365 }; 366 367 static int msi; 368 module_param(msi, int, 0); 369 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)"); 370 371 static const char console_inq_page[] = 372 { 373 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30, 374 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */ 375 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */ 376 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */ 377 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */ 378 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */ 379 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */ 380 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20 381 }; 382 383 MODULE_AUTHOR("Ed Lin"); 384 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers"); 385 MODULE_LICENSE("GPL"); 386 MODULE_VERSION(ST_DRIVER_VERSION); 387 388 static struct status_msg *stex_get_status(struct st_hba *hba) 389 { 390 struct status_msg *status = hba->status_buffer + hba->status_tail; 391 392 ++hba->status_tail; 393 hba->status_tail %= hba->sts_count+1; 394 395 return status; 396 } 397 398 static void stex_invalid_field(struct scsi_cmnd *cmd, 399 void (*done)(struct scsi_cmnd *)) 400 { 401 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; 402 403 /* "Invalid field in cdb" */ 404 scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24, 405 0x0); 406 done(cmd); 407 } 408 409 static struct req_msg *stex_alloc_req(struct st_hba *hba) 410 { 411 struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size; 412 413 ++hba->req_head; 414 hba->req_head %= hba->rq_count+1; 415 416 return req; 417 } 418 419 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba) 420 { 421 return (struct req_msg *)(hba->dma_mem + 422 hba->req_head * hba->rq_size + sizeof(struct st_msg_header)); 423 } 424 425 static int stex_map_sg(struct st_hba *hba, 426 struct req_msg *req, struct st_ccb *ccb) 427 { 428 struct scsi_cmnd *cmd; 429 struct scatterlist *sg; 430 struct st_sgtable *dst; 431 struct st_sgitem *table; 432 int i, nseg; 433 434 cmd = ccb->cmd; 435 nseg = scsi_dma_map(cmd); 436 BUG_ON(nseg < 0); 437 if (nseg) { 438 dst = (struct st_sgtable *)req->variable; 439 440 ccb->sg_count = nseg; 441 dst->sg_count = cpu_to_le16((u16)nseg); 442 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize); 443 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); 444 445 table = (struct st_sgitem *)(dst + 1); 446 scsi_for_each_sg(cmd, sg, nseg, i) { 447 table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); 448 table[i].addr = cpu_to_le64(sg_dma_address(sg)); 449 table[i].ctrl = SG_CF_64B | SG_CF_HOST; 450 } 451 table[--i].ctrl |= SG_CF_EOT; 452 } 453 454 return nseg; 455 } 456 457 static int stex_ss_map_sg(struct st_hba *hba, 458 struct req_msg *req, struct st_ccb *ccb) 459 { 460 struct scsi_cmnd *cmd; 461 struct scatterlist *sg; 462 struct st_sgtable *dst; 463 struct st_ss_sgitem *table; 464 int i, nseg; 465 466 cmd = ccb->cmd; 467 nseg = scsi_dma_map(cmd); 468 BUG_ON(nseg < 0); 469 if (nseg) { 470 dst = (struct st_sgtable *)req->variable; 471 472 ccb->sg_count = nseg; 473 dst->sg_count = cpu_to_le16((u16)nseg); 474 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize); 475 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); 476 477 table = (struct st_ss_sgitem *)(dst + 1); 478 scsi_for_each_sg(cmd, sg, nseg, i) { 479 table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); 480 table[i].addr = 481 cpu_to_le32(sg_dma_address(sg) & 0xffffffff); 482 table[i].addr_hi = 483 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16); 484 } 485 } 486 487 return nseg; 488 } 489 490 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb) 491 { 492 struct st_frame *p; 493 size_t count = sizeof(struct st_frame); 494 495 p = hba->copy_buffer; 496 scsi_sg_copy_to_buffer(ccb->cmd, p, count); 497 memset(p->base, 0, sizeof(u32)*6); 498 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0); 499 p->rom_addr = 0; 500 501 p->drv_ver.major = ST_VER_MAJOR; 502 p->drv_ver.minor = ST_VER_MINOR; 503 p->drv_ver.oem = ST_OEM; 504 p->drv_ver.build = ST_BUILD_VER; 505 506 p->bus = hba->pdev->bus->number; 507 p->slot = hba->pdev->devfn; 508 p->irq_level = 0; 509 p->irq_vec = hba->pdev->irq; 510 p->id = hba->pdev->vendor << 16 | hba->pdev->device; 511 p->subid = 512 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device; 513 514 scsi_sg_copy_from_buffer(ccb->cmd, p, count); 515 } 516 517 static void 518 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) 519 { 520 req->tag = cpu_to_le16(tag); 521 522 hba->ccb[tag].req = req; 523 hba->out_req_cnt++; 524 525 writel(hba->req_head, hba->mmio_base + IMR0); 526 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); 527 readl(hba->mmio_base + IDBL); /* flush */ 528 } 529 530 static void 531 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) 532 { 533 struct scsi_cmnd *cmd; 534 struct st_msg_header *msg_h; 535 dma_addr_t addr; 536 537 req->tag = cpu_to_le16(tag); 538 539 hba->ccb[tag].req = req; 540 hba->out_req_cnt++; 541 542 cmd = hba->ccb[tag].cmd; 543 msg_h = (struct st_msg_header *)req - 1; 544 if (likely(cmd)) { 545 msg_h->channel = (u8)cmd->device->channel; 546 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ); 547 } 548 addr = hba->dma_handle + hba->req_head * hba->rq_size; 549 addr += (hba->ccb[tag].sg_count+4)/11; 550 msg_h->handle = cpu_to_le64(addr); 551 552 ++hba->req_head; 553 hba->req_head %= hba->rq_count+1; 554 if (hba->cardtype == st_P3) { 555 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); 556 writel(addr, hba->mmio_base + YH2I_REQ); 557 } else { 558 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); 559 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */ 560 writel(addr, hba->mmio_base + YH2I_REQ); 561 readl(hba->mmio_base + YH2I_REQ); /* flush */ 562 } 563 } 564 565 static void return_abnormal_state(struct st_hba *hba, int status) 566 { 567 struct st_ccb *ccb; 568 unsigned long flags; 569 u16 tag; 570 571 spin_lock_irqsave(hba->host->host_lock, flags); 572 for (tag = 0; tag < hba->host->can_queue; tag++) { 573 ccb = &hba->ccb[tag]; 574 if (ccb->req == NULL) 575 continue; 576 ccb->req = NULL; 577 if (ccb->cmd) { 578 scsi_dma_unmap(ccb->cmd); 579 ccb->cmd->result = status << 16; 580 ccb->cmd->scsi_done(ccb->cmd); 581 ccb->cmd = NULL; 582 } 583 } 584 spin_unlock_irqrestore(hba->host->host_lock, flags); 585 } 586 static int 587 stex_slave_config(struct scsi_device *sdev) 588 { 589 sdev->use_10_for_rw = 1; 590 sdev->use_10_for_ms = 1; 591 blk_queue_rq_timeout(sdev->request_queue, 60 * HZ); 592 593 return 0; 594 } 595 596 static int 597 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *)) 598 { 599 struct st_hba *hba; 600 struct Scsi_Host *host; 601 unsigned int id, lun; 602 struct req_msg *req; 603 u16 tag; 604 605 host = cmd->device->host; 606 id = cmd->device->id; 607 lun = cmd->device->lun; 608 hba = (struct st_hba *) &host->hostdata[0]; 609 if (hba->mu_status == MU_STATE_NOCONNECT) { 610 cmd->result = DID_NO_CONNECT; 611 done(cmd); 612 return 0; 613 } 614 if (unlikely(hba->mu_status != MU_STATE_STARTED)) 615 return SCSI_MLQUEUE_HOST_BUSY; 616 617 switch (cmd->cmnd[0]) { 618 case MODE_SENSE_10: 619 { 620 static char ms10_caching_page[12] = 621 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 }; 622 unsigned char page; 623 624 page = cmd->cmnd[2] & 0x3f; 625 if (page == 0x8 || page == 0x3f) { 626 scsi_sg_copy_from_buffer(cmd, ms10_caching_page, 627 sizeof(ms10_caching_page)); 628 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 629 done(cmd); 630 } else 631 stex_invalid_field(cmd, done); 632 return 0; 633 } 634 case REPORT_LUNS: 635 /* 636 * The shasta firmware does not report actual luns in the 637 * target, so fail the command to force sequential lun scan. 638 * Also, the console device does not support this command. 639 */ 640 if (hba->cardtype == st_shasta || id == host->max_id - 1) { 641 stex_invalid_field(cmd, done); 642 return 0; 643 } 644 break; 645 case TEST_UNIT_READY: 646 if (id == host->max_id - 1) { 647 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 648 done(cmd); 649 return 0; 650 } 651 break; 652 case INQUIRY: 653 if (lun >= host->max_lun) { 654 cmd->result = DID_NO_CONNECT << 16; 655 done(cmd); 656 return 0; 657 } 658 if (id != host->max_id - 1) 659 break; 660 if (!lun && !cmd->device->channel && 661 (cmd->cmnd[1] & INQUIRY_EVPD) == 0) { 662 scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page, 663 sizeof(console_inq_page)); 664 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 665 done(cmd); 666 } else 667 stex_invalid_field(cmd, done); 668 return 0; 669 case PASSTHRU_CMD: 670 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) { 671 struct st_drvver ver; 672 size_t cp_len = sizeof(ver); 673 674 ver.major = ST_VER_MAJOR; 675 ver.minor = ST_VER_MINOR; 676 ver.oem = ST_OEM; 677 ver.build = ST_BUILD_VER; 678 ver.signature[0] = PASSTHRU_SIGNATURE; 679 ver.console_id = host->max_id - 1; 680 ver.host_no = hba->host->host_no; 681 cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len); 682 cmd->result = sizeof(ver) == cp_len ? 683 DID_OK << 16 | COMMAND_COMPLETE << 8 : 684 DID_ERROR << 16 | COMMAND_COMPLETE << 8; 685 done(cmd); 686 return 0; 687 } 688 default: 689 break; 690 } 691 692 cmd->scsi_done = done; 693 694 tag = cmd->request->tag; 695 696 if (unlikely(tag >= host->can_queue)) 697 return SCSI_MLQUEUE_HOST_BUSY; 698 699 req = hba->alloc_rq(hba); 700 701 req->lun = lun; 702 req->target = id; 703 704 /* cdb */ 705 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH); 706 707 if (cmd->sc_data_direction == DMA_FROM_DEVICE) 708 req->data_dir = MSG_DATA_DIR_IN; 709 else if (cmd->sc_data_direction == DMA_TO_DEVICE) 710 req->data_dir = MSG_DATA_DIR_OUT; 711 else 712 req->data_dir = MSG_DATA_DIR_ND; 713 714 hba->ccb[tag].cmd = cmd; 715 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE; 716 hba->ccb[tag].sense_buffer = cmd->sense_buffer; 717 718 if (!hba->map_sg(hba, req, &hba->ccb[tag])) { 719 hba->ccb[tag].sg_count = 0; 720 memset(&req->variable[0], 0, 8); 721 } 722 723 hba->send(hba, req, tag); 724 return 0; 725 } 726 727 static DEF_SCSI_QCMD(stex_queuecommand) 728 729 static void stex_scsi_done(struct st_ccb *ccb) 730 { 731 struct scsi_cmnd *cmd = ccb->cmd; 732 int result; 733 734 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) { 735 result = ccb->scsi_status; 736 switch (ccb->scsi_status) { 737 case SAM_STAT_GOOD: 738 result |= DID_OK << 16 | COMMAND_COMPLETE << 8; 739 break; 740 case SAM_STAT_CHECK_CONDITION: 741 result |= DRIVER_SENSE << 24; 742 break; 743 case SAM_STAT_BUSY: 744 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; 745 break; 746 default: 747 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8; 748 break; 749 } 750 } 751 else if (ccb->srb_status & SRB_SEE_SENSE) 752 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION; 753 else switch (ccb->srb_status) { 754 case SRB_STATUS_SELECTION_TIMEOUT: 755 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8; 756 break; 757 case SRB_STATUS_BUSY: 758 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; 759 break; 760 case SRB_STATUS_INVALID_REQUEST: 761 case SRB_STATUS_ERROR: 762 default: 763 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8; 764 break; 765 } 766 767 cmd->result = result; 768 cmd->scsi_done(cmd); 769 } 770 771 static void stex_copy_data(struct st_ccb *ccb, 772 struct status_msg *resp, unsigned int variable) 773 { 774 if (resp->scsi_status != SAM_STAT_GOOD) { 775 if (ccb->sense_buffer != NULL) 776 memcpy(ccb->sense_buffer, resp->variable, 777 min(variable, ccb->sense_bufflen)); 778 return; 779 } 780 781 if (ccb->cmd == NULL) 782 return; 783 scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable); 784 } 785 786 static void stex_check_cmd(struct st_hba *hba, 787 struct st_ccb *ccb, struct status_msg *resp) 788 { 789 if (ccb->cmd->cmnd[0] == MGT_CMD && 790 resp->scsi_status != SAM_STAT_CHECK_CONDITION) 791 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) - 792 le32_to_cpu(*(__le32 *)&resp->variable[0])); 793 } 794 795 static void stex_mu_intr(struct st_hba *hba, u32 doorbell) 796 { 797 void __iomem *base = hba->mmio_base; 798 struct status_msg *resp; 799 struct st_ccb *ccb; 800 unsigned int size; 801 u16 tag; 802 803 if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))) 804 return; 805 806 /* status payloads */ 807 hba->status_head = readl(base + OMR1); 808 if (unlikely(hba->status_head > hba->sts_count)) { 809 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n", 810 pci_name(hba->pdev)); 811 return; 812 } 813 814 /* 815 * it's not a valid status payload if: 816 * 1. there are no pending requests(e.g. during init stage) 817 * 2. there are some pending requests, but the controller is in 818 * reset status, and its type is not st_yosemite 819 * firmware of st_yosemite in reset status will return pending requests 820 * to driver, so we allow it to pass 821 */ 822 if (unlikely(hba->out_req_cnt <= 0 || 823 (hba->mu_status == MU_STATE_RESETTING && 824 hba->cardtype != st_yosemite))) { 825 hba->status_tail = hba->status_head; 826 goto update_status; 827 } 828 829 while (hba->status_tail != hba->status_head) { 830 resp = stex_get_status(hba); 831 tag = le16_to_cpu(resp->tag); 832 if (unlikely(tag >= hba->host->can_queue)) { 833 printk(KERN_WARNING DRV_NAME 834 "(%s): invalid tag\n", pci_name(hba->pdev)); 835 continue; 836 } 837 838 hba->out_req_cnt--; 839 ccb = &hba->ccb[tag]; 840 if (unlikely(hba->wait_ccb == ccb)) 841 hba->wait_ccb = NULL; 842 if (unlikely(ccb->req == NULL)) { 843 printk(KERN_WARNING DRV_NAME 844 "(%s): lagging req\n", pci_name(hba->pdev)); 845 continue; 846 } 847 848 size = resp->payload_sz * sizeof(u32); /* payload size */ 849 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || 850 size > sizeof(*resp))) { 851 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n", 852 pci_name(hba->pdev)); 853 } else { 854 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */ 855 if (size) 856 stex_copy_data(ccb, resp, size); 857 } 858 859 ccb->req = NULL; 860 ccb->srb_status = resp->srb_status; 861 ccb->scsi_status = resp->scsi_status; 862 863 if (likely(ccb->cmd != NULL)) { 864 if (hba->cardtype == st_yosemite) 865 stex_check_cmd(hba, ccb, resp); 866 867 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD && 868 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER)) 869 stex_controller_info(hba, ccb); 870 871 scsi_dma_unmap(ccb->cmd); 872 stex_scsi_done(ccb); 873 } else 874 ccb->req_type = 0; 875 } 876 877 update_status: 878 writel(hba->status_head, base + IMR1); 879 readl(base + IMR1); /* flush */ 880 } 881 882 static irqreturn_t stex_intr(int irq, void *__hba) 883 { 884 struct st_hba *hba = __hba; 885 void __iomem *base = hba->mmio_base; 886 u32 data; 887 unsigned long flags; 888 889 spin_lock_irqsave(hba->host->host_lock, flags); 890 891 data = readl(base + ODBL); 892 893 if (data && data != 0xffffffff) { 894 /* clear the interrupt */ 895 writel(data, base + ODBL); 896 readl(base + ODBL); /* flush */ 897 stex_mu_intr(hba, data); 898 spin_unlock_irqrestore(hba->host->host_lock, flags); 899 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET && 900 hba->cardtype == st_shasta)) 901 queue_work(hba->work_q, &hba->reset_work); 902 return IRQ_HANDLED; 903 } 904 905 spin_unlock_irqrestore(hba->host->host_lock, flags); 906 907 return IRQ_NONE; 908 } 909 910 static void stex_ss_mu_intr(struct st_hba *hba) 911 { 912 struct status_msg *resp; 913 struct st_ccb *ccb; 914 __le32 *scratch; 915 unsigned int size; 916 int count = 0; 917 u32 value; 918 u16 tag; 919 920 if (unlikely(hba->out_req_cnt <= 0 || 921 hba->mu_status == MU_STATE_RESETTING)) 922 return; 923 924 while (count < hba->sts_count) { 925 scratch = hba->scratch + hba->status_tail; 926 value = le32_to_cpu(*scratch); 927 if (unlikely(!(value & SS_STS_NORMAL))) 928 return; 929 930 resp = hba->status_buffer + hba->status_tail; 931 *scratch = 0; 932 ++count; 933 ++hba->status_tail; 934 hba->status_tail %= hba->sts_count+1; 935 936 tag = (u16)value; 937 if (unlikely(tag >= hba->host->can_queue)) { 938 printk(KERN_WARNING DRV_NAME 939 "(%s): invalid tag\n", pci_name(hba->pdev)); 940 continue; 941 } 942 943 hba->out_req_cnt--; 944 ccb = &hba->ccb[tag]; 945 if (unlikely(hba->wait_ccb == ccb)) 946 hba->wait_ccb = NULL; 947 if (unlikely(ccb->req == NULL)) { 948 printk(KERN_WARNING DRV_NAME 949 "(%s): lagging req\n", pci_name(hba->pdev)); 950 continue; 951 } 952 953 ccb->req = NULL; 954 if (likely(value & SS_STS_DONE)) { /* normal case */ 955 ccb->srb_status = SRB_STATUS_SUCCESS; 956 ccb->scsi_status = SAM_STAT_GOOD; 957 } else { 958 ccb->srb_status = resp->srb_status; 959 ccb->scsi_status = resp->scsi_status; 960 size = resp->payload_sz * sizeof(u32); 961 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || 962 size > sizeof(*resp))) { 963 printk(KERN_WARNING DRV_NAME 964 "(%s): bad status size\n", 965 pci_name(hba->pdev)); 966 } else { 967 size -= sizeof(*resp) - STATUS_VAR_LEN; 968 if (size) 969 stex_copy_data(ccb, resp, size); 970 } 971 if (likely(ccb->cmd != NULL)) 972 stex_check_cmd(hba, ccb, resp); 973 } 974 975 if (likely(ccb->cmd != NULL)) { 976 scsi_dma_unmap(ccb->cmd); 977 stex_scsi_done(ccb); 978 } else 979 ccb->req_type = 0; 980 } 981 } 982 983 static irqreturn_t stex_ss_intr(int irq, void *__hba) 984 { 985 struct st_hba *hba = __hba; 986 void __iomem *base = hba->mmio_base; 987 u32 data; 988 unsigned long flags; 989 990 spin_lock_irqsave(hba->host->host_lock, flags); 991 992 if (hba->cardtype == st_yel) { 993 data = readl(base + YI2H_INT); 994 if (data && data != 0xffffffff) { 995 /* clear the interrupt */ 996 writel(data, base + YI2H_INT_C); 997 stex_ss_mu_intr(hba); 998 spin_unlock_irqrestore(hba->host->host_lock, flags); 999 if (unlikely(data & SS_I2H_REQUEST_RESET)) 1000 queue_work(hba->work_q, &hba->reset_work); 1001 return IRQ_HANDLED; 1002 } 1003 } else { 1004 data = readl(base + PSCRATCH4); 1005 if (data != 0xffffffff) { 1006 if (data != 0) { 1007 /* clear the interrupt */ 1008 writel(data, base + PSCRATCH1); 1009 writel((1 << 22), base + YH2I_INT); 1010 } 1011 stex_ss_mu_intr(hba); 1012 spin_unlock_irqrestore(hba->host->host_lock, flags); 1013 if (unlikely(data & SS_I2H_REQUEST_RESET)) 1014 queue_work(hba->work_q, &hba->reset_work); 1015 return IRQ_HANDLED; 1016 } 1017 } 1018 1019 spin_unlock_irqrestore(hba->host->host_lock, flags); 1020 1021 return IRQ_NONE; 1022 } 1023 1024 static int stex_common_handshake(struct st_hba *hba) 1025 { 1026 void __iomem *base = hba->mmio_base; 1027 struct handshake_frame *h; 1028 dma_addr_t status_phys; 1029 u32 data; 1030 unsigned long before; 1031 1032 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 1033 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 1034 readl(base + IDBL); 1035 before = jiffies; 1036 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 1037 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1038 printk(KERN_ERR DRV_NAME 1039 "(%s): no handshake signature\n", 1040 pci_name(hba->pdev)); 1041 return -1; 1042 } 1043 rmb(); 1044 msleep(1); 1045 } 1046 } 1047 1048 udelay(10); 1049 1050 data = readl(base + OMR1); 1051 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) { 1052 data &= 0x0000ffff; 1053 if (hba->host->can_queue > data) { 1054 hba->host->can_queue = data; 1055 hba->host->cmd_per_lun = data; 1056 } 1057 } 1058 1059 h = (struct handshake_frame *)hba->status_buffer; 1060 h->rb_phy = cpu_to_le64(hba->dma_handle); 1061 h->req_sz = cpu_to_le16(hba->rq_size); 1062 h->req_cnt = cpu_to_le16(hba->rq_count+1); 1063 h->status_sz = cpu_to_le16(sizeof(struct status_msg)); 1064 h->status_cnt = cpu_to_le16(hba->sts_count+1); 1065 h->hosttime = cpu_to_le64(ktime_get_real_seconds()); 1066 h->partner_type = HMU_PARTNER_TYPE; 1067 if (hba->extra_offset) { 1068 h->extra_offset = cpu_to_le32(hba->extra_offset); 1069 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset); 1070 } else 1071 h->extra_offset = h->extra_size = 0; 1072 1073 status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size; 1074 writel(status_phys, base + IMR0); 1075 readl(base + IMR0); 1076 writel((status_phys >> 16) >> 16, base + IMR1); 1077 readl(base + IMR1); 1078 1079 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */ 1080 readl(base + OMR0); 1081 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 1082 readl(base + IDBL); /* flush */ 1083 1084 udelay(10); 1085 before = jiffies; 1086 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 1087 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1088 printk(KERN_ERR DRV_NAME 1089 "(%s): no signature after handshake frame\n", 1090 pci_name(hba->pdev)); 1091 return -1; 1092 } 1093 rmb(); 1094 msleep(1); 1095 } 1096 1097 writel(0, base + IMR0); 1098 readl(base + IMR0); 1099 writel(0, base + OMR0); 1100 readl(base + OMR0); 1101 writel(0, base + IMR1); 1102 readl(base + IMR1); 1103 writel(0, base + OMR1); 1104 readl(base + OMR1); /* flush */ 1105 return 0; 1106 } 1107 1108 static int stex_ss_handshake(struct st_hba *hba) 1109 { 1110 void __iomem *base = hba->mmio_base; 1111 struct st_msg_header *msg_h; 1112 struct handshake_frame *h; 1113 __le32 *scratch; 1114 u32 data, scratch_size, mailboxdata, operationaldata; 1115 unsigned long before; 1116 int ret = 0; 1117 1118 before = jiffies; 1119 1120 if (hba->cardtype == st_yel) { 1121 operationaldata = readl(base + YIOA_STATUS); 1122 while (operationaldata != SS_MU_OPERATIONAL) { 1123 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1124 printk(KERN_ERR DRV_NAME 1125 "(%s): firmware not operational\n", 1126 pci_name(hba->pdev)); 1127 return -1; 1128 } 1129 msleep(1); 1130 operationaldata = readl(base + YIOA_STATUS); 1131 } 1132 } else { 1133 operationaldata = readl(base + PSCRATCH3); 1134 while (operationaldata != SS_MU_OPERATIONAL) { 1135 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1136 printk(KERN_ERR DRV_NAME 1137 "(%s): firmware not operational\n", 1138 pci_name(hba->pdev)); 1139 return -1; 1140 } 1141 msleep(1); 1142 operationaldata = readl(base + PSCRATCH3); 1143 } 1144 } 1145 1146 msg_h = (struct st_msg_header *)hba->dma_mem; 1147 msg_h->handle = cpu_to_le64(hba->dma_handle); 1148 msg_h->flag = SS_HEAD_HANDSHAKE; 1149 1150 h = (struct handshake_frame *)(msg_h + 1); 1151 h->rb_phy = cpu_to_le64(hba->dma_handle); 1152 h->req_sz = cpu_to_le16(hba->rq_size); 1153 h->req_cnt = cpu_to_le16(hba->rq_count+1); 1154 h->status_sz = cpu_to_le16(sizeof(struct status_msg)); 1155 h->status_cnt = cpu_to_le16(hba->sts_count+1); 1156 h->hosttime = cpu_to_le64(ktime_get_real_seconds()); 1157 h->partner_type = HMU_PARTNER_TYPE; 1158 h->extra_offset = h->extra_size = 0; 1159 scratch_size = (hba->sts_count+1)*sizeof(u32); 1160 h->scratch_size = cpu_to_le32(scratch_size); 1161 1162 if (hba->cardtype == st_yel) { 1163 data = readl(base + YINT_EN); 1164 data &= ~4; 1165 writel(data, base + YINT_EN); 1166 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI); 1167 readl(base + YH2I_REQ_HI); 1168 writel(hba->dma_handle, base + YH2I_REQ); 1169 readl(base + YH2I_REQ); /* flush */ 1170 } else { 1171 data = readl(base + YINT_EN); 1172 data &= ~(1 << 0); 1173 data &= ~(1 << 2); 1174 writel(data, base + YINT_EN); 1175 if (hba->msi_lock == 0) { 1176 /* P3 MSI Register cannot access twice */ 1177 writel((1 << 6), base + YH2I_INT); 1178 hba->msi_lock = 1; 1179 } 1180 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI); 1181 writel(hba->dma_handle, base + YH2I_REQ); 1182 } 1183 1184 before = jiffies; 1185 scratch = hba->scratch; 1186 if (hba->cardtype == st_yel) { 1187 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) { 1188 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1189 printk(KERN_ERR DRV_NAME 1190 "(%s): no signature after handshake frame\n", 1191 pci_name(hba->pdev)); 1192 ret = -1; 1193 break; 1194 } 1195 rmb(); 1196 msleep(1); 1197 } 1198 } else { 1199 mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS); 1200 while (mailboxdata != SS_STS_HANDSHAKE) { 1201 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1202 printk(KERN_ERR DRV_NAME 1203 "(%s): no signature after handshake frame\n", 1204 pci_name(hba->pdev)); 1205 ret = -1; 1206 break; 1207 } 1208 rmb(); 1209 msleep(1); 1210 mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS); 1211 } 1212 } 1213 memset(scratch, 0, scratch_size); 1214 msg_h->flag = 0; 1215 1216 return ret; 1217 } 1218 1219 static int stex_handshake(struct st_hba *hba) 1220 { 1221 int err; 1222 unsigned long flags; 1223 unsigned int mu_status; 1224 1225 if (hba->cardtype == st_yel || hba->cardtype == st_P3) 1226 err = stex_ss_handshake(hba); 1227 else 1228 err = stex_common_handshake(hba); 1229 spin_lock_irqsave(hba->host->host_lock, flags); 1230 mu_status = hba->mu_status; 1231 if (err == 0) { 1232 hba->req_head = 0; 1233 hba->req_tail = 0; 1234 hba->status_head = 0; 1235 hba->status_tail = 0; 1236 hba->out_req_cnt = 0; 1237 hba->mu_status = MU_STATE_STARTED; 1238 } else 1239 hba->mu_status = MU_STATE_FAILED; 1240 if (mu_status == MU_STATE_RESETTING) 1241 wake_up_all(&hba->reset_waitq); 1242 spin_unlock_irqrestore(hba->host->host_lock, flags); 1243 return err; 1244 } 1245 1246 static int stex_abort(struct scsi_cmnd *cmd) 1247 { 1248 struct Scsi_Host *host = cmd->device->host; 1249 struct st_hba *hba = (struct st_hba *)host->hostdata; 1250 u16 tag = cmd->request->tag; 1251 void __iomem *base; 1252 u32 data; 1253 int result = SUCCESS; 1254 unsigned long flags; 1255 1256 scmd_printk(KERN_INFO, cmd, "aborting command\n"); 1257 1258 base = hba->mmio_base; 1259 spin_lock_irqsave(host->host_lock, flags); 1260 if (tag < host->can_queue && 1261 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd) 1262 hba->wait_ccb = &hba->ccb[tag]; 1263 else 1264 goto out; 1265 1266 if (hba->cardtype == st_yel) { 1267 data = readl(base + YI2H_INT); 1268 if (data == 0 || data == 0xffffffff) 1269 goto fail_out; 1270 1271 writel(data, base + YI2H_INT_C); 1272 stex_ss_mu_intr(hba); 1273 } else if (hba->cardtype == st_P3) { 1274 data = readl(base + PSCRATCH4); 1275 if (data == 0xffffffff) 1276 goto fail_out; 1277 if (data != 0) { 1278 writel(data, base + PSCRATCH1); 1279 writel((1 << 22), base + YH2I_INT); 1280 } 1281 stex_ss_mu_intr(hba); 1282 } else { 1283 data = readl(base + ODBL); 1284 if (data == 0 || data == 0xffffffff) 1285 goto fail_out; 1286 1287 writel(data, base + ODBL); 1288 readl(base + ODBL); /* flush */ 1289 stex_mu_intr(hba, data); 1290 } 1291 if (hba->wait_ccb == NULL) { 1292 printk(KERN_WARNING DRV_NAME 1293 "(%s): lost interrupt\n", pci_name(hba->pdev)); 1294 goto out; 1295 } 1296 1297 fail_out: 1298 scsi_dma_unmap(cmd); 1299 hba->wait_ccb->req = NULL; /* nullify the req's future return */ 1300 hba->wait_ccb = NULL; 1301 result = FAILED; 1302 out: 1303 spin_unlock_irqrestore(host->host_lock, flags); 1304 return result; 1305 } 1306 1307 static void stex_hard_reset(struct st_hba *hba) 1308 { 1309 struct pci_bus *bus; 1310 int i; 1311 u16 pci_cmd; 1312 u8 pci_bctl; 1313 1314 for (i = 0; i < 16; i++) 1315 pci_read_config_dword(hba->pdev, i * 4, 1316 &hba->pdev->saved_config_space[i]); 1317 1318 /* Reset secondary bus. Our controller(MU/ATU) is the only device on 1319 secondary bus. Consult Intel 80331/3 developer's manual for detail */ 1320 bus = hba->pdev->bus; 1321 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); 1322 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; 1323 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1324 1325 /* 1326 * 1 ms may be enough for 8-port controllers. But 16-port controllers 1327 * require more time to finish bus reset. Use 100 ms here for safety 1328 */ 1329 msleep(100); 1330 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; 1331 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1332 1333 for (i = 0; i < MU_HARD_RESET_WAIT; i++) { 1334 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd); 1335 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER)) 1336 break; 1337 msleep(1); 1338 } 1339 1340 ssleep(5); 1341 for (i = 0; i < 16; i++) 1342 pci_write_config_dword(hba->pdev, i * 4, 1343 hba->pdev->saved_config_space[i]); 1344 } 1345 1346 static int stex_yos_reset(struct st_hba *hba) 1347 { 1348 void __iomem *base; 1349 unsigned long flags, before; 1350 int ret = 0; 1351 1352 base = hba->mmio_base; 1353 writel(MU_INBOUND_DOORBELL_RESET, base + IDBL); 1354 readl(base + IDBL); /* flush */ 1355 before = jiffies; 1356 while (hba->out_req_cnt > 0) { 1357 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { 1358 printk(KERN_WARNING DRV_NAME 1359 "(%s): reset timeout\n", pci_name(hba->pdev)); 1360 ret = -1; 1361 break; 1362 } 1363 msleep(1); 1364 } 1365 1366 spin_lock_irqsave(hba->host->host_lock, flags); 1367 if (ret == -1) 1368 hba->mu_status = MU_STATE_FAILED; 1369 else 1370 hba->mu_status = MU_STATE_STARTED; 1371 wake_up_all(&hba->reset_waitq); 1372 spin_unlock_irqrestore(hba->host->host_lock, flags); 1373 1374 return ret; 1375 } 1376 1377 static void stex_ss_reset(struct st_hba *hba) 1378 { 1379 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT); 1380 readl(hba->mmio_base + YH2I_INT); 1381 ssleep(5); 1382 } 1383 1384 static void stex_p3_reset(struct st_hba *hba) 1385 { 1386 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT); 1387 ssleep(5); 1388 } 1389 1390 static int stex_do_reset(struct st_hba *hba) 1391 { 1392 unsigned long flags; 1393 unsigned int mu_status = MU_STATE_RESETTING; 1394 1395 spin_lock_irqsave(hba->host->host_lock, flags); 1396 if (hba->mu_status == MU_STATE_STARTING) { 1397 spin_unlock_irqrestore(hba->host->host_lock, flags); 1398 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n", 1399 pci_name(hba->pdev)); 1400 return 0; 1401 } 1402 while (hba->mu_status == MU_STATE_RESETTING) { 1403 spin_unlock_irqrestore(hba->host->host_lock, flags); 1404 wait_event_timeout(hba->reset_waitq, 1405 hba->mu_status != MU_STATE_RESETTING, 1406 MU_MAX_DELAY * HZ); 1407 spin_lock_irqsave(hba->host->host_lock, flags); 1408 mu_status = hba->mu_status; 1409 } 1410 1411 if (mu_status != MU_STATE_RESETTING) { 1412 spin_unlock_irqrestore(hba->host->host_lock, flags); 1413 return (mu_status == MU_STATE_STARTED) ? 0 : -1; 1414 } 1415 1416 hba->mu_status = MU_STATE_RESETTING; 1417 spin_unlock_irqrestore(hba->host->host_lock, flags); 1418 1419 if (hba->cardtype == st_yosemite) 1420 return stex_yos_reset(hba); 1421 1422 if (hba->cardtype == st_shasta) 1423 stex_hard_reset(hba); 1424 else if (hba->cardtype == st_yel) 1425 stex_ss_reset(hba); 1426 else if (hba->cardtype == st_P3) 1427 stex_p3_reset(hba); 1428 1429 return_abnormal_state(hba, DID_RESET); 1430 1431 if (stex_handshake(hba) == 0) 1432 return 0; 1433 1434 printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n", 1435 pci_name(hba->pdev)); 1436 return -1; 1437 } 1438 1439 static int stex_reset(struct scsi_cmnd *cmd) 1440 { 1441 struct st_hba *hba; 1442 1443 hba = (struct st_hba *) &cmd->device->host->hostdata[0]; 1444 1445 shost_printk(KERN_INFO, cmd->device->host, 1446 "resetting host\n"); 1447 1448 return stex_do_reset(hba) ? FAILED : SUCCESS; 1449 } 1450 1451 static void stex_reset_work(struct work_struct *work) 1452 { 1453 struct st_hba *hba = container_of(work, struct st_hba, reset_work); 1454 1455 stex_do_reset(hba); 1456 } 1457 1458 static int stex_biosparam(struct scsi_device *sdev, 1459 struct block_device *bdev, sector_t capacity, int geom[]) 1460 { 1461 int heads = 255, sectors = 63; 1462 1463 if (capacity < 0x200000) { 1464 heads = 64; 1465 sectors = 32; 1466 } 1467 1468 sector_div(capacity, heads * sectors); 1469 1470 geom[0] = heads; 1471 geom[1] = sectors; 1472 geom[2] = capacity; 1473 1474 return 0; 1475 } 1476 1477 static struct scsi_host_template driver_template = { 1478 .module = THIS_MODULE, 1479 .name = DRV_NAME, 1480 .proc_name = DRV_NAME, 1481 .bios_param = stex_biosparam, 1482 .queuecommand = stex_queuecommand, 1483 .slave_configure = stex_slave_config, 1484 .eh_abort_handler = stex_abort, 1485 .eh_host_reset_handler = stex_reset, 1486 .this_id = -1, 1487 .dma_boundary = PAGE_SIZE - 1, 1488 }; 1489 1490 static struct pci_device_id stex_pci_tbl[] = { 1491 /* st_shasta */ 1492 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1493 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */ 1494 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1495 st_shasta }, /* SuperTrak EX12350 */ 1496 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1497 st_shasta }, /* SuperTrak EX4350 */ 1498 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1499 st_shasta }, /* SuperTrak EX24350 */ 1500 1501 /* st_vsc */ 1502 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc }, 1503 1504 /* st_yosemite */ 1505 { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite }, 1506 1507 /* st_seq */ 1508 { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq }, 1509 1510 /* st_yel */ 1511 { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel }, 1512 { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel }, 1513 1514 /* st_P3, pluto */ 1515 { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE, 1516 0x8870, 0, 0, st_P3 }, 1517 /* st_P3, p3 */ 1518 { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE, 1519 0x4300, 0, 0, st_P3 }, 1520 1521 /* st_P3, SymplyStor4E */ 1522 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE, 1523 0x4311, 0, 0, st_P3 }, 1524 /* st_P3, SymplyStor8E */ 1525 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE, 1526 0x4312, 0, 0, st_P3 }, 1527 /* st_P3, SymplyStor4 */ 1528 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE, 1529 0x4321, 0, 0, st_P3 }, 1530 /* st_P3, SymplyStor8 */ 1531 { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE, 1532 0x4322, 0, 0, st_P3 }, 1533 { } /* terminate list */ 1534 }; 1535 1536 static struct st_card_info stex_card_info[] = { 1537 /* st_shasta */ 1538 { 1539 .max_id = 17, 1540 .max_lun = 8, 1541 .max_channel = 0, 1542 .rq_count = 32, 1543 .rq_size = 1048, 1544 .sts_count = 32, 1545 .alloc_rq = stex_alloc_req, 1546 .map_sg = stex_map_sg, 1547 .send = stex_send_cmd, 1548 }, 1549 1550 /* st_vsc */ 1551 { 1552 .max_id = 129, 1553 .max_lun = 1, 1554 .max_channel = 0, 1555 .rq_count = 32, 1556 .rq_size = 1048, 1557 .sts_count = 32, 1558 .alloc_rq = stex_alloc_req, 1559 .map_sg = stex_map_sg, 1560 .send = stex_send_cmd, 1561 }, 1562 1563 /* st_yosemite */ 1564 { 1565 .max_id = 2, 1566 .max_lun = 256, 1567 .max_channel = 0, 1568 .rq_count = 256, 1569 .rq_size = 1048, 1570 .sts_count = 256, 1571 .alloc_rq = stex_alloc_req, 1572 .map_sg = stex_map_sg, 1573 .send = stex_send_cmd, 1574 }, 1575 1576 /* st_seq */ 1577 { 1578 .max_id = 129, 1579 .max_lun = 1, 1580 .max_channel = 0, 1581 .rq_count = 32, 1582 .rq_size = 1048, 1583 .sts_count = 32, 1584 .alloc_rq = stex_alloc_req, 1585 .map_sg = stex_map_sg, 1586 .send = stex_send_cmd, 1587 }, 1588 1589 /* st_yel */ 1590 { 1591 .max_id = 129, 1592 .max_lun = 256, 1593 .max_channel = 3, 1594 .rq_count = 801, 1595 .rq_size = 512, 1596 .sts_count = 801, 1597 .alloc_rq = stex_ss_alloc_req, 1598 .map_sg = stex_ss_map_sg, 1599 .send = stex_ss_send_cmd, 1600 }, 1601 1602 /* st_P3 */ 1603 { 1604 .max_id = 129, 1605 .max_lun = 256, 1606 .max_channel = 0, 1607 .rq_count = 801, 1608 .rq_size = 512, 1609 .sts_count = 801, 1610 .alloc_rq = stex_ss_alloc_req, 1611 .map_sg = stex_ss_map_sg, 1612 .send = stex_ss_send_cmd, 1613 }, 1614 }; 1615 1616 static int stex_request_irq(struct st_hba *hba) 1617 { 1618 struct pci_dev *pdev = hba->pdev; 1619 int status; 1620 1621 if (msi || hba->cardtype == st_P3) { 1622 status = pci_enable_msi(pdev); 1623 if (status != 0) 1624 printk(KERN_ERR DRV_NAME 1625 "(%s): error %d setting up MSI\n", 1626 pci_name(pdev), status); 1627 else 1628 hba->msi_enabled = 1; 1629 } else 1630 hba->msi_enabled = 0; 1631 1632 status = request_irq(pdev->irq, 1633 (hba->cardtype == st_yel || hba->cardtype == st_P3) ? 1634 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba); 1635 1636 if (status != 0) { 1637 if (hba->msi_enabled) 1638 pci_disable_msi(pdev); 1639 } 1640 return status; 1641 } 1642 1643 static void stex_free_irq(struct st_hba *hba) 1644 { 1645 struct pci_dev *pdev = hba->pdev; 1646 1647 free_irq(pdev->irq, hba); 1648 if (hba->msi_enabled) 1649 pci_disable_msi(pdev); 1650 } 1651 1652 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1653 { 1654 struct st_hba *hba; 1655 struct Scsi_Host *host; 1656 const struct st_card_info *ci = NULL; 1657 u32 sts_offset, cp_offset, scratch_offset; 1658 int err; 1659 1660 err = pci_enable_device(pdev); 1661 if (err) 1662 return err; 1663 1664 pci_set_master(pdev); 1665 1666 S6flag = 0; 1667 register_reboot_notifier(&stex_notifier); 1668 1669 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba)); 1670 1671 if (!host) { 1672 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n", 1673 pci_name(pdev)); 1674 err = -ENOMEM; 1675 goto out_disable; 1676 } 1677 1678 hba = (struct st_hba *)host->hostdata; 1679 memset(hba, 0, sizeof(struct st_hba)); 1680 1681 err = pci_request_regions(pdev, DRV_NAME); 1682 if (err < 0) { 1683 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n", 1684 pci_name(pdev)); 1685 goto out_scsi_host_put; 1686 } 1687 1688 hba->mmio_base = pci_ioremap_bar(pdev, 0); 1689 if ( !hba->mmio_base) { 1690 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n", 1691 pci_name(pdev)); 1692 err = -ENOMEM; 1693 goto out_release_regions; 1694 } 1695 1696 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1697 if (err) 1698 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1699 if (err) { 1700 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n", 1701 pci_name(pdev)); 1702 goto out_iounmap; 1703 } 1704 1705 hba->cardtype = (unsigned int) id->driver_data; 1706 ci = &stex_card_info[hba->cardtype]; 1707 switch (id->subdevice) { 1708 case 0x4221: 1709 case 0x4222: 1710 case 0x4223: 1711 case 0x4224: 1712 case 0x4225: 1713 case 0x4226: 1714 case 0x4227: 1715 case 0x4261: 1716 case 0x4262: 1717 case 0x4263: 1718 case 0x4264: 1719 case 0x4265: 1720 break; 1721 default: 1722 if (hba->cardtype == st_yel || hba->cardtype == st_P3) 1723 hba->supports_pm = 1; 1724 } 1725 1726 sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size; 1727 if (hba->cardtype == st_yel || hba->cardtype == st_P3) 1728 sts_offset += (ci->sts_count+1) * sizeof(u32); 1729 cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg); 1730 hba->dma_size = cp_offset + sizeof(struct st_frame); 1731 if (hba->cardtype == st_seq || 1732 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) { 1733 hba->extra_offset = hba->dma_size; 1734 hba->dma_size += ST_ADDITIONAL_MEM; 1735 } 1736 hba->dma_mem = dma_alloc_coherent(&pdev->dev, 1737 hba->dma_size, &hba->dma_handle, GFP_KERNEL); 1738 if (!hba->dma_mem) { 1739 /* Retry minimum coherent mapping for st_seq and st_vsc */ 1740 if (hba->cardtype == st_seq || 1741 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) { 1742 printk(KERN_WARNING DRV_NAME 1743 "(%s): allocating min buffer for controller\n", 1744 pci_name(pdev)); 1745 hba->dma_size = hba->extra_offset 1746 + ST_ADDITIONAL_MEM_MIN; 1747 hba->dma_mem = dma_alloc_coherent(&pdev->dev, 1748 hba->dma_size, &hba->dma_handle, GFP_KERNEL); 1749 } 1750 1751 if (!hba->dma_mem) { 1752 err = -ENOMEM; 1753 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n", 1754 pci_name(pdev)); 1755 goto out_iounmap; 1756 } 1757 } 1758 1759 hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL); 1760 if (!hba->ccb) { 1761 err = -ENOMEM; 1762 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n", 1763 pci_name(pdev)); 1764 goto out_pci_free; 1765 } 1766 1767 if (hba->cardtype == st_yel || hba->cardtype == st_P3) 1768 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset); 1769 hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset); 1770 hba->copy_buffer = hba->dma_mem + cp_offset; 1771 hba->rq_count = ci->rq_count; 1772 hba->rq_size = ci->rq_size; 1773 hba->sts_count = ci->sts_count; 1774 hba->alloc_rq = ci->alloc_rq; 1775 hba->map_sg = ci->map_sg; 1776 hba->send = ci->send; 1777 hba->mu_status = MU_STATE_STARTING; 1778 hba->msi_lock = 0; 1779 1780 if (hba->cardtype == st_yel || hba->cardtype == st_P3) 1781 host->sg_tablesize = 38; 1782 else 1783 host->sg_tablesize = 32; 1784 host->can_queue = ci->rq_count; 1785 host->cmd_per_lun = ci->rq_count; 1786 host->max_id = ci->max_id; 1787 host->max_lun = ci->max_lun; 1788 host->max_channel = ci->max_channel; 1789 host->unique_id = host->host_no; 1790 host->max_cmd_len = STEX_CDB_LENGTH; 1791 1792 hba->host = host; 1793 hba->pdev = pdev; 1794 init_waitqueue_head(&hba->reset_waitq); 1795 1796 snprintf(hba->work_q_name, sizeof(hba->work_q_name), 1797 "stex_wq_%d", host->host_no); 1798 hba->work_q = create_singlethread_workqueue(hba->work_q_name); 1799 if (!hba->work_q) { 1800 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n", 1801 pci_name(pdev)); 1802 err = -ENOMEM; 1803 goto out_ccb_free; 1804 } 1805 INIT_WORK(&hba->reset_work, stex_reset_work); 1806 1807 err = stex_request_irq(hba); 1808 if (err) { 1809 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n", 1810 pci_name(pdev)); 1811 goto out_free_wq; 1812 } 1813 1814 err = stex_handshake(hba); 1815 if (err) 1816 goto out_free_irq; 1817 1818 pci_set_drvdata(pdev, hba); 1819 1820 err = scsi_add_host(host, &pdev->dev); 1821 if (err) { 1822 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n", 1823 pci_name(pdev)); 1824 goto out_free_irq; 1825 } 1826 1827 scsi_scan_host(host); 1828 1829 return 0; 1830 1831 out_free_irq: 1832 stex_free_irq(hba); 1833 out_free_wq: 1834 destroy_workqueue(hba->work_q); 1835 out_ccb_free: 1836 kfree(hba->ccb); 1837 out_pci_free: 1838 dma_free_coherent(&pdev->dev, hba->dma_size, 1839 hba->dma_mem, hba->dma_handle); 1840 out_iounmap: 1841 iounmap(hba->mmio_base); 1842 out_release_regions: 1843 pci_release_regions(pdev); 1844 out_scsi_host_put: 1845 scsi_host_put(host); 1846 out_disable: 1847 pci_disable_device(pdev); 1848 1849 return err; 1850 } 1851 1852 static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic) 1853 { 1854 struct req_msg *req; 1855 struct st_msg_header *msg_h; 1856 unsigned long flags; 1857 unsigned long before; 1858 u16 tag = 0; 1859 1860 spin_lock_irqsave(hba->host->host_lock, flags); 1861 1862 if ((hba->cardtype == st_yel || hba->cardtype == st_P3) && 1863 hba->supports_pm == 1) { 1864 if (st_sleep_mic == ST_NOTHANDLED) { 1865 spin_unlock_irqrestore(hba->host->host_lock, flags); 1866 return; 1867 } 1868 } 1869 req = hba->alloc_rq(hba); 1870 if (hba->cardtype == st_yel || hba->cardtype == st_P3) { 1871 msg_h = (struct st_msg_header *)req - 1; 1872 memset(msg_h, 0, hba->rq_size); 1873 } else 1874 memset(req, 0, hba->rq_size); 1875 1876 if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel 1877 || hba->cardtype == st_P3) 1878 && st_sleep_mic == ST_IGNORED) { 1879 req->cdb[0] = MGT_CMD; 1880 req->cdb[1] = MGT_CMD_SIGNATURE; 1881 req->cdb[2] = CTLR_CONFIG_CMD; 1882 req->cdb[3] = CTLR_SHUTDOWN; 1883 } else if ((hba->cardtype == st_yel || hba->cardtype == st_P3) 1884 && st_sleep_mic != ST_IGNORED) { 1885 req->cdb[0] = MGT_CMD; 1886 req->cdb[1] = MGT_CMD_SIGNATURE; 1887 req->cdb[2] = CTLR_CONFIG_CMD; 1888 req->cdb[3] = PMIC_SHUTDOWN; 1889 req->cdb[4] = st_sleep_mic; 1890 } else { 1891 req->cdb[0] = CONTROLLER_CMD; 1892 req->cdb[1] = CTLR_POWER_STATE_CHANGE; 1893 req->cdb[2] = CTLR_POWER_SAVING; 1894 } 1895 hba->ccb[tag].cmd = NULL; 1896 hba->ccb[tag].sg_count = 0; 1897 hba->ccb[tag].sense_bufflen = 0; 1898 hba->ccb[tag].sense_buffer = NULL; 1899 hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE; 1900 hba->send(hba, req, tag); 1901 spin_unlock_irqrestore(hba->host->host_lock, flags); 1902 before = jiffies; 1903 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) { 1904 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { 1905 hba->ccb[tag].req_type = 0; 1906 hba->mu_status = MU_STATE_STOP; 1907 return; 1908 } 1909 msleep(1); 1910 } 1911 hba->mu_status = MU_STATE_STOP; 1912 } 1913 1914 static void stex_hba_free(struct st_hba *hba) 1915 { 1916 stex_free_irq(hba); 1917 1918 destroy_workqueue(hba->work_q); 1919 1920 iounmap(hba->mmio_base); 1921 1922 pci_release_regions(hba->pdev); 1923 1924 kfree(hba->ccb); 1925 1926 dma_free_coherent(&hba->pdev->dev, hba->dma_size, 1927 hba->dma_mem, hba->dma_handle); 1928 } 1929 1930 static void stex_remove(struct pci_dev *pdev) 1931 { 1932 struct st_hba *hba = pci_get_drvdata(pdev); 1933 1934 hba->mu_status = MU_STATE_NOCONNECT; 1935 return_abnormal_state(hba, DID_NO_CONNECT); 1936 scsi_remove_host(hba->host); 1937 1938 scsi_block_requests(hba->host); 1939 1940 stex_hba_free(hba); 1941 1942 scsi_host_put(hba->host); 1943 1944 pci_disable_device(pdev); 1945 1946 unregister_reboot_notifier(&stex_notifier); 1947 } 1948 1949 static void stex_shutdown(struct pci_dev *pdev) 1950 { 1951 struct st_hba *hba = pci_get_drvdata(pdev); 1952 1953 if (hba->supports_pm == 0) { 1954 stex_hba_stop(hba, ST_IGNORED); 1955 } else if (hba->supports_pm == 1 && S6flag) { 1956 unregister_reboot_notifier(&stex_notifier); 1957 stex_hba_stop(hba, ST_S6); 1958 } else 1959 stex_hba_stop(hba, ST_S5); 1960 } 1961 1962 static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state) 1963 { 1964 switch (state.event) { 1965 case PM_EVENT_SUSPEND: 1966 return ST_S3; 1967 case PM_EVENT_HIBERNATE: 1968 hba->msi_lock = 0; 1969 return ST_S4; 1970 default: 1971 return ST_NOTHANDLED; 1972 } 1973 } 1974 1975 static int stex_suspend(struct pci_dev *pdev, pm_message_t state) 1976 { 1977 struct st_hba *hba = pci_get_drvdata(pdev); 1978 1979 if ((hba->cardtype == st_yel || hba->cardtype == st_P3) 1980 && hba->supports_pm == 1) 1981 stex_hba_stop(hba, stex_choice_sleep_mic(hba, state)); 1982 else 1983 stex_hba_stop(hba, ST_IGNORED); 1984 return 0; 1985 } 1986 1987 static int stex_resume(struct pci_dev *pdev) 1988 { 1989 struct st_hba *hba = pci_get_drvdata(pdev); 1990 1991 hba->mu_status = MU_STATE_STARTING; 1992 stex_handshake(hba); 1993 return 0; 1994 } 1995 1996 static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf) 1997 { 1998 S6flag = 1; 1999 return NOTIFY_OK; 2000 } 2001 MODULE_DEVICE_TABLE(pci, stex_pci_tbl); 2002 2003 static struct pci_driver stex_pci_driver = { 2004 .name = DRV_NAME, 2005 .id_table = stex_pci_tbl, 2006 .probe = stex_probe, 2007 .remove = stex_remove, 2008 .shutdown = stex_shutdown, 2009 .suspend = stex_suspend, 2010 .resume = stex_resume, 2011 }; 2012 2013 static int __init stex_init(void) 2014 { 2015 printk(KERN_INFO DRV_NAME 2016 ": Promise SuperTrak EX Driver version: %s\n", 2017 ST_DRIVER_VERSION); 2018 2019 return pci_register_driver(&stex_pci_driver); 2020 } 2021 2022 static void __exit stex_exit(void) 2023 { 2024 pci_unregister_driver(&stex_pci_driver); 2025 } 2026 2027 module_init(stex_init); 2028 module_exit(stex_exit); 2029