1 /* 2 * SuperTrak EX Series Storage Controller driver for Linux 3 * 4 * Copyright (C) 2005-2015 Promise Technology Inc. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 * Written By: 12 * Ed Lin <promise_linux@promise.com> 13 * 14 */ 15 16 #include <linux/init.h> 17 #include <linux/errno.h> 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/slab.h> 21 #include <linux/time.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/interrupt.h> 25 #include <linux/types.h> 26 #include <linux/module.h> 27 #include <linux/spinlock.h> 28 #include <linux/ktime.h> 29 #include <asm/io.h> 30 #include <asm/irq.h> 31 #include <asm/byteorder.h> 32 #include <scsi/scsi.h> 33 #include <scsi/scsi_device.h> 34 #include <scsi/scsi_cmnd.h> 35 #include <scsi/scsi_host.h> 36 #include <scsi/scsi_tcq.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_eh.h> 39 40 #define DRV_NAME "stex" 41 #define ST_DRIVER_VERSION "5.00.0000.01" 42 #define ST_VER_MAJOR 5 43 #define ST_VER_MINOR 00 44 #define ST_OEM 0000 45 #define ST_BUILD_VER 01 46 47 enum { 48 /* MU register offset */ 49 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */ 50 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */ 51 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */ 52 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */ 53 IDBL = 0x20, /* MU_INBOUND_DOORBELL */ 54 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */ 55 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */ 56 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */ 57 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */ 58 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */ 59 60 YIOA_STATUS = 0x00, 61 YH2I_INT = 0x20, 62 YINT_EN = 0x34, 63 YI2H_INT = 0x9c, 64 YI2H_INT_C = 0xa0, 65 YH2I_REQ = 0xc0, 66 YH2I_REQ_HI = 0xc4, 67 68 /* MU register value */ 69 MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0), 70 MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1), 71 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2), 72 MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3), 73 MU_INBOUND_DOORBELL_RESET = (1 << 4), 74 75 MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0), 76 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1), 77 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2), 78 MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3), 79 MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4), 80 MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27), 81 82 /* MU status code */ 83 MU_STATE_STARTING = 1, 84 MU_STATE_STARTED = 2, 85 MU_STATE_RESETTING = 3, 86 MU_STATE_FAILED = 4, 87 MU_STATE_STOP = 5, 88 MU_STATE_NOCONNECT = 6, 89 90 MU_MAX_DELAY = 120, 91 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55, 92 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000, 93 MU_HARD_RESET_WAIT = 30000, 94 HMU_PARTNER_TYPE = 2, 95 96 /* firmware returned values */ 97 SRB_STATUS_SUCCESS = 0x01, 98 SRB_STATUS_ERROR = 0x04, 99 SRB_STATUS_BUSY = 0x05, 100 SRB_STATUS_INVALID_REQUEST = 0x06, 101 SRB_STATUS_SELECTION_TIMEOUT = 0x0A, 102 SRB_SEE_SENSE = 0x80, 103 104 /* task attribute */ 105 TASK_ATTRIBUTE_SIMPLE = 0x0, 106 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, 107 TASK_ATTRIBUTE_ORDERED = 0x2, 108 TASK_ATTRIBUTE_ACA = 0x4, 109 110 SS_STS_NORMAL = 0x80000000, 111 SS_STS_DONE = 0x40000000, 112 SS_STS_HANDSHAKE = 0x20000000, 113 114 SS_HEAD_HANDSHAKE = 0x80, 115 116 SS_H2I_INT_RESET = 0x100, 117 118 SS_I2H_REQUEST_RESET = 0x2000, 119 120 SS_MU_OPERATIONAL = 0x80000000, 121 122 STEX_CDB_LENGTH = 16, 123 STATUS_VAR_LEN = 128, 124 125 /* sg flags */ 126 SG_CF_EOT = 0x80, /* end of table */ 127 SG_CF_64B = 0x40, /* 64 bit item */ 128 SG_CF_HOST = 0x20, /* sg in host memory */ 129 MSG_DATA_DIR_ND = 0, 130 MSG_DATA_DIR_IN = 1, 131 MSG_DATA_DIR_OUT = 2, 132 133 st_shasta = 0, 134 st_vsc = 1, 135 st_yosemite = 2, 136 st_seq = 3, 137 st_yel = 4, 138 139 PASSTHRU_REQ_TYPE = 0x00000001, 140 PASSTHRU_REQ_NO_WAKEUP = 0x00000100, 141 ST_INTERNAL_TIMEOUT = 180, 142 143 ST_TO_CMD = 0, 144 ST_FROM_CMD = 1, 145 146 /* vendor specific commands of Promise */ 147 MGT_CMD = 0xd8, 148 SINBAND_MGT_CMD = 0xd9, 149 ARRAY_CMD = 0xe0, 150 CONTROLLER_CMD = 0xe1, 151 DEBUGGING_CMD = 0xe2, 152 PASSTHRU_CMD = 0xe3, 153 154 PASSTHRU_GET_ADAPTER = 0x05, 155 PASSTHRU_GET_DRVVER = 0x10, 156 157 CTLR_CONFIG_CMD = 0x03, 158 CTLR_SHUTDOWN = 0x0d, 159 160 CTLR_POWER_STATE_CHANGE = 0x0e, 161 CTLR_POWER_SAVING = 0x01, 162 163 PASSTHRU_SIGNATURE = 0x4e415041, 164 MGT_CMD_SIGNATURE = 0xba, 165 166 INQUIRY_EVPD = 0x01, 167 168 ST_ADDITIONAL_MEM = 0x200000, 169 ST_ADDITIONAL_MEM_MIN = 0x80000, 170 PMIC_SHUTDOWN = 0x0D, 171 PMIC_REUMSE = 0x10, 172 ST_IGNORED = -1, 173 ST_NOTHANDLED = 7, 174 ST_S3 = 3, 175 ST_S4 = 4, 176 ST_S5 = 5, 177 ST_S6 = 6, 178 }; 179 180 struct st_sgitem { 181 u8 ctrl; /* SG_CF_xxx */ 182 u8 reserved[3]; 183 __le32 count; 184 __le64 addr; 185 }; 186 187 struct st_ss_sgitem { 188 __le32 addr; 189 __le32 addr_hi; 190 __le32 count; 191 }; 192 193 struct st_sgtable { 194 __le16 sg_count; 195 __le16 max_sg_count; 196 __le32 sz_in_byte; 197 }; 198 199 struct st_msg_header { 200 __le64 handle; 201 u8 flag; 202 u8 channel; 203 __le16 timeout; 204 u32 reserved; 205 }; 206 207 struct handshake_frame { 208 __le64 rb_phy; /* request payload queue physical address */ 209 __le16 req_sz; /* size of each request payload */ 210 __le16 req_cnt; /* count of reqs the buffer can hold */ 211 __le16 status_sz; /* size of each status payload */ 212 __le16 status_cnt; /* count of status the buffer can hold */ 213 __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */ 214 u8 partner_type; /* who sends this frame */ 215 u8 reserved0[7]; 216 __le32 partner_ver_major; 217 __le32 partner_ver_minor; 218 __le32 partner_ver_oem; 219 __le32 partner_ver_build; 220 __le32 extra_offset; /* NEW */ 221 __le32 extra_size; /* NEW */ 222 __le32 scratch_size; 223 u32 reserved1; 224 }; 225 226 struct req_msg { 227 __le16 tag; 228 u8 lun; 229 u8 target; 230 u8 task_attr; 231 u8 task_manage; 232 u8 data_dir; 233 u8 payload_sz; /* payload size in 4-byte, not used */ 234 u8 cdb[STEX_CDB_LENGTH]; 235 u32 variable[0]; 236 }; 237 238 struct status_msg { 239 __le16 tag; 240 u8 lun; 241 u8 target; 242 u8 srb_status; 243 u8 scsi_status; 244 u8 reserved; 245 u8 payload_sz; /* payload size in 4-byte */ 246 u8 variable[STATUS_VAR_LEN]; 247 }; 248 249 struct ver_info { 250 u32 major; 251 u32 minor; 252 u32 oem; 253 u32 build; 254 u32 reserved[2]; 255 }; 256 257 struct st_frame { 258 u32 base[6]; 259 u32 rom_addr; 260 261 struct ver_info drv_ver; 262 struct ver_info bios_ver; 263 264 u32 bus; 265 u32 slot; 266 u32 irq_level; 267 u32 irq_vec; 268 u32 id; 269 u32 subid; 270 271 u32 dimm_size; 272 u8 dimm_type; 273 u8 reserved[3]; 274 275 u32 channel; 276 u32 reserved1; 277 }; 278 279 struct st_drvver { 280 u32 major; 281 u32 minor; 282 u32 oem; 283 u32 build; 284 u32 signature[2]; 285 u8 console_id; 286 u8 host_no; 287 u8 reserved0[2]; 288 u32 reserved[3]; 289 }; 290 291 struct st_ccb { 292 struct req_msg *req; 293 struct scsi_cmnd *cmd; 294 295 void *sense_buffer; 296 unsigned int sense_bufflen; 297 int sg_count; 298 299 u32 req_type; 300 u8 srb_status; 301 u8 scsi_status; 302 u8 reserved[2]; 303 }; 304 305 struct st_hba { 306 void __iomem *mmio_base; /* iomapped PCI memory space */ 307 void *dma_mem; 308 dma_addr_t dma_handle; 309 size_t dma_size; 310 311 struct Scsi_Host *host; 312 struct pci_dev *pdev; 313 314 struct req_msg * (*alloc_rq) (struct st_hba *); 315 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *); 316 void (*send) (struct st_hba *, struct req_msg *, u16); 317 318 u32 req_head; 319 u32 req_tail; 320 u32 status_head; 321 u32 status_tail; 322 323 struct status_msg *status_buffer; 324 void *copy_buffer; /* temp buffer for driver-handled commands */ 325 struct st_ccb *ccb; 326 struct st_ccb *wait_ccb; 327 __le32 *scratch; 328 329 char work_q_name[20]; 330 struct workqueue_struct *work_q; 331 struct work_struct reset_work; 332 wait_queue_head_t reset_waitq; 333 unsigned int mu_status; 334 unsigned int cardtype; 335 int msi_enabled; 336 int out_req_cnt; 337 u32 extra_offset; 338 u16 rq_count; 339 u16 rq_size; 340 u16 sts_count; 341 u8 supports_pm; 342 }; 343 344 struct st_card_info { 345 struct req_msg * (*alloc_rq) (struct st_hba *); 346 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *); 347 void (*send) (struct st_hba *, struct req_msg *, u16); 348 unsigned int max_id; 349 unsigned int max_lun; 350 unsigned int max_channel; 351 u16 rq_count; 352 u16 rq_size; 353 u16 sts_count; 354 }; 355 356 static int msi; 357 module_param(msi, int, 0); 358 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)"); 359 360 static const char console_inq_page[] = 361 { 362 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30, 363 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */ 364 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */ 365 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */ 366 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */ 367 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */ 368 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */ 369 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20 370 }; 371 372 MODULE_AUTHOR("Ed Lin"); 373 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers"); 374 MODULE_LICENSE("GPL"); 375 MODULE_VERSION(ST_DRIVER_VERSION); 376 377 static struct status_msg *stex_get_status(struct st_hba *hba) 378 { 379 struct status_msg *status = hba->status_buffer + hba->status_tail; 380 381 ++hba->status_tail; 382 hba->status_tail %= hba->sts_count+1; 383 384 return status; 385 } 386 387 static void stex_invalid_field(struct scsi_cmnd *cmd, 388 void (*done)(struct scsi_cmnd *)) 389 { 390 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; 391 392 /* "Invalid field in cdb" */ 393 scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24, 394 0x0); 395 done(cmd); 396 } 397 398 static struct req_msg *stex_alloc_req(struct st_hba *hba) 399 { 400 struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size; 401 402 ++hba->req_head; 403 hba->req_head %= hba->rq_count+1; 404 405 return req; 406 } 407 408 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba) 409 { 410 return (struct req_msg *)(hba->dma_mem + 411 hba->req_head * hba->rq_size + sizeof(struct st_msg_header)); 412 } 413 414 static int stex_map_sg(struct st_hba *hba, 415 struct req_msg *req, struct st_ccb *ccb) 416 { 417 struct scsi_cmnd *cmd; 418 struct scatterlist *sg; 419 struct st_sgtable *dst; 420 struct st_sgitem *table; 421 int i, nseg; 422 423 cmd = ccb->cmd; 424 nseg = scsi_dma_map(cmd); 425 BUG_ON(nseg < 0); 426 if (nseg) { 427 dst = (struct st_sgtable *)req->variable; 428 429 ccb->sg_count = nseg; 430 dst->sg_count = cpu_to_le16((u16)nseg); 431 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize); 432 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); 433 434 table = (struct st_sgitem *)(dst + 1); 435 scsi_for_each_sg(cmd, sg, nseg, i) { 436 table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); 437 table[i].addr = cpu_to_le64(sg_dma_address(sg)); 438 table[i].ctrl = SG_CF_64B | SG_CF_HOST; 439 } 440 table[--i].ctrl |= SG_CF_EOT; 441 } 442 443 return nseg; 444 } 445 446 static int stex_ss_map_sg(struct st_hba *hba, 447 struct req_msg *req, struct st_ccb *ccb) 448 { 449 struct scsi_cmnd *cmd; 450 struct scatterlist *sg; 451 struct st_sgtable *dst; 452 struct st_ss_sgitem *table; 453 int i, nseg; 454 455 cmd = ccb->cmd; 456 nseg = scsi_dma_map(cmd); 457 BUG_ON(nseg < 0); 458 if (nseg) { 459 dst = (struct st_sgtable *)req->variable; 460 461 ccb->sg_count = nseg; 462 dst->sg_count = cpu_to_le16((u16)nseg); 463 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize); 464 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); 465 466 table = (struct st_ss_sgitem *)(dst + 1); 467 scsi_for_each_sg(cmd, sg, nseg, i) { 468 table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); 469 table[i].addr = 470 cpu_to_le32(sg_dma_address(sg) & 0xffffffff); 471 table[i].addr_hi = 472 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16); 473 } 474 } 475 476 return nseg; 477 } 478 479 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb) 480 { 481 struct st_frame *p; 482 size_t count = sizeof(struct st_frame); 483 484 p = hba->copy_buffer; 485 scsi_sg_copy_to_buffer(ccb->cmd, p, count); 486 memset(p->base, 0, sizeof(u32)*6); 487 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0); 488 p->rom_addr = 0; 489 490 p->drv_ver.major = ST_VER_MAJOR; 491 p->drv_ver.minor = ST_VER_MINOR; 492 p->drv_ver.oem = ST_OEM; 493 p->drv_ver.build = ST_BUILD_VER; 494 495 p->bus = hba->pdev->bus->number; 496 p->slot = hba->pdev->devfn; 497 p->irq_level = 0; 498 p->irq_vec = hba->pdev->irq; 499 p->id = hba->pdev->vendor << 16 | hba->pdev->device; 500 p->subid = 501 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device; 502 503 scsi_sg_copy_from_buffer(ccb->cmd, p, count); 504 } 505 506 static void 507 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) 508 { 509 req->tag = cpu_to_le16(tag); 510 511 hba->ccb[tag].req = req; 512 hba->out_req_cnt++; 513 514 writel(hba->req_head, hba->mmio_base + IMR0); 515 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); 516 readl(hba->mmio_base + IDBL); /* flush */ 517 } 518 519 static void 520 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) 521 { 522 struct scsi_cmnd *cmd; 523 struct st_msg_header *msg_h; 524 dma_addr_t addr; 525 526 req->tag = cpu_to_le16(tag); 527 528 hba->ccb[tag].req = req; 529 hba->out_req_cnt++; 530 531 cmd = hba->ccb[tag].cmd; 532 msg_h = (struct st_msg_header *)req - 1; 533 if (likely(cmd)) { 534 msg_h->channel = (u8)cmd->device->channel; 535 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ); 536 } 537 addr = hba->dma_handle + hba->req_head * hba->rq_size; 538 addr += (hba->ccb[tag].sg_count+4)/11; 539 msg_h->handle = cpu_to_le64(addr); 540 541 ++hba->req_head; 542 hba->req_head %= hba->rq_count+1; 543 544 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); 545 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */ 546 writel(addr, hba->mmio_base + YH2I_REQ); 547 readl(hba->mmio_base + YH2I_REQ); /* flush */ 548 } 549 550 static void return_abnormal_state(struct st_hba *hba, int status) 551 { 552 struct st_ccb *ccb; 553 unsigned long flags; 554 u16 tag; 555 556 spin_lock_irqsave(hba->host->host_lock, flags); 557 for (tag = 0; tag < hba->host->can_queue; tag++) { 558 ccb = &hba->ccb[tag]; 559 if (ccb->req == NULL) 560 continue; 561 ccb->req = NULL; 562 if (ccb->cmd) { 563 scsi_dma_unmap(ccb->cmd); 564 ccb->cmd->result = status << 16; 565 ccb->cmd->scsi_done(ccb->cmd); 566 ccb->cmd = NULL; 567 } 568 } 569 spin_unlock_irqrestore(hba->host->host_lock, flags); 570 } 571 static int 572 stex_slave_config(struct scsi_device *sdev) 573 { 574 sdev->use_10_for_rw = 1; 575 sdev->use_10_for_ms = 1; 576 blk_queue_rq_timeout(sdev->request_queue, 60 * HZ); 577 578 return 0; 579 } 580 581 static int 582 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *)) 583 { 584 struct st_hba *hba; 585 struct Scsi_Host *host; 586 unsigned int id, lun; 587 struct req_msg *req; 588 u16 tag; 589 590 host = cmd->device->host; 591 id = cmd->device->id; 592 lun = cmd->device->lun; 593 hba = (struct st_hba *) &host->hostdata[0]; 594 if (hba->mu_status == MU_STATE_NOCONNECT) { 595 cmd->result = DID_NO_CONNECT; 596 done(cmd); 597 return 0; 598 } 599 if (unlikely(hba->mu_status != MU_STATE_STARTED)) 600 return SCSI_MLQUEUE_HOST_BUSY; 601 602 switch (cmd->cmnd[0]) { 603 case MODE_SENSE_10: 604 { 605 static char ms10_caching_page[12] = 606 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 }; 607 unsigned char page; 608 609 page = cmd->cmnd[2] & 0x3f; 610 if (page == 0x8 || page == 0x3f) { 611 scsi_sg_copy_from_buffer(cmd, ms10_caching_page, 612 sizeof(ms10_caching_page)); 613 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 614 done(cmd); 615 } else 616 stex_invalid_field(cmd, done); 617 return 0; 618 } 619 case REPORT_LUNS: 620 /* 621 * The shasta firmware does not report actual luns in the 622 * target, so fail the command to force sequential lun scan. 623 * Also, the console device does not support this command. 624 */ 625 if (hba->cardtype == st_shasta || id == host->max_id - 1) { 626 stex_invalid_field(cmd, done); 627 return 0; 628 } 629 break; 630 case TEST_UNIT_READY: 631 if (id == host->max_id - 1) { 632 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 633 done(cmd); 634 return 0; 635 } 636 break; 637 case INQUIRY: 638 if (lun >= host->max_lun) { 639 cmd->result = DID_NO_CONNECT << 16; 640 done(cmd); 641 return 0; 642 } 643 if (id != host->max_id - 1) 644 break; 645 if (!lun && !cmd->device->channel && 646 (cmd->cmnd[1] & INQUIRY_EVPD) == 0) { 647 scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page, 648 sizeof(console_inq_page)); 649 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; 650 done(cmd); 651 } else 652 stex_invalid_field(cmd, done); 653 return 0; 654 case PASSTHRU_CMD: 655 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) { 656 struct st_drvver ver; 657 size_t cp_len = sizeof(ver); 658 659 ver.major = ST_VER_MAJOR; 660 ver.minor = ST_VER_MINOR; 661 ver.oem = ST_OEM; 662 ver.build = ST_BUILD_VER; 663 ver.signature[0] = PASSTHRU_SIGNATURE; 664 ver.console_id = host->max_id - 1; 665 ver.host_no = hba->host->host_no; 666 cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len); 667 cmd->result = sizeof(ver) == cp_len ? 668 DID_OK << 16 | COMMAND_COMPLETE << 8 : 669 DID_ERROR << 16 | COMMAND_COMPLETE << 8; 670 done(cmd); 671 return 0; 672 } 673 default: 674 break; 675 } 676 677 cmd->scsi_done = done; 678 679 tag = cmd->request->tag; 680 681 if (unlikely(tag >= host->can_queue)) 682 return SCSI_MLQUEUE_HOST_BUSY; 683 684 req = hba->alloc_rq(hba); 685 686 req->lun = lun; 687 req->target = id; 688 689 /* cdb */ 690 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH); 691 692 if (cmd->sc_data_direction == DMA_FROM_DEVICE) 693 req->data_dir = MSG_DATA_DIR_IN; 694 else if (cmd->sc_data_direction == DMA_TO_DEVICE) 695 req->data_dir = MSG_DATA_DIR_OUT; 696 else 697 req->data_dir = MSG_DATA_DIR_ND; 698 699 hba->ccb[tag].cmd = cmd; 700 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE; 701 hba->ccb[tag].sense_buffer = cmd->sense_buffer; 702 703 if (!hba->map_sg(hba, req, &hba->ccb[tag])) { 704 hba->ccb[tag].sg_count = 0; 705 memset(&req->variable[0], 0, 8); 706 } 707 708 hba->send(hba, req, tag); 709 return 0; 710 } 711 712 static DEF_SCSI_QCMD(stex_queuecommand) 713 714 static void stex_scsi_done(struct st_ccb *ccb) 715 { 716 struct scsi_cmnd *cmd = ccb->cmd; 717 int result; 718 719 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) { 720 result = ccb->scsi_status; 721 switch (ccb->scsi_status) { 722 case SAM_STAT_GOOD: 723 result |= DID_OK << 16 | COMMAND_COMPLETE << 8; 724 break; 725 case SAM_STAT_CHECK_CONDITION: 726 result |= DRIVER_SENSE << 24; 727 break; 728 case SAM_STAT_BUSY: 729 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; 730 break; 731 default: 732 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8; 733 break; 734 } 735 } 736 else if (ccb->srb_status & SRB_SEE_SENSE) 737 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION; 738 else switch (ccb->srb_status) { 739 case SRB_STATUS_SELECTION_TIMEOUT: 740 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8; 741 break; 742 case SRB_STATUS_BUSY: 743 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; 744 break; 745 case SRB_STATUS_INVALID_REQUEST: 746 case SRB_STATUS_ERROR: 747 default: 748 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8; 749 break; 750 } 751 752 cmd->result = result; 753 cmd->scsi_done(cmd); 754 } 755 756 static void stex_copy_data(struct st_ccb *ccb, 757 struct status_msg *resp, unsigned int variable) 758 { 759 if (resp->scsi_status != SAM_STAT_GOOD) { 760 if (ccb->sense_buffer != NULL) 761 memcpy(ccb->sense_buffer, resp->variable, 762 min(variable, ccb->sense_bufflen)); 763 return; 764 } 765 766 if (ccb->cmd == NULL) 767 return; 768 scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable); 769 } 770 771 static void stex_check_cmd(struct st_hba *hba, 772 struct st_ccb *ccb, struct status_msg *resp) 773 { 774 if (ccb->cmd->cmnd[0] == MGT_CMD && 775 resp->scsi_status != SAM_STAT_CHECK_CONDITION) 776 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) - 777 le32_to_cpu(*(__le32 *)&resp->variable[0])); 778 } 779 780 static void stex_mu_intr(struct st_hba *hba, u32 doorbell) 781 { 782 void __iomem *base = hba->mmio_base; 783 struct status_msg *resp; 784 struct st_ccb *ccb; 785 unsigned int size; 786 u16 tag; 787 788 if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))) 789 return; 790 791 /* status payloads */ 792 hba->status_head = readl(base + OMR1); 793 if (unlikely(hba->status_head > hba->sts_count)) { 794 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n", 795 pci_name(hba->pdev)); 796 return; 797 } 798 799 /* 800 * it's not a valid status payload if: 801 * 1. there are no pending requests(e.g. during init stage) 802 * 2. there are some pending requests, but the controller is in 803 * reset status, and its type is not st_yosemite 804 * firmware of st_yosemite in reset status will return pending requests 805 * to driver, so we allow it to pass 806 */ 807 if (unlikely(hba->out_req_cnt <= 0 || 808 (hba->mu_status == MU_STATE_RESETTING && 809 hba->cardtype != st_yosemite))) { 810 hba->status_tail = hba->status_head; 811 goto update_status; 812 } 813 814 while (hba->status_tail != hba->status_head) { 815 resp = stex_get_status(hba); 816 tag = le16_to_cpu(resp->tag); 817 if (unlikely(tag >= hba->host->can_queue)) { 818 printk(KERN_WARNING DRV_NAME 819 "(%s): invalid tag\n", pci_name(hba->pdev)); 820 continue; 821 } 822 823 hba->out_req_cnt--; 824 ccb = &hba->ccb[tag]; 825 if (unlikely(hba->wait_ccb == ccb)) 826 hba->wait_ccb = NULL; 827 if (unlikely(ccb->req == NULL)) { 828 printk(KERN_WARNING DRV_NAME 829 "(%s): lagging req\n", pci_name(hba->pdev)); 830 continue; 831 } 832 833 size = resp->payload_sz * sizeof(u32); /* payload size */ 834 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || 835 size > sizeof(*resp))) { 836 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n", 837 pci_name(hba->pdev)); 838 } else { 839 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */ 840 if (size) 841 stex_copy_data(ccb, resp, size); 842 } 843 844 ccb->req = NULL; 845 ccb->srb_status = resp->srb_status; 846 ccb->scsi_status = resp->scsi_status; 847 848 if (likely(ccb->cmd != NULL)) { 849 if (hba->cardtype == st_yosemite) 850 stex_check_cmd(hba, ccb, resp); 851 852 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD && 853 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER)) 854 stex_controller_info(hba, ccb); 855 856 scsi_dma_unmap(ccb->cmd); 857 stex_scsi_done(ccb); 858 } else 859 ccb->req_type = 0; 860 } 861 862 update_status: 863 writel(hba->status_head, base + IMR1); 864 readl(base + IMR1); /* flush */ 865 } 866 867 static irqreturn_t stex_intr(int irq, void *__hba) 868 { 869 struct st_hba *hba = __hba; 870 void __iomem *base = hba->mmio_base; 871 u32 data; 872 unsigned long flags; 873 874 spin_lock_irqsave(hba->host->host_lock, flags); 875 876 data = readl(base + ODBL); 877 878 if (data && data != 0xffffffff) { 879 /* clear the interrupt */ 880 writel(data, base + ODBL); 881 readl(base + ODBL); /* flush */ 882 stex_mu_intr(hba, data); 883 spin_unlock_irqrestore(hba->host->host_lock, flags); 884 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET && 885 hba->cardtype == st_shasta)) 886 queue_work(hba->work_q, &hba->reset_work); 887 return IRQ_HANDLED; 888 } 889 890 spin_unlock_irqrestore(hba->host->host_lock, flags); 891 892 return IRQ_NONE; 893 } 894 895 static void stex_ss_mu_intr(struct st_hba *hba) 896 { 897 struct status_msg *resp; 898 struct st_ccb *ccb; 899 __le32 *scratch; 900 unsigned int size; 901 int count = 0; 902 u32 value; 903 u16 tag; 904 905 if (unlikely(hba->out_req_cnt <= 0 || 906 hba->mu_status == MU_STATE_RESETTING)) 907 return; 908 909 while (count < hba->sts_count) { 910 scratch = hba->scratch + hba->status_tail; 911 value = le32_to_cpu(*scratch); 912 if (unlikely(!(value & SS_STS_NORMAL))) 913 return; 914 915 resp = hba->status_buffer + hba->status_tail; 916 *scratch = 0; 917 ++count; 918 ++hba->status_tail; 919 hba->status_tail %= hba->sts_count+1; 920 921 tag = (u16)value; 922 if (unlikely(tag >= hba->host->can_queue)) { 923 printk(KERN_WARNING DRV_NAME 924 "(%s): invalid tag\n", pci_name(hba->pdev)); 925 continue; 926 } 927 928 hba->out_req_cnt--; 929 ccb = &hba->ccb[tag]; 930 if (unlikely(hba->wait_ccb == ccb)) 931 hba->wait_ccb = NULL; 932 if (unlikely(ccb->req == NULL)) { 933 printk(KERN_WARNING DRV_NAME 934 "(%s): lagging req\n", pci_name(hba->pdev)); 935 continue; 936 } 937 938 ccb->req = NULL; 939 if (likely(value & SS_STS_DONE)) { /* normal case */ 940 ccb->srb_status = SRB_STATUS_SUCCESS; 941 ccb->scsi_status = SAM_STAT_GOOD; 942 } else { 943 ccb->srb_status = resp->srb_status; 944 ccb->scsi_status = resp->scsi_status; 945 size = resp->payload_sz * sizeof(u32); 946 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || 947 size > sizeof(*resp))) { 948 printk(KERN_WARNING DRV_NAME 949 "(%s): bad status size\n", 950 pci_name(hba->pdev)); 951 } else { 952 size -= sizeof(*resp) - STATUS_VAR_LEN; 953 if (size) 954 stex_copy_data(ccb, resp, size); 955 } 956 if (likely(ccb->cmd != NULL)) 957 stex_check_cmd(hba, ccb, resp); 958 } 959 960 if (likely(ccb->cmd != NULL)) { 961 scsi_dma_unmap(ccb->cmd); 962 stex_scsi_done(ccb); 963 } else 964 ccb->req_type = 0; 965 } 966 } 967 968 static irqreturn_t stex_ss_intr(int irq, void *__hba) 969 { 970 struct st_hba *hba = __hba; 971 void __iomem *base = hba->mmio_base; 972 u32 data; 973 unsigned long flags; 974 975 spin_lock_irqsave(hba->host->host_lock, flags); 976 977 data = readl(base + YI2H_INT); 978 if (data && data != 0xffffffff) { 979 /* clear the interrupt */ 980 writel(data, base + YI2H_INT_C); 981 stex_ss_mu_intr(hba); 982 spin_unlock_irqrestore(hba->host->host_lock, flags); 983 if (unlikely(data & SS_I2H_REQUEST_RESET)) 984 queue_work(hba->work_q, &hba->reset_work); 985 return IRQ_HANDLED; 986 } 987 988 spin_unlock_irqrestore(hba->host->host_lock, flags); 989 990 return IRQ_NONE; 991 } 992 993 static int stex_common_handshake(struct st_hba *hba) 994 { 995 void __iomem *base = hba->mmio_base; 996 struct handshake_frame *h; 997 dma_addr_t status_phys; 998 u32 data; 999 unsigned long before; 1000 1001 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 1002 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 1003 readl(base + IDBL); 1004 before = jiffies; 1005 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 1006 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1007 printk(KERN_ERR DRV_NAME 1008 "(%s): no handshake signature\n", 1009 pci_name(hba->pdev)); 1010 return -1; 1011 } 1012 rmb(); 1013 msleep(1); 1014 } 1015 } 1016 1017 udelay(10); 1018 1019 data = readl(base + OMR1); 1020 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) { 1021 data &= 0x0000ffff; 1022 if (hba->host->can_queue > data) { 1023 hba->host->can_queue = data; 1024 hba->host->cmd_per_lun = data; 1025 } 1026 } 1027 1028 h = (struct handshake_frame *)hba->status_buffer; 1029 h->rb_phy = cpu_to_le64(hba->dma_handle); 1030 h->req_sz = cpu_to_le16(hba->rq_size); 1031 h->req_cnt = cpu_to_le16(hba->rq_count+1); 1032 h->status_sz = cpu_to_le16(sizeof(struct status_msg)); 1033 h->status_cnt = cpu_to_le16(hba->sts_count+1); 1034 h->hosttime = cpu_to_le64(ktime_get_real_seconds()); 1035 h->partner_type = HMU_PARTNER_TYPE; 1036 if (hba->extra_offset) { 1037 h->extra_offset = cpu_to_le32(hba->extra_offset); 1038 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset); 1039 } else 1040 h->extra_offset = h->extra_size = 0; 1041 1042 status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size; 1043 writel(status_phys, base + IMR0); 1044 readl(base + IMR0); 1045 writel((status_phys >> 16) >> 16, base + IMR1); 1046 readl(base + IMR1); 1047 1048 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */ 1049 readl(base + OMR0); 1050 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); 1051 readl(base + IDBL); /* flush */ 1052 1053 udelay(10); 1054 before = jiffies; 1055 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { 1056 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1057 printk(KERN_ERR DRV_NAME 1058 "(%s): no signature after handshake frame\n", 1059 pci_name(hba->pdev)); 1060 return -1; 1061 } 1062 rmb(); 1063 msleep(1); 1064 } 1065 1066 writel(0, base + IMR0); 1067 readl(base + IMR0); 1068 writel(0, base + OMR0); 1069 readl(base + OMR0); 1070 writel(0, base + IMR1); 1071 readl(base + IMR1); 1072 writel(0, base + OMR1); 1073 readl(base + OMR1); /* flush */ 1074 return 0; 1075 } 1076 1077 static int stex_ss_handshake(struct st_hba *hba) 1078 { 1079 void __iomem *base = hba->mmio_base; 1080 struct st_msg_header *msg_h; 1081 struct handshake_frame *h; 1082 __le32 *scratch; 1083 u32 data, scratch_size; 1084 unsigned long before; 1085 int ret = 0; 1086 1087 before = jiffies; 1088 while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) { 1089 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1090 printk(KERN_ERR DRV_NAME 1091 "(%s): firmware not operational\n", 1092 pci_name(hba->pdev)); 1093 return -1; 1094 } 1095 msleep(1); 1096 } 1097 1098 msg_h = (struct st_msg_header *)hba->dma_mem; 1099 msg_h->handle = cpu_to_le64(hba->dma_handle); 1100 msg_h->flag = SS_HEAD_HANDSHAKE; 1101 1102 h = (struct handshake_frame *)(msg_h + 1); 1103 h->rb_phy = cpu_to_le64(hba->dma_handle); 1104 h->req_sz = cpu_to_le16(hba->rq_size); 1105 h->req_cnt = cpu_to_le16(hba->rq_count+1); 1106 h->status_sz = cpu_to_le16(sizeof(struct status_msg)); 1107 h->status_cnt = cpu_to_le16(hba->sts_count+1); 1108 h->hosttime = cpu_to_le64(ktime_get_real_seconds()); 1109 h->partner_type = HMU_PARTNER_TYPE; 1110 h->extra_offset = h->extra_size = 0; 1111 scratch_size = (hba->sts_count+1)*sizeof(u32); 1112 h->scratch_size = cpu_to_le32(scratch_size); 1113 1114 data = readl(base + YINT_EN); 1115 data &= ~4; 1116 writel(data, base + YINT_EN); 1117 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI); 1118 readl(base + YH2I_REQ_HI); 1119 writel(hba->dma_handle, base + YH2I_REQ); 1120 readl(base + YH2I_REQ); /* flush */ 1121 1122 scratch = hba->scratch; 1123 before = jiffies; 1124 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) { 1125 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { 1126 printk(KERN_ERR DRV_NAME 1127 "(%s): no signature after handshake frame\n", 1128 pci_name(hba->pdev)); 1129 ret = -1; 1130 break; 1131 } 1132 rmb(); 1133 msleep(1); 1134 } 1135 1136 memset(scratch, 0, scratch_size); 1137 msg_h->flag = 0; 1138 return ret; 1139 } 1140 1141 static int stex_handshake(struct st_hba *hba) 1142 { 1143 int err; 1144 unsigned long flags; 1145 unsigned int mu_status; 1146 1147 err = (hba->cardtype == st_yel) ? 1148 stex_ss_handshake(hba) : stex_common_handshake(hba); 1149 spin_lock_irqsave(hba->host->host_lock, flags); 1150 mu_status = hba->mu_status; 1151 if (err == 0) { 1152 hba->req_head = 0; 1153 hba->req_tail = 0; 1154 hba->status_head = 0; 1155 hba->status_tail = 0; 1156 hba->out_req_cnt = 0; 1157 hba->mu_status = MU_STATE_STARTED; 1158 } else 1159 hba->mu_status = MU_STATE_FAILED; 1160 if (mu_status == MU_STATE_RESETTING) 1161 wake_up_all(&hba->reset_waitq); 1162 spin_unlock_irqrestore(hba->host->host_lock, flags); 1163 return err; 1164 } 1165 1166 static int stex_abort(struct scsi_cmnd *cmd) 1167 { 1168 struct Scsi_Host *host = cmd->device->host; 1169 struct st_hba *hba = (struct st_hba *)host->hostdata; 1170 u16 tag = cmd->request->tag; 1171 void __iomem *base; 1172 u32 data; 1173 int result = SUCCESS; 1174 unsigned long flags; 1175 1176 scmd_printk(KERN_INFO, cmd, "aborting command\n"); 1177 1178 base = hba->mmio_base; 1179 spin_lock_irqsave(host->host_lock, flags); 1180 if (tag < host->can_queue && 1181 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd) 1182 hba->wait_ccb = &hba->ccb[tag]; 1183 else 1184 goto out; 1185 1186 if (hba->cardtype == st_yel) { 1187 data = readl(base + YI2H_INT); 1188 if (data == 0 || data == 0xffffffff) 1189 goto fail_out; 1190 1191 writel(data, base + YI2H_INT_C); 1192 stex_ss_mu_intr(hba); 1193 } else { 1194 data = readl(base + ODBL); 1195 if (data == 0 || data == 0xffffffff) 1196 goto fail_out; 1197 1198 writel(data, base + ODBL); 1199 readl(base + ODBL); /* flush */ 1200 1201 stex_mu_intr(hba, data); 1202 } 1203 if (hba->wait_ccb == NULL) { 1204 printk(KERN_WARNING DRV_NAME 1205 "(%s): lost interrupt\n", pci_name(hba->pdev)); 1206 goto out; 1207 } 1208 1209 fail_out: 1210 scsi_dma_unmap(cmd); 1211 hba->wait_ccb->req = NULL; /* nullify the req's future return */ 1212 hba->wait_ccb = NULL; 1213 result = FAILED; 1214 out: 1215 spin_unlock_irqrestore(host->host_lock, flags); 1216 return result; 1217 } 1218 1219 static void stex_hard_reset(struct st_hba *hba) 1220 { 1221 struct pci_bus *bus; 1222 int i; 1223 u16 pci_cmd; 1224 u8 pci_bctl; 1225 1226 for (i = 0; i < 16; i++) 1227 pci_read_config_dword(hba->pdev, i * 4, 1228 &hba->pdev->saved_config_space[i]); 1229 1230 /* Reset secondary bus. Our controller(MU/ATU) is the only device on 1231 secondary bus. Consult Intel 80331/3 developer's manual for detail */ 1232 bus = hba->pdev->bus; 1233 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); 1234 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; 1235 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1236 1237 /* 1238 * 1 ms may be enough for 8-port controllers. But 16-port controllers 1239 * require more time to finish bus reset. Use 100 ms here for safety 1240 */ 1241 msleep(100); 1242 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; 1243 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); 1244 1245 for (i = 0; i < MU_HARD_RESET_WAIT; i++) { 1246 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd); 1247 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER)) 1248 break; 1249 msleep(1); 1250 } 1251 1252 ssleep(5); 1253 for (i = 0; i < 16; i++) 1254 pci_write_config_dword(hba->pdev, i * 4, 1255 hba->pdev->saved_config_space[i]); 1256 } 1257 1258 static int stex_yos_reset(struct st_hba *hba) 1259 { 1260 void __iomem *base; 1261 unsigned long flags, before; 1262 int ret = 0; 1263 1264 base = hba->mmio_base; 1265 writel(MU_INBOUND_DOORBELL_RESET, base + IDBL); 1266 readl(base + IDBL); /* flush */ 1267 before = jiffies; 1268 while (hba->out_req_cnt > 0) { 1269 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { 1270 printk(KERN_WARNING DRV_NAME 1271 "(%s): reset timeout\n", pci_name(hba->pdev)); 1272 ret = -1; 1273 break; 1274 } 1275 msleep(1); 1276 } 1277 1278 spin_lock_irqsave(hba->host->host_lock, flags); 1279 if (ret == -1) 1280 hba->mu_status = MU_STATE_FAILED; 1281 else 1282 hba->mu_status = MU_STATE_STARTED; 1283 wake_up_all(&hba->reset_waitq); 1284 spin_unlock_irqrestore(hba->host->host_lock, flags); 1285 1286 return ret; 1287 } 1288 1289 static void stex_ss_reset(struct st_hba *hba) 1290 { 1291 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT); 1292 readl(hba->mmio_base + YH2I_INT); 1293 ssleep(5); 1294 } 1295 1296 static int stex_do_reset(struct st_hba *hba) 1297 { 1298 unsigned long flags; 1299 unsigned int mu_status = MU_STATE_RESETTING; 1300 1301 spin_lock_irqsave(hba->host->host_lock, flags); 1302 if (hba->mu_status == MU_STATE_STARTING) { 1303 spin_unlock_irqrestore(hba->host->host_lock, flags); 1304 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n", 1305 pci_name(hba->pdev)); 1306 return 0; 1307 } 1308 while (hba->mu_status == MU_STATE_RESETTING) { 1309 spin_unlock_irqrestore(hba->host->host_lock, flags); 1310 wait_event_timeout(hba->reset_waitq, 1311 hba->mu_status != MU_STATE_RESETTING, 1312 MU_MAX_DELAY * HZ); 1313 spin_lock_irqsave(hba->host->host_lock, flags); 1314 mu_status = hba->mu_status; 1315 } 1316 1317 if (mu_status != MU_STATE_RESETTING) { 1318 spin_unlock_irqrestore(hba->host->host_lock, flags); 1319 return (mu_status == MU_STATE_STARTED) ? 0 : -1; 1320 } 1321 1322 hba->mu_status = MU_STATE_RESETTING; 1323 spin_unlock_irqrestore(hba->host->host_lock, flags); 1324 1325 if (hba->cardtype == st_yosemite) 1326 return stex_yos_reset(hba); 1327 1328 if (hba->cardtype == st_shasta) 1329 stex_hard_reset(hba); 1330 else if (hba->cardtype == st_yel) 1331 stex_ss_reset(hba); 1332 1333 1334 return_abnormal_state(hba, DID_RESET); 1335 1336 if (stex_handshake(hba) == 0) 1337 return 0; 1338 1339 printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n", 1340 pci_name(hba->pdev)); 1341 return -1; 1342 } 1343 1344 static int stex_reset(struct scsi_cmnd *cmd) 1345 { 1346 struct st_hba *hba; 1347 1348 hba = (struct st_hba *) &cmd->device->host->hostdata[0]; 1349 1350 shost_printk(KERN_INFO, cmd->device->host, 1351 "resetting host\n"); 1352 1353 return stex_do_reset(hba) ? FAILED : SUCCESS; 1354 } 1355 1356 static void stex_reset_work(struct work_struct *work) 1357 { 1358 struct st_hba *hba = container_of(work, struct st_hba, reset_work); 1359 1360 stex_do_reset(hba); 1361 } 1362 1363 static int stex_biosparam(struct scsi_device *sdev, 1364 struct block_device *bdev, sector_t capacity, int geom[]) 1365 { 1366 int heads = 255, sectors = 63; 1367 1368 if (capacity < 0x200000) { 1369 heads = 64; 1370 sectors = 32; 1371 } 1372 1373 sector_div(capacity, heads * sectors); 1374 1375 geom[0] = heads; 1376 geom[1] = sectors; 1377 geom[2] = capacity; 1378 1379 return 0; 1380 } 1381 1382 static struct scsi_host_template driver_template = { 1383 .module = THIS_MODULE, 1384 .name = DRV_NAME, 1385 .proc_name = DRV_NAME, 1386 .bios_param = stex_biosparam, 1387 .queuecommand = stex_queuecommand, 1388 .slave_configure = stex_slave_config, 1389 .eh_abort_handler = stex_abort, 1390 .eh_host_reset_handler = stex_reset, 1391 .this_id = -1, 1392 }; 1393 1394 static struct pci_device_id stex_pci_tbl[] = { 1395 /* st_shasta */ 1396 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1397 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */ 1398 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1399 st_shasta }, /* SuperTrak EX12350 */ 1400 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1401 st_shasta }, /* SuperTrak EX4350 */ 1402 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1403 st_shasta }, /* SuperTrak EX24350 */ 1404 1405 /* st_vsc */ 1406 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc }, 1407 1408 /* st_yosemite */ 1409 { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite }, 1410 1411 /* st_seq */ 1412 { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq }, 1413 1414 /* st_yel */ 1415 { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel }, 1416 { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel }, 1417 { } /* terminate list */ 1418 }; 1419 1420 static struct st_card_info stex_card_info[] = { 1421 /* st_shasta */ 1422 { 1423 .max_id = 17, 1424 .max_lun = 8, 1425 .max_channel = 0, 1426 .rq_count = 32, 1427 .rq_size = 1048, 1428 .sts_count = 32, 1429 .alloc_rq = stex_alloc_req, 1430 .map_sg = stex_map_sg, 1431 .send = stex_send_cmd, 1432 }, 1433 1434 /* st_vsc */ 1435 { 1436 .max_id = 129, 1437 .max_lun = 1, 1438 .max_channel = 0, 1439 .rq_count = 32, 1440 .rq_size = 1048, 1441 .sts_count = 32, 1442 .alloc_rq = stex_alloc_req, 1443 .map_sg = stex_map_sg, 1444 .send = stex_send_cmd, 1445 }, 1446 1447 /* st_yosemite */ 1448 { 1449 .max_id = 2, 1450 .max_lun = 256, 1451 .max_channel = 0, 1452 .rq_count = 256, 1453 .rq_size = 1048, 1454 .sts_count = 256, 1455 .alloc_rq = stex_alloc_req, 1456 .map_sg = stex_map_sg, 1457 .send = stex_send_cmd, 1458 }, 1459 1460 /* st_seq */ 1461 { 1462 .max_id = 129, 1463 .max_lun = 1, 1464 .max_channel = 0, 1465 .rq_count = 32, 1466 .rq_size = 1048, 1467 .sts_count = 32, 1468 .alloc_rq = stex_alloc_req, 1469 .map_sg = stex_map_sg, 1470 .send = stex_send_cmd, 1471 }, 1472 1473 /* st_yel */ 1474 { 1475 .max_id = 129, 1476 .max_lun = 256, 1477 .max_channel = 3, 1478 .rq_count = 801, 1479 .rq_size = 512, 1480 .sts_count = 801, 1481 .alloc_rq = stex_ss_alloc_req, 1482 .map_sg = stex_ss_map_sg, 1483 .send = stex_ss_send_cmd, 1484 }, 1485 }; 1486 1487 static int stex_set_dma_mask(struct pci_dev * pdev) 1488 { 1489 int ret; 1490 1491 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) 1492 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) 1493 return 0; 1494 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1495 if (!ret) 1496 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1497 return ret; 1498 } 1499 1500 static int stex_request_irq(struct st_hba *hba) 1501 { 1502 struct pci_dev *pdev = hba->pdev; 1503 int status; 1504 1505 if (msi) { 1506 status = pci_enable_msi(pdev); 1507 if (status != 0) 1508 printk(KERN_ERR DRV_NAME 1509 "(%s): error %d setting up MSI\n", 1510 pci_name(pdev), status); 1511 else 1512 hba->msi_enabled = 1; 1513 } else 1514 hba->msi_enabled = 0; 1515 1516 status = request_irq(pdev->irq, hba->cardtype == st_yel ? 1517 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba); 1518 1519 if (status != 0) { 1520 if (hba->msi_enabled) 1521 pci_disable_msi(pdev); 1522 } 1523 return status; 1524 } 1525 1526 static void stex_free_irq(struct st_hba *hba) 1527 { 1528 struct pci_dev *pdev = hba->pdev; 1529 1530 free_irq(pdev->irq, hba); 1531 if (hba->msi_enabled) 1532 pci_disable_msi(pdev); 1533 } 1534 1535 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1536 { 1537 struct st_hba *hba; 1538 struct Scsi_Host *host; 1539 const struct st_card_info *ci = NULL; 1540 u32 sts_offset, cp_offset, scratch_offset; 1541 int err; 1542 1543 err = pci_enable_device(pdev); 1544 if (err) 1545 return err; 1546 1547 pci_set_master(pdev); 1548 1549 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba)); 1550 1551 if (!host) { 1552 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n", 1553 pci_name(pdev)); 1554 err = -ENOMEM; 1555 goto out_disable; 1556 } 1557 1558 hba = (struct st_hba *)host->hostdata; 1559 memset(hba, 0, sizeof(struct st_hba)); 1560 1561 err = pci_request_regions(pdev, DRV_NAME); 1562 if (err < 0) { 1563 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n", 1564 pci_name(pdev)); 1565 goto out_scsi_host_put; 1566 } 1567 1568 hba->mmio_base = pci_ioremap_bar(pdev, 0); 1569 if ( !hba->mmio_base) { 1570 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n", 1571 pci_name(pdev)); 1572 err = -ENOMEM; 1573 goto out_release_regions; 1574 } 1575 1576 err = stex_set_dma_mask(pdev); 1577 if (err) { 1578 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n", 1579 pci_name(pdev)); 1580 goto out_iounmap; 1581 } 1582 1583 hba->cardtype = (unsigned int) id->driver_data; 1584 ci = &stex_card_info[hba->cardtype]; 1585 switch (id->subdevice) { 1586 case 0x4221: 1587 case 0x4222: 1588 case 0x4223: 1589 case 0x4224: 1590 case 0x4225: 1591 case 0x4226: 1592 case 0x4227: 1593 case 0x4261: 1594 case 0x4262: 1595 case 0x4263: 1596 case 0x4264: 1597 case 0x4265: 1598 break; 1599 default: 1600 if (hba->cardtype == st_yel) 1601 hba->supports_pm = 1; 1602 } 1603 1604 sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size; 1605 if (hba->cardtype == st_yel) 1606 sts_offset += (ci->sts_count+1) * sizeof(u32); 1607 cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg); 1608 hba->dma_size = cp_offset + sizeof(struct st_frame); 1609 if (hba->cardtype == st_seq || 1610 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) { 1611 hba->extra_offset = hba->dma_size; 1612 hba->dma_size += ST_ADDITIONAL_MEM; 1613 } 1614 hba->dma_mem = dma_alloc_coherent(&pdev->dev, 1615 hba->dma_size, &hba->dma_handle, GFP_KERNEL); 1616 if (!hba->dma_mem) { 1617 /* Retry minimum coherent mapping for st_seq and st_vsc */ 1618 if (hba->cardtype == st_seq || 1619 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) { 1620 printk(KERN_WARNING DRV_NAME 1621 "(%s): allocating min buffer for controller\n", 1622 pci_name(pdev)); 1623 hba->dma_size = hba->extra_offset 1624 + ST_ADDITIONAL_MEM_MIN; 1625 hba->dma_mem = dma_alloc_coherent(&pdev->dev, 1626 hba->dma_size, &hba->dma_handle, GFP_KERNEL); 1627 } 1628 1629 if (!hba->dma_mem) { 1630 err = -ENOMEM; 1631 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n", 1632 pci_name(pdev)); 1633 goto out_iounmap; 1634 } 1635 } 1636 1637 hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL); 1638 if (!hba->ccb) { 1639 err = -ENOMEM; 1640 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n", 1641 pci_name(pdev)); 1642 goto out_pci_free; 1643 } 1644 1645 if (hba->cardtype == st_yel) 1646 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset); 1647 hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset); 1648 hba->copy_buffer = hba->dma_mem + cp_offset; 1649 hba->rq_count = ci->rq_count; 1650 hba->rq_size = ci->rq_size; 1651 hba->sts_count = ci->sts_count; 1652 hba->alloc_rq = ci->alloc_rq; 1653 hba->map_sg = ci->map_sg; 1654 hba->send = ci->send; 1655 hba->mu_status = MU_STATE_STARTING; 1656 1657 if (hba->cardtype == st_yel) 1658 host->sg_tablesize = 38; 1659 else 1660 host->sg_tablesize = 32; 1661 host->can_queue = ci->rq_count; 1662 host->cmd_per_lun = ci->rq_count; 1663 host->max_id = ci->max_id; 1664 host->max_lun = ci->max_lun; 1665 host->max_channel = ci->max_channel; 1666 host->unique_id = host->host_no; 1667 host->max_cmd_len = STEX_CDB_LENGTH; 1668 1669 hba->host = host; 1670 hba->pdev = pdev; 1671 init_waitqueue_head(&hba->reset_waitq); 1672 1673 snprintf(hba->work_q_name, sizeof(hba->work_q_name), 1674 "stex_wq_%d", host->host_no); 1675 hba->work_q = create_singlethread_workqueue(hba->work_q_name); 1676 if (!hba->work_q) { 1677 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n", 1678 pci_name(pdev)); 1679 err = -ENOMEM; 1680 goto out_ccb_free; 1681 } 1682 INIT_WORK(&hba->reset_work, stex_reset_work); 1683 1684 err = stex_request_irq(hba); 1685 if (err) { 1686 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n", 1687 pci_name(pdev)); 1688 goto out_free_wq; 1689 } 1690 1691 err = stex_handshake(hba); 1692 if (err) 1693 goto out_free_irq; 1694 1695 pci_set_drvdata(pdev, hba); 1696 1697 err = scsi_add_host(host, &pdev->dev); 1698 if (err) { 1699 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n", 1700 pci_name(pdev)); 1701 goto out_free_irq; 1702 } 1703 1704 scsi_scan_host(host); 1705 1706 return 0; 1707 1708 out_free_irq: 1709 stex_free_irq(hba); 1710 out_free_wq: 1711 destroy_workqueue(hba->work_q); 1712 out_ccb_free: 1713 kfree(hba->ccb); 1714 out_pci_free: 1715 dma_free_coherent(&pdev->dev, hba->dma_size, 1716 hba->dma_mem, hba->dma_handle); 1717 out_iounmap: 1718 iounmap(hba->mmio_base); 1719 out_release_regions: 1720 pci_release_regions(pdev); 1721 out_scsi_host_put: 1722 scsi_host_put(host); 1723 out_disable: 1724 pci_disable_device(pdev); 1725 1726 return err; 1727 } 1728 1729 static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic) 1730 { 1731 struct req_msg *req; 1732 struct st_msg_header *msg_h; 1733 unsigned long flags; 1734 unsigned long before; 1735 u16 tag = 0; 1736 1737 spin_lock_irqsave(hba->host->host_lock, flags); 1738 1739 if (hba->cardtype == st_yel && hba->supports_pm == 1) 1740 { 1741 if(st_sleep_mic == ST_NOTHANDLED) 1742 { 1743 spin_unlock_irqrestore(hba->host->host_lock, flags); 1744 return; 1745 } 1746 } 1747 req = hba->alloc_rq(hba); 1748 if (hba->cardtype == st_yel) { 1749 msg_h = (struct st_msg_header *)req - 1; 1750 memset(msg_h, 0, hba->rq_size); 1751 } else 1752 memset(req, 0, hba->rq_size); 1753 1754 if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel) 1755 && st_sleep_mic == ST_IGNORED) { 1756 req->cdb[0] = MGT_CMD; 1757 req->cdb[1] = MGT_CMD_SIGNATURE; 1758 req->cdb[2] = CTLR_CONFIG_CMD; 1759 req->cdb[3] = CTLR_SHUTDOWN; 1760 } else if (hba->cardtype == st_yel && st_sleep_mic != ST_IGNORED) { 1761 req->cdb[0] = MGT_CMD; 1762 req->cdb[1] = MGT_CMD_SIGNATURE; 1763 req->cdb[2] = CTLR_CONFIG_CMD; 1764 req->cdb[3] = PMIC_SHUTDOWN; 1765 req->cdb[4] = st_sleep_mic; 1766 } else { 1767 req->cdb[0] = CONTROLLER_CMD; 1768 req->cdb[1] = CTLR_POWER_STATE_CHANGE; 1769 req->cdb[2] = CTLR_POWER_SAVING; 1770 } 1771 1772 hba->ccb[tag].cmd = NULL; 1773 hba->ccb[tag].sg_count = 0; 1774 hba->ccb[tag].sense_bufflen = 0; 1775 hba->ccb[tag].sense_buffer = NULL; 1776 hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE; 1777 1778 hba->send(hba, req, tag); 1779 spin_unlock_irqrestore(hba->host->host_lock, flags); 1780 1781 before = jiffies; 1782 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) { 1783 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { 1784 hba->ccb[tag].req_type = 0; 1785 hba->mu_status = MU_STATE_STOP; 1786 return; 1787 } 1788 msleep(1); 1789 } 1790 hba->mu_status = MU_STATE_STOP; 1791 } 1792 1793 static void stex_hba_free(struct st_hba *hba) 1794 { 1795 stex_free_irq(hba); 1796 1797 destroy_workqueue(hba->work_q); 1798 1799 iounmap(hba->mmio_base); 1800 1801 pci_release_regions(hba->pdev); 1802 1803 kfree(hba->ccb); 1804 1805 dma_free_coherent(&hba->pdev->dev, hba->dma_size, 1806 hba->dma_mem, hba->dma_handle); 1807 } 1808 1809 static void stex_remove(struct pci_dev *pdev) 1810 { 1811 struct st_hba *hba = pci_get_drvdata(pdev); 1812 1813 hba->mu_status = MU_STATE_NOCONNECT; 1814 return_abnormal_state(hba, DID_NO_CONNECT); 1815 scsi_remove_host(hba->host); 1816 1817 scsi_block_requests(hba->host); 1818 1819 stex_hba_free(hba); 1820 1821 scsi_host_put(hba->host); 1822 1823 pci_disable_device(pdev); 1824 } 1825 1826 static void stex_shutdown(struct pci_dev *pdev) 1827 { 1828 struct st_hba *hba = pci_get_drvdata(pdev); 1829 1830 if (hba->supports_pm == 0) 1831 stex_hba_stop(hba, ST_IGNORED); 1832 else 1833 stex_hba_stop(hba, ST_S5); 1834 } 1835 1836 static int stex_choice_sleep_mic(pm_message_t state) 1837 { 1838 switch (state.event) { 1839 case PM_EVENT_SUSPEND: 1840 return ST_S3; 1841 case PM_EVENT_HIBERNATE: 1842 return ST_S4; 1843 default: 1844 return ST_NOTHANDLED; 1845 } 1846 } 1847 1848 static int stex_suspend(struct pci_dev *pdev, pm_message_t state) 1849 { 1850 struct st_hba *hba = pci_get_drvdata(pdev); 1851 1852 if (hba->cardtype == st_yel && hba->supports_pm == 1) 1853 stex_hba_stop(hba, stex_choice_sleep_mic(state)); 1854 else 1855 stex_hba_stop(hba, ST_IGNORED); 1856 return 0; 1857 } 1858 1859 static int stex_resume(struct pci_dev *pdev) 1860 { 1861 struct st_hba *hba = pci_get_drvdata(pdev); 1862 1863 hba->mu_status = MU_STATE_STARTING; 1864 stex_handshake(hba); 1865 return 0; 1866 } 1867 MODULE_DEVICE_TABLE(pci, stex_pci_tbl); 1868 1869 static struct pci_driver stex_pci_driver = { 1870 .name = DRV_NAME, 1871 .id_table = stex_pci_tbl, 1872 .probe = stex_probe, 1873 .remove = stex_remove, 1874 .shutdown = stex_shutdown, 1875 .suspend = stex_suspend, 1876 .resume = stex_resume, 1877 }; 1878 1879 static int __init stex_init(void) 1880 { 1881 printk(KERN_INFO DRV_NAME 1882 ": Promise SuperTrak EX Driver version: %s\n", 1883 ST_DRIVER_VERSION); 1884 1885 return pci_register_driver(&stex_pci_driver); 1886 } 1887 1888 static void __exit stex_exit(void) 1889 { 1890 pci_unregister_driver(&stex_pci_driver); 1891 } 1892 1893 module_init(stex_init); 1894 module_exit(stex_exit); 1895