1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * driver for Microsemi PQI-based storage controllers 4 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries 5 * Copyright (c) 2016-2018 Microsemi Corporation 6 * Copyright (c) 2016 PMC-Sierra, Inc. 7 * 8 * Questions/Comments/Bugfixes to storagedev@microchip.com 9 * 10 */ 11 12 #include <linux/io-64-nonatomic-lo-hi.h> 13 14 #if !defined(_SMARTPQI_H) 15 #define _SMARTPQI_H 16 17 #include <scsi/scsi_host.h> 18 #include <linux/bsg-lib.h> 19 20 #pragma pack(1) 21 22 #define PQI_DEVICE_SIGNATURE "PQI DREG" 23 24 /* This structure is defined by the PQI specification. */ 25 struct pqi_device_registers { 26 __le64 signature; 27 u8 function_and_status_code; 28 u8 reserved[7]; 29 u8 max_admin_iq_elements; 30 u8 max_admin_oq_elements; 31 u8 admin_iq_element_length; /* in 16-byte units */ 32 u8 admin_oq_element_length; /* in 16-byte units */ 33 __le16 max_reset_timeout; /* in 100-millisecond units */ 34 u8 reserved1[2]; 35 __le32 legacy_intx_status; 36 __le32 legacy_intx_mask_set; 37 __le32 legacy_intx_mask_clear; 38 u8 reserved2[28]; 39 __le32 device_status; 40 u8 reserved3[4]; 41 __le64 admin_iq_pi_offset; 42 __le64 admin_oq_ci_offset; 43 __le64 admin_iq_element_array_addr; 44 __le64 admin_oq_element_array_addr; 45 __le64 admin_iq_ci_addr; 46 __le64 admin_oq_pi_addr; 47 u8 admin_iq_num_elements; 48 u8 admin_oq_num_elements; 49 __le16 admin_queue_int_msg_num; 50 u8 reserved4[4]; 51 __le32 device_error; 52 u8 reserved5[4]; 53 __le64 error_details; 54 __le32 device_reset; 55 __le32 power_action; 56 u8 reserved6[104]; 57 }; 58 59 /* 60 * controller registers 61 * 62 * These are defined by the Microsemi implementation. 63 * 64 * Some registers (those named sis_*) are only used when in 65 * legacy SIS mode before we transition the controller into 66 * PQI mode. There are a number of other SIS mode registers, 67 * but we don't use them, so only the SIS registers that we 68 * care about are defined here. The offsets mentioned in the 69 * comments are the offsets from the PCIe BAR 0. 70 */ 71 struct pqi_ctrl_registers { 72 u8 reserved[0x20]; 73 __le32 sis_host_to_ctrl_doorbell; /* 20h */ 74 u8 reserved1[0x34 - (0x20 + sizeof(__le32))]; 75 __le32 sis_interrupt_mask; /* 34h */ 76 u8 reserved2[0x9c - (0x34 + sizeof(__le32))]; 77 __le32 sis_ctrl_to_host_doorbell; /* 9Ch */ 78 u8 reserved3[0xa0 - (0x9c + sizeof(__le32))]; 79 __le32 sis_ctrl_to_host_doorbell_clear; /* A0h */ 80 u8 reserved4[0xb0 - (0xa0 + sizeof(__le32))]; 81 __le32 sis_driver_scratch; /* B0h */ 82 u8 reserved5[0xbc - (0xb0 + sizeof(__le32))]; 83 __le32 sis_firmware_status; /* BCh */ 84 u8 reserved6[0x1000 - (0xbc + sizeof(__le32))]; 85 __le32 sis_mailbox[8]; /* 1000h */ 86 u8 reserved7[0x4000 - (0x1000 + (sizeof(__le32) * 8))]; 87 /* 88 * The PQI spec states that the PQI registers should be at 89 * offset 0 from the PCIe BAR 0. However, we can't map 90 * them at offset 0 because that would break compatibility 91 * with the SIS registers. So we map them at offset 4000h. 92 */ 93 struct pqi_device_registers pqi_registers; /* 4000h */ 94 }; 95 96 #if ((HZ) < 1000) 97 #define PQI_HZ 1000 98 #else 99 #define PQI_HZ (HZ) 100 #endif 101 102 #define PQI_DEVICE_REGISTERS_OFFSET 0x4000 103 104 enum pqi_io_path { 105 RAID_PATH = 0, 106 AIO_PATH = 1 107 }; 108 109 enum pqi_irq_mode { 110 IRQ_MODE_NONE, 111 IRQ_MODE_INTX, 112 IRQ_MODE_MSIX 113 }; 114 115 struct pqi_sg_descriptor { 116 __le64 address; 117 __le32 length; 118 __le32 flags; 119 }; 120 121 /* manifest constants for the flags field of pqi_sg_descriptor */ 122 #define CISS_SG_LAST 0x40000000 123 #define CISS_SG_CHAIN 0x80000000 124 125 struct pqi_iu_header { 126 u8 iu_type; 127 u8 reserved; 128 __le16 iu_length; /* in bytes - does not include the length */ 129 /* of this header */ 130 __le16 response_queue_id; /* specifies the OQ where the */ 131 /* response IU is to be delivered */ 132 u8 work_area[2]; /* reserved for driver use */ 133 }; 134 135 /* 136 * According to the PQI spec, the IU header is only the first 4 bytes of our 137 * pqi_iu_header structure. 138 */ 139 #define PQI_REQUEST_HEADER_LENGTH 4 140 141 struct pqi_general_admin_request { 142 struct pqi_iu_header header; 143 __le16 request_id; 144 u8 function_code; 145 union { 146 struct { 147 u8 reserved[33]; 148 __le32 buffer_length; 149 struct pqi_sg_descriptor sg_descriptor; 150 } report_device_capability; 151 152 struct { 153 u8 reserved; 154 __le16 queue_id; 155 u8 reserved1[2]; 156 __le64 element_array_addr; 157 __le64 ci_addr; 158 __le16 num_elements; 159 __le16 element_length; 160 u8 queue_protocol; 161 u8 reserved2[23]; 162 __le32 vendor_specific; 163 } create_operational_iq; 164 165 struct { 166 u8 reserved; 167 __le16 queue_id; 168 u8 reserved1[2]; 169 __le64 element_array_addr; 170 __le64 pi_addr; 171 __le16 num_elements; 172 __le16 element_length; 173 u8 queue_protocol; 174 u8 reserved2[3]; 175 __le16 int_msg_num; 176 __le16 coalescing_count; 177 __le32 min_coalescing_time; 178 __le32 max_coalescing_time; 179 u8 reserved3[8]; 180 __le32 vendor_specific; 181 } create_operational_oq; 182 183 struct { 184 u8 reserved; 185 __le16 queue_id; 186 u8 reserved1[50]; 187 } delete_operational_queue; 188 189 struct { 190 u8 reserved; 191 __le16 queue_id; 192 u8 reserved1[46]; 193 __le32 vendor_specific; 194 } change_operational_iq_properties; 195 196 } data; 197 }; 198 199 struct pqi_general_admin_response { 200 struct pqi_iu_header header; 201 __le16 request_id; 202 u8 function_code; 203 u8 status; 204 union { 205 struct { 206 u8 status_descriptor[4]; 207 __le64 iq_pi_offset; 208 u8 reserved[40]; 209 } create_operational_iq; 210 211 struct { 212 u8 status_descriptor[4]; 213 __le64 oq_ci_offset; 214 u8 reserved[40]; 215 } create_operational_oq; 216 } data; 217 }; 218 219 struct pqi_iu_layer_descriptor { 220 u8 inbound_spanning_supported : 1; 221 u8 reserved : 7; 222 u8 reserved1[5]; 223 __le16 max_inbound_iu_length; 224 u8 outbound_spanning_supported : 1; 225 u8 reserved2 : 7; 226 u8 reserved3[5]; 227 __le16 max_outbound_iu_length; 228 }; 229 230 struct pqi_device_capability { 231 __le16 data_length; 232 u8 reserved[6]; 233 u8 iq_arbitration_priority_support_bitmask; 234 u8 maximum_aw_a; 235 u8 maximum_aw_b; 236 u8 maximum_aw_c; 237 u8 max_arbitration_burst : 3; 238 u8 reserved1 : 4; 239 u8 iqa : 1; 240 u8 reserved2[2]; 241 u8 iq_freeze : 1; 242 u8 reserved3 : 7; 243 __le16 max_inbound_queues; 244 __le16 max_elements_per_iq; 245 u8 reserved4[4]; 246 __le16 max_iq_element_length; 247 __le16 min_iq_element_length; 248 u8 reserved5[2]; 249 __le16 max_outbound_queues; 250 __le16 max_elements_per_oq; 251 __le16 intr_coalescing_time_granularity; 252 __le16 max_oq_element_length; 253 __le16 min_oq_element_length; 254 u8 reserved6[24]; 255 struct pqi_iu_layer_descriptor iu_layer_descriptors[32]; 256 }; 257 258 #define PQI_MAX_EMBEDDED_SG_DESCRIPTORS 4 259 260 struct pqi_raid_path_request { 261 struct pqi_iu_header header; 262 __le16 request_id; 263 __le16 nexus_id; 264 __le32 buffer_length; 265 u8 lun_number[8]; 266 __le16 protocol_specific; 267 u8 data_direction : 2; 268 u8 partial : 1; 269 u8 reserved1 : 4; 270 u8 fence : 1; 271 __le16 error_index; 272 u8 reserved2; 273 u8 task_attribute : 3; 274 u8 command_priority : 4; 275 u8 reserved3 : 1; 276 u8 reserved4 : 2; 277 u8 additional_cdb_bytes_usage : 3; 278 u8 reserved5 : 3; 279 u8 cdb[32]; 280 struct pqi_sg_descriptor 281 sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS]; 282 }; 283 284 struct pqi_aio_path_request { 285 struct pqi_iu_header header; 286 __le16 request_id; 287 u8 reserved1[2]; 288 __le32 nexus_id; 289 __le32 buffer_length; 290 u8 data_direction : 2; 291 u8 partial : 1; 292 u8 memory_type : 1; 293 u8 fence : 1; 294 u8 encryption_enable : 1; 295 u8 reserved2 : 2; 296 u8 task_attribute : 3; 297 u8 command_priority : 4; 298 u8 reserved3 : 1; 299 __le16 data_encryption_key_index; 300 __le32 encrypt_tweak_lower; 301 __le32 encrypt_tweak_upper; 302 u8 cdb[16]; 303 __le16 error_index; 304 u8 num_sg_descriptors; 305 u8 cdb_length; 306 u8 lun_number[8]; 307 u8 reserved4[4]; 308 struct pqi_sg_descriptor 309 sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS]; 310 }; 311 312 struct pqi_io_response { 313 struct pqi_iu_header header; 314 __le16 request_id; 315 __le16 error_index; 316 u8 reserved2[4]; 317 }; 318 319 struct pqi_general_management_request { 320 struct pqi_iu_header header; 321 __le16 request_id; 322 union { 323 struct { 324 u8 reserved[2]; 325 __le32 buffer_length; 326 struct pqi_sg_descriptor sg_descriptors[3]; 327 } report_event_configuration; 328 329 struct { 330 __le16 global_event_oq_id; 331 __le32 buffer_length; 332 struct pqi_sg_descriptor sg_descriptors[3]; 333 } set_event_configuration; 334 } data; 335 }; 336 337 struct pqi_event_descriptor { 338 u8 event_type; 339 u8 reserved; 340 __le16 oq_id; 341 }; 342 343 struct pqi_event_config { 344 u8 reserved[2]; 345 u8 num_event_descriptors; 346 u8 reserved1; 347 struct pqi_event_descriptor descriptors[1]; 348 }; 349 350 #define PQI_MAX_EVENT_DESCRIPTORS 255 351 352 #define PQI_EVENT_OFA_MEMORY_ALLOCATION 0x0 353 #define PQI_EVENT_OFA_QUIESCE 0x1 354 #define PQI_EVENT_OFA_CANCELLED 0x2 355 356 struct pqi_event_response { 357 struct pqi_iu_header header; 358 u8 event_type; 359 u8 reserved2 : 7; 360 u8 request_acknowlege : 1; 361 __le16 event_id; 362 __le32 additional_event_id; 363 union { 364 struct { 365 __le32 bytes_requested; 366 u8 reserved[12]; 367 } ofa_memory_allocation; 368 369 struct { 370 __le16 reason; /* reason for cancellation */ 371 u8 reserved[14]; 372 } ofa_cancelled; 373 } data; 374 }; 375 376 struct pqi_event_acknowledge_request { 377 struct pqi_iu_header header; 378 u8 event_type; 379 u8 reserved2; 380 __le16 event_id; 381 __le32 additional_event_id; 382 }; 383 384 struct pqi_task_management_request { 385 struct pqi_iu_header header; 386 __le16 request_id; 387 __le16 nexus_id; 388 u8 reserved[4]; 389 u8 lun_number[8]; 390 __le16 protocol_specific; 391 __le16 outbound_queue_id_to_manage; 392 __le16 request_id_to_manage; 393 u8 task_management_function; 394 u8 reserved2 : 7; 395 u8 fence : 1; 396 }; 397 398 #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8 399 400 struct pqi_task_management_response { 401 struct pqi_iu_header header; 402 __le16 request_id; 403 __le16 nexus_id; 404 u8 additional_response_info[3]; 405 u8 response_code; 406 }; 407 408 struct pqi_vendor_general_request { 409 struct pqi_iu_header header; 410 __le16 request_id; 411 __le16 function_code; 412 union { 413 struct { 414 __le16 first_section; 415 __le16 last_section; 416 u8 reserved[48]; 417 } config_table_update; 418 419 struct { 420 __le64 buffer_address; 421 __le32 buffer_length; 422 u8 reserved[40]; 423 } ofa_memory_allocation; 424 } data; 425 }; 426 427 struct pqi_vendor_general_response { 428 struct pqi_iu_header header; 429 __le16 request_id; 430 __le16 function_code; 431 __le16 status; 432 u8 reserved[2]; 433 }; 434 435 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0 436 #define PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE 1 437 438 #define PQI_OFA_VERSION 1 439 #define PQI_OFA_SIGNATURE "OFA_QRM" 440 #define PQI_OFA_MAX_SG_DESCRIPTORS 64 441 442 #define PQI_OFA_MEMORY_DESCRIPTOR_LENGTH \ 443 (offsetof(struct pqi_ofa_memory, sg_descriptor) + \ 444 (PQI_OFA_MAX_SG_DESCRIPTORS * sizeof(struct pqi_sg_descriptor))) 445 446 struct pqi_ofa_memory { 447 __le64 signature; /* "OFA_QRM" */ 448 __le16 version; /* version of this struct(1 = 1st version) */ 449 u8 reserved[62]; 450 __le32 bytes_allocated; /* total allocated memory in bytes */ 451 __le16 num_memory_descriptors; 452 u8 reserved1[2]; 453 struct pqi_sg_descriptor sg_descriptor[1]; 454 }; 455 456 struct pqi_aio_error_info { 457 u8 status; 458 u8 service_response; 459 u8 data_present; 460 u8 reserved; 461 __le32 residual_count; 462 __le16 data_length; 463 __le16 reserved1; 464 u8 data[256]; 465 }; 466 467 struct pqi_raid_error_info { 468 u8 data_in_result; 469 u8 data_out_result; 470 u8 reserved[3]; 471 u8 status; 472 __le16 status_qualifier; 473 __le16 sense_data_length; 474 __le16 response_data_length; 475 __le32 data_in_transferred; 476 __le32 data_out_transferred; 477 u8 data[256]; 478 }; 479 480 #define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13 481 #define PQI_REQUEST_IU_RAID_PATH_IO 0x14 482 #define PQI_REQUEST_IU_AIO_PATH_IO 0x15 483 #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60 484 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72 485 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73 486 #define PQI_REQUEST_IU_VENDOR_GENERAL 0x75 487 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 488 489 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 490 #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93 491 #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0 492 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0 493 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1 494 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2 495 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3 496 #define PQI_RESPONSE_IU_AIO_PATH_DISABLED 0xf4 497 #define PQI_RESPONSE_IU_VENDOR_EVENT 0xf5 498 #define PQI_RESPONSE_IU_VENDOR_GENERAL 0xf7 499 500 #define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY 0x0 501 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ 0x10 502 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ 0x11 503 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ 0x12 504 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ 0x13 505 #define PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY 0x14 506 507 #define PQI_GENERAL_ADMIN_STATUS_SUCCESS 0x0 508 509 #define PQI_IQ_PROPERTY_IS_AIO_QUEUE 0x1 510 511 #define PQI_GENERAL_ADMIN_IU_LENGTH 0x3c 512 #define PQI_PROTOCOL_SOP 0x0 513 514 #define PQI_DATA_IN_OUT_GOOD 0x0 515 #define PQI_DATA_IN_OUT_UNDERFLOW 0x1 516 #define PQI_DATA_IN_OUT_BUFFER_ERROR 0x40 517 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW 0x41 518 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42 519 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43 520 #define PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60 521 #define PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61 522 #define PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62 523 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED 0x63 524 #define PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64 525 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65 526 #define PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66 527 #define PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67 528 #define PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x6F 529 #define PQI_DATA_IN_OUT_ERROR 0xf0 530 #define PQI_DATA_IN_OUT_PROTOCOL_ERROR 0xf1 531 #define PQI_DATA_IN_OUT_HARDWARE_ERROR 0xf2 532 #define PQI_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3 533 #define PQI_DATA_IN_OUT_ABORTED 0xf4 534 #define PQI_DATA_IN_OUT_TIMEOUT 0xf5 535 536 #define CISS_CMD_STATUS_SUCCESS 0x0 537 #define CISS_CMD_STATUS_TARGET_STATUS 0x1 538 #define CISS_CMD_STATUS_DATA_UNDERRUN 0x2 539 #define CISS_CMD_STATUS_DATA_OVERRUN 0x3 540 #define CISS_CMD_STATUS_INVALID 0x4 541 #define CISS_CMD_STATUS_PROTOCOL_ERROR 0x5 542 #define CISS_CMD_STATUS_HARDWARE_ERROR 0x6 543 #define CISS_CMD_STATUS_CONNECTION_LOST 0x7 544 #define CISS_CMD_STATUS_ABORTED 0x8 545 #define CISS_CMD_STATUS_ABORT_FAILED 0x9 546 #define CISS_CMD_STATUS_UNSOLICITED_ABORT 0xa 547 #define CISS_CMD_STATUS_TIMEOUT 0xb 548 #define CISS_CMD_STATUS_UNABORTABLE 0xc 549 #define CISS_CMD_STATUS_TMF 0xd 550 #define CISS_CMD_STATUS_AIO_DISABLED 0xe 551 552 #define PQI_CMD_STATUS_ABORTED CISS_CMD_STATUS_ABORTED 553 554 #define PQI_NUM_EVENT_QUEUE_ELEMENTS 32 555 #define PQI_EVENT_OQ_ELEMENT_LENGTH sizeof(struct pqi_event_response) 556 557 #define PQI_EVENT_TYPE_HOTPLUG 0x1 558 #define PQI_EVENT_TYPE_HARDWARE 0x2 559 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4 560 #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5 561 #define PQI_EVENT_TYPE_OFA 0xfb 562 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd 563 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe 564 565 #pragma pack() 566 567 #define PQI_ERROR_BUFFER_ELEMENT_LENGTH \ 568 sizeof(struct pqi_raid_error_info) 569 570 /* these values are based on our implementation */ 571 #define PQI_ADMIN_IQ_NUM_ELEMENTS 8 572 #define PQI_ADMIN_OQ_NUM_ELEMENTS 20 573 #define PQI_ADMIN_IQ_ELEMENT_LENGTH 64 574 #define PQI_ADMIN_OQ_ELEMENT_LENGTH 64 575 576 #define PQI_OPERATIONAL_IQ_ELEMENT_LENGTH 128 577 #define PQI_OPERATIONAL_OQ_ELEMENT_LENGTH 16 578 579 #define PQI_MIN_MSIX_VECTORS 1 580 #define PQI_MAX_MSIX_VECTORS 64 581 582 /* these values are defined by the PQI spec */ 583 #define PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE 255 584 #define PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE 65535 585 #define PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT 64 586 #define PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT 16 587 #define PQI_ADMIN_INDEX_ALIGNMENT 64 588 #define PQI_OPERATIONAL_INDEX_ALIGNMENT 4 589 590 #define PQI_MIN_OPERATIONAL_QUEUE_ID 1 591 #define PQI_MAX_OPERATIONAL_QUEUE_ID 65535 592 593 #define PQI_AIO_SERV_RESPONSE_COMPLETE 0 594 #define PQI_AIO_SERV_RESPONSE_FAILURE 1 595 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2 596 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3 597 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4 598 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5 599 600 #define PQI_AIO_STATUS_IO_ERROR 0x1 601 #define PQI_AIO_STATUS_IO_ABORTED 0x2 602 #define PQI_AIO_STATUS_NO_PATH_TO_DEVICE 0x3 603 #define PQI_AIO_STATUS_INVALID_DEVICE 0x4 604 #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe 605 #define PQI_AIO_STATUS_UNDERRUN 0x51 606 #define PQI_AIO_STATUS_OVERRUN 0x75 607 608 typedef u32 pqi_index_t; 609 610 /* SOP data direction flags */ 611 #define SOP_NO_DIRECTION_FLAG 0 612 #define SOP_WRITE_FLAG 1 /* host writes data to Data-Out */ 613 /* buffer */ 614 #define SOP_READ_FLAG 2 /* host receives data from Data-In */ 615 /* buffer */ 616 #define SOP_BIDIRECTIONAL 3 /* data is transferred from the */ 617 /* Data-Out buffer and data is */ 618 /* transferred to the Data-In buffer */ 619 620 #define SOP_TASK_ATTRIBUTE_SIMPLE 0 621 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1 622 #define SOP_TASK_ATTRIBUTE_ORDERED 2 623 #define SOP_TASK_ATTRIBUTE_ACA 4 624 625 #define SOP_TMF_COMPLETE 0x0 626 #define SOP_TMF_REJECTED 0x4 627 #define SOP_TMF_FUNCTION_SUCCEEDED 0x8 628 629 /* additional CDB bytes usage field codes */ 630 #define SOP_ADDITIONAL_CDB_BYTES_0 0 /* 16-byte CDB */ 631 #define SOP_ADDITIONAL_CDB_BYTES_4 1 /* 20-byte CDB */ 632 #define SOP_ADDITIONAL_CDB_BYTES_8 2 /* 24-byte CDB */ 633 #define SOP_ADDITIONAL_CDB_BYTES_12 3 /* 28-byte CDB */ 634 #define SOP_ADDITIONAL_CDB_BYTES_16 4 /* 32-byte CDB */ 635 636 /* 637 * The purpose of this structure is to obtain proper alignment of objects in 638 * an admin queue pair. 639 */ 640 struct pqi_admin_queues_aligned { 641 __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT) 642 u8 iq_element_array[PQI_ADMIN_IQ_ELEMENT_LENGTH] 643 [PQI_ADMIN_IQ_NUM_ELEMENTS]; 644 __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT) 645 u8 oq_element_array[PQI_ADMIN_OQ_ELEMENT_LENGTH] 646 [PQI_ADMIN_OQ_NUM_ELEMENTS]; 647 __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t iq_ci; 648 __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t oq_pi; 649 }; 650 651 struct pqi_admin_queues { 652 void *iq_element_array; 653 void *oq_element_array; 654 pqi_index_t *iq_ci; 655 pqi_index_t __iomem *oq_pi; 656 dma_addr_t iq_element_array_bus_addr; 657 dma_addr_t oq_element_array_bus_addr; 658 dma_addr_t iq_ci_bus_addr; 659 dma_addr_t oq_pi_bus_addr; 660 __le32 __iomem *iq_pi; 661 pqi_index_t iq_pi_copy; 662 __le32 __iomem *oq_ci; 663 pqi_index_t oq_ci_copy; 664 struct task_struct *task; 665 u16 int_msg_num; 666 }; 667 668 struct pqi_queue_group { 669 struct pqi_ctrl_info *ctrl_info; /* backpointer */ 670 u16 iq_id[2]; 671 u16 oq_id; 672 u16 int_msg_num; 673 void *iq_element_array[2]; 674 void *oq_element_array; 675 dma_addr_t iq_element_array_bus_addr[2]; 676 dma_addr_t oq_element_array_bus_addr; 677 __le32 __iomem *iq_pi[2]; 678 pqi_index_t iq_pi_copy[2]; 679 pqi_index_t __iomem *iq_ci[2]; 680 pqi_index_t __iomem *oq_pi; 681 dma_addr_t iq_ci_bus_addr[2]; 682 dma_addr_t oq_pi_bus_addr; 683 __le32 __iomem *oq_ci; 684 pqi_index_t oq_ci_copy; 685 spinlock_t submit_lock[2]; /* protect submission queue */ 686 struct list_head request_list[2]; 687 }; 688 689 struct pqi_event_queue { 690 u16 oq_id; 691 u16 int_msg_num; 692 void *oq_element_array; 693 pqi_index_t __iomem *oq_pi; 694 dma_addr_t oq_element_array_bus_addr; 695 dma_addr_t oq_pi_bus_addr; 696 __le32 __iomem *oq_ci; 697 pqi_index_t oq_ci_copy; 698 }; 699 700 #define PQI_DEFAULT_QUEUE_GROUP 0 701 #define PQI_MAX_QUEUE_GROUPS PQI_MAX_MSIX_VECTORS 702 703 struct pqi_encryption_info { 704 u16 data_encryption_key_index; 705 u32 encrypt_tweak_lower; 706 u32 encrypt_tweak_upper; 707 }; 708 709 #pragma pack(1) 710 711 #define PQI_CONFIG_TABLE_SIGNATURE "CFGTABLE" 712 #define PQI_CONFIG_TABLE_MAX_LENGTH ((u16)~0) 713 714 /* configuration table section IDs */ 715 #define PQI_CONFIG_TABLE_ALL_SECTIONS (-1) 716 #define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO 0 717 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES 1 718 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA 2 719 #define PQI_CONFIG_TABLE_SECTION_DEBUG 3 720 #define PQI_CONFIG_TABLE_SECTION_HEARTBEAT 4 721 #define PQI_CONFIG_TABLE_SECTION_SOFT_RESET 5 722 723 struct pqi_config_table { 724 u8 signature[8]; /* "CFGTABLE" */ 725 __le32 first_section_offset; /* offset in bytes from the base */ 726 /* address of this table to the */ 727 /* first section */ 728 }; 729 730 struct pqi_config_table_section_header { 731 __le16 section_id; /* as defined by the */ 732 /* PQI_CONFIG_TABLE_SECTION_* */ 733 /* manifest constants above */ 734 __le16 next_section_offset; /* offset in bytes from base */ 735 /* address of the table of the */ 736 /* next section or 0 if last entry */ 737 }; 738 739 struct pqi_config_table_general_info { 740 struct pqi_config_table_section_header header; 741 __le32 section_length; /* size of this section in bytes */ 742 /* including the section header */ 743 __le32 max_outstanding_requests; /* max. outstanding */ 744 /* commands supported by */ 745 /* the controller */ 746 __le32 max_sg_size; /* max. transfer size of a single */ 747 /* command */ 748 __le32 max_sg_per_request; /* max. number of scatter-gather */ 749 /* entries supported in a single */ 750 /* command */ 751 }; 752 753 struct pqi_config_table_firmware_features { 754 struct pqi_config_table_section_header header; 755 __le16 num_elements; 756 u8 features_supported[]; 757 /* u8 features_requested_by_host[]; */ 758 /* u8 features_enabled[]; */ 759 }; 760 761 #define PQI_FIRMWARE_FEATURE_OFA 0 762 #define PQI_FIRMWARE_FEATURE_SMP 1 763 #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE 11 764 765 struct pqi_config_table_debug { 766 struct pqi_config_table_section_header header; 767 __le32 scratchpad; 768 }; 769 770 struct pqi_config_table_heartbeat { 771 struct pqi_config_table_section_header header; 772 __le32 heartbeat_counter; 773 }; 774 775 struct pqi_config_table_soft_reset { 776 struct pqi_config_table_section_header header; 777 u8 soft_reset_status; 778 }; 779 780 #define PQI_SOFT_RESET_INITIATE 0x1 781 #define PQI_SOFT_RESET_ABORT 0x2 782 783 enum pqi_soft_reset_status { 784 RESET_INITIATE_FIRMWARE, 785 RESET_INITIATE_DRIVER, 786 RESET_ABORT, 787 RESET_NORESPONSE, 788 RESET_TIMEDOUT 789 }; 790 791 union pqi_reset_register { 792 struct { 793 u32 reset_type : 3; 794 u32 reserved : 2; 795 u32 reset_action : 3; 796 u32 hold_in_pd1 : 1; 797 u32 reserved2 : 23; 798 } bits; 799 u32 all_bits; 800 }; 801 802 #define PQI_RESET_ACTION_RESET 0x1 803 804 #define PQI_RESET_TYPE_NO_RESET 0x0 805 #define PQI_RESET_TYPE_SOFT_RESET 0x1 806 #define PQI_RESET_TYPE_FIRM_RESET 0x2 807 #define PQI_RESET_TYPE_HARD_RESET 0x3 808 809 #define PQI_RESET_ACTION_COMPLETED 0x2 810 811 #define PQI_RESET_POLL_INTERVAL_MSECS 100 812 813 #define PQI_MAX_OUTSTANDING_REQUESTS ((u32)~0) 814 #define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP 32 815 #define PQI_MAX_TRANSFER_SIZE (1024U * 1024U) 816 #define PQI_MAX_TRANSFER_SIZE_KDUMP (512 * 1024U) 817 818 #define RAID_MAP_MAX_ENTRIES 1024 819 820 #define PQI_PHYSICAL_DEVICE_BUS 0 821 #define PQI_RAID_VOLUME_BUS 1 822 #define PQI_HBA_BUS 2 823 #define PQI_EXTERNAL_RAID_VOLUME_BUS 3 824 #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS 825 826 struct report_lun_header { 827 __be32 list_length; 828 u8 extended_response; 829 u8 reserved[3]; 830 }; 831 832 struct report_log_lun_extended_entry { 833 u8 lunid[8]; 834 u8 volume_id[16]; 835 }; 836 837 struct report_log_lun_extended { 838 struct report_lun_header header; 839 struct report_log_lun_extended_entry lun_entries[1]; 840 }; 841 842 struct report_phys_lun_extended_entry { 843 u8 lunid[8]; 844 __be64 wwid; 845 u8 device_type; 846 u8 device_flags; 847 u8 lun_count; /* number of LUNs in a multi-LUN device */ 848 u8 redundant_paths; 849 u32 aio_handle; 850 }; 851 852 /* for device_flags field of struct report_phys_lun_extended_entry */ 853 #define REPORT_PHYS_LUN_DEV_FLAG_AIO_ENABLED 0x8 854 855 struct report_phys_lun_extended { 856 struct report_lun_header header; 857 struct report_phys_lun_extended_entry lun_entries[1]; 858 }; 859 860 struct raid_map_disk_data { 861 u32 aio_handle; 862 u8 xor_mult[2]; 863 u8 reserved[2]; 864 }; 865 866 /* constants for flags field of RAID map */ 867 #define RAID_MAP_ENCRYPTION_ENABLED 0x1 868 869 struct raid_map { 870 __le32 structure_size; /* size of entire structure in bytes */ 871 __le32 volume_blk_size; /* bytes / block in the volume */ 872 __le64 volume_blk_cnt; /* logical blocks on the volume */ 873 u8 phys_blk_shift; /* shift factor to convert between */ 874 /* units of logical blocks and */ 875 /* physical disk blocks */ 876 u8 parity_rotation_shift; /* shift factor to convert between */ 877 /* units of logical stripes and */ 878 /* physical stripes */ 879 __le16 strip_size; /* blocks used on each disk / stripe */ 880 __le64 disk_starting_blk; /* first disk block used in volume */ 881 __le64 disk_blk_cnt; /* disk blocks used by volume / disk */ 882 __le16 data_disks_per_row; /* data disk entries / row in the map */ 883 __le16 metadata_disks_per_row; /* mirror/parity disk entries / row */ 884 /* in the map */ 885 __le16 row_cnt; /* rows in each layout map */ 886 __le16 layout_map_count; /* layout maps (1 map per */ 887 /* mirror parity group) */ 888 __le16 flags; 889 __le16 data_encryption_key_index; 890 u8 reserved[16]; 891 struct raid_map_disk_data disk_data[RAID_MAP_MAX_ENTRIES]; 892 }; 893 894 #pragma pack() 895 896 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 897 898 struct pqi_scsi_dev { 899 int devtype; /* as reported by INQUIRY commmand */ 900 u8 device_type; /* as reported by */ 901 /* BMIC_IDENTIFY_PHYSICAL_DEVICE */ 902 /* only valid for devtype = TYPE_DISK */ 903 int bus; 904 int target; 905 int lun; 906 u8 scsi3addr[8]; 907 __be64 wwid; 908 u8 volume_id[16]; 909 u8 unique_id[16]; 910 u8 is_physical_device : 1; 911 u8 is_external_raid_device : 1; 912 u8 is_expander_smp_device : 1; 913 u8 target_lun_valid : 1; 914 u8 device_gone : 1; 915 u8 new_device : 1; 916 u8 keep_device : 1; 917 u8 volume_offline : 1; 918 bool aio_enabled; /* only valid for physical disks */ 919 bool in_reset; 920 bool in_remove; 921 bool device_offline; 922 u8 vendor[8]; /* bytes 8-15 of inquiry data */ 923 u8 model[16]; /* bytes 16-31 of inquiry data */ 924 u64 sas_address; 925 u8 raid_level; 926 u16 queue_depth; /* max. queue_depth for this device */ 927 u16 advertised_queue_depth; 928 u32 aio_handle; 929 u8 volume_status; 930 u8 active_path_index; 931 u8 path_map; 932 u8 bay; 933 u8 box[8]; 934 u16 phys_connector[8]; 935 bool raid_bypass_configured; /* RAID bypass configured */ 936 bool raid_bypass_enabled; /* RAID bypass enabled */ 937 int offload_to_mirror; /* Send next RAID bypass request */ 938 /* to mirror drive. */ 939 struct raid_map *raid_map; /* RAID bypass map */ 940 941 struct pqi_sas_port *sas_port; 942 struct scsi_device *sdev; 943 944 struct list_head scsi_device_list_entry; 945 struct list_head new_device_list_entry; 946 struct list_head add_list_entry; 947 struct list_head delete_list_entry; 948 949 atomic_t scsi_cmds_outstanding; 950 }; 951 952 /* VPD inquiry pages */ 953 #define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */ 954 #define SCSI_VPD_DEVICE_ID 0x83 /* standard page */ 955 #define CISS_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */ 956 #define CISS_VPD_LV_BYPASS_STATUS 0xc2 /* vendor-specific page */ 957 #define CISS_VPD_LV_STATUS 0xc3 /* vendor-specific page */ 958 #define SCSI_VPD_HEADER_SZ 4 959 #define SCSI_VPD_DEVICE_ID_IDX 8 /* Index of page id in page */ 960 961 #define VPD_PAGE (1 << 8) 962 963 #pragma pack(1) 964 965 /* structure for CISS_VPD_LV_STATUS */ 966 struct ciss_vpd_logical_volume_status { 967 u8 peripheral_info; 968 u8 page_code; 969 u8 reserved; 970 u8 page_length; 971 u8 volume_status; 972 u8 reserved2[3]; 973 __be32 flags; 974 }; 975 976 #pragma pack() 977 978 /* constants for volume_status field of ciss_vpd_logical_volume_status */ 979 #define CISS_LV_OK 0 980 #define CISS_LV_FAILED 1 981 #define CISS_LV_NOT_CONFIGURED 2 982 #define CISS_LV_DEGRADED 3 983 #define CISS_LV_READY_FOR_RECOVERY 4 984 #define CISS_LV_UNDERGOING_RECOVERY 5 985 #define CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED 6 986 #define CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM 7 987 #define CISS_LV_HARDWARE_OVERHEATING 8 988 #define CISS_LV_HARDWARE_HAS_OVERHEATED 9 989 #define CISS_LV_UNDERGOING_EXPANSION 10 990 #define CISS_LV_NOT_AVAILABLE 11 991 #define CISS_LV_QUEUED_FOR_EXPANSION 12 992 #define CISS_LV_DISABLED_SCSI_ID_CONFLICT 13 993 #define CISS_LV_EJECTED 14 994 #define CISS_LV_UNDERGOING_ERASE 15 995 /* state 16 not used */ 996 #define CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD 17 997 #define CISS_LV_UNDERGOING_RPI 18 998 #define CISS_LV_PENDING_RPI 19 999 #define CISS_LV_ENCRYPTED_NO_KEY 20 1000 /* state 21 not used */ 1001 #define CISS_LV_UNDERGOING_ENCRYPTION 22 1002 #define CISS_LV_UNDERGOING_ENCRYPTION_REKEYING 23 1003 #define CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 24 1004 #define CISS_LV_PENDING_ENCRYPTION 25 1005 #define CISS_LV_PENDING_ENCRYPTION_REKEYING 26 1006 #define CISS_LV_NOT_SUPPORTED 27 1007 #define CISS_LV_STATUS_UNAVAILABLE 255 1008 1009 /* constants for flags field of ciss_vpd_logical_volume_status */ 1010 #define CISS_LV_FLAGS_NO_HOST_IO 0x1 /* volume not available for */ 1011 /* host I/O */ 1012 1013 /* for SAS hosts and SAS expanders */ 1014 struct pqi_sas_node { 1015 struct device *parent_dev; 1016 struct list_head port_list_head; 1017 }; 1018 1019 struct pqi_sas_port { 1020 struct list_head port_list_entry; 1021 u64 sas_address; 1022 struct pqi_scsi_dev *device; 1023 struct sas_port *port; 1024 int next_phy_index; 1025 struct list_head phy_list_head; 1026 struct pqi_sas_node *parent_node; 1027 struct sas_rphy *rphy; 1028 }; 1029 1030 struct pqi_sas_phy { 1031 struct list_head phy_list_entry; 1032 struct sas_phy *phy; 1033 struct pqi_sas_port *parent_port; 1034 bool added_to_port; 1035 }; 1036 1037 struct pqi_io_request { 1038 atomic_t refcount; 1039 u16 index; 1040 void (*io_complete_callback)(struct pqi_io_request *io_request, 1041 void *context); 1042 void *context; 1043 u8 raid_bypass : 1; 1044 int status; 1045 struct pqi_queue_group *queue_group; 1046 struct scsi_cmnd *scmd; 1047 void *error_info; 1048 struct pqi_sg_descriptor *sg_chain_buffer; 1049 dma_addr_t sg_chain_buffer_dma_handle; 1050 void *iu; 1051 struct list_head request_list_entry; 1052 }; 1053 1054 #define PQI_NUM_SUPPORTED_EVENTS 7 1055 1056 struct pqi_event { 1057 bool pending; 1058 u8 event_type; 1059 __le16 event_id; 1060 __le32 additional_event_id; 1061 __le32 ofa_bytes_requested; 1062 __le16 ofa_cancel_reason; 1063 }; 1064 1065 #define PQI_RESERVED_IO_SLOTS_LUN_RESET 1 1066 #define PQI_RESERVED_IO_SLOTS_EVENT_ACK PQI_NUM_SUPPORTED_EVENTS 1067 #define PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS 3 1068 #define PQI_RESERVED_IO_SLOTS \ 1069 (PQI_RESERVED_IO_SLOTS_LUN_RESET + PQI_RESERVED_IO_SLOTS_EVENT_ACK + \ 1070 PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS) 1071 1072 struct pqi_ctrl_info { 1073 unsigned int ctrl_id; 1074 struct pci_dev *pci_dev; 1075 char firmware_version[11]; 1076 void __iomem *iomem_base; 1077 struct pqi_ctrl_registers __iomem *registers; 1078 struct pqi_device_registers __iomem *pqi_registers; 1079 u32 max_sg_entries; 1080 u32 config_table_offset; 1081 u32 config_table_length; 1082 u16 max_inbound_queues; 1083 u16 max_elements_per_iq; 1084 u16 max_iq_element_length; 1085 u16 max_outbound_queues; 1086 u16 max_elements_per_oq; 1087 u16 max_oq_element_length; 1088 u32 max_transfer_size; 1089 u32 max_outstanding_requests; 1090 u32 max_io_slots; 1091 unsigned int scsi_ml_can_queue; 1092 unsigned short sg_tablesize; 1093 unsigned int max_sectors; 1094 u32 error_buffer_length; 1095 void *error_buffer; 1096 dma_addr_t error_buffer_dma_handle; 1097 size_t sg_chain_buffer_length; 1098 unsigned int num_queue_groups; 1099 u16 max_hw_queue_index; 1100 u16 num_elements_per_iq; 1101 u16 num_elements_per_oq; 1102 u16 max_inbound_iu_length_per_firmware; 1103 u16 max_inbound_iu_length; 1104 unsigned int max_sg_per_iu; 1105 void *admin_queue_memory_base; 1106 u32 admin_queue_memory_length; 1107 dma_addr_t admin_queue_memory_base_dma_handle; 1108 void *queue_memory_base; 1109 u32 queue_memory_length; 1110 dma_addr_t queue_memory_base_dma_handle; 1111 struct pqi_admin_queues admin_queues; 1112 struct pqi_queue_group queue_groups[PQI_MAX_QUEUE_GROUPS]; 1113 struct pqi_event_queue event_queue; 1114 enum pqi_irq_mode irq_mode; 1115 int max_msix_vectors; 1116 int num_msix_vectors_enabled; 1117 int num_msix_vectors_initialized; 1118 int event_irq; 1119 struct Scsi_Host *scsi_host; 1120 1121 struct mutex scan_mutex; 1122 struct mutex lun_reset_mutex; 1123 struct mutex ofa_mutex; /* serialize ofa */ 1124 bool controller_online; 1125 bool block_requests; 1126 bool in_shutdown; 1127 bool in_ofa; 1128 u8 inbound_spanning_supported : 1; 1129 u8 outbound_spanning_supported : 1; 1130 u8 pqi_mode_enabled : 1; 1131 u8 pqi_reset_quiesce_supported : 1; 1132 u8 soft_reset_handshake_supported : 1; 1133 1134 struct list_head scsi_device_list; 1135 spinlock_t scsi_device_list_lock; 1136 1137 struct delayed_work rescan_work; 1138 struct delayed_work update_time_work; 1139 1140 struct pqi_sas_node *sas_host; 1141 u64 sas_address; 1142 1143 struct pqi_io_request *io_request_pool; 1144 u16 next_io_request_slot; 1145 1146 struct pqi_event events[PQI_NUM_SUPPORTED_EVENTS]; 1147 struct work_struct event_work; 1148 1149 atomic_t num_interrupts; 1150 int previous_num_interrupts; 1151 u32 previous_heartbeat_count; 1152 __le32 __iomem *heartbeat_counter; 1153 u8 __iomem *soft_reset_status; 1154 struct timer_list heartbeat_timer; 1155 struct work_struct ctrl_offline_work; 1156 1157 struct semaphore sync_request_sem; 1158 atomic_t num_busy_threads; 1159 atomic_t num_blocked_threads; 1160 wait_queue_head_t block_requests_wait; 1161 1162 struct list_head raid_bypass_retry_list; 1163 spinlock_t raid_bypass_retry_list_lock; 1164 struct work_struct raid_bypass_retry_work; 1165 1166 struct pqi_ofa_memory *pqi_ofa_mem_virt_addr; 1167 dma_addr_t pqi_ofa_mem_dma_handle; 1168 void **pqi_ofa_chunk_virt_addr; 1169 }; 1170 1171 enum pqi_ctrl_mode { 1172 SIS_MODE = 0, 1173 PQI_MODE 1174 }; 1175 1176 /* 1177 * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands 1178 */ 1179 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 1180 1181 /* CISS commands */ 1182 #define CISS_READ 0xc0 1183 #define CISS_REPORT_LOG 0xc2 /* Report Logical LUNs */ 1184 #define CISS_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 1185 #define CISS_GET_RAID_MAP 0xc8 1186 1187 /* constants for CISS_REPORT_LOG/CISS_REPORT_PHYS commands */ 1188 #define CISS_REPORT_LOG_EXTENDED 0x1 1189 #define CISS_REPORT_PHYS_EXTENDED 0x2 1190 1191 /* BMIC commands */ 1192 #define BMIC_IDENTIFY_CONTROLLER 0x11 1193 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 1194 #define BMIC_READ 0x26 1195 #define BMIC_WRITE 0x27 1196 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 1197 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 1198 #define BMIC_CSMI_PASSTHRU 0x68 1199 #define BMIC_WRITE_HOST_WELLNESS 0xa5 1200 #define BMIC_FLUSH_CACHE 0xc2 1201 #define BMIC_SET_DIAG_OPTIONS 0xf4 1202 #define BMIC_SENSE_DIAG_OPTIONS 0xf5 1203 1204 #define CSMI_CC_SAS_SMP_PASSTHRU 0X17 1205 1206 #define SA_FLUSH_CACHE 0x1 1207 1208 #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xc0) 1209 #define CISS_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3f) 1210 #define CISS_GET_LEVEL_2_TARGET(lunid) ((lunid)[6]) 1211 #define CISS_GET_DRIVE_NUMBER(lunid) \ 1212 (((CISS_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \ 1213 CISS_GET_LEVEL_2_TARGET((lunid))) 1214 1215 #define NO_TIMEOUT ((unsigned long) -1) 1216 1217 #pragma pack(1) 1218 1219 struct bmic_identify_controller { 1220 u8 configured_logical_drive_count; 1221 __le32 configuration_signature; 1222 u8 firmware_version[4]; 1223 u8 reserved[145]; 1224 __le16 extended_logical_unit_count; 1225 u8 reserved1[34]; 1226 __le16 firmware_build_number; 1227 u8 reserved2[100]; 1228 u8 controller_mode; 1229 u8 reserved3[32]; 1230 }; 1231 1232 #define SA_EXPANDER_SMP_DEVICE 0x05 1233 /*SCSI Invalid Device Type for SAS devices*/ 1234 #define PQI_SAS_SCSI_INVALID_DEVTYPE 0xff 1235 1236 struct bmic_identify_physical_device { 1237 u8 scsi_bus; /* SCSI Bus number on controller */ 1238 u8 scsi_id; /* SCSI ID on this bus */ 1239 __le16 block_size; /* sector size in bytes */ 1240 __le32 total_blocks; /* number for sectors on drive */ 1241 __le32 reserved_blocks; /* controller reserved (RIS) */ 1242 u8 model[40]; /* Physical Drive Model */ 1243 u8 serial_number[40]; /* Drive Serial Number */ 1244 u8 firmware_revision[8]; /* drive firmware revision */ 1245 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ 1246 u8 compaq_drive_stamp; /* 0 means drive not stamped */ 1247 u8 last_failure_reason; 1248 u8 flags; 1249 u8 more_flags; 1250 u8 scsi_lun; /* SCSI LUN for phys drive */ 1251 u8 yet_more_flags; 1252 u8 even_more_flags; 1253 __le32 spi_speed_rules; 1254 u8 phys_connector[2]; /* connector number on controller */ 1255 u8 phys_box_on_bus; /* phys enclosure this drive resides */ 1256 u8 phys_bay_in_box; /* phys drv bay this drive resides */ 1257 __le32 rpm; /* drive rotational speed in RPM */ 1258 u8 device_type; /* type of drive */ 1259 u8 sata_version; /* only valid when device_type = */ 1260 /* BMIC_DEVICE_TYPE_SATA */ 1261 __le64 big_total_block_count; 1262 __le64 ris_starting_lba; 1263 __le32 ris_size; 1264 u8 wwid[20]; 1265 u8 controller_phy_map[32]; 1266 __le16 phy_count; 1267 u8 phy_connected_dev_type[256]; 1268 u8 phy_to_drive_bay_num[256]; 1269 __le16 phy_to_attached_dev_index[256]; 1270 u8 box_index; 1271 u8 reserved; 1272 __le16 extra_physical_drive_flags; 1273 u8 negotiated_link_rate[256]; 1274 u8 phy_to_phy_map[256]; 1275 u8 redundant_path_present_map; 1276 u8 redundant_path_failure_map; 1277 u8 active_path_number; 1278 __le16 alternate_paths_phys_connector[8]; 1279 u8 alternate_paths_phys_box_on_port[8]; 1280 u8 multi_lun_device_lun_count; 1281 u8 minimum_good_fw_revision[8]; 1282 u8 unique_inquiry_bytes[20]; 1283 u8 current_temperature_degrees; 1284 u8 temperature_threshold_degrees; 1285 u8 max_temperature_degrees; 1286 u8 logical_blocks_per_phys_block_exp; 1287 __le16 current_queue_depth_limit; 1288 u8 switch_name[10]; 1289 __le16 switch_port; 1290 u8 alternate_paths_switch_name[40]; 1291 u8 alternate_paths_switch_port[8]; 1292 __le16 power_on_hours; 1293 __le16 percent_endurance_used; 1294 u8 drive_authentication; 1295 u8 smart_carrier_authentication; 1296 u8 smart_carrier_app_fw_version; 1297 u8 smart_carrier_bootloader_fw_version; 1298 u8 sanitize_flags; 1299 u8 encryption_key_flags; 1300 u8 encryption_key_name[64]; 1301 __le32 misc_drive_flags; 1302 __le16 dek_index; 1303 __le16 hba_drive_encryption_flags; 1304 __le16 max_overwrite_time; 1305 __le16 max_block_erase_time; 1306 __le16 max_crypto_erase_time; 1307 u8 connector_info[5]; 1308 u8 connector_name[8][8]; 1309 u8 page_83_identifier[16]; 1310 u8 maximum_link_rate[256]; 1311 u8 negotiated_physical_link_rate[256]; 1312 u8 box_connector_name[8]; 1313 u8 padding_to_multiple_of_512[9]; 1314 }; 1315 1316 struct bmic_smp_request { 1317 u8 frame_type; 1318 u8 function; 1319 u8 allocated_response_length; 1320 u8 request_length; 1321 u8 additional_request_bytes[1016]; 1322 }; 1323 1324 struct bmic_smp_response { 1325 u8 frame_type; 1326 u8 function; 1327 u8 function_result; 1328 u8 response_length; 1329 u8 additional_response_bytes[1016]; 1330 }; 1331 1332 struct bmic_csmi_ioctl_header { 1333 __le32 header_length; 1334 u8 signature[8]; 1335 __le32 timeout; 1336 __le32 control_code; 1337 __le32 return_code; 1338 __le32 length; 1339 }; 1340 1341 struct bmic_csmi_smp_passthru { 1342 u8 phy_identifier; 1343 u8 port_identifier; 1344 u8 connection_rate; 1345 u8 reserved; 1346 __be64 destination_sas_address; 1347 __le32 request_length; 1348 struct bmic_smp_request request; 1349 u8 connection_status; 1350 u8 reserved1[3]; 1351 __le32 response_length; 1352 struct bmic_smp_response response; 1353 }; 1354 1355 struct bmic_csmi_smp_passthru_buffer { 1356 struct bmic_csmi_ioctl_header ioctl_header; 1357 struct bmic_csmi_smp_passthru parameters; 1358 }; 1359 1360 struct bmic_flush_cache { 1361 u8 disable_flag; 1362 u8 system_power_action; 1363 u8 ndu_flush; 1364 u8 shutdown_event; 1365 u8 reserved[28]; 1366 }; 1367 1368 /* for shutdown_event member of struct bmic_flush_cache */ 1369 enum bmic_flush_cache_shutdown_event { 1370 NONE_CACHE_FLUSH_ONLY = 0, 1371 SHUTDOWN = 1, 1372 HIBERNATE = 2, 1373 SUSPEND = 3, 1374 RESTART = 4 1375 }; 1376 1377 struct bmic_diag_options { 1378 __le32 options; 1379 }; 1380 1381 #pragma pack() 1382 1383 static inline struct pqi_ctrl_info *shost_to_hba(struct Scsi_Host *shost) 1384 { 1385 void *hostdata = shost_priv(shost); 1386 1387 return *((struct pqi_ctrl_info **)hostdata); 1388 } 1389 1390 static inline bool pqi_ctrl_offline(struct pqi_ctrl_info *ctrl_info) 1391 { 1392 return !ctrl_info->controller_online; 1393 } 1394 1395 static inline void pqi_ctrl_busy(struct pqi_ctrl_info *ctrl_info) 1396 { 1397 atomic_inc(&ctrl_info->num_busy_threads); 1398 } 1399 1400 static inline void pqi_ctrl_unbusy(struct pqi_ctrl_info *ctrl_info) 1401 { 1402 atomic_dec(&ctrl_info->num_busy_threads); 1403 } 1404 1405 static inline bool pqi_ctrl_blocked(struct pqi_ctrl_info *ctrl_info) 1406 { 1407 return ctrl_info->block_requests; 1408 } 1409 1410 void pqi_sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost, 1411 struct sas_rphy *rphy); 1412 1413 int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info); 1414 void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info); 1415 int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node, 1416 struct pqi_scsi_dev *device); 1417 void pqi_remove_sas_device(struct pqi_scsi_dev *device); 1418 struct pqi_scsi_dev *pqi_find_device_by_sas_rphy( 1419 struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy); 1420 void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd); 1421 int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info, 1422 struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length, 1423 struct pqi_raid_error_info *error_info); 1424 1425 extern struct sas_function_template pqi_sas_transport_functions; 1426 1427 #endif /* _SMARTPQI_H */ 1428