1 /* 2 * driver for Microsemi PQI-based storage controllers 3 * Copyright (c) 2016-2017 Microsemi Corporation 4 * Copyright (c) 2016 PMC-Sierra, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more details. 14 * 15 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com 16 * 17 */ 18 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 21 #if !defined(_SMARTPQI_H) 22 #define _SMARTPQI_H 23 24 #pragma pack(1) 25 26 #define PQI_DEVICE_SIGNATURE "PQI DREG" 27 28 /* This structure is defined by the PQI specification. */ 29 struct pqi_device_registers { 30 __le64 signature; 31 u8 function_and_status_code; 32 u8 reserved[7]; 33 u8 max_admin_iq_elements; 34 u8 max_admin_oq_elements; 35 u8 admin_iq_element_length; /* in 16-byte units */ 36 u8 admin_oq_element_length; /* in 16-byte units */ 37 __le16 max_reset_timeout; /* in 100-millisecond units */ 38 u8 reserved1[2]; 39 __le32 legacy_intx_status; 40 __le32 legacy_intx_mask_set; 41 __le32 legacy_intx_mask_clear; 42 u8 reserved2[28]; 43 __le32 device_status; 44 u8 reserved3[4]; 45 __le64 admin_iq_pi_offset; 46 __le64 admin_oq_ci_offset; 47 __le64 admin_iq_element_array_addr; 48 __le64 admin_oq_element_array_addr; 49 __le64 admin_iq_ci_addr; 50 __le64 admin_oq_pi_addr; 51 u8 admin_iq_num_elements; 52 u8 admin_oq_num_elements; 53 __le16 admin_queue_int_msg_num; 54 u8 reserved4[4]; 55 __le32 device_error; 56 u8 reserved5[4]; 57 __le64 error_details; 58 __le32 device_reset; 59 __le32 power_action; 60 u8 reserved6[104]; 61 }; 62 63 /* 64 * controller registers 65 * 66 * These are defined by the Microsemi implementation. 67 * 68 * Some registers (those named sis_*) are only used when in 69 * legacy SIS mode before we transition the controller into 70 * PQI mode. There are a number of other SIS mode registers, 71 * but we don't use them, so only the SIS registers that we 72 * care about are defined here. The offsets mentioned in the 73 * comments are the offsets from the PCIe BAR 0. 74 */ 75 struct pqi_ctrl_registers { 76 u8 reserved[0x20]; 77 __le32 sis_host_to_ctrl_doorbell; /* 20h */ 78 u8 reserved1[0x34 - (0x20 + sizeof(__le32))]; 79 __le32 sis_interrupt_mask; /* 34h */ 80 u8 reserved2[0x9c - (0x34 + sizeof(__le32))]; 81 __le32 sis_ctrl_to_host_doorbell; /* 9Ch */ 82 u8 reserved3[0xa0 - (0x9c + sizeof(__le32))]; 83 __le32 sis_ctrl_to_host_doorbell_clear; /* A0h */ 84 u8 reserved4[0xb0 - (0xa0 + sizeof(__le32))]; 85 __le32 sis_driver_scratch; /* B0h */ 86 u8 reserved5[0xbc - (0xb0 + sizeof(__le32))]; 87 __le32 sis_firmware_status; /* BCh */ 88 u8 reserved6[0x1000 - (0xbc + sizeof(__le32))]; 89 __le32 sis_mailbox[8]; /* 1000h */ 90 u8 reserved7[0x4000 - (0x1000 + (sizeof(__le32) * 8))]; 91 /* 92 * The PQI spec states that the PQI registers should be at 93 * offset 0 from the PCIe BAR 0. However, we can't map 94 * them at offset 0 because that would break compatibility 95 * with the SIS registers. So we map them at offset 4000h. 96 */ 97 struct pqi_device_registers pqi_registers; /* 4000h */ 98 }; 99 100 #define PQI_DEVICE_REGISTERS_OFFSET 0x4000 101 102 enum pqi_io_path { 103 RAID_PATH = 0, 104 AIO_PATH = 1 105 }; 106 107 enum pqi_irq_mode { 108 IRQ_MODE_NONE, 109 IRQ_MODE_INTX, 110 IRQ_MODE_MSIX 111 }; 112 113 struct pqi_sg_descriptor { 114 __le64 address; 115 __le32 length; 116 __le32 flags; 117 }; 118 119 /* manifest constants for the flags field of pqi_sg_descriptor */ 120 #define CISS_SG_LAST 0x40000000 121 #define CISS_SG_CHAIN 0x80000000 122 123 struct pqi_iu_header { 124 u8 iu_type; 125 u8 reserved; 126 __le16 iu_length; /* in bytes - does not include the length */ 127 /* of this header */ 128 __le16 response_queue_id; /* specifies the OQ where the */ 129 /* response IU is to be delivered */ 130 u8 work_area[2]; /* reserved for driver use */ 131 }; 132 133 /* 134 * According to the PQI spec, the IU header is only the first 4 bytes of our 135 * pqi_iu_header structure. 136 */ 137 #define PQI_REQUEST_HEADER_LENGTH 4 138 139 struct pqi_general_admin_request { 140 struct pqi_iu_header header; 141 __le16 request_id; 142 u8 function_code; 143 union { 144 struct { 145 u8 reserved[33]; 146 __le32 buffer_length; 147 struct pqi_sg_descriptor sg_descriptor; 148 } report_device_capability; 149 150 struct { 151 u8 reserved; 152 __le16 queue_id; 153 u8 reserved1[2]; 154 __le64 element_array_addr; 155 __le64 ci_addr; 156 __le16 num_elements; 157 __le16 element_length; 158 u8 queue_protocol; 159 u8 reserved2[23]; 160 __le32 vendor_specific; 161 } create_operational_iq; 162 163 struct { 164 u8 reserved; 165 __le16 queue_id; 166 u8 reserved1[2]; 167 __le64 element_array_addr; 168 __le64 pi_addr; 169 __le16 num_elements; 170 __le16 element_length; 171 u8 queue_protocol; 172 u8 reserved2[3]; 173 __le16 int_msg_num; 174 __le16 coalescing_count; 175 __le32 min_coalescing_time; 176 __le32 max_coalescing_time; 177 u8 reserved3[8]; 178 __le32 vendor_specific; 179 } create_operational_oq; 180 181 struct { 182 u8 reserved; 183 __le16 queue_id; 184 u8 reserved1[50]; 185 } delete_operational_queue; 186 187 struct { 188 u8 reserved; 189 __le16 queue_id; 190 u8 reserved1[46]; 191 __le32 vendor_specific; 192 } change_operational_iq_properties; 193 194 } data; 195 }; 196 197 struct pqi_general_admin_response { 198 struct pqi_iu_header header; 199 __le16 request_id; 200 u8 function_code; 201 u8 status; 202 union { 203 struct { 204 u8 status_descriptor[4]; 205 __le64 iq_pi_offset; 206 u8 reserved[40]; 207 } create_operational_iq; 208 209 struct { 210 u8 status_descriptor[4]; 211 __le64 oq_ci_offset; 212 u8 reserved[40]; 213 } create_operational_oq; 214 } data; 215 }; 216 217 struct pqi_iu_layer_descriptor { 218 u8 inbound_spanning_supported : 1; 219 u8 reserved : 7; 220 u8 reserved1[5]; 221 __le16 max_inbound_iu_length; 222 u8 outbound_spanning_supported : 1; 223 u8 reserved2 : 7; 224 u8 reserved3[5]; 225 __le16 max_outbound_iu_length; 226 }; 227 228 struct pqi_device_capability { 229 __le16 data_length; 230 u8 reserved[6]; 231 u8 iq_arbitration_priority_support_bitmask; 232 u8 maximum_aw_a; 233 u8 maximum_aw_b; 234 u8 maximum_aw_c; 235 u8 max_arbitration_burst : 3; 236 u8 reserved1 : 4; 237 u8 iqa : 1; 238 u8 reserved2[2]; 239 u8 iq_freeze : 1; 240 u8 reserved3 : 7; 241 __le16 max_inbound_queues; 242 __le16 max_elements_per_iq; 243 u8 reserved4[4]; 244 __le16 max_iq_element_length; 245 __le16 min_iq_element_length; 246 u8 reserved5[2]; 247 __le16 max_outbound_queues; 248 __le16 max_elements_per_oq; 249 __le16 intr_coalescing_time_granularity; 250 __le16 max_oq_element_length; 251 __le16 min_oq_element_length; 252 u8 reserved6[24]; 253 struct pqi_iu_layer_descriptor iu_layer_descriptors[32]; 254 }; 255 256 #define PQI_MAX_EMBEDDED_SG_DESCRIPTORS 4 257 258 struct pqi_raid_path_request { 259 struct pqi_iu_header header; 260 __le16 request_id; 261 __le16 nexus_id; 262 __le32 buffer_length; 263 u8 lun_number[8]; 264 __le16 protocol_specific; 265 u8 data_direction : 2; 266 u8 partial : 1; 267 u8 reserved1 : 4; 268 u8 fence : 1; 269 __le16 error_index; 270 u8 reserved2; 271 u8 task_attribute : 3; 272 u8 command_priority : 4; 273 u8 reserved3 : 1; 274 u8 reserved4 : 2; 275 u8 additional_cdb_bytes_usage : 3; 276 u8 reserved5 : 3; 277 u8 cdb[32]; 278 struct pqi_sg_descriptor 279 sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS]; 280 }; 281 282 struct pqi_aio_path_request { 283 struct pqi_iu_header header; 284 __le16 request_id; 285 u8 reserved1[2]; 286 __le32 nexus_id; 287 __le32 buffer_length; 288 u8 data_direction : 2; 289 u8 partial : 1; 290 u8 memory_type : 1; 291 u8 fence : 1; 292 u8 encryption_enable : 1; 293 u8 reserved2 : 2; 294 u8 task_attribute : 3; 295 u8 command_priority : 4; 296 u8 reserved3 : 1; 297 __le16 data_encryption_key_index; 298 __le32 encrypt_tweak_lower; 299 __le32 encrypt_tweak_upper; 300 u8 cdb[16]; 301 __le16 error_index; 302 u8 num_sg_descriptors; 303 u8 cdb_length; 304 u8 lun_number[8]; 305 u8 reserved4[4]; 306 struct pqi_sg_descriptor 307 sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS]; 308 }; 309 310 struct pqi_io_response { 311 struct pqi_iu_header header; 312 __le16 request_id; 313 __le16 error_index; 314 u8 reserved2[4]; 315 }; 316 317 struct pqi_general_management_request { 318 struct pqi_iu_header header; 319 __le16 request_id; 320 union { 321 struct { 322 u8 reserved[2]; 323 __le32 buffer_length; 324 struct pqi_sg_descriptor sg_descriptors[3]; 325 } report_event_configuration; 326 327 struct { 328 __le16 global_event_oq_id; 329 __le32 buffer_length; 330 struct pqi_sg_descriptor sg_descriptors[3]; 331 } set_event_configuration; 332 } data; 333 }; 334 335 struct pqi_event_descriptor { 336 u8 event_type; 337 u8 reserved; 338 __le16 oq_id; 339 }; 340 341 struct pqi_event_config { 342 u8 reserved[2]; 343 u8 num_event_descriptors; 344 u8 reserved1; 345 struct pqi_event_descriptor descriptors[1]; 346 }; 347 348 #define PQI_MAX_EVENT_DESCRIPTORS 255 349 350 struct pqi_event_response { 351 struct pqi_iu_header header; 352 u8 event_type; 353 u8 reserved2 : 7; 354 u8 request_acknowlege : 1; 355 __le16 event_id; 356 __le32 additional_event_id; 357 u8 data[16]; 358 }; 359 360 struct pqi_event_acknowledge_request { 361 struct pqi_iu_header header; 362 u8 event_type; 363 u8 reserved2; 364 __le16 event_id; 365 __le32 additional_event_id; 366 }; 367 368 struct pqi_task_management_request { 369 struct pqi_iu_header header; 370 __le16 request_id; 371 __le16 nexus_id; 372 u8 reserved[4]; 373 u8 lun_number[8]; 374 __le16 protocol_specific; 375 __le16 outbound_queue_id_to_manage; 376 __le16 request_id_to_manage; 377 u8 task_management_function; 378 u8 reserved2 : 7; 379 u8 fence : 1; 380 }; 381 382 #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8 383 384 struct pqi_task_management_response { 385 struct pqi_iu_header header; 386 __le16 request_id; 387 __le16 nexus_id; 388 u8 additional_response_info[3]; 389 u8 response_code; 390 }; 391 392 struct pqi_aio_error_info { 393 u8 status; 394 u8 service_response; 395 u8 data_present; 396 u8 reserved; 397 __le32 residual_count; 398 __le16 data_length; 399 __le16 reserved1; 400 u8 data[256]; 401 }; 402 403 struct pqi_raid_error_info { 404 u8 data_in_result; 405 u8 data_out_result; 406 u8 reserved[3]; 407 u8 status; 408 __le16 status_qualifier; 409 __le16 sense_data_length; 410 __le16 response_data_length; 411 __le32 data_in_transferred; 412 __le32 data_out_transferred; 413 u8 data[256]; 414 }; 415 416 #define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13 417 #define PQI_REQUEST_IU_RAID_PATH_IO 0x14 418 #define PQI_REQUEST_IU_AIO_PATH_IO 0x15 419 #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60 420 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72 421 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73 422 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 423 424 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 425 #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93 426 #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0 427 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0 428 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1 429 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2 430 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3 431 #define PQI_RESPONSE_IU_AIO_PATH_DISABLED 0xf4 432 #define PQI_RESPONSE_IU_VENDOR_EVENT 0xf5 433 434 #define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY 0x0 435 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ 0x10 436 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ 0x11 437 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ 0x12 438 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ 0x13 439 #define PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY 0x14 440 441 #define PQI_GENERAL_ADMIN_STATUS_SUCCESS 0x0 442 443 #define PQI_IQ_PROPERTY_IS_AIO_QUEUE 0x1 444 445 #define PQI_GENERAL_ADMIN_IU_LENGTH 0x3c 446 #define PQI_PROTOCOL_SOP 0x0 447 448 #define PQI_DATA_IN_OUT_GOOD 0x0 449 #define PQI_DATA_IN_OUT_UNDERFLOW 0x1 450 #define PQI_DATA_IN_OUT_BUFFER_ERROR 0x40 451 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW 0x41 452 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42 453 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43 454 #define PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60 455 #define PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61 456 #define PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62 457 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED 0x63 458 #define PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64 459 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65 460 #define PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66 461 #define PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67 462 #define PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x6F 463 #define PQI_DATA_IN_OUT_ERROR 0xf0 464 #define PQI_DATA_IN_OUT_PROTOCOL_ERROR 0xf1 465 #define PQI_DATA_IN_OUT_HARDWARE_ERROR 0xf2 466 #define PQI_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3 467 #define PQI_DATA_IN_OUT_ABORTED 0xf4 468 #define PQI_DATA_IN_OUT_TIMEOUT 0xf5 469 470 #define CISS_CMD_STATUS_SUCCESS 0x0 471 #define CISS_CMD_STATUS_TARGET_STATUS 0x1 472 #define CISS_CMD_STATUS_DATA_UNDERRUN 0x2 473 #define CISS_CMD_STATUS_DATA_OVERRUN 0x3 474 #define CISS_CMD_STATUS_INVALID 0x4 475 #define CISS_CMD_STATUS_PROTOCOL_ERROR 0x5 476 #define CISS_CMD_STATUS_HARDWARE_ERROR 0x6 477 #define CISS_CMD_STATUS_CONNECTION_LOST 0x7 478 #define CISS_CMD_STATUS_ABORTED 0x8 479 #define CISS_CMD_STATUS_ABORT_FAILED 0x9 480 #define CISS_CMD_STATUS_UNSOLICITED_ABORT 0xa 481 #define CISS_CMD_STATUS_TIMEOUT 0xb 482 #define CISS_CMD_STATUS_UNABORTABLE 0xc 483 #define CISS_CMD_STATUS_TMF 0xd 484 #define CISS_CMD_STATUS_AIO_DISABLED 0xe 485 486 #define PQI_NUM_EVENT_QUEUE_ELEMENTS 32 487 #define PQI_EVENT_OQ_ELEMENT_LENGTH sizeof(struct pqi_event_response) 488 489 #define PQI_EVENT_TYPE_HOTPLUG 0x1 490 #define PQI_EVENT_TYPE_HARDWARE 0x2 491 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4 492 #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5 493 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd 494 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe 495 496 #pragma pack() 497 498 #define PQI_ERROR_BUFFER_ELEMENT_LENGTH \ 499 sizeof(struct pqi_raid_error_info) 500 501 /* these values are based on our implementation */ 502 #define PQI_ADMIN_IQ_NUM_ELEMENTS 8 503 #define PQI_ADMIN_OQ_NUM_ELEMENTS 20 504 #define PQI_ADMIN_IQ_ELEMENT_LENGTH 64 505 #define PQI_ADMIN_OQ_ELEMENT_LENGTH 64 506 507 #define PQI_OPERATIONAL_IQ_ELEMENT_LENGTH 128 508 #define PQI_OPERATIONAL_OQ_ELEMENT_LENGTH 16 509 510 #define PQI_MIN_MSIX_VECTORS 1 511 #define PQI_MAX_MSIX_VECTORS 64 512 513 /* these values are defined by the PQI spec */ 514 #define PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE 255 515 #define PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE 65535 516 #define PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT 64 517 #define PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT 16 518 #define PQI_ADMIN_INDEX_ALIGNMENT 64 519 #define PQI_OPERATIONAL_INDEX_ALIGNMENT 4 520 521 #define PQI_MIN_OPERATIONAL_QUEUE_ID 1 522 #define PQI_MAX_OPERATIONAL_QUEUE_ID 65535 523 524 #define PQI_AIO_SERV_RESPONSE_COMPLETE 0 525 #define PQI_AIO_SERV_RESPONSE_FAILURE 1 526 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2 527 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3 528 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4 529 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5 530 531 #define PQI_AIO_STATUS_IO_ERROR 0x1 532 #define PQI_AIO_STATUS_IO_ABORTED 0x2 533 #define PQI_AIO_STATUS_NO_PATH_TO_DEVICE 0x3 534 #define PQI_AIO_STATUS_INVALID_DEVICE 0x4 535 #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe 536 #define PQI_AIO_STATUS_UNDERRUN 0x51 537 #define PQI_AIO_STATUS_OVERRUN 0x75 538 539 typedef u32 pqi_index_t; 540 541 /* SOP data direction flags */ 542 #define SOP_NO_DIRECTION_FLAG 0 543 #define SOP_WRITE_FLAG 1 /* host writes data to Data-Out */ 544 /* buffer */ 545 #define SOP_READ_FLAG 2 /* host receives data from Data-In */ 546 /* buffer */ 547 #define SOP_BIDIRECTIONAL 3 /* data is transferred from the */ 548 /* Data-Out buffer and data is */ 549 /* transferred to the Data-In buffer */ 550 551 #define SOP_TASK_ATTRIBUTE_SIMPLE 0 552 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1 553 #define SOP_TASK_ATTRIBUTE_ORDERED 2 554 #define SOP_TASK_ATTRIBUTE_ACA 4 555 556 #define SOP_TMF_COMPLETE 0x0 557 #define SOP_TMF_FUNCTION_SUCCEEDED 0x8 558 559 /* additional CDB bytes usage field codes */ 560 #define SOP_ADDITIONAL_CDB_BYTES_0 0 /* 16-byte CDB */ 561 #define SOP_ADDITIONAL_CDB_BYTES_4 1 /* 20-byte CDB */ 562 #define SOP_ADDITIONAL_CDB_BYTES_8 2 /* 24-byte CDB */ 563 #define SOP_ADDITIONAL_CDB_BYTES_12 3 /* 28-byte CDB */ 564 #define SOP_ADDITIONAL_CDB_BYTES_16 4 /* 32-byte CDB */ 565 566 /* 567 * The purpose of this structure is to obtain proper alignment of objects in 568 * an admin queue pair. 569 */ 570 struct pqi_admin_queues_aligned { 571 __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT) 572 u8 iq_element_array[PQI_ADMIN_IQ_ELEMENT_LENGTH] 573 [PQI_ADMIN_IQ_NUM_ELEMENTS]; 574 __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT) 575 u8 oq_element_array[PQI_ADMIN_OQ_ELEMENT_LENGTH] 576 [PQI_ADMIN_OQ_NUM_ELEMENTS]; 577 __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t iq_ci; 578 __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t oq_pi; 579 }; 580 581 struct pqi_admin_queues { 582 void *iq_element_array; 583 void *oq_element_array; 584 volatile pqi_index_t *iq_ci; 585 volatile pqi_index_t *oq_pi; 586 dma_addr_t iq_element_array_bus_addr; 587 dma_addr_t oq_element_array_bus_addr; 588 dma_addr_t iq_ci_bus_addr; 589 dma_addr_t oq_pi_bus_addr; 590 __le32 __iomem *iq_pi; 591 pqi_index_t iq_pi_copy; 592 __le32 __iomem *oq_ci; 593 pqi_index_t oq_ci_copy; 594 struct task_struct *task; 595 u16 int_msg_num; 596 }; 597 598 struct pqi_queue_group { 599 struct pqi_ctrl_info *ctrl_info; /* backpointer */ 600 u16 iq_id[2]; 601 u16 oq_id; 602 u16 int_msg_num; 603 void *iq_element_array[2]; 604 void *oq_element_array; 605 dma_addr_t iq_element_array_bus_addr[2]; 606 dma_addr_t oq_element_array_bus_addr; 607 __le32 __iomem *iq_pi[2]; 608 pqi_index_t iq_pi_copy[2]; 609 volatile pqi_index_t *iq_ci[2]; 610 volatile pqi_index_t *oq_pi; 611 dma_addr_t iq_ci_bus_addr[2]; 612 dma_addr_t oq_pi_bus_addr; 613 __le32 __iomem *oq_ci; 614 pqi_index_t oq_ci_copy; 615 spinlock_t submit_lock[2]; /* protect submission queue */ 616 struct list_head request_list[2]; 617 }; 618 619 struct pqi_event_queue { 620 u16 oq_id; 621 u16 int_msg_num; 622 void *oq_element_array; 623 volatile pqi_index_t *oq_pi; 624 dma_addr_t oq_element_array_bus_addr; 625 dma_addr_t oq_pi_bus_addr; 626 __le32 __iomem *oq_ci; 627 pqi_index_t oq_ci_copy; 628 }; 629 630 #define PQI_DEFAULT_QUEUE_GROUP 0 631 #define PQI_MAX_QUEUE_GROUPS PQI_MAX_MSIX_VECTORS 632 633 struct pqi_encryption_info { 634 u16 data_encryption_key_index; 635 u32 encrypt_tweak_lower; 636 u32 encrypt_tweak_upper; 637 }; 638 639 #pragma pack(1) 640 641 #define PQI_CONFIG_TABLE_SIGNATURE "CFGTABLE" 642 #define PQI_CONFIG_TABLE_MAX_LENGTH ((u16)~0) 643 644 /* configuration table section IDs */ 645 #define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO 0 646 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES 1 647 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA 2 648 #define PQI_CONFIG_TABLE_SECTION_DEBUG 3 649 #define PQI_CONFIG_TABLE_SECTION_HEARTBEAT 4 650 651 struct pqi_config_table { 652 u8 signature[8]; /* "CFGTABLE" */ 653 __le32 first_section_offset; /* offset in bytes from the base */ 654 /* address of this table to the */ 655 /* first section */ 656 }; 657 658 struct pqi_config_table_section_header { 659 __le16 section_id; /* as defined by the */ 660 /* PQI_CONFIG_TABLE_SECTION_* */ 661 /* manifest constants above */ 662 __le16 next_section_offset; /* offset in bytes from base */ 663 /* address of the table of the */ 664 /* next section or 0 if last entry */ 665 }; 666 667 struct pqi_config_table_general_info { 668 struct pqi_config_table_section_header header; 669 __le32 section_length; /* size of this section in bytes */ 670 /* including the section header */ 671 __le32 max_outstanding_requests; /* max. outstanding */ 672 /* commands supported by */ 673 /* the controller */ 674 __le32 max_sg_size; /* max. transfer size of a single */ 675 /* command */ 676 __le32 max_sg_per_request; /* max. number of scatter-gather */ 677 /* entries supported in a single */ 678 /* command */ 679 }; 680 681 struct pqi_config_table_debug { 682 struct pqi_config_table_section_header header; 683 __le32 scratchpad; 684 }; 685 686 struct pqi_config_table_heartbeat { 687 struct pqi_config_table_section_header header; 688 __le32 heartbeat_counter; 689 }; 690 691 union pqi_reset_register { 692 struct { 693 u32 reset_type : 3; 694 u32 reserved : 2; 695 u32 reset_action : 3; 696 u32 hold_in_pd1 : 1; 697 u32 reserved2 : 23; 698 } bits; 699 u32 all_bits; 700 }; 701 702 #define PQI_RESET_ACTION_RESET 0x1 703 704 #define PQI_RESET_TYPE_NO_RESET 0x0 705 #define PQI_RESET_TYPE_SOFT_RESET 0x1 706 #define PQI_RESET_TYPE_FIRM_RESET 0x2 707 #define PQI_RESET_TYPE_HARD_RESET 0x3 708 709 #define PQI_RESET_ACTION_COMPLETED 0x2 710 711 #define PQI_RESET_POLL_INTERVAL_MSECS 100 712 713 #define PQI_MAX_OUTSTANDING_REQUESTS ((u32)~0) 714 #define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP 32 715 #define PQI_MAX_TRANSFER_SIZE (1024U * 1024U) 716 #define PQI_MAX_TRANSFER_SIZE_KDUMP (512 * 1024U) 717 718 #define RAID_MAP_MAX_ENTRIES 1024 719 720 #define PQI_PHYSICAL_DEVICE_BUS 0 721 #define PQI_RAID_VOLUME_BUS 1 722 #define PQI_HBA_BUS 2 723 #define PQI_EXTERNAL_RAID_VOLUME_BUS 3 724 #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS 725 726 struct report_lun_header { 727 __be32 list_length; 728 u8 extended_response; 729 u8 reserved[3]; 730 }; 731 732 struct report_log_lun_extended_entry { 733 u8 lunid[8]; 734 u8 volume_id[16]; 735 }; 736 737 struct report_log_lun_extended { 738 struct report_lun_header header; 739 struct report_log_lun_extended_entry lun_entries[1]; 740 }; 741 742 struct report_phys_lun_extended_entry { 743 u8 lunid[8]; 744 __be64 wwid; 745 u8 device_type; 746 u8 device_flags; 747 u8 lun_count; /* number of LUNs in a multi-LUN device */ 748 u8 redundant_paths; 749 u32 aio_handle; 750 }; 751 752 /* for device_flags field of struct report_phys_lun_extended_entry */ 753 #define REPORT_PHYS_LUN_DEV_FLAG_AIO_ENABLED 0x8 754 755 struct report_phys_lun_extended { 756 struct report_lun_header header; 757 struct report_phys_lun_extended_entry lun_entries[1]; 758 }; 759 760 struct raid_map_disk_data { 761 u32 aio_handle; 762 u8 xor_mult[2]; 763 u8 reserved[2]; 764 }; 765 766 /* constants for flags field of RAID map */ 767 #define RAID_MAP_ENCRYPTION_ENABLED 0x1 768 769 struct raid_map { 770 __le32 structure_size; /* size of entire structure in bytes */ 771 __le32 volume_blk_size; /* bytes / block in the volume */ 772 __le64 volume_blk_cnt; /* logical blocks on the volume */ 773 u8 phys_blk_shift; /* shift factor to convert between */ 774 /* units of logical blocks and */ 775 /* physical disk blocks */ 776 u8 parity_rotation_shift; /* shift factor to convert between */ 777 /* units of logical stripes and */ 778 /* physical stripes */ 779 __le16 strip_size; /* blocks used on each disk / stripe */ 780 __le64 disk_starting_blk; /* first disk block used in volume */ 781 __le64 disk_blk_cnt; /* disk blocks used by volume / disk */ 782 __le16 data_disks_per_row; /* data disk entries / row in the map */ 783 __le16 metadata_disks_per_row; /* mirror/parity disk entries / row */ 784 /* in the map */ 785 __le16 row_cnt; /* rows in each layout map */ 786 __le16 layout_map_count; /* layout maps (1 map per */ 787 /* mirror parity group) */ 788 __le16 flags; 789 __le16 data_encryption_key_index; 790 u8 reserved[16]; 791 struct raid_map_disk_data disk_data[RAID_MAP_MAX_ENTRIES]; 792 }; 793 794 #pragma pack() 795 796 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 797 798 struct pqi_scsi_dev { 799 int devtype; /* as reported by INQUIRY commmand */ 800 u8 device_type; /* as reported by */ 801 /* BMIC_IDENTIFY_PHYSICAL_DEVICE */ 802 /* only valid for devtype = TYPE_DISK */ 803 int bus; 804 int target; 805 int lun; 806 u8 scsi3addr[8]; 807 __be64 wwid; 808 u8 volume_id[16]; 809 u8 is_physical_device : 1; 810 u8 is_external_raid_device : 1; 811 u8 target_lun_valid : 1; 812 u8 device_gone : 1; 813 u8 new_device : 1; 814 u8 keep_device : 1; 815 u8 volume_offline : 1; 816 bool aio_enabled; /* only valid for physical disks */ 817 bool in_reset; 818 bool device_offline; 819 u8 vendor[8]; /* bytes 8-15 of inquiry data */ 820 u8 model[16]; /* bytes 16-31 of inquiry data */ 821 u64 sas_address; 822 u8 raid_level; 823 u16 queue_depth; /* max. queue_depth for this device */ 824 u16 advertised_queue_depth; 825 u32 aio_handle; 826 u8 volume_status; 827 u8 active_path_index; 828 u8 path_map; 829 u8 bay; 830 u8 box[8]; 831 u16 phys_connector[8]; 832 bool raid_bypass_configured; /* RAID bypass configured */ 833 bool raid_bypass_enabled; /* RAID bypass enabled */ 834 int offload_to_mirror; /* Send next RAID bypass request */ 835 /* to mirror drive. */ 836 struct raid_map *raid_map; /* RAID bypass map */ 837 838 struct pqi_sas_port *sas_port; 839 struct scsi_device *sdev; 840 841 struct list_head scsi_device_list_entry; 842 struct list_head new_device_list_entry; 843 struct list_head add_list_entry; 844 struct list_head delete_list_entry; 845 846 atomic_t scsi_cmds_outstanding; 847 }; 848 849 /* VPD inquiry pages */ 850 #define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */ 851 #define SCSI_VPD_DEVICE_ID 0x83 /* standard page */ 852 #define CISS_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */ 853 #define CISS_VPD_LV_BYPASS_STATUS 0xc2 /* vendor-specific page */ 854 #define CISS_VPD_LV_STATUS 0xc3 /* vendor-specific page */ 855 856 #define VPD_PAGE (1 << 8) 857 858 #pragma pack(1) 859 860 /* structure for CISS_VPD_LV_STATUS */ 861 struct ciss_vpd_logical_volume_status { 862 u8 peripheral_info; 863 u8 page_code; 864 u8 reserved; 865 u8 page_length; 866 u8 volume_status; 867 u8 reserved2[3]; 868 __be32 flags; 869 }; 870 871 #pragma pack() 872 873 /* constants for volume_status field of ciss_vpd_logical_volume_status */ 874 #define CISS_LV_OK 0 875 #define CISS_LV_FAILED 1 876 #define CISS_LV_NOT_CONFIGURED 2 877 #define CISS_LV_DEGRADED 3 878 #define CISS_LV_READY_FOR_RECOVERY 4 879 #define CISS_LV_UNDERGOING_RECOVERY 5 880 #define CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED 6 881 #define CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM 7 882 #define CISS_LV_HARDWARE_OVERHEATING 8 883 #define CISS_LV_HARDWARE_HAS_OVERHEATED 9 884 #define CISS_LV_UNDERGOING_EXPANSION 10 885 #define CISS_LV_NOT_AVAILABLE 11 886 #define CISS_LV_QUEUED_FOR_EXPANSION 12 887 #define CISS_LV_DISABLED_SCSI_ID_CONFLICT 13 888 #define CISS_LV_EJECTED 14 889 #define CISS_LV_UNDERGOING_ERASE 15 890 /* state 16 not used */ 891 #define CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD 17 892 #define CISS_LV_UNDERGOING_RPI 18 893 #define CISS_LV_PENDING_RPI 19 894 #define CISS_LV_ENCRYPTED_NO_KEY 20 895 /* state 21 not used */ 896 #define CISS_LV_UNDERGOING_ENCRYPTION 22 897 #define CISS_LV_UNDERGOING_ENCRYPTION_REKEYING 23 898 #define CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 24 899 #define CISS_LV_PENDING_ENCRYPTION 25 900 #define CISS_LV_PENDING_ENCRYPTION_REKEYING 26 901 #define CISS_LV_NOT_SUPPORTED 27 902 #define CISS_LV_STATUS_UNAVAILABLE 255 903 904 /* constants for flags field of ciss_vpd_logical_volume_status */ 905 #define CISS_LV_FLAGS_NO_HOST_IO 0x1 /* volume not available for */ 906 /* host I/O */ 907 908 /* for SAS hosts and SAS expanders */ 909 struct pqi_sas_node { 910 struct device *parent_dev; 911 struct list_head port_list_head; 912 }; 913 914 struct pqi_sas_port { 915 struct list_head port_list_entry; 916 u64 sas_address; 917 struct sas_port *port; 918 int next_phy_index; 919 struct list_head phy_list_head; 920 struct pqi_sas_node *parent_node; 921 struct sas_rphy *rphy; 922 }; 923 924 struct pqi_sas_phy { 925 struct list_head phy_list_entry; 926 struct sas_phy *phy; 927 struct pqi_sas_port *parent_port; 928 bool added_to_port; 929 }; 930 931 struct pqi_io_request { 932 atomic_t refcount; 933 u16 index; 934 void (*io_complete_callback)(struct pqi_io_request *io_request, 935 void *context); 936 void *context; 937 u8 raid_bypass : 1; 938 int status; 939 struct pqi_queue_group *queue_group; 940 struct scsi_cmnd *scmd; 941 void *error_info; 942 struct pqi_sg_descriptor *sg_chain_buffer; 943 dma_addr_t sg_chain_buffer_dma_handle; 944 void *iu; 945 struct list_head request_list_entry; 946 }; 947 948 #define PQI_NUM_SUPPORTED_EVENTS 6 949 950 struct pqi_event { 951 bool pending; 952 u8 event_type; 953 __le16 event_id; 954 __le32 additional_event_id; 955 }; 956 957 #define PQI_RESERVED_IO_SLOTS_LUN_RESET 1 958 #define PQI_RESERVED_IO_SLOTS_EVENT_ACK PQI_NUM_SUPPORTED_EVENTS 959 #define PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS 3 960 #define PQI_RESERVED_IO_SLOTS \ 961 (PQI_RESERVED_IO_SLOTS_LUN_RESET + PQI_RESERVED_IO_SLOTS_EVENT_ACK + \ 962 PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS) 963 964 struct pqi_ctrl_info { 965 unsigned int ctrl_id; 966 struct pci_dev *pci_dev; 967 char firmware_version[11]; 968 void __iomem *iomem_base; 969 struct pqi_ctrl_registers __iomem *registers; 970 struct pqi_device_registers __iomem *pqi_registers; 971 u32 max_sg_entries; 972 u32 config_table_offset; 973 u32 config_table_length; 974 u16 max_inbound_queues; 975 u16 max_elements_per_iq; 976 u16 max_iq_element_length; 977 u16 max_outbound_queues; 978 u16 max_elements_per_oq; 979 u16 max_oq_element_length; 980 u32 max_transfer_size; 981 u32 max_outstanding_requests; 982 u32 max_io_slots; 983 unsigned int scsi_ml_can_queue; 984 unsigned short sg_tablesize; 985 unsigned int max_sectors; 986 u32 error_buffer_length; 987 void *error_buffer; 988 dma_addr_t error_buffer_dma_handle; 989 size_t sg_chain_buffer_length; 990 unsigned int num_queue_groups; 991 u16 max_hw_queue_index; 992 u16 num_elements_per_iq; 993 u16 num_elements_per_oq; 994 u16 max_inbound_iu_length_per_firmware; 995 u16 max_inbound_iu_length; 996 unsigned int max_sg_per_iu; 997 void *admin_queue_memory_base; 998 u32 admin_queue_memory_length; 999 dma_addr_t admin_queue_memory_base_dma_handle; 1000 void *queue_memory_base; 1001 u32 queue_memory_length; 1002 dma_addr_t queue_memory_base_dma_handle; 1003 struct pqi_admin_queues admin_queues; 1004 struct pqi_queue_group queue_groups[PQI_MAX_QUEUE_GROUPS]; 1005 struct pqi_event_queue event_queue; 1006 enum pqi_irq_mode irq_mode; 1007 int max_msix_vectors; 1008 int num_msix_vectors_enabled; 1009 int num_msix_vectors_initialized; 1010 int event_irq; 1011 struct Scsi_Host *scsi_host; 1012 1013 struct mutex scan_mutex; 1014 struct mutex lun_reset_mutex; 1015 bool controller_online; 1016 bool block_requests; 1017 u8 inbound_spanning_supported : 1; 1018 u8 outbound_spanning_supported : 1; 1019 u8 pqi_mode_enabled : 1; 1020 u8 pqi_reset_quiesce_supported : 1; 1021 1022 struct list_head scsi_device_list; 1023 spinlock_t scsi_device_list_lock; 1024 1025 struct delayed_work rescan_work; 1026 struct delayed_work update_time_work; 1027 1028 struct pqi_sas_node *sas_host; 1029 u64 sas_address; 1030 1031 struct pqi_io_request *io_request_pool; 1032 u16 next_io_request_slot; 1033 1034 struct pqi_event events[PQI_NUM_SUPPORTED_EVENTS]; 1035 struct work_struct event_work; 1036 1037 atomic_t num_interrupts; 1038 int previous_num_interrupts; 1039 u32 previous_heartbeat_count; 1040 __le32 __iomem *heartbeat_counter; 1041 struct timer_list heartbeat_timer; 1042 struct work_struct ctrl_offline_work; 1043 1044 struct semaphore sync_request_sem; 1045 atomic_t num_busy_threads; 1046 atomic_t num_blocked_threads; 1047 wait_queue_head_t block_requests_wait; 1048 1049 struct list_head raid_bypass_retry_list; 1050 spinlock_t raid_bypass_retry_list_lock; 1051 struct work_struct raid_bypass_retry_work; 1052 }; 1053 1054 enum pqi_ctrl_mode { 1055 SIS_MODE = 0, 1056 PQI_MODE 1057 }; 1058 1059 /* 1060 * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands 1061 */ 1062 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 1063 1064 /* CISS commands */ 1065 #define CISS_READ 0xc0 1066 #define CISS_REPORT_LOG 0xc2 /* Report Logical LUNs */ 1067 #define CISS_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 1068 #define CISS_GET_RAID_MAP 0xc8 1069 1070 /* constants for CISS_REPORT_LOG/CISS_REPORT_PHYS commands */ 1071 #define CISS_REPORT_LOG_EXTENDED 0x1 1072 #define CISS_REPORT_PHYS_EXTENDED 0x2 1073 1074 /* BMIC commands */ 1075 #define BMIC_IDENTIFY_CONTROLLER 0x11 1076 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 1077 #define BMIC_READ 0x26 1078 #define BMIC_WRITE 0x27 1079 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 1080 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 1081 #define BMIC_WRITE_HOST_WELLNESS 0xa5 1082 #define BMIC_FLUSH_CACHE 0xc2 1083 1084 #define SA_FLUSH_CACHE 0x1 1085 1086 #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xc0) 1087 #define CISS_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3f) 1088 #define CISS_GET_LEVEL_2_TARGET(lunid) ((lunid)[6]) 1089 #define CISS_GET_DRIVE_NUMBER(lunid) \ 1090 (((CISS_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \ 1091 CISS_GET_LEVEL_2_TARGET((lunid))) 1092 1093 #define NO_TIMEOUT ((unsigned long) -1) 1094 1095 #pragma pack(1) 1096 1097 struct bmic_identify_controller { 1098 u8 configured_logical_drive_count; 1099 __le32 configuration_signature; 1100 u8 firmware_version[4]; 1101 u8 reserved[145]; 1102 __le16 extended_logical_unit_count; 1103 u8 reserved1[34]; 1104 __le16 firmware_build_number; 1105 u8 reserved2[100]; 1106 u8 controller_mode; 1107 u8 reserved3[32]; 1108 }; 1109 1110 struct bmic_identify_physical_device { 1111 u8 scsi_bus; /* SCSI Bus number on controller */ 1112 u8 scsi_id; /* SCSI ID on this bus */ 1113 __le16 block_size; /* sector size in bytes */ 1114 __le32 total_blocks; /* number for sectors on drive */ 1115 __le32 reserved_blocks; /* controller reserved (RIS) */ 1116 u8 model[40]; /* Physical Drive Model */ 1117 u8 serial_number[40]; /* Drive Serial Number */ 1118 u8 firmware_revision[8]; /* drive firmware revision */ 1119 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ 1120 u8 compaq_drive_stamp; /* 0 means drive not stamped */ 1121 u8 last_failure_reason; 1122 u8 flags; 1123 u8 more_flags; 1124 u8 scsi_lun; /* SCSI LUN for phys drive */ 1125 u8 yet_more_flags; 1126 u8 even_more_flags; 1127 __le32 spi_speed_rules; 1128 u8 phys_connector[2]; /* connector number on controller */ 1129 u8 phys_box_on_bus; /* phys enclosure this drive resides */ 1130 u8 phys_bay_in_box; /* phys drv bay this drive resides */ 1131 __le32 rpm; /* drive rotational speed in RPM */ 1132 u8 device_type; /* type of drive */ 1133 u8 sata_version; /* only valid when device_type = */ 1134 /* BMIC_DEVICE_TYPE_SATA */ 1135 __le64 big_total_block_count; 1136 __le64 ris_starting_lba; 1137 __le32 ris_size; 1138 u8 wwid[20]; 1139 u8 controller_phy_map[32]; 1140 __le16 phy_count; 1141 u8 phy_connected_dev_type[256]; 1142 u8 phy_to_drive_bay_num[256]; 1143 __le16 phy_to_attached_dev_index[256]; 1144 u8 box_index; 1145 u8 reserved; 1146 __le16 extra_physical_drive_flags; 1147 u8 negotiated_link_rate[256]; 1148 u8 phy_to_phy_map[256]; 1149 u8 redundant_path_present_map; 1150 u8 redundant_path_failure_map; 1151 u8 active_path_number; 1152 __le16 alternate_paths_phys_connector[8]; 1153 u8 alternate_paths_phys_box_on_port[8]; 1154 u8 multi_lun_device_lun_count; 1155 u8 minimum_good_fw_revision[8]; 1156 u8 unique_inquiry_bytes[20]; 1157 u8 current_temperature_degrees; 1158 u8 temperature_threshold_degrees; 1159 u8 max_temperature_degrees; 1160 u8 logical_blocks_per_phys_block_exp; 1161 __le16 current_queue_depth_limit; 1162 u8 switch_name[10]; 1163 __le16 switch_port; 1164 u8 alternate_paths_switch_name[40]; 1165 u8 alternate_paths_switch_port[8]; 1166 __le16 power_on_hours; 1167 __le16 percent_endurance_used; 1168 u8 drive_authentication; 1169 u8 smart_carrier_authentication; 1170 u8 smart_carrier_app_fw_version; 1171 u8 smart_carrier_bootloader_fw_version; 1172 u8 sanitize_flags; 1173 u8 encryption_key_flags; 1174 u8 encryption_key_name[64]; 1175 __le32 misc_drive_flags; 1176 __le16 dek_index; 1177 __le16 hba_drive_encryption_flags; 1178 __le16 max_overwrite_time; 1179 __le16 max_block_erase_time; 1180 __le16 max_crypto_erase_time; 1181 u8 connector_info[5]; 1182 u8 connector_name[8][8]; 1183 u8 page_83_identifier[16]; 1184 u8 maximum_link_rate[256]; 1185 u8 negotiated_physical_link_rate[256]; 1186 u8 box_connector_name[8]; 1187 u8 padding_to_multiple_of_512[9]; 1188 }; 1189 1190 struct bmic_flush_cache { 1191 u8 disable_flag; 1192 u8 system_power_action; 1193 u8 ndu_flush; 1194 u8 shutdown_event; 1195 u8 reserved[28]; 1196 }; 1197 1198 /* for shutdown_event member of struct bmic_flush_cache */ 1199 enum bmic_flush_cache_shutdown_event { 1200 NONE_CACHE_FLUSH_ONLY = 0, 1201 SHUTDOWN = 1, 1202 HIBERNATE = 2, 1203 SUSPEND = 3, 1204 RESTART = 4 1205 }; 1206 1207 #pragma pack() 1208 1209 int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info); 1210 void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info); 1211 int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node, 1212 struct pqi_scsi_dev *device); 1213 void pqi_remove_sas_device(struct pqi_scsi_dev *device); 1214 struct pqi_scsi_dev *pqi_find_device_by_sas_rphy( 1215 struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy); 1216 void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd); 1217 1218 extern struct sas_function_template pqi_sas_transport_functions; 1219 1220 #endif /* _SMARTPQI_H */ 1221