12cc37b15SDon Brace /* SPDX-License-Identifier: GPL-2.0 */
26c223761SKevin Barnett /*
3889653ecSKevin Barnett * driver for Microchip PQI-based storage controllers
449fd52d4SDon Brace * Copyright (c) 2019-2023 Microchip Technology Inc. and its subsidiaries
52f4c4b92SDon Brace * Copyright (c) 2016-2018 Microsemi Corporation
66c223761SKevin Barnett * Copyright (c) 2016 PMC-Sierra, Inc.
76c223761SKevin Barnett *
82f4c4b92SDon Brace * Questions/Comments/Bugfixes to storagedev@microchip.com
96c223761SKevin Barnett *
106c223761SKevin Barnett */
116c223761SKevin Barnett
12ebaec8e3SCorentin Labbe #include <linux/io-64-nonatomic-lo-hi.h>
13ebaec8e3SCorentin Labbe
146c223761SKevin Barnett #if !defined(_SMARTPQI_H)
156c223761SKevin Barnett #define _SMARTPQI_H
166c223761SKevin Barnett
173d46a59aSDon Brace #include <scsi/scsi_host.h>
183d46a59aSDon Brace #include <linux/bsg-lib.h>
193d46a59aSDon Brace
206c223761SKevin Barnett #pragma pack(1)
216c223761SKevin Barnett
226c223761SKevin Barnett #define PQI_DEVICE_SIGNATURE "PQI DREG"
236c223761SKevin Barnett
246c223761SKevin Barnett /* This structure is defined by the PQI specification. */
256c223761SKevin Barnett struct pqi_device_registers {
266c223761SKevin Barnett __le64 signature;
276c223761SKevin Barnett u8 function_and_status_code;
286c223761SKevin Barnett u8 reserved[7];
296c223761SKevin Barnett u8 max_admin_iq_elements;
306c223761SKevin Barnett u8 max_admin_oq_elements;
316c223761SKevin Barnett u8 admin_iq_element_length; /* in 16-byte units */
326c223761SKevin Barnett u8 admin_oq_element_length; /* in 16-byte units */
336c223761SKevin Barnett __le16 max_reset_timeout; /* in 100-millisecond units */
346c223761SKevin Barnett u8 reserved1[2];
356c223761SKevin Barnett __le32 legacy_intx_status;
366c223761SKevin Barnett __le32 legacy_intx_mask_set;
376c223761SKevin Barnett __le32 legacy_intx_mask_clear;
386c223761SKevin Barnett u8 reserved2[28];
396c223761SKevin Barnett __le32 device_status;
406c223761SKevin Barnett u8 reserved3[4];
416c223761SKevin Barnett __le64 admin_iq_pi_offset;
426c223761SKevin Barnett __le64 admin_oq_ci_offset;
436c223761SKevin Barnett __le64 admin_iq_element_array_addr;
446c223761SKevin Barnett __le64 admin_oq_element_array_addr;
456c223761SKevin Barnett __le64 admin_iq_ci_addr;
466c223761SKevin Barnett __le64 admin_oq_pi_addr;
476c223761SKevin Barnett u8 admin_iq_num_elements;
486c223761SKevin Barnett u8 admin_oq_num_elements;
496c223761SKevin Barnett __le16 admin_queue_int_msg_num;
506c223761SKevin Barnett u8 reserved4[4];
516c223761SKevin Barnett __le32 device_error;
526c223761SKevin Barnett u8 reserved5[4];
536c223761SKevin Barnett __le64 error_details;
546c223761SKevin Barnett __le32 device_reset;
556c223761SKevin Barnett __le32 power_action;
566c223761SKevin Barnett u8 reserved6[104];
576c223761SKevin Barnett };
586c223761SKevin Barnett
596c223761SKevin Barnett /*
606c223761SKevin Barnett * controller registers
616c223761SKevin Barnett *
62889653ecSKevin Barnett * These are defined by the Microchip implementation.
636c223761SKevin Barnett *
646c223761SKevin Barnett * Some registers (those named sis_*) are only used when in
656c223761SKevin Barnett * legacy SIS mode before we transition the controller into
666c223761SKevin Barnett * PQI mode. There are a number of other SIS mode registers,
676c223761SKevin Barnett * but we don't use them, so only the SIS registers that we
686c223761SKevin Barnett * care about are defined here. The offsets mentioned in the
696c223761SKevin Barnett * comments are the offsets from the PCIe BAR 0.
706c223761SKevin Barnett */
716c223761SKevin Barnett struct pqi_ctrl_registers {
726c223761SKevin Barnett u8 reserved[0x20];
736c223761SKevin Barnett __le32 sis_host_to_ctrl_doorbell; /* 20h */
746c223761SKevin Barnett u8 reserved1[0x34 - (0x20 + sizeof(__le32))];
756c223761SKevin Barnett __le32 sis_interrupt_mask; /* 34h */
766c223761SKevin Barnett u8 reserved2[0x9c - (0x34 + sizeof(__le32))];
776c223761SKevin Barnett __le32 sis_ctrl_to_host_doorbell; /* 9Ch */
786c223761SKevin Barnett u8 reserved3[0xa0 - (0x9c + sizeof(__le32))];
796c223761SKevin Barnett __le32 sis_ctrl_to_host_doorbell_clear; /* A0h */
80ff6abb73SKevin Barnett u8 reserved4[0xb0 - (0xa0 + sizeof(__le32))];
81ff6abb73SKevin Barnett __le32 sis_driver_scratch; /* B0h */
822708a256SKevin Barnett __le32 sis_product_identifier; /* B4h */
832708a256SKevin Barnett u8 reserved5[0xbc - (0xb4 + sizeof(__le32))];
846c223761SKevin Barnett __le32 sis_firmware_status; /* BCh */
855d1f03e6SMurthy Bhat u8 reserved6[0xcc - (0xbc + sizeof(__le32))];
865d1f03e6SMurthy Bhat __le32 sis_ctrl_shutdown_reason_code; /* CCh */
875d1f03e6SMurthy Bhat u8 reserved7[0x1000 - (0xcc + sizeof(__le32))];
886c223761SKevin Barnett __le32 sis_mailbox[8]; /* 1000h */
895d1f03e6SMurthy Bhat u8 reserved8[0x4000 - (0x1000 + (sizeof(__le32) * 8))];
906c223761SKevin Barnett /*
916c223761SKevin Barnett * The PQI spec states that the PQI registers should be at
926c223761SKevin Barnett * offset 0 from the PCIe BAR 0. However, we can't map
936c223761SKevin Barnett * them at offset 0 because that would break compatibility
946c223761SKevin Barnett * with the SIS registers. So we map them at offset 4000h.
956c223761SKevin Barnett */
966c223761SKevin Barnett struct pqi_device_registers pqi_registers; /* 4000h */
976c223761SKevin Barnett };
986c223761SKevin Barnett
996c223761SKevin Barnett #define PQI_DEVICE_REGISTERS_OFFSET 0x4000
1006c223761SKevin Barnett
1015d1f03e6SMurthy Bhat /* shutdown reasons for taking the controller offline */
1025d1f03e6SMurthy Bhat enum pqi_ctrl_shutdown_reason {
1035d1f03e6SMurthy Bhat PQI_IQ_NOT_DRAINED_TIMEOUT = 1,
1045d1f03e6SMurthy Bhat PQI_LUN_RESET_TIMEOUT = 2,
1055d1f03e6SMurthy Bhat PQI_IO_PENDING_POST_LUN_RESET_TIMEOUT = 3,
1065d1f03e6SMurthy Bhat PQI_NO_HEARTBEAT = 4,
1075d1f03e6SMurthy Bhat PQI_FIRMWARE_KERNEL_NOT_UP = 5,
1085d1f03e6SMurthy Bhat PQI_OFA_RESPONSE_TIMEOUT = 6,
1095d1f03e6SMurthy Bhat PQI_INVALID_REQ_ID = 7,
1105d1f03e6SMurthy Bhat PQI_UNMATCHED_REQ_ID = 8,
1115d1f03e6SMurthy Bhat PQI_IO_PI_OUT_OF_RANGE = 9,
1125d1f03e6SMurthy Bhat PQI_EVENT_PI_OUT_OF_RANGE = 10,
1135d1f03e6SMurthy Bhat PQI_UNEXPECTED_IU_TYPE = 11
1145d1f03e6SMurthy Bhat };
1155d1f03e6SMurthy Bhat
1166c223761SKevin Barnett enum pqi_io_path {
1176c223761SKevin Barnett RAID_PATH = 0,
1186c223761SKevin Barnett AIO_PATH = 1
1196c223761SKevin Barnett };
1206c223761SKevin Barnett
121061ef06aSKevin Barnett enum pqi_irq_mode {
122061ef06aSKevin Barnett IRQ_MODE_NONE,
123061ef06aSKevin Barnett IRQ_MODE_INTX,
124061ef06aSKevin Barnett IRQ_MODE_MSIX
125061ef06aSKevin Barnett };
126061ef06aSKevin Barnett
1276c223761SKevin Barnett struct pqi_sg_descriptor {
1286c223761SKevin Barnett __le64 address;
1296c223761SKevin Barnett __le32 length;
1306c223761SKevin Barnett __le32 flags;
1316c223761SKevin Barnett };
1326c223761SKevin Barnett
1336c223761SKevin Barnett /* manifest constants for the flags field of pqi_sg_descriptor */
1346c223761SKevin Barnett #define CISS_SG_LAST 0x40000000
1356c223761SKevin Barnett #define CISS_SG_CHAIN 0x80000000
1366c223761SKevin Barnett
1376c223761SKevin Barnett struct pqi_iu_header {
1386c223761SKevin Barnett u8 iu_type;
1396c223761SKevin Barnett u8 reserved;
1406c223761SKevin Barnett __le16 iu_length; /* in bytes - does not include the length */
1416c223761SKevin Barnett /* of this header */
1426c223761SKevin Barnett __le16 response_queue_id; /* specifies the OQ where the */
1436c223761SKevin Barnett /* response IU is to be delivered */
144ae0c189dSKevin Barnett u16 driver_flags; /* reserved for driver use */
1456c223761SKevin Barnett };
1466c223761SKevin Barnett
147ae0c189dSKevin Barnett /* manifest constants for pqi_iu_header.driver_flags */
148ae0c189dSKevin Barnett #define PQI_DRIVER_NONBLOCKABLE_REQUEST 0x1
149ae0c189dSKevin Barnett
1506c223761SKevin Barnett /*
1516c223761SKevin Barnett * According to the PQI spec, the IU header is only the first 4 bytes of our
1526c223761SKevin Barnett * pqi_iu_header structure.
1536c223761SKevin Barnett */
1546c223761SKevin Barnett #define PQI_REQUEST_HEADER_LENGTH 4
1556c223761SKevin Barnett
1566c223761SKevin Barnett struct pqi_general_admin_request {
1576c223761SKevin Barnett struct pqi_iu_header header;
1586c223761SKevin Barnett __le16 request_id;
1596c223761SKevin Barnett u8 function_code;
1606c223761SKevin Barnett union {
1616c223761SKevin Barnett struct {
1626c223761SKevin Barnett u8 reserved[33];
1636c223761SKevin Barnett __le32 buffer_length;
1646c223761SKevin Barnett struct pqi_sg_descriptor sg_descriptor;
1656c223761SKevin Barnett } report_device_capability;
1666c223761SKevin Barnett
1676c223761SKevin Barnett struct {
1686c223761SKevin Barnett u8 reserved;
1696c223761SKevin Barnett __le16 queue_id;
1706c223761SKevin Barnett u8 reserved1[2];
1716c223761SKevin Barnett __le64 element_array_addr;
1726c223761SKevin Barnett __le64 ci_addr;
1736c223761SKevin Barnett __le16 num_elements;
1746c223761SKevin Barnett __le16 element_length;
1756c223761SKevin Barnett u8 queue_protocol;
1766c223761SKevin Barnett u8 reserved2[23];
1776c223761SKevin Barnett __le32 vendor_specific;
1786c223761SKevin Barnett } create_operational_iq;
1796c223761SKevin Barnett
1806c223761SKevin Barnett struct {
1816c223761SKevin Barnett u8 reserved;
1826c223761SKevin Barnett __le16 queue_id;
1836c223761SKevin Barnett u8 reserved1[2];
1846c223761SKevin Barnett __le64 element_array_addr;
1856c223761SKevin Barnett __le64 pi_addr;
1866c223761SKevin Barnett __le16 num_elements;
1876c223761SKevin Barnett __le16 element_length;
1886c223761SKevin Barnett u8 queue_protocol;
1896c223761SKevin Barnett u8 reserved2[3];
1906c223761SKevin Barnett __le16 int_msg_num;
1916c223761SKevin Barnett __le16 coalescing_count;
1926c223761SKevin Barnett __le32 min_coalescing_time;
1936c223761SKevin Barnett __le32 max_coalescing_time;
1946c223761SKevin Barnett u8 reserved3[8];
1956c223761SKevin Barnett __le32 vendor_specific;
1966c223761SKevin Barnett } create_operational_oq;
1976c223761SKevin Barnett
1986c223761SKevin Barnett struct {
1996c223761SKevin Barnett u8 reserved;
2006c223761SKevin Barnett __le16 queue_id;
2016c223761SKevin Barnett u8 reserved1[50];
2026c223761SKevin Barnett } delete_operational_queue;
2036c223761SKevin Barnett
2046c223761SKevin Barnett struct {
2056c223761SKevin Barnett u8 reserved;
2066c223761SKevin Barnett __le16 queue_id;
2076c223761SKevin Barnett u8 reserved1[46];
2086c223761SKevin Barnett __le32 vendor_specific;
2096c223761SKevin Barnett } change_operational_iq_properties;
2106c223761SKevin Barnett
2116c223761SKevin Barnett } data;
2126c223761SKevin Barnett };
2136c223761SKevin Barnett
2146c223761SKevin Barnett struct pqi_general_admin_response {
2156c223761SKevin Barnett struct pqi_iu_header header;
2166c223761SKevin Barnett __le16 request_id;
2176c223761SKevin Barnett u8 function_code;
2186c223761SKevin Barnett u8 status;
2196c223761SKevin Barnett union {
2206c223761SKevin Barnett struct {
2216c223761SKevin Barnett u8 status_descriptor[4];
2226c223761SKevin Barnett __le64 iq_pi_offset;
2236c223761SKevin Barnett u8 reserved[40];
2246c223761SKevin Barnett } create_operational_iq;
2256c223761SKevin Barnett
2266c223761SKevin Barnett struct {
2276c223761SKevin Barnett u8 status_descriptor[4];
2286c223761SKevin Barnett __le64 oq_ci_offset;
2296c223761SKevin Barnett u8 reserved[40];
2306c223761SKevin Barnett } create_operational_oq;
2316c223761SKevin Barnett } data;
2326c223761SKevin Barnett };
2336c223761SKevin Barnett
2346c223761SKevin Barnett struct pqi_iu_layer_descriptor {
2356c223761SKevin Barnett u8 inbound_spanning_supported : 1;
2366c223761SKevin Barnett u8 reserved : 7;
2376c223761SKevin Barnett u8 reserved1[5];
2386c223761SKevin Barnett __le16 max_inbound_iu_length;
2396c223761SKevin Barnett u8 outbound_spanning_supported : 1;
2406c223761SKevin Barnett u8 reserved2 : 7;
2416c223761SKevin Barnett u8 reserved3[5];
2426c223761SKevin Barnett __le16 max_outbound_iu_length;
2436c223761SKevin Barnett };
2446c223761SKevin Barnett
2456c223761SKevin Barnett struct pqi_device_capability {
2466c223761SKevin Barnett __le16 data_length;
2476c223761SKevin Barnett u8 reserved[6];
2486c223761SKevin Barnett u8 iq_arbitration_priority_support_bitmask;
2496c223761SKevin Barnett u8 maximum_aw_a;
2506c223761SKevin Barnett u8 maximum_aw_b;
2516c223761SKevin Barnett u8 maximum_aw_c;
2526c223761SKevin Barnett u8 max_arbitration_burst : 3;
2536c223761SKevin Barnett u8 reserved1 : 4;
2546c223761SKevin Barnett u8 iqa : 1;
2556c223761SKevin Barnett u8 reserved2[2];
2566c223761SKevin Barnett u8 iq_freeze : 1;
2576c223761SKevin Barnett u8 reserved3 : 7;
2586c223761SKevin Barnett __le16 max_inbound_queues;
2596c223761SKevin Barnett __le16 max_elements_per_iq;
2606c223761SKevin Barnett u8 reserved4[4];
2616c223761SKevin Barnett __le16 max_iq_element_length;
2626c223761SKevin Barnett __le16 min_iq_element_length;
2636c223761SKevin Barnett u8 reserved5[2];
2646c223761SKevin Barnett __le16 max_outbound_queues;
2656c223761SKevin Barnett __le16 max_elements_per_oq;
2666c223761SKevin Barnett __le16 intr_coalescing_time_granularity;
2676c223761SKevin Barnett __le16 max_oq_element_length;
2686c223761SKevin Barnett __le16 min_oq_element_length;
2696c223761SKevin Barnett u8 reserved6[24];
2706c223761SKevin Barnett struct pqi_iu_layer_descriptor iu_layer_descriptors[32];
2716c223761SKevin Barnett };
2726c223761SKevin Barnett
2736c223761SKevin Barnett #define PQI_MAX_EMBEDDED_SG_DESCRIPTORS 4
2746702d2c4SDon Brace #define PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS 3
2756c223761SKevin Barnett
2766c223761SKevin Barnett struct pqi_raid_path_request {
2776c223761SKevin Barnett struct pqi_iu_header header;
2786c223761SKevin Barnett __le16 request_id;
2796c223761SKevin Barnett __le16 nexus_id;
2806c223761SKevin Barnett __le32 buffer_length;
2816c223761SKevin Barnett u8 lun_number[8];
2826c223761SKevin Barnett __le16 protocol_specific;
2836c223761SKevin Barnett u8 data_direction : 2;
2846c223761SKevin Barnett u8 partial : 1;
2856c223761SKevin Barnett u8 reserved1 : 4;
2866c223761SKevin Barnett u8 fence : 1;
2876c223761SKevin Barnett __le16 error_index;
2886c223761SKevin Barnett u8 reserved2;
2896c223761SKevin Barnett u8 task_attribute : 3;
2906c223761SKevin Barnett u8 command_priority : 4;
2916c223761SKevin Barnett u8 reserved3 : 1;
2926c223761SKevin Barnett u8 reserved4 : 2;
2936c223761SKevin Barnett u8 additional_cdb_bytes_usage : 3;
2946c223761SKevin Barnett u8 reserved5 : 3;
29521432010Skoshyaji u8 cdb[16];
296904f2bfdSKumar Meiyappan u8 reserved6[11];
297904f2bfdSKumar Meiyappan u8 ml_device_lun_number;
29821432010Skoshyaji __le32 timeout;
299583891c9SKevin Barnett struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
3006c223761SKevin Barnett };
3016c223761SKevin Barnett
3026c223761SKevin Barnett struct pqi_aio_path_request {
3036c223761SKevin Barnett struct pqi_iu_header header;
3046c223761SKevin Barnett __le16 request_id;
3056c223761SKevin Barnett u8 reserved1[2];
3066c223761SKevin Barnett __le32 nexus_id;
3076c223761SKevin Barnett __le32 buffer_length;
3086c223761SKevin Barnett u8 data_direction : 2;
3096c223761SKevin Barnett u8 partial : 1;
3106c223761SKevin Barnett u8 memory_type : 1;
3116c223761SKevin Barnett u8 fence : 1;
3126c223761SKevin Barnett u8 encryption_enable : 1;
3136c223761SKevin Barnett u8 reserved2 : 2;
3146c223761SKevin Barnett u8 task_attribute : 3;
3156c223761SKevin Barnett u8 command_priority : 4;
3166c223761SKevin Barnett u8 reserved3 : 1;
3176c223761SKevin Barnett __le16 data_encryption_key_index;
3186c223761SKevin Barnett __le32 encrypt_tweak_lower;
3196c223761SKevin Barnett __le32 encrypt_tweak_upper;
3206c223761SKevin Barnett u8 cdb[16];
3216c223761SKevin Barnett __le16 error_index;
3226c223761SKevin Barnett u8 num_sg_descriptors;
3236c223761SKevin Barnett u8 cdb_length;
3246c223761SKevin Barnett u8 lun_number[8];
3256c223761SKevin Barnett u8 reserved4[4];
326583891c9SKevin Barnett struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
3276c223761SKevin Barnett };
3286c223761SKevin Barnett
3297a012c23SDon Brace #define PQI_RAID1_NVME_XFER_LIMIT (32 * 1024) /* 32 KiB */
330583891c9SKevin Barnett
3317a012c23SDon Brace struct pqi_aio_r1_path_request {
3327a012c23SDon Brace struct pqi_iu_header header;
3337a012c23SDon Brace __le16 request_id;
3347a012c23SDon Brace __le16 volume_id; /* ID of the RAID volume */
3357a012c23SDon Brace __le32 it_nexus_1; /* IT nexus of the 1st drive in the RAID volume */
3367a012c23SDon Brace __le32 it_nexus_2; /* IT nexus of the 2nd drive in the RAID volume */
3377a012c23SDon Brace __le32 it_nexus_3; /* IT nexus of the 3rd drive in the RAID volume */
3387a012c23SDon Brace __le32 data_length; /* total bytes to read/write */
3397a012c23SDon Brace u8 data_direction : 2;
3407a012c23SDon Brace u8 partial : 1;
3417a012c23SDon Brace u8 memory_type : 1;
3427a012c23SDon Brace u8 fence : 1;
3437a012c23SDon Brace u8 encryption_enable : 1;
3447a012c23SDon Brace u8 reserved : 2;
3457a012c23SDon Brace u8 task_attribute : 3;
3467a012c23SDon Brace u8 command_priority : 4;
3477a012c23SDon Brace u8 reserved2 : 1;
3487a012c23SDon Brace __le16 data_encryption_key_index;
3497a012c23SDon Brace u8 cdb[16];
3507a012c23SDon Brace __le16 error_index;
3517a012c23SDon Brace u8 num_sg_descriptors;
3527a012c23SDon Brace u8 cdb_length;
3537a012c23SDon Brace u8 num_drives; /* number of drives in the RAID volume (2 or 3) */
3547a012c23SDon Brace u8 reserved3[3];
3557a012c23SDon Brace __le32 encrypt_tweak_lower;
3567a012c23SDon Brace __le32 encrypt_tweak_upper;
3577a012c23SDon Brace struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
3587a012c23SDon Brace };
3597a012c23SDon Brace
360f6cc2a77SKevin Barnett #define PQI_DEFAULT_MAX_WRITE_RAID_5_6 (8 * 1024U)
361f6cc2a77SKevin Barnett #define PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_SAS_SATA (~0U)
362f6cc2a77SKevin Barnett #define PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_NVME (32 * 1024U)
363f6cc2a77SKevin Barnett
3646702d2c4SDon Brace struct pqi_aio_r56_path_request {
3656702d2c4SDon Brace struct pqi_iu_header header;
3666702d2c4SDon Brace __le16 request_id;
3676702d2c4SDon Brace __le16 volume_id; /* ID of the RAID volume */
3686702d2c4SDon Brace __le32 data_it_nexus; /* IT nexus for the data drive */
3696702d2c4SDon Brace __le32 p_parity_it_nexus; /* IT nexus for the P parity drive */
3706702d2c4SDon Brace __le32 q_parity_it_nexus; /* IT nexus for the Q parity drive */
3716702d2c4SDon Brace __le32 data_length; /* total bytes to read/write */
3726702d2c4SDon Brace u8 data_direction : 2;
3736702d2c4SDon Brace u8 partial : 1;
3746702d2c4SDon Brace u8 mem_type : 1; /* 0 = PCIe, 1 = DDR */
3756702d2c4SDon Brace u8 fence : 1;
3766702d2c4SDon Brace u8 encryption_enable : 1;
3776702d2c4SDon Brace u8 reserved : 2;
3786702d2c4SDon Brace u8 task_attribute : 3;
3796702d2c4SDon Brace u8 command_priority : 4;
3806702d2c4SDon Brace u8 reserved1 : 1;
3816702d2c4SDon Brace __le16 data_encryption_key_index;
3826702d2c4SDon Brace u8 cdb[16];
3836702d2c4SDon Brace __le16 error_index;
3846702d2c4SDon Brace u8 num_sg_descriptors;
3856702d2c4SDon Brace u8 cdb_length;
3866702d2c4SDon Brace u8 xor_multiplier;
3876702d2c4SDon Brace u8 reserved2[3];
3886702d2c4SDon Brace __le32 encrypt_tweak_lower;
3896702d2c4SDon Brace __le32 encrypt_tweak_upper;
3906702d2c4SDon Brace __le64 row; /* row = logical LBA/blocks per row */
3916702d2c4SDon Brace u8 reserved3[8];
3926702d2c4SDon Brace struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS];
3936702d2c4SDon Brace };
3946702d2c4SDon Brace
3956c223761SKevin Barnett struct pqi_io_response {
3966c223761SKevin Barnett struct pqi_iu_header header;
3976c223761SKevin Barnett __le16 request_id;
3986c223761SKevin Barnett __le16 error_index;
3996c223761SKevin Barnett u8 reserved2[4];
4006c223761SKevin Barnett };
4016c223761SKevin Barnett
4026c223761SKevin Barnett struct pqi_general_management_request {
4036c223761SKevin Barnett struct pqi_iu_header header;
4046c223761SKevin Barnett __le16 request_id;
4056c223761SKevin Barnett union {
4066c223761SKevin Barnett struct {
4076c223761SKevin Barnett u8 reserved[2];
4086c223761SKevin Barnett __le32 buffer_length;
4096c223761SKevin Barnett struct pqi_sg_descriptor sg_descriptors[3];
4106c223761SKevin Barnett } report_event_configuration;
4116c223761SKevin Barnett
4126c223761SKevin Barnett struct {
4136c223761SKevin Barnett __le16 global_event_oq_id;
4146c223761SKevin Barnett __le32 buffer_length;
4156c223761SKevin Barnett struct pqi_sg_descriptor sg_descriptors[3];
4166c223761SKevin Barnett } set_event_configuration;
4176c223761SKevin Barnett } data;
4186c223761SKevin Barnett };
4196c223761SKevin Barnett
4206c223761SKevin Barnett struct pqi_event_descriptor {
4216c223761SKevin Barnett u8 event_type;
4226c223761SKevin Barnett u8 reserved;
4236c223761SKevin Barnett __le16 oq_id;
4246c223761SKevin Barnett };
4256c223761SKevin Barnett
4266c223761SKevin Barnett struct pqi_event_config {
4276c223761SKevin Barnett u8 reserved[2];
4286c223761SKevin Barnett u8 num_event_descriptors;
4296c223761SKevin Barnett u8 reserved1;
4305f492a7aSGustavo A. R. Silva struct pqi_event_descriptor descriptors[];
4316c223761SKevin Barnett };
4326c223761SKevin Barnett
4336c223761SKevin Barnett #define PQI_MAX_EVENT_DESCRIPTORS 255
4346c223761SKevin Barnett
4354fd22c13SMahesh Rajashekhara #define PQI_EVENT_OFA_MEMORY_ALLOCATION 0x0
4364fd22c13SMahesh Rajashekhara #define PQI_EVENT_OFA_QUIESCE 0x1
437583891c9SKevin Barnett #define PQI_EVENT_OFA_CANCELED 0x2
4384fd22c13SMahesh Rajashekhara
4396c223761SKevin Barnett struct pqi_event_response {
4406c223761SKevin Barnett struct pqi_iu_header header;
4416c223761SKevin Barnett u8 event_type;
4426c223761SKevin Barnett u8 reserved2 : 7;
4439e68ccccSKevin Barnett u8 request_acknowledge : 1;
4446c223761SKevin Barnett __le16 event_id;
4456c223761SKevin Barnett __le32 additional_event_id;
4464fd22c13SMahesh Rajashekhara union {
4474fd22c13SMahesh Rajashekhara struct {
4484fd22c13SMahesh Rajashekhara __le32 bytes_requested;
4494fd22c13SMahesh Rajashekhara u8 reserved[12];
4504fd22c13SMahesh Rajashekhara } ofa_memory_allocation;
4514fd22c13SMahesh Rajashekhara
4524fd22c13SMahesh Rajashekhara struct {
4534fd22c13SMahesh Rajashekhara __le16 reason; /* reason for cancellation */
4544fd22c13SMahesh Rajashekhara u8 reserved[14];
4554fd22c13SMahesh Rajashekhara } ofa_cancelled;
4564fd22c13SMahesh Rajashekhara } data;
4576c223761SKevin Barnett };
4586c223761SKevin Barnett
4596c223761SKevin Barnett struct pqi_event_acknowledge_request {
4606c223761SKevin Barnett struct pqi_iu_header header;
4616c223761SKevin Barnett u8 event_type;
4626c223761SKevin Barnett u8 reserved2;
4636c223761SKevin Barnett __le16 event_id;
4646c223761SKevin Barnett __le32 additional_event_id;
4656c223761SKevin Barnett };
4666c223761SKevin Barnett
4676c223761SKevin Barnett struct pqi_task_management_request {
4686c223761SKevin Barnett struct pqi_iu_header header;
4696c223761SKevin Barnett __le16 request_id;
4706c223761SKevin Barnett __le16 nexus_id;
471904f2bfdSKumar Meiyappan u8 reserved;
472904f2bfdSKumar Meiyappan u8 ml_device_lun_number;
473c2922f17SMurthy Bhat __le16 timeout;
4746c223761SKevin Barnett u8 lun_number[8];
4756c223761SKevin Barnett __le16 protocol_specific;
4766c223761SKevin Barnett __le16 outbound_queue_id_to_manage;
4776c223761SKevin Barnett __le16 request_id_to_manage;
4786c223761SKevin Barnett u8 task_management_function;
4796c223761SKevin Barnett u8 reserved2 : 7;
4806c223761SKevin Barnett u8 fence : 1;
4816c223761SKevin Barnett };
4826c223761SKevin Barnett
4836c223761SKevin Barnett #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8
4846c223761SKevin Barnett
4856c223761SKevin Barnett struct pqi_task_management_response {
4866c223761SKevin Barnett struct pqi_iu_header header;
4876c223761SKevin Barnett __le16 request_id;
4886c223761SKevin Barnett __le16 nexus_id;
4896c223761SKevin Barnett u8 additional_response_info[3];
4906c223761SKevin Barnett u8 response_code;
4916c223761SKevin Barnett };
4926c223761SKevin Barnett
493b212c251SKevin Barnett struct pqi_vendor_general_request {
494b212c251SKevin Barnett struct pqi_iu_header header;
495b212c251SKevin Barnett __le16 request_id;
496b212c251SKevin Barnett __le16 function_code;
497b212c251SKevin Barnett union {
498b212c251SKevin Barnett struct {
499b212c251SKevin Barnett __le16 first_section;
500b212c251SKevin Barnett __le16 last_section;
501b212c251SKevin Barnett u8 reserved[48];
502b212c251SKevin Barnett } config_table_update;
503b212c251SKevin Barnett
504b212c251SKevin Barnett struct {
505b212c251SKevin Barnett __le64 buffer_address;
506b212c251SKevin Barnett __le32 buffer_length;
507b212c251SKevin Barnett u8 reserved[40];
508b212c251SKevin Barnett } ofa_memory_allocation;
509b212c251SKevin Barnett } data;
510b212c251SKevin Barnett };
511b212c251SKevin Barnett
512b212c251SKevin Barnett struct pqi_vendor_general_response {
513b212c251SKevin Barnett struct pqi_iu_header header;
514b212c251SKevin Barnett __le16 request_id;
515b212c251SKevin Barnett __le16 function_code;
516b212c251SKevin Barnett __le16 status;
517b212c251SKevin Barnett u8 reserved[2];
518b212c251SKevin Barnett };
519b212c251SKevin Barnett
520b212c251SKevin Barnett #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
5214fd22c13SMahesh Rajashekhara #define PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE 1
5224fd22c13SMahesh Rajashekhara
5234fd22c13SMahesh Rajashekhara #define PQI_OFA_VERSION 1
5244fd22c13SMahesh Rajashekhara #define PQI_OFA_SIGNATURE "OFA_QRM"
5254fd22c13SMahesh Rajashekhara #define PQI_OFA_MAX_SG_DESCRIPTORS 64
5264fd22c13SMahesh Rajashekhara
5274fd22c13SMahesh Rajashekhara struct pqi_ofa_memory {
5284fd22c13SMahesh Rajashekhara __le64 signature; /* "OFA_QRM" */
5294fd22c13SMahesh Rajashekhara __le16 version; /* version of this struct (1 = 1st version) */
5304fd22c13SMahesh Rajashekhara u8 reserved[62];
5314fd22c13SMahesh Rajashekhara __le32 bytes_allocated; /* total allocated memory in bytes */
5324fd22c13SMahesh Rajashekhara __le16 num_memory_descriptors;
5334fd22c13SMahesh Rajashekhara u8 reserved1[2];
5342790cd4dSKevin Barnett struct pqi_sg_descriptor sg_descriptor[PQI_OFA_MAX_SG_DESCRIPTORS];
5354fd22c13SMahesh Rajashekhara };
536b212c251SKevin Barnett
5376c223761SKevin Barnett struct pqi_aio_error_info {
5386c223761SKevin Barnett u8 status;
5396c223761SKevin Barnett u8 service_response;
5406c223761SKevin Barnett u8 data_present;
5416c223761SKevin Barnett u8 reserved;
5426c223761SKevin Barnett __le32 residual_count;
5436c223761SKevin Barnett __le16 data_length;
5446c223761SKevin Barnett __le16 reserved1;
5456c223761SKevin Barnett u8 data[256];
5466c223761SKevin Barnett };
5476c223761SKevin Barnett
5486c223761SKevin Barnett struct pqi_raid_error_info {
5496c223761SKevin Barnett u8 data_in_result;
5506c223761SKevin Barnett u8 data_out_result;
5516c223761SKevin Barnett u8 reserved[3];
5526c223761SKevin Barnett u8 status;
5536c223761SKevin Barnett __le16 status_qualifier;
5546c223761SKevin Barnett __le16 sense_data_length;
5556c223761SKevin Barnett __le16 response_data_length;
5566c223761SKevin Barnett __le32 data_in_transferred;
5576c223761SKevin Barnett __le32 data_out_transferred;
5586c223761SKevin Barnett u8 data[256];
5596c223761SKevin Barnett };
5606c223761SKevin Barnett
5616c223761SKevin Barnett #define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13
5626c223761SKevin Barnett #define PQI_REQUEST_IU_RAID_PATH_IO 0x14
5636c223761SKevin Barnett #define PQI_REQUEST_IU_AIO_PATH_IO 0x15
5646702d2c4SDon Brace #define PQI_REQUEST_IU_AIO_PATH_RAID5_IO 0x18
5656702d2c4SDon Brace #define PQI_REQUEST_IU_AIO_PATH_RAID6_IO 0x19
5667a012c23SDon Brace #define PQI_REQUEST_IU_AIO_PATH_RAID1_IO 0x1A
5676c223761SKevin Barnett #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60
5686c223761SKevin Barnett #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72
5696c223761SKevin Barnett #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73
570b212c251SKevin Barnett #define PQI_REQUEST_IU_VENDOR_GENERAL 0x75
5716c223761SKevin Barnett #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
5726c223761SKevin Barnett
5736c223761SKevin Barnett #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
5746c223761SKevin Barnett #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93
5756c223761SKevin Barnett #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0
5766c223761SKevin Barnett #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0
5776c223761SKevin Barnett #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1
5786c223761SKevin Barnett #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2
5796c223761SKevin Barnett #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3
5806c223761SKevin Barnett #define PQI_RESPONSE_IU_AIO_PATH_DISABLED 0xf4
5816c223761SKevin Barnett #define PQI_RESPONSE_IU_VENDOR_EVENT 0xf5
582b212c251SKevin Barnett #define PQI_RESPONSE_IU_VENDOR_GENERAL 0xf7
5836c223761SKevin Barnett
5846c223761SKevin Barnett #define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY 0x0
5856c223761SKevin Barnett #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ 0x10
5866c223761SKevin Barnett #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ 0x11
5876c223761SKevin Barnett #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ 0x12
5886c223761SKevin Barnett #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ 0x13
5896c223761SKevin Barnett #define PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY 0x14
5906c223761SKevin Barnett
5916c223761SKevin Barnett #define PQI_GENERAL_ADMIN_STATUS_SUCCESS 0x0
5926c223761SKevin Barnett
5936c223761SKevin Barnett #define PQI_IQ_PROPERTY_IS_AIO_QUEUE 0x1
5946c223761SKevin Barnett
5956c223761SKevin Barnett #define PQI_GENERAL_ADMIN_IU_LENGTH 0x3c
5966c223761SKevin Barnett #define PQI_PROTOCOL_SOP 0x0
5976c223761SKevin Barnett
5986c223761SKevin Barnett #define PQI_DATA_IN_OUT_GOOD 0x0
5996c223761SKevin Barnett #define PQI_DATA_IN_OUT_UNDERFLOW 0x1
6006c223761SKevin Barnett #define PQI_DATA_IN_OUT_BUFFER_ERROR 0x40
6016c223761SKevin Barnett #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW 0x41
6026c223761SKevin Barnett #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42
6036c223761SKevin Barnett #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43
6046c223761SKevin Barnett #define PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60
6056c223761SKevin Barnett #define PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61
6066c223761SKevin Barnett #define PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62
6076c223761SKevin Barnett #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED 0x63
6086c223761SKevin Barnett #define PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64
6096c223761SKevin Barnett #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65
6106c223761SKevin Barnett #define PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66
6116c223761SKevin Barnett #define PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67
6126c223761SKevin Barnett #define PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x6F
6136c223761SKevin Barnett #define PQI_DATA_IN_OUT_ERROR 0xf0
6146c223761SKevin Barnett #define PQI_DATA_IN_OUT_PROTOCOL_ERROR 0xf1
6156c223761SKevin Barnett #define PQI_DATA_IN_OUT_HARDWARE_ERROR 0xf2
6166c223761SKevin Barnett #define PQI_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3
6176c223761SKevin Barnett #define PQI_DATA_IN_OUT_ABORTED 0xf4
6186c223761SKevin Barnett #define PQI_DATA_IN_OUT_TIMEOUT 0xf5
6196c223761SKevin Barnett
6206c223761SKevin Barnett #define CISS_CMD_STATUS_SUCCESS 0x0
6216c223761SKevin Barnett #define CISS_CMD_STATUS_TARGET_STATUS 0x1
6226c223761SKevin Barnett #define CISS_CMD_STATUS_DATA_UNDERRUN 0x2
6236c223761SKevin Barnett #define CISS_CMD_STATUS_DATA_OVERRUN 0x3
6246c223761SKevin Barnett #define CISS_CMD_STATUS_INVALID 0x4
6256c223761SKevin Barnett #define CISS_CMD_STATUS_PROTOCOL_ERROR 0x5
6266c223761SKevin Barnett #define CISS_CMD_STATUS_HARDWARE_ERROR 0x6
6276c223761SKevin Barnett #define CISS_CMD_STATUS_CONNECTION_LOST 0x7
6286c223761SKevin Barnett #define CISS_CMD_STATUS_ABORTED 0x8
6296c223761SKevin Barnett #define CISS_CMD_STATUS_ABORT_FAILED 0x9
6306c223761SKevin Barnett #define CISS_CMD_STATUS_UNSOLICITED_ABORT 0xa
6316c223761SKevin Barnett #define CISS_CMD_STATUS_TIMEOUT 0xb
6326c223761SKevin Barnett #define CISS_CMD_STATUS_UNABORTABLE 0xc
6336c223761SKevin Barnett #define CISS_CMD_STATUS_TMF 0xd
6346c223761SKevin Barnett #define CISS_CMD_STATUS_AIO_DISABLED 0xe
6356c223761SKevin Barnett
63626b390abSKevin Barnett #define PQI_CMD_STATUS_ABORTED CISS_CMD_STATUS_ABORTED
63726b390abSKevin Barnett
6386c223761SKevin Barnett #define PQI_NUM_EVENT_QUEUE_ELEMENTS 32
6396c223761SKevin Barnett #define PQI_EVENT_OQ_ELEMENT_LENGTH sizeof(struct pqi_event_response)
6406c223761SKevin Barnett
6416c223761SKevin Barnett #define PQI_EVENT_TYPE_HOTPLUG 0x1
6426c223761SKevin Barnett #define PQI_EVENT_TYPE_HARDWARE 0x2
6436c223761SKevin Barnett #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4
6446c223761SKevin Barnett #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5
6454fd22c13SMahesh Rajashekhara #define PQI_EVENT_TYPE_OFA 0xfb
6466c223761SKevin Barnett #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd
6476c223761SKevin Barnett #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe
6486c223761SKevin Barnett
6496c223761SKevin Barnett #pragma pack()
6506c223761SKevin Barnett
6516c223761SKevin Barnett #define PQI_ERROR_BUFFER_ELEMENT_LENGTH \
6526c223761SKevin Barnett sizeof(struct pqi_raid_error_info)
6536c223761SKevin Barnett
6546c223761SKevin Barnett /* these values are based on our implementation */
6556c223761SKevin Barnett #define PQI_ADMIN_IQ_NUM_ELEMENTS 8
6566c223761SKevin Barnett #define PQI_ADMIN_OQ_NUM_ELEMENTS 20
6576c223761SKevin Barnett #define PQI_ADMIN_IQ_ELEMENT_LENGTH 64
6586c223761SKevin Barnett #define PQI_ADMIN_OQ_ELEMENT_LENGTH 64
6596c223761SKevin Barnett
6606c223761SKevin Barnett #define PQI_OPERATIONAL_IQ_ELEMENT_LENGTH 128
6616c223761SKevin Barnett #define PQI_OPERATIONAL_OQ_ELEMENT_LENGTH 16
6626c223761SKevin Barnett
6636c223761SKevin Barnett #define PQI_MIN_MSIX_VECTORS 1
6646c223761SKevin Barnett #define PQI_MAX_MSIX_VECTORS 64
6656c223761SKevin Barnett
6666c223761SKevin Barnett /* these values are defined by the PQI spec */
6676c223761SKevin Barnett #define PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE 255
6686c223761SKevin Barnett #define PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE 65535
6692708a256SKevin Barnett
6706c223761SKevin Barnett #define PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT 64
6716c223761SKevin Barnett #define PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT 16
6726c223761SKevin Barnett #define PQI_ADMIN_INDEX_ALIGNMENT 64
6736c223761SKevin Barnett #define PQI_OPERATIONAL_INDEX_ALIGNMENT 4
6746c223761SKevin Barnett
6756c223761SKevin Barnett #define PQI_MIN_OPERATIONAL_QUEUE_ID 1
6766c223761SKevin Barnett #define PQI_MAX_OPERATIONAL_QUEUE_ID 65535
6776c223761SKevin Barnett
6786c223761SKevin Barnett #define PQI_AIO_SERV_RESPONSE_COMPLETE 0
6796c223761SKevin Barnett #define PQI_AIO_SERV_RESPONSE_FAILURE 1
6806c223761SKevin Barnett #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2
6816c223761SKevin Barnett #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3
6826c223761SKevin Barnett #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4
6836c223761SKevin Barnett #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5
6846c223761SKevin Barnett
6856c223761SKevin Barnett #define PQI_AIO_STATUS_IO_ERROR 0x1
6866c223761SKevin Barnett #define PQI_AIO_STATUS_IO_ABORTED 0x2
6876c223761SKevin Barnett #define PQI_AIO_STATUS_NO_PATH_TO_DEVICE 0x3
6886c223761SKevin Barnett #define PQI_AIO_STATUS_INVALID_DEVICE 0x4
6896c223761SKevin Barnett #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe
6906c223761SKevin Barnett #define PQI_AIO_STATUS_UNDERRUN 0x51
6916c223761SKevin Barnett #define PQI_AIO_STATUS_OVERRUN 0x75
6926c223761SKevin Barnett
6936c223761SKevin Barnett typedef u32 pqi_index_t;
6946c223761SKevin Barnett
6956c223761SKevin Barnett /* SOP data direction flags */
6966c223761SKevin Barnett #define SOP_NO_DIRECTION_FLAG 0
6976c223761SKevin Barnett #define SOP_WRITE_FLAG 1 /* host writes data to Data-Out */
6986c223761SKevin Barnett /* buffer */
6996c223761SKevin Barnett #define SOP_READ_FLAG 2 /* host receives data from Data-In */
7006c223761SKevin Barnett /* buffer */
7016c223761SKevin Barnett #define SOP_BIDIRECTIONAL 3 /* data is transferred from the */
7026c223761SKevin Barnett /* Data-Out buffer and data is */
7036c223761SKevin Barnett /* transferred to the Data-In buffer */
7046c223761SKevin Barnett
7056c223761SKevin Barnett #define SOP_TASK_ATTRIBUTE_SIMPLE 0
7066c223761SKevin Barnett #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1
7076c223761SKevin Barnett #define SOP_TASK_ATTRIBUTE_ORDERED 2
7086c223761SKevin Barnett #define SOP_TASK_ATTRIBUTE_ACA 4
7096c223761SKevin Barnett
710b17f0486SKevin Barnett #define SOP_TMF_COMPLETE 0x0
7113406384bSMahesh Rajashekhara #define SOP_TMF_REJECTED 0x4
712b17f0486SKevin Barnett #define SOP_TMF_FUNCTION_SUCCEEDED 0x8
713*43cf3a6eSKevin Barnett #define SOP_TMF_INCORRECT_LOGICAL_UNIT 0x9
7146c223761SKevin Barnett
7156c223761SKevin Barnett /* additional CDB bytes usage field codes */
7166c223761SKevin Barnett #define SOP_ADDITIONAL_CDB_BYTES_0 0 /* 16-byte CDB */
7176c223761SKevin Barnett #define SOP_ADDITIONAL_CDB_BYTES_4 1 /* 20-byte CDB */
7186c223761SKevin Barnett #define SOP_ADDITIONAL_CDB_BYTES_8 2 /* 24-byte CDB */
7196c223761SKevin Barnett #define SOP_ADDITIONAL_CDB_BYTES_12 3 /* 28-byte CDB */
7206c223761SKevin Barnett #define SOP_ADDITIONAL_CDB_BYTES_16 4 /* 32-byte CDB */
7216c223761SKevin Barnett
7226c223761SKevin Barnett /*
7236c223761SKevin Barnett * The purpose of this structure is to obtain proper alignment of objects in
7246c223761SKevin Barnett * an admin queue pair.
7256c223761SKevin Barnett */
7266c223761SKevin Barnett struct pqi_admin_queues_aligned {
7276c223761SKevin Barnett __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
7286c223761SKevin Barnett u8 iq_element_array[PQI_ADMIN_IQ_ELEMENT_LENGTH]
7296c223761SKevin Barnett [PQI_ADMIN_IQ_NUM_ELEMENTS];
7306c223761SKevin Barnett __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
7316c223761SKevin Barnett u8 oq_element_array[PQI_ADMIN_OQ_ELEMENT_LENGTH]
7326c223761SKevin Barnett [PQI_ADMIN_OQ_NUM_ELEMENTS];
7336c223761SKevin Barnett __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t iq_ci;
7346c223761SKevin Barnett __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t oq_pi;
7356c223761SKevin Barnett };
7366c223761SKevin Barnett
7376c223761SKevin Barnett struct pqi_admin_queues {
7386c223761SKevin Barnett void *iq_element_array;
7396c223761SKevin Barnett void *oq_element_array;
740583891c9SKevin Barnett pqi_index_t __iomem *iq_ci;
741dac12fbcSKevin Barnett pqi_index_t __iomem *oq_pi;
7426c223761SKevin Barnett dma_addr_t iq_element_array_bus_addr;
7436c223761SKevin Barnett dma_addr_t oq_element_array_bus_addr;
7446c223761SKevin Barnett dma_addr_t iq_ci_bus_addr;
7456c223761SKevin Barnett dma_addr_t oq_pi_bus_addr;
7466c223761SKevin Barnett __le32 __iomem *iq_pi;
7476c223761SKevin Barnett pqi_index_t iq_pi_copy;
7486c223761SKevin Barnett __le32 __iomem *oq_ci;
7496c223761SKevin Barnett pqi_index_t oq_ci_copy;
7506c223761SKevin Barnett struct task_struct *task;
7516c223761SKevin Barnett u16 int_msg_num;
7526c223761SKevin Barnett };
7536c223761SKevin Barnett
7546c223761SKevin Barnett struct pqi_queue_group {
7556c223761SKevin Barnett struct pqi_ctrl_info *ctrl_info; /* backpointer */
7566c223761SKevin Barnett u16 iq_id[2];
7576c223761SKevin Barnett u16 oq_id;
7586c223761SKevin Barnett u16 int_msg_num;
7596c223761SKevin Barnett void *iq_element_array[2];
7606c223761SKevin Barnett void *oq_element_array;
7616c223761SKevin Barnett dma_addr_t iq_element_array_bus_addr[2];
7626c223761SKevin Barnett dma_addr_t oq_element_array_bus_addr;
7636c223761SKevin Barnett __le32 __iomem *iq_pi[2];
7646c223761SKevin Barnett pqi_index_t iq_pi_copy[2];
765dac12fbcSKevin Barnett pqi_index_t __iomem *iq_ci[2];
766dac12fbcSKevin Barnett pqi_index_t __iomem *oq_pi;
7676c223761SKevin Barnett dma_addr_t iq_ci_bus_addr[2];
7686c223761SKevin Barnett dma_addr_t oq_pi_bus_addr;
7696c223761SKevin Barnett __le32 __iomem *oq_ci;
7706c223761SKevin Barnett pqi_index_t oq_ci_copy;
7716c223761SKevin Barnett spinlock_t submit_lock[2]; /* protect submission queue */
7726c223761SKevin Barnett struct list_head request_list[2];
7736c223761SKevin Barnett };
7746c223761SKevin Barnett
7756c223761SKevin Barnett struct pqi_event_queue {
7766c223761SKevin Barnett u16 oq_id;
7776c223761SKevin Barnett u16 int_msg_num;
7786c223761SKevin Barnett void *oq_element_array;
779dac12fbcSKevin Barnett pqi_index_t __iomem *oq_pi;
7806c223761SKevin Barnett dma_addr_t oq_element_array_bus_addr;
7816c223761SKevin Barnett dma_addr_t oq_pi_bus_addr;
7826c223761SKevin Barnett __le32 __iomem *oq_ci;
7836c223761SKevin Barnett pqi_index_t oq_ci_copy;
7846c223761SKevin Barnett };
7856c223761SKevin Barnett
7866c223761SKevin Barnett #define PQI_DEFAULT_QUEUE_GROUP 0
7876c223761SKevin Barnett #define PQI_MAX_QUEUE_GROUPS PQI_MAX_MSIX_VECTORS
7886c223761SKevin Barnett
7896c223761SKevin Barnett struct pqi_encryption_info {
7906c223761SKevin Barnett u16 data_encryption_key_index;
7916c223761SKevin Barnett u32 encrypt_tweak_lower;
7926c223761SKevin Barnett u32 encrypt_tweak_upper;
7936c223761SKevin Barnett };
7946c223761SKevin Barnett
79598f87667SKevin Barnett #pragma pack(1)
79698f87667SKevin Barnett
79798f87667SKevin Barnett #define PQI_CONFIG_TABLE_SIGNATURE "CFGTABLE"
79898f87667SKevin Barnett #define PQI_CONFIG_TABLE_MAX_LENGTH ((u16)~0)
79998f87667SKevin Barnett
80098f87667SKevin Barnett /* configuration table section IDs */
801b212c251SKevin Barnett #define PQI_CONFIG_TABLE_ALL_SECTIONS (-1)
80298f87667SKevin Barnett #define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO 0
80398f87667SKevin Barnett #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES 1
80498f87667SKevin Barnett #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA 2
80598f87667SKevin Barnett #define PQI_CONFIG_TABLE_SECTION_DEBUG 3
80698f87667SKevin Barnett #define PQI_CONFIG_TABLE_SECTION_HEARTBEAT 4
8074fd22c13SMahesh Rajashekhara #define PQI_CONFIG_TABLE_SECTION_SOFT_RESET 5
80898f87667SKevin Barnett
80998f87667SKevin Barnett struct pqi_config_table {
81098f87667SKevin Barnett u8 signature[8]; /* "CFGTABLE" */
81198f87667SKevin Barnett __le32 first_section_offset; /* offset in bytes from the base */
81298f87667SKevin Barnett /* address of this table to the */
81398f87667SKevin Barnett /* first section */
81498f87667SKevin Barnett };
81598f87667SKevin Barnett
81698f87667SKevin Barnett struct pqi_config_table_section_header {
81798f87667SKevin Barnett __le16 section_id; /* as defined by the */
81898f87667SKevin Barnett /* PQI_CONFIG_TABLE_SECTION_* */
81998f87667SKevin Barnett /* manifest constants above */
82098f87667SKevin Barnett __le16 next_section_offset; /* offset in bytes from base */
82198f87667SKevin Barnett /* address of the table of the */
82298f87667SKevin Barnett /* next section or 0 if last entry */
82398f87667SKevin Barnett };
82498f87667SKevin Barnett
82598f87667SKevin Barnett struct pqi_config_table_general_info {
82698f87667SKevin Barnett struct pqi_config_table_section_header header;
82798f87667SKevin Barnett __le32 section_length; /* size of this section in bytes */
82898f87667SKevin Barnett /* including the section header */
82998f87667SKevin Barnett __le32 max_outstanding_requests; /* max. outstanding */
83098f87667SKevin Barnett /* commands supported by */
83198f87667SKevin Barnett /* the controller */
83298f87667SKevin Barnett __le32 max_sg_size; /* max. transfer size of a single */
83398f87667SKevin Barnett /* command */
83498f87667SKevin Barnett __le32 max_sg_per_request; /* max. number of scatter-gather */
83598f87667SKevin Barnett /* entries supported in a single */
83698f87667SKevin Barnett /* command */
83798f87667SKevin Barnett };
83898f87667SKevin Barnett
839b212c251SKevin Barnett struct pqi_config_table_firmware_features {
840b212c251SKevin Barnett struct pqi_config_table_section_header header;
841b212c251SKevin Barnett __le16 num_elements;
842b212c251SKevin Barnett u8 features_supported[];
843b212c251SKevin Barnett /* u8 features_requested_by_host[]; */
844b212c251SKevin Barnett /* u8 features_enabled[]; */
845f6cc2a77SKevin Barnett /* The 2 fields below are only valid if the MAX_KNOWN_FEATURE bit is set. */
846f6cc2a77SKevin Barnett /* __le16 firmware_max_known_feature; */
847f6cc2a77SKevin Barnett /* __le16 host_max_known_feature; */
848b212c251SKevin Barnett };
849b212c251SKevin Barnett
850b212c251SKevin Barnett #define PQI_FIRMWARE_FEATURE_OFA 0
851b212c251SKevin Barnett #define PQI_FIRMWARE_FEATURE_SMP 1
852f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_MAX_KNOWN_FEATURE 2
853f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_RAID_0_READ_BYPASS 3
854f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_RAID_1_READ_BYPASS 4
855f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_RAID_5_READ_BYPASS 5
856f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_RAID_6_READ_BYPASS 6
857f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_RAID_0_WRITE_BYPASS 7
858f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_RAID_1_WRITE_BYPASS 8
859f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_RAID_5_WRITE_BYPASS 9
860f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_RAID_6_WRITE_BYPASS 10
8614fd22c13SMahesh Rajashekhara #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE 11
862f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_UNIQUE_SATA_WWN 12
86321432010Skoshyaji #define PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT 13
864c2922f17SMurthy Bhat #define PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT 14
865f6cc2a77SKevin Barnett #define PQI_FIRMWARE_FEATURE_RAID_BYPASS_ON_ENCRYPTED_NVME 15
8667a84a821SKevin Barnett #define PQI_FIRMWARE_FEATURE_UNIQUE_WWID_IN_REPORT_PHYS_LUN 16
8675d1f03e6SMurthy Bhat #define PQI_FIRMWARE_FEATURE_FW_TRIAGE 17
86828ca6d87SMike McGowen #define PQI_FIRMWARE_FEATURE_RPL_EXTENDED_FORMAT_4_5 18
869904f2bfdSKumar Meiyappan #define PQI_FIRMWARE_FEATURE_MULTI_LUN_DEVICE_SUPPORT 21
870904f2bfdSKumar Meiyappan #define PQI_FIRMWARE_FEATURE_MAXIMUM 21
871b212c251SKevin Barnett
87298f87667SKevin Barnett struct pqi_config_table_debug {
87398f87667SKevin Barnett struct pqi_config_table_section_header header;
87498f87667SKevin Barnett __le32 scratchpad;
87598f87667SKevin Barnett };
87698f87667SKevin Barnett
87798f87667SKevin Barnett struct pqi_config_table_heartbeat {
87898f87667SKevin Barnett struct pqi_config_table_section_header header;
87998f87667SKevin Barnett __le32 heartbeat_counter;
88098f87667SKevin Barnett };
88198f87667SKevin Barnett
8824fd22c13SMahesh Rajashekhara struct pqi_config_table_soft_reset {
8834fd22c13SMahesh Rajashekhara struct pqi_config_table_section_header header;
8844fd22c13SMahesh Rajashekhara u8 soft_reset_status;
8854fd22c13SMahesh Rajashekhara };
8864fd22c13SMahesh Rajashekhara
8874fd22c13SMahesh Rajashekhara #define PQI_SOFT_RESET_INITIATE 0x1
8884fd22c13SMahesh Rajashekhara #define PQI_SOFT_RESET_ABORT 0x2
8894fd22c13SMahesh Rajashekhara
8904fd22c13SMahesh Rajashekhara enum pqi_soft_reset_status {
8914fd22c13SMahesh Rajashekhara RESET_INITIATE_FIRMWARE,
8924fd22c13SMahesh Rajashekhara RESET_INITIATE_DRIVER,
8934fd22c13SMahesh Rajashekhara RESET_ABORT,
8944fd22c13SMahesh Rajashekhara RESET_NORESPONSE,
8954fd22c13SMahesh Rajashekhara RESET_TIMEDOUT
8964fd22c13SMahesh Rajashekhara };
8974fd22c13SMahesh Rajashekhara
898336b6819SKevin Barnett union pqi_reset_register {
899336b6819SKevin Barnett struct {
900336b6819SKevin Barnett u32 reset_type : 3;
901336b6819SKevin Barnett u32 reserved : 2;
902336b6819SKevin Barnett u32 reset_action : 3;
903336b6819SKevin Barnett u32 hold_in_pd1 : 1;
904336b6819SKevin Barnett u32 reserved2 : 23;
905336b6819SKevin Barnett } bits;
906336b6819SKevin Barnett u32 all_bits;
907336b6819SKevin Barnett };
908336b6819SKevin Barnett
909336b6819SKevin Barnett #define PQI_RESET_ACTION_RESET 0x1
910336b6819SKevin Barnett
911336b6819SKevin Barnett #define PQI_RESET_TYPE_NO_RESET 0x0
912336b6819SKevin Barnett #define PQI_RESET_TYPE_SOFT_RESET 0x1
913336b6819SKevin Barnett #define PQI_RESET_TYPE_FIRM_RESET 0x2
914336b6819SKevin Barnett #define PQI_RESET_TYPE_HARD_RESET 0x3
915336b6819SKevin Barnett
916336b6819SKevin Barnett #define PQI_RESET_ACTION_COMPLETED 0x2
917336b6819SKevin Barnett
918336b6819SKevin Barnett #define PQI_RESET_POLL_INTERVAL_MSECS 100
919336b6819SKevin Barnett
9206c223761SKevin Barnett #define PQI_MAX_OUTSTANDING_REQUESTS ((u32)~0)
921d727a776SKevin Barnett #define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP 32
922eeee4107SYadan Fan #define PQI_MAX_TRANSFER_SIZE (1024U * 1024U)
923d727a776SKevin Barnett #define PQI_MAX_TRANSFER_SIZE_KDUMP (512 * 1024U)
9246c223761SKevin Barnett
9256c223761SKevin Barnett #define RAID_MAP_MAX_ENTRIES 1024
9265d8fbce0SMike McGowen #define RAID_MAP_MAX_DATA_DISKS_PER_ROW 128
9276c223761SKevin Barnett
9286c223761SKevin Barnett #define PQI_PHYSICAL_DEVICE_BUS 0
9296c223761SKevin Barnett #define PQI_RAID_VOLUME_BUS 1
9306c223761SKevin Barnett #define PQI_HBA_BUS 2
931bd10cf0bSKevin Barnett #define PQI_EXTERNAL_RAID_VOLUME_BUS 3
932bd10cf0bSKevin Barnett #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS
933522bc026SDave Carroll #define PQI_VSEP_CISS_BTL 379
9346c223761SKevin Barnett
9356c223761SKevin Barnett struct report_lun_header {
9366c223761SKevin Barnett __be32 list_length;
937694c5d5bSKevin Barnett u8 flags;
9386c223761SKevin Barnett u8 reserved[3];
9396c223761SKevin Barnett };
9406c223761SKevin Barnett
941694c5d5bSKevin Barnett /* for flags field of struct report_lun_header */
942694c5d5bSKevin Barnett #define CISS_REPORT_LOG_FLAG_UNIQUE_LUN_ID (1 << 0)
943694c5d5bSKevin Barnett #define CISS_REPORT_LOG_FLAG_QUEUE_DEPTH (1 << 5)
944694c5d5bSKevin Barnett #define CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX (1 << 6)
945694c5d5bSKevin Barnett
94628ca6d87SMike McGowen #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_2 0x2
94728ca6d87SMike McGowen #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_4 0x4
94828ca6d87SMike McGowen #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_MASK 0xf
949694c5d5bSKevin Barnett
95028ca6d87SMike McGowen struct report_log_lun {
9516c223761SKevin Barnett u8 lunid[8];
9526c223761SKevin Barnett u8 volume_id[16];
9536c223761SKevin Barnett };
9546c223761SKevin Barnett
95528ca6d87SMike McGowen struct report_log_lun_list {
9566c223761SKevin Barnett struct report_lun_header header;
957ead82126SGustavo A. R. Silva struct report_log_lun lun_entries[];
9586c223761SKevin Barnett };
9596c223761SKevin Barnett
96028ca6d87SMike McGowen struct report_phys_lun_8byte_wwid {
9616c223761SKevin Barnett u8 lunid[8];
9626c223761SKevin Barnett __be64 wwid;
9636c223761SKevin Barnett u8 device_type;
9646c223761SKevin Barnett u8 device_flags;
9656c223761SKevin Barnett u8 lun_count; /* number of LUNs in a multi-LUN device */
9666c223761SKevin Barnett u8 redundant_paths;
9676c223761SKevin Barnett u32 aio_handle;
9686c223761SKevin Barnett };
9696c223761SKevin Barnett
97028ca6d87SMike McGowen struct report_phys_lun_16byte_wwid {
97128ca6d87SMike McGowen u8 lunid[8];
97228ca6d87SMike McGowen u8 wwid[16];
97328ca6d87SMike McGowen u8 device_type;
97428ca6d87SMike McGowen u8 device_flags;
97528ca6d87SMike McGowen u8 lun_count; /* number of LUNs in a multi-LUN device */
97628ca6d87SMike McGowen u8 redundant_paths;
97728ca6d87SMike McGowen u32 aio_handle;
97828ca6d87SMike McGowen };
97928ca6d87SMike McGowen
9806c223761SKevin Barnett /* for device_flags field of struct report_phys_lun_extended_entry */
981694c5d5bSKevin Barnett #define CISS_REPORT_PHYS_DEV_FLAG_AIO_ENABLED 0x8
9826c223761SKevin Barnett
98328ca6d87SMike McGowen struct report_phys_lun_8byte_wwid_list {
9846c223761SKevin Barnett struct report_lun_header header;
9856f0a92fdSGustavo A. R. Silva struct report_phys_lun_8byte_wwid lun_entries[];
98628ca6d87SMike McGowen };
98728ca6d87SMike McGowen
98828ca6d87SMike McGowen struct report_phys_lun_16byte_wwid_list {
98928ca6d87SMike McGowen struct report_lun_header header;
9906f0a92fdSGustavo A. R. Silva struct report_phys_lun_16byte_wwid lun_entries[];
9916c223761SKevin Barnett };
9926c223761SKevin Barnett
9936c223761SKevin Barnett struct raid_map_disk_data {
9946c223761SKevin Barnett u32 aio_handle;
9956c223761SKevin Barnett u8 xor_mult[2];
9966c223761SKevin Barnett u8 reserved[2];
9976c223761SKevin Barnett };
9986c223761SKevin Barnett
999694c5d5bSKevin Barnett /* for flags field of RAID map */
10006c223761SKevin Barnett #define RAID_MAP_ENCRYPTION_ENABLED 0x1
10016c223761SKevin Barnett
10026c223761SKevin Barnett struct raid_map {
10036c223761SKevin Barnett __le32 structure_size; /* size of entire structure in bytes */
10046c223761SKevin Barnett __le32 volume_blk_size; /* bytes / block in the volume */
10056c223761SKevin Barnett __le64 volume_blk_cnt; /* logical blocks on the volume */
10066c223761SKevin Barnett u8 phys_blk_shift; /* shift factor to convert between */
10076c223761SKevin Barnett /* units of logical blocks and */
10086c223761SKevin Barnett /* physical disk blocks */
10096c223761SKevin Barnett u8 parity_rotation_shift; /* shift factor to convert between */
10106c223761SKevin Barnett /* units of logical stripes and */
10116c223761SKevin Barnett /* physical stripes */
10126c223761SKevin Barnett __le16 strip_size; /* blocks used on each disk / stripe */
10136c223761SKevin Barnett __le64 disk_starting_blk; /* first disk block used in volume */
10146c223761SKevin Barnett __le64 disk_blk_cnt; /* disk blocks used by volume / disk */
10156c223761SKevin Barnett __le16 data_disks_per_row; /* data disk entries / row in the map */
10166c223761SKevin Barnett __le16 metadata_disks_per_row; /* mirror/parity disk entries / row */
10176c223761SKevin Barnett /* in the map */
10186c223761SKevin Barnett __le16 row_cnt; /* rows in each layout map */
10196c223761SKevin Barnett __le16 layout_map_count; /* layout maps (1 map per */
10206c223761SKevin Barnett /* mirror parity group) */
10216c223761SKevin Barnett __le16 flags;
10226c223761SKevin Barnett __le16 data_encryption_key_index;
10236c223761SKevin Barnett u8 reserved[16];
10246c223761SKevin Barnett struct raid_map_disk_data disk_data[RAID_MAP_MAX_ENTRIES];
10256c223761SKevin Barnett };
10266c223761SKevin Barnett
10276c223761SKevin Barnett #pragma pack()
10286c223761SKevin Barnett
1029281a817fSDon Brace struct pqi_scsi_dev_raid_map_data {
1030281a817fSDon Brace bool is_write;
1031281a817fSDon Brace u8 raid_level;
1032281a817fSDon Brace u32 map_index;
1033281a817fSDon Brace u64 first_block;
1034281a817fSDon Brace u64 last_block;
1035281a817fSDon Brace u32 data_length;
1036281a817fSDon Brace u32 block_cnt;
1037281a817fSDon Brace u32 blocks_per_row;
1038281a817fSDon Brace u64 first_row;
1039281a817fSDon Brace u64 last_row;
1040281a817fSDon Brace u32 first_row_offset;
1041281a817fSDon Brace u32 last_row_offset;
1042281a817fSDon Brace u32 first_column;
1043281a817fSDon Brace u32 last_column;
1044281a817fSDon Brace u64 r5or6_first_row;
1045281a817fSDon Brace u64 r5or6_last_row;
1046281a817fSDon Brace u32 r5or6_first_row_offset;
1047281a817fSDon Brace u32 r5or6_last_row_offset;
1048281a817fSDon Brace u32 r5or6_first_column;
1049281a817fSDon Brace u32 r5or6_last_column;
1050281a817fSDon Brace u16 data_disks_per_row;
1051281a817fSDon Brace u32 total_disks_per_row;
1052281a817fSDon Brace u16 layout_map_count;
1053281a817fSDon Brace u32 stripesize;
1054281a817fSDon Brace u16 strip_size;
1055281a817fSDon Brace u32 first_group;
1056281a817fSDon Brace u32 last_group;
1057281a817fSDon Brace u32 map_row;
1058281a817fSDon Brace u32 aio_handle;
1059281a817fSDon Brace u64 disk_block;
1060281a817fSDon Brace u32 disk_block_cnt;
1061281a817fSDon Brace u8 cdb[16];
1062281a817fSDon Brace u8 cdb_length;
1063281a817fSDon Brace
1064281a817fSDon Brace /* RAID 1 specific */
1065281a817fSDon Brace #define NUM_RAID1_MAP_ENTRIES 3
1066281a817fSDon Brace u32 num_it_nexus_entries;
1067281a817fSDon Brace u32 it_nexus[NUM_RAID1_MAP_ENTRIES];
1068281a817fSDon Brace
1069583891c9SKevin Barnett /* RAID 5 / RAID 6 specific */
1070281a817fSDon Brace u32 p_parity_it_nexus; /* aio_handle */
1071281a817fSDon Brace u32 q_parity_it_nexus; /* aio_handle */
1072281a817fSDon Brace u8 xor_mult;
1073281a817fSDon Brace u64 row;
1074281a817fSDon Brace u64 stripe_lba;
1075281a817fSDon Brace u32 p_index;
1076281a817fSDon Brace u32 q_index;
1077281a817fSDon Brace };
1078281a817fSDon Brace
10796c223761SKevin Barnett #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
10806c223761SKevin Barnett
1081c7ffedb3SDon Brace #define NUM_STREAMS_PER_LUN 8
1082c7ffedb3SDon Brace
1083c7ffedb3SDon Brace struct pqi_stream_data {
1084c7ffedb3SDon Brace u64 next_lba;
1085c7ffedb3SDon Brace u32 last_accessed;
1086c7ffedb3SDon Brace };
1087c7ffedb3SDon Brace
1088904f2bfdSKumar Meiyappan #define PQI_MAX_LUNS_PER_DEVICE 256
1089904f2bfdSKumar Meiyappan
1090153c45ddSKevin Barnett struct pqi_tmf_work {
1091153c45ddSKevin Barnett struct work_struct work_struct;
1092153c45ddSKevin Barnett struct scsi_cmnd *scmd;
1093153c45ddSKevin Barnett struct pqi_ctrl_info *ctrl_info;
1094153c45ddSKevin Barnett struct pqi_scsi_dev *device;
1095153c45ddSKevin Barnett u8 lun;
1096153c45ddSKevin Barnett u8 scsi_opcode;
1097153c45ddSKevin Barnett };
1098153c45ddSKevin Barnett
10996c223761SKevin Barnett struct pqi_scsi_dev {
11008946ea28SJulia Lawall int devtype; /* as reported by INQUIRY command */
11016c223761SKevin Barnett u8 device_type; /* as reported by */
11026c223761SKevin Barnett /* BMIC_IDENTIFY_PHYSICAL_DEVICE */
11036c223761SKevin Barnett /* only valid for devtype = TYPE_DISK */
11046c223761SKevin Barnett int bus;
11056c223761SKevin Barnett int target;
11066c223761SKevin Barnett int lun;
11076c223761SKevin Barnett u8 scsi3addr[8];
110828ca6d87SMike McGowen u8 wwid[16];
11096c223761SKevin Barnett u8 volume_id[16];
11106c223761SKevin Barnett u8 is_physical_device : 1;
1111bd10cf0bSKevin Barnett u8 is_external_raid_device : 1;
11123d46a59aSDon Brace u8 is_expander_smp_device : 1;
11136c223761SKevin Barnett u8 target_lun_valid : 1;
11146c223761SKevin Barnett u8 device_gone : 1;
11156c223761SKevin Barnett u8 new_device : 1;
11166c223761SKevin Barnett u8 keep_device : 1;
11176c223761SKevin Barnett u8 volume_offline : 1;
1118244ca45eSMahesh Rajashekhara u8 rescan : 1;
1119d4dc6aeaSKevin Barnett u8 ignore_device : 1;
11202eddf98dSKevin Barnett u8 erase_in_progress : 1;
1121376fb880SKevin Barnett bool aio_enabled; /* only valid for physical disks */
11221e46731eSMahesh Rajashekhara bool in_remove;
1123153c45ddSKevin Barnett bool in_reset[PQI_MAX_LUNS_PER_DEVICE];
11247561a7e4SKevin Barnett bool device_offline;
11256c223761SKevin Barnett u8 vendor[8]; /* bytes 8-15 of inquiry data */
11266c223761SKevin Barnett u8 model[16]; /* bytes 16-31 of inquiry data */
11276c223761SKevin Barnett u64 sas_address;
11286c223761SKevin Barnett u8 raid_level;
11296c223761SKevin Barnett u16 queue_depth; /* max. queue_depth for this device */
11306c223761SKevin Barnett u16 advertised_queue_depth;
11316c223761SKevin Barnett u32 aio_handle;
11326c223761SKevin Barnett u8 volume_status;
11336c223761SKevin Barnett u8 active_path_index;
11346c223761SKevin Barnett u8 path_map;
11356c223761SKevin Barnett u8 bay;
11362d2ad4bcSGilbert Wu u8 box_index;
11372d2ad4bcSGilbert Wu u8 phys_box_on_bus;
11382d2ad4bcSGilbert Wu u8 phy_connected_dev_type;
11396c223761SKevin Barnett u8 box[8];
11406c223761SKevin Barnett u16 phys_connector[8];
1141ec504b23SMurthy Bhat u8 phy_id;
11422a47834dSGilbert Wu u8 ncq_prio_enable;
11432a47834dSGilbert Wu u8 ncq_prio_support;
1144cc9befcbSKumar Meiyappan u8 lun_count;
1145588a63feSKevin Barnett bool raid_bypass_configured; /* RAID bypass configured */
1146588a63feSKevin Barnett bool raid_bypass_enabled; /* RAID bypass enabled */
11475d8fbce0SMike McGowen u32 next_bypass_group[RAID_MAP_MAX_DATA_DISKS_PER_ROW];
1148588a63feSKevin Barnett struct raid_map *raid_map; /* RAID bypass map */
1149f6cc2a77SKevin Barnett u32 max_transfer_encrypted;
11506c223761SKevin Barnett
11516c223761SKevin Barnett struct pqi_sas_port *sas_port;
11526c223761SKevin Barnett struct scsi_device *sdev;
11536c223761SKevin Barnett
11546c223761SKevin Barnett struct list_head scsi_device_list_entry;
11556c223761SKevin Barnett struct list_head new_device_list_entry;
11566c223761SKevin Barnett struct list_head add_list_entry;
11576c223761SKevin Barnett struct list_head delete_list_entry;
11587561a7e4SKevin Barnett
1159c7ffedb3SDon Brace struct pqi_stream_data stream_data[NUM_STREAMS_PER_LUN];
1160904f2bfdSKumar Meiyappan atomic_t scsi_cmds_outstanding[PQI_MAX_LUNS_PER_DEVICE];
116180d560d9SMike McGowen unsigned int raid_bypass_cnt;
1162153c45ddSKevin Barnett
1163153c45ddSKevin Barnett struct pqi_tmf_work tmf_work[PQI_MAX_LUNS_PER_DEVICE];
11646c223761SKevin Barnett };
11656c223761SKevin Barnett
11666c223761SKevin Barnett /* VPD inquiry pages */
11676c223761SKevin Barnett #define CISS_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */
1168588a63feSKevin Barnett #define CISS_VPD_LV_BYPASS_STATUS 0xc2 /* vendor-specific page */
11696c223761SKevin Barnett #define CISS_VPD_LV_STATUS 0xc3 /* vendor-specific page */
11706c223761SKevin Barnett
11716c223761SKevin Barnett #define VPD_PAGE (1 << 8)
11726c223761SKevin Barnett
11736c223761SKevin Barnett #pragma pack(1)
11746c223761SKevin Barnett
11756c223761SKevin Barnett /* structure for CISS_VPD_LV_STATUS */
11766c223761SKevin Barnett struct ciss_vpd_logical_volume_status {
11776c223761SKevin Barnett u8 peripheral_info;
11786c223761SKevin Barnett u8 page_code;
11796c223761SKevin Barnett u8 reserved;
11806c223761SKevin Barnett u8 page_length;
11816c223761SKevin Barnett u8 volume_status;
11826c223761SKevin Barnett u8 reserved2[3];
11836c223761SKevin Barnett __be32 flags;
11846c223761SKevin Barnett };
11856c223761SKevin Barnett
11866c223761SKevin Barnett #pragma pack()
11876c223761SKevin Barnett
11886c223761SKevin Barnett /* constants for volume_status field of ciss_vpd_logical_volume_status */
11896c223761SKevin Barnett #define CISS_LV_OK 0
11906c223761SKevin Barnett #define CISS_LV_FAILED 1
11916c223761SKevin Barnett #define CISS_LV_NOT_CONFIGURED 2
11926c223761SKevin Barnett #define CISS_LV_DEGRADED 3
11936c223761SKevin Barnett #define CISS_LV_READY_FOR_RECOVERY 4
11946c223761SKevin Barnett #define CISS_LV_UNDERGOING_RECOVERY 5
11956c223761SKevin Barnett #define CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED 6
11966c223761SKevin Barnett #define CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM 7
11976c223761SKevin Barnett #define CISS_LV_HARDWARE_OVERHEATING 8
11986c223761SKevin Barnett #define CISS_LV_HARDWARE_HAS_OVERHEATED 9
11996c223761SKevin Barnett #define CISS_LV_UNDERGOING_EXPANSION 10
12006c223761SKevin Barnett #define CISS_LV_NOT_AVAILABLE 11
12016c223761SKevin Barnett #define CISS_LV_QUEUED_FOR_EXPANSION 12
12026c223761SKevin Barnett #define CISS_LV_DISABLED_SCSI_ID_CONFLICT 13
12036c223761SKevin Barnett #define CISS_LV_EJECTED 14
12046c223761SKevin Barnett #define CISS_LV_UNDERGOING_ERASE 15
12056c223761SKevin Barnett /* state 16 not used */
12066c223761SKevin Barnett #define CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD 17
12076c223761SKevin Barnett #define CISS_LV_UNDERGOING_RPI 18
12086c223761SKevin Barnett #define CISS_LV_PENDING_RPI 19
12096c223761SKevin Barnett #define CISS_LV_ENCRYPTED_NO_KEY 20
12106c223761SKevin Barnett /* state 21 not used */
12116c223761SKevin Barnett #define CISS_LV_UNDERGOING_ENCRYPTION 22
12126c223761SKevin Barnett #define CISS_LV_UNDERGOING_ENCRYPTION_REKEYING 23
12136c223761SKevin Barnett #define CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 24
12146c223761SKevin Barnett #define CISS_LV_PENDING_ENCRYPTION 25
12156c223761SKevin Barnett #define CISS_LV_PENDING_ENCRYPTION_REKEYING 26
12166c223761SKevin Barnett #define CISS_LV_NOT_SUPPORTED 27
12176c223761SKevin Barnett #define CISS_LV_STATUS_UNAVAILABLE 255
12186c223761SKevin Barnett
12196c223761SKevin Barnett /* constants for flags field of ciss_vpd_logical_volume_status */
12206c223761SKevin Barnett #define CISS_LV_FLAGS_NO_HOST_IO 0x1 /* volume not available for */
12216c223761SKevin Barnett /* host I/O */
12226c223761SKevin Barnett
12236c223761SKevin Barnett /* for SAS hosts and SAS expanders */
12246c223761SKevin Barnett struct pqi_sas_node {
12256c223761SKevin Barnett struct device *parent_dev;
12266c223761SKevin Barnett struct list_head port_list_head;
12276c223761SKevin Barnett };
12286c223761SKevin Barnett
12296c223761SKevin Barnett struct pqi_sas_port {
12306c223761SKevin Barnett struct list_head port_list_entry;
12316c223761SKevin Barnett u64 sas_address;
12323d46a59aSDon Brace struct pqi_scsi_dev *device;
12336c223761SKevin Barnett struct sas_port *port;
12346c223761SKevin Barnett int next_phy_index;
12356c223761SKevin Barnett struct list_head phy_list_head;
12366c223761SKevin Barnett struct pqi_sas_node *parent_node;
12376c223761SKevin Barnett struct sas_rphy *rphy;
12386c223761SKevin Barnett };
12396c223761SKevin Barnett
12406c223761SKevin Barnett struct pqi_sas_phy {
12416c223761SKevin Barnett struct list_head phy_list_entry;
12426c223761SKevin Barnett struct sas_phy *phy;
12436c223761SKevin Barnett struct pqi_sas_port *parent_port;
12446c223761SKevin Barnett bool added_to_port;
12456c223761SKevin Barnett };
12466c223761SKevin Barnett
12476c223761SKevin Barnett struct pqi_io_request {
12486c223761SKevin Barnett atomic_t refcount;
12496c223761SKevin Barnett u16 index;
12506c223761SKevin Barnett void (*io_complete_callback)(struct pqi_io_request *io_request,
12516c223761SKevin Barnett void *context);
12526c223761SKevin Barnett void *context;
1253376fb880SKevin Barnett u8 raid_bypass : 1;
12546c223761SKevin Barnett int status;
1255376fb880SKevin Barnett struct pqi_queue_group *queue_group;
12566c223761SKevin Barnett struct scsi_cmnd *scmd;
12576c223761SKevin Barnett void *error_info;
12586c223761SKevin Barnett struct pqi_sg_descriptor *sg_chain_buffer;
12596c223761SKevin Barnett dma_addr_t sg_chain_buffer_dma_handle;
12606c223761SKevin Barnett void *iu;
12616c223761SKevin Barnett struct list_head request_list_entry;
12626c223761SKevin Barnett };
12636c223761SKevin Barnett
12644fd22c13SMahesh Rajashekhara #define PQI_NUM_SUPPORTED_EVENTS 7
12656c223761SKevin Barnett
12666c223761SKevin Barnett struct pqi_event {
12676c223761SKevin Barnett bool pending;
12686c223761SKevin Barnett u8 event_type;
126906b41e0dSKevin Barnett u16 event_id;
127006b41e0dSKevin Barnett u32 additional_event_id;
12716c223761SKevin Barnett };
12726c223761SKevin Barnett
12735e6429dfSKevin Barnett #define PQI_RESERVED_IO_SLOTS_LUN_RESET 1
12745e6429dfSKevin Barnett #define PQI_RESERVED_IO_SLOTS_EVENT_ACK PQI_NUM_SUPPORTED_EVENTS
12755e6429dfSKevin Barnett #define PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS 3
12765e6429dfSKevin Barnett #define PQI_RESERVED_IO_SLOTS \
12775e6429dfSKevin Barnett (PQI_RESERVED_IO_SLOTS_LUN_RESET + PQI_RESERVED_IO_SLOTS_EVENT_ACK + \
12785e6429dfSKevin Barnett PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS)
12795e6429dfSKevin Barnett
12802708a256SKevin Barnett #define PQI_CTRL_PRODUCT_ID_GEN1 0
12812708a256SKevin Barnett #define PQI_CTRL_PRODUCT_ID_GEN2 7
12822708a256SKevin Barnett #define PQI_CTRL_PRODUCT_REVISION_A 0
12832708a256SKevin Barnett #define PQI_CTRL_PRODUCT_REVISION_B 1
12842708a256SKevin Barnett
1285331f7e99SSagar Biradar enum pqi_ctrl_removal_state {
1286331f7e99SSagar Biradar PQI_CTRL_PRESENT = 0,
1287331f7e99SSagar Biradar PQI_CTRL_GRACEFUL_REMOVAL,
1288331f7e99SSagar Biradar PQI_CTRL_SURPRISE_REMOVAL
1289331f7e99SSagar Biradar };
1290331f7e99SSagar Biradar
12916c223761SKevin Barnett struct pqi_ctrl_info {
12926c223761SKevin Barnett unsigned int ctrl_id;
12936c223761SKevin Barnett struct pci_dev *pci_dev;
1294598bef8dSKevin Barnett char firmware_version[32];
12956d90615fSMurthy Bhat char serial_number[17];
12966d90615fSMurthy Bhat char model[17];
12976d90615fSMurthy Bhat char vendor[9];
12982708a256SKevin Barnett u8 product_id;
12992708a256SKevin Barnett u8 product_revision;
13006c223761SKevin Barnett void __iomem *iomem_base;
13016c223761SKevin Barnett struct pqi_ctrl_registers __iomem *registers;
13026c223761SKevin Barnett struct pqi_device_registers __iomem *pqi_registers;
13036c223761SKevin Barnett u32 max_sg_entries;
13046c223761SKevin Barnett u32 config_table_offset;
13056c223761SKevin Barnett u32 config_table_length;
13066c223761SKevin Barnett u16 max_inbound_queues;
13076c223761SKevin Barnett u16 max_elements_per_iq;
13086c223761SKevin Barnett u16 max_iq_element_length;
13096c223761SKevin Barnett u16 max_outbound_queues;
13106c223761SKevin Barnett u16 max_elements_per_oq;
13116c223761SKevin Barnett u16 max_oq_element_length;
13126c223761SKevin Barnett u32 max_transfer_size;
13136c223761SKevin Barnett u32 max_outstanding_requests;
13146c223761SKevin Barnett u32 max_io_slots;
13156c223761SKevin Barnett unsigned int scsi_ml_can_queue;
13166c223761SKevin Barnett unsigned short sg_tablesize;
13176c223761SKevin Barnett unsigned int max_sectors;
13186c223761SKevin Barnett u32 error_buffer_length;
13196c223761SKevin Barnett void *error_buffer;
13206c223761SKevin Barnett dma_addr_t error_buffer_dma_handle;
13216c223761SKevin Barnett size_t sg_chain_buffer_length;
13226c223761SKevin Barnett unsigned int num_queue_groups;
13236c223761SKevin Barnett u16 num_elements_per_iq;
13246c223761SKevin Barnett u16 num_elements_per_oq;
13256c223761SKevin Barnett u16 max_inbound_iu_length_per_firmware;
13266c223761SKevin Barnett u16 max_inbound_iu_length;
13276c223761SKevin Barnett unsigned int max_sg_per_iu;
13286702d2c4SDon Brace unsigned int max_sg_per_r56_iu;
13296c223761SKevin Barnett void *admin_queue_memory_base;
13306c223761SKevin Barnett u32 admin_queue_memory_length;
13316c223761SKevin Barnett dma_addr_t admin_queue_memory_base_dma_handle;
13326c223761SKevin Barnett void *queue_memory_base;
13336c223761SKevin Barnett u32 queue_memory_length;
13346c223761SKevin Barnett dma_addr_t queue_memory_base_dma_handle;
13356c223761SKevin Barnett struct pqi_admin_queues admin_queues;
13366c223761SKevin Barnett struct pqi_queue_group queue_groups[PQI_MAX_QUEUE_GROUPS];
13376c223761SKevin Barnett struct pqi_event_queue event_queue;
1338061ef06aSKevin Barnett enum pqi_irq_mode irq_mode;
13396c223761SKevin Barnett int max_msix_vectors;
13406c223761SKevin Barnett int num_msix_vectors_enabled;
13416c223761SKevin Barnett int num_msix_vectors_initialized;
13426c223761SKevin Barnett int event_irq;
13436c223761SKevin Barnett struct Scsi_Host *scsi_host;
13446c223761SKevin Barnett
13456c223761SKevin Barnett struct mutex scan_mutex;
13467561a7e4SKevin Barnett struct mutex lun_reset_mutex;
13477561a7e4SKevin Barnett bool controller_online;
13487561a7e4SKevin Barnett bool block_requests;
13499fa82023SKevin Barnett bool scan_blocked;
13506c223761SKevin Barnett u8 inbound_spanning_supported : 1;
13516c223761SKevin Barnett u8 outbound_spanning_supported : 1;
13526c223761SKevin Barnett u8 pqi_mode_enabled : 1;
1353336b6819SKevin Barnett u8 pqi_reset_quiesce_supported : 1;
13544fd22c13SMahesh Rajashekhara u8 soft_reset_handshake_supported : 1;
135521432010Skoshyaji u8 raid_iu_timeout_supported : 1;
1356c2922f17SMurthy Bhat u8 tmf_iu_timeout_supported : 1;
13575d1f03e6SMurthy Bhat u8 firmware_triage_supported : 1;
135828ca6d87SMike McGowen u8 rpl_extended_format_4_5_supported : 1;
1359904f2bfdSKumar Meiyappan u8 multi_lun_device_supported : 1;
13607a012c23SDon Brace u8 enable_r1_writes : 1;
13616702d2c4SDon Brace u8 enable_r5_writes : 1;
13626702d2c4SDon Brace u8 enable_r6_writes : 1;
1363f6cc2a77SKevin Barnett u8 lv_drive_type_mix_valid : 1;
1364c7ffedb3SDon Brace u8 enable_stream_detection : 1;
1365cf15c3e7SMike McGowen u8 disable_managed_interrupts : 1;
1366f6cc2a77SKevin Barnett u8 ciss_report_log_flags;
1367f6cc2a77SKevin Barnett u32 max_transfer_encrypted_sas_sata;
1368f6cc2a77SKevin Barnett u32 max_transfer_encrypted_nvme;
1369f6cc2a77SKevin Barnett u32 max_write_raid_5_6;
1370f6cc2a77SKevin Barnett u32 max_write_raid_1_10_2drive;
1371f6cc2a77SKevin Barnett u32 max_write_raid_1_10_3drive;
1372d2c7583fSDon Brace int numa_node;
13736c223761SKevin Barnett
13746c223761SKevin Barnett struct list_head scsi_device_list;
13756c223761SKevin Barnett spinlock_t scsi_device_list_lock;
13766c223761SKevin Barnett
13776c223761SKevin Barnett struct delayed_work rescan_work;
13786c223761SKevin Barnett struct delayed_work update_time_work;
13796c223761SKevin Barnett
13806c223761SKevin Barnett struct pqi_sas_node *sas_host;
13816c223761SKevin Barnett u64 sas_address;
13826c223761SKevin Barnett
13836c223761SKevin Barnett struct pqi_io_request *io_request_pool;
13846a50d6adSKevin Barnett struct pqi_event events[PQI_NUM_SUPPORTED_EVENTS];
13856c223761SKevin Barnett struct work_struct event_work;
13866c223761SKevin Barnett
13876c223761SKevin Barnett atomic_t num_interrupts;
13886c223761SKevin Barnett int previous_num_interrupts;
138998f87667SKevin Barnett u32 previous_heartbeat_count;
139098f87667SKevin Barnett __le32 __iomem *heartbeat_counter;
13914fd22c13SMahesh Rajashekhara u8 __iomem *soft_reset_status;
13926c223761SKevin Barnett struct timer_list heartbeat_timer;
13935f310425SKevin Barnett struct work_struct ctrl_offline_work;
13946c223761SKevin Barnett
13956c223761SKevin Barnett struct semaphore sync_request_sem;
13967561a7e4SKevin Barnett atomic_t num_busy_threads;
13977561a7e4SKevin Barnett atomic_t num_blocked_threads;
13987561a7e4SKevin Barnett wait_queue_head_t block_requests_wait;
1399376fb880SKevin Barnett
14002790cd4dSKevin Barnett struct mutex ofa_mutex;
14014fd22c13SMahesh Rajashekhara struct pqi_ofa_memory *pqi_ofa_mem_virt_addr;
14024fd22c13SMahesh Rajashekhara dma_addr_t pqi_ofa_mem_dma_handle;
14034fd22c13SMahesh Rajashekhara void **pqi_ofa_chunk_virt_addr;
14042790cd4dSKevin Barnett struct work_struct ofa_memory_alloc_work;
14052790cd4dSKevin Barnett struct work_struct ofa_quiesce_work;
14062790cd4dSKevin Barnett u32 ofa_bytes_requested;
14072790cd4dSKevin Barnett u16 ofa_cancel_reason;
1408331f7e99SSagar Biradar enum pqi_ctrl_removal_state ctrl_removal_state;
14096c223761SKevin Barnett };
14106c223761SKevin Barnett
1411ff6abb73SKevin Barnett enum pqi_ctrl_mode {
1412162d7753SKevin Barnett SIS_MODE = 0,
1413ff6abb73SKevin Barnett PQI_MODE
1414ff6abb73SKevin Barnett };
1415ff6abb73SKevin Barnett
14166c223761SKevin Barnett /*
14176c223761SKevin Barnett * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands
14186c223761SKevin Barnett */
14196c223761SKevin Barnett #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27
14206c223761SKevin Barnett
14216c223761SKevin Barnett /* CISS commands */
14226c223761SKevin Barnett #define CISS_READ 0xc0
14236c223761SKevin Barnett #define CISS_REPORT_LOG 0xc2 /* Report Logical LUNs */
14246c223761SKevin Barnett #define CISS_REPORT_PHYS 0xc3 /* Report Physical LUNs */
14256c223761SKevin Barnett #define CISS_GET_RAID_MAP 0xc8
14266c223761SKevin Barnett
14276c223761SKevin Barnett /* BMIC commands */
14286c223761SKevin Barnett #define BMIC_IDENTIFY_CONTROLLER 0x11
14296c223761SKevin Barnett #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
14306c223761SKevin Barnett #define BMIC_READ 0x26
14316c223761SKevin Barnett #define BMIC_WRITE 0x27
1432f6cc2a77SKevin Barnett #define BMIC_SENSE_FEATURE 0x61
14336c223761SKevin Barnett #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
14346c223761SKevin Barnett #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
14353d46a59aSDon Brace #define BMIC_CSMI_PASSTHRU 0x68
14366c223761SKevin Barnett #define BMIC_WRITE_HOST_WELLNESS 0xa5
143758322fe0SKevin Barnett #define BMIC_FLUSH_CACHE 0xc2
1438171c2865SDave Carroll #define BMIC_SET_DIAG_OPTIONS 0xf4
1439171c2865SDave Carroll #define BMIC_SENSE_DIAG_OPTIONS 0xf5
14406c223761SKevin Barnett
1441694c5d5bSKevin Barnett #define CSMI_CC_SAS_SMP_PASSTHRU 0x17
14423d46a59aSDon Brace
144358322fe0SKevin Barnett #define SA_FLUSH_CACHE 0x1
14446c223761SKevin Barnett
14456c223761SKevin Barnett #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xc0)
1446bd10cf0bSKevin Barnett #define CISS_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3f)
14476c223761SKevin Barnett #define CISS_GET_LEVEL_2_TARGET(lunid) ((lunid)[6])
14486c223761SKevin Barnett #define CISS_GET_DRIVE_NUMBER(lunid) \
1449bd10cf0bSKevin Barnett (((CISS_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \
14506c223761SKevin Barnett CISS_GET_LEVEL_2_TARGET((lunid)))
14516c223761SKevin Barnett
1452f6cc2a77SKevin Barnett #define LV_GET_DRIVE_TYPE_MIX(lunid) ((lunid)[6])
1453f6cc2a77SKevin Barnett
1454f6cc2a77SKevin Barnett #define LV_DRIVE_TYPE_MIX_UNKNOWN 0
1455f6cc2a77SKevin Barnett #define LV_DRIVE_TYPE_MIX_NO_RESTRICTION 1
1456f6cc2a77SKevin Barnett #define LV_DRIVE_TYPE_MIX_SAS_HDD_ONLY 2
1457f6cc2a77SKevin Barnett #define LV_DRIVE_TYPE_MIX_SATA_HDD_ONLY 3
1458f6cc2a77SKevin Barnett #define LV_DRIVE_TYPE_MIX_SAS_OR_SATA_SSD_ONLY 4
1459f6cc2a77SKevin Barnett #define LV_DRIVE_TYPE_MIX_SAS_SSD_ONLY 5
1460f6cc2a77SKevin Barnett #define LV_DRIVE_TYPE_MIX_SATA_SSD_ONLY 6
1461f6cc2a77SKevin Barnett #define LV_DRIVE_TYPE_MIX_SAS_ONLY 7
1462f6cc2a77SKevin Barnett #define LV_DRIVE_TYPE_MIX_SATA_ONLY 8
1463f6cc2a77SKevin Barnett #define LV_DRIVE_TYPE_MIX_NVME_ONLY 9
1464f6cc2a77SKevin Barnett
14656c223761SKevin Barnett #define NO_TIMEOUT ((unsigned long) -1)
14666c223761SKevin Barnett
14676c223761SKevin Barnett #pragma pack(1)
14686c223761SKevin Barnett
14696c223761SKevin Barnett struct bmic_identify_controller {
14706c223761SKevin Barnett u8 configured_logical_drive_count;
14716c223761SKevin Barnett __le32 configuration_signature;
1472598bef8dSKevin Barnett u8 firmware_version_short[4];
14736c223761SKevin Barnett u8 reserved[145];
14746c223761SKevin Barnett __le16 extended_logical_unit_count;
14756c223761SKevin Barnett u8 reserved1[34];
14766c223761SKevin Barnett __le16 firmware_build_number;
14776d90615fSMurthy Bhat u8 reserved2[8];
14786d90615fSMurthy Bhat u8 vendor_id[8];
14796d90615fSMurthy Bhat u8 product_id[16];
1480598bef8dSKevin Barnett u8 reserved3[62];
1481598bef8dSKevin Barnett __le32 extra_controller_flags;
1482598bef8dSKevin Barnett u8 reserved4[2];
14836c223761SKevin Barnett u8 controller_mode;
1484598bef8dSKevin Barnett u8 spare_part_number[32];
1485598bef8dSKevin Barnett u8 firmware_version_long[32];
14866d90615fSMurthy Bhat };
14876d90615fSMurthy Bhat
1488598bef8dSKevin Barnett /* constants for extra_controller_flags field of bmic_identify_controller */
1489598bef8dSKevin Barnett #define BMIC_IDENTIFY_EXTRA_FLAGS_LONG_FW_VERSION_SUPPORTED 0x20000000
1490598bef8dSKevin Barnett
14916d90615fSMurthy Bhat struct bmic_sense_subsystem_info {
14926d90615fSMurthy Bhat u8 reserved[44];
14936d90615fSMurthy Bhat u8 ctrl_serial_number[16];
14946c223761SKevin Barnett };
14956c223761SKevin Barnett
1496694c5d5bSKevin Barnett /* constants for device_type field */
1497694c5d5bSKevin Barnett #define SA_DEVICE_TYPE_SATA 0x1
1498694c5d5bSKevin Barnett #define SA_DEVICE_TYPE_SAS 0x2
1499694c5d5bSKevin Barnett #define SA_DEVICE_TYPE_EXPANDER_SMP 0x5
1500ce143793SKevin Barnett #define SA_DEVICE_TYPE_SES 0x6
1501694c5d5bSKevin Barnett #define SA_DEVICE_TYPE_CONTROLLER 0x7
1502694c5d5bSKevin Barnett #define SA_DEVICE_TYPE_NVME 0x9
15033d46a59aSDon Brace
15046c223761SKevin Barnett struct bmic_identify_physical_device {
15056c223761SKevin Barnett u8 scsi_bus; /* SCSI Bus number on controller */
15066c223761SKevin Barnett u8 scsi_id; /* SCSI ID on this bus */
15076c223761SKevin Barnett __le16 block_size; /* sector size in bytes */
15086c223761SKevin Barnett __le32 total_blocks; /* number for sectors on drive */
15096c223761SKevin Barnett __le32 reserved_blocks; /* controller reserved (RIS) */
15106c223761SKevin Barnett u8 model[40]; /* Physical Drive Model */
15116c223761SKevin Barnett u8 serial_number[40]; /* Drive Serial Number */
15126c223761SKevin Barnett u8 firmware_revision[8]; /* drive firmware revision */
15136c223761SKevin Barnett u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
15146c223761SKevin Barnett u8 compaq_drive_stamp; /* 0 means drive not stamped */
15156c223761SKevin Barnett u8 last_failure_reason;
15166c223761SKevin Barnett u8 flags;
15176c223761SKevin Barnett u8 more_flags;
15186c223761SKevin Barnett u8 scsi_lun; /* SCSI LUN for phys drive */
15196c223761SKevin Barnett u8 yet_more_flags;
15206c223761SKevin Barnett u8 even_more_flags;
15216c223761SKevin Barnett __le32 spi_speed_rules;
15226c223761SKevin Barnett u8 phys_connector[2]; /* connector number on controller */
15236c223761SKevin Barnett u8 phys_box_on_bus; /* phys enclosure this drive resides */
15246c223761SKevin Barnett u8 phys_bay_in_box; /* phys drv bay this drive resides */
15256c223761SKevin Barnett __le32 rpm; /* drive rotational speed in RPM */
15266c223761SKevin Barnett u8 device_type; /* type of drive */
15276c223761SKevin Barnett u8 sata_version; /* only valid when device_type = */
1528694c5d5bSKevin Barnett /* SA_DEVICE_TYPE_SATA */
15296c223761SKevin Barnett __le64 big_total_block_count;
15306c223761SKevin Barnett __le64 ris_starting_lba;
15316c223761SKevin Barnett __le32 ris_size;
15326c223761SKevin Barnett u8 wwid[20];
15336c223761SKevin Barnett u8 controller_phy_map[32];
15346c223761SKevin Barnett __le16 phy_count;
15356c223761SKevin Barnett u8 phy_connected_dev_type[256];
15366c223761SKevin Barnett u8 phy_to_drive_bay_num[256];
15376c223761SKevin Barnett __le16 phy_to_attached_dev_index[256];
15386c223761SKevin Barnett u8 box_index;
15396c223761SKevin Barnett u8 reserved;
15406c223761SKevin Barnett __le16 extra_physical_drive_flags;
15416c223761SKevin Barnett u8 negotiated_link_rate[256];
15426c223761SKevin Barnett u8 phy_to_phy_map[256];
15436c223761SKevin Barnett u8 redundant_path_present_map;
15446c223761SKevin Barnett u8 redundant_path_failure_map;
15456c223761SKevin Barnett u8 active_path_number;
15466c223761SKevin Barnett __le16 alternate_paths_phys_connector[8];
15476c223761SKevin Barnett u8 alternate_paths_phys_box_on_port[8];
15486c223761SKevin Barnett u8 multi_lun_device_lun_count;
15496c223761SKevin Barnett u8 minimum_good_fw_revision[8];
15506c223761SKevin Barnett u8 unique_inquiry_bytes[20];
15511be42f46SKevin Barnett u8 current_temperature_degrees;
15521be42f46SKevin Barnett u8 temperature_threshold_degrees;
15531be42f46SKevin Barnett u8 max_temperature_degrees;
15546c223761SKevin Barnett u8 logical_blocks_per_phys_block_exp;
15556c223761SKevin Barnett __le16 current_queue_depth_limit;
15566c223761SKevin Barnett u8 switch_name[10];
15576c223761SKevin Barnett __le16 switch_port;
15586c223761SKevin Barnett u8 alternate_paths_switch_name[40];
15596c223761SKevin Barnett u8 alternate_paths_switch_port[8];
15606c223761SKevin Barnett __le16 power_on_hours;
15616c223761SKevin Barnett __le16 percent_endurance_used;
15626c223761SKevin Barnett u8 drive_authentication;
15636c223761SKevin Barnett u8 smart_carrier_authentication;
15646c223761SKevin Barnett u8 smart_carrier_app_fw_version;
15656c223761SKevin Barnett u8 smart_carrier_bootloader_fw_version;
15661be42f46SKevin Barnett u8 sanitize_flags;
15671be42f46SKevin Barnett u8 encryption_key_flags;
15686c223761SKevin Barnett u8 encryption_key_name[64];
15696c223761SKevin Barnett __le32 misc_drive_flags;
15706c223761SKevin Barnett __le16 dek_index;
15711be42f46SKevin Barnett __le16 hba_drive_encryption_flags;
15721be42f46SKevin Barnett __le16 max_overwrite_time;
15731be42f46SKevin Barnett __le16 max_block_erase_time;
15741be42f46SKevin Barnett __le16 max_crypto_erase_time;
15751be42f46SKevin Barnett u8 connector_info[5];
15761be42f46SKevin Barnett u8 connector_name[8][8];
15771be42f46SKevin Barnett u8 page_83_identifier[16];
15781be42f46SKevin Barnett u8 maximum_link_rate[256];
15791be42f46SKevin Barnett u8 negotiated_physical_link_rate[256];
15801be42f46SKevin Barnett u8 box_connector_name[8];
15811be42f46SKevin Barnett u8 padding_to_multiple_of_512[9];
15826c223761SKevin Barnett };
15836c223761SKevin Barnett
1584f6cc2a77SKevin Barnett #define BMIC_SENSE_FEATURE_IO_PAGE 0x8
1585f6cc2a77SKevin Barnett #define BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE 0x2
1586f6cc2a77SKevin Barnett
1587f6cc2a77SKevin Barnett struct bmic_sense_feature_buffer_header {
1588f6cc2a77SKevin Barnett u8 page_code;
1589f6cc2a77SKevin Barnett u8 subpage_code;
1590f6cc2a77SKevin Barnett __le16 buffer_length;
1591f6cc2a77SKevin Barnett };
1592f6cc2a77SKevin Barnett
1593f6cc2a77SKevin Barnett struct bmic_sense_feature_page_header {
1594f6cc2a77SKevin Barnett u8 page_code;
1595f6cc2a77SKevin Barnett u8 subpage_code;
1596f6cc2a77SKevin Barnett __le16 page_length;
1597f6cc2a77SKevin Barnett };
1598f6cc2a77SKevin Barnett
1599f6cc2a77SKevin Barnett struct bmic_sense_feature_io_page_aio_subpage {
1600f6cc2a77SKevin Barnett struct bmic_sense_feature_page_header header;
1601f6cc2a77SKevin Barnett u8 firmware_read_support;
1602f6cc2a77SKevin Barnett u8 driver_read_support;
1603f6cc2a77SKevin Barnett u8 firmware_write_support;
1604f6cc2a77SKevin Barnett u8 driver_write_support;
1605f6cc2a77SKevin Barnett __le16 max_transfer_encrypted_sas_sata;
1606f6cc2a77SKevin Barnett __le16 max_transfer_encrypted_nvme;
1607f6cc2a77SKevin Barnett __le16 max_write_raid_5_6;
1608f6cc2a77SKevin Barnett __le16 max_write_raid_1_10_2drive;
1609f6cc2a77SKevin Barnett __le16 max_write_raid_1_10_3drive;
1610f6cc2a77SKevin Barnett };
1611f6cc2a77SKevin Barnett
16123d46a59aSDon Brace struct bmic_smp_request {
16133d46a59aSDon Brace u8 frame_type;
16143d46a59aSDon Brace u8 function;
16153d46a59aSDon Brace u8 allocated_response_length;
16163d46a59aSDon Brace u8 request_length;
16173d46a59aSDon Brace u8 additional_request_bytes[1016];
16183d46a59aSDon Brace };
16193d46a59aSDon Brace
16203d46a59aSDon Brace struct bmic_smp_response {
16213d46a59aSDon Brace u8 frame_type;
16223d46a59aSDon Brace u8 function;
16233d46a59aSDon Brace u8 function_result;
16243d46a59aSDon Brace u8 response_length;
16253d46a59aSDon Brace u8 additional_response_bytes[1016];
16263d46a59aSDon Brace };
16273d46a59aSDon Brace
16283d46a59aSDon Brace struct bmic_csmi_ioctl_header {
16293d46a59aSDon Brace __le32 header_length;
16303d46a59aSDon Brace u8 signature[8];
16313d46a59aSDon Brace __le32 timeout;
16323d46a59aSDon Brace __le32 control_code;
16333d46a59aSDon Brace __le32 return_code;
16343d46a59aSDon Brace __le32 length;
16353d46a59aSDon Brace };
16363d46a59aSDon Brace
16373d46a59aSDon Brace struct bmic_csmi_smp_passthru {
16383d46a59aSDon Brace u8 phy_identifier;
16393d46a59aSDon Brace u8 port_identifier;
16403d46a59aSDon Brace u8 connection_rate;
16413d46a59aSDon Brace u8 reserved;
16423d46a59aSDon Brace __be64 destination_sas_address;
16433d46a59aSDon Brace __le32 request_length;
16443d46a59aSDon Brace struct bmic_smp_request request;
16453d46a59aSDon Brace u8 connection_status;
16463d46a59aSDon Brace u8 reserved1[3];
16473d46a59aSDon Brace __le32 response_length;
16483d46a59aSDon Brace struct bmic_smp_response response;
16493d46a59aSDon Brace };
16503d46a59aSDon Brace
16513d46a59aSDon Brace struct bmic_csmi_smp_passthru_buffer {
16523d46a59aSDon Brace struct bmic_csmi_ioctl_header ioctl_header;
16533d46a59aSDon Brace struct bmic_csmi_smp_passthru parameters;
16543d46a59aSDon Brace };
16553d46a59aSDon Brace
165658322fe0SKevin Barnett struct bmic_flush_cache {
165758322fe0SKevin Barnett u8 disable_flag;
165858322fe0SKevin Barnett u8 system_power_action;
165958322fe0SKevin Barnett u8 ndu_flush;
166058322fe0SKevin Barnett u8 shutdown_event;
166158322fe0SKevin Barnett u8 reserved[28];
166258322fe0SKevin Barnett };
166358322fe0SKevin Barnett
166458322fe0SKevin Barnett /* for shutdown_event member of struct bmic_flush_cache */
166558322fe0SKevin Barnett enum bmic_flush_cache_shutdown_event {
166658322fe0SKevin Barnett NONE_CACHE_FLUSH_ONLY = 0,
166758322fe0SKevin Barnett SHUTDOWN = 1,
166858322fe0SKevin Barnett HIBERNATE = 2,
166958322fe0SKevin Barnett SUSPEND = 3,
167058322fe0SKevin Barnett RESTART = 4
167158322fe0SKevin Barnett };
167258322fe0SKevin Barnett
1673171c2865SDave Carroll struct bmic_diag_options {
1674171c2865SDave Carroll __le32 options;
1675171c2865SDave Carroll };
1676171c2865SDave Carroll
16776c223761SKevin Barnett #pragma pack()
16786c223761SKevin Barnett
shost_to_hba(struct Scsi_Host * shost)1679694c5d5bSKevin Barnett static inline struct pqi_ctrl_info *shost_to_hba(struct Scsi_Host *shost)
16803d46a59aSDon Brace {
1681694c5d5bSKevin Barnett void *hostdata = shost_priv(shost);
16823d46a59aSDon Brace
1683694c5d5bSKevin Barnett return *((struct pqi_ctrl_info **)hostdata);
16840530736eSKevin Barnett }
16850530736eSKevin Barnett
16863d46a59aSDon Brace void pqi_sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost,
16873d46a59aSDon Brace struct sas_rphy *rphy);
16883d46a59aSDon Brace
16896c223761SKevin Barnett int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info);
16906c223761SKevin Barnett void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info);
16916c223761SKevin Barnett int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node,
16926c223761SKevin Barnett struct pqi_scsi_dev *device);
16936c223761SKevin Barnett void pqi_remove_sas_device(struct pqi_scsi_dev *device);
16946c223761SKevin Barnett struct pqi_scsi_dev *pqi_find_device_by_sas_rphy(
16956c223761SKevin Barnett struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy);
16967561a7e4SKevin Barnett void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd);
16973d46a59aSDon Brace int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info,
16983d46a59aSDon Brace struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length,
16993d46a59aSDon Brace struct pqi_raid_error_info *error_info);
17006c223761SKevin Barnett
17016c223761SKevin Barnett extern struct sas_function_template pqi_sas_transport_functions;
17026c223761SKevin Barnett
17036c223761SKevin Barnett #endif /* _SMARTPQI_H */
1704