1 /* qlogicpti.c: Performance Technologies QlogicISP sbus card driver. 2 * 3 * Copyright (C) 1996, 2006 David S. Miller (davem@davemloft.net) 4 * 5 * A lot of this driver was directly stolen from Erik H. Moe's PCI 6 * Qlogic ISP driver. Mucho kudos to him for this code. 7 * 8 * An even bigger kudos to John Grana at Performance Technologies 9 * for providing me with the hardware to write this driver, you rule 10 * John you really do. 11 * 12 * May, 2, 1997: Added support for QLGC,isp --jj 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/delay.h> 17 #include <linux/types.h> 18 #include <linux/string.h> 19 #include <linux/slab.h> 20 #include <linux/blkdev.h> 21 #include <linux/proc_fs.h> 22 #include <linux/stat.h> 23 #include <linux/init.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/module.h> 27 #include <linux/jiffies.h> 28 29 #include <asm/byteorder.h> 30 31 #include "qlogicpti.h" 32 33 #include <asm/sbus.h> 34 #include <asm/dma.h> 35 #include <asm/system.h> 36 #include <asm/ptrace.h> 37 #include <asm/pgtable.h> 38 #include <asm/oplib.h> 39 #include <asm/io.h> 40 #include <asm/irq.h> 41 42 #include <scsi/scsi.h> 43 #include <scsi/scsi_cmnd.h> 44 #include <scsi/scsi_device.h> 45 #include <scsi/scsi_eh.h> 46 #include <scsi/scsi_tcq.h> 47 #include <scsi/scsi_host.h> 48 49 #define MAX_TARGETS 16 50 #define MAX_LUNS 8 /* 32 for 1.31 F/W */ 51 52 #define DEFAULT_LOOP_COUNT 10000 53 54 #include "qlogicpti_asm.c" 55 56 static struct qlogicpti *qptichain = NULL; 57 static DEFINE_SPINLOCK(qptichain_lock); 58 59 #define PACKB(a, b) (((a)<<4)|(b)) 60 61 static const u_char mbox_param[] = { 62 PACKB(1, 1), /* MBOX_NO_OP */ 63 PACKB(5, 5), /* MBOX_LOAD_RAM */ 64 PACKB(2, 0), /* MBOX_EXEC_FIRMWARE */ 65 PACKB(5, 5), /* MBOX_DUMP_RAM */ 66 PACKB(3, 3), /* MBOX_WRITE_RAM_WORD */ 67 PACKB(2, 3), /* MBOX_READ_RAM_WORD */ 68 PACKB(6, 6), /* MBOX_MAILBOX_REG_TEST */ 69 PACKB(2, 3), /* MBOX_VERIFY_CHECKSUM */ 70 PACKB(1, 3), /* MBOX_ABOUT_FIRMWARE */ 71 PACKB(0, 0), /* 0x0009 */ 72 PACKB(0, 0), /* 0x000a */ 73 PACKB(0, 0), /* 0x000b */ 74 PACKB(0, 0), /* 0x000c */ 75 PACKB(0, 0), /* 0x000d */ 76 PACKB(1, 2), /* MBOX_CHECK_FIRMWARE */ 77 PACKB(0, 0), /* 0x000f */ 78 PACKB(5, 5), /* MBOX_INIT_REQ_QUEUE */ 79 PACKB(6, 6), /* MBOX_INIT_RES_QUEUE */ 80 PACKB(4, 4), /* MBOX_EXECUTE_IOCB */ 81 PACKB(2, 2), /* MBOX_WAKE_UP */ 82 PACKB(1, 6), /* MBOX_STOP_FIRMWARE */ 83 PACKB(4, 4), /* MBOX_ABORT */ 84 PACKB(2, 2), /* MBOX_ABORT_DEVICE */ 85 PACKB(3, 3), /* MBOX_ABORT_TARGET */ 86 PACKB(2, 2), /* MBOX_BUS_RESET */ 87 PACKB(2, 3), /* MBOX_STOP_QUEUE */ 88 PACKB(2, 3), /* MBOX_START_QUEUE */ 89 PACKB(2, 3), /* MBOX_SINGLE_STEP_QUEUE */ 90 PACKB(2, 3), /* MBOX_ABORT_QUEUE */ 91 PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_STATUS */ 92 PACKB(0, 0), /* 0x001e */ 93 PACKB(1, 3), /* MBOX_GET_FIRMWARE_STATUS */ 94 PACKB(1, 2), /* MBOX_GET_INIT_SCSI_ID */ 95 PACKB(1, 2), /* MBOX_GET_SELECT_TIMEOUT */ 96 PACKB(1, 3), /* MBOX_GET_RETRY_COUNT */ 97 PACKB(1, 2), /* MBOX_GET_TAG_AGE_LIMIT */ 98 PACKB(1, 2), /* MBOX_GET_CLOCK_RATE */ 99 PACKB(1, 2), /* MBOX_GET_ACT_NEG_STATE */ 100 PACKB(1, 2), /* MBOX_GET_ASYNC_DATA_SETUP_TIME */ 101 PACKB(1, 3), /* MBOX_GET_SBUS_PARAMS */ 102 PACKB(2, 4), /* MBOX_GET_TARGET_PARAMS */ 103 PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_PARAMS */ 104 PACKB(0, 0), /* 0x002a */ 105 PACKB(0, 0), /* 0x002b */ 106 PACKB(0, 0), /* 0x002c */ 107 PACKB(0, 0), /* 0x002d */ 108 PACKB(0, 0), /* 0x002e */ 109 PACKB(0, 0), /* 0x002f */ 110 PACKB(2, 2), /* MBOX_SET_INIT_SCSI_ID */ 111 PACKB(2, 2), /* MBOX_SET_SELECT_TIMEOUT */ 112 PACKB(3, 3), /* MBOX_SET_RETRY_COUNT */ 113 PACKB(2, 2), /* MBOX_SET_TAG_AGE_LIMIT */ 114 PACKB(2, 2), /* MBOX_SET_CLOCK_RATE */ 115 PACKB(2, 2), /* MBOX_SET_ACTIVE_NEG_STATE */ 116 PACKB(2, 2), /* MBOX_SET_ASYNC_DATA_SETUP_TIME */ 117 PACKB(3, 3), /* MBOX_SET_SBUS_CONTROL_PARAMS */ 118 PACKB(4, 4), /* MBOX_SET_TARGET_PARAMS */ 119 PACKB(4, 4), /* MBOX_SET_DEV_QUEUE_PARAMS */ 120 PACKB(0, 0), /* 0x003a */ 121 PACKB(0, 0), /* 0x003b */ 122 PACKB(0, 0), /* 0x003c */ 123 PACKB(0, 0), /* 0x003d */ 124 PACKB(0, 0), /* 0x003e */ 125 PACKB(0, 0), /* 0x003f */ 126 PACKB(0, 0), /* 0x0040 */ 127 PACKB(0, 0), /* 0x0041 */ 128 PACKB(0, 0) /* 0x0042 */ 129 }; 130 131 #define MAX_MBOX_COMMAND ARRAY_SIZE(mbox_param) 132 133 /* queue length's _must_ be power of two: */ 134 #define QUEUE_DEPTH(in, out, ql) ((in - out) & (ql)) 135 #define REQ_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, \ 136 QLOGICPTI_REQ_QUEUE_LEN) 137 #define RES_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, RES_QUEUE_LEN) 138 139 static inline void qlogicpti_enable_irqs(struct qlogicpti *qpti) 140 { 141 sbus_writew(SBUS_CTRL_ERIRQ | SBUS_CTRL_GENAB, 142 qpti->qregs + SBUS_CTRL); 143 } 144 145 static inline void qlogicpti_disable_irqs(struct qlogicpti *qpti) 146 { 147 sbus_writew(0, qpti->qregs + SBUS_CTRL); 148 } 149 150 static inline void set_sbus_cfg1(struct qlogicpti *qpti) 151 { 152 u16 val; 153 u8 bursts = qpti->bursts; 154 155 #if 0 /* It appears that at least PTI cards do not support 156 * 64-byte bursts and that setting the B64 bit actually 157 * is a nop and the chip ends up using the smallest burst 158 * size. -DaveM 159 */ 160 if (sbus_can_burst64(qpti->sdev) && (bursts & DMA_BURST64)) { 161 val = (SBUS_CFG1_BENAB | SBUS_CFG1_B64); 162 } else 163 #endif 164 if (bursts & DMA_BURST32) { 165 val = (SBUS_CFG1_BENAB | SBUS_CFG1_B32); 166 } else if (bursts & DMA_BURST16) { 167 val = (SBUS_CFG1_BENAB | SBUS_CFG1_B16); 168 } else if (bursts & DMA_BURST8) { 169 val = (SBUS_CFG1_BENAB | SBUS_CFG1_B8); 170 } else { 171 val = 0; /* No sbus bursts for you... */ 172 } 173 sbus_writew(val, qpti->qregs + SBUS_CFG1); 174 } 175 176 static int qlogicpti_mbox_command(struct qlogicpti *qpti, u_short param[], int force) 177 { 178 int loop_count; 179 u16 tmp; 180 181 if (mbox_param[param[0]] == 0) 182 return 1; 183 184 /* Set SBUS semaphore. */ 185 tmp = sbus_readw(qpti->qregs + SBUS_SEMAPHORE); 186 tmp |= SBUS_SEMAPHORE_LCK; 187 sbus_writew(tmp, qpti->qregs + SBUS_SEMAPHORE); 188 189 /* Wait for host IRQ bit to clear. */ 190 loop_count = DEFAULT_LOOP_COUNT; 191 while (--loop_count && (sbus_readw(qpti->qregs + HCCTRL) & HCCTRL_HIRQ)) { 192 barrier(); 193 cpu_relax(); 194 } 195 if (!loop_count) 196 printk(KERN_EMERG "qlogicpti%d: mbox_command loop timeout #1\n", 197 qpti->qpti_id); 198 199 /* Write mailbox command registers. */ 200 switch (mbox_param[param[0]] >> 4) { 201 case 6: sbus_writew(param[5], qpti->qregs + MBOX5); 202 case 5: sbus_writew(param[4], qpti->qregs + MBOX4); 203 case 4: sbus_writew(param[3], qpti->qregs + MBOX3); 204 case 3: sbus_writew(param[2], qpti->qregs + MBOX2); 205 case 2: sbus_writew(param[1], qpti->qregs + MBOX1); 206 case 1: sbus_writew(param[0], qpti->qregs + MBOX0); 207 } 208 209 /* Clear RISC interrupt. */ 210 tmp = sbus_readw(qpti->qregs + HCCTRL); 211 tmp |= HCCTRL_CRIRQ; 212 sbus_writew(tmp, qpti->qregs + HCCTRL); 213 214 /* Clear SBUS semaphore. */ 215 sbus_writew(0, qpti->qregs + SBUS_SEMAPHORE); 216 217 /* Set HOST interrupt. */ 218 tmp = sbus_readw(qpti->qregs + HCCTRL); 219 tmp |= HCCTRL_SHIRQ; 220 sbus_writew(tmp, qpti->qregs + HCCTRL); 221 222 /* Wait for HOST interrupt clears. */ 223 loop_count = DEFAULT_LOOP_COUNT; 224 while (--loop_count && 225 (sbus_readw(qpti->qregs + HCCTRL) & HCCTRL_CRIRQ)) 226 udelay(20); 227 if (!loop_count) 228 printk(KERN_EMERG "qlogicpti%d: mbox_command[%04x] loop timeout #2\n", 229 qpti->qpti_id, param[0]); 230 231 /* Wait for SBUS semaphore to get set. */ 232 loop_count = DEFAULT_LOOP_COUNT; 233 while (--loop_count && 234 !(sbus_readw(qpti->qregs + SBUS_SEMAPHORE) & SBUS_SEMAPHORE_LCK)) { 235 udelay(20); 236 237 /* Workaround for some buggy chips. */ 238 if (sbus_readw(qpti->qregs + MBOX0) & 0x4000) 239 break; 240 } 241 if (!loop_count) 242 printk(KERN_EMERG "qlogicpti%d: mbox_command[%04x] loop timeout #3\n", 243 qpti->qpti_id, param[0]); 244 245 /* Wait for MBOX busy condition to go away. */ 246 loop_count = DEFAULT_LOOP_COUNT; 247 while (--loop_count && (sbus_readw(qpti->qregs + MBOX0) == 0x04)) 248 udelay(20); 249 if (!loop_count) 250 printk(KERN_EMERG "qlogicpti%d: mbox_command[%04x] loop timeout #4\n", 251 qpti->qpti_id, param[0]); 252 253 /* Read back output parameters. */ 254 switch (mbox_param[param[0]] & 0xf) { 255 case 6: param[5] = sbus_readw(qpti->qregs + MBOX5); 256 case 5: param[4] = sbus_readw(qpti->qregs + MBOX4); 257 case 4: param[3] = sbus_readw(qpti->qregs + MBOX3); 258 case 3: param[2] = sbus_readw(qpti->qregs + MBOX2); 259 case 2: param[1] = sbus_readw(qpti->qregs + MBOX1); 260 case 1: param[0] = sbus_readw(qpti->qregs + MBOX0); 261 } 262 263 /* Clear RISC interrupt. */ 264 tmp = sbus_readw(qpti->qregs + HCCTRL); 265 tmp |= HCCTRL_CRIRQ; 266 sbus_writew(tmp, qpti->qregs + HCCTRL); 267 268 /* Release SBUS semaphore. */ 269 tmp = sbus_readw(qpti->qregs + SBUS_SEMAPHORE); 270 tmp &= ~(SBUS_SEMAPHORE_LCK); 271 sbus_writew(tmp, qpti->qregs + SBUS_SEMAPHORE); 272 273 /* We're done. */ 274 return 0; 275 } 276 277 static inline void qlogicpti_set_hostdev_defaults(struct qlogicpti *qpti) 278 { 279 int i; 280 281 qpti->host_param.initiator_scsi_id = qpti->scsi_id; 282 qpti->host_param.bus_reset_delay = 3; 283 qpti->host_param.retry_count = 0; 284 qpti->host_param.retry_delay = 5; 285 qpti->host_param.async_data_setup_time = 3; 286 qpti->host_param.req_ack_active_negation = 1; 287 qpti->host_param.data_line_active_negation = 1; 288 qpti->host_param.data_dma_burst_enable = 1; 289 qpti->host_param.command_dma_burst_enable = 1; 290 qpti->host_param.tag_aging = 8; 291 qpti->host_param.selection_timeout = 250; 292 qpti->host_param.max_queue_depth = 256; 293 294 for(i = 0; i < MAX_TARGETS; i++) { 295 /* 296 * disconnect, parity, arq, reneg on reset, and, oddly enough 297 * tags...the midlayer's notion of tagged support has to match 298 * our device settings, and since we base whether we enable a 299 * tag on a per-cmnd basis upon what the midlayer sez, we 300 * actually enable the capability here. 301 */ 302 qpti->dev_param[i].device_flags = 0xcd; 303 qpti->dev_param[i].execution_throttle = 16; 304 if (qpti->ultra) { 305 qpti->dev_param[i].synchronous_period = 12; 306 qpti->dev_param[i].synchronous_offset = 8; 307 } else { 308 qpti->dev_param[i].synchronous_period = 25; 309 qpti->dev_param[i].synchronous_offset = 12; 310 } 311 qpti->dev_param[i].device_enable = 1; 312 } 313 } 314 315 static int qlogicpti_reset_hardware(struct Scsi_Host *host) 316 { 317 struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata; 318 u_short param[6]; 319 unsigned short risc_code_addr; 320 int loop_count, i; 321 unsigned long flags; 322 323 risc_code_addr = 0x1000; /* all load addresses are at 0x1000 */ 324 325 spin_lock_irqsave(host->host_lock, flags); 326 327 sbus_writew(HCCTRL_PAUSE, qpti->qregs + HCCTRL); 328 329 /* Only reset the scsi bus if it is not free. */ 330 if (sbus_readw(qpti->qregs + CPU_PCTRL) & CPU_PCTRL_BSY) { 331 sbus_writew(CPU_ORIDE_RMOD, qpti->qregs + CPU_ORIDE); 332 sbus_writew(CPU_CMD_BRESET, qpti->qregs + CPU_CMD); 333 udelay(400); 334 } 335 336 sbus_writew(SBUS_CTRL_RESET, qpti->qregs + SBUS_CTRL); 337 sbus_writew((DMA_CTRL_CCLEAR | DMA_CTRL_CIRQ), qpti->qregs + CMD_DMA_CTRL); 338 sbus_writew((DMA_CTRL_CCLEAR | DMA_CTRL_CIRQ), qpti->qregs + DATA_DMA_CTRL); 339 340 loop_count = DEFAULT_LOOP_COUNT; 341 while (--loop_count && ((sbus_readw(qpti->qregs + MBOX0) & 0xff) == 0x04)) 342 udelay(20); 343 if (!loop_count) 344 printk(KERN_EMERG "qlogicpti%d: reset_hardware loop timeout\n", 345 qpti->qpti_id); 346 347 sbus_writew(HCCTRL_PAUSE, qpti->qregs + HCCTRL); 348 set_sbus_cfg1(qpti); 349 qlogicpti_enable_irqs(qpti); 350 351 if (sbus_readw(qpti->qregs + RISC_PSR) & RISC_PSR_ULTRA) { 352 qpti->ultra = 1; 353 sbus_writew((RISC_MTREG_P0ULTRA | RISC_MTREG_P1ULTRA), 354 qpti->qregs + RISC_MTREG); 355 } else { 356 qpti->ultra = 0; 357 sbus_writew((RISC_MTREG_P0DFLT | RISC_MTREG_P1DFLT), 358 qpti->qregs + RISC_MTREG); 359 } 360 361 /* reset adapter and per-device default values. */ 362 /* do it after finding out whether we're ultra mode capable */ 363 qlogicpti_set_hostdev_defaults(qpti); 364 365 /* Release the RISC processor. */ 366 sbus_writew(HCCTRL_REL, qpti->qregs + HCCTRL); 367 368 /* Get RISC to start executing the firmware code. */ 369 param[0] = MBOX_EXEC_FIRMWARE; 370 param[1] = risc_code_addr; 371 if (qlogicpti_mbox_command(qpti, param, 1)) { 372 printk(KERN_EMERG "qlogicpti%d: Cannot execute ISP firmware.\n", 373 qpti->qpti_id); 374 spin_unlock_irqrestore(host->host_lock, flags); 375 return 1; 376 } 377 378 /* Set initiator scsi ID. */ 379 param[0] = MBOX_SET_INIT_SCSI_ID; 380 param[1] = qpti->host_param.initiator_scsi_id; 381 if (qlogicpti_mbox_command(qpti, param, 1) || 382 (param[0] != MBOX_COMMAND_COMPLETE)) { 383 printk(KERN_EMERG "qlogicpti%d: Cannot set initiator SCSI ID.\n", 384 qpti->qpti_id); 385 spin_unlock_irqrestore(host->host_lock, flags); 386 return 1; 387 } 388 389 /* Initialize state of the queues, both hw and sw. */ 390 qpti->req_in_ptr = qpti->res_out_ptr = 0; 391 392 param[0] = MBOX_INIT_RES_QUEUE; 393 param[1] = RES_QUEUE_LEN + 1; 394 param[2] = (u_short) (qpti->res_dvma >> 16); 395 param[3] = (u_short) (qpti->res_dvma & 0xffff); 396 param[4] = param[5] = 0; 397 if (qlogicpti_mbox_command(qpti, param, 1)) { 398 printk(KERN_EMERG "qlogicpti%d: Cannot init response queue.\n", 399 qpti->qpti_id); 400 spin_unlock_irqrestore(host->host_lock, flags); 401 return 1; 402 } 403 404 param[0] = MBOX_INIT_REQ_QUEUE; 405 param[1] = QLOGICPTI_REQ_QUEUE_LEN + 1; 406 param[2] = (u_short) (qpti->req_dvma >> 16); 407 param[3] = (u_short) (qpti->req_dvma & 0xffff); 408 param[4] = param[5] = 0; 409 if (qlogicpti_mbox_command(qpti, param, 1)) { 410 printk(KERN_EMERG "qlogicpti%d: Cannot init request queue.\n", 411 qpti->qpti_id); 412 spin_unlock_irqrestore(host->host_lock, flags); 413 return 1; 414 } 415 416 param[0] = MBOX_SET_RETRY_COUNT; 417 param[1] = qpti->host_param.retry_count; 418 param[2] = qpti->host_param.retry_delay; 419 qlogicpti_mbox_command(qpti, param, 0); 420 421 param[0] = MBOX_SET_TAG_AGE_LIMIT; 422 param[1] = qpti->host_param.tag_aging; 423 qlogicpti_mbox_command(qpti, param, 0); 424 425 for (i = 0; i < MAX_TARGETS; i++) { 426 param[0] = MBOX_GET_DEV_QUEUE_PARAMS; 427 param[1] = (i << 8); 428 qlogicpti_mbox_command(qpti, param, 0); 429 } 430 431 param[0] = MBOX_GET_FIRMWARE_STATUS; 432 qlogicpti_mbox_command(qpti, param, 0); 433 434 param[0] = MBOX_SET_SELECT_TIMEOUT; 435 param[1] = qpti->host_param.selection_timeout; 436 qlogicpti_mbox_command(qpti, param, 0); 437 438 for (i = 0; i < MAX_TARGETS; i++) { 439 param[0] = MBOX_SET_TARGET_PARAMS; 440 param[1] = (i << 8); 441 param[2] = (qpti->dev_param[i].device_flags << 8); 442 /* 443 * Since we're now loading 1.31 f/w, force narrow/async. 444 */ 445 param[2] |= 0xc0; 446 param[3] = 0; /* no offset, we do not have sync mode yet */ 447 qlogicpti_mbox_command(qpti, param, 0); 448 } 449 450 /* 451 * Always (sigh) do an initial bus reset (kicks f/w). 452 */ 453 param[0] = MBOX_BUS_RESET; 454 param[1] = qpti->host_param.bus_reset_delay; 455 qlogicpti_mbox_command(qpti, param, 0); 456 qpti->send_marker = 1; 457 458 spin_unlock_irqrestore(host->host_lock, flags); 459 return 0; 460 } 461 462 #define PTI_RESET_LIMIT 400 463 464 static int __devinit qlogicpti_load_firmware(struct qlogicpti *qpti) 465 { 466 struct Scsi_Host *host = qpti->qhost; 467 unsigned short csum = 0; 468 unsigned short param[6]; 469 unsigned short *risc_code, risc_code_addr, risc_code_length; 470 unsigned long flags; 471 int i, timeout; 472 473 risc_code = &sbus_risc_code01[0]; 474 risc_code_addr = 0x1000; /* all f/w modules load at 0x1000 */ 475 risc_code_length = sbus_risc_code_length01; 476 477 spin_lock_irqsave(host->host_lock, flags); 478 479 /* Verify the checksum twice, one before loading it, and once 480 * afterwards via the mailbox commands. 481 */ 482 for (i = 0; i < risc_code_length; i++) 483 csum += risc_code[i]; 484 if (csum) { 485 spin_unlock_irqrestore(host->host_lock, flags); 486 printk(KERN_EMERG "qlogicpti%d: Aieee, firmware checksum failed!", 487 qpti->qpti_id); 488 return 1; 489 } 490 sbus_writew(SBUS_CTRL_RESET, qpti->qregs + SBUS_CTRL); 491 sbus_writew((DMA_CTRL_CCLEAR | DMA_CTRL_CIRQ), qpti->qregs + CMD_DMA_CTRL); 492 sbus_writew((DMA_CTRL_CCLEAR | DMA_CTRL_CIRQ), qpti->qregs + DATA_DMA_CTRL); 493 timeout = PTI_RESET_LIMIT; 494 while (--timeout && (sbus_readw(qpti->qregs + SBUS_CTRL) & SBUS_CTRL_RESET)) 495 udelay(20); 496 if (!timeout) { 497 spin_unlock_irqrestore(host->host_lock, flags); 498 printk(KERN_EMERG "qlogicpti%d: Cannot reset the ISP.", qpti->qpti_id); 499 return 1; 500 } 501 502 sbus_writew(HCCTRL_RESET, qpti->qregs + HCCTRL); 503 mdelay(1); 504 505 sbus_writew((SBUS_CTRL_GENAB | SBUS_CTRL_ERIRQ), qpti->qregs + SBUS_CTRL); 506 set_sbus_cfg1(qpti); 507 sbus_writew(0, qpti->qregs + SBUS_SEMAPHORE); 508 509 if (sbus_readw(qpti->qregs + RISC_PSR) & RISC_PSR_ULTRA) { 510 qpti->ultra = 1; 511 sbus_writew((RISC_MTREG_P0ULTRA | RISC_MTREG_P1ULTRA), 512 qpti->qregs + RISC_MTREG); 513 } else { 514 qpti->ultra = 0; 515 sbus_writew((RISC_MTREG_P0DFLT | RISC_MTREG_P1DFLT), 516 qpti->qregs + RISC_MTREG); 517 } 518 519 sbus_writew(HCCTRL_REL, qpti->qregs + HCCTRL); 520 521 /* Pin lines are only stable while RISC is paused. */ 522 sbus_writew(HCCTRL_PAUSE, qpti->qregs + HCCTRL); 523 if (sbus_readw(qpti->qregs + CPU_PDIFF) & CPU_PDIFF_MODE) 524 qpti->differential = 1; 525 else 526 qpti->differential = 0; 527 sbus_writew(HCCTRL_REL, qpti->qregs + HCCTRL); 528 529 /* This shouldn't be necessary- we've reset things so we should be 530 running from the ROM now.. */ 531 532 param[0] = MBOX_STOP_FIRMWARE; 533 param[1] = param[2] = param[3] = param[4] = param[5] = 0; 534 if (qlogicpti_mbox_command(qpti, param, 1)) { 535 printk(KERN_EMERG "qlogicpti%d: Cannot stop firmware for reload.\n", 536 qpti->qpti_id); 537 spin_unlock_irqrestore(host->host_lock, flags); 538 return 1; 539 } 540 541 /* Load it up.. */ 542 for (i = 0; i < risc_code_length; i++) { 543 param[0] = MBOX_WRITE_RAM_WORD; 544 param[1] = risc_code_addr + i; 545 param[2] = risc_code[i]; 546 if (qlogicpti_mbox_command(qpti, param, 1) || 547 param[0] != MBOX_COMMAND_COMPLETE) { 548 printk("qlogicpti%d: Firmware dload failed, I'm bolixed!\n", 549 qpti->qpti_id); 550 spin_unlock_irqrestore(host->host_lock, flags); 551 return 1; 552 } 553 } 554 555 /* Reset the ISP again. */ 556 sbus_writew(HCCTRL_RESET, qpti->qregs + HCCTRL); 557 mdelay(1); 558 559 qlogicpti_enable_irqs(qpti); 560 sbus_writew(0, qpti->qregs + SBUS_SEMAPHORE); 561 sbus_writew(HCCTRL_REL, qpti->qregs + HCCTRL); 562 563 /* Ask ISP to verify the checksum of the new code. */ 564 param[0] = MBOX_VERIFY_CHECKSUM; 565 param[1] = risc_code_addr; 566 if (qlogicpti_mbox_command(qpti, param, 1) || 567 (param[0] != MBOX_COMMAND_COMPLETE)) { 568 printk(KERN_EMERG "qlogicpti%d: New firmware csum failure!\n", 569 qpti->qpti_id); 570 spin_unlock_irqrestore(host->host_lock, flags); 571 return 1; 572 } 573 574 /* Start using newly downloaded firmware. */ 575 param[0] = MBOX_EXEC_FIRMWARE; 576 param[1] = risc_code_addr; 577 qlogicpti_mbox_command(qpti, param, 1); 578 579 param[0] = MBOX_ABOUT_FIRMWARE; 580 if (qlogicpti_mbox_command(qpti, param, 1) || 581 (param[0] != MBOX_COMMAND_COMPLETE)) { 582 printk(KERN_EMERG "qlogicpti%d: AboutFirmware cmd fails.\n", 583 qpti->qpti_id); 584 spin_unlock_irqrestore(host->host_lock, flags); 585 return 1; 586 } 587 588 /* Snag the major and minor revisions from the result. */ 589 qpti->fware_majrev = param[1]; 590 qpti->fware_minrev = param[2]; 591 qpti->fware_micrev = param[3]; 592 593 /* Set the clock rate */ 594 param[0] = MBOX_SET_CLOCK_RATE; 595 param[1] = qpti->clock; 596 if (qlogicpti_mbox_command(qpti, param, 1) || 597 (param[0] != MBOX_COMMAND_COMPLETE)) { 598 printk(KERN_EMERG "qlogicpti%d: could not set clock rate.\n", 599 qpti->qpti_id); 600 spin_unlock_irqrestore(host->host_lock, flags); 601 return 1; 602 } 603 604 if (qpti->is_pti != 0) { 605 /* Load scsi initiator ID and interrupt level into sbus static ram. */ 606 param[0] = MBOX_WRITE_RAM_WORD; 607 param[1] = 0xff80; 608 param[2] = (unsigned short) qpti->scsi_id; 609 qlogicpti_mbox_command(qpti, param, 1); 610 611 param[0] = MBOX_WRITE_RAM_WORD; 612 param[1] = 0xff00; 613 param[2] = (unsigned short) 3; 614 qlogicpti_mbox_command(qpti, param, 1); 615 } 616 617 spin_unlock_irqrestore(host->host_lock, flags); 618 return 0; 619 } 620 621 static int qlogicpti_verify_tmon(struct qlogicpti *qpti) 622 { 623 int curstat = sbus_readb(qpti->sreg); 624 625 curstat &= 0xf0; 626 if (!(curstat & SREG_FUSE) && (qpti->swsreg & SREG_FUSE)) 627 printk("qlogicpti%d: Fuse returned to normal state.\n", qpti->qpti_id); 628 if (!(curstat & SREG_TPOWER) && (qpti->swsreg & SREG_TPOWER)) 629 printk("qlogicpti%d: termpwr back to normal state.\n", qpti->qpti_id); 630 if (curstat != qpti->swsreg) { 631 int error = 0; 632 if (curstat & SREG_FUSE) { 633 error++; 634 printk("qlogicpti%d: Fuse is open!\n", qpti->qpti_id); 635 } 636 if (curstat & SREG_TPOWER) { 637 error++; 638 printk("qlogicpti%d: termpwr failure\n", qpti->qpti_id); 639 } 640 if (qpti->differential && 641 (curstat & SREG_DSENSE) != SREG_DSENSE) { 642 error++; 643 printk("qlogicpti%d: You have a single ended device on a " 644 "differential bus! Please fix!\n", qpti->qpti_id); 645 } 646 qpti->swsreg = curstat; 647 return error; 648 } 649 return 0; 650 } 651 652 static irqreturn_t qpti_intr(int irq, void *dev_id); 653 654 static void __devinit qpti_chain_add(struct qlogicpti *qpti) 655 { 656 spin_lock_irq(&qptichain_lock); 657 if (qptichain != NULL) { 658 struct qlogicpti *qlink = qptichain; 659 660 while(qlink->next) 661 qlink = qlink->next; 662 qlink->next = qpti; 663 } else { 664 qptichain = qpti; 665 } 666 qpti->next = NULL; 667 spin_unlock_irq(&qptichain_lock); 668 } 669 670 static void __devexit qpti_chain_del(struct qlogicpti *qpti) 671 { 672 spin_lock_irq(&qptichain_lock); 673 if (qptichain == qpti) { 674 qptichain = qpti->next; 675 } else { 676 struct qlogicpti *qlink = qptichain; 677 while(qlink->next != qpti) 678 qlink = qlink->next; 679 qlink->next = qpti->next; 680 } 681 qpti->next = NULL; 682 spin_unlock_irq(&qptichain_lock); 683 } 684 685 static int __devinit qpti_map_regs(struct qlogicpti *qpti) 686 { 687 struct sbus_dev *sdev = qpti->sdev; 688 689 qpti->qregs = sbus_ioremap(&sdev->resource[0], 0, 690 sdev->reg_addrs[0].reg_size, 691 "PTI Qlogic/ISP"); 692 if (!qpti->qregs) { 693 printk("PTI: Qlogic/ISP registers are unmappable\n"); 694 return -1; 695 } 696 if (qpti->is_pti) { 697 qpti->sreg = sbus_ioremap(&sdev->resource[0], (16 * 4096), 698 sizeof(unsigned char), 699 "PTI Qlogic/ISP statreg"); 700 if (!qpti->sreg) { 701 printk("PTI: Qlogic/ISP status register is unmappable\n"); 702 return -1; 703 } 704 } 705 return 0; 706 } 707 708 static int __devinit qpti_register_irq(struct qlogicpti *qpti) 709 { 710 struct sbus_dev *sdev = qpti->sdev; 711 712 qpti->qhost->irq = qpti->irq = sdev->irqs[0]; 713 714 /* We used to try various overly-clever things to 715 * reduce the interrupt processing overhead on 716 * sun4c/sun4m when multiple PTI's shared the 717 * same IRQ. It was too complex and messy to 718 * sanely maintain. 719 */ 720 if (request_irq(qpti->irq, qpti_intr, 721 IRQF_SHARED, "Qlogic/PTI", qpti)) 722 goto fail; 723 724 printk("qlogicpti%d: IRQ %d ", qpti->qpti_id, qpti->irq); 725 726 return 0; 727 728 fail: 729 printk("qlogicpti%d: Cannot acquire irq line\n", qpti->qpti_id); 730 return -1; 731 } 732 733 static void __devinit qpti_get_scsi_id(struct qlogicpti *qpti) 734 { 735 qpti->scsi_id = prom_getintdefault(qpti->prom_node, 736 "initiator-id", 737 -1); 738 if (qpti->scsi_id == -1) 739 qpti->scsi_id = prom_getintdefault(qpti->prom_node, 740 "scsi-initiator-id", 741 -1); 742 if (qpti->scsi_id == -1) 743 qpti->scsi_id = 744 prom_getintdefault(qpti->sdev->bus->prom_node, 745 "scsi-initiator-id", 7); 746 qpti->qhost->this_id = qpti->scsi_id; 747 qpti->qhost->max_sectors = 64; 748 749 printk("SCSI ID %d ", qpti->scsi_id); 750 } 751 752 static void qpti_get_bursts(struct qlogicpti *qpti) 753 { 754 struct sbus_dev *sdev = qpti->sdev; 755 u8 bursts, bmask; 756 757 bursts = prom_getintdefault(qpti->prom_node, "burst-sizes", 0xff); 758 bmask = prom_getintdefault(sdev->bus->prom_node, 759 "burst-sizes", 0xff); 760 if (bmask != 0xff) 761 bursts &= bmask; 762 if (bursts == 0xff || 763 (bursts & DMA_BURST16) == 0 || 764 (bursts & DMA_BURST32) == 0) 765 bursts = (DMA_BURST32 - 1); 766 767 qpti->bursts = bursts; 768 } 769 770 static void qpti_get_clock(struct qlogicpti *qpti) 771 { 772 unsigned int cfreq; 773 774 /* Check for what the clock input to this card is. 775 * Default to 40Mhz. 776 */ 777 cfreq = prom_getintdefault(qpti->prom_node,"clock-frequency",40000000); 778 qpti->clock = (cfreq + 500000)/1000000; 779 if (qpti->clock == 0) /* bullshit */ 780 qpti->clock = 40; 781 } 782 783 /* The request and response queues must each be aligned 784 * on a page boundary. 785 */ 786 static int __devinit qpti_map_queues(struct qlogicpti *qpti) 787 { 788 struct sbus_dev *sdev = qpti->sdev; 789 790 #define QSIZE(entries) (((entries) + 1) * QUEUE_ENTRY_LEN) 791 qpti->res_cpu = sbus_alloc_consistent(sdev, 792 QSIZE(RES_QUEUE_LEN), 793 &qpti->res_dvma); 794 if (qpti->res_cpu == NULL || 795 qpti->res_dvma == 0) { 796 printk("QPTI: Cannot map response queue.\n"); 797 return -1; 798 } 799 800 qpti->req_cpu = sbus_alloc_consistent(sdev, 801 QSIZE(QLOGICPTI_REQ_QUEUE_LEN), 802 &qpti->req_dvma); 803 if (qpti->req_cpu == NULL || 804 qpti->req_dvma == 0) { 805 sbus_free_consistent(sdev, QSIZE(RES_QUEUE_LEN), 806 qpti->res_cpu, qpti->res_dvma); 807 printk("QPTI: Cannot map request queue.\n"); 808 return -1; 809 } 810 memset(qpti->res_cpu, 0, QSIZE(RES_QUEUE_LEN)); 811 memset(qpti->req_cpu, 0, QSIZE(QLOGICPTI_REQ_QUEUE_LEN)); 812 return 0; 813 } 814 815 const char *qlogicpti_info(struct Scsi_Host *host) 816 { 817 static char buf[80]; 818 struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata; 819 820 sprintf(buf, "PTI Qlogic,ISP SBUS SCSI irq %d regs at %p", 821 qpti->qhost->irq, qpti->qregs); 822 return buf; 823 } 824 825 /* I am a certified frobtronicist. */ 826 static inline void marker_frob(struct Command_Entry *cmd) 827 { 828 struct Marker_Entry *marker = (struct Marker_Entry *) cmd; 829 830 memset(marker, 0, sizeof(struct Marker_Entry)); 831 marker->hdr.entry_cnt = 1; 832 marker->hdr.entry_type = ENTRY_MARKER; 833 marker->modifier = SYNC_ALL; 834 marker->rsvd = 0; 835 } 836 837 static inline void cmd_frob(struct Command_Entry *cmd, struct scsi_cmnd *Cmnd, 838 struct qlogicpti *qpti) 839 { 840 memset(cmd, 0, sizeof(struct Command_Entry)); 841 cmd->hdr.entry_cnt = 1; 842 cmd->hdr.entry_type = ENTRY_COMMAND; 843 cmd->target_id = Cmnd->device->id; 844 cmd->target_lun = Cmnd->device->lun; 845 cmd->cdb_length = Cmnd->cmd_len; 846 cmd->control_flags = 0; 847 if (Cmnd->device->tagged_supported) { 848 if (qpti->cmd_count[Cmnd->device->id] == 0) 849 qpti->tag_ages[Cmnd->device->id] = jiffies; 850 if (time_after(jiffies, qpti->tag_ages[Cmnd->device->id] + (5*HZ))) { 851 cmd->control_flags = CFLAG_ORDERED_TAG; 852 qpti->tag_ages[Cmnd->device->id] = jiffies; 853 } else 854 cmd->control_flags = CFLAG_SIMPLE_TAG; 855 } 856 if ((Cmnd->cmnd[0] == WRITE_6) || 857 (Cmnd->cmnd[0] == WRITE_10) || 858 (Cmnd->cmnd[0] == WRITE_12)) 859 cmd->control_flags |= CFLAG_WRITE; 860 else 861 cmd->control_flags |= CFLAG_READ; 862 cmd->time_out = 30; 863 memcpy(cmd->cdb, Cmnd->cmnd, Cmnd->cmd_len); 864 } 865 866 /* Do it to it baby. */ 867 static inline int load_cmd(struct scsi_cmnd *Cmnd, struct Command_Entry *cmd, 868 struct qlogicpti *qpti, u_int in_ptr, u_int out_ptr) 869 { 870 struct dataseg *ds; 871 struct scatterlist *sg, *s; 872 int i, n; 873 874 if (scsi_bufflen(Cmnd)) { 875 int sg_count; 876 877 sg = scsi_sglist(Cmnd); 878 sg_count = sbus_map_sg(qpti->sdev, sg, scsi_sg_count(Cmnd), 879 Cmnd->sc_data_direction); 880 881 ds = cmd->dataseg; 882 cmd->segment_cnt = sg_count; 883 884 /* Fill in first four sg entries: */ 885 n = sg_count; 886 if (n > 4) 887 n = 4; 888 for_each_sg(sg, s, n, i) { 889 ds[i].d_base = sg_dma_address(s); 890 ds[i].d_count = sg_dma_len(s); 891 } 892 sg_count -= 4; 893 sg = s; 894 while (sg_count > 0) { 895 struct Continuation_Entry *cont; 896 897 ++cmd->hdr.entry_cnt; 898 cont = (struct Continuation_Entry *) &qpti->req_cpu[in_ptr]; 899 in_ptr = NEXT_REQ_PTR(in_ptr); 900 if (in_ptr == out_ptr) 901 return -1; 902 903 cont->hdr.entry_type = ENTRY_CONTINUATION; 904 cont->hdr.entry_cnt = 0; 905 cont->hdr.sys_def_1 = 0; 906 cont->hdr.flags = 0; 907 cont->reserved = 0; 908 ds = cont->dataseg; 909 n = sg_count; 910 if (n > 7) 911 n = 7; 912 for_each_sg(sg, s, n, i) { 913 ds[i].d_base = sg_dma_address(s); 914 ds[i].d_count = sg_dma_len(s); 915 } 916 sg_count -= n; 917 } 918 } else { 919 cmd->dataseg[0].d_base = 0; 920 cmd->dataseg[0].d_count = 0; 921 cmd->segment_cnt = 1; /* Shouldn't this be 0? */ 922 } 923 924 /* Committed, record Scsi_Cmd so we can find it later. */ 925 cmd->handle = in_ptr; 926 qpti->cmd_slots[in_ptr] = Cmnd; 927 928 qpti->cmd_count[Cmnd->device->id]++; 929 sbus_writew(in_ptr, qpti->qregs + MBOX4); 930 qpti->req_in_ptr = in_ptr; 931 932 return in_ptr; 933 } 934 935 static inline void update_can_queue(struct Scsi_Host *host, u_int in_ptr, u_int out_ptr) 936 { 937 /* Temporary workaround until bug is found and fixed (one bug has been found 938 already, but fixing it makes things even worse) -jj */ 939 int num_free = QLOGICPTI_REQ_QUEUE_LEN - REQ_QUEUE_DEPTH(in_ptr, out_ptr) - 64; 940 host->can_queue = host->host_busy + num_free; 941 host->sg_tablesize = QLOGICPTI_MAX_SG(num_free); 942 } 943 944 static int qlogicpti_slave_configure(struct scsi_device *sdev) 945 { 946 struct qlogicpti *qpti = shost_priv(sdev->host); 947 int tgt = sdev->id; 948 u_short param[6]; 949 950 /* tags handled in midlayer */ 951 /* enable sync mode? */ 952 if (sdev->sdtr) { 953 qpti->dev_param[tgt].device_flags |= 0x10; 954 } else { 955 qpti->dev_param[tgt].synchronous_offset = 0; 956 qpti->dev_param[tgt].synchronous_period = 0; 957 } 958 /* are we wide capable? */ 959 if (sdev->wdtr) 960 qpti->dev_param[tgt].device_flags |= 0x20; 961 962 param[0] = MBOX_SET_TARGET_PARAMS; 963 param[1] = (tgt << 8); 964 param[2] = (qpti->dev_param[tgt].device_flags << 8); 965 if (qpti->dev_param[tgt].device_flags & 0x10) { 966 param[3] = (qpti->dev_param[tgt].synchronous_offset << 8) | 967 qpti->dev_param[tgt].synchronous_period; 968 } else { 969 param[3] = 0; 970 } 971 qlogicpti_mbox_command(qpti, param, 0); 972 return 0; 973 } 974 975 /* 976 * The middle SCSI layer ensures that queuecommand never gets invoked 977 * concurrently with itself or the interrupt handler (though the 978 * interrupt handler may call this routine as part of 979 * request-completion handling). 980 * 981 * "This code must fly." -davem 982 */ 983 static int qlogicpti_queuecommand(struct scsi_cmnd *Cmnd, void (*done)(struct scsi_cmnd *)) 984 { 985 struct Scsi_Host *host = Cmnd->device->host; 986 struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata; 987 struct Command_Entry *cmd; 988 u_int out_ptr; 989 int in_ptr; 990 991 Cmnd->scsi_done = done; 992 993 in_ptr = qpti->req_in_ptr; 994 cmd = (struct Command_Entry *) &qpti->req_cpu[in_ptr]; 995 out_ptr = sbus_readw(qpti->qregs + MBOX4); 996 in_ptr = NEXT_REQ_PTR(in_ptr); 997 if (in_ptr == out_ptr) 998 goto toss_command; 999 1000 if (qpti->send_marker) { 1001 marker_frob(cmd); 1002 qpti->send_marker = 0; 1003 if (NEXT_REQ_PTR(in_ptr) == out_ptr) { 1004 sbus_writew(in_ptr, qpti->qregs + MBOX4); 1005 qpti->req_in_ptr = in_ptr; 1006 goto toss_command; 1007 } 1008 cmd = (struct Command_Entry *) &qpti->req_cpu[in_ptr]; 1009 in_ptr = NEXT_REQ_PTR(in_ptr); 1010 } 1011 cmd_frob(cmd, Cmnd, qpti); 1012 if ((in_ptr = load_cmd(Cmnd, cmd, qpti, in_ptr, out_ptr)) == -1) 1013 goto toss_command; 1014 1015 update_can_queue(host, in_ptr, out_ptr); 1016 1017 return 0; 1018 1019 toss_command: 1020 printk(KERN_EMERG "qlogicpti%d: request queue overflow\n", 1021 qpti->qpti_id); 1022 1023 /* Unfortunately, unless you use the new EH code, which 1024 * we don't, the midlayer will ignore the return value, 1025 * which is insane. We pick up the pieces like this. 1026 */ 1027 Cmnd->result = DID_BUS_BUSY; 1028 done(Cmnd); 1029 return 1; 1030 } 1031 1032 static int qlogicpti_return_status(struct Status_Entry *sts, int id) 1033 { 1034 int host_status = DID_ERROR; 1035 1036 switch (sts->completion_status) { 1037 case CS_COMPLETE: 1038 host_status = DID_OK; 1039 break; 1040 case CS_INCOMPLETE: 1041 if (!(sts->state_flags & SF_GOT_BUS)) 1042 host_status = DID_NO_CONNECT; 1043 else if (!(sts->state_flags & SF_GOT_TARGET)) 1044 host_status = DID_BAD_TARGET; 1045 else if (!(sts->state_flags & SF_SENT_CDB)) 1046 host_status = DID_ERROR; 1047 else if (!(sts->state_flags & SF_TRANSFERRED_DATA)) 1048 host_status = DID_ERROR; 1049 else if (!(sts->state_flags & SF_GOT_STATUS)) 1050 host_status = DID_ERROR; 1051 else if (!(sts->state_flags & SF_GOT_SENSE)) 1052 host_status = DID_ERROR; 1053 break; 1054 case CS_DMA_ERROR: 1055 case CS_TRANSPORT_ERROR: 1056 host_status = DID_ERROR; 1057 break; 1058 case CS_RESET_OCCURRED: 1059 case CS_BUS_RESET: 1060 host_status = DID_RESET; 1061 break; 1062 case CS_ABORTED: 1063 host_status = DID_ABORT; 1064 break; 1065 case CS_TIMEOUT: 1066 host_status = DID_TIME_OUT; 1067 break; 1068 case CS_DATA_OVERRUN: 1069 case CS_COMMAND_OVERRUN: 1070 case CS_STATUS_OVERRUN: 1071 case CS_BAD_MESSAGE: 1072 case CS_NO_MESSAGE_OUT: 1073 case CS_EXT_ID_FAILED: 1074 case CS_IDE_MSG_FAILED: 1075 case CS_ABORT_MSG_FAILED: 1076 case CS_NOP_MSG_FAILED: 1077 case CS_PARITY_ERROR_MSG_FAILED: 1078 case CS_DEVICE_RESET_MSG_FAILED: 1079 case CS_ID_MSG_FAILED: 1080 case CS_UNEXP_BUS_FREE: 1081 host_status = DID_ERROR; 1082 break; 1083 case CS_DATA_UNDERRUN: 1084 host_status = DID_OK; 1085 break; 1086 default: 1087 printk(KERN_EMERG "qlogicpti%d: unknown completion status 0x%04x\n", 1088 id, sts->completion_status); 1089 host_status = DID_ERROR; 1090 break; 1091 } 1092 1093 return (sts->scsi_status & STATUS_MASK) | (host_status << 16); 1094 } 1095 1096 static struct scsi_cmnd *qlogicpti_intr_handler(struct qlogicpti *qpti) 1097 { 1098 struct scsi_cmnd *Cmnd, *done_queue = NULL; 1099 struct Status_Entry *sts; 1100 u_int in_ptr, out_ptr; 1101 1102 if (!(sbus_readw(qpti->qregs + SBUS_STAT) & SBUS_STAT_RINT)) 1103 return NULL; 1104 1105 in_ptr = sbus_readw(qpti->qregs + MBOX5); 1106 sbus_writew(HCCTRL_CRIRQ, qpti->qregs + HCCTRL); 1107 if (sbus_readw(qpti->qregs + SBUS_SEMAPHORE) & SBUS_SEMAPHORE_LCK) { 1108 switch (sbus_readw(qpti->qregs + MBOX0)) { 1109 case ASYNC_SCSI_BUS_RESET: 1110 case EXECUTION_TIMEOUT_RESET: 1111 qpti->send_marker = 1; 1112 break; 1113 case INVALID_COMMAND: 1114 case HOST_INTERFACE_ERROR: 1115 case COMMAND_ERROR: 1116 case COMMAND_PARAM_ERROR: 1117 break; 1118 }; 1119 sbus_writew(0, qpti->qregs + SBUS_SEMAPHORE); 1120 } 1121 1122 /* This looks like a network driver! */ 1123 out_ptr = qpti->res_out_ptr; 1124 while (out_ptr != in_ptr) { 1125 u_int cmd_slot; 1126 1127 sts = (struct Status_Entry *) &qpti->res_cpu[out_ptr]; 1128 out_ptr = NEXT_RES_PTR(out_ptr); 1129 1130 /* We store an index in the handle, not the pointer in 1131 * some form. This avoids problems due to the fact 1132 * that the handle provided is only 32-bits. -DaveM 1133 */ 1134 cmd_slot = sts->handle; 1135 Cmnd = qpti->cmd_slots[cmd_slot]; 1136 qpti->cmd_slots[cmd_slot] = NULL; 1137 1138 if (sts->completion_status == CS_RESET_OCCURRED || 1139 sts->completion_status == CS_ABORTED || 1140 (sts->status_flags & STF_BUS_RESET)) 1141 qpti->send_marker = 1; 1142 1143 if (sts->state_flags & SF_GOT_SENSE) 1144 memcpy(Cmnd->sense_buffer, sts->req_sense_data, 1145 SCSI_SENSE_BUFFERSIZE); 1146 1147 if (sts->hdr.entry_type == ENTRY_STATUS) 1148 Cmnd->result = 1149 qlogicpti_return_status(sts, qpti->qpti_id); 1150 else 1151 Cmnd->result = DID_ERROR << 16; 1152 1153 if (scsi_bufflen(Cmnd)) 1154 sbus_unmap_sg(qpti->sdev, 1155 scsi_sglist(Cmnd), scsi_sg_count(Cmnd), 1156 Cmnd->sc_data_direction); 1157 1158 qpti->cmd_count[Cmnd->device->id]--; 1159 sbus_writew(out_ptr, qpti->qregs + MBOX5); 1160 Cmnd->host_scribble = (unsigned char *) done_queue; 1161 done_queue = Cmnd; 1162 } 1163 qpti->res_out_ptr = out_ptr; 1164 1165 return done_queue; 1166 } 1167 1168 static irqreturn_t qpti_intr(int irq, void *dev_id) 1169 { 1170 struct qlogicpti *qpti = dev_id; 1171 unsigned long flags; 1172 struct scsi_cmnd *dq; 1173 1174 spin_lock_irqsave(qpti->qhost->host_lock, flags); 1175 dq = qlogicpti_intr_handler(qpti); 1176 1177 if (dq != NULL) { 1178 do { 1179 struct scsi_cmnd *next; 1180 1181 next = (struct scsi_cmnd *) dq->host_scribble; 1182 dq->scsi_done(dq); 1183 dq = next; 1184 } while (dq != NULL); 1185 } 1186 spin_unlock_irqrestore(qpti->qhost->host_lock, flags); 1187 1188 return IRQ_HANDLED; 1189 } 1190 1191 static int qlogicpti_abort(struct scsi_cmnd *Cmnd) 1192 { 1193 u_short param[6]; 1194 struct Scsi_Host *host = Cmnd->device->host; 1195 struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata; 1196 int return_status = SUCCESS; 1197 u32 cmd_cookie; 1198 int i; 1199 1200 printk(KERN_WARNING "qlogicpti%d: Aborting cmd for tgt[%d] lun[%d]\n", 1201 qpti->qpti_id, (int)Cmnd->device->id, (int)Cmnd->device->lun); 1202 1203 qlogicpti_disable_irqs(qpti); 1204 1205 /* Find the 32-bit cookie we gave to the firmware for 1206 * this command. 1207 */ 1208 for (i = 0; i < QLOGICPTI_REQ_QUEUE_LEN + 1; i++) 1209 if (qpti->cmd_slots[i] == Cmnd) 1210 break; 1211 cmd_cookie = i; 1212 1213 param[0] = MBOX_ABORT; 1214 param[1] = (((u_short) Cmnd->device->id) << 8) | Cmnd->device->lun; 1215 param[2] = cmd_cookie >> 16; 1216 param[3] = cmd_cookie & 0xffff; 1217 if (qlogicpti_mbox_command(qpti, param, 0) || 1218 (param[0] != MBOX_COMMAND_COMPLETE)) { 1219 printk(KERN_EMERG "qlogicpti%d: scsi abort failure: %x\n", 1220 qpti->qpti_id, param[0]); 1221 return_status = FAILED; 1222 } 1223 1224 qlogicpti_enable_irqs(qpti); 1225 1226 return return_status; 1227 } 1228 1229 static int qlogicpti_reset(struct scsi_cmnd *Cmnd) 1230 { 1231 u_short param[6]; 1232 struct Scsi_Host *host = Cmnd->device->host; 1233 struct qlogicpti *qpti = (struct qlogicpti *) host->hostdata; 1234 int return_status = SUCCESS; 1235 1236 printk(KERN_WARNING "qlogicpti%d: Resetting SCSI bus!\n", 1237 qpti->qpti_id); 1238 1239 qlogicpti_disable_irqs(qpti); 1240 1241 param[0] = MBOX_BUS_RESET; 1242 param[1] = qpti->host_param.bus_reset_delay; 1243 if (qlogicpti_mbox_command(qpti, param, 0) || 1244 (param[0] != MBOX_COMMAND_COMPLETE)) { 1245 printk(KERN_EMERG "qlogicisp%d: scsi bus reset failure: %x\n", 1246 qpti->qpti_id, param[0]); 1247 return_status = FAILED; 1248 } 1249 1250 qlogicpti_enable_irqs(qpti); 1251 1252 return return_status; 1253 } 1254 1255 static struct scsi_host_template qpti_template = { 1256 .module = THIS_MODULE, 1257 .name = "qlogicpti", 1258 .info = qlogicpti_info, 1259 .queuecommand = qlogicpti_queuecommand, 1260 .slave_configure = qlogicpti_slave_configure, 1261 .eh_abort_handler = qlogicpti_abort, 1262 .eh_bus_reset_handler = qlogicpti_reset, 1263 .can_queue = QLOGICPTI_REQ_QUEUE_LEN, 1264 .this_id = 7, 1265 .sg_tablesize = QLOGICPTI_MAX_SG(QLOGICPTI_REQ_QUEUE_LEN), 1266 .cmd_per_lun = 1, 1267 .use_clustering = ENABLE_CLUSTERING, 1268 }; 1269 1270 static int __devinit qpti_sbus_probe(struct of_device *dev, const struct of_device_id *match) 1271 { 1272 static int nqptis; 1273 struct sbus_dev *sdev = to_sbus_device(&dev->dev); 1274 struct device_node *dp = dev->node; 1275 struct scsi_host_template *tpnt = match->data; 1276 struct Scsi_Host *host; 1277 struct qlogicpti *qpti; 1278 const char *fcode; 1279 1280 /* Sometimes Antares cards come up not completely 1281 * setup, and we get a report of a zero IRQ. 1282 */ 1283 if (sdev->irqs[0] == 0) 1284 return -ENODEV; 1285 1286 host = scsi_host_alloc(tpnt, sizeof(struct qlogicpti)); 1287 if (!host) 1288 return -ENOMEM; 1289 1290 qpti = (struct qlogicpti *) host->hostdata; 1291 1292 host->max_id = MAX_TARGETS; 1293 qpti->qhost = host; 1294 qpti->sdev = sdev; 1295 qpti->qpti_id = nqptis; 1296 qpti->prom_node = sdev->prom_node; 1297 strcpy(qpti->prom_name, sdev->ofdev.node->name); 1298 qpti->is_pti = strcmp(qpti->prom_name, "QLGC,isp"); 1299 1300 if (qpti_map_regs(qpti) < 0) 1301 goto fail_unlink; 1302 1303 if (qpti_register_irq(qpti) < 0) 1304 goto fail_unmap_regs; 1305 1306 qpti_get_scsi_id(qpti); 1307 qpti_get_bursts(qpti); 1308 qpti_get_clock(qpti); 1309 1310 /* Clear out scsi_cmnd array. */ 1311 memset(qpti->cmd_slots, 0, sizeof(qpti->cmd_slots)); 1312 1313 if (qpti_map_queues(qpti) < 0) 1314 goto fail_free_irq; 1315 1316 /* Load the firmware. */ 1317 if (qlogicpti_load_firmware(qpti)) 1318 goto fail_unmap_queues; 1319 if (qpti->is_pti) { 1320 /* Check the PTI status reg. */ 1321 if (qlogicpti_verify_tmon(qpti)) 1322 goto fail_unmap_queues; 1323 } 1324 1325 /* Reset the ISP and init res/req queues. */ 1326 if (qlogicpti_reset_hardware(host)) 1327 goto fail_unmap_queues; 1328 1329 printk("(Firmware v%d.%d.%d)", qpti->fware_majrev, 1330 qpti->fware_minrev, qpti->fware_micrev); 1331 1332 fcode = of_get_property(dp, "isp-fcode", NULL); 1333 if (fcode && fcode[0]) 1334 printk("(FCode %s)", fcode); 1335 if (of_find_property(dp, "differential", NULL) != NULL) 1336 qpti->differential = 1; 1337 1338 printk("\nqlogicpti%d: [%s Wide, using %s interface]\n", 1339 qpti->qpti_id, 1340 (qpti->ultra ? "Ultra" : "Fast"), 1341 (qpti->differential ? "differential" : "single ended")); 1342 1343 if (scsi_add_host(host, &dev->dev)) { 1344 printk("qlogicpti%d: Failed scsi_add_host\n", qpti->qpti_id); 1345 goto fail_unmap_queues; 1346 } 1347 1348 dev_set_drvdata(&sdev->ofdev.dev, qpti); 1349 1350 qpti_chain_add(qpti); 1351 1352 scsi_scan_host(host); 1353 nqptis++; 1354 1355 return 0; 1356 1357 fail_unmap_queues: 1358 #define QSIZE(entries) (((entries) + 1) * QUEUE_ENTRY_LEN) 1359 sbus_free_consistent(qpti->sdev, 1360 QSIZE(RES_QUEUE_LEN), 1361 qpti->res_cpu, qpti->res_dvma); 1362 sbus_free_consistent(qpti->sdev, 1363 QSIZE(QLOGICPTI_REQ_QUEUE_LEN), 1364 qpti->req_cpu, qpti->req_dvma); 1365 #undef QSIZE 1366 1367 fail_unmap_regs: 1368 sbus_iounmap(qpti->qregs, 1369 qpti->sdev->reg_addrs[0].reg_size); 1370 if (qpti->is_pti) 1371 sbus_iounmap(qpti->sreg, sizeof(unsigned char)); 1372 1373 fail_free_irq: 1374 free_irq(qpti->irq, qpti); 1375 1376 fail_unlink: 1377 scsi_host_put(host); 1378 1379 return -ENODEV; 1380 } 1381 1382 static int __devexit qpti_sbus_remove(struct of_device *dev) 1383 { 1384 struct qlogicpti *qpti = dev_get_drvdata(&dev->dev); 1385 1386 qpti_chain_del(qpti); 1387 1388 scsi_remove_host(qpti->qhost); 1389 1390 /* Shut up the card. */ 1391 sbus_writew(0, qpti->qregs + SBUS_CTRL); 1392 1393 /* Free IRQ handler and unmap Qlogic,ISP and PTI status regs. */ 1394 free_irq(qpti->irq, qpti); 1395 1396 #define QSIZE(entries) (((entries) + 1) * QUEUE_ENTRY_LEN) 1397 sbus_free_consistent(qpti->sdev, 1398 QSIZE(RES_QUEUE_LEN), 1399 qpti->res_cpu, qpti->res_dvma); 1400 sbus_free_consistent(qpti->sdev, 1401 QSIZE(QLOGICPTI_REQ_QUEUE_LEN), 1402 qpti->req_cpu, qpti->req_dvma); 1403 #undef QSIZE 1404 1405 sbus_iounmap(qpti->qregs, qpti->sdev->reg_addrs[0].reg_size); 1406 if (qpti->is_pti) 1407 sbus_iounmap(qpti->sreg, sizeof(unsigned char)); 1408 1409 scsi_host_put(qpti->qhost); 1410 1411 return 0; 1412 } 1413 1414 static struct of_device_id qpti_match[] = { 1415 { 1416 .name = "ptisp", 1417 .data = &qpti_template, 1418 }, 1419 { 1420 .name = "PTI,ptisp", 1421 .data = &qpti_template, 1422 }, 1423 { 1424 .name = "QLGC,isp", 1425 .data = &qpti_template, 1426 }, 1427 { 1428 .name = "SUNW,isp", 1429 .data = &qpti_template, 1430 }, 1431 {}, 1432 }; 1433 MODULE_DEVICE_TABLE(of, qpti_match); 1434 1435 static struct of_platform_driver qpti_sbus_driver = { 1436 .name = "qpti", 1437 .match_table = qpti_match, 1438 .probe = qpti_sbus_probe, 1439 .remove = __devexit_p(qpti_sbus_remove), 1440 }; 1441 1442 static int __init qpti_init(void) 1443 { 1444 return of_register_driver(&qpti_sbus_driver, &sbus_bus_type); 1445 } 1446 1447 static void __exit qpti_exit(void) 1448 { 1449 of_unregister_driver(&qpti_sbus_driver); 1450 } 1451 1452 MODULE_DESCRIPTION("QlogicISP SBUS driver"); 1453 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); 1454 MODULE_LICENSE("GPL"); 1455 MODULE_VERSION("2.0"); 1456 1457 module_init(qpti_init); 1458 module_exit(qpti_exit); 1459