1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_NX_H 8 #define __QLA_NX_H 9 10 /* 11 * Following are the states of the Phantom. Phantom will set them and 12 * Host will read to check if the fields are correct. 13 */ 14 #define PHAN_INITIALIZE_FAILED 0xffff 15 #define PHAN_INITIALIZE_COMPLETE 0xff01 16 17 /* Host writes the following to notify that it has done the init-handshake */ 18 #define PHAN_INITIALIZE_ACK 0xf00f 19 #define PHAN_PEG_RCV_INITIALIZED 0xff01 20 21 /*CRB_RELATED*/ 22 #define QLA82XX_CRB_BASE (QLA82XX_CAM_RAM(0x200)) 23 #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X)) 24 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50) 25 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c) 26 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc) 27 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4) 28 29 #define qla82xx_get_temp_val(x) ((x) >> 16) 30 #define qla82xx_get_temp_state(x) ((x) & 0xffff) 31 #define qla82xx_encode_temp(val, state) (((val) << 16) | (state)) 32 33 /* 34 * Temperature control. 35 */ 36 enum { 37 QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */ 38 QLA82XX_TEMP_WARN, /* Sound alert, temperature getting high */ 39 QLA82XX_TEMP_PANIC /* Fatal error, hardware has shut down. */ 40 }; 41 42 #define CRB_NIU_XG_PAUSE_CTL_P0 0x1 43 #define CRB_NIU_XG_PAUSE_CTL_P1 0x8 44 45 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05 46 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E 47 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03 48 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01 49 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06 50 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07 51 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08 52 53 /* Hub 0 */ 54 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15 55 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25 56 57 /* Hub 1 */ 58 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73 59 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00 60 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b 61 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01 62 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02 63 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03 64 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04 65 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58 66 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59 67 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a 68 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a 69 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c 70 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f 71 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12 72 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18 73 74 /* Hub 2 */ 75 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31 76 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19 77 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29 78 79 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10 80 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20 81 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22 82 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21 83 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66 84 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60 85 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61 86 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62 87 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63 88 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09 89 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d 90 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e 91 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11 92 93 /* Hub 3 */ 94 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A 95 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50 96 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51 97 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08 98 99 /* Hub 4 */ 100 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40 101 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41 102 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42 103 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43 104 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44 105 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45 106 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46 107 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47 108 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48 109 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49 110 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a 111 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b 112 113 /* Hub 5 */ 114 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40 115 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41 116 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42 117 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43 118 119 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44 120 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45 121 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46 122 123 /* Hub 6 */ 124 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46 125 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47 126 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48 127 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49 128 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16 129 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17 130 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05 131 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06 132 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07 133 134 /* This field defines PCI/X adr [25:20] of agents on the CRB */ 135 /* */ 136 #define QLA82XX_HW_PX_MAP_CRB_PH 0 137 #define QLA82XX_HW_PX_MAP_CRB_PS 1 138 #define QLA82XX_HW_PX_MAP_CRB_MN 2 139 #define QLA82XX_HW_PX_MAP_CRB_MS 3 140 #define QLA82XX_HW_PX_MAP_CRB_SRE 5 141 #define QLA82XX_HW_PX_MAP_CRB_NIU 6 142 #define QLA82XX_HW_PX_MAP_CRB_QMN 7 143 #define QLA82XX_HW_PX_MAP_CRB_SQN0 8 144 #define QLA82XX_HW_PX_MAP_CRB_SQN1 9 145 #define QLA82XX_HW_PX_MAP_CRB_SQN2 10 146 #define QLA82XX_HW_PX_MAP_CRB_SQN3 11 147 #define QLA82XX_HW_PX_MAP_CRB_QMS 12 148 #define QLA82XX_HW_PX_MAP_CRB_SQS0 13 149 #define QLA82XX_HW_PX_MAP_CRB_SQS1 14 150 #define QLA82XX_HW_PX_MAP_CRB_SQS2 15 151 #define QLA82XX_HW_PX_MAP_CRB_SQS3 16 152 #define QLA82XX_HW_PX_MAP_CRB_PGN0 17 153 #define QLA82XX_HW_PX_MAP_CRB_PGN1 18 154 #define QLA82XX_HW_PX_MAP_CRB_PGN2 19 155 #define QLA82XX_HW_PX_MAP_CRB_PGN3 20 156 #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2 157 #define QLA82XX_HW_PX_MAP_CRB_PGND 21 158 #define QLA82XX_HW_PX_MAP_CRB_PGNI 22 159 #define QLA82XX_HW_PX_MAP_CRB_PGS0 23 160 #define QLA82XX_HW_PX_MAP_CRB_PGS1 24 161 #define QLA82XX_HW_PX_MAP_CRB_PGS2 25 162 #define QLA82XX_HW_PX_MAP_CRB_PGS3 26 163 #define QLA82XX_HW_PX_MAP_CRB_PGSD 27 164 #define QLA82XX_HW_PX_MAP_CRB_PGSI 28 165 #define QLA82XX_HW_PX_MAP_CRB_SN 29 166 #define QLA82XX_HW_PX_MAP_CRB_EG 31 167 #define QLA82XX_HW_PX_MAP_CRB_PH2 32 168 #define QLA82XX_HW_PX_MAP_CRB_PS2 33 169 #define QLA82XX_HW_PX_MAP_CRB_CAM 34 170 #define QLA82XX_HW_PX_MAP_CRB_CAS0 35 171 #define QLA82XX_HW_PX_MAP_CRB_CAS1 36 172 #define QLA82XX_HW_PX_MAP_CRB_CAS2 37 173 #define QLA82XX_HW_PX_MAP_CRB_C2C0 38 174 #define QLA82XX_HW_PX_MAP_CRB_C2C1 39 175 #define QLA82XX_HW_PX_MAP_CRB_TIMR 40 176 #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42 177 #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43 178 #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44 179 #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45 180 #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46 181 #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47 182 #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48 183 #define QLA82XX_HW_PX_MAP_CRB_XDMA 49 184 #define QLA82XX_HW_PX_MAP_CRB_I2Q 50 185 #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51 186 #define QLA82XX_HW_PX_MAP_CRB_CAS3 52 187 #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53 188 #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54 189 #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55 190 #define QLA82XX_HW_PX_MAP_CRB_OCM0 56 191 #define QLA82XX_HW_PX_MAP_CRB_OCM1 57 192 #define QLA82XX_HW_PX_MAP_CRB_SMB 58 193 #define QLA82XX_HW_PX_MAP_CRB_I2C0 59 194 #define QLA82XX_HW_PX_MAP_CRB_I2C1 60 195 #define QLA82XX_HW_PX_MAP_CRB_LPC 61 196 #define QLA82XX_HW_PX_MAP_CRB_PGNC 62 197 #define QLA82XX_HW_PX_MAP_CRB_PGR0 63 198 #define QLA82XX_HW_PX_MAP_CRB_PGR1 4 199 #define QLA82XX_HW_PX_MAP_CRB_PGR2 30 200 #define QLA82XX_HW_PX_MAP_CRB_PGR3 41 201 202 /* This field defines CRB adr [31:20] of the agents */ 203 /* */ 204 205 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 206 QLA82XX_HW_MN_CRB_AGT_ADR) 207 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 208 QLA82XX_HW_PH_CRB_AGT_ADR) 209 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ 210 QLA82XX_HW_MS_CRB_AGT_ADR) 211 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 212 QLA82XX_HW_PS_CRB_AGT_ADR) 213 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 214 QLA82XX_HW_SS_CRB_AGT_ADR) 215 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 216 QLA82XX_HW_RPMX3_CRB_AGT_ADR) 217 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 218 QLA82XX_HW_QMS_CRB_AGT_ADR) 219 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 220 QLA82XX_HW_SQGS0_CRB_AGT_ADR) 221 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 222 QLA82XX_HW_SQGS1_CRB_AGT_ADR) 223 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 224 QLA82XX_HW_SQGS2_CRB_AGT_ADR) 225 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 226 QLA82XX_HW_SQGS3_CRB_AGT_ADR) 227 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 228 QLA82XX_HW_C2C0_CRB_AGT_ADR) 229 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 230 QLA82XX_HW_C2C1_CRB_AGT_ADR) 231 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 232 QLA82XX_HW_RPMX2_CRB_AGT_ADR) 233 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 234 QLA82XX_HW_RPMX4_CRB_AGT_ADR) 235 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 236 QLA82XX_HW_RPMX7_CRB_AGT_ADR) 237 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 238 QLA82XX_HW_RPMX9_CRB_AGT_ADR) 239 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ 240 QLA82XX_HW_SMB_CRB_AGT_ADR) 241 242 #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 243 QLA82XX_HW_NIU_CRB_AGT_ADR) 244 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 245 QLA82XX_HW_I2C0_CRB_AGT_ADR) 246 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ 247 QLA82XX_HW_I2C1_CRB_AGT_ADR) 248 249 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 250 QLA82XX_HW_SRE_CRB_AGT_ADR) 251 #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 252 QLA82XX_HW_EG_CRB_AGT_ADR) 253 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 254 QLA82XX_HW_RPMX0_CRB_AGT_ADR) 255 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 256 QLA82XX_HW_QM_CRB_AGT_ADR) 257 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 258 QLA82XX_HW_SQG0_CRB_AGT_ADR) 259 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 260 QLA82XX_HW_SQG1_CRB_AGT_ADR) 261 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 262 QLA82XX_HW_SQG2_CRB_AGT_ADR) 263 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 264 QLA82XX_HW_SQG3_CRB_AGT_ADR) 265 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 266 QLA82XX_HW_RPMX1_CRB_AGT_ADR) 267 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 268 QLA82XX_HW_RPMX5_CRB_AGT_ADR) 269 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 270 QLA82XX_HW_RPMX6_CRB_AGT_ADR) 271 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 272 QLA82XX_HW_RPMX8_CRB_AGT_ADR) 273 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 274 QLA82XX_HW_CAS0_CRB_AGT_ADR) 275 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 276 QLA82XX_HW_CAS1_CRB_AGT_ADR) 277 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 278 QLA82XX_HW_CAS2_CRB_AGT_ADR) 279 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ 280 QLA82XX_HW_CAS3_CRB_AGT_ADR) 281 282 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 283 QLA82XX_HW_PEGNI_CRB_AGT_ADR) 284 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 285 QLA82XX_HW_PEGND_CRB_AGT_ADR) 286 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 287 QLA82XX_HW_PEGN0_CRB_AGT_ADR) 288 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 289 QLA82XX_HW_PEGN1_CRB_AGT_ADR) 290 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 291 QLA82XX_HW_PEGN2_CRB_AGT_ADR) 292 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 293 QLA82XX_HW_PEGN3_CRB_AGT_ADR) 294 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 295 QLA82XX_HW_PEGN4_CRB_AGT_ADR) 296 297 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 298 QLA82XX_HW_PEGNC_CRB_AGT_ADR) 299 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 300 QLA82XX_HW_PEGR0_CRB_AGT_ADR) 301 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 302 QLA82XX_HW_PEGR1_CRB_AGT_ADR) 303 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 304 QLA82XX_HW_PEGR2_CRB_AGT_ADR) 305 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ 306 QLA82XX_HW_PEGR3_CRB_AGT_ADR) 307 308 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 309 QLA82XX_HW_PEGSI_CRB_AGT_ADR) 310 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 311 QLA82XX_HW_PEGSD_CRB_AGT_ADR) 312 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 313 QLA82XX_HW_PEGS0_CRB_AGT_ADR) 314 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 315 QLA82XX_HW_PEGS1_CRB_AGT_ADR) 316 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 317 QLA82XX_HW_PEGS2_CRB_AGT_ADR) 318 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 319 QLA82XX_HW_PEGS3_CRB_AGT_ADR) 320 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ 321 QLA82XX_HW_PEGSC_CRB_AGT_ADR) 322 323 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 324 QLA82XX_HW_NCM_CRB_AGT_ADR) 325 #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 326 QLA82XX_HW_TMR_CRB_AGT_ADR) 327 #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 328 QLA82XX_HW_XDMA_CRB_AGT_ADR) 329 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 330 QLA82XX_HW_SN_CRB_AGT_ADR) 331 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 332 QLA82XX_HW_I2Q_CRB_AGT_ADR) 333 #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 334 QLA82XX_HW_ROMUSB_CRB_AGT_ADR) 335 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 336 QLA82XX_HW_OCM0_CRB_AGT_ADR) 337 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 338 QLA82XX_HW_OCM1_CRB_AGT_ADR) 339 #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ 340 QLA82XX_HW_LPC_CRB_AGT_ADR) 341 342 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000) 343 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) 344 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) 345 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) 346 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) 347 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) 348 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) 349 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) 350 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) 351 352 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000) 353 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) 354 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) 355 356 /* Lock IDs for ROM lock */ 357 #define ROM_LOCK_DRIVER 0x0d417340 358 359 #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */ 360 #define QLA82XX_PCI_CRB_WINDOW(A) (QLA82XX_PCI_CRBSPACE + \ 361 (A)*QLA82XX_PCI_CRB_WINDOWSIZE) 362 363 #define QLA82XX_CRB_C2C_0 \ 364 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0) 365 #define QLA82XX_CRB_C2C_1 \ 366 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1) 367 #define QLA82XX_CRB_C2C_2 \ 368 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2) 369 #define QLA82XX_CRB_CAM \ 370 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM) 371 #define QLA82XX_CRB_CASPER \ 372 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS) 373 #define QLA82XX_CRB_CASPER_0 \ 374 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0) 375 #define QLA82XX_CRB_CASPER_1 \ 376 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1) 377 #define QLA82XX_CRB_CASPER_2 \ 378 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2) 379 #define QLA82XX_CRB_DDR_MD \ 380 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS) 381 #define QLA82XX_CRB_DDR_NET \ 382 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN) 383 #define QLA82XX_CRB_EPG \ 384 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG) 385 #define QLA82XX_CRB_I2Q \ 386 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q) 387 #define QLA82XX_CRB_NIU \ 388 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU) 389 /* HACK upon HACK upon HACK (for PCIE builds) */ 390 #define QLA82XX_CRB_PCIX_HOST \ 391 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH) 392 #define QLA82XX_CRB_PCIX_HOST2 \ 393 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2) 394 #define QLA82XX_CRB_PCIX_MD \ 395 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS) 396 #define QLA82XX_CRB_PCIE QLA82XX_CRB_PCIX_MD 397 /* window 1 pcie slot */ 398 #define QLA82XX_CRB_PCIE2 \ 399 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2) 400 401 #define QLA82XX_CRB_PEG_MD_0 \ 402 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0) 403 #define QLA82XX_CRB_PEG_MD_1 \ 404 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1) 405 #define QLA82XX_CRB_PEG_MD_2 \ 406 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2) 407 #define QLA82XX_CRB_PEG_MD_3 \ 408 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3) 409 #define QLA82XX_CRB_PEG_MD_3 \ 410 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3) 411 #define QLA82XX_CRB_PEG_MD_D \ 412 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD) 413 #define QLA82XX_CRB_PEG_MD_I \ 414 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI) 415 #define QLA82XX_CRB_PEG_NET_0 \ 416 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0) 417 #define QLA82XX_CRB_PEG_NET_1 \ 418 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1) 419 #define QLA82XX_CRB_PEG_NET_2 \ 420 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2) 421 #define QLA82XX_CRB_PEG_NET_3 \ 422 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3) 423 #define QLA82XX_CRB_PEG_NET_4 \ 424 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4) 425 #define QLA82XX_CRB_PEG_NET_D \ 426 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND) 427 #define QLA82XX_CRB_PEG_NET_I \ 428 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI) 429 #define QLA82XX_CRB_PQM_MD \ 430 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS) 431 #define QLA82XX_CRB_PQM_NET \ 432 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN) 433 #define QLA82XX_CRB_QDR_MD \ 434 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS) 435 #define QLA82XX_CRB_QDR_NET \ 436 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN) 437 #define QLA82XX_CRB_ROMUSB \ 438 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB) 439 #define QLA82XX_CRB_RPMX_0 \ 440 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0) 441 #define QLA82XX_CRB_RPMX_1 \ 442 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1) 443 #define QLA82XX_CRB_RPMX_2 \ 444 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2) 445 #define QLA82XX_CRB_RPMX_3 \ 446 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3) 447 #define QLA82XX_CRB_RPMX_4 \ 448 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4) 449 #define QLA82XX_CRB_RPMX_5 \ 450 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5) 451 #define QLA82XX_CRB_RPMX_6 \ 452 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6) 453 #define QLA82XX_CRB_RPMX_7 \ 454 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7) 455 #define QLA82XX_CRB_SQM_MD_0 \ 456 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0) 457 #define QLA82XX_CRB_SQM_MD_1 \ 458 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1) 459 #define QLA82XX_CRB_SQM_MD_2 \ 460 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2) 461 #define QLA82XX_CRB_SQM_MD_3 \ 462 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3) 463 #define QLA82XX_CRB_SQM_NET_0 \ 464 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0) 465 #define QLA82XX_CRB_SQM_NET_1 \ 466 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1) 467 #define QLA82XX_CRB_SQM_NET_2 \ 468 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2) 469 #define QLA82XX_CRB_SQM_NET_3 \ 470 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3) 471 #define QLA82XX_CRB_SRE \ 472 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE) 473 #define QLA82XX_CRB_TIMER \ 474 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR) 475 #define QLA82XX_CRB_XDMA \ 476 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA) 477 #define QLA82XX_CRB_I2C0 \ 478 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0) 479 #define QLA82XX_CRB_I2C1 \ 480 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1) 481 #define QLA82XX_CRB_OCM0 \ 482 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0) 483 #define QLA82XX_CRB_SMB \ 484 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB) 485 486 #define QLA82XX_CRB_MAX QLA82XX_PCI_CRB_WINDOW(64) 487 488 /* 489 * ====================== BASE ADDRESSES ON-CHIP ====================== 490 * Base addresses of major components on-chip. 491 * ====================== BASE ADDRESSES ON-CHIP ====================== 492 */ 493 #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL) 494 #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL) 495 496 /* Imbus address bit used to indicate a host address. This bit is 497 * eliminated by the pcie bar and bar select before presentation 498 * over pcie. */ 499 /* host memory via IMBUS */ 500 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL) 501 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL) 502 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL) 503 #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL) 504 #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL) 505 #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL) 506 #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL) 507 #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL) 508 509 #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL) 510 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL) 511 512 #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000 513 #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000 514 #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000 515 #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff 516 #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000 517 #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000 518 #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff 519 520 /* 521 * Register offsets for MN 522 */ 523 #define MIU_CONTROL (0x000) 524 #define MIU_TAG (0x004) 525 #define MIU_TEST_AGT_CTRL (0x090) 526 #define MIU_TEST_AGT_ADDR_LO (0x094) 527 #define MIU_TEST_AGT_ADDR_HI (0x098) 528 #define MIU_TEST_AGT_WRDATA_LO (0x0a0) 529 #define MIU_TEST_AGT_WRDATA_HI (0x0a4) 530 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i))) 531 #define MIU_TEST_AGT_RDDATA_LO (0x0a8) 532 #define MIU_TEST_AGT_RDDATA_HI (0x0ac) 533 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i))) 534 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 535 #define MIU_TEST_AGT_UPPER_ADDR(off) (0) 536 537 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */ 538 #define MIU_TA_CTL_START 1 539 #define MIU_TA_CTL_ENABLE 2 540 #define MIU_TA_CTL_WRITE 4 541 #define MIU_TA_CTL_BUSY 8 542 543 /*CAM RAM */ 544 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000) 545 # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg)) 546 547 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24)) 548 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8)) 549 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac)) 550 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0)) 551 #define QLA82XX_CAM_RAM_DB1 (QLA82XX_CAM_RAM(0x1b0)) 552 #define QLA82XX_CAM_RAM_DB2 (QLA82XX_CAM_RAM(0x1b4)) 553 554 #define HALT_STATUS_UNRECOVERABLE 0x80000000 555 #define HALT_STATUS_RECOVERABLE 0x40000000 556 557 558 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100)) 559 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124)) 560 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150)) 561 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154)) 562 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158)) 563 #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg)) 564 565 /* Driver Coexistence Defines */ 566 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138)) 567 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140)) 568 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) 569 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174)) 570 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144)) 571 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148)) 572 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) 573 574 /* Every driver should use these Device State */ 575 #define QLA82XX_DEV_COLD 1 576 #define QLA82XX_DEV_INITIALIZING 2 577 #define QLA82XX_DEV_READY 3 578 #define QLA82XX_DEV_NEED_RESET 4 579 #define QLA82XX_DEV_NEED_QUIESCENT 5 580 #define QLA82XX_DEV_FAILED 6 581 #define QLA82XX_DEV_QUIESCENT 7 582 #define MAX_STATES 8 /* Increment if new state added */ 583 584 #define QLA82XX_IDC_VERSION 0x1 585 #define ROM_DEV_INIT_TIMEOUT 30 586 #define ROM_DRV_RESET_ACK_TIMEOUT 10 587 588 #define PCIE_SETUP_FUNCTION (0x12040) 589 #define PCIE_SETUP_FUNCTION2 (0x12048) 590 591 #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg)) 592 #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg)) 593 594 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ 595 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ 596 #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */ 597 #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */ 598 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ 599 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/ 600 601 /* 602 * The PCI VendorID and DeviceID for our board. 603 */ 604 #define QLA82XX_MSIX_TBL_SPACE 8192 605 #define QLA82XX_PCI_REG_MSIX_TBL 0x44 606 #define QLA82XX_PCI_MSIX_CONTROL 0x40 607 608 struct crb_128M_2M_sub_block_map { 609 unsigned valid; 610 unsigned start_128M; 611 unsigned end_128M; 612 unsigned start_2M; 613 }; 614 615 struct crb_128M_2M_block_map { 616 struct crb_128M_2M_sub_block_map sub_block[16]; 617 }; 618 619 struct crb_addr_pair { 620 long addr; 621 long data; 622 }; 623 624 #define ADDR_ERROR ((unsigned long) 0xffffffff) 625 #define MAX_CTL_CHECK 1000 626 #define QLA82XX_FWERROR_CODE(code) ((code >> 8) & 0x1fffff) 627 628 /*************************************************************************** 629 * PCI related defines. 630 **************************************************************************/ 631 632 /* 633 * Interrupt related defines. 634 */ 635 #define PCIX_TARGET_STATUS (0x10118) 636 #define PCIX_TARGET_STATUS_F1 (0x10160) 637 #define PCIX_TARGET_STATUS_F2 (0x10164) 638 #define PCIX_TARGET_STATUS_F3 (0x10168) 639 #define PCIX_TARGET_STATUS_F4 (0x10360) 640 #define PCIX_TARGET_STATUS_F5 (0x10364) 641 #define PCIX_TARGET_STATUS_F6 (0x10368) 642 #define PCIX_TARGET_STATUS_F7 (0x1036c) 643 644 #define PCIX_TARGET_MASK (0x10128) 645 #define PCIX_TARGET_MASK_F1 (0x10170) 646 #define PCIX_TARGET_MASK_F2 (0x10174) 647 #define PCIX_TARGET_MASK_F3 (0x10178) 648 #define PCIX_TARGET_MASK_F4 (0x10370) 649 #define PCIX_TARGET_MASK_F5 (0x10374) 650 #define PCIX_TARGET_MASK_F6 (0x10378) 651 #define PCIX_TARGET_MASK_F7 (0x1037c) 652 653 /* 654 * Message Signaled Interrupts 655 */ 656 #define PCIX_MSI_F0 (0x13000) 657 #define PCIX_MSI_F1 (0x13004) 658 #define PCIX_MSI_F2 (0x13008) 659 #define PCIX_MSI_F3 (0x1300c) 660 #define PCIX_MSI_F4 (0x13010) 661 #define PCIX_MSI_F5 (0x13014) 662 #define PCIX_MSI_F6 (0x13018) 663 #define PCIX_MSI_F7 (0x1301c) 664 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4)) 665 666 /* 667 * 668 */ 669 #define PCIX_INT_VECTOR (0x10100) 670 #define PCIX_INT_MASK (0x10104) 671 672 /* 673 * Interrupt state machine and other bits. 674 */ 675 #define PCIE_MISCCFG_RC (0x1206c) 676 677 678 #define ISR_INT_TARGET_STATUS \ 679 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS)) 680 #define ISR_INT_TARGET_STATUS_F1 \ 681 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) 682 #define ISR_INT_TARGET_STATUS_F2 \ 683 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) 684 #define ISR_INT_TARGET_STATUS_F3 \ 685 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) 686 #define ISR_INT_TARGET_STATUS_F4 \ 687 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) 688 #define ISR_INT_TARGET_STATUS_F5 \ 689 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) 690 #define ISR_INT_TARGET_STATUS_F6 \ 691 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) 692 #define ISR_INT_TARGET_STATUS_F7 \ 693 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) 694 695 #define ISR_INT_TARGET_MASK \ 696 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK)) 697 #define ISR_INT_TARGET_MASK_F1 \ 698 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) 699 #define ISR_INT_TARGET_MASK_F2 \ 700 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) 701 #define ISR_INT_TARGET_MASK_F3 \ 702 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) 703 #define ISR_INT_TARGET_MASK_F4 \ 704 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) 705 #define ISR_INT_TARGET_MASK_F5 \ 706 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) 707 #define ISR_INT_TARGET_MASK_F6 \ 708 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) 709 #define ISR_INT_TARGET_MASK_F7 \ 710 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) 711 712 #define ISR_INT_VECTOR (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR)) 713 #define ISR_INT_MASK (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK)) 714 #define ISR_INT_STATE_REG (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC)) 715 716 #define ISR_MSI_INT_TRIGGER(FUNC) (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC))) 717 718 719 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) 720 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) 721 722 /* 723 * PCI Interrupt Vector Values. 724 */ 725 #define PCIX_INT_VECTOR_BIT_F0 0x0080 726 #define PCIX_INT_VECTOR_BIT_F1 0x0100 727 #define PCIX_INT_VECTOR_BIT_F2 0x0200 728 #define PCIX_INT_VECTOR_BIT_F3 0x0400 729 #define PCIX_INT_VECTOR_BIT_F4 0x0800 730 #define PCIX_INT_VECTOR_BIT_F5 0x1000 731 #define PCIX_INT_VECTOR_BIT_F6 0x2000 732 #define PCIX_INT_VECTOR_BIT_F7 0x4000 733 734 /* struct qla4_8xxx_legacy_intr_set defined in ql4_def.h */ 735 736 #define QLA82XX_LEGACY_INTR_CONFIG \ 737 { \ 738 { \ 739 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \ 740 .tgt_status_reg = ISR_INT_TARGET_STATUS, \ 741 .tgt_mask_reg = ISR_INT_TARGET_MASK, \ 742 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \ 743 \ 744 { \ 745 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \ 746 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \ 747 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \ 748 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \ 749 \ 750 { \ 751 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \ 752 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \ 753 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \ 754 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \ 755 \ 756 { \ 757 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \ 758 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \ 759 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \ 760 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \ 761 \ 762 { \ 763 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \ 764 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \ 765 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \ 766 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \ 767 \ 768 { \ 769 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \ 770 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \ 771 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \ 772 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \ 773 \ 774 { \ 775 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \ 776 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \ 777 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \ 778 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \ 779 \ 780 { \ 781 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \ 782 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \ 783 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \ 784 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \ 785 } 786 787 /* Magic number to let user know flash is programmed */ 788 #define QLA82XX_BDINFO_MAGIC 0x12345678 789 #define FW_SIZE_OFFSET (0x3e840c) 790 791 /* QLA82XX additions */ 792 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0) 793 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4) 794 795 /* Minidump related */ 796 797 /* Entry Type Defines */ 798 #define QLA82XX_RDNOP 0 799 #define QLA82XX_RDCRB 1 800 #define QLA82XX_RDMUX 2 801 #define QLA82XX_QUEUE 3 802 #define QLA82XX_BOARD 4 803 #define QLA82XX_RDOCM 6 804 #define QLA82XX_PREGS 7 805 #define QLA82XX_L1DTG 8 806 #define QLA82XX_L1ITG 9 807 #define QLA82XX_L1DAT 11 808 #define QLA82XX_L1INS 12 809 #define QLA82XX_L2DTG 21 810 #define QLA82XX_L2ITG 22 811 #define QLA82XX_L2DAT 23 812 #define QLA82XX_L2INS 24 813 #define QLA82XX_RDROM 71 814 #define QLA82XX_RDMEM 72 815 #define QLA82XX_CNTRL 98 816 #define QLA82XX_RDEND 255 817 818 /* Opcodes for Control Entries. 819 * These Flags are bit fields. 820 */ 821 #define QLA82XX_DBG_OPCODE_WR 0x01 822 #define QLA82XX_DBG_OPCODE_RW 0x02 823 #define QLA82XX_DBG_OPCODE_AND 0x04 824 #define QLA82XX_DBG_OPCODE_OR 0x08 825 #define QLA82XX_DBG_OPCODE_POLL 0x10 826 #define QLA82XX_DBG_OPCODE_RDSTATE 0x20 827 #define QLA82XX_DBG_OPCODE_WRSTATE 0x40 828 #define QLA82XX_DBG_OPCODE_MDSTATE 0x80 829 830 /* Driver Flags */ 831 #define QLA82XX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */ 832 #define QLA82XX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size 833 * mismatch */ 834 835 /* Driver_code is for driver to write some info about the entry 836 * currently not used. 837 */ 838 struct qla82xx_minidump_entry_hdr { 839 uint32_t entry_type; 840 uint32_t entry_size; 841 uint32_t entry_capture_size; 842 struct { 843 uint8_t entry_capture_mask; 844 uint8_t entry_code; 845 uint8_t driver_code; 846 uint8_t driver_flags; 847 } d_ctrl; 848 }; 849 850 /* Read CRB entry header */ 851 struct qla82xx_minidump_entry_crb { 852 struct qla82xx_minidump_entry_hdr h; 853 uint32_t addr; 854 struct { 855 uint8_t addr_stride; 856 uint8_t state_index_a; 857 uint16_t poll_timeout; 858 } crb_strd; 859 uint32_t data_size; 860 uint32_t op_count; 861 862 struct { 863 uint8_t opcode; 864 uint8_t state_index_v; 865 uint8_t shl; 866 uint8_t shr; 867 } crb_ctrl; 868 869 uint32_t value_1; 870 uint32_t value_2; 871 uint32_t value_3; 872 }; 873 874 struct qla82xx_minidump_entry_cache { 875 struct qla82xx_minidump_entry_hdr h; 876 uint32_t tag_reg_addr; 877 struct { 878 uint16_t tag_value_stride; 879 uint16_t init_tag_value; 880 } addr_ctrl; 881 uint32_t data_size; 882 uint32_t op_count; 883 uint32_t control_addr; 884 struct { 885 uint16_t write_value; 886 uint8_t poll_mask; 887 uint8_t poll_wait; 888 } cache_ctrl; 889 uint32_t read_addr; 890 struct { 891 uint8_t read_addr_stride; 892 uint8_t read_addr_cnt; 893 uint16_t rsvd_1; 894 } read_ctrl; 895 }; 896 897 /* Read OCM */ 898 struct qla82xx_minidump_entry_rdocm { 899 struct qla82xx_minidump_entry_hdr h; 900 uint32_t rsvd_0; 901 uint32_t rsvd_1; 902 uint32_t data_size; 903 uint32_t op_count; 904 uint32_t rsvd_2; 905 uint32_t rsvd_3; 906 uint32_t read_addr; 907 uint32_t read_addr_stride; 908 }; 909 910 /* Read Memory */ 911 struct qla82xx_minidump_entry_rdmem { 912 struct qla82xx_minidump_entry_hdr h; 913 uint32_t rsvd[6]; 914 uint32_t read_addr; 915 uint32_t read_data_size; 916 }; 917 918 /* Read ROM */ 919 struct qla82xx_minidump_entry_rdrom { 920 struct qla82xx_minidump_entry_hdr h; 921 uint32_t rsvd[6]; 922 uint32_t read_addr; 923 uint32_t read_data_size; 924 }; 925 926 /* Mux entry */ 927 struct qla82xx_minidump_entry_mux { 928 struct qla82xx_minidump_entry_hdr h; 929 uint32_t select_addr; 930 uint32_t rsvd_0; 931 uint32_t data_size; 932 uint32_t op_count; 933 uint32_t select_value; 934 uint32_t select_value_stride; 935 uint32_t read_addr; 936 uint32_t rsvd_1; 937 }; 938 939 /* Queue entry */ 940 struct qla82xx_minidump_entry_queue { 941 struct qla82xx_minidump_entry_hdr h; 942 uint32_t select_addr; 943 struct { 944 uint16_t queue_id_stride; 945 uint16_t rsvd_0; 946 } q_strd; 947 uint32_t data_size; 948 uint32_t op_count; 949 uint32_t rsvd_1; 950 uint32_t rsvd_2; 951 uint32_t read_addr; 952 struct { 953 uint8_t read_addr_stride; 954 uint8_t read_addr_cnt; 955 uint16_t rsvd_3; 956 } rd_strd; 957 }; 958 959 #define QLA82XX_MINIDUMP_OCM0_SIZE (256 * 1024) 960 #define QLA82XX_MINIDUMP_L1C_SIZE (256 * 1024) 961 #define QLA82XX_MINIDUMP_L2C_SIZE 1572864 962 #define QLA82XX_MINIDUMP_COMMON_STR_SIZE 0 963 #define QLA82XX_MINIDUMP_FCOE_STR_SIZE 0 964 #define QLA82XX_MINIDUMP_MEM_SIZE 0 965 #define QLA82XX_MAX_ENTRY_HDR 4 966 967 struct qla82xx_minidump { 968 uint32_t md_ocm0_data[QLA82XX_MINIDUMP_OCM0_SIZE]; 969 uint32_t md_l1c_data[QLA82XX_MINIDUMP_L1C_SIZE]; 970 uint32_t md_l2c_data[QLA82XX_MINIDUMP_L2C_SIZE]; 971 uint32_t md_cs_data[QLA82XX_MINIDUMP_COMMON_STR_SIZE]; 972 uint32_t md_fcoes_data[QLA82XX_MINIDUMP_FCOE_STR_SIZE]; 973 uint32_t md_mem_data[QLA82XX_MINIDUMP_MEM_SIZE]; 974 }; 975 976 #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129 977 #define RQST_TMPLT_SIZE 0x0 978 #define RQST_TMPLT 0x1 979 #define MD_DIRECT_ROM_WINDOW 0x42110030 980 #define MD_DIRECT_ROM_READ_BASE 0x42150000 981 #define MD_MIU_TEST_AGT_CTRL 0x41000090 982 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 983 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 984 985 static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8, 986 0x410000AC, 0x410000B8, 0x410000BC }; 987 #endif 988