1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 #include <linux/delay.h> 8 #include <linux/io.h> 9 #include <linux/pci.h> 10 #include <linux/ratelimit.h> 11 #include "ql4_def.h" 12 #include "ql4_glbl.h" 13 14 #include <asm-generic/io-64-nonatomic-lo-hi.h> 15 16 #define MASK(n) DMA_BIT_MASK(n) 17 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 18 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 19 #define MS_WIN(addr) (addr & 0x0ffc0000) 20 #define QLA82XX_PCI_MN_2M (0) 21 #define QLA82XX_PCI_MS_2M (0x80000) 22 #define QLA82XX_PCI_OCM0_2M (0xc0000) 23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25 26 /* CRB window related */ 27 #define CRB_BLK(off) ((off >> 20) & 0x3f) 28 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 29 #define CRB_WINDOW_2M (0x130060) 30 #define CRB_HI(off) ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 31 ((off) & 0xf0000)) 32 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 33 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 34 #define CRB_INDIRECT_2M (0x1e0000UL) 35 36 static inline void __iomem * 37 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) 38 { 39 if ((off < ha->first_page_group_end) && 40 (off >= ha->first_page_group_start)) 41 return (void __iomem *)(ha->nx_pcibase + off); 42 43 return NULL; 44 } 45 46 #define MAX_CRB_XFORM 60 47 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 48 static int qla4_8xxx_crb_table_initialized; 49 50 #define qla4_8xxx_crb_addr_transform(name) \ 51 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 52 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 53 static void 54 qla4_8xxx_crb_addr_transform_setup(void) 55 { 56 qla4_8xxx_crb_addr_transform(XDMA); 57 qla4_8xxx_crb_addr_transform(TIMR); 58 qla4_8xxx_crb_addr_transform(SRE); 59 qla4_8xxx_crb_addr_transform(SQN3); 60 qla4_8xxx_crb_addr_transform(SQN2); 61 qla4_8xxx_crb_addr_transform(SQN1); 62 qla4_8xxx_crb_addr_transform(SQN0); 63 qla4_8xxx_crb_addr_transform(SQS3); 64 qla4_8xxx_crb_addr_transform(SQS2); 65 qla4_8xxx_crb_addr_transform(SQS1); 66 qla4_8xxx_crb_addr_transform(SQS0); 67 qla4_8xxx_crb_addr_transform(RPMX7); 68 qla4_8xxx_crb_addr_transform(RPMX6); 69 qla4_8xxx_crb_addr_transform(RPMX5); 70 qla4_8xxx_crb_addr_transform(RPMX4); 71 qla4_8xxx_crb_addr_transform(RPMX3); 72 qla4_8xxx_crb_addr_transform(RPMX2); 73 qla4_8xxx_crb_addr_transform(RPMX1); 74 qla4_8xxx_crb_addr_transform(RPMX0); 75 qla4_8xxx_crb_addr_transform(ROMUSB); 76 qla4_8xxx_crb_addr_transform(SN); 77 qla4_8xxx_crb_addr_transform(QMN); 78 qla4_8xxx_crb_addr_transform(QMS); 79 qla4_8xxx_crb_addr_transform(PGNI); 80 qla4_8xxx_crb_addr_transform(PGND); 81 qla4_8xxx_crb_addr_transform(PGN3); 82 qla4_8xxx_crb_addr_transform(PGN2); 83 qla4_8xxx_crb_addr_transform(PGN1); 84 qla4_8xxx_crb_addr_transform(PGN0); 85 qla4_8xxx_crb_addr_transform(PGSI); 86 qla4_8xxx_crb_addr_transform(PGSD); 87 qla4_8xxx_crb_addr_transform(PGS3); 88 qla4_8xxx_crb_addr_transform(PGS2); 89 qla4_8xxx_crb_addr_transform(PGS1); 90 qla4_8xxx_crb_addr_transform(PGS0); 91 qla4_8xxx_crb_addr_transform(PS); 92 qla4_8xxx_crb_addr_transform(PH); 93 qla4_8xxx_crb_addr_transform(NIU); 94 qla4_8xxx_crb_addr_transform(I2Q); 95 qla4_8xxx_crb_addr_transform(EG); 96 qla4_8xxx_crb_addr_transform(MN); 97 qla4_8xxx_crb_addr_transform(MS); 98 qla4_8xxx_crb_addr_transform(CAS2); 99 qla4_8xxx_crb_addr_transform(CAS1); 100 qla4_8xxx_crb_addr_transform(CAS0); 101 qla4_8xxx_crb_addr_transform(CAM); 102 qla4_8xxx_crb_addr_transform(C2C1); 103 qla4_8xxx_crb_addr_transform(C2C0); 104 qla4_8xxx_crb_addr_transform(SMB); 105 qla4_8xxx_crb_addr_transform(OCM0); 106 qla4_8xxx_crb_addr_transform(I2C0); 107 108 qla4_8xxx_crb_table_initialized = 1; 109 } 110 111 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 112 {{{0, 0, 0, 0} } }, /* 0: PCI */ 113 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 114 {1, 0x0110000, 0x0120000, 0x130000}, 115 {1, 0x0120000, 0x0122000, 0x124000}, 116 {1, 0x0130000, 0x0132000, 0x126000}, 117 {1, 0x0140000, 0x0142000, 0x128000}, 118 {1, 0x0150000, 0x0152000, 0x12a000}, 119 {1, 0x0160000, 0x0170000, 0x110000}, 120 {1, 0x0170000, 0x0172000, 0x12e000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {0, 0x0000000, 0x0000000, 0x000000}, 124 {0, 0x0000000, 0x0000000, 0x000000}, 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {0, 0x0000000, 0x0000000, 0x000000}, 127 {1, 0x01e0000, 0x01e0800, 0x122000}, 128 {0, 0x0000000, 0x0000000, 0x000000} } }, 129 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 130 {{{0, 0, 0, 0} } }, /* 3: */ 131 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 132 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 133 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 134 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 135 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 151 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 167 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000}, 177 {0, 0x0000000, 0x0000000, 0x000000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 183 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {0, 0x0000000, 0x0000000, 0x000000}, 193 {0, 0x0000000, 0x0000000, 0x000000}, 194 {0, 0x0000000, 0x0000000, 0x000000}, 195 {0, 0x0000000, 0x0000000, 0x000000}, 196 {0, 0x0000000, 0x0000000, 0x000000}, 197 {0, 0x0000000, 0x0000000, 0x000000}, 198 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 199 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 200 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 201 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 202 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 203 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 204 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 205 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 206 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 207 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 208 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 209 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 210 {{{0, 0, 0, 0} } }, /* 23: */ 211 {{{0, 0, 0, 0} } }, /* 24: */ 212 {{{0, 0, 0, 0} } }, /* 25: */ 213 {{{0, 0, 0, 0} } }, /* 26: */ 214 {{{0, 0, 0, 0} } }, /* 27: */ 215 {{{0, 0, 0, 0} } }, /* 28: */ 216 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 217 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 218 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 219 {{{0} } }, /* 32: PCI */ 220 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 221 {1, 0x2110000, 0x2120000, 0x130000}, 222 {1, 0x2120000, 0x2122000, 0x124000}, 223 {1, 0x2130000, 0x2132000, 0x126000}, 224 {1, 0x2140000, 0x2142000, 0x128000}, 225 {1, 0x2150000, 0x2152000, 0x12a000}, 226 {1, 0x2160000, 0x2170000, 0x110000}, 227 {1, 0x2170000, 0x2172000, 0x12e000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000}, 230 {0, 0x0000000, 0x0000000, 0x000000}, 231 {0, 0x0000000, 0x0000000, 0x000000}, 232 {0, 0x0000000, 0x0000000, 0x000000}, 233 {0, 0x0000000, 0x0000000, 0x000000}, 234 {0, 0x0000000, 0x0000000, 0x000000}, 235 {0, 0x0000000, 0x0000000, 0x000000} } }, 236 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 237 {{{0} } }, /* 35: */ 238 {{{0} } }, /* 36: */ 239 {{{0} } }, /* 37: */ 240 {{{0} } }, /* 38: */ 241 {{{0} } }, /* 39: */ 242 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 243 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 244 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 245 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 246 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 247 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 248 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 249 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 250 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 251 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 252 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 253 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 254 {{{0} } }, /* 52: */ 255 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 256 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 257 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 258 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 259 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 260 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 261 {{{0} } }, /* 59: I2C0 */ 262 {{{0} } }, /* 60: I2C1 */ 263 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ 264 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 265 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 266 }; 267 268 /* 269 * top 12 bits of crb internal address (hub, agent) 270 */ 271 static unsigned qla4_8xxx_crb_hub_agt[64] = { 272 0, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 276 0, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 298 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 299 0, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 301 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 302 0, 303 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 304 0, 305 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 306 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 307 0, 308 0, 309 0, 310 0, 311 0, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 313 0, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 323 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 324 0, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 327 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 329 0, 330 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 332 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 333 0, 334 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 335 0, 336 }; 337 338 /* Device states */ 339 static char *qdev_state[] = { 340 "Unknown", 341 "Cold", 342 "Initializing", 343 "Ready", 344 "Need Reset", 345 "Need Quiescent", 346 "Failed", 347 "Quiescent", 348 }; 349 350 /* 351 * In: 'off' is offset from CRB space in 128M pci map 352 * Out: 'off' is 2M pci map addr 353 * side effect: lock crb window 354 */ 355 static void 356 qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) 357 { 358 u32 win_read; 359 360 ha->crb_win = CRB_HI(*off); 361 writel(ha->crb_win, 362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363 364 /* Read back value to make sure write has gone through before trying 365 * to use it. */ 366 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 367 if (win_read != ha->crb_win) { 368 DEBUG2(ql4_printk(KERN_INFO, ha, 369 "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," 370 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 371 } 372 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 373 } 374 375 void 376 qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) 377 { 378 unsigned long flags = 0; 379 int rv; 380 381 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off); 382 383 BUG_ON(rv == -1); 384 385 if (rv == 1) { 386 write_lock_irqsave(&ha->hw_lock, flags); 387 qla4_8xxx_crb_win_lock(ha); 388 qla4_8xxx_pci_set_crbwindow_2M(ha, &off); 389 } 390 391 writel(data, (void __iomem *)off); 392 393 if (rv == 1) { 394 qla4_8xxx_crb_win_unlock(ha); 395 write_unlock_irqrestore(&ha->hw_lock, flags); 396 } 397 } 398 399 int 400 qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off) 401 { 402 unsigned long flags = 0; 403 int rv; 404 u32 data; 405 406 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off); 407 408 BUG_ON(rv == -1); 409 410 if (rv == 1) { 411 write_lock_irqsave(&ha->hw_lock, flags); 412 qla4_8xxx_crb_win_lock(ha); 413 qla4_8xxx_pci_set_crbwindow_2M(ha, &off); 414 } 415 data = readl((void __iomem *)off); 416 417 if (rv == 1) { 418 qla4_8xxx_crb_win_unlock(ha); 419 write_unlock_irqrestore(&ha->hw_lock, flags); 420 } 421 return data; 422 } 423 424 /* Minidump related functions */ 425 static int qla4_8xxx_md_rw_32(struct scsi_qla_host *ha, uint32_t off, 426 u32 data, uint8_t flag) 427 { 428 uint32_t win_read, off_value, rval = QLA_SUCCESS; 429 430 off_value = off & 0xFFFF0000; 431 writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 432 433 /* Read back value to make sure write has gone through before trying 434 * to use it. 435 */ 436 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 437 if (win_read != off_value) { 438 DEBUG2(ql4_printk(KERN_INFO, ha, 439 "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 440 __func__, off_value, win_read, off)); 441 return QLA_ERROR; 442 } 443 444 off_value = off & 0x0000FFFF; 445 446 if (flag) 447 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M + 448 ha->nx_pcibase)); 449 else 450 rval = readl((void __iomem *)(off_value + CRB_INDIRECT_2M + 451 ha->nx_pcibase)); 452 453 return rval; 454 } 455 456 #define CRB_WIN_LOCK_TIMEOUT 100000000 457 458 int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha) 459 { 460 int i; 461 int done = 0, timeout = 0; 462 463 while (!done) { 464 /* acquire semaphore3 from PCI HW block */ 465 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 466 if (done == 1) 467 break; 468 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 469 return -1; 470 471 timeout++; 472 473 /* Yield CPU */ 474 if (!in_interrupt()) 475 schedule(); 476 else { 477 for (i = 0; i < 20; i++) 478 cpu_relax(); /*This a nop instr on i386*/ 479 } 480 } 481 qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); 482 return 0; 483 } 484 485 void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha) 486 { 487 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 488 } 489 490 #define IDC_LOCK_TIMEOUT 100000000 491 492 /** 493 * qla4_8xxx_idc_lock - hw_lock 494 * @ha: pointer to adapter structure 495 * 496 * General purpose lock used to synchronize access to 497 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. 498 **/ 499 int qla4_8xxx_idc_lock(struct scsi_qla_host *ha) 500 { 501 int i; 502 int done = 0, timeout = 0; 503 504 while (!done) { 505 /* acquire semaphore5 from PCI HW block */ 506 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 507 if (done == 1) 508 break; 509 if (timeout >= IDC_LOCK_TIMEOUT) 510 return -1; 511 512 timeout++; 513 514 /* Yield CPU */ 515 if (!in_interrupt()) 516 schedule(); 517 else { 518 for (i = 0; i < 20; i++) 519 cpu_relax(); /*This a nop instr on i386*/ 520 } 521 } 522 return 0; 523 } 524 525 void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha) 526 { 527 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 528 } 529 530 int 531 qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) 532 { 533 struct crb_128M_2M_sub_block_map *m; 534 535 if (*off >= QLA82XX_CRB_MAX) 536 return -1; 537 538 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 539 *off = (*off - QLA82XX_PCI_CAMQM) + 540 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 541 return 0; 542 } 543 544 if (*off < QLA82XX_PCI_CRBSPACE) 545 return -1; 546 547 *off -= QLA82XX_PCI_CRBSPACE; 548 /* 549 * Try direct map 550 */ 551 552 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 553 554 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 555 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 556 return 0; 557 } 558 559 /* 560 * Not in direct map, use crb window 561 */ 562 return 1; 563 } 564 565 /* PCI Windowing for DDR regions. */ 566 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 567 (((addr) <= (high)) && ((addr) >= (low))) 568 569 /* 570 * check memory access boundary. 571 * used by test agent. support ddr access only for now 572 */ 573 static unsigned long 574 qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha, 575 unsigned long long addr, int size) 576 { 577 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 578 QLA82XX_ADDR_DDR_NET_MAX) || 579 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, 580 QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) || 581 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { 582 return 0; 583 } 584 return 1; 585 } 586 587 static int qla4_8xxx_pci_set_window_warning_count; 588 589 static unsigned long 590 qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) 591 { 592 int window; 593 u32 win_read; 594 595 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 596 QLA82XX_ADDR_DDR_NET_MAX)) { 597 /* DDR network side */ 598 window = MN_WIN(addr); 599 ha->ddr_mn_window = window; 600 qla4_8xxx_wr_32(ha, ha->mn_win_crb | 601 QLA82XX_PCI_CRBSPACE, window); 602 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb | 603 QLA82XX_PCI_CRBSPACE); 604 if ((win_read << 17) != window) { 605 ql4_printk(KERN_WARNING, ha, 606 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 607 __func__, window, win_read); 608 } 609 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 610 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 611 QLA82XX_ADDR_OCM0_MAX)) { 612 unsigned int temp1; 613 /* if bits 19:18&17:11 are on */ 614 if ((addr & 0x00ff800) == 0xff800) { 615 printk("%s: QM access not handled.\n", __func__); 616 addr = -1UL; 617 } 618 619 window = OCM_WIN(addr); 620 ha->ddr_mn_window = window; 621 qla4_8xxx_wr_32(ha, ha->mn_win_crb | 622 QLA82XX_PCI_CRBSPACE, window); 623 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb | 624 QLA82XX_PCI_CRBSPACE); 625 temp1 = ((window & 0x1FF) << 7) | 626 ((window & 0x0FFFE0000) >> 17); 627 if (win_read != temp1) { 628 printk("%s: Written OCMwin (0x%x) != Read" 629 " OCMwin (0x%x)\n", __func__, temp1, win_read); 630 } 631 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 632 633 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 634 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 635 /* QDR network side */ 636 window = MS_WIN(addr); 637 ha->qdr_sn_window = window; 638 qla4_8xxx_wr_32(ha, ha->ms_win_crb | 639 QLA82XX_PCI_CRBSPACE, window); 640 win_read = qla4_8xxx_rd_32(ha, 641 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 642 if (win_read != window) { 643 printk("%s: Written MSwin (0x%x) != Read " 644 "MSwin (0x%x)\n", __func__, window, win_read); 645 } 646 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 647 648 } else { 649 /* 650 * peg gdb frequently accesses memory that doesn't exist, 651 * this limits the chit chat so debugging isn't slowed down. 652 */ 653 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) || 654 (qla4_8xxx_pci_set_window_warning_count%64 == 0)) { 655 printk("%s: Warning:%s Unknown address range!\n", 656 __func__, DRIVER_NAME); 657 } 658 addr = -1UL; 659 } 660 return addr; 661 } 662 663 /* check if address is in the same windows as the previous access */ 664 static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha, 665 unsigned long long addr) 666 { 667 int window; 668 unsigned long long qdr_max; 669 670 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 671 672 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 673 QLA82XX_ADDR_DDR_NET_MAX)) { 674 /* DDR network side */ 675 BUG(); /* MN access can not come here */ 676 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 677 QLA82XX_ADDR_OCM0_MAX)) { 678 return 1; 679 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 680 QLA82XX_ADDR_OCM1_MAX)) { 681 return 1; 682 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 683 qdr_max)) { 684 /* QDR network side */ 685 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 686 if (ha->qdr_sn_window == window) 687 return 1; 688 } 689 690 return 0; 691 } 692 693 static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha, 694 u64 off, void *data, int size) 695 { 696 unsigned long flags; 697 void __iomem *addr; 698 int ret = 0; 699 u64 start; 700 void __iomem *mem_ptr = NULL; 701 unsigned long mem_base; 702 unsigned long mem_page; 703 704 write_lock_irqsave(&ha->hw_lock, flags); 705 706 /* 707 * If attempting to access unknown address or straddle hw windows, 708 * do not access. 709 */ 710 start = qla4_8xxx_pci_set_window(ha, off); 711 if ((start == -1UL) || 712 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) { 713 write_unlock_irqrestore(&ha->hw_lock, flags); 714 printk(KERN_ERR"%s out of bound pci memory access. " 715 "offset is 0x%llx\n", DRIVER_NAME, off); 716 return -1; 717 } 718 719 addr = qla4_8xxx_pci_base_offsetfset(ha, start); 720 if (!addr) { 721 write_unlock_irqrestore(&ha->hw_lock, flags); 722 mem_base = pci_resource_start(ha->pdev, 0); 723 mem_page = start & PAGE_MASK; 724 /* Map two pages whenever user tries to access addresses in two 725 consecutive pages. 726 */ 727 if (mem_page != ((start + size - 1) & PAGE_MASK)) 728 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 729 else 730 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 731 732 if (mem_ptr == NULL) { 733 *(u8 *)data = 0; 734 return -1; 735 } 736 addr = mem_ptr; 737 addr += start & (PAGE_SIZE - 1); 738 write_lock_irqsave(&ha->hw_lock, flags); 739 } 740 741 switch (size) { 742 case 1: 743 *(u8 *)data = readb(addr); 744 break; 745 case 2: 746 *(u16 *)data = readw(addr); 747 break; 748 case 4: 749 *(u32 *)data = readl(addr); 750 break; 751 case 8: 752 *(u64 *)data = readq(addr); 753 break; 754 default: 755 ret = -1; 756 break; 757 } 758 write_unlock_irqrestore(&ha->hw_lock, flags); 759 760 if (mem_ptr) 761 iounmap(mem_ptr); 762 return ret; 763 } 764 765 static int 766 qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, 767 void *data, int size) 768 { 769 unsigned long flags; 770 void __iomem *addr; 771 int ret = 0; 772 u64 start; 773 void __iomem *mem_ptr = NULL; 774 unsigned long mem_base; 775 unsigned long mem_page; 776 777 write_lock_irqsave(&ha->hw_lock, flags); 778 779 /* 780 * If attempting to access unknown address or straddle hw windows, 781 * do not access. 782 */ 783 start = qla4_8xxx_pci_set_window(ha, off); 784 if ((start == -1UL) || 785 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) { 786 write_unlock_irqrestore(&ha->hw_lock, flags); 787 printk(KERN_ERR"%s out of bound pci memory access. " 788 "offset is 0x%llx\n", DRIVER_NAME, off); 789 return -1; 790 } 791 792 addr = qla4_8xxx_pci_base_offsetfset(ha, start); 793 if (!addr) { 794 write_unlock_irqrestore(&ha->hw_lock, flags); 795 mem_base = pci_resource_start(ha->pdev, 0); 796 mem_page = start & PAGE_MASK; 797 /* Map two pages whenever user tries to access addresses in two 798 consecutive pages. 799 */ 800 if (mem_page != ((start + size - 1) & PAGE_MASK)) 801 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 802 else 803 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 804 if (mem_ptr == NULL) 805 return -1; 806 807 addr = mem_ptr; 808 addr += start & (PAGE_SIZE - 1); 809 write_lock_irqsave(&ha->hw_lock, flags); 810 } 811 812 switch (size) { 813 case 1: 814 writeb(*(u8 *)data, addr); 815 break; 816 case 2: 817 writew(*(u16 *)data, addr); 818 break; 819 case 4: 820 writel(*(u32 *)data, addr); 821 break; 822 case 8: 823 writeq(*(u64 *)data, addr); 824 break; 825 default: 826 ret = -1; 827 break; 828 } 829 write_unlock_irqrestore(&ha->hw_lock, flags); 830 if (mem_ptr) 831 iounmap(mem_ptr); 832 return ret; 833 } 834 835 #define MTU_FUDGE_FACTOR 100 836 837 static unsigned long 838 qla4_8xxx_decode_crb_addr(unsigned long addr) 839 { 840 int i; 841 unsigned long base_addr, offset, pci_base; 842 843 if (!qla4_8xxx_crb_table_initialized) 844 qla4_8xxx_crb_addr_transform_setup(); 845 846 pci_base = ADDR_ERROR; 847 base_addr = addr & 0xfff00000; 848 offset = addr & 0x000fffff; 849 850 for (i = 0; i < MAX_CRB_XFORM; i++) { 851 if (crb_addr_xform[i] == base_addr) { 852 pci_base = i << 20; 853 break; 854 } 855 } 856 if (pci_base == ADDR_ERROR) 857 return pci_base; 858 else 859 return pci_base + offset; 860 } 861 862 static long rom_max_timeout = 100; 863 static long qla4_8xxx_rom_lock_timeout = 100; 864 865 static int 866 qla4_8xxx_rom_lock(struct scsi_qla_host *ha) 867 { 868 int i; 869 int done = 0, timeout = 0; 870 871 while (!done) { 872 /* acquire semaphore2 from PCI HW block */ 873 874 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 875 if (done == 1) 876 break; 877 if (timeout >= qla4_8xxx_rom_lock_timeout) 878 return -1; 879 880 timeout++; 881 882 /* Yield CPU */ 883 if (!in_interrupt()) 884 schedule(); 885 else { 886 for (i = 0; i < 20; i++) 887 cpu_relax(); /*This a nop instr on i386*/ 888 } 889 } 890 qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 891 return 0; 892 } 893 894 static void 895 qla4_8xxx_rom_unlock(struct scsi_qla_host *ha) 896 { 897 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 898 } 899 900 static int 901 qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha) 902 { 903 long timeout = 0; 904 long done = 0 ; 905 906 while (done == 0) { 907 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 908 done &= 2; 909 timeout++; 910 if (timeout >= rom_max_timeout) { 911 printk("%s: Timeout reached waiting for rom done", 912 DRIVER_NAME); 913 return -1; 914 } 915 } 916 return 0; 917 } 918 919 static int 920 qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 921 { 922 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 923 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 924 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 925 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 926 if (qla4_8xxx_wait_rom_done(ha)) { 927 printk("%s: Error waiting for rom done\n", DRIVER_NAME); 928 return -1; 929 } 930 /* reset abyte_cnt and dummy_byte_cnt */ 931 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 932 udelay(10); 933 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 934 935 *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 936 return 0; 937 } 938 939 static int 940 qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 941 { 942 int ret, loops = 0; 943 944 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) { 945 udelay(100); 946 loops++; 947 } 948 if (loops >= 50000) { 949 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME); 950 return -1; 951 } 952 ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp); 953 qla4_8xxx_rom_unlock(ha); 954 return ret; 955 } 956 957 /** 958 * This routine does CRB initialize sequence 959 * to put the ISP into operational state 960 **/ 961 static int 962 qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) 963 { 964 int addr, val; 965 int i ; 966 struct crb_addr_pair *buf; 967 unsigned long off; 968 unsigned offset, n; 969 970 struct crb_addr_pair { 971 long addr; 972 long data; 973 }; 974 975 /* Halt all the indiviual PEGs and other blocks of the ISP */ 976 qla4_8xxx_rom_lock(ha); 977 978 /* disable all I2Q */ 979 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 980 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 981 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 982 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 983 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 984 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 985 986 /* disable all niu interrupts */ 987 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 988 /* disable xge rx/tx */ 989 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 990 /* disable xg1 rx/tx */ 991 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 992 /* disable sideband mac */ 993 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 994 /* disable ap0 mac */ 995 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 996 /* disable ap1 mac */ 997 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 998 999 /* halt sre */ 1000 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1001 qla4_8xxx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1002 1003 /* halt epg */ 1004 qla4_8xxx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1005 1006 /* halt timers */ 1007 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1008 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1009 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1010 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1011 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1012 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1013 1014 /* halt pegs */ 1015 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1016 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1017 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1018 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1019 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1020 msleep(5); 1021 1022 /* big hammer */ 1023 if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 1024 /* don't reset CAM block on reset */ 1025 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1026 else 1027 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1028 1029 qla4_8xxx_rom_unlock(ha); 1030 1031 /* Read the signature value from the flash. 1032 * Offset 0: Contain signature (0xcafecafe) 1033 * Offset 4: Offset and number of addr/value pairs 1034 * that present in CRB initialize sequence 1035 */ 1036 if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1037 qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) { 1038 ql4_printk(KERN_WARNING, ha, 1039 "[ERROR] Reading crb_init area: n: %08x\n", n); 1040 return -1; 1041 } 1042 1043 /* Offset in flash = lower 16 bits 1044 * Number of enteries = upper 16 bits 1045 */ 1046 offset = n & 0xffffU; 1047 n = (n >> 16) & 0xffffU; 1048 1049 /* number of addr/value pair should not exceed 1024 enteries */ 1050 if (n >= 1024) { 1051 ql4_printk(KERN_WARNING, ha, 1052 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1053 DRIVER_NAME, __func__, n); 1054 return -1; 1055 } 1056 1057 ql4_printk(KERN_INFO, ha, 1058 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); 1059 1060 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1061 if (buf == NULL) { 1062 ql4_printk(KERN_WARNING, ha, 1063 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); 1064 return -1; 1065 } 1066 1067 for (i = 0; i < n; i++) { 1068 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1069 qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 1070 0) { 1071 kfree(buf); 1072 return -1; 1073 } 1074 1075 buf[i].addr = addr; 1076 buf[i].data = val; 1077 } 1078 1079 for (i = 0; i < n; i++) { 1080 /* Translate internal CRB initialization 1081 * address to PCI bus address 1082 */ 1083 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) + 1084 QLA82XX_PCI_CRBSPACE; 1085 /* Not all CRB addr/value pair to be written, 1086 * some of them are skipped 1087 */ 1088 1089 /* skip if LS bit is set*/ 1090 if (off & 0x1) { 1091 DEBUG2(ql4_printk(KERN_WARNING, ha, 1092 "Skip CRB init replay for offset = 0x%lx\n", off)); 1093 continue; 1094 } 1095 1096 /* skipping cold reboot MAGIC */ 1097 if (off == QLA82XX_CAM_RAM(0x1fc)) 1098 continue; 1099 1100 /* do not reset PCI */ 1101 if (off == (ROMUSB_GLB + 0xbc)) 1102 continue; 1103 1104 /* skip core clock, so that firmware can increase the clock */ 1105 if (off == (ROMUSB_GLB + 0xc8)) 1106 continue; 1107 1108 /* skip the function enable register */ 1109 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1110 continue; 1111 1112 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1113 continue; 1114 1115 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1116 continue; 1117 1118 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1119 continue; 1120 1121 if (off == ADDR_ERROR) { 1122 ql4_printk(KERN_WARNING, ha, 1123 "%s: [ERROR] Unknown addr: 0x%08lx\n", 1124 DRIVER_NAME, buf[i].addr); 1125 continue; 1126 } 1127 1128 qla4_8xxx_wr_32(ha, off, buf[i].data); 1129 1130 /* ISP requires much bigger delay to settle down, 1131 * else crb_window returns 0xffffffff 1132 */ 1133 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1134 msleep(1000); 1135 1136 /* ISP requires millisec delay between 1137 * successive CRB register updation 1138 */ 1139 msleep(1); 1140 } 1141 1142 kfree(buf); 1143 1144 /* Resetting the data and instruction cache */ 1145 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1146 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1147 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1148 1149 /* Clear all protocol processing engines */ 1150 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1151 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1152 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1153 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1154 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1155 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1156 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1157 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1158 1159 return 0; 1160 } 1161 1162 static int 1163 qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) 1164 { 1165 int i, rval = 0; 1166 long size = 0; 1167 long flashaddr, memaddr; 1168 u64 data; 1169 u32 high, low; 1170 1171 flashaddr = memaddr = ha->hw.flt_region_bootload; 1172 size = (image_start - flashaddr) / 8; 1173 1174 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", 1175 ha->host_no, __func__, flashaddr, image_start)); 1176 1177 for (i = 0; i < size; i++) { 1178 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1179 (qla4_8xxx_rom_fast_read(ha, flashaddr + 4, 1180 (int *)&high))) { 1181 rval = -1; 1182 goto exit_load_from_flash; 1183 } 1184 data = ((u64)high << 32) | low ; 1185 rval = qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8); 1186 if (rval) 1187 goto exit_load_from_flash; 1188 1189 flashaddr += 8; 1190 memaddr += 8; 1191 1192 if (i % 0x1000 == 0) 1193 msleep(1); 1194 1195 } 1196 1197 udelay(100); 1198 1199 read_lock(&ha->hw_lock); 1200 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1201 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1202 read_unlock(&ha->hw_lock); 1203 1204 exit_load_from_flash: 1205 return rval; 1206 } 1207 1208 static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) 1209 { 1210 u32 rst; 1211 1212 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1213 if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { 1214 printk(KERN_WARNING "%s: Error during CRB Initialization\n", 1215 __func__); 1216 return QLA_ERROR; 1217 } 1218 1219 udelay(500); 1220 1221 /* at this point, QM is in reset. This could be a problem if there are 1222 * incoming d* transition queue messages. QM/PCIE could wedge. 1223 * To get around this, QM is brought out of reset. 1224 */ 1225 1226 rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 1227 /* unreset qm */ 1228 rst &= ~(1 << 28); 1229 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 1230 1231 if (qla4_8xxx_load_from_flash(ha, image_start)) { 1232 printk("%s: Error trying to load fw from flash!\n", __func__); 1233 return QLA_ERROR; 1234 } 1235 1236 return QLA_SUCCESS; 1237 } 1238 1239 int 1240 qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha, 1241 u64 off, void *data, int size) 1242 { 1243 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1244 int shift_amount; 1245 uint32_t temp; 1246 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1247 1248 /* 1249 * If not MN, go check for MS or invalid. 1250 */ 1251 1252 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1253 mem_crb = QLA82XX_CRB_QDR_NET; 1254 else { 1255 mem_crb = QLA82XX_CRB_DDR_NET; 1256 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0) 1257 return qla4_8xxx_pci_mem_read_direct(ha, 1258 off, data, size); 1259 } 1260 1261 1262 off8 = off & 0xfffffff0; 1263 off0[0] = off & 0xf; 1264 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1265 shift_amount = 4; 1266 1267 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1268 off0[1] = 0; 1269 sz[1] = size - sz[0]; 1270 1271 for (i = 0; i < loop; i++) { 1272 temp = off8 + (i << shift_amount); 1273 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1274 temp = 0; 1275 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1276 temp = MIU_TA_CTL_ENABLE; 1277 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1278 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1279 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1280 1281 for (j = 0; j < MAX_CTL_CHECK; j++) { 1282 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1283 if ((temp & MIU_TA_CTL_BUSY) == 0) 1284 break; 1285 } 1286 1287 if (j >= MAX_CTL_CHECK) { 1288 printk_ratelimited(KERN_ERR 1289 "%s: failed to read through agent\n", 1290 __func__); 1291 break; 1292 } 1293 1294 start = off0[i] >> 2; 1295 end = (off0[i] + sz[i] - 1) >> 2; 1296 for (k = start; k <= end; k++) { 1297 temp = qla4_8xxx_rd_32(ha, 1298 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1299 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1300 } 1301 } 1302 1303 if (j >= MAX_CTL_CHECK) 1304 return -1; 1305 1306 if ((off0[0] & 7) == 0) { 1307 val = word[0]; 1308 } else { 1309 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1310 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1311 } 1312 1313 switch (size) { 1314 case 1: 1315 *(uint8_t *)data = val; 1316 break; 1317 case 2: 1318 *(uint16_t *)data = val; 1319 break; 1320 case 4: 1321 *(uint32_t *)data = val; 1322 break; 1323 case 8: 1324 *(uint64_t *)data = val; 1325 break; 1326 } 1327 return 0; 1328 } 1329 1330 int 1331 qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha, 1332 u64 off, void *data, int size) 1333 { 1334 int i, j, ret = 0, loop, sz[2], off0; 1335 int scale, shift_amount, startword; 1336 uint32_t temp; 1337 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1338 1339 /* 1340 * If not MN, go check for MS or invalid. 1341 */ 1342 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1343 mem_crb = QLA82XX_CRB_QDR_NET; 1344 else { 1345 mem_crb = QLA82XX_CRB_DDR_NET; 1346 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0) 1347 return qla4_8xxx_pci_mem_write_direct(ha, 1348 off, data, size); 1349 } 1350 1351 off0 = off & 0x7; 1352 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1353 sz[1] = size - sz[0]; 1354 1355 off8 = off & 0xfffffff0; 1356 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1357 shift_amount = 4; 1358 scale = 2; 1359 startword = (off & 0xf)/8; 1360 1361 for (i = 0; i < loop; i++) { 1362 if (qla4_8xxx_pci_mem_read_2M(ha, off8 + 1363 (i << shift_amount), &word[i * scale], 8)) 1364 return -1; 1365 } 1366 1367 switch (size) { 1368 case 1: 1369 tmpw = *((uint8_t *)data); 1370 break; 1371 case 2: 1372 tmpw = *((uint16_t *)data); 1373 break; 1374 case 4: 1375 tmpw = *((uint32_t *)data); 1376 break; 1377 case 8: 1378 default: 1379 tmpw = *((uint64_t *)data); 1380 break; 1381 } 1382 1383 if (sz[0] == 8) 1384 word[startword] = tmpw; 1385 else { 1386 word[startword] &= 1387 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1388 word[startword] |= tmpw << (off0 * 8); 1389 } 1390 1391 if (sz[1] != 0) { 1392 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1393 word[startword+1] |= tmpw >> (sz[0] * 8); 1394 } 1395 1396 for (i = 0; i < loop; i++) { 1397 temp = off8 + (i << shift_amount); 1398 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1399 temp = 0; 1400 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1401 temp = word[i * scale] & 0xffffffff; 1402 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1403 temp = (word[i * scale] >> 32) & 0xffffffff; 1404 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1405 temp = word[i*scale + 1] & 0xffffffff; 1406 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, 1407 temp); 1408 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1409 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, 1410 temp); 1411 1412 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1413 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1414 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1415 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1416 1417 for (j = 0; j < MAX_CTL_CHECK; j++) { 1418 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1419 if ((temp & MIU_TA_CTL_BUSY) == 0) 1420 break; 1421 } 1422 1423 if (j >= MAX_CTL_CHECK) { 1424 if (printk_ratelimit()) 1425 ql4_printk(KERN_ERR, ha, 1426 "%s: failed to read through agent\n", 1427 __func__); 1428 ret = -1; 1429 break; 1430 } 1431 } 1432 1433 return ret; 1434 } 1435 1436 static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) 1437 { 1438 u32 val = 0; 1439 int retries = 60; 1440 1441 if (!pegtune_val) { 1442 do { 1443 val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE); 1444 if ((val == PHAN_INITIALIZE_COMPLETE) || 1445 (val == PHAN_INITIALIZE_ACK)) 1446 return 0; 1447 set_current_state(TASK_UNINTERRUPTIBLE); 1448 schedule_timeout(500); 1449 1450 } while (--retries); 1451 1452 if (!retries) { 1453 pegtune_val = qla4_8xxx_rd_32(ha, 1454 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1455 printk(KERN_WARNING "%s: init failed, " 1456 "pegtune_val = %x\n", __func__, pegtune_val); 1457 return -1; 1458 } 1459 } 1460 return 0; 1461 } 1462 1463 static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha) 1464 { 1465 uint32_t state = 0; 1466 int loops = 0; 1467 1468 /* Window 1 call */ 1469 read_lock(&ha->hw_lock); 1470 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE); 1471 read_unlock(&ha->hw_lock); 1472 1473 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { 1474 udelay(100); 1475 /* Window 1 call */ 1476 read_lock(&ha->hw_lock); 1477 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE); 1478 read_unlock(&ha->hw_lock); 1479 1480 loops++; 1481 } 1482 1483 if (loops >= 30000) { 1484 DEBUG2(ql4_printk(KERN_INFO, ha, 1485 "Receive Peg initialization not complete: 0x%x.\n", state)); 1486 return QLA_ERROR; 1487 } 1488 1489 return QLA_SUCCESS; 1490 } 1491 1492 void 1493 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) 1494 { 1495 uint32_t drv_active; 1496 1497 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1498 drv_active |= (1 << (ha->func_num * 4)); 1499 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1500 __func__, ha->host_no, drv_active); 1501 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1502 } 1503 1504 void 1505 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) 1506 { 1507 uint32_t drv_active; 1508 1509 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1510 drv_active &= ~(1 << (ha->func_num * 4)); 1511 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1512 __func__, ha->host_no, drv_active); 1513 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1514 } 1515 1516 static inline int 1517 qla4_8xxx_need_reset(struct scsi_qla_host *ha) 1518 { 1519 uint32_t drv_state, drv_active; 1520 int rval; 1521 1522 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1523 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1524 rval = drv_state & (1 << (ha->func_num * 4)); 1525 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 1526 rval = 1; 1527 1528 return rval; 1529 } 1530 1531 static inline void 1532 qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) 1533 { 1534 uint32_t drv_state; 1535 1536 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1537 drv_state |= (1 << (ha->func_num * 4)); 1538 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1539 __func__, ha->host_no, drv_state); 1540 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1541 } 1542 1543 static inline void 1544 qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) 1545 { 1546 uint32_t drv_state; 1547 1548 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1549 drv_state &= ~(1 << (ha->func_num * 4)); 1550 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1551 __func__, ha->host_no, drv_state); 1552 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1553 } 1554 1555 static inline void 1556 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) 1557 { 1558 uint32_t qsnt_state; 1559 1560 qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1561 qsnt_state |= (2 << (ha->func_num * 4)); 1562 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 1563 } 1564 1565 1566 static int 1567 qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) 1568 { 1569 int pcie_cap; 1570 uint16_t lnk; 1571 1572 /* scrub dma mask expansion register */ 1573 qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 1574 1575 /* Overwrite stale initialization register values */ 1576 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1577 qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0); 1578 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 1579 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 1580 1581 if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) { 1582 printk("%s: Error trying to start fw!\n", __func__); 1583 return QLA_ERROR; 1584 } 1585 1586 /* Handshake with the card before we register the devices. */ 1587 if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { 1588 printk("%s: Error during card handshake!\n", __func__); 1589 return QLA_ERROR; 1590 } 1591 1592 /* Negotiated Link width */ 1593 pcie_cap = pci_pcie_cap(ha->pdev); 1594 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 1595 ha->link_width = (lnk >> 4) & 0x3f; 1596 1597 /* Synchronize with Receive peg */ 1598 return qla4_8xxx_rcvpeg_ready(ha); 1599 } 1600 1601 static int 1602 qla4_8xxx_try_start_fw(struct scsi_qla_host *ha) 1603 { 1604 int rval = QLA_ERROR; 1605 1606 /* 1607 * FW Load priority: 1608 * 1) Operational firmware residing in flash. 1609 * 2) Fail 1610 */ 1611 1612 ql4_printk(KERN_INFO, ha, 1613 "FW: Retrieving flash offsets from FLT/FDT ...\n"); 1614 rval = qla4_8xxx_get_flash_info(ha); 1615 if (rval != QLA_SUCCESS) 1616 return rval; 1617 1618 ql4_printk(KERN_INFO, ha, 1619 "FW: Attempting to load firmware from flash...\n"); 1620 rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw); 1621 1622 if (rval != QLA_SUCCESS) { 1623 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" 1624 " FAILED...\n"); 1625 return rval; 1626 } 1627 1628 return rval; 1629 } 1630 1631 static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha) 1632 { 1633 if (qla4_8xxx_rom_lock(ha)) { 1634 /* Someone else is holding the lock. */ 1635 dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); 1636 } 1637 1638 /* 1639 * Either we got the lock, or someone 1640 * else died while holding it. 1641 * In either case, unlock. 1642 */ 1643 qla4_8xxx_rom_unlock(ha); 1644 } 1645 1646 static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha, 1647 struct qla82xx_minidump_entry_hdr *entry_hdr, 1648 uint32_t **d_ptr) 1649 { 1650 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 1651 struct qla82xx_minidump_entry_crb *crb_hdr; 1652 uint32_t *data_ptr = *d_ptr; 1653 1654 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1655 crb_hdr = (struct qla82xx_minidump_entry_crb *)entry_hdr; 1656 r_addr = crb_hdr->addr; 1657 r_stride = crb_hdr->crb_strd.addr_stride; 1658 loop_cnt = crb_hdr->op_count; 1659 1660 for (i = 0; i < loop_cnt; i++) { 1661 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1662 *data_ptr++ = cpu_to_le32(r_addr); 1663 *data_ptr++ = cpu_to_le32(r_value); 1664 r_addr += r_stride; 1665 } 1666 *d_ptr = data_ptr; 1667 } 1668 1669 static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha, 1670 struct qla82xx_minidump_entry_hdr *entry_hdr, 1671 uint32_t **d_ptr) 1672 { 1673 uint32_t addr, r_addr, c_addr, t_r_addr; 1674 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 1675 unsigned long p_wait, w_time, p_mask; 1676 uint32_t c_value_w, c_value_r; 1677 struct qla82xx_minidump_entry_cache *cache_hdr; 1678 int rval = QLA_ERROR; 1679 uint32_t *data_ptr = *d_ptr; 1680 1681 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1682 cache_hdr = (struct qla82xx_minidump_entry_cache *)entry_hdr; 1683 1684 loop_count = cache_hdr->op_count; 1685 r_addr = cache_hdr->read_addr; 1686 c_addr = cache_hdr->control_addr; 1687 c_value_w = cache_hdr->cache_ctrl.write_value; 1688 1689 t_r_addr = cache_hdr->tag_reg_addr; 1690 t_value = cache_hdr->addr_ctrl.init_tag_value; 1691 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 1692 p_wait = cache_hdr->cache_ctrl.poll_wait; 1693 p_mask = cache_hdr->cache_ctrl.poll_mask; 1694 1695 for (i = 0; i < loop_count; i++) { 1696 qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1); 1697 1698 if (c_value_w) 1699 qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1); 1700 1701 if (p_mask) { 1702 w_time = jiffies + p_wait; 1703 do { 1704 c_value_r = qla4_8xxx_md_rw_32(ha, c_addr, 1705 0, 0); 1706 if ((c_value_r & p_mask) == 0) { 1707 break; 1708 } else if (time_after_eq(jiffies, w_time)) { 1709 /* capturing dump failed */ 1710 return rval; 1711 } 1712 } while (1); 1713 } 1714 1715 addr = r_addr; 1716 for (k = 0; k < r_cnt; k++) { 1717 r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1718 *data_ptr++ = cpu_to_le32(r_value); 1719 addr += cache_hdr->read_ctrl.read_addr_stride; 1720 } 1721 1722 t_value += cache_hdr->addr_ctrl.tag_value_stride; 1723 } 1724 *d_ptr = data_ptr; 1725 return QLA_SUCCESS; 1726 } 1727 1728 static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, 1729 struct qla82xx_minidump_entry_hdr *entry_hdr) 1730 { 1731 struct qla82xx_minidump_entry_crb *crb_entry; 1732 uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS; 1733 uint32_t crb_addr; 1734 unsigned long wtime; 1735 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 1736 int i; 1737 1738 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1739 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 1740 ha->fw_dump_tmplt_hdr; 1741 crb_entry = (struct qla82xx_minidump_entry_crb *)entry_hdr; 1742 1743 crb_addr = crb_entry->addr; 1744 for (i = 0; i < crb_entry->op_count; i++) { 1745 opcode = crb_entry->crb_ctrl.opcode; 1746 if (opcode & QLA82XX_DBG_OPCODE_WR) { 1747 qla4_8xxx_md_rw_32(ha, crb_addr, 1748 crb_entry->value_1, 1); 1749 opcode &= ~QLA82XX_DBG_OPCODE_WR; 1750 } 1751 if (opcode & QLA82XX_DBG_OPCODE_RW) { 1752 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1753 qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1754 opcode &= ~QLA82XX_DBG_OPCODE_RW; 1755 } 1756 if (opcode & QLA82XX_DBG_OPCODE_AND) { 1757 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1758 read_value &= crb_entry->value_2; 1759 opcode &= ~QLA82XX_DBG_OPCODE_AND; 1760 if (opcode & QLA82XX_DBG_OPCODE_OR) { 1761 read_value |= crb_entry->value_3; 1762 opcode &= ~QLA82XX_DBG_OPCODE_OR; 1763 } 1764 qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1765 } 1766 if (opcode & QLA82XX_DBG_OPCODE_OR) { 1767 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1768 read_value |= crb_entry->value_3; 1769 qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1770 opcode &= ~QLA82XX_DBG_OPCODE_OR; 1771 } 1772 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 1773 poll_time = crb_entry->crb_strd.poll_timeout; 1774 wtime = jiffies + poll_time; 1775 read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1776 1777 do { 1778 if ((read_value & crb_entry->value_2) == 1779 crb_entry->value_1) 1780 break; 1781 else if (time_after_eq(jiffies, wtime)) { 1782 /* capturing dump failed */ 1783 rval = QLA_ERROR; 1784 break; 1785 } else 1786 read_value = qla4_8xxx_md_rw_32(ha, 1787 crb_addr, 0, 0); 1788 } while (1); 1789 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 1790 } 1791 1792 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 1793 if (crb_entry->crb_strd.state_index_a) { 1794 index = crb_entry->crb_strd.state_index_a; 1795 addr = tmplt_hdr->saved_state_array[index]; 1796 } else { 1797 addr = crb_addr; 1798 } 1799 1800 read_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1801 index = crb_entry->crb_ctrl.state_index_v; 1802 tmplt_hdr->saved_state_array[index] = read_value; 1803 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 1804 } 1805 1806 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 1807 if (crb_entry->crb_strd.state_index_a) { 1808 index = crb_entry->crb_strd.state_index_a; 1809 addr = tmplt_hdr->saved_state_array[index]; 1810 } else { 1811 addr = crb_addr; 1812 } 1813 1814 if (crb_entry->crb_ctrl.state_index_v) { 1815 index = crb_entry->crb_ctrl.state_index_v; 1816 read_value = 1817 tmplt_hdr->saved_state_array[index]; 1818 } else { 1819 read_value = crb_entry->value_1; 1820 } 1821 1822 qla4_8xxx_md_rw_32(ha, addr, read_value, 1); 1823 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 1824 } 1825 1826 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 1827 index = crb_entry->crb_ctrl.state_index_v; 1828 read_value = tmplt_hdr->saved_state_array[index]; 1829 read_value <<= crb_entry->crb_ctrl.shl; 1830 read_value >>= crb_entry->crb_ctrl.shr; 1831 if (crb_entry->value_2) 1832 read_value &= crb_entry->value_2; 1833 read_value |= crb_entry->value_3; 1834 read_value += crb_entry->value_1; 1835 tmplt_hdr->saved_state_array[index] = read_value; 1836 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 1837 } 1838 crb_addr += crb_entry->crb_strd.addr_stride; 1839 } 1840 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); 1841 return rval; 1842 } 1843 1844 static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha, 1845 struct qla82xx_minidump_entry_hdr *entry_hdr, 1846 uint32_t **d_ptr) 1847 { 1848 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 1849 struct qla82xx_minidump_entry_rdocm *ocm_hdr; 1850 uint32_t *data_ptr = *d_ptr; 1851 1852 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1853 ocm_hdr = (struct qla82xx_minidump_entry_rdocm *)entry_hdr; 1854 r_addr = ocm_hdr->read_addr; 1855 r_stride = ocm_hdr->read_addr_stride; 1856 loop_cnt = ocm_hdr->op_count; 1857 1858 DEBUG2(ql4_printk(KERN_INFO, ha, 1859 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", 1860 __func__, r_addr, r_stride, loop_cnt)); 1861 1862 for (i = 0; i < loop_cnt; i++) { 1863 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); 1864 *data_ptr++ = cpu_to_le32(r_value); 1865 r_addr += r_stride; 1866 } 1867 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n", 1868 __func__, (loop_cnt * sizeof(uint32_t)))); 1869 *d_ptr = data_ptr; 1870 } 1871 1872 static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha, 1873 struct qla82xx_minidump_entry_hdr *entry_hdr, 1874 uint32_t **d_ptr) 1875 { 1876 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 1877 struct qla82xx_minidump_entry_mux *mux_hdr; 1878 uint32_t *data_ptr = *d_ptr; 1879 1880 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1881 mux_hdr = (struct qla82xx_minidump_entry_mux *)entry_hdr; 1882 r_addr = mux_hdr->read_addr; 1883 s_addr = mux_hdr->select_addr; 1884 s_stride = mux_hdr->select_value_stride; 1885 s_value = mux_hdr->select_value; 1886 loop_cnt = mux_hdr->op_count; 1887 1888 for (i = 0; i < loop_cnt; i++) { 1889 qla4_8xxx_md_rw_32(ha, s_addr, s_value, 1); 1890 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1891 *data_ptr++ = cpu_to_le32(s_value); 1892 *data_ptr++ = cpu_to_le32(r_value); 1893 s_value += s_stride; 1894 } 1895 *d_ptr = data_ptr; 1896 } 1897 1898 static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha, 1899 struct qla82xx_minidump_entry_hdr *entry_hdr, 1900 uint32_t **d_ptr) 1901 { 1902 uint32_t addr, r_addr, c_addr, t_r_addr; 1903 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 1904 uint32_t c_value_w; 1905 struct qla82xx_minidump_entry_cache *cache_hdr; 1906 uint32_t *data_ptr = *d_ptr; 1907 1908 cache_hdr = (struct qla82xx_minidump_entry_cache *)entry_hdr; 1909 loop_count = cache_hdr->op_count; 1910 r_addr = cache_hdr->read_addr; 1911 c_addr = cache_hdr->control_addr; 1912 c_value_w = cache_hdr->cache_ctrl.write_value; 1913 1914 t_r_addr = cache_hdr->tag_reg_addr; 1915 t_value = cache_hdr->addr_ctrl.init_tag_value; 1916 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 1917 1918 for (i = 0; i < loop_count; i++) { 1919 qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1); 1920 qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1); 1921 addr = r_addr; 1922 for (k = 0; k < r_cnt; k++) { 1923 r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1924 *data_ptr++ = cpu_to_le32(r_value); 1925 addr += cache_hdr->read_ctrl.read_addr_stride; 1926 } 1927 t_value += cache_hdr->addr_ctrl.tag_value_stride; 1928 } 1929 *d_ptr = data_ptr; 1930 } 1931 1932 static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha, 1933 struct qla82xx_minidump_entry_hdr *entry_hdr, 1934 uint32_t **d_ptr) 1935 { 1936 uint32_t s_addr, r_addr; 1937 uint32_t r_stride, r_value, r_cnt, qid = 0; 1938 uint32_t i, k, loop_cnt; 1939 struct qla82xx_minidump_entry_queue *q_hdr; 1940 uint32_t *data_ptr = *d_ptr; 1941 1942 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1943 q_hdr = (struct qla82xx_minidump_entry_queue *)entry_hdr; 1944 s_addr = q_hdr->select_addr; 1945 r_cnt = q_hdr->rd_strd.read_addr_cnt; 1946 r_stride = q_hdr->rd_strd.read_addr_stride; 1947 loop_cnt = q_hdr->op_count; 1948 1949 for (i = 0; i < loop_cnt; i++) { 1950 qla4_8xxx_md_rw_32(ha, s_addr, qid, 1); 1951 r_addr = q_hdr->read_addr; 1952 for (k = 0; k < r_cnt; k++) { 1953 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1954 *data_ptr++ = cpu_to_le32(r_value); 1955 r_addr += r_stride; 1956 } 1957 qid += q_hdr->q_strd.queue_id_stride; 1958 } 1959 *d_ptr = data_ptr; 1960 } 1961 1962 #define MD_DIRECT_ROM_WINDOW 0x42110030 1963 #define MD_DIRECT_ROM_READ_BASE 0x42150000 1964 1965 static void qla4_8xxx_minidump_process_rdrom(struct scsi_qla_host *ha, 1966 struct qla82xx_minidump_entry_hdr *entry_hdr, 1967 uint32_t **d_ptr) 1968 { 1969 uint32_t r_addr, r_value; 1970 uint32_t i, loop_cnt; 1971 struct qla82xx_minidump_entry_rdrom *rom_hdr; 1972 uint32_t *data_ptr = *d_ptr; 1973 1974 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1975 rom_hdr = (struct qla82xx_minidump_entry_rdrom *)entry_hdr; 1976 r_addr = rom_hdr->read_addr; 1977 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 1978 1979 DEBUG2(ql4_printk(KERN_INFO, ha, 1980 "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n", 1981 __func__, r_addr, loop_cnt)); 1982 1983 for (i = 0; i < loop_cnt; i++) { 1984 qla4_8xxx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 1985 (r_addr & 0xFFFF0000), 1); 1986 r_value = qla4_8xxx_md_rw_32(ha, 1987 MD_DIRECT_ROM_READ_BASE + 1988 (r_addr & 0x0000FFFF), 0, 0); 1989 *data_ptr++ = cpu_to_le32(r_value); 1990 r_addr += sizeof(uint32_t); 1991 } 1992 *d_ptr = data_ptr; 1993 } 1994 1995 #define MD_MIU_TEST_AGT_CTRL 0x41000090 1996 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 1997 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 1998 1999 static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 2000 struct qla82xx_minidump_entry_hdr *entry_hdr, 2001 uint32_t **d_ptr) 2002 { 2003 uint32_t r_addr, r_value, r_data; 2004 uint32_t i, j, loop_cnt; 2005 struct qla82xx_minidump_entry_rdmem *m_hdr; 2006 unsigned long flags; 2007 uint32_t *data_ptr = *d_ptr; 2008 2009 DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2010 m_hdr = (struct qla82xx_minidump_entry_rdmem *)entry_hdr; 2011 r_addr = m_hdr->read_addr; 2012 loop_cnt = m_hdr->read_data_size/16; 2013 2014 DEBUG2(ql4_printk(KERN_INFO, ha, 2015 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", 2016 __func__, r_addr, m_hdr->read_data_size)); 2017 2018 if (r_addr & 0xf) { 2019 DEBUG2(ql4_printk(KERN_INFO, ha, 2020 "[%s]: Read addr 0x%x not 16 bytes alligned\n", 2021 __func__, r_addr)); 2022 return QLA_ERROR; 2023 } 2024 2025 if (m_hdr->read_data_size % 16) { 2026 DEBUG2(ql4_printk(KERN_INFO, ha, 2027 "[%s]: Read data[0x%x] not multiple of 16 bytes\n", 2028 __func__, m_hdr->read_data_size)); 2029 return QLA_ERROR; 2030 } 2031 2032 DEBUG2(ql4_printk(KERN_INFO, ha, 2033 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 2034 __func__, r_addr, m_hdr->read_data_size, loop_cnt)); 2035 2036 write_lock_irqsave(&ha->hw_lock, flags); 2037 for (i = 0; i < loop_cnt; i++) { 2038 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 2039 r_value = 0; 2040 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 2041 r_value = MIU_TA_CTL_ENABLE; 2042 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 2043 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 2044 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 2045 2046 for (j = 0; j < MAX_CTL_CHECK; j++) { 2047 r_value = qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, 2048 0, 0); 2049 if ((r_value & MIU_TA_CTL_BUSY) == 0) 2050 break; 2051 } 2052 2053 if (j >= MAX_CTL_CHECK) { 2054 printk_ratelimited(KERN_ERR 2055 "%s: failed to read through agent\n", 2056 __func__); 2057 write_unlock_irqrestore(&ha->hw_lock, flags); 2058 return QLA_SUCCESS; 2059 } 2060 2061 for (j = 0; j < 4; j++) { 2062 r_data = qla4_8xxx_md_rw_32(ha, 2063 MD_MIU_TEST_AGT_RDDATA[j], 2064 0, 0); 2065 *data_ptr++ = cpu_to_le32(r_data); 2066 } 2067 2068 r_addr += 16; 2069 } 2070 write_unlock_irqrestore(&ha->hw_lock, flags); 2071 2072 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n", 2073 __func__, (loop_cnt * 16))); 2074 2075 *d_ptr = data_ptr; 2076 return QLA_SUCCESS; 2077 } 2078 2079 static void ql4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha, 2080 struct qla82xx_minidump_entry_hdr *entry_hdr, 2081 int index) 2082 { 2083 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 2084 DEBUG2(ql4_printk(KERN_INFO, ha, 2085 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", 2086 ha->host_no, index, entry_hdr->entry_type, 2087 entry_hdr->d_ctrl.entry_capture_mask)); 2088 } 2089 2090 /** 2091 * qla82xx_collect_md_data - Retrieve firmware minidump data. 2092 * @ha: pointer to adapter structure 2093 **/ 2094 static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) 2095 { 2096 int num_entry_hdr = 0; 2097 struct qla82xx_minidump_entry_hdr *entry_hdr; 2098 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 2099 uint32_t *data_ptr; 2100 uint32_t data_collected = 0; 2101 int i, rval = QLA_ERROR; 2102 uint64_t now; 2103 uint32_t timestamp; 2104 2105 if (!ha->fw_dump) { 2106 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n", 2107 __func__, ha->host_no); 2108 return rval; 2109 } 2110 2111 tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 2112 ha->fw_dump_tmplt_hdr; 2113 data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump + 2114 ha->fw_dump_tmplt_size); 2115 data_collected += ha->fw_dump_tmplt_size; 2116 2117 num_entry_hdr = tmplt_hdr->num_of_entries; 2118 ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n", 2119 __func__, data_ptr); 2120 ql4_printk(KERN_INFO, ha, 2121 "[%s]: no of entry headers in Template: 0x%x\n", 2122 __func__, num_entry_hdr); 2123 ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n", 2124 __func__, ha->fw_dump_capture_mask); 2125 ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n", 2126 __func__, ha->fw_dump_size, ha->fw_dump_size); 2127 2128 /* Update current timestamp before taking dump */ 2129 now = get_jiffies_64(); 2130 timestamp = (u32)(jiffies_to_msecs(now) / 1000); 2131 tmplt_hdr->driver_timestamp = timestamp; 2132 2133 entry_hdr = (struct qla82xx_minidump_entry_hdr *) 2134 (((uint8_t *)ha->fw_dump_tmplt_hdr) + 2135 tmplt_hdr->first_entry_offset); 2136 2137 /* Walk through the entry headers - validate/perform required action */ 2138 for (i = 0; i < num_entry_hdr; i++) { 2139 if (data_collected >= ha->fw_dump_size) { 2140 ql4_printk(KERN_INFO, ha, 2141 "Data collected: [0x%x], Total Dump size: [0x%x]\n", 2142 data_collected, ha->fw_dump_size); 2143 return rval; 2144 } 2145 2146 if (!(entry_hdr->d_ctrl.entry_capture_mask & 2147 ha->fw_dump_capture_mask)) { 2148 entry_hdr->d_ctrl.driver_flags |= 2149 QLA82XX_DBG_SKIPPED_FLAG; 2150 goto skip_nxt_entry; 2151 } 2152 2153 DEBUG2(ql4_printk(KERN_INFO, ha, 2154 "Data collected: [0x%x], Dump size left:[0x%x]\n", 2155 data_collected, 2156 (ha->fw_dump_size - data_collected))); 2157 2158 /* Decode the entry type and take required action to capture 2159 * debug data 2160 */ 2161 switch (entry_hdr->entry_type) { 2162 case QLA82XX_RDEND: 2163 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2164 break; 2165 case QLA82XX_CNTRL: 2166 rval = qla4_8xxx_minidump_process_control(ha, 2167 entry_hdr); 2168 if (rval != QLA_SUCCESS) { 2169 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2170 goto md_failed; 2171 } 2172 break; 2173 case QLA82XX_RDCRB: 2174 qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, 2175 &data_ptr); 2176 break; 2177 case QLA82XX_RDMEM: 2178 rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 2179 &data_ptr); 2180 if (rval != QLA_SUCCESS) { 2181 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2182 goto md_failed; 2183 } 2184 break; 2185 case QLA82XX_BOARD: 2186 case QLA82XX_RDROM: 2187 qla4_8xxx_minidump_process_rdrom(ha, entry_hdr, 2188 &data_ptr); 2189 break; 2190 case QLA82XX_L2DTG: 2191 case QLA82XX_L2ITG: 2192 case QLA82XX_L2DAT: 2193 case QLA82XX_L2INS: 2194 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, 2195 &data_ptr); 2196 if (rval != QLA_SUCCESS) { 2197 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2198 goto md_failed; 2199 } 2200 break; 2201 case QLA82XX_L1DAT: 2202 case QLA82XX_L1INS: 2203 qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, 2204 &data_ptr); 2205 break; 2206 case QLA82XX_RDOCM: 2207 qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, 2208 &data_ptr); 2209 break; 2210 case QLA82XX_RDMUX: 2211 qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, 2212 &data_ptr); 2213 break; 2214 case QLA82XX_QUEUE: 2215 qla4_8xxx_minidump_process_queue(ha, entry_hdr, 2216 &data_ptr); 2217 break; 2218 case QLA82XX_RDNOP: 2219 default: 2220 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2221 break; 2222 } 2223 2224 data_collected = (uint8_t *)data_ptr - 2225 ((uint8_t *)((uint8_t *)ha->fw_dump + 2226 ha->fw_dump_tmplt_size)); 2227 skip_nxt_entry: 2228 /* next entry in the template */ 2229 entry_hdr = (struct qla82xx_minidump_entry_hdr *) 2230 (((uint8_t *)entry_hdr) + 2231 entry_hdr->entry_size); 2232 } 2233 2234 if ((data_collected + ha->fw_dump_tmplt_size) != ha->fw_dump_size) { 2235 ql4_printk(KERN_INFO, ha, 2236 "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n", 2237 data_collected, ha->fw_dump_size); 2238 goto md_failed; 2239 } 2240 2241 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n", 2242 __func__, i)); 2243 md_failed: 2244 return rval; 2245 } 2246 2247 /** 2248 * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready. 2249 * @ha: pointer to adapter structure 2250 **/ 2251 static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code) 2252 { 2253 char event_string[40]; 2254 char *envp[] = { event_string, NULL }; 2255 2256 switch (code) { 2257 case QL4_UEVENT_CODE_FW_DUMP: 2258 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 2259 ha->host_no); 2260 break; 2261 default: 2262 /*do nothing*/ 2263 break; 2264 } 2265 2266 kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp); 2267 } 2268 2269 /** 2270 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw 2271 * @ha: pointer to adapter structure 2272 * 2273 * Note: IDC lock must be held upon entry 2274 **/ 2275 static int 2276 qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) 2277 { 2278 int rval = QLA_ERROR; 2279 int i, timeout; 2280 uint32_t old_count, count; 2281 int need_reset = 0, peg_stuck = 1; 2282 2283 need_reset = qla4_8xxx_need_reset(ha); 2284 2285 old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2286 2287 for (i = 0; i < 10; i++) { 2288 timeout = msleep_interruptible(200); 2289 if (timeout) { 2290 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2291 QLA82XX_DEV_FAILED); 2292 return rval; 2293 } 2294 2295 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2296 if (count != old_count) 2297 peg_stuck = 0; 2298 } 2299 2300 if (need_reset) { 2301 /* We are trying to perform a recovery here. */ 2302 if (peg_stuck) 2303 qla4_8xxx_rom_lock_recovery(ha); 2304 goto dev_initialize; 2305 } else { 2306 /* Start of day for this ha context. */ 2307 if (peg_stuck) { 2308 /* Either we are the first or recovery in progress. */ 2309 qla4_8xxx_rom_lock_recovery(ha); 2310 goto dev_initialize; 2311 } else { 2312 /* Firmware already running. */ 2313 rval = QLA_SUCCESS; 2314 goto dev_ready; 2315 } 2316 } 2317 2318 dev_initialize: 2319 /* set to DEV_INITIALIZING */ 2320 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 2321 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 2322 2323 /* Driver that sets device state to initializating sets IDC version */ 2324 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 2325 2326 qla4_8xxx_idc_unlock(ha); 2327 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) && 2328 !test_and_set_bit(AF_82XX_FW_DUMPED, &ha->flags)) { 2329 if (!qla4_8xxx_collect_md_data(ha)) { 2330 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP); 2331 } else { 2332 ql4_printk(KERN_INFO, ha, "Unable to collect minidump\n"); 2333 clear_bit(AF_82XX_FW_DUMPED, &ha->flags); 2334 } 2335 } 2336 rval = qla4_8xxx_try_start_fw(ha); 2337 qla4_8xxx_idc_lock(ha); 2338 2339 if (rval != QLA_SUCCESS) { 2340 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 2341 qla4_8xxx_clear_drv_active(ha); 2342 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 2343 return rval; 2344 } 2345 2346 dev_ready: 2347 ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 2348 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 2349 2350 return rval; 2351 } 2352 2353 /** 2354 * qla4_8xxx_need_reset_handler - Code to start reset sequence 2355 * @ha: pointer to adapter structure 2356 * 2357 * Note: IDC lock must be held upon entry 2358 **/ 2359 static void 2360 qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha) 2361 { 2362 uint32_t dev_state, drv_state, drv_active; 2363 uint32_t active_mask = 0xFFFFFFFF; 2364 unsigned long reset_timeout; 2365 2366 ql4_printk(KERN_INFO, ha, 2367 "Performing ISP error recovery\n"); 2368 2369 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { 2370 qla4_8xxx_idc_unlock(ha); 2371 ha->isp_ops->disable_intrs(ha); 2372 qla4_8xxx_idc_lock(ha); 2373 } 2374 2375 if (!test_bit(AF_82XX_RST_OWNER, &ha->flags)) { 2376 DEBUG2(ql4_printk(KERN_INFO, ha, 2377 "%s(%ld): reset acknowledged\n", 2378 __func__, ha->host_no)); 2379 qla4_8xxx_set_rst_ready(ha); 2380 } else { 2381 active_mask = (~(1 << (ha->func_num * 4))); 2382 } 2383 2384 /* wait for 10 seconds for reset ack from all functions */ 2385 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 2386 2387 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2388 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2389 2390 ql4_printk(KERN_INFO, ha, 2391 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 2392 __func__, ha->host_no, drv_state, drv_active); 2393 2394 while (drv_state != (drv_active & active_mask)) { 2395 if (time_after_eq(jiffies, reset_timeout)) { 2396 ql4_printk(KERN_INFO, ha, 2397 "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", 2398 DRIVER_NAME, drv_state, drv_active); 2399 break; 2400 } 2401 2402 /* 2403 * When reset_owner times out, check which functions 2404 * acked/did not ack 2405 */ 2406 if (test_bit(AF_82XX_RST_OWNER, &ha->flags)) { 2407 ql4_printk(KERN_INFO, ha, 2408 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 2409 __func__, ha->host_no, drv_state, 2410 drv_active); 2411 } 2412 qla4_8xxx_idc_unlock(ha); 2413 msleep(1000); 2414 qla4_8xxx_idc_lock(ha); 2415 2416 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2417 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2418 } 2419 2420 /* Clear RESET OWNER as we are not going to use it any further */ 2421 clear_bit(AF_82XX_RST_OWNER, &ha->flags); 2422 2423 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2424 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, 2425 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 2426 2427 /* Force to DEV_COLD unless someone else is starting a reset */ 2428 if (dev_state != QLA82XX_DEV_INITIALIZING) { 2429 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 2430 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 2431 qla4_8xxx_set_rst_ready(ha); 2432 } 2433 } 2434 2435 /** 2436 * qla4_8xxx_need_qsnt_handler - Code to start qsnt 2437 * @ha: pointer to adapter structure 2438 **/ 2439 void 2440 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 2441 { 2442 qla4_8xxx_idc_lock(ha); 2443 qla4_8xxx_set_qsnt_ready(ha); 2444 qla4_8xxx_idc_unlock(ha); 2445 } 2446 2447 /** 2448 * qla4_8xxx_device_state_handler - Adapter state machine 2449 * @ha: pointer to host adapter structure. 2450 * 2451 * Note: IDC lock must be UNLOCKED upon entry 2452 **/ 2453 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) 2454 { 2455 uint32_t dev_state; 2456 int rval = QLA_SUCCESS; 2457 unsigned long dev_init_timeout; 2458 2459 if (!test_bit(AF_INIT_DONE, &ha->flags)) { 2460 qla4_8xxx_idc_lock(ha); 2461 qla4_8xxx_set_drv_active(ha); 2462 qla4_8xxx_idc_unlock(ha); 2463 } 2464 2465 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2466 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 2467 dev_state, dev_state < MAX_STATES ? 2468 qdev_state[dev_state] : "Unknown")); 2469 2470 /* wait for 30 seconds for device to go ready */ 2471 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 2472 2473 qla4_8xxx_idc_lock(ha); 2474 while (1) { 2475 2476 if (time_after_eq(jiffies, dev_init_timeout)) { 2477 ql4_printk(KERN_WARNING, ha, 2478 "%s: Device Init Failed 0x%x = %s\n", 2479 DRIVER_NAME, 2480 dev_state, dev_state < MAX_STATES ? 2481 qdev_state[dev_state] : "Unknown"); 2482 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2483 QLA82XX_DEV_FAILED); 2484 } 2485 2486 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2487 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 2488 dev_state, dev_state < MAX_STATES ? 2489 qdev_state[dev_state] : "Unknown"); 2490 2491 /* NOTE: Make sure idc unlocked upon exit of switch statement */ 2492 switch (dev_state) { 2493 case QLA82XX_DEV_READY: 2494 goto exit; 2495 case QLA82XX_DEV_COLD: 2496 rval = qla4_8xxx_device_bootstrap(ha); 2497 goto exit; 2498 case QLA82XX_DEV_INITIALIZING: 2499 qla4_8xxx_idc_unlock(ha); 2500 msleep(1000); 2501 qla4_8xxx_idc_lock(ha); 2502 break; 2503 case QLA82XX_DEV_NEED_RESET: 2504 if (!ql4xdontresethba) { 2505 qla4_8xxx_need_reset_handler(ha); 2506 /* Update timeout value after need 2507 * reset handler */ 2508 dev_init_timeout = jiffies + 2509 (ha->nx_dev_init_timeout * HZ); 2510 } else { 2511 qla4_8xxx_idc_unlock(ha); 2512 msleep(1000); 2513 qla4_8xxx_idc_lock(ha); 2514 } 2515 break; 2516 case QLA82XX_DEV_NEED_QUIESCENT: 2517 /* idc locked/unlocked in handler */ 2518 qla4_8xxx_need_qsnt_handler(ha); 2519 break; 2520 case QLA82XX_DEV_QUIESCENT: 2521 qla4_8xxx_idc_unlock(ha); 2522 msleep(1000); 2523 qla4_8xxx_idc_lock(ha); 2524 break; 2525 case QLA82XX_DEV_FAILED: 2526 qla4_8xxx_idc_unlock(ha); 2527 qla4xxx_dead_adapter_cleanup(ha); 2528 rval = QLA_ERROR; 2529 qla4_8xxx_idc_lock(ha); 2530 goto exit; 2531 default: 2532 qla4_8xxx_idc_unlock(ha); 2533 qla4xxx_dead_adapter_cleanup(ha); 2534 rval = QLA_ERROR; 2535 qla4_8xxx_idc_lock(ha); 2536 goto exit; 2537 } 2538 } 2539 exit: 2540 qla4_8xxx_idc_unlock(ha); 2541 return rval; 2542 } 2543 2544 int qla4_8xxx_load_risc(struct scsi_qla_host *ha) 2545 { 2546 int retval; 2547 2548 /* clear the interrupt */ 2549 writel(0, &ha->qla4_8xxx_reg->host_int); 2550 readl(&ha->qla4_8xxx_reg->host_int); 2551 2552 retval = qla4_8xxx_device_state_handler(ha); 2553 2554 if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags)) 2555 retval = qla4xxx_request_irqs(ha); 2556 2557 return retval; 2558 } 2559 2560 /*****************************************************************************/ 2561 /* Flash Manipulation Routines */ 2562 /*****************************************************************************/ 2563 2564 #define OPTROM_BURST_SIZE 0x1000 2565 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 2566 2567 #define FARX_DATA_FLAG BIT_31 2568 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 2569 #define FARX_ACCESS_FLASH_DATA 0x7FF00000 2570 2571 static inline uint32_t 2572 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 2573 { 2574 return hw->flash_conf_off | faddr; 2575 } 2576 2577 static inline uint32_t 2578 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 2579 { 2580 return hw->flash_data_off | faddr; 2581 } 2582 2583 static uint32_t * 2584 qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, 2585 uint32_t faddr, uint32_t length) 2586 { 2587 uint32_t i; 2588 uint32_t val; 2589 int loops = 0; 2590 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) { 2591 udelay(100); 2592 cond_resched(); 2593 loops++; 2594 } 2595 if (loops >= 50000) { 2596 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); 2597 return dwptr; 2598 } 2599 2600 /* Dword reads to flash. */ 2601 for (i = 0; i < length/4; i++, faddr += 4) { 2602 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) { 2603 ql4_printk(KERN_WARNING, ha, 2604 "Do ROM fast read failed\n"); 2605 goto done_read; 2606 } 2607 dwptr[i] = __constant_cpu_to_le32(val); 2608 } 2609 2610 done_read: 2611 qla4_8xxx_rom_unlock(ha); 2612 return dwptr; 2613 } 2614 2615 /** 2616 * Address and length are byte address 2617 **/ 2618 static uint8_t * 2619 qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 2620 uint32_t offset, uint32_t length) 2621 { 2622 qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length); 2623 return buf; 2624 } 2625 2626 static int 2627 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) 2628 { 2629 const char *loc, *locations[] = { "DEF", "PCI" }; 2630 2631 /* 2632 * FLT-location structure resides after the last PCI region. 2633 */ 2634 2635 /* Begin with sane defaults. */ 2636 loc = locations[0]; 2637 *start = FA_FLASH_LAYOUT_ADDR_82; 2638 2639 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 2640 return QLA_SUCCESS; 2641 } 2642 2643 static void 2644 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) 2645 { 2646 const char *loc, *locations[] = { "DEF", "FLT" }; 2647 uint16_t *wptr; 2648 uint16_t cnt, chksum; 2649 uint32_t start; 2650 struct qla_flt_header *flt; 2651 struct qla_flt_region *region; 2652 struct ql82xx_hw_data *hw = &ha->hw; 2653 2654 hw->flt_region_flt = flt_addr; 2655 wptr = (uint16_t *)ha->request_ring; 2656 flt = (struct qla_flt_header *)ha->request_ring; 2657 region = (struct qla_flt_region *)&flt[1]; 2658 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2659 flt_addr << 2, OPTROM_BURST_SIZE); 2660 if (*wptr == __constant_cpu_to_le16(0xffff)) 2661 goto no_flash_data; 2662 if (flt->version != __constant_cpu_to_le16(1)) { 2663 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " 2664 "version=0x%x length=0x%x checksum=0x%x.\n", 2665 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 2666 le16_to_cpu(flt->checksum))); 2667 goto no_flash_data; 2668 } 2669 2670 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 2671 for (chksum = 0; cnt; cnt--) 2672 chksum += le16_to_cpu(*wptr++); 2673 if (chksum) { 2674 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 2675 "version=0x%x length=0x%x checksum=0x%x.\n", 2676 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 2677 chksum)); 2678 goto no_flash_data; 2679 } 2680 2681 loc = locations[1]; 2682 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 2683 for ( ; cnt; cnt--, region++) { 2684 /* Store addresses as DWORD offsets. */ 2685 start = le32_to_cpu(region->start) >> 2; 2686 2687 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 2688 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 2689 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 2690 2691 switch (le32_to_cpu(region->code) & 0xff) { 2692 case FLT_REG_FDT: 2693 hw->flt_region_fdt = start; 2694 break; 2695 case FLT_REG_BOOT_CODE_82: 2696 hw->flt_region_boot = start; 2697 break; 2698 case FLT_REG_FW_82: 2699 case FLT_REG_FW_82_1: 2700 hw->flt_region_fw = start; 2701 break; 2702 case FLT_REG_BOOTLOAD_82: 2703 hw->flt_region_bootload = start; 2704 break; 2705 case FLT_REG_ISCSI_PARAM: 2706 hw->flt_iscsi_param = start; 2707 break; 2708 case FLT_REG_ISCSI_CHAP: 2709 hw->flt_region_chap = start; 2710 hw->flt_chap_size = le32_to_cpu(region->size); 2711 break; 2712 } 2713 } 2714 goto done; 2715 2716 no_flash_data: 2717 /* Use hardcoded defaults. */ 2718 loc = locations[0]; 2719 2720 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; 2721 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; 2722 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; 2723 hw->flt_region_fw = FA_RISC_CODE_ADDR_82; 2724 hw->flt_region_chap = FA_FLASH_ISCSI_CHAP; 2725 hw->flt_chap_size = FA_FLASH_CHAP_SIZE; 2726 2727 done: 2728 DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x " 2729 "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt, 2730 hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload, 2731 hw->flt_region_fw)); 2732 } 2733 2734 static void 2735 qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha) 2736 { 2737 #define FLASH_BLK_SIZE_4K 0x1000 2738 #define FLASH_BLK_SIZE_32K 0x8000 2739 #define FLASH_BLK_SIZE_64K 0x10000 2740 const char *loc, *locations[] = { "MID", "FDT" }; 2741 uint16_t cnt, chksum; 2742 uint16_t *wptr; 2743 struct qla_fdt_layout *fdt; 2744 uint16_t mid = 0; 2745 uint16_t fid = 0; 2746 struct ql82xx_hw_data *hw = &ha->hw; 2747 2748 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2749 hw->flash_data_off = FARX_ACCESS_FLASH_DATA; 2750 2751 wptr = (uint16_t *)ha->request_ring; 2752 fdt = (struct qla_fdt_layout *)ha->request_ring; 2753 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2754 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); 2755 2756 if (*wptr == __constant_cpu_to_le16(0xffff)) 2757 goto no_flash_data; 2758 2759 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 2760 fdt->sig[3] != 'D') 2761 goto no_flash_data; 2762 2763 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 2764 cnt++) 2765 chksum += le16_to_cpu(*wptr++); 2766 2767 if (chksum) { 2768 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 2769 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 2770 le16_to_cpu(fdt->version))); 2771 goto no_flash_data; 2772 } 2773 2774 loc = locations[1]; 2775 mid = le16_to_cpu(fdt->man_id); 2776 fid = le16_to_cpu(fdt->id); 2777 hw->fdt_wrt_disable = fdt->wrt_disable_bits; 2778 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); 2779 hw->fdt_block_size = le32_to_cpu(fdt->block_size); 2780 2781 if (fdt->unprotect_sec_cmd) { 2782 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | 2783 fdt->unprotect_sec_cmd); 2784 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 2785 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : 2786 flash_conf_addr(hw, 0x0336); 2787 } 2788 goto done; 2789 2790 no_flash_data: 2791 loc = locations[0]; 2792 hw->fdt_block_size = FLASH_BLK_SIZE_64K; 2793 done: 2794 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 2795 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 2796 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, 2797 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, 2798 hw->fdt_block_size)); 2799 } 2800 2801 static void 2802 qla4_8xxx_get_idc_param(struct scsi_qla_host *ha) 2803 { 2804 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 2805 uint32_t *wptr; 2806 2807 if (!is_qla8022(ha)) 2808 return; 2809 wptr = (uint32_t *)ha->request_ring; 2810 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2811 QLA82XX_IDC_PARAM_ADDR , 8); 2812 2813 if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 2814 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; 2815 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; 2816 } else { 2817 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 2818 ha->nx_reset_timeout = le32_to_cpu(*wptr); 2819 } 2820 2821 DEBUG2(ql4_printk(KERN_DEBUG, ha, 2822 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); 2823 DEBUG2(ql4_printk(KERN_DEBUG, ha, 2824 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); 2825 return; 2826 } 2827 2828 int 2829 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 2830 { 2831 int ret; 2832 uint32_t flt_addr; 2833 2834 ret = qla4_8xxx_find_flt_start(ha, &flt_addr); 2835 if (ret != QLA_SUCCESS) 2836 return ret; 2837 2838 qla4_8xxx_get_flt_info(ha, flt_addr); 2839 qla4_8xxx_get_fdt_info(ha); 2840 qla4_8xxx_get_idc_param(ha); 2841 2842 return QLA_SUCCESS; 2843 } 2844 2845 /** 2846 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance 2847 * @ha: pointer to host adapter structure. 2848 * 2849 * Remarks: 2850 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will 2851 * not be available after successful return. Driver must cleanup potential 2852 * outstanding I/O's after calling this funcion. 2853 **/ 2854 int 2855 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) 2856 { 2857 int status; 2858 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2859 uint32_t mbox_sts[MBOX_REG_COUNT]; 2860 2861 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2862 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2863 2864 mbox_cmd[0] = MBOX_CMD_STOP_FW; 2865 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, 2866 &mbox_cmd[0], &mbox_sts[0]); 2867 2868 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, 2869 __func__, status)); 2870 return status; 2871 } 2872 2873 /** 2874 * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands. 2875 * @ha: pointer to host adapter structure. 2876 **/ 2877 int 2878 qla4_8xxx_isp_reset(struct scsi_qla_host *ha) 2879 { 2880 int rval; 2881 uint32_t dev_state; 2882 2883 qla4_8xxx_idc_lock(ha); 2884 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2885 2886 if (dev_state == QLA82XX_DEV_READY) { 2887 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 2888 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2889 QLA82XX_DEV_NEED_RESET); 2890 set_bit(AF_82XX_RST_OWNER, &ha->flags); 2891 } else 2892 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); 2893 2894 qla4_8xxx_idc_unlock(ha); 2895 2896 rval = qla4_8xxx_device_state_handler(ha); 2897 2898 qla4_8xxx_idc_lock(ha); 2899 qla4_8xxx_clear_rst_ready(ha); 2900 qla4_8xxx_idc_unlock(ha); 2901 2902 if (rval == QLA_SUCCESS) { 2903 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_8xxx_isp_reset\n"); 2904 clear_bit(AF_FW_RECOVERY, &ha->flags); 2905 } 2906 2907 return rval; 2908 } 2909 2910 /** 2911 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number 2912 * @ha: pointer to host adapter structure. 2913 * 2914 **/ 2915 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) 2916 { 2917 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2918 uint32_t mbox_sts[MBOX_REG_COUNT]; 2919 struct mbx_sys_info *sys_info; 2920 dma_addr_t sys_info_dma; 2921 int status = QLA_ERROR; 2922 2923 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), 2924 &sys_info_dma, GFP_KERNEL); 2925 if (sys_info == NULL) { 2926 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", 2927 ha->host_no, __func__)); 2928 return status; 2929 } 2930 2931 memset(sys_info, 0, sizeof(*sys_info)); 2932 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2933 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2934 2935 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; 2936 mbox_cmd[1] = LSDW(sys_info_dma); 2937 mbox_cmd[2] = MSDW(sys_info_dma); 2938 mbox_cmd[4] = sizeof(*sys_info); 2939 2940 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], 2941 &mbox_sts[0]) != QLA_SUCCESS) { 2942 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", 2943 ha->host_no, __func__)); 2944 goto exit_validate_mac82; 2945 } 2946 2947 /* Make sure we receive the minimum required data to cache internally */ 2948 if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) { 2949 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" 2950 " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); 2951 goto exit_validate_mac82; 2952 2953 } 2954 2955 /* Save M.A.C. address & serial_number */ 2956 ha->port_num = sys_info->port_num; 2957 memcpy(ha->my_mac, &sys_info->mac_addr[0], 2958 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); 2959 memcpy(ha->serial_number, &sys_info->serial_number, 2960 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); 2961 memcpy(ha->model_name, &sys_info->board_id_str, 2962 min(sizeof(ha->model_name), sizeof(sys_info->board_id_str))); 2963 ha->phy_port_cnt = sys_info->phys_port_cnt; 2964 ha->phy_port_num = sys_info->port_num; 2965 ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt; 2966 2967 DEBUG2(printk("scsi%ld: %s: " 2968 "mac %02x:%02x:%02x:%02x:%02x:%02x " 2969 "serial %s\n", ha->host_no, __func__, 2970 ha->my_mac[0], ha->my_mac[1], ha->my_mac[2], 2971 ha->my_mac[3], ha->my_mac[4], ha->my_mac[5], 2972 ha->serial_number)); 2973 2974 status = QLA_SUCCESS; 2975 2976 exit_validate_mac82: 2977 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, 2978 sys_info_dma); 2979 return status; 2980 } 2981 2982 /* Interrupt handling helpers. */ 2983 2984 static int 2985 qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha) 2986 { 2987 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2988 uint32_t mbox_sts[MBOX_REG_COUNT]; 2989 2990 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 2991 2992 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2993 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2994 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 2995 mbox_cmd[1] = INTR_ENABLE; 2996 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 2997 &mbox_sts[0]) != QLA_SUCCESS) { 2998 DEBUG2(ql4_printk(KERN_INFO, ha, 2999 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 3000 __func__, mbox_sts[0])); 3001 return QLA_ERROR; 3002 } 3003 return QLA_SUCCESS; 3004 } 3005 3006 static int 3007 qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha) 3008 { 3009 uint32_t mbox_cmd[MBOX_REG_COUNT]; 3010 uint32_t mbox_sts[MBOX_REG_COUNT]; 3011 3012 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 3013 3014 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 3015 memset(&mbox_sts, 0, sizeof(mbox_sts)); 3016 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 3017 mbox_cmd[1] = INTR_DISABLE; 3018 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 3019 &mbox_sts[0]) != QLA_SUCCESS) { 3020 DEBUG2(ql4_printk(KERN_INFO, ha, 3021 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 3022 __func__, mbox_sts[0])); 3023 return QLA_ERROR; 3024 } 3025 3026 return QLA_SUCCESS; 3027 } 3028 3029 void 3030 qla4_8xxx_enable_intrs(struct scsi_qla_host *ha) 3031 { 3032 qla4_8xxx_mbx_intr_enable(ha); 3033 3034 spin_lock_irq(&ha->hardware_lock); 3035 /* BIT 10 - reset */ 3036 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 3037 spin_unlock_irq(&ha->hardware_lock); 3038 set_bit(AF_INTERRUPTS_ON, &ha->flags); 3039 } 3040 3041 void 3042 qla4_8xxx_disable_intrs(struct scsi_qla_host *ha) 3043 { 3044 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) 3045 qla4_8xxx_mbx_intr_disable(ha); 3046 3047 spin_lock_irq(&ha->hardware_lock); 3048 /* BIT 10 - set */ 3049 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 3050 spin_unlock_irq(&ha->hardware_lock); 3051 } 3052 3053 struct ql4_init_msix_entry { 3054 uint16_t entry; 3055 uint16_t index; 3056 const char *name; 3057 irq_handler_t handler; 3058 }; 3059 3060 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = { 3061 { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT, 3062 "qla4xxx (default)", 3063 (irq_handler_t)qla4_8xxx_default_intr_handler }, 3064 { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q, 3065 "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q }, 3066 }; 3067 3068 void 3069 qla4_8xxx_disable_msix(struct scsi_qla_host *ha) 3070 { 3071 int i; 3072 struct ql4_msix_entry *qentry; 3073 3074 for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 3075 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 3076 if (qentry->have_irq) { 3077 free_irq(qentry->msix_vector, ha); 3078 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 3079 __func__, qla4_8xxx_msix_entries[i].name)); 3080 } 3081 } 3082 pci_disable_msix(ha->pdev); 3083 clear_bit(AF_MSIX_ENABLED, &ha->flags); 3084 } 3085 3086 int 3087 qla4_8xxx_enable_msix(struct scsi_qla_host *ha) 3088 { 3089 int i, ret; 3090 struct msix_entry entries[QLA_MSIX_ENTRIES]; 3091 struct ql4_msix_entry *qentry; 3092 3093 for (i = 0; i < QLA_MSIX_ENTRIES; i++) 3094 entries[i].entry = qla4_8xxx_msix_entries[i].entry; 3095 3096 ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries)); 3097 if (ret) { 3098 ql4_printk(KERN_WARNING, ha, 3099 "MSI-X: Failed to enable support -- %d/%d\n", 3100 QLA_MSIX_ENTRIES, ret); 3101 goto msix_out; 3102 } 3103 set_bit(AF_MSIX_ENABLED, &ha->flags); 3104 3105 for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 3106 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 3107 qentry->msix_vector = entries[i].vector; 3108 qentry->msix_entry = entries[i].entry; 3109 qentry->have_irq = 0; 3110 ret = request_irq(qentry->msix_vector, 3111 qla4_8xxx_msix_entries[i].handler, 0, 3112 qla4_8xxx_msix_entries[i].name, ha); 3113 if (ret) { 3114 ql4_printk(KERN_WARNING, ha, 3115 "MSI-X: Unable to register handler -- %x/%d.\n", 3116 qla4_8xxx_msix_entries[i].index, ret); 3117 qla4_8xxx_disable_msix(ha); 3118 goto msix_out; 3119 } 3120 qentry->have_irq = 1; 3121 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 3122 __func__, qla4_8xxx_msix_entries[i].name)); 3123 } 3124 msix_out: 3125 return ret; 3126 } 3127