1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 #include <linux/delay.h> 8 #include <linux/io.h> 9 #include <linux/pci.h> 10 #include "ql4_def.h" 11 #include "ql4_glbl.h" 12 13 #define MASK(n) DMA_BIT_MASK(n) 14 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 15 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 16 #define MS_WIN(addr) (addr & 0x0ffc0000) 17 #define QLA82XX_PCI_MN_2M (0) 18 #define QLA82XX_PCI_MS_2M (0x80000) 19 #define QLA82XX_PCI_OCM0_2M (0xc0000) 20 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 21 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 22 23 /* CRB window related */ 24 #define CRB_BLK(off) ((off >> 20) & 0x3f) 25 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 26 #define CRB_WINDOW_2M (0x130060) 27 #define CRB_HI(off) ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 28 ((off) & 0xf0000)) 29 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 30 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 31 #define CRB_INDIRECT_2M (0x1e0000UL) 32 33 static inline void __iomem * 34 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) 35 { 36 if ((off < ha->first_page_group_end) && 37 (off >= ha->first_page_group_start)) 38 return (void __iomem *)(ha->nx_pcibase + off); 39 40 return NULL; 41 } 42 43 #define MAX_CRB_XFORM 60 44 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 45 static int qla4_8xxx_crb_table_initialized; 46 47 #define qla4_8xxx_crb_addr_transform(name) \ 48 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 49 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 50 static void 51 qla4_8xxx_crb_addr_transform_setup(void) 52 { 53 qla4_8xxx_crb_addr_transform(XDMA); 54 qla4_8xxx_crb_addr_transform(TIMR); 55 qla4_8xxx_crb_addr_transform(SRE); 56 qla4_8xxx_crb_addr_transform(SQN3); 57 qla4_8xxx_crb_addr_transform(SQN2); 58 qla4_8xxx_crb_addr_transform(SQN1); 59 qla4_8xxx_crb_addr_transform(SQN0); 60 qla4_8xxx_crb_addr_transform(SQS3); 61 qla4_8xxx_crb_addr_transform(SQS2); 62 qla4_8xxx_crb_addr_transform(SQS1); 63 qla4_8xxx_crb_addr_transform(SQS0); 64 qla4_8xxx_crb_addr_transform(RPMX7); 65 qla4_8xxx_crb_addr_transform(RPMX6); 66 qla4_8xxx_crb_addr_transform(RPMX5); 67 qla4_8xxx_crb_addr_transform(RPMX4); 68 qla4_8xxx_crb_addr_transform(RPMX3); 69 qla4_8xxx_crb_addr_transform(RPMX2); 70 qla4_8xxx_crb_addr_transform(RPMX1); 71 qla4_8xxx_crb_addr_transform(RPMX0); 72 qla4_8xxx_crb_addr_transform(ROMUSB); 73 qla4_8xxx_crb_addr_transform(SN); 74 qla4_8xxx_crb_addr_transform(QMN); 75 qla4_8xxx_crb_addr_transform(QMS); 76 qla4_8xxx_crb_addr_transform(PGNI); 77 qla4_8xxx_crb_addr_transform(PGND); 78 qla4_8xxx_crb_addr_transform(PGN3); 79 qla4_8xxx_crb_addr_transform(PGN2); 80 qla4_8xxx_crb_addr_transform(PGN1); 81 qla4_8xxx_crb_addr_transform(PGN0); 82 qla4_8xxx_crb_addr_transform(PGSI); 83 qla4_8xxx_crb_addr_transform(PGSD); 84 qla4_8xxx_crb_addr_transform(PGS3); 85 qla4_8xxx_crb_addr_transform(PGS2); 86 qla4_8xxx_crb_addr_transform(PGS1); 87 qla4_8xxx_crb_addr_transform(PGS0); 88 qla4_8xxx_crb_addr_transform(PS); 89 qla4_8xxx_crb_addr_transform(PH); 90 qla4_8xxx_crb_addr_transform(NIU); 91 qla4_8xxx_crb_addr_transform(I2Q); 92 qla4_8xxx_crb_addr_transform(EG); 93 qla4_8xxx_crb_addr_transform(MN); 94 qla4_8xxx_crb_addr_transform(MS); 95 qla4_8xxx_crb_addr_transform(CAS2); 96 qla4_8xxx_crb_addr_transform(CAS1); 97 qla4_8xxx_crb_addr_transform(CAS0); 98 qla4_8xxx_crb_addr_transform(CAM); 99 qla4_8xxx_crb_addr_transform(C2C1); 100 qla4_8xxx_crb_addr_transform(C2C0); 101 qla4_8xxx_crb_addr_transform(SMB); 102 qla4_8xxx_crb_addr_transform(OCM0); 103 qla4_8xxx_crb_addr_transform(I2C0); 104 105 qla4_8xxx_crb_table_initialized = 1; 106 } 107 108 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 109 {{{0, 0, 0, 0} } }, /* 0: PCI */ 110 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 111 {1, 0x0110000, 0x0120000, 0x130000}, 112 {1, 0x0120000, 0x0122000, 0x124000}, 113 {1, 0x0130000, 0x0132000, 0x126000}, 114 {1, 0x0140000, 0x0142000, 0x128000}, 115 {1, 0x0150000, 0x0152000, 0x12a000}, 116 {1, 0x0160000, 0x0170000, 0x110000}, 117 {1, 0x0170000, 0x0172000, 0x12e000}, 118 {0, 0x0000000, 0x0000000, 0x000000}, 119 {0, 0x0000000, 0x0000000, 0x000000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {0, 0x0000000, 0x0000000, 0x000000}, 124 {1, 0x01e0000, 0x01e0800, 0x122000}, 125 {0, 0x0000000, 0x0000000, 0x000000} } }, 126 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 127 {{{0, 0, 0, 0} } }, /* 3: */ 128 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 129 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 130 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 131 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 132 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 133 {0, 0x0000000, 0x0000000, 0x000000}, 134 {0, 0x0000000, 0x0000000, 0x000000}, 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 148 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 149 {0, 0x0000000, 0x0000000, 0x000000}, 150 {0, 0x0000000, 0x0000000, 0x000000}, 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 164 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 165 {0, 0x0000000, 0x0000000, 0x000000}, 166 {0, 0x0000000, 0x0000000, 0x000000}, 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000}, 177 {0, 0x0000000, 0x0000000, 0x000000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 180 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 181 {0, 0x0000000, 0x0000000, 0x000000}, 182 {0, 0x0000000, 0x0000000, 0x000000}, 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {0, 0x0000000, 0x0000000, 0x000000}, 193 {0, 0x0000000, 0x0000000, 0x000000}, 194 {0, 0x0000000, 0x0000000, 0x000000}, 195 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 196 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 197 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 198 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 199 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 200 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 201 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 202 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 203 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 204 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 205 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 206 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 207 {{{0, 0, 0, 0} } }, /* 23: */ 208 {{{0, 0, 0, 0} } }, /* 24: */ 209 {{{0, 0, 0, 0} } }, /* 25: */ 210 {{{0, 0, 0, 0} } }, /* 26: */ 211 {{{0, 0, 0, 0} } }, /* 27: */ 212 {{{0, 0, 0, 0} } }, /* 28: */ 213 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 214 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 215 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 216 {{{0} } }, /* 32: PCI */ 217 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 218 {1, 0x2110000, 0x2120000, 0x130000}, 219 {1, 0x2120000, 0x2122000, 0x124000}, 220 {1, 0x2130000, 0x2132000, 0x126000}, 221 {1, 0x2140000, 0x2142000, 0x128000}, 222 {1, 0x2150000, 0x2152000, 0x12a000}, 223 {1, 0x2160000, 0x2170000, 0x110000}, 224 {1, 0x2170000, 0x2172000, 0x12e000}, 225 {0, 0x0000000, 0x0000000, 0x000000}, 226 {0, 0x0000000, 0x0000000, 0x000000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000}, 230 {0, 0x0000000, 0x0000000, 0x000000}, 231 {0, 0x0000000, 0x0000000, 0x000000}, 232 {0, 0x0000000, 0x0000000, 0x000000} } }, 233 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 234 {{{0} } }, /* 35: */ 235 {{{0} } }, /* 36: */ 236 {{{0} } }, /* 37: */ 237 {{{0} } }, /* 38: */ 238 {{{0} } }, /* 39: */ 239 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 240 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 241 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 242 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 243 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 244 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 245 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 246 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 247 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 248 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 249 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 250 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 251 {{{0} } }, /* 52: */ 252 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 253 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 254 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 255 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 256 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 257 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 258 {{{0} } }, /* 59: I2C0 */ 259 {{{0} } }, /* 60: I2C1 */ 260 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ 261 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 262 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 263 }; 264 265 /* 266 * top 12 bits of crb internal address (hub, agent) 267 */ 268 static unsigned qla4_8xxx_crb_hub_agt[64] = { 269 0, 270 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 271 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 273 0, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 275 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 296 0, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 298 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 299 0, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 301 0, 302 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 303 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 304 0, 305 0, 306 0, 307 0, 308 0, 309 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 310 0, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 318 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 321 0, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 323 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 326 0, 327 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 328 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 329 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 330 0, 331 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 332 0, 333 }; 334 335 /* Device states */ 336 static char *qdev_state[] = { 337 "Unknown", 338 "Cold", 339 "Initializing", 340 "Ready", 341 "Need Reset", 342 "Need Quiescent", 343 "Failed", 344 "Quiescent", 345 }; 346 347 /* 348 * In: 'off' is offset from CRB space in 128M pci map 349 * Out: 'off' is 2M pci map addr 350 * side effect: lock crb window 351 */ 352 static void 353 qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) 354 { 355 u32 win_read; 356 357 ha->crb_win = CRB_HI(*off); 358 writel(ha->crb_win, 359 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 360 361 /* Read back value to make sure write has gone through before trying 362 * to use it. */ 363 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 364 if (win_read != ha->crb_win) { 365 DEBUG2(ql4_printk(KERN_INFO, ha, 366 "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," 367 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 368 } 369 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 370 } 371 372 void 373 qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) 374 { 375 unsigned long flags = 0; 376 int rv; 377 378 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off); 379 380 BUG_ON(rv == -1); 381 382 if (rv == 1) { 383 write_lock_irqsave(&ha->hw_lock, flags); 384 qla4_8xxx_crb_win_lock(ha); 385 qla4_8xxx_pci_set_crbwindow_2M(ha, &off); 386 } 387 388 writel(data, (void __iomem *)off); 389 390 if (rv == 1) { 391 qla4_8xxx_crb_win_unlock(ha); 392 write_unlock_irqrestore(&ha->hw_lock, flags); 393 } 394 } 395 396 int 397 qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off) 398 { 399 unsigned long flags = 0; 400 int rv; 401 u32 data; 402 403 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off); 404 405 BUG_ON(rv == -1); 406 407 if (rv == 1) { 408 write_lock_irqsave(&ha->hw_lock, flags); 409 qla4_8xxx_crb_win_lock(ha); 410 qla4_8xxx_pci_set_crbwindow_2M(ha, &off); 411 } 412 data = readl((void __iomem *)off); 413 414 if (rv == 1) { 415 qla4_8xxx_crb_win_unlock(ha); 416 write_unlock_irqrestore(&ha->hw_lock, flags); 417 } 418 return data; 419 } 420 421 #define CRB_WIN_LOCK_TIMEOUT 100000000 422 423 int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha) 424 { 425 int i; 426 int done = 0, timeout = 0; 427 428 while (!done) { 429 /* acquire semaphore3 from PCI HW block */ 430 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 431 if (done == 1) 432 break; 433 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 434 return -1; 435 436 timeout++; 437 438 /* Yield CPU */ 439 if (!in_interrupt()) 440 schedule(); 441 else { 442 for (i = 0; i < 20; i++) 443 cpu_relax(); /*This a nop instr on i386*/ 444 } 445 } 446 qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); 447 return 0; 448 } 449 450 void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha) 451 { 452 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 453 } 454 455 #define IDC_LOCK_TIMEOUT 100000000 456 457 /** 458 * qla4_8xxx_idc_lock - hw_lock 459 * @ha: pointer to adapter structure 460 * 461 * General purpose lock used to synchronize access to 462 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. 463 **/ 464 int qla4_8xxx_idc_lock(struct scsi_qla_host *ha) 465 { 466 int i; 467 int done = 0, timeout = 0; 468 469 while (!done) { 470 /* acquire semaphore5 from PCI HW block */ 471 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 472 if (done == 1) 473 break; 474 if (timeout >= IDC_LOCK_TIMEOUT) 475 return -1; 476 477 timeout++; 478 479 /* Yield CPU */ 480 if (!in_interrupt()) 481 schedule(); 482 else { 483 for (i = 0; i < 20; i++) 484 cpu_relax(); /*This a nop instr on i386*/ 485 } 486 } 487 return 0; 488 } 489 490 void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha) 491 { 492 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 493 } 494 495 int 496 qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) 497 { 498 struct crb_128M_2M_sub_block_map *m; 499 500 if (*off >= QLA82XX_CRB_MAX) 501 return -1; 502 503 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 504 *off = (*off - QLA82XX_PCI_CAMQM) + 505 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 506 return 0; 507 } 508 509 if (*off < QLA82XX_PCI_CRBSPACE) 510 return -1; 511 512 *off -= QLA82XX_PCI_CRBSPACE; 513 /* 514 * Try direct map 515 */ 516 517 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 518 519 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 520 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 521 return 0; 522 } 523 524 /* 525 * Not in direct map, use crb window 526 */ 527 return 1; 528 } 529 530 /* PCI Windowing for DDR regions. */ 531 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 532 (((addr) <= (high)) && ((addr) >= (low))) 533 534 /* 535 * check memory access boundary. 536 * used by test agent. support ddr access only for now 537 */ 538 static unsigned long 539 qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha, 540 unsigned long long addr, int size) 541 { 542 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 543 QLA82XX_ADDR_DDR_NET_MAX) || 544 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, 545 QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) || 546 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { 547 return 0; 548 } 549 return 1; 550 } 551 552 static int qla4_8xxx_pci_set_window_warning_count; 553 554 static unsigned long 555 qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) 556 { 557 int window; 558 u32 win_read; 559 560 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 561 QLA82XX_ADDR_DDR_NET_MAX)) { 562 /* DDR network side */ 563 window = MN_WIN(addr); 564 ha->ddr_mn_window = window; 565 qla4_8xxx_wr_32(ha, ha->mn_win_crb | 566 QLA82XX_PCI_CRBSPACE, window); 567 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb | 568 QLA82XX_PCI_CRBSPACE); 569 if ((win_read << 17) != window) { 570 ql4_printk(KERN_WARNING, ha, 571 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 572 __func__, window, win_read); 573 } 574 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 575 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 576 QLA82XX_ADDR_OCM0_MAX)) { 577 unsigned int temp1; 578 /* if bits 19:18&17:11 are on */ 579 if ((addr & 0x00ff800) == 0xff800) { 580 printk("%s: QM access not handled.\n", __func__); 581 addr = -1UL; 582 } 583 584 window = OCM_WIN(addr); 585 ha->ddr_mn_window = window; 586 qla4_8xxx_wr_32(ha, ha->mn_win_crb | 587 QLA82XX_PCI_CRBSPACE, window); 588 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb | 589 QLA82XX_PCI_CRBSPACE); 590 temp1 = ((window & 0x1FF) << 7) | 591 ((window & 0x0FFFE0000) >> 17); 592 if (win_read != temp1) { 593 printk("%s: Written OCMwin (0x%x) != Read" 594 " OCMwin (0x%x)\n", __func__, temp1, win_read); 595 } 596 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 597 598 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 599 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 600 /* QDR network side */ 601 window = MS_WIN(addr); 602 ha->qdr_sn_window = window; 603 qla4_8xxx_wr_32(ha, ha->ms_win_crb | 604 QLA82XX_PCI_CRBSPACE, window); 605 win_read = qla4_8xxx_rd_32(ha, 606 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 607 if (win_read != window) { 608 printk("%s: Written MSwin (0x%x) != Read " 609 "MSwin (0x%x)\n", __func__, window, win_read); 610 } 611 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 612 613 } else { 614 /* 615 * peg gdb frequently accesses memory that doesn't exist, 616 * this limits the chit chat so debugging isn't slowed down. 617 */ 618 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) || 619 (qla4_8xxx_pci_set_window_warning_count%64 == 0)) { 620 printk("%s: Warning:%s Unknown address range!\n", 621 __func__, DRIVER_NAME); 622 } 623 addr = -1UL; 624 } 625 return addr; 626 } 627 628 /* check if address is in the same windows as the previous access */ 629 static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha, 630 unsigned long long addr) 631 { 632 int window; 633 unsigned long long qdr_max; 634 635 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 636 637 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 638 QLA82XX_ADDR_DDR_NET_MAX)) { 639 /* DDR network side */ 640 BUG(); /* MN access can not come here */ 641 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 642 QLA82XX_ADDR_OCM0_MAX)) { 643 return 1; 644 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 645 QLA82XX_ADDR_OCM1_MAX)) { 646 return 1; 647 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 648 qdr_max)) { 649 /* QDR network side */ 650 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 651 if (ha->qdr_sn_window == window) 652 return 1; 653 } 654 655 return 0; 656 } 657 658 static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha, 659 u64 off, void *data, int size) 660 { 661 unsigned long flags; 662 void __iomem *addr; 663 int ret = 0; 664 u64 start; 665 void __iomem *mem_ptr = NULL; 666 unsigned long mem_base; 667 unsigned long mem_page; 668 669 write_lock_irqsave(&ha->hw_lock, flags); 670 671 /* 672 * If attempting to access unknown address or straddle hw windows, 673 * do not access. 674 */ 675 start = qla4_8xxx_pci_set_window(ha, off); 676 if ((start == -1UL) || 677 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) { 678 write_unlock_irqrestore(&ha->hw_lock, flags); 679 printk(KERN_ERR"%s out of bound pci memory access. " 680 "offset is 0x%llx\n", DRIVER_NAME, off); 681 return -1; 682 } 683 684 addr = qla4_8xxx_pci_base_offsetfset(ha, start); 685 if (!addr) { 686 write_unlock_irqrestore(&ha->hw_lock, flags); 687 mem_base = pci_resource_start(ha->pdev, 0); 688 mem_page = start & PAGE_MASK; 689 /* Map two pages whenever user tries to access addresses in two 690 consecutive pages. 691 */ 692 if (mem_page != ((start + size - 1) & PAGE_MASK)) 693 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 694 else 695 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 696 697 if (mem_ptr == NULL) { 698 *(u8 *)data = 0; 699 return -1; 700 } 701 addr = mem_ptr; 702 addr += start & (PAGE_SIZE - 1); 703 write_lock_irqsave(&ha->hw_lock, flags); 704 } 705 706 switch (size) { 707 case 1: 708 *(u8 *)data = readb(addr); 709 break; 710 case 2: 711 *(u16 *)data = readw(addr); 712 break; 713 case 4: 714 *(u32 *)data = readl(addr); 715 break; 716 case 8: 717 *(u64 *)data = readq(addr); 718 break; 719 default: 720 ret = -1; 721 break; 722 } 723 write_unlock_irqrestore(&ha->hw_lock, flags); 724 725 if (mem_ptr) 726 iounmap(mem_ptr); 727 return ret; 728 } 729 730 static int 731 qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, 732 void *data, int size) 733 { 734 unsigned long flags; 735 void __iomem *addr; 736 int ret = 0; 737 u64 start; 738 void __iomem *mem_ptr = NULL; 739 unsigned long mem_base; 740 unsigned long mem_page; 741 742 write_lock_irqsave(&ha->hw_lock, flags); 743 744 /* 745 * If attempting to access unknown address or straddle hw windows, 746 * do not access. 747 */ 748 start = qla4_8xxx_pci_set_window(ha, off); 749 if ((start == -1UL) || 750 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) { 751 write_unlock_irqrestore(&ha->hw_lock, flags); 752 printk(KERN_ERR"%s out of bound pci memory access. " 753 "offset is 0x%llx\n", DRIVER_NAME, off); 754 return -1; 755 } 756 757 addr = qla4_8xxx_pci_base_offsetfset(ha, start); 758 if (!addr) { 759 write_unlock_irqrestore(&ha->hw_lock, flags); 760 mem_base = pci_resource_start(ha->pdev, 0); 761 mem_page = start & PAGE_MASK; 762 /* Map two pages whenever user tries to access addresses in two 763 consecutive pages. 764 */ 765 if (mem_page != ((start + size - 1) & PAGE_MASK)) 766 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 767 else 768 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 769 if (mem_ptr == NULL) 770 return -1; 771 772 addr = mem_ptr; 773 addr += start & (PAGE_SIZE - 1); 774 write_lock_irqsave(&ha->hw_lock, flags); 775 } 776 777 switch (size) { 778 case 1: 779 writeb(*(u8 *)data, addr); 780 break; 781 case 2: 782 writew(*(u16 *)data, addr); 783 break; 784 case 4: 785 writel(*(u32 *)data, addr); 786 break; 787 case 8: 788 writeq(*(u64 *)data, addr); 789 break; 790 default: 791 ret = -1; 792 break; 793 } 794 write_unlock_irqrestore(&ha->hw_lock, flags); 795 if (mem_ptr) 796 iounmap(mem_ptr); 797 return ret; 798 } 799 800 #define MTU_FUDGE_FACTOR 100 801 802 static unsigned long 803 qla4_8xxx_decode_crb_addr(unsigned long addr) 804 { 805 int i; 806 unsigned long base_addr, offset, pci_base; 807 808 if (!qla4_8xxx_crb_table_initialized) 809 qla4_8xxx_crb_addr_transform_setup(); 810 811 pci_base = ADDR_ERROR; 812 base_addr = addr & 0xfff00000; 813 offset = addr & 0x000fffff; 814 815 for (i = 0; i < MAX_CRB_XFORM; i++) { 816 if (crb_addr_xform[i] == base_addr) { 817 pci_base = i << 20; 818 break; 819 } 820 } 821 if (pci_base == ADDR_ERROR) 822 return pci_base; 823 else 824 return pci_base + offset; 825 } 826 827 static long rom_max_timeout = 100; 828 static long qla4_8xxx_rom_lock_timeout = 100; 829 830 static int 831 qla4_8xxx_rom_lock(struct scsi_qla_host *ha) 832 { 833 int i; 834 int done = 0, timeout = 0; 835 836 while (!done) { 837 /* acquire semaphore2 from PCI HW block */ 838 839 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 840 if (done == 1) 841 break; 842 if (timeout >= qla4_8xxx_rom_lock_timeout) { 843 ql4_printk(KERN_WARNING, ha, 844 "%s: Failed to acquire rom lock", __func__); 845 return -1; 846 } 847 848 timeout++; 849 850 /* Yield CPU */ 851 if (!in_interrupt()) 852 schedule(); 853 else { 854 for (i = 0; i < 20; i++) 855 cpu_relax(); /*This a nop instr on i386*/ 856 } 857 } 858 qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 859 return 0; 860 } 861 862 static void 863 qla4_8xxx_rom_unlock(struct scsi_qla_host *ha) 864 { 865 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 866 } 867 868 static int 869 qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha) 870 { 871 long timeout = 0; 872 long done = 0 ; 873 874 while (done == 0) { 875 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 876 done &= 2; 877 timeout++; 878 if (timeout >= rom_max_timeout) { 879 printk("%s: Timeout reached waiting for rom done", 880 DRIVER_NAME); 881 return -1; 882 } 883 } 884 return 0; 885 } 886 887 static int 888 qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 889 { 890 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 891 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 892 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 893 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 894 if (qla4_8xxx_wait_rom_done(ha)) { 895 printk("%s: Error waiting for rom done\n", DRIVER_NAME); 896 return -1; 897 } 898 /* reset abyte_cnt and dummy_byte_cnt */ 899 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 900 udelay(10); 901 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 902 903 *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 904 return 0; 905 } 906 907 static int 908 qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 909 { 910 int ret, loops = 0; 911 912 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) { 913 udelay(100); 914 loops++; 915 } 916 if (loops >= 50000) { 917 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME); 918 return -1; 919 } 920 ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp); 921 qla4_8xxx_rom_unlock(ha); 922 return ret; 923 } 924 925 /** 926 * This routine does CRB initialize sequence 927 * to put the ISP into operational state 928 **/ 929 static int 930 qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) 931 { 932 int addr, val; 933 int i ; 934 struct crb_addr_pair *buf; 935 unsigned long off; 936 unsigned offset, n; 937 938 struct crb_addr_pair { 939 long addr; 940 long data; 941 }; 942 943 /* Halt all the indiviual PEGs and other blocks of the ISP */ 944 qla4_8xxx_rom_lock(ha); 945 946 /* mask all niu interrupts */ 947 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 948 /* disable xge rx/tx */ 949 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 950 /* disable xg1 rx/tx */ 951 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 952 953 /* halt sre */ 954 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 955 qla4_8xxx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 956 957 /* halt epg */ 958 qla4_8xxx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 959 960 /* halt timers */ 961 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 962 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 963 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 964 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 965 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 966 967 /* halt pegs */ 968 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 969 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 970 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 971 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 972 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 973 974 /* big hammer */ 975 msleep(1000); 976 if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 977 /* don't reset CAM block on reset */ 978 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 979 else 980 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 981 982 /* reset ms */ 983 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 984 val |= (1 << 1); 985 qla4_8xxx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 986 987 msleep(20); 988 /* unreset ms */ 989 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 990 val &= ~(1 << 1); 991 qla4_8xxx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 992 msleep(20); 993 994 qla4_8xxx_rom_unlock(ha); 995 996 /* Read the signature value from the flash. 997 * Offset 0: Contain signature (0xcafecafe) 998 * Offset 4: Offset and number of addr/value pairs 999 * that present in CRB initialize sequence 1000 */ 1001 if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1002 qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) { 1003 ql4_printk(KERN_WARNING, ha, 1004 "[ERROR] Reading crb_init area: n: %08x\n", n); 1005 return -1; 1006 } 1007 1008 /* Offset in flash = lower 16 bits 1009 * Number of enteries = upper 16 bits 1010 */ 1011 offset = n & 0xffffU; 1012 n = (n >> 16) & 0xffffU; 1013 1014 /* number of addr/value pair should not exceed 1024 enteries */ 1015 if (n >= 1024) { 1016 ql4_printk(KERN_WARNING, ha, 1017 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1018 DRIVER_NAME, __func__, n); 1019 return -1; 1020 } 1021 1022 ql4_printk(KERN_INFO, ha, 1023 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); 1024 1025 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1026 if (buf == NULL) { 1027 ql4_printk(KERN_WARNING, ha, 1028 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); 1029 return -1; 1030 } 1031 1032 for (i = 0; i < n; i++) { 1033 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1034 qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 1035 0) { 1036 kfree(buf); 1037 return -1; 1038 } 1039 1040 buf[i].addr = addr; 1041 buf[i].data = val; 1042 } 1043 1044 for (i = 0; i < n; i++) { 1045 /* Translate internal CRB initialization 1046 * address to PCI bus address 1047 */ 1048 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) + 1049 QLA82XX_PCI_CRBSPACE; 1050 /* Not all CRB addr/value pair to be written, 1051 * some of them are skipped 1052 */ 1053 1054 /* skip if LS bit is set*/ 1055 if (off & 0x1) { 1056 DEBUG2(ql4_printk(KERN_WARNING, ha, 1057 "Skip CRB init replay for offset = 0x%lx\n", off)); 1058 continue; 1059 } 1060 1061 /* skipping cold reboot MAGIC */ 1062 if (off == QLA82XX_CAM_RAM(0x1fc)) 1063 continue; 1064 1065 /* do not reset PCI */ 1066 if (off == (ROMUSB_GLB + 0xbc)) 1067 continue; 1068 1069 /* skip core clock, so that firmware can increase the clock */ 1070 if (off == (ROMUSB_GLB + 0xc8)) 1071 continue; 1072 1073 /* skip the function enable register */ 1074 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1075 continue; 1076 1077 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1078 continue; 1079 1080 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1081 continue; 1082 1083 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1084 continue; 1085 1086 if (off == ADDR_ERROR) { 1087 ql4_printk(KERN_WARNING, ha, 1088 "%s: [ERROR] Unknown addr: 0x%08lx\n", 1089 DRIVER_NAME, buf[i].addr); 1090 continue; 1091 } 1092 1093 qla4_8xxx_wr_32(ha, off, buf[i].data); 1094 1095 /* ISP requires much bigger delay to settle down, 1096 * else crb_window returns 0xffffffff 1097 */ 1098 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1099 msleep(1000); 1100 1101 /* ISP requires millisec delay between 1102 * successive CRB register updation 1103 */ 1104 msleep(1); 1105 } 1106 1107 kfree(buf); 1108 1109 /* Resetting the data and instruction cache */ 1110 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1111 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1112 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1113 1114 /* Clear all protocol processing engines */ 1115 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1116 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1117 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1118 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1119 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1120 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1121 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1122 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1123 1124 return 0; 1125 } 1126 1127 static int 1128 qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) 1129 { 1130 int i, rval = 0; 1131 long size = 0; 1132 long flashaddr, memaddr; 1133 u64 data; 1134 u32 high, low; 1135 1136 flashaddr = memaddr = ha->hw.flt_region_bootload; 1137 size = (image_start - flashaddr) / 8; 1138 1139 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", 1140 ha->host_no, __func__, flashaddr, image_start)); 1141 1142 for (i = 0; i < size; i++) { 1143 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1144 (qla4_8xxx_rom_fast_read(ha, flashaddr + 4, 1145 (int *)&high))) { 1146 rval = -1; 1147 goto exit_load_from_flash; 1148 } 1149 data = ((u64)high << 32) | low ; 1150 rval = qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8); 1151 if (rval) 1152 goto exit_load_from_flash; 1153 1154 flashaddr += 8; 1155 memaddr += 8; 1156 1157 if (i % 0x1000 == 0) 1158 msleep(1); 1159 1160 } 1161 1162 udelay(100); 1163 1164 read_lock(&ha->hw_lock); 1165 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1166 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1167 read_unlock(&ha->hw_lock); 1168 1169 exit_load_from_flash: 1170 return rval; 1171 } 1172 1173 static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) 1174 { 1175 u32 rst; 1176 1177 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1178 if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { 1179 printk(KERN_WARNING "%s: Error during CRB Initialization\n", 1180 __func__); 1181 return QLA_ERROR; 1182 } 1183 1184 udelay(500); 1185 1186 /* at this point, QM is in reset. This could be a problem if there are 1187 * incoming d* transition queue messages. QM/PCIE could wedge. 1188 * To get around this, QM is brought out of reset. 1189 */ 1190 1191 rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 1192 /* unreset qm */ 1193 rst &= ~(1 << 28); 1194 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 1195 1196 if (qla4_8xxx_load_from_flash(ha, image_start)) { 1197 printk("%s: Error trying to load fw from flash!\n", __func__); 1198 return QLA_ERROR; 1199 } 1200 1201 return QLA_SUCCESS; 1202 } 1203 1204 int 1205 qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha, 1206 u64 off, void *data, int size) 1207 { 1208 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1209 int shift_amount; 1210 uint32_t temp; 1211 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1212 1213 /* 1214 * If not MN, go check for MS or invalid. 1215 */ 1216 1217 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1218 mem_crb = QLA82XX_CRB_QDR_NET; 1219 else { 1220 mem_crb = QLA82XX_CRB_DDR_NET; 1221 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0) 1222 return qla4_8xxx_pci_mem_read_direct(ha, 1223 off, data, size); 1224 } 1225 1226 1227 off8 = off & 0xfffffff0; 1228 off0[0] = off & 0xf; 1229 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1230 shift_amount = 4; 1231 1232 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1233 off0[1] = 0; 1234 sz[1] = size - sz[0]; 1235 1236 for (i = 0; i < loop; i++) { 1237 temp = off8 + (i << shift_amount); 1238 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1239 temp = 0; 1240 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1241 temp = MIU_TA_CTL_ENABLE; 1242 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1243 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1244 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1245 1246 for (j = 0; j < MAX_CTL_CHECK; j++) { 1247 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1248 if ((temp & MIU_TA_CTL_BUSY) == 0) 1249 break; 1250 } 1251 1252 if (j >= MAX_CTL_CHECK) { 1253 if (printk_ratelimit()) 1254 ql4_printk(KERN_ERR, ha, 1255 "failed to read through agent\n"); 1256 break; 1257 } 1258 1259 start = off0[i] >> 2; 1260 end = (off0[i] + sz[i] - 1) >> 2; 1261 for (k = start; k <= end; k++) { 1262 temp = qla4_8xxx_rd_32(ha, 1263 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1264 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1265 } 1266 } 1267 1268 if (j >= MAX_CTL_CHECK) 1269 return -1; 1270 1271 if ((off0[0] & 7) == 0) { 1272 val = word[0]; 1273 } else { 1274 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1275 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1276 } 1277 1278 switch (size) { 1279 case 1: 1280 *(uint8_t *)data = val; 1281 break; 1282 case 2: 1283 *(uint16_t *)data = val; 1284 break; 1285 case 4: 1286 *(uint32_t *)data = val; 1287 break; 1288 case 8: 1289 *(uint64_t *)data = val; 1290 break; 1291 } 1292 return 0; 1293 } 1294 1295 int 1296 qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha, 1297 u64 off, void *data, int size) 1298 { 1299 int i, j, ret = 0, loop, sz[2], off0; 1300 int scale, shift_amount, startword; 1301 uint32_t temp; 1302 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1303 1304 /* 1305 * If not MN, go check for MS or invalid. 1306 */ 1307 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1308 mem_crb = QLA82XX_CRB_QDR_NET; 1309 else { 1310 mem_crb = QLA82XX_CRB_DDR_NET; 1311 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0) 1312 return qla4_8xxx_pci_mem_write_direct(ha, 1313 off, data, size); 1314 } 1315 1316 off0 = off & 0x7; 1317 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1318 sz[1] = size - sz[0]; 1319 1320 off8 = off & 0xfffffff0; 1321 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1322 shift_amount = 4; 1323 scale = 2; 1324 startword = (off & 0xf)/8; 1325 1326 for (i = 0; i < loop; i++) { 1327 if (qla4_8xxx_pci_mem_read_2M(ha, off8 + 1328 (i << shift_amount), &word[i * scale], 8)) 1329 return -1; 1330 } 1331 1332 switch (size) { 1333 case 1: 1334 tmpw = *((uint8_t *)data); 1335 break; 1336 case 2: 1337 tmpw = *((uint16_t *)data); 1338 break; 1339 case 4: 1340 tmpw = *((uint32_t *)data); 1341 break; 1342 case 8: 1343 default: 1344 tmpw = *((uint64_t *)data); 1345 break; 1346 } 1347 1348 if (sz[0] == 8) 1349 word[startword] = tmpw; 1350 else { 1351 word[startword] &= 1352 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1353 word[startword] |= tmpw << (off0 * 8); 1354 } 1355 1356 if (sz[1] != 0) { 1357 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1358 word[startword+1] |= tmpw >> (sz[0] * 8); 1359 } 1360 1361 for (i = 0; i < loop; i++) { 1362 temp = off8 + (i << shift_amount); 1363 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1364 temp = 0; 1365 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1366 temp = word[i * scale] & 0xffffffff; 1367 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1368 temp = (word[i * scale] >> 32) & 0xffffffff; 1369 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1370 temp = word[i*scale + 1] & 0xffffffff; 1371 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, 1372 temp); 1373 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1374 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, 1375 temp); 1376 1377 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1378 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1379 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1380 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1381 1382 for (j = 0; j < MAX_CTL_CHECK; j++) { 1383 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1384 if ((temp & MIU_TA_CTL_BUSY) == 0) 1385 break; 1386 } 1387 1388 if (j >= MAX_CTL_CHECK) { 1389 if (printk_ratelimit()) 1390 ql4_printk(KERN_ERR, ha, 1391 "failed to write through agent\n"); 1392 ret = -1; 1393 break; 1394 } 1395 } 1396 1397 return ret; 1398 } 1399 1400 static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) 1401 { 1402 u32 val = 0; 1403 int retries = 60; 1404 1405 if (!pegtune_val) { 1406 do { 1407 val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE); 1408 if ((val == PHAN_INITIALIZE_COMPLETE) || 1409 (val == PHAN_INITIALIZE_ACK)) 1410 return 0; 1411 set_current_state(TASK_UNINTERRUPTIBLE); 1412 schedule_timeout(500); 1413 1414 } while (--retries); 1415 1416 if (!retries) { 1417 pegtune_val = qla4_8xxx_rd_32(ha, 1418 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1419 printk(KERN_WARNING "%s: init failed, " 1420 "pegtune_val = %x\n", __func__, pegtune_val); 1421 return -1; 1422 } 1423 } 1424 return 0; 1425 } 1426 1427 static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha) 1428 { 1429 uint32_t state = 0; 1430 int loops = 0; 1431 1432 /* Window 1 call */ 1433 read_lock(&ha->hw_lock); 1434 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE); 1435 read_unlock(&ha->hw_lock); 1436 1437 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { 1438 udelay(100); 1439 /* Window 1 call */ 1440 read_lock(&ha->hw_lock); 1441 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE); 1442 read_unlock(&ha->hw_lock); 1443 1444 loops++; 1445 } 1446 1447 if (loops >= 30000) { 1448 DEBUG2(ql4_printk(KERN_INFO, ha, 1449 "Receive Peg initialization not complete: 0x%x.\n", state)); 1450 return QLA_ERROR; 1451 } 1452 1453 return QLA_SUCCESS; 1454 } 1455 1456 void 1457 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) 1458 { 1459 uint32_t drv_active; 1460 1461 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1462 drv_active |= (1 << (ha->func_num * 4)); 1463 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1464 } 1465 1466 void 1467 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) 1468 { 1469 uint32_t drv_active; 1470 1471 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1472 drv_active &= ~(1 << (ha->func_num * 4)); 1473 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1474 } 1475 1476 static inline int 1477 qla4_8xxx_need_reset(struct scsi_qla_host *ha) 1478 { 1479 uint32_t drv_state, drv_active; 1480 int rval; 1481 1482 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1483 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1484 rval = drv_state & (1 << (ha->func_num * 4)); 1485 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 1486 rval = 1; 1487 1488 return rval; 1489 } 1490 1491 static inline void 1492 qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) 1493 { 1494 uint32_t drv_state; 1495 1496 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1497 drv_state |= (1 << (ha->func_num * 4)); 1498 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1499 } 1500 1501 static inline void 1502 qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) 1503 { 1504 uint32_t drv_state; 1505 1506 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1507 drv_state &= ~(1 << (ha->func_num * 4)); 1508 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1509 } 1510 1511 static inline void 1512 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) 1513 { 1514 uint32_t qsnt_state; 1515 1516 qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1517 qsnt_state |= (2 << (ha->func_num * 4)); 1518 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 1519 } 1520 1521 1522 static int 1523 qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) 1524 { 1525 int pcie_cap; 1526 uint16_t lnk; 1527 1528 /* scrub dma mask expansion register */ 1529 qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 1530 1531 /* Overwrite stale initialization register values */ 1532 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1533 qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0); 1534 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 1535 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 1536 1537 if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) { 1538 printk("%s: Error trying to start fw!\n", __func__); 1539 return QLA_ERROR; 1540 } 1541 1542 /* Handshake with the card before we register the devices. */ 1543 if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { 1544 printk("%s: Error during card handshake!\n", __func__); 1545 return QLA_ERROR; 1546 } 1547 1548 /* Negotiated Link width */ 1549 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1550 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 1551 ha->link_width = (lnk >> 4) & 0x3f; 1552 1553 /* Synchronize with Receive peg */ 1554 return qla4_8xxx_rcvpeg_ready(ha); 1555 } 1556 1557 static int 1558 qla4_8xxx_try_start_fw(struct scsi_qla_host *ha) 1559 { 1560 int rval = QLA_ERROR; 1561 1562 /* 1563 * FW Load priority: 1564 * 1) Operational firmware residing in flash. 1565 * 2) Fail 1566 */ 1567 1568 ql4_printk(KERN_INFO, ha, 1569 "FW: Retrieving flash offsets from FLT/FDT ...\n"); 1570 rval = qla4_8xxx_get_flash_info(ha); 1571 if (rval != QLA_SUCCESS) 1572 return rval; 1573 1574 ql4_printk(KERN_INFO, ha, 1575 "FW: Attempting to load firmware from flash...\n"); 1576 rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw); 1577 1578 if (rval != QLA_SUCCESS) { 1579 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" 1580 " FAILED...\n"); 1581 return rval; 1582 } 1583 1584 return rval; 1585 } 1586 1587 static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha) 1588 { 1589 if (qla4_8xxx_rom_lock(ha)) { 1590 /* Someone else is holding the lock. */ 1591 dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); 1592 } 1593 1594 /* 1595 * Either we got the lock, or someone 1596 * else died while holding it. 1597 * In either case, unlock. 1598 */ 1599 qla4_8xxx_rom_unlock(ha); 1600 } 1601 1602 /** 1603 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw 1604 * @ha: pointer to adapter structure 1605 * 1606 * Note: IDC lock must be held upon entry 1607 **/ 1608 static int 1609 qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) 1610 { 1611 int rval = QLA_ERROR; 1612 int i, timeout; 1613 uint32_t old_count, count; 1614 int need_reset = 0, peg_stuck = 1; 1615 1616 need_reset = qla4_8xxx_need_reset(ha); 1617 1618 old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 1619 1620 for (i = 0; i < 10; i++) { 1621 timeout = msleep_interruptible(200); 1622 if (timeout) { 1623 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 1624 QLA82XX_DEV_FAILED); 1625 return rval; 1626 } 1627 1628 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 1629 if (count != old_count) 1630 peg_stuck = 0; 1631 } 1632 1633 if (need_reset) { 1634 /* We are trying to perform a recovery here. */ 1635 if (peg_stuck) 1636 qla4_8xxx_rom_lock_recovery(ha); 1637 goto dev_initialize; 1638 } else { 1639 /* Start of day for this ha context. */ 1640 if (peg_stuck) { 1641 /* Either we are the first or recovery in progress. */ 1642 qla4_8xxx_rom_lock_recovery(ha); 1643 goto dev_initialize; 1644 } else { 1645 /* Firmware already running. */ 1646 rval = QLA_SUCCESS; 1647 goto dev_ready; 1648 } 1649 } 1650 1651 dev_initialize: 1652 /* set to DEV_INITIALIZING */ 1653 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 1654 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 1655 1656 /* Driver that sets device state to initializating sets IDC version */ 1657 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 1658 1659 qla4_8xxx_idc_unlock(ha); 1660 rval = qla4_8xxx_try_start_fw(ha); 1661 qla4_8xxx_idc_lock(ha); 1662 1663 if (rval != QLA_SUCCESS) { 1664 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 1665 qla4_8xxx_clear_drv_active(ha); 1666 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 1667 return rval; 1668 } 1669 1670 dev_ready: 1671 ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 1672 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 1673 1674 return rval; 1675 } 1676 1677 /** 1678 * qla4_8xxx_need_reset_handler - Code to start reset sequence 1679 * @ha: pointer to adapter structure 1680 * 1681 * Note: IDC lock must be held upon entry 1682 **/ 1683 static void 1684 qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha) 1685 { 1686 uint32_t dev_state, drv_state, drv_active; 1687 unsigned long reset_timeout; 1688 1689 ql4_printk(KERN_INFO, ha, 1690 "Performing ISP error recovery\n"); 1691 1692 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { 1693 qla4_8xxx_idc_unlock(ha); 1694 ha->isp_ops->disable_intrs(ha); 1695 qla4_8xxx_idc_lock(ha); 1696 } 1697 1698 qla4_8xxx_set_rst_ready(ha); 1699 1700 /* wait for 10 seconds for reset ack from all functions */ 1701 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 1702 1703 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1704 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1705 1706 ql4_printk(KERN_INFO, ha, 1707 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 1708 __func__, ha->host_no, drv_state, drv_active); 1709 1710 while (drv_state != drv_active) { 1711 if (time_after_eq(jiffies, reset_timeout)) { 1712 printk("%s: RESET TIMEOUT!\n", DRIVER_NAME); 1713 break; 1714 } 1715 1716 qla4_8xxx_idc_unlock(ha); 1717 msleep(1000); 1718 qla4_8xxx_idc_lock(ha); 1719 1720 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1721 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1722 } 1723 1724 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 1725 ql4_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state, 1726 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 1727 1728 /* Force to DEV_COLD unless someone else is starting a reset */ 1729 if (dev_state != QLA82XX_DEV_INITIALIZING) { 1730 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 1731 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 1732 } 1733 } 1734 1735 /** 1736 * qla4_8xxx_need_qsnt_handler - Code to start qsnt 1737 * @ha: pointer to adapter structure 1738 **/ 1739 void 1740 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 1741 { 1742 qla4_8xxx_idc_lock(ha); 1743 qla4_8xxx_set_qsnt_ready(ha); 1744 qla4_8xxx_idc_unlock(ha); 1745 } 1746 1747 /** 1748 * qla4_8xxx_device_state_handler - Adapter state machine 1749 * @ha: pointer to host adapter structure. 1750 * 1751 * Note: IDC lock must be UNLOCKED upon entry 1752 **/ 1753 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) 1754 { 1755 uint32_t dev_state; 1756 int rval = QLA_SUCCESS; 1757 unsigned long dev_init_timeout; 1758 1759 if (!test_bit(AF_INIT_DONE, &ha->flags)) 1760 qla4_8xxx_set_drv_active(ha); 1761 1762 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 1763 ql4_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state, 1764 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 1765 1766 /* wait for 30 seconds for device to go ready */ 1767 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 1768 1769 while (1) { 1770 qla4_8xxx_idc_lock(ha); 1771 1772 if (time_after_eq(jiffies, dev_init_timeout)) { 1773 ql4_printk(KERN_WARNING, ha, "Device init failed!\n"); 1774 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 1775 QLA82XX_DEV_FAILED); 1776 } 1777 1778 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 1779 ql4_printk(KERN_INFO, ha, 1780 "2:Device state is 0x%x = %s\n", dev_state, 1781 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 1782 1783 /* NOTE: Make sure idc unlocked upon exit of switch statement */ 1784 switch (dev_state) { 1785 case QLA82XX_DEV_READY: 1786 qla4_8xxx_idc_unlock(ha); 1787 goto exit; 1788 case QLA82XX_DEV_COLD: 1789 rval = qla4_8xxx_device_bootstrap(ha); 1790 qla4_8xxx_idc_unlock(ha); 1791 goto exit; 1792 case QLA82XX_DEV_INITIALIZING: 1793 qla4_8xxx_idc_unlock(ha); 1794 msleep(1000); 1795 break; 1796 case QLA82XX_DEV_NEED_RESET: 1797 if (!ql4xdontresethba) { 1798 qla4_8xxx_need_reset_handler(ha); 1799 /* Update timeout value after need 1800 * reset handler */ 1801 dev_init_timeout = jiffies + 1802 (ha->nx_dev_init_timeout * HZ); 1803 } 1804 qla4_8xxx_idc_unlock(ha); 1805 break; 1806 case QLA82XX_DEV_NEED_QUIESCENT: 1807 qla4_8xxx_idc_unlock(ha); 1808 /* idc locked/unlocked in handler */ 1809 qla4_8xxx_need_qsnt_handler(ha); 1810 qla4_8xxx_idc_lock(ha); 1811 /* fall thru needs idc_locked */ 1812 case QLA82XX_DEV_QUIESCENT: 1813 qla4_8xxx_idc_unlock(ha); 1814 msleep(1000); 1815 break; 1816 case QLA82XX_DEV_FAILED: 1817 qla4_8xxx_idc_unlock(ha); 1818 qla4xxx_dead_adapter_cleanup(ha); 1819 rval = QLA_ERROR; 1820 goto exit; 1821 default: 1822 qla4_8xxx_idc_unlock(ha); 1823 qla4xxx_dead_adapter_cleanup(ha); 1824 rval = QLA_ERROR; 1825 goto exit; 1826 } 1827 } 1828 exit: 1829 return rval; 1830 } 1831 1832 int qla4_8xxx_load_risc(struct scsi_qla_host *ha) 1833 { 1834 int retval; 1835 retval = qla4_8xxx_device_state_handler(ha); 1836 1837 if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags)) 1838 retval = qla4xxx_request_irqs(ha); 1839 1840 return retval; 1841 } 1842 1843 /*****************************************************************************/ 1844 /* Flash Manipulation Routines */ 1845 /*****************************************************************************/ 1846 1847 #define OPTROM_BURST_SIZE 0x1000 1848 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 1849 1850 #define FARX_DATA_FLAG BIT_31 1851 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 1852 #define FARX_ACCESS_FLASH_DATA 0x7FF00000 1853 1854 static inline uint32_t 1855 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 1856 { 1857 return hw->flash_conf_off | faddr; 1858 } 1859 1860 static inline uint32_t 1861 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 1862 { 1863 return hw->flash_data_off | faddr; 1864 } 1865 1866 static uint32_t * 1867 qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, 1868 uint32_t faddr, uint32_t length) 1869 { 1870 uint32_t i; 1871 uint32_t val; 1872 int loops = 0; 1873 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) { 1874 udelay(100); 1875 cond_resched(); 1876 loops++; 1877 } 1878 if (loops >= 50000) { 1879 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); 1880 return dwptr; 1881 } 1882 1883 /* Dword reads to flash. */ 1884 for (i = 0; i < length/4; i++, faddr += 4) { 1885 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) { 1886 ql4_printk(KERN_WARNING, ha, 1887 "Do ROM fast read failed\n"); 1888 goto done_read; 1889 } 1890 dwptr[i] = __constant_cpu_to_le32(val); 1891 } 1892 1893 done_read: 1894 qla4_8xxx_rom_unlock(ha); 1895 return dwptr; 1896 } 1897 1898 /** 1899 * Address and length are byte address 1900 **/ 1901 static uint8_t * 1902 qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1903 uint32_t offset, uint32_t length) 1904 { 1905 qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length); 1906 return buf; 1907 } 1908 1909 static int 1910 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) 1911 { 1912 const char *loc, *locations[] = { "DEF", "PCI" }; 1913 1914 /* 1915 * FLT-location structure resides after the last PCI region. 1916 */ 1917 1918 /* Begin with sane defaults. */ 1919 loc = locations[0]; 1920 *start = FA_FLASH_LAYOUT_ADDR_82; 1921 1922 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 1923 return QLA_SUCCESS; 1924 } 1925 1926 static void 1927 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) 1928 { 1929 const char *loc, *locations[] = { "DEF", "FLT" }; 1930 uint16_t *wptr; 1931 uint16_t cnt, chksum; 1932 uint32_t start; 1933 struct qla_flt_header *flt; 1934 struct qla_flt_region *region; 1935 struct ql82xx_hw_data *hw = &ha->hw; 1936 1937 hw->flt_region_flt = flt_addr; 1938 wptr = (uint16_t *)ha->request_ring; 1939 flt = (struct qla_flt_header *)ha->request_ring; 1940 region = (struct qla_flt_region *)&flt[1]; 1941 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 1942 flt_addr << 2, OPTROM_BURST_SIZE); 1943 if (*wptr == __constant_cpu_to_le16(0xffff)) 1944 goto no_flash_data; 1945 if (flt->version != __constant_cpu_to_le16(1)) { 1946 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " 1947 "version=0x%x length=0x%x checksum=0x%x.\n", 1948 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 1949 le16_to_cpu(flt->checksum))); 1950 goto no_flash_data; 1951 } 1952 1953 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 1954 for (chksum = 0; cnt; cnt--) 1955 chksum += le16_to_cpu(*wptr++); 1956 if (chksum) { 1957 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 1958 "version=0x%x length=0x%x checksum=0x%x.\n", 1959 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 1960 chksum)); 1961 goto no_flash_data; 1962 } 1963 1964 loc = locations[1]; 1965 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 1966 for ( ; cnt; cnt--, region++) { 1967 /* Store addresses as DWORD offsets. */ 1968 start = le32_to_cpu(region->start) >> 2; 1969 1970 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 1971 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 1972 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 1973 1974 switch (le32_to_cpu(region->code) & 0xff) { 1975 case FLT_REG_FDT: 1976 hw->flt_region_fdt = start; 1977 break; 1978 case FLT_REG_BOOT_CODE_82: 1979 hw->flt_region_boot = start; 1980 break; 1981 case FLT_REG_FW_82: 1982 hw->flt_region_fw = start; 1983 break; 1984 case FLT_REG_BOOTLOAD_82: 1985 hw->flt_region_bootload = start; 1986 break; 1987 } 1988 } 1989 goto done; 1990 1991 no_flash_data: 1992 /* Use hardcoded defaults. */ 1993 loc = locations[0]; 1994 1995 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; 1996 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; 1997 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; 1998 hw->flt_region_fw = FA_RISC_CODE_ADDR_82; 1999 done: 2000 DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x " 2001 "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt, 2002 hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload, 2003 hw->flt_region_fw)); 2004 } 2005 2006 static void 2007 qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha) 2008 { 2009 #define FLASH_BLK_SIZE_4K 0x1000 2010 #define FLASH_BLK_SIZE_32K 0x8000 2011 #define FLASH_BLK_SIZE_64K 0x10000 2012 const char *loc, *locations[] = { "MID", "FDT" }; 2013 uint16_t cnt, chksum; 2014 uint16_t *wptr; 2015 struct qla_fdt_layout *fdt; 2016 uint16_t mid = 0; 2017 uint16_t fid = 0; 2018 struct ql82xx_hw_data *hw = &ha->hw; 2019 2020 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2021 hw->flash_data_off = FARX_ACCESS_FLASH_DATA; 2022 2023 wptr = (uint16_t *)ha->request_ring; 2024 fdt = (struct qla_fdt_layout *)ha->request_ring; 2025 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2026 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); 2027 2028 if (*wptr == __constant_cpu_to_le16(0xffff)) 2029 goto no_flash_data; 2030 2031 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 2032 fdt->sig[3] != 'D') 2033 goto no_flash_data; 2034 2035 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 2036 cnt++) 2037 chksum += le16_to_cpu(*wptr++); 2038 2039 if (chksum) { 2040 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 2041 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 2042 le16_to_cpu(fdt->version))); 2043 goto no_flash_data; 2044 } 2045 2046 loc = locations[1]; 2047 mid = le16_to_cpu(fdt->man_id); 2048 fid = le16_to_cpu(fdt->id); 2049 hw->fdt_wrt_disable = fdt->wrt_disable_bits; 2050 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); 2051 hw->fdt_block_size = le32_to_cpu(fdt->block_size); 2052 2053 if (fdt->unprotect_sec_cmd) { 2054 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | 2055 fdt->unprotect_sec_cmd); 2056 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 2057 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : 2058 flash_conf_addr(hw, 0x0336); 2059 } 2060 goto done; 2061 2062 no_flash_data: 2063 loc = locations[0]; 2064 hw->fdt_block_size = FLASH_BLK_SIZE_64K; 2065 done: 2066 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 2067 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 2068 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, 2069 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, 2070 hw->fdt_block_size)); 2071 } 2072 2073 static void 2074 qla4_8xxx_get_idc_param(struct scsi_qla_host *ha) 2075 { 2076 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 2077 uint32_t *wptr; 2078 2079 if (!is_qla8022(ha)) 2080 return; 2081 wptr = (uint32_t *)ha->request_ring; 2082 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2083 QLA82XX_IDC_PARAM_ADDR , 8); 2084 2085 if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 2086 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; 2087 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; 2088 } else { 2089 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 2090 ha->nx_reset_timeout = le32_to_cpu(*wptr); 2091 } 2092 2093 DEBUG2(ql4_printk(KERN_DEBUG, ha, 2094 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); 2095 DEBUG2(ql4_printk(KERN_DEBUG, ha, 2096 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); 2097 return; 2098 } 2099 2100 int 2101 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 2102 { 2103 int ret; 2104 uint32_t flt_addr; 2105 2106 ret = qla4_8xxx_find_flt_start(ha, &flt_addr); 2107 if (ret != QLA_SUCCESS) 2108 return ret; 2109 2110 qla4_8xxx_get_flt_info(ha, flt_addr); 2111 qla4_8xxx_get_fdt_info(ha); 2112 qla4_8xxx_get_idc_param(ha); 2113 2114 return QLA_SUCCESS; 2115 } 2116 2117 /** 2118 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance 2119 * @ha: pointer to host adapter structure. 2120 * 2121 * Remarks: 2122 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will 2123 * not be available after successful return. Driver must cleanup potential 2124 * outstanding I/O's after calling this funcion. 2125 **/ 2126 int 2127 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) 2128 { 2129 int status; 2130 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2131 uint32_t mbox_sts[MBOX_REG_COUNT]; 2132 2133 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2134 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2135 2136 mbox_cmd[0] = MBOX_CMD_STOP_FW; 2137 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, 2138 &mbox_cmd[0], &mbox_sts[0]); 2139 2140 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, 2141 __func__, status)); 2142 return status; 2143 } 2144 2145 /** 2146 * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands. 2147 * @ha: pointer to host adapter structure. 2148 **/ 2149 int 2150 qla4_8xxx_isp_reset(struct scsi_qla_host *ha) 2151 { 2152 int rval; 2153 uint32_t dev_state; 2154 2155 qla4_8xxx_idc_lock(ha); 2156 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2157 2158 if (dev_state == QLA82XX_DEV_READY) { 2159 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 2160 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2161 QLA82XX_DEV_NEED_RESET); 2162 } else 2163 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); 2164 2165 qla4_8xxx_idc_unlock(ha); 2166 2167 rval = qla4_8xxx_device_state_handler(ha); 2168 2169 qla4_8xxx_idc_lock(ha); 2170 qla4_8xxx_clear_rst_ready(ha); 2171 qla4_8xxx_idc_unlock(ha); 2172 2173 if (rval == QLA_SUCCESS) 2174 clear_bit(AF_FW_RECOVERY, &ha->flags); 2175 2176 return rval; 2177 } 2178 2179 /** 2180 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number 2181 * @ha: pointer to host adapter structure. 2182 * 2183 **/ 2184 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) 2185 { 2186 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2187 uint32_t mbox_sts[MBOX_REG_COUNT]; 2188 struct mbx_sys_info *sys_info; 2189 dma_addr_t sys_info_dma; 2190 int status = QLA_ERROR; 2191 2192 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), 2193 &sys_info_dma, GFP_KERNEL); 2194 if (sys_info == NULL) { 2195 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", 2196 ha->host_no, __func__)); 2197 return status; 2198 } 2199 2200 memset(sys_info, 0, sizeof(*sys_info)); 2201 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2202 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2203 2204 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; 2205 mbox_cmd[1] = LSDW(sys_info_dma); 2206 mbox_cmd[2] = MSDW(sys_info_dma); 2207 mbox_cmd[4] = sizeof(*sys_info); 2208 2209 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], 2210 &mbox_sts[0]) != QLA_SUCCESS) { 2211 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", 2212 ha->host_no, __func__)); 2213 goto exit_validate_mac82; 2214 } 2215 2216 /* Make sure we receive the minimum required data to cache internally */ 2217 if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) { 2218 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" 2219 " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); 2220 goto exit_validate_mac82; 2221 2222 } 2223 2224 /* Save M.A.C. address & serial_number */ 2225 memcpy(ha->my_mac, &sys_info->mac_addr[0], 2226 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); 2227 memcpy(ha->serial_number, &sys_info->serial_number, 2228 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); 2229 2230 DEBUG2(printk("scsi%ld: %s: " 2231 "mac %02x:%02x:%02x:%02x:%02x:%02x " 2232 "serial %s\n", ha->host_no, __func__, 2233 ha->my_mac[0], ha->my_mac[1], ha->my_mac[2], 2234 ha->my_mac[3], ha->my_mac[4], ha->my_mac[5], 2235 ha->serial_number)); 2236 2237 status = QLA_SUCCESS; 2238 2239 exit_validate_mac82: 2240 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, 2241 sys_info_dma); 2242 return status; 2243 } 2244 2245 /* Interrupt handling helpers. */ 2246 2247 static int 2248 qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha) 2249 { 2250 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2251 uint32_t mbox_sts[MBOX_REG_COUNT]; 2252 2253 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 2254 2255 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2256 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2257 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 2258 mbox_cmd[1] = INTR_ENABLE; 2259 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 2260 &mbox_sts[0]) != QLA_SUCCESS) { 2261 DEBUG2(ql4_printk(KERN_INFO, ha, 2262 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 2263 __func__, mbox_sts[0])); 2264 return QLA_ERROR; 2265 } 2266 return QLA_SUCCESS; 2267 } 2268 2269 static int 2270 qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha) 2271 { 2272 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2273 uint32_t mbox_sts[MBOX_REG_COUNT]; 2274 2275 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 2276 2277 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2278 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2279 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 2280 mbox_cmd[1] = INTR_DISABLE; 2281 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 2282 &mbox_sts[0]) != QLA_SUCCESS) { 2283 DEBUG2(ql4_printk(KERN_INFO, ha, 2284 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 2285 __func__, mbox_sts[0])); 2286 return QLA_ERROR; 2287 } 2288 2289 return QLA_SUCCESS; 2290 } 2291 2292 void 2293 qla4_8xxx_enable_intrs(struct scsi_qla_host *ha) 2294 { 2295 qla4_8xxx_mbx_intr_enable(ha); 2296 2297 spin_lock_irq(&ha->hardware_lock); 2298 /* BIT 10 - reset */ 2299 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2300 spin_unlock_irq(&ha->hardware_lock); 2301 set_bit(AF_INTERRUPTS_ON, &ha->flags); 2302 } 2303 2304 void 2305 qla4_8xxx_disable_intrs(struct scsi_qla_host *ha) 2306 { 2307 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) 2308 qla4_8xxx_mbx_intr_disable(ha); 2309 2310 spin_lock_irq(&ha->hardware_lock); 2311 /* BIT 10 - set */ 2312 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2313 spin_unlock_irq(&ha->hardware_lock); 2314 } 2315 2316 struct ql4_init_msix_entry { 2317 uint16_t entry; 2318 uint16_t index; 2319 const char *name; 2320 irq_handler_t handler; 2321 }; 2322 2323 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = { 2324 { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT, 2325 "qla4xxx (default)", 2326 (irq_handler_t)qla4_8xxx_default_intr_handler }, 2327 { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q, 2328 "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q }, 2329 }; 2330 2331 void 2332 qla4_8xxx_disable_msix(struct scsi_qla_host *ha) 2333 { 2334 int i; 2335 struct ql4_msix_entry *qentry; 2336 2337 for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 2338 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 2339 if (qentry->have_irq) { 2340 free_irq(qentry->msix_vector, ha); 2341 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 2342 __func__, qla4_8xxx_msix_entries[i].name)); 2343 } 2344 } 2345 pci_disable_msix(ha->pdev); 2346 clear_bit(AF_MSIX_ENABLED, &ha->flags); 2347 } 2348 2349 int 2350 qla4_8xxx_enable_msix(struct scsi_qla_host *ha) 2351 { 2352 int i, ret; 2353 struct msix_entry entries[QLA_MSIX_ENTRIES]; 2354 struct ql4_msix_entry *qentry; 2355 2356 for (i = 0; i < QLA_MSIX_ENTRIES; i++) 2357 entries[i].entry = qla4_8xxx_msix_entries[i].entry; 2358 2359 ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries)); 2360 if (ret) { 2361 ql4_printk(KERN_WARNING, ha, 2362 "MSI-X: Failed to enable support -- %d/%d\n", 2363 QLA_MSIX_ENTRIES, ret); 2364 goto msix_out; 2365 } 2366 set_bit(AF_MSIX_ENABLED, &ha->flags); 2367 2368 for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 2369 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 2370 qentry->msix_vector = entries[i].vector; 2371 qentry->msix_entry = entries[i].entry; 2372 qentry->have_irq = 0; 2373 ret = request_irq(qentry->msix_vector, 2374 qla4_8xxx_msix_entries[i].handler, 0, 2375 qla4_8xxx_msix_entries[i].name, ha); 2376 if (ret) { 2377 ql4_printk(KERN_WARNING, ha, 2378 "MSI-X: Unable to register handler -- %x/%d.\n", 2379 qla4_8xxx_msix_entries[i].index, ret); 2380 qla4_8xxx_disable_msix(ha); 2381 goto msix_out; 2382 } 2383 qentry->have_irq = 1; 2384 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 2385 __func__, qla4_8xxx_msix_entries[i].name)); 2386 } 2387 msix_out: 2388 return ret; 2389 } 2390