1f4f5df23SVikas Chaudhary /* 2f4f5df23SVikas Chaudhary * QLogic iSCSI HBA Driver 3f4f5df23SVikas Chaudhary * Copyright (c) 2003-2009 QLogic Corporation 4f4f5df23SVikas Chaudhary * 5f4f5df23SVikas Chaudhary * See LICENSE.qla4xxx for copyright and licensing details. 6f4f5df23SVikas Chaudhary */ 7f4f5df23SVikas Chaudhary #include <linux/delay.h> 8f4f5df23SVikas Chaudhary #include <linux/pci.h> 9f4f5df23SVikas Chaudhary #include "ql4_def.h" 10f4f5df23SVikas Chaudhary #include "ql4_glbl.h" 11f4f5df23SVikas Chaudhary 12f4f5df23SVikas Chaudhary #define MASK(n) DMA_BIT_MASK(n) 13f4f5df23SVikas Chaudhary #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 14f4f5df23SVikas Chaudhary #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 15f4f5df23SVikas Chaudhary #define MS_WIN(addr) (addr & 0x0ffc0000) 16f4f5df23SVikas Chaudhary #define QLA82XX_PCI_MN_2M (0) 17f4f5df23SVikas Chaudhary #define QLA82XX_PCI_MS_2M (0x80000) 18f4f5df23SVikas Chaudhary #define QLA82XX_PCI_OCM0_2M (0xc0000) 19f4f5df23SVikas Chaudhary #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 20f4f5df23SVikas Chaudhary #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 21f4f5df23SVikas Chaudhary 22f4f5df23SVikas Chaudhary /* CRB window related */ 23f4f5df23SVikas Chaudhary #define CRB_BLK(off) ((off >> 20) & 0x3f) 24f4f5df23SVikas Chaudhary #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 25f4f5df23SVikas Chaudhary #define CRB_WINDOW_2M (0x130060) 26f4f5df23SVikas Chaudhary #define CRB_HI(off) ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 27f4f5df23SVikas Chaudhary ((off) & 0xf0000)) 28f4f5df23SVikas Chaudhary #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 29f4f5df23SVikas Chaudhary #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 30f4f5df23SVikas Chaudhary #define CRB_INDIRECT_2M (0x1e0000UL) 31f4f5df23SVikas Chaudhary 32f4f5df23SVikas Chaudhary static inline void __iomem * 33f4f5df23SVikas Chaudhary qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) 34f4f5df23SVikas Chaudhary { 35f4f5df23SVikas Chaudhary if ((off < ha->first_page_group_end) && 36f4f5df23SVikas Chaudhary (off >= ha->first_page_group_start)) 37f4f5df23SVikas Chaudhary return (void __iomem *)(ha->nx_pcibase + off); 38f4f5df23SVikas Chaudhary 39f4f5df23SVikas Chaudhary return NULL; 40f4f5df23SVikas Chaudhary } 41f4f5df23SVikas Chaudhary 42f4f5df23SVikas Chaudhary #define MAX_CRB_XFORM 60 43f4f5df23SVikas Chaudhary static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 44f4f5df23SVikas Chaudhary static int qla4_8xxx_crb_table_initialized; 45f4f5df23SVikas Chaudhary 46f4f5df23SVikas Chaudhary #define qla4_8xxx_crb_addr_transform(name) \ 47f4f5df23SVikas Chaudhary (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 48f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 49f4f5df23SVikas Chaudhary static void 50f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform_setup(void) 51f4f5df23SVikas Chaudhary { 52f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(XDMA); 53f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(TIMR); 54f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SRE); 55f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN3); 56f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN2); 57f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN1); 58f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN0); 59f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS3); 60f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS2); 61f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS1); 62f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS0); 63f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX7); 64f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX6); 65f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX5); 66f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX4); 67f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX3); 68f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX2); 69f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX1); 70f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX0); 71f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(ROMUSB); 72f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SN); 73f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(QMN); 74f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(QMS); 75f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGNI); 76f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGND); 77f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN3); 78f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN2); 79f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN1); 80f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN0); 81f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGSI); 82f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGSD); 83f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS3); 84f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS2); 85f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS1); 86f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS0); 87f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PS); 88f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PH); 89f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(NIU); 90f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(I2Q); 91f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(EG); 92f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(MN); 93f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(MS); 94f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS2); 95f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS1); 96f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS0); 97f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAM); 98f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(C2C1); 99f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(C2C0); 100f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SMB); 101f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(OCM0); 102f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(I2C0); 103f4f5df23SVikas Chaudhary 104f4f5df23SVikas Chaudhary qla4_8xxx_crb_table_initialized = 1; 105f4f5df23SVikas Chaudhary } 106f4f5df23SVikas Chaudhary 107f4f5df23SVikas Chaudhary static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 108f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 0: PCI */ 109f4f5df23SVikas Chaudhary {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 110f4f5df23SVikas Chaudhary {1, 0x0110000, 0x0120000, 0x130000}, 111f4f5df23SVikas Chaudhary {1, 0x0120000, 0x0122000, 0x124000}, 112f4f5df23SVikas Chaudhary {1, 0x0130000, 0x0132000, 0x126000}, 113f4f5df23SVikas Chaudhary {1, 0x0140000, 0x0142000, 0x128000}, 114f4f5df23SVikas Chaudhary {1, 0x0150000, 0x0152000, 0x12a000}, 115f4f5df23SVikas Chaudhary {1, 0x0160000, 0x0170000, 0x110000}, 116f4f5df23SVikas Chaudhary {1, 0x0170000, 0x0172000, 0x12e000}, 117f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 118f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 119f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 120f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 121f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 122f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 123f4f5df23SVikas Chaudhary {1, 0x01e0000, 0x01e0800, 0x122000}, 124f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000} } }, 125f4f5df23SVikas Chaudhary {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 126f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 3: */ 127f4f5df23SVikas Chaudhary {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 128f4f5df23SVikas Chaudhary {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 129f4f5df23SVikas Chaudhary {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 130f4f5df23SVikas Chaudhary {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 131f4f5df23SVikas Chaudhary {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 132f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 133f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 134f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 135f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 136f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 137f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 138f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 139f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 140f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 141f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 142f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 143f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 144f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 145f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 146f4f5df23SVikas Chaudhary {1, 0x08f0000, 0x08f2000, 0x172000} } }, 147f4f5df23SVikas Chaudhary {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 148f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 149f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 150f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 151f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 152f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 153f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 154f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 155f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 156f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 157f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 158f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 159f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 160f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 161f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 162f4f5df23SVikas Chaudhary {1, 0x09f0000, 0x09f2000, 0x176000} } }, 163f4f5df23SVikas Chaudhary {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 164f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 165f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 166f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 167f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 168f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 169f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 170f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 171f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 172f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 173f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 174f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 175f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 176f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 177f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 178f4f5df23SVikas Chaudhary {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 179f4f5df23SVikas Chaudhary {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 180f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 181f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 182f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 183f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 184f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 185f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 186f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 187f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 188f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 189f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 190f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 191f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 192f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 193f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 194f4f5df23SVikas Chaudhary {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 195f4f5df23SVikas Chaudhary {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 196f4f5df23SVikas Chaudhary {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 197f4f5df23SVikas Chaudhary {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 198f4f5df23SVikas Chaudhary {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 199f4f5df23SVikas Chaudhary {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 200f4f5df23SVikas Chaudhary {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 201f4f5df23SVikas Chaudhary {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 202f4f5df23SVikas Chaudhary {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 203f4f5df23SVikas Chaudhary {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 204f4f5df23SVikas Chaudhary {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 205f4f5df23SVikas Chaudhary {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 206f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 23: */ 207f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 24: */ 208f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 25: */ 209f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 26: */ 210f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 27: */ 211f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 28: */ 212f4f5df23SVikas Chaudhary {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 213f4f5df23SVikas Chaudhary {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 214f4f5df23SVikas Chaudhary {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 215f4f5df23SVikas Chaudhary {{{0} } }, /* 32: PCI */ 216f4f5df23SVikas Chaudhary {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 217f4f5df23SVikas Chaudhary {1, 0x2110000, 0x2120000, 0x130000}, 218f4f5df23SVikas Chaudhary {1, 0x2120000, 0x2122000, 0x124000}, 219f4f5df23SVikas Chaudhary {1, 0x2130000, 0x2132000, 0x126000}, 220f4f5df23SVikas Chaudhary {1, 0x2140000, 0x2142000, 0x128000}, 221f4f5df23SVikas Chaudhary {1, 0x2150000, 0x2152000, 0x12a000}, 222f4f5df23SVikas Chaudhary {1, 0x2160000, 0x2170000, 0x110000}, 223f4f5df23SVikas Chaudhary {1, 0x2170000, 0x2172000, 0x12e000}, 224f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 225f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 226f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 227f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 228f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 229f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 230f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 231f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000} } }, 232f4f5df23SVikas Chaudhary {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 233f4f5df23SVikas Chaudhary {{{0} } }, /* 35: */ 234f4f5df23SVikas Chaudhary {{{0} } }, /* 36: */ 235f4f5df23SVikas Chaudhary {{{0} } }, /* 37: */ 236f4f5df23SVikas Chaudhary {{{0} } }, /* 38: */ 237f4f5df23SVikas Chaudhary {{{0} } }, /* 39: */ 238f4f5df23SVikas Chaudhary {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 239f4f5df23SVikas Chaudhary {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 240f4f5df23SVikas Chaudhary {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 241f4f5df23SVikas Chaudhary {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 242f4f5df23SVikas Chaudhary {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 243f4f5df23SVikas Chaudhary {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 244f4f5df23SVikas Chaudhary {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 245f4f5df23SVikas Chaudhary {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 246f4f5df23SVikas Chaudhary {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 247f4f5df23SVikas Chaudhary {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 248f4f5df23SVikas Chaudhary {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 249f4f5df23SVikas Chaudhary {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 250f4f5df23SVikas Chaudhary {{{0} } }, /* 52: */ 251f4f5df23SVikas Chaudhary {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 252f4f5df23SVikas Chaudhary {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 253f4f5df23SVikas Chaudhary {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 254f4f5df23SVikas Chaudhary {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 255f4f5df23SVikas Chaudhary {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 256f4f5df23SVikas Chaudhary {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 257f4f5df23SVikas Chaudhary {{{0} } }, /* 59: I2C0 */ 258f4f5df23SVikas Chaudhary {{{0} } }, /* 60: I2C1 */ 259f4f5df23SVikas Chaudhary {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ 260f4f5df23SVikas Chaudhary {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 261f4f5df23SVikas Chaudhary {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 262f4f5df23SVikas Chaudhary }; 263f4f5df23SVikas Chaudhary 264f4f5df23SVikas Chaudhary /* 265f4f5df23SVikas Chaudhary * top 12 bits of crb internal address (hub, agent) 266f4f5df23SVikas Chaudhary */ 267f4f5df23SVikas Chaudhary static unsigned qla4_8xxx_crb_hub_agt[64] = { 268f4f5df23SVikas Chaudhary 0, 269f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 270f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 271f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 272f4f5df23SVikas Chaudhary 0, 273f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 274f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 275f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 276f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 277f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 278f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 279f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 280f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 281f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 282f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 283f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 284f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 285f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 286f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 287f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 288f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 289f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 290f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 291f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 292f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 293f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 294f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 295f4f5df23SVikas Chaudhary 0, 296f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 297f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 298f4f5df23SVikas Chaudhary 0, 299f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 300f4f5df23SVikas Chaudhary 0, 301f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 302f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 303f4f5df23SVikas Chaudhary 0, 304f4f5df23SVikas Chaudhary 0, 305f4f5df23SVikas Chaudhary 0, 306f4f5df23SVikas Chaudhary 0, 307f4f5df23SVikas Chaudhary 0, 308f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 309f4f5df23SVikas Chaudhary 0, 310f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 311f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 312f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 313f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 314f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 315f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 316f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 317f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 318f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 319f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 320f4f5df23SVikas Chaudhary 0, 321f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 322f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 323f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 324f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 325f4f5df23SVikas Chaudhary 0, 326f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 327f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 328f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 329f4f5df23SVikas Chaudhary 0, 330f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 331f4f5df23SVikas Chaudhary 0, 332f4f5df23SVikas Chaudhary }; 333f4f5df23SVikas Chaudhary 334f4f5df23SVikas Chaudhary /* Device states */ 335f4f5df23SVikas Chaudhary static char *qdev_state[] = { 336f4f5df23SVikas Chaudhary "Unknown", 337f4f5df23SVikas Chaudhary "Cold", 338f4f5df23SVikas Chaudhary "Initializing", 339f4f5df23SVikas Chaudhary "Ready", 340f4f5df23SVikas Chaudhary "Need Reset", 341f4f5df23SVikas Chaudhary "Need Quiescent", 342f4f5df23SVikas Chaudhary "Failed", 343f4f5df23SVikas Chaudhary "Quiescent", 344f4f5df23SVikas Chaudhary }; 345f4f5df23SVikas Chaudhary 346f4f5df23SVikas Chaudhary /* 347f4f5df23SVikas Chaudhary * In: 'off' is offset from CRB space in 128M pci map 348f4f5df23SVikas Chaudhary * Out: 'off' is 2M pci map addr 349f4f5df23SVikas Chaudhary * side effect: lock crb window 350f4f5df23SVikas Chaudhary */ 351f4f5df23SVikas Chaudhary static void 352f4f5df23SVikas Chaudhary qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) 353f4f5df23SVikas Chaudhary { 354f4f5df23SVikas Chaudhary u32 win_read; 355f4f5df23SVikas Chaudhary 356f4f5df23SVikas Chaudhary ha->crb_win = CRB_HI(*off); 357f4f5df23SVikas Chaudhary writel(ha->crb_win, 358f4f5df23SVikas Chaudhary (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 359f4f5df23SVikas Chaudhary 360f4f5df23SVikas Chaudhary /* Read back value to make sure write has gone through before trying 361f4f5df23SVikas Chaudhary * to use it. */ 362f4f5df23SVikas Chaudhary win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363f4f5df23SVikas Chaudhary if (win_read != ha->crb_win) { 364f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 365f4f5df23SVikas Chaudhary "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," 366f4f5df23SVikas Chaudhary " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 367f4f5df23SVikas Chaudhary } 368f4f5df23SVikas Chaudhary *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 369f4f5df23SVikas Chaudhary } 370f4f5df23SVikas Chaudhary 371f4f5df23SVikas Chaudhary void 372f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) 373f4f5df23SVikas Chaudhary { 374f4f5df23SVikas Chaudhary unsigned long flags = 0; 375f4f5df23SVikas Chaudhary int rv; 376f4f5df23SVikas Chaudhary 377f4f5df23SVikas Chaudhary rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off); 378f4f5df23SVikas Chaudhary 379f4f5df23SVikas Chaudhary BUG_ON(rv == -1); 380f4f5df23SVikas Chaudhary 381f4f5df23SVikas Chaudhary if (rv == 1) { 382f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 383f4f5df23SVikas Chaudhary qla4_8xxx_crb_win_lock(ha); 384f4f5df23SVikas Chaudhary qla4_8xxx_pci_set_crbwindow_2M(ha, &off); 385f4f5df23SVikas Chaudhary } 386f4f5df23SVikas Chaudhary 387f4f5df23SVikas Chaudhary writel(data, (void __iomem *)off); 388f4f5df23SVikas Chaudhary 389f4f5df23SVikas Chaudhary if (rv == 1) { 390f4f5df23SVikas Chaudhary qla4_8xxx_crb_win_unlock(ha); 391f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 392f4f5df23SVikas Chaudhary } 393f4f5df23SVikas Chaudhary } 394f4f5df23SVikas Chaudhary 395f4f5df23SVikas Chaudhary int 396f4f5df23SVikas Chaudhary qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off) 397f4f5df23SVikas Chaudhary { 398f4f5df23SVikas Chaudhary unsigned long flags = 0; 399f4f5df23SVikas Chaudhary int rv; 400f4f5df23SVikas Chaudhary u32 data; 401f4f5df23SVikas Chaudhary 402f4f5df23SVikas Chaudhary rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off); 403f4f5df23SVikas Chaudhary 404f4f5df23SVikas Chaudhary BUG_ON(rv == -1); 405f4f5df23SVikas Chaudhary 406f4f5df23SVikas Chaudhary if (rv == 1) { 407f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 408f4f5df23SVikas Chaudhary qla4_8xxx_crb_win_lock(ha); 409f4f5df23SVikas Chaudhary qla4_8xxx_pci_set_crbwindow_2M(ha, &off); 410f4f5df23SVikas Chaudhary } 411f4f5df23SVikas Chaudhary data = readl((void __iomem *)off); 412f4f5df23SVikas Chaudhary 413f4f5df23SVikas Chaudhary if (rv == 1) { 414f4f5df23SVikas Chaudhary qla4_8xxx_crb_win_unlock(ha); 415f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 416f4f5df23SVikas Chaudhary } 417f4f5df23SVikas Chaudhary return data; 418f4f5df23SVikas Chaudhary } 419f4f5df23SVikas Chaudhary 420f4f5df23SVikas Chaudhary #define CRB_WIN_LOCK_TIMEOUT 100000000 421f4f5df23SVikas Chaudhary 422f4f5df23SVikas Chaudhary int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha) 423f4f5df23SVikas Chaudhary { 424f4f5df23SVikas Chaudhary int i; 425f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 426f4f5df23SVikas Chaudhary 427f4f5df23SVikas Chaudhary while (!done) { 428f4f5df23SVikas Chaudhary /* acquire semaphore3 from PCI HW block */ 429f4f5df23SVikas Chaudhary done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 430f4f5df23SVikas Chaudhary if (done == 1) 431f4f5df23SVikas Chaudhary break; 432f4f5df23SVikas Chaudhary if (timeout >= CRB_WIN_LOCK_TIMEOUT) 433f4f5df23SVikas Chaudhary return -1; 434f4f5df23SVikas Chaudhary 435f4f5df23SVikas Chaudhary timeout++; 436f4f5df23SVikas Chaudhary 437f4f5df23SVikas Chaudhary /* Yield CPU */ 438f4f5df23SVikas Chaudhary if (!in_interrupt()) 439f4f5df23SVikas Chaudhary schedule(); 440f4f5df23SVikas Chaudhary else { 441f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 442f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 443f4f5df23SVikas Chaudhary } 444f4f5df23SVikas Chaudhary } 445f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); 446f4f5df23SVikas Chaudhary return 0; 447f4f5df23SVikas Chaudhary } 448f4f5df23SVikas Chaudhary 449f4f5df23SVikas Chaudhary void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha) 450f4f5df23SVikas Chaudhary { 451f4f5df23SVikas Chaudhary qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 452f4f5df23SVikas Chaudhary } 453f4f5df23SVikas Chaudhary 454f4f5df23SVikas Chaudhary #define IDC_LOCK_TIMEOUT 100000000 455f4f5df23SVikas Chaudhary 456f4f5df23SVikas Chaudhary /** 457f4f5df23SVikas Chaudhary * qla4_8xxx_idc_lock - hw_lock 458f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 459f4f5df23SVikas Chaudhary * 460f4f5df23SVikas Chaudhary * General purpose lock used to synchronize access to 461f4f5df23SVikas Chaudhary * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. 462f4f5df23SVikas Chaudhary **/ 463f4f5df23SVikas Chaudhary int qla4_8xxx_idc_lock(struct scsi_qla_host *ha) 464f4f5df23SVikas Chaudhary { 465f4f5df23SVikas Chaudhary int i; 466f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 467f4f5df23SVikas Chaudhary 468f4f5df23SVikas Chaudhary while (!done) { 469f4f5df23SVikas Chaudhary /* acquire semaphore5 from PCI HW block */ 470f4f5df23SVikas Chaudhary done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 471f4f5df23SVikas Chaudhary if (done == 1) 472f4f5df23SVikas Chaudhary break; 473f4f5df23SVikas Chaudhary if (timeout >= IDC_LOCK_TIMEOUT) 474f4f5df23SVikas Chaudhary return -1; 475f4f5df23SVikas Chaudhary 476f4f5df23SVikas Chaudhary timeout++; 477f4f5df23SVikas Chaudhary 478f4f5df23SVikas Chaudhary /* Yield CPU */ 479f4f5df23SVikas Chaudhary if (!in_interrupt()) 480f4f5df23SVikas Chaudhary schedule(); 481f4f5df23SVikas Chaudhary else { 482f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 483f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 484f4f5df23SVikas Chaudhary } 485f4f5df23SVikas Chaudhary } 486f4f5df23SVikas Chaudhary return 0; 487f4f5df23SVikas Chaudhary } 488f4f5df23SVikas Chaudhary 489f4f5df23SVikas Chaudhary void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha) 490f4f5df23SVikas Chaudhary { 491f4f5df23SVikas Chaudhary qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 492f4f5df23SVikas Chaudhary } 493f4f5df23SVikas Chaudhary 494f4f5df23SVikas Chaudhary int 495f4f5df23SVikas Chaudhary qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) 496f4f5df23SVikas Chaudhary { 497f4f5df23SVikas Chaudhary struct crb_128M_2M_sub_block_map *m; 498f4f5df23SVikas Chaudhary 499f4f5df23SVikas Chaudhary if (*off >= QLA82XX_CRB_MAX) 500f4f5df23SVikas Chaudhary return -1; 501f4f5df23SVikas Chaudhary 502f4f5df23SVikas Chaudhary if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 503f4f5df23SVikas Chaudhary *off = (*off - QLA82XX_PCI_CAMQM) + 504f4f5df23SVikas Chaudhary QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 505f4f5df23SVikas Chaudhary return 0; 506f4f5df23SVikas Chaudhary } 507f4f5df23SVikas Chaudhary 508f4f5df23SVikas Chaudhary if (*off < QLA82XX_PCI_CRBSPACE) 509f4f5df23SVikas Chaudhary return -1; 510f4f5df23SVikas Chaudhary 511f4f5df23SVikas Chaudhary *off -= QLA82XX_PCI_CRBSPACE; 512f4f5df23SVikas Chaudhary /* 513f4f5df23SVikas Chaudhary * Try direct map 514f4f5df23SVikas Chaudhary */ 515f4f5df23SVikas Chaudhary 516f4f5df23SVikas Chaudhary m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 517f4f5df23SVikas Chaudhary 518f4f5df23SVikas Chaudhary if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 519f4f5df23SVikas Chaudhary *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 520f4f5df23SVikas Chaudhary return 0; 521f4f5df23SVikas Chaudhary } 522f4f5df23SVikas Chaudhary 523f4f5df23SVikas Chaudhary /* 524f4f5df23SVikas Chaudhary * Not in direct map, use crb window 525f4f5df23SVikas Chaudhary */ 526f4f5df23SVikas Chaudhary return 1; 527f4f5df23SVikas Chaudhary } 528f4f5df23SVikas Chaudhary 529f4f5df23SVikas Chaudhary /* PCI Windowing for DDR regions. */ 530f4f5df23SVikas Chaudhary #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 531f4f5df23SVikas Chaudhary (((addr) <= (high)) && ((addr) >= (low))) 532f4f5df23SVikas Chaudhary 533f4f5df23SVikas Chaudhary /* 534f4f5df23SVikas Chaudhary * check memory access boundary. 535f4f5df23SVikas Chaudhary * used by test agent. support ddr access only for now 536f4f5df23SVikas Chaudhary */ 537f4f5df23SVikas Chaudhary static unsigned long 538f4f5df23SVikas Chaudhary qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha, 539f4f5df23SVikas Chaudhary unsigned long long addr, int size) 540f4f5df23SVikas Chaudhary { 541f4f5df23SVikas Chaudhary if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 542f4f5df23SVikas Chaudhary QLA82XX_ADDR_DDR_NET_MAX) || 543f4f5df23SVikas Chaudhary !QLA82XX_ADDR_IN_RANGE(addr + size - 1, 544f4f5df23SVikas Chaudhary QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) || 545f4f5df23SVikas Chaudhary ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { 546f4f5df23SVikas Chaudhary return 0; 547f4f5df23SVikas Chaudhary } 548f4f5df23SVikas Chaudhary return 1; 549f4f5df23SVikas Chaudhary } 550f4f5df23SVikas Chaudhary 551f4f5df23SVikas Chaudhary static int qla4_8xxx_pci_set_window_warning_count; 552f4f5df23SVikas Chaudhary 553f4f5df23SVikas Chaudhary static unsigned long 554f4f5df23SVikas Chaudhary qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) 555f4f5df23SVikas Chaudhary { 556f4f5df23SVikas Chaudhary int window; 557f4f5df23SVikas Chaudhary u32 win_read; 558f4f5df23SVikas Chaudhary 559f4f5df23SVikas Chaudhary if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 560f4f5df23SVikas Chaudhary QLA82XX_ADDR_DDR_NET_MAX)) { 561f4f5df23SVikas Chaudhary /* DDR network side */ 562f4f5df23SVikas Chaudhary window = MN_WIN(addr); 563f4f5df23SVikas Chaudhary ha->ddr_mn_window = window; 564f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, ha->mn_win_crb | 565f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 566f4f5df23SVikas Chaudhary win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb | 567f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE); 568f4f5df23SVikas Chaudhary if ((win_read << 17) != window) { 569f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 570f4f5df23SVikas Chaudhary "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 571f4f5df23SVikas Chaudhary __func__, window, win_read); 572f4f5df23SVikas Chaudhary } 573f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 574f4f5df23SVikas Chaudhary } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 575f4f5df23SVikas Chaudhary QLA82XX_ADDR_OCM0_MAX)) { 576f4f5df23SVikas Chaudhary unsigned int temp1; 577f4f5df23SVikas Chaudhary /* if bits 19:18&17:11 are on */ 578f4f5df23SVikas Chaudhary if ((addr & 0x00ff800) == 0xff800) { 579f4f5df23SVikas Chaudhary printk("%s: QM access not handled.\n", __func__); 580f4f5df23SVikas Chaudhary addr = -1UL; 581f4f5df23SVikas Chaudhary } 582f4f5df23SVikas Chaudhary 583f4f5df23SVikas Chaudhary window = OCM_WIN(addr); 584f4f5df23SVikas Chaudhary ha->ddr_mn_window = window; 585f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, ha->mn_win_crb | 586f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 587f4f5df23SVikas Chaudhary win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb | 588f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE); 589f4f5df23SVikas Chaudhary temp1 = ((window & 0x1FF) << 7) | 590f4f5df23SVikas Chaudhary ((window & 0x0FFFE0000) >> 17); 591f4f5df23SVikas Chaudhary if (win_read != temp1) { 592f4f5df23SVikas Chaudhary printk("%s: Written OCMwin (0x%x) != Read" 593f4f5df23SVikas Chaudhary " OCMwin (0x%x)\n", __func__, temp1, win_read); 594f4f5df23SVikas Chaudhary } 595f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 596f4f5df23SVikas Chaudhary 597f4f5df23SVikas Chaudhary } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 598f4f5df23SVikas Chaudhary QLA82XX_P3_ADDR_QDR_NET_MAX)) { 599f4f5df23SVikas Chaudhary /* QDR network side */ 600f4f5df23SVikas Chaudhary window = MS_WIN(addr); 601f4f5df23SVikas Chaudhary ha->qdr_sn_window = window; 602f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, ha->ms_win_crb | 603f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 604f4f5df23SVikas Chaudhary win_read = qla4_8xxx_rd_32(ha, 605f4f5df23SVikas Chaudhary ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 606f4f5df23SVikas Chaudhary if (win_read != window) { 607f4f5df23SVikas Chaudhary printk("%s: Written MSwin (0x%x) != Read " 608f4f5df23SVikas Chaudhary "MSwin (0x%x)\n", __func__, window, win_read); 609f4f5df23SVikas Chaudhary } 610f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 611f4f5df23SVikas Chaudhary 612f4f5df23SVikas Chaudhary } else { 613f4f5df23SVikas Chaudhary /* 614f4f5df23SVikas Chaudhary * peg gdb frequently accesses memory that doesn't exist, 615f4f5df23SVikas Chaudhary * this limits the chit chat so debugging isn't slowed down. 616f4f5df23SVikas Chaudhary */ 617f4f5df23SVikas Chaudhary if ((qla4_8xxx_pci_set_window_warning_count++ < 8) || 618f4f5df23SVikas Chaudhary (qla4_8xxx_pci_set_window_warning_count%64 == 0)) { 619f4f5df23SVikas Chaudhary printk("%s: Warning:%s Unknown address range!\n", 620f4f5df23SVikas Chaudhary __func__, DRIVER_NAME); 621f4f5df23SVikas Chaudhary } 622f4f5df23SVikas Chaudhary addr = -1UL; 623f4f5df23SVikas Chaudhary } 624f4f5df23SVikas Chaudhary return addr; 625f4f5df23SVikas Chaudhary } 626f4f5df23SVikas Chaudhary 627f4f5df23SVikas Chaudhary /* check if address is in the same windows as the previous access */ 628f4f5df23SVikas Chaudhary static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha, 629f4f5df23SVikas Chaudhary unsigned long long addr) 630f4f5df23SVikas Chaudhary { 631f4f5df23SVikas Chaudhary int window; 632f4f5df23SVikas Chaudhary unsigned long long qdr_max; 633f4f5df23SVikas Chaudhary 634f4f5df23SVikas Chaudhary qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 635f4f5df23SVikas Chaudhary 636f4f5df23SVikas Chaudhary if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 637f4f5df23SVikas Chaudhary QLA82XX_ADDR_DDR_NET_MAX)) { 638f4f5df23SVikas Chaudhary /* DDR network side */ 639f4f5df23SVikas Chaudhary BUG(); /* MN access can not come here */ 640f4f5df23SVikas Chaudhary } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 641f4f5df23SVikas Chaudhary QLA82XX_ADDR_OCM0_MAX)) { 642f4f5df23SVikas Chaudhary return 1; 643f4f5df23SVikas Chaudhary } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 644f4f5df23SVikas Chaudhary QLA82XX_ADDR_OCM1_MAX)) { 645f4f5df23SVikas Chaudhary return 1; 646f4f5df23SVikas Chaudhary } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 647f4f5df23SVikas Chaudhary qdr_max)) { 648f4f5df23SVikas Chaudhary /* QDR network side */ 649f4f5df23SVikas Chaudhary window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 650f4f5df23SVikas Chaudhary if (ha->qdr_sn_window == window) 651f4f5df23SVikas Chaudhary return 1; 652f4f5df23SVikas Chaudhary } 653f4f5df23SVikas Chaudhary 654f4f5df23SVikas Chaudhary return 0; 655f4f5df23SVikas Chaudhary } 656f4f5df23SVikas Chaudhary 657f4f5df23SVikas Chaudhary static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha, 658f4f5df23SVikas Chaudhary u64 off, void *data, int size) 659f4f5df23SVikas Chaudhary { 660f4f5df23SVikas Chaudhary unsigned long flags; 661f4f5df23SVikas Chaudhary void __iomem *addr; 662f4f5df23SVikas Chaudhary int ret = 0; 663f4f5df23SVikas Chaudhary u64 start; 664f4f5df23SVikas Chaudhary void __iomem *mem_ptr = NULL; 665f4f5df23SVikas Chaudhary unsigned long mem_base; 666f4f5df23SVikas Chaudhary unsigned long mem_page; 667f4f5df23SVikas Chaudhary 668f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 669f4f5df23SVikas Chaudhary 670f4f5df23SVikas Chaudhary /* 671f4f5df23SVikas Chaudhary * If attempting to access unknown address or straddle hw windows, 672f4f5df23SVikas Chaudhary * do not access. 673f4f5df23SVikas Chaudhary */ 674f4f5df23SVikas Chaudhary start = qla4_8xxx_pci_set_window(ha, off); 675f4f5df23SVikas Chaudhary if ((start == -1UL) || 676f4f5df23SVikas Chaudhary (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) { 677f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 678f4f5df23SVikas Chaudhary printk(KERN_ERR"%s out of bound pci memory access. " 679f4f5df23SVikas Chaudhary "offset is 0x%llx\n", DRIVER_NAME, off); 680f4f5df23SVikas Chaudhary return -1; 681f4f5df23SVikas Chaudhary } 682f4f5df23SVikas Chaudhary 683f4f5df23SVikas Chaudhary addr = qla4_8xxx_pci_base_offsetfset(ha, start); 684f4f5df23SVikas Chaudhary if (!addr) { 685f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 686f4f5df23SVikas Chaudhary mem_base = pci_resource_start(ha->pdev, 0); 687f4f5df23SVikas Chaudhary mem_page = start & PAGE_MASK; 688f4f5df23SVikas Chaudhary /* Map two pages whenever user tries to access addresses in two 689f4f5df23SVikas Chaudhary consecutive pages. 690f4f5df23SVikas Chaudhary */ 691f4f5df23SVikas Chaudhary if (mem_page != ((start + size - 1) & PAGE_MASK)) 692f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 693f4f5df23SVikas Chaudhary else 694f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 695f4f5df23SVikas Chaudhary 696f4f5df23SVikas Chaudhary if (mem_ptr == NULL) { 697f4f5df23SVikas Chaudhary *(u8 *)data = 0; 698f4f5df23SVikas Chaudhary return -1; 699f4f5df23SVikas Chaudhary } 700f4f5df23SVikas Chaudhary addr = mem_ptr; 701f4f5df23SVikas Chaudhary addr += start & (PAGE_SIZE - 1); 702f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 703f4f5df23SVikas Chaudhary } 704f4f5df23SVikas Chaudhary 705f4f5df23SVikas Chaudhary switch (size) { 706f4f5df23SVikas Chaudhary case 1: 707f4f5df23SVikas Chaudhary *(u8 *)data = readb(addr); 708f4f5df23SVikas Chaudhary break; 709f4f5df23SVikas Chaudhary case 2: 710f4f5df23SVikas Chaudhary *(u16 *)data = readw(addr); 711f4f5df23SVikas Chaudhary break; 712f4f5df23SVikas Chaudhary case 4: 713f4f5df23SVikas Chaudhary *(u32 *)data = readl(addr); 714f4f5df23SVikas Chaudhary break; 715f4f5df23SVikas Chaudhary case 8: 716f4f5df23SVikas Chaudhary *(u64 *)data = readq(addr); 717f4f5df23SVikas Chaudhary break; 718f4f5df23SVikas Chaudhary default: 719f4f5df23SVikas Chaudhary ret = -1; 720f4f5df23SVikas Chaudhary break; 721f4f5df23SVikas Chaudhary } 722f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 723f4f5df23SVikas Chaudhary 724f4f5df23SVikas Chaudhary if (mem_ptr) 725f4f5df23SVikas Chaudhary iounmap(mem_ptr); 726f4f5df23SVikas Chaudhary return ret; 727f4f5df23SVikas Chaudhary } 728f4f5df23SVikas Chaudhary 729f4f5df23SVikas Chaudhary static int 730f4f5df23SVikas Chaudhary qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, 731f4f5df23SVikas Chaudhary void *data, int size) 732f4f5df23SVikas Chaudhary { 733f4f5df23SVikas Chaudhary unsigned long flags; 734f4f5df23SVikas Chaudhary void __iomem *addr; 735f4f5df23SVikas Chaudhary int ret = 0; 736f4f5df23SVikas Chaudhary u64 start; 737f4f5df23SVikas Chaudhary void __iomem *mem_ptr = NULL; 738f4f5df23SVikas Chaudhary unsigned long mem_base; 739f4f5df23SVikas Chaudhary unsigned long mem_page; 740f4f5df23SVikas Chaudhary 741f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 742f4f5df23SVikas Chaudhary 743f4f5df23SVikas Chaudhary /* 744f4f5df23SVikas Chaudhary * If attempting to access unknown address or straddle hw windows, 745f4f5df23SVikas Chaudhary * do not access. 746f4f5df23SVikas Chaudhary */ 747f4f5df23SVikas Chaudhary start = qla4_8xxx_pci_set_window(ha, off); 748f4f5df23SVikas Chaudhary if ((start == -1UL) || 749f4f5df23SVikas Chaudhary (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) { 750f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 751f4f5df23SVikas Chaudhary printk(KERN_ERR"%s out of bound pci memory access. " 752f4f5df23SVikas Chaudhary "offset is 0x%llx\n", DRIVER_NAME, off); 753f4f5df23SVikas Chaudhary return -1; 754f4f5df23SVikas Chaudhary } 755f4f5df23SVikas Chaudhary 756f4f5df23SVikas Chaudhary addr = qla4_8xxx_pci_base_offsetfset(ha, start); 757f4f5df23SVikas Chaudhary if (!addr) { 758f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 759f4f5df23SVikas Chaudhary mem_base = pci_resource_start(ha->pdev, 0); 760f4f5df23SVikas Chaudhary mem_page = start & PAGE_MASK; 761f4f5df23SVikas Chaudhary /* Map two pages whenever user tries to access addresses in two 762f4f5df23SVikas Chaudhary consecutive pages. 763f4f5df23SVikas Chaudhary */ 764f4f5df23SVikas Chaudhary if (mem_page != ((start + size - 1) & PAGE_MASK)) 765f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 766f4f5df23SVikas Chaudhary else 767f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 768f4f5df23SVikas Chaudhary if (mem_ptr == NULL) 769f4f5df23SVikas Chaudhary return -1; 770f4f5df23SVikas Chaudhary 771f4f5df23SVikas Chaudhary addr = mem_ptr; 772f4f5df23SVikas Chaudhary addr += start & (PAGE_SIZE - 1); 773f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 774f4f5df23SVikas Chaudhary } 775f4f5df23SVikas Chaudhary 776f4f5df23SVikas Chaudhary switch (size) { 777f4f5df23SVikas Chaudhary case 1: 778f4f5df23SVikas Chaudhary writeb(*(u8 *)data, addr); 779f4f5df23SVikas Chaudhary break; 780f4f5df23SVikas Chaudhary case 2: 781f4f5df23SVikas Chaudhary writew(*(u16 *)data, addr); 782f4f5df23SVikas Chaudhary break; 783f4f5df23SVikas Chaudhary case 4: 784f4f5df23SVikas Chaudhary writel(*(u32 *)data, addr); 785f4f5df23SVikas Chaudhary break; 786f4f5df23SVikas Chaudhary case 8: 787f4f5df23SVikas Chaudhary writeq(*(u64 *)data, addr); 788f4f5df23SVikas Chaudhary break; 789f4f5df23SVikas Chaudhary default: 790f4f5df23SVikas Chaudhary ret = -1; 791f4f5df23SVikas Chaudhary break; 792f4f5df23SVikas Chaudhary } 793f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 794f4f5df23SVikas Chaudhary if (mem_ptr) 795f4f5df23SVikas Chaudhary iounmap(mem_ptr); 796f4f5df23SVikas Chaudhary return ret; 797f4f5df23SVikas Chaudhary } 798f4f5df23SVikas Chaudhary 799f4f5df23SVikas Chaudhary #define MTU_FUDGE_FACTOR 100 800f4f5df23SVikas Chaudhary 801f4f5df23SVikas Chaudhary static unsigned long 802f4f5df23SVikas Chaudhary qla4_8xxx_decode_crb_addr(unsigned long addr) 803f4f5df23SVikas Chaudhary { 804f4f5df23SVikas Chaudhary int i; 805f4f5df23SVikas Chaudhary unsigned long base_addr, offset, pci_base; 806f4f5df23SVikas Chaudhary 807f4f5df23SVikas Chaudhary if (!qla4_8xxx_crb_table_initialized) 808f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform_setup(); 809f4f5df23SVikas Chaudhary 810f4f5df23SVikas Chaudhary pci_base = ADDR_ERROR; 811f4f5df23SVikas Chaudhary base_addr = addr & 0xfff00000; 812f4f5df23SVikas Chaudhary offset = addr & 0x000fffff; 813f4f5df23SVikas Chaudhary 814f4f5df23SVikas Chaudhary for (i = 0; i < MAX_CRB_XFORM; i++) { 815f4f5df23SVikas Chaudhary if (crb_addr_xform[i] == base_addr) { 816f4f5df23SVikas Chaudhary pci_base = i << 20; 817f4f5df23SVikas Chaudhary break; 818f4f5df23SVikas Chaudhary } 819f4f5df23SVikas Chaudhary } 820f4f5df23SVikas Chaudhary if (pci_base == ADDR_ERROR) 821f4f5df23SVikas Chaudhary return pci_base; 822f4f5df23SVikas Chaudhary else 823f4f5df23SVikas Chaudhary return pci_base + offset; 824f4f5df23SVikas Chaudhary } 825f4f5df23SVikas Chaudhary 826f4f5df23SVikas Chaudhary static long rom_max_timeout = 100; 827f4f5df23SVikas Chaudhary static long qla4_8xxx_rom_lock_timeout = 100; 828f4f5df23SVikas Chaudhary 829f4f5df23SVikas Chaudhary static int 830f4f5df23SVikas Chaudhary qla4_8xxx_rom_lock(struct scsi_qla_host *ha) 831f4f5df23SVikas Chaudhary { 832f4f5df23SVikas Chaudhary int i; 833f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 834f4f5df23SVikas Chaudhary 835f4f5df23SVikas Chaudhary while (!done) { 836f4f5df23SVikas Chaudhary /* acquire semaphore2 from PCI HW block */ 837f4f5df23SVikas Chaudhary 838f4f5df23SVikas Chaudhary done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 839f4f5df23SVikas Chaudhary if (done == 1) 840f4f5df23SVikas Chaudhary break; 841f4f5df23SVikas Chaudhary if (timeout >= qla4_8xxx_rom_lock_timeout) 842f4f5df23SVikas Chaudhary return -1; 843f4f5df23SVikas Chaudhary 844f4f5df23SVikas Chaudhary timeout++; 845f4f5df23SVikas Chaudhary 846f4f5df23SVikas Chaudhary /* Yield CPU */ 847f4f5df23SVikas Chaudhary if (!in_interrupt()) 848f4f5df23SVikas Chaudhary schedule(); 849f4f5df23SVikas Chaudhary else { 850f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 851f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 852f4f5df23SVikas Chaudhary } 853f4f5df23SVikas Chaudhary } 854f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 855f4f5df23SVikas Chaudhary return 0; 856f4f5df23SVikas Chaudhary } 857f4f5df23SVikas Chaudhary 858f4f5df23SVikas Chaudhary static void 859f4f5df23SVikas Chaudhary qla4_8xxx_rom_unlock(struct scsi_qla_host *ha) 860f4f5df23SVikas Chaudhary { 861f4f5df23SVikas Chaudhary qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 862f4f5df23SVikas Chaudhary } 863f4f5df23SVikas Chaudhary 864f4f5df23SVikas Chaudhary static int 865f4f5df23SVikas Chaudhary qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha) 866f4f5df23SVikas Chaudhary { 867f4f5df23SVikas Chaudhary long timeout = 0; 868f4f5df23SVikas Chaudhary long done = 0 ; 869f4f5df23SVikas Chaudhary 870f4f5df23SVikas Chaudhary while (done == 0) { 871f4f5df23SVikas Chaudhary done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 872f4f5df23SVikas Chaudhary done &= 2; 873f4f5df23SVikas Chaudhary timeout++; 874f4f5df23SVikas Chaudhary if (timeout >= rom_max_timeout) { 875f4f5df23SVikas Chaudhary printk("%s: Timeout reached waiting for rom done", 876f4f5df23SVikas Chaudhary DRIVER_NAME); 877f4f5df23SVikas Chaudhary return -1; 878f4f5df23SVikas Chaudhary } 879f4f5df23SVikas Chaudhary } 880f4f5df23SVikas Chaudhary return 0; 881f4f5df23SVikas Chaudhary } 882f4f5df23SVikas Chaudhary 883f4f5df23SVikas Chaudhary static int 884f4f5df23SVikas Chaudhary qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 885f4f5df23SVikas Chaudhary { 886f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 887f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 888f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 889f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 890f4f5df23SVikas Chaudhary if (qla4_8xxx_wait_rom_done(ha)) { 891f4f5df23SVikas Chaudhary printk("%s: Error waiting for rom done\n", DRIVER_NAME); 892f4f5df23SVikas Chaudhary return -1; 893f4f5df23SVikas Chaudhary } 894f4f5df23SVikas Chaudhary /* reset abyte_cnt and dummy_byte_cnt */ 895f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 896f4f5df23SVikas Chaudhary udelay(10); 897f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 898f4f5df23SVikas Chaudhary 899f4f5df23SVikas Chaudhary *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 900f4f5df23SVikas Chaudhary return 0; 901f4f5df23SVikas Chaudhary } 902f4f5df23SVikas Chaudhary 903f4f5df23SVikas Chaudhary static int 904f4f5df23SVikas Chaudhary qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 905f4f5df23SVikas Chaudhary { 906f4f5df23SVikas Chaudhary int ret, loops = 0; 907f4f5df23SVikas Chaudhary 908f4f5df23SVikas Chaudhary while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) { 909f4f5df23SVikas Chaudhary udelay(100); 910f4f5df23SVikas Chaudhary loops++; 911f4f5df23SVikas Chaudhary } 912f4f5df23SVikas Chaudhary if (loops >= 50000) { 913f4f5df23SVikas Chaudhary printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME); 914f4f5df23SVikas Chaudhary return -1; 915f4f5df23SVikas Chaudhary } 916f4f5df23SVikas Chaudhary ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp); 917f4f5df23SVikas Chaudhary qla4_8xxx_rom_unlock(ha); 918f4f5df23SVikas Chaudhary return ret; 919f4f5df23SVikas Chaudhary } 920f4f5df23SVikas Chaudhary 921f4f5df23SVikas Chaudhary /** 922f4f5df23SVikas Chaudhary * This routine does CRB initialize sequence 923f4f5df23SVikas Chaudhary * to put the ISP into operational state 924f4f5df23SVikas Chaudhary **/ 925f4f5df23SVikas Chaudhary static int 926f4f5df23SVikas Chaudhary qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) 927f4f5df23SVikas Chaudhary { 928f4f5df23SVikas Chaudhary int addr, val; 929f4f5df23SVikas Chaudhary int i ; 930f4f5df23SVikas Chaudhary struct crb_addr_pair *buf; 931f4f5df23SVikas Chaudhary unsigned long off; 932f4f5df23SVikas Chaudhary unsigned offset, n; 933f4f5df23SVikas Chaudhary 934f4f5df23SVikas Chaudhary struct crb_addr_pair { 935f4f5df23SVikas Chaudhary long addr; 936f4f5df23SVikas Chaudhary long data; 937f4f5df23SVikas Chaudhary }; 938f4f5df23SVikas Chaudhary 939f4f5df23SVikas Chaudhary /* Halt all the indiviual PEGs and other blocks of the ISP */ 940f4f5df23SVikas Chaudhary qla4_8xxx_rom_lock(ha); 941f4f5df23SVikas Chaudhary if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 942f4f5df23SVikas Chaudhary /* don't reset CAM block on reset */ 943f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 944f4f5df23SVikas Chaudhary else 945f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 946f4f5df23SVikas Chaudhary 947f4f5df23SVikas Chaudhary qla4_8xxx_rom_unlock(ha); 948f4f5df23SVikas Chaudhary 949f4f5df23SVikas Chaudhary /* Read the signature value from the flash. 950f4f5df23SVikas Chaudhary * Offset 0: Contain signature (0xcafecafe) 951f4f5df23SVikas Chaudhary * Offset 4: Offset and number of addr/value pairs 952f4f5df23SVikas Chaudhary * that present in CRB initialize sequence 953f4f5df23SVikas Chaudhary */ 954f4f5df23SVikas Chaudhary if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 955f4f5df23SVikas Chaudhary qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) { 956f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 957f4f5df23SVikas Chaudhary "[ERROR] Reading crb_init area: n: %08x\n", n); 958f4f5df23SVikas Chaudhary return -1; 959f4f5df23SVikas Chaudhary } 960f4f5df23SVikas Chaudhary 961f4f5df23SVikas Chaudhary /* Offset in flash = lower 16 bits 962f4f5df23SVikas Chaudhary * Number of enteries = upper 16 bits 963f4f5df23SVikas Chaudhary */ 964f4f5df23SVikas Chaudhary offset = n & 0xffffU; 965f4f5df23SVikas Chaudhary n = (n >> 16) & 0xffffU; 966f4f5df23SVikas Chaudhary 967f4f5df23SVikas Chaudhary /* number of addr/value pair should not exceed 1024 enteries */ 968f4f5df23SVikas Chaudhary if (n >= 1024) { 969f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 970f4f5df23SVikas Chaudhary "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 971f4f5df23SVikas Chaudhary DRIVER_NAME, __func__, n); 972f4f5df23SVikas Chaudhary return -1; 973f4f5df23SVikas Chaudhary } 974f4f5df23SVikas Chaudhary 975f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 976f4f5df23SVikas Chaudhary "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); 977f4f5df23SVikas Chaudhary 978f4f5df23SVikas Chaudhary buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 979f4f5df23SVikas Chaudhary if (buf == NULL) { 980f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 981f4f5df23SVikas Chaudhary "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); 982f4f5df23SVikas Chaudhary return -1; 983f4f5df23SVikas Chaudhary } 984f4f5df23SVikas Chaudhary 985f4f5df23SVikas Chaudhary for (i = 0; i < n; i++) { 986f4f5df23SVikas Chaudhary if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 987f4f5df23SVikas Chaudhary qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 988f4f5df23SVikas Chaudhary 0) { 989f4f5df23SVikas Chaudhary kfree(buf); 990f4f5df23SVikas Chaudhary return -1; 991f4f5df23SVikas Chaudhary } 992f4f5df23SVikas Chaudhary 993f4f5df23SVikas Chaudhary buf[i].addr = addr; 994f4f5df23SVikas Chaudhary buf[i].data = val; 995f4f5df23SVikas Chaudhary } 996f4f5df23SVikas Chaudhary 997f4f5df23SVikas Chaudhary for (i = 0; i < n; i++) { 998f4f5df23SVikas Chaudhary /* Translate internal CRB initialization 999f4f5df23SVikas Chaudhary * address to PCI bus address 1000f4f5df23SVikas Chaudhary */ 1001f4f5df23SVikas Chaudhary off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) + 1002f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE; 1003f4f5df23SVikas Chaudhary /* Not all CRB addr/value pair to be written, 1004f4f5df23SVikas Chaudhary * some of them are skipped 1005f4f5df23SVikas Chaudhary */ 1006f4f5df23SVikas Chaudhary 1007f4f5df23SVikas Chaudhary /* skip if LS bit is set*/ 1008f4f5df23SVikas Chaudhary if (off & 0x1) { 1009f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_WARNING, ha, 1010f4f5df23SVikas Chaudhary "Skip CRB init replay for offset = 0x%lx\n", off)); 1011f4f5df23SVikas Chaudhary continue; 1012f4f5df23SVikas Chaudhary } 1013f4f5df23SVikas Chaudhary 1014f4f5df23SVikas Chaudhary /* skipping cold reboot MAGIC */ 1015f4f5df23SVikas Chaudhary if (off == QLA82XX_CAM_RAM(0x1fc)) 1016f4f5df23SVikas Chaudhary continue; 1017f4f5df23SVikas Chaudhary 1018f4f5df23SVikas Chaudhary /* do not reset PCI */ 1019f4f5df23SVikas Chaudhary if (off == (ROMUSB_GLB + 0xbc)) 1020f4f5df23SVikas Chaudhary continue; 1021f4f5df23SVikas Chaudhary 1022f4f5df23SVikas Chaudhary /* skip core clock, so that firmware can increase the clock */ 1023f4f5df23SVikas Chaudhary if (off == (ROMUSB_GLB + 0xc8)) 1024f4f5df23SVikas Chaudhary continue; 1025f4f5df23SVikas Chaudhary 1026f4f5df23SVikas Chaudhary /* skip the function enable register */ 1027f4f5df23SVikas Chaudhary if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1028f4f5df23SVikas Chaudhary continue; 1029f4f5df23SVikas Chaudhary 1030f4f5df23SVikas Chaudhary if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1031f4f5df23SVikas Chaudhary continue; 1032f4f5df23SVikas Chaudhary 1033f4f5df23SVikas Chaudhary if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1034f4f5df23SVikas Chaudhary continue; 1035f4f5df23SVikas Chaudhary 1036f4f5df23SVikas Chaudhary if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1037f4f5df23SVikas Chaudhary continue; 1038f4f5df23SVikas Chaudhary 1039f4f5df23SVikas Chaudhary if (off == ADDR_ERROR) { 1040f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1041f4f5df23SVikas Chaudhary "%s: [ERROR] Unknown addr: 0x%08lx\n", 1042f4f5df23SVikas Chaudhary DRIVER_NAME, buf[i].addr); 1043f4f5df23SVikas Chaudhary continue; 1044f4f5df23SVikas Chaudhary } 1045f4f5df23SVikas Chaudhary 1046f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, off, buf[i].data); 1047f4f5df23SVikas Chaudhary 1048f4f5df23SVikas Chaudhary /* ISP requires much bigger delay to settle down, 1049f4f5df23SVikas Chaudhary * else crb_window returns 0xffffffff 1050f4f5df23SVikas Chaudhary */ 1051f4f5df23SVikas Chaudhary if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1052f4f5df23SVikas Chaudhary msleep(1000); 1053f4f5df23SVikas Chaudhary 1054f4f5df23SVikas Chaudhary /* ISP requires millisec delay between 1055f4f5df23SVikas Chaudhary * successive CRB register updation 1056f4f5df23SVikas Chaudhary */ 1057f4f5df23SVikas Chaudhary msleep(1); 1058f4f5df23SVikas Chaudhary } 1059f4f5df23SVikas Chaudhary 1060f4f5df23SVikas Chaudhary kfree(buf); 1061f4f5df23SVikas Chaudhary 1062f4f5df23SVikas Chaudhary /* Resetting the data and instruction cache */ 1063f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1064f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1065f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1066f4f5df23SVikas Chaudhary 1067f4f5df23SVikas Chaudhary /* Clear all protocol processing engines */ 1068f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1069f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1070f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1071f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1072f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1073f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1074f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1075f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1076f4f5df23SVikas Chaudhary 1077f4f5df23SVikas Chaudhary return 0; 1078f4f5df23SVikas Chaudhary } 1079f4f5df23SVikas Chaudhary 1080f4f5df23SVikas Chaudhary static int qla4_8xxx_check_for_bad_spd(struct scsi_qla_host *ha) 1081f4f5df23SVikas Chaudhary { 1082f4f5df23SVikas Chaudhary u32 val = 0; 1083f4f5df23SVikas Chaudhary val = qla4_8xxx_rd_32(ha, BOOT_LOADER_DIMM_STATUS) ; 1084f4f5df23SVikas Chaudhary val &= QLA82XX_BOOT_LOADER_MN_ISSUE; 1085f4f5df23SVikas Chaudhary if (val & QLA82XX_PEG_TUNE_MN_SPD_ZEROED) { 1086f4f5df23SVikas Chaudhary printk("Memory DIMM SPD not programmed. Assumed valid.\n"); 1087f4f5df23SVikas Chaudhary return 1; 1088f4f5df23SVikas Chaudhary } else if (val) { 1089f4f5df23SVikas Chaudhary printk("Memory DIMM type incorrect. Info:%08X.\n", val); 1090f4f5df23SVikas Chaudhary return 2; 1091f4f5df23SVikas Chaudhary } 1092f4f5df23SVikas Chaudhary return 0; 1093f4f5df23SVikas Chaudhary } 1094f4f5df23SVikas Chaudhary 1095f4f5df23SVikas Chaudhary static int 1096f4f5df23SVikas Chaudhary qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) 1097f4f5df23SVikas Chaudhary { 1098f4f5df23SVikas Chaudhary int i; 1099f4f5df23SVikas Chaudhary long size = 0; 1100f4f5df23SVikas Chaudhary long flashaddr, memaddr; 1101f4f5df23SVikas Chaudhary u64 data; 1102f4f5df23SVikas Chaudhary u32 high, low; 1103f4f5df23SVikas Chaudhary 1104f4f5df23SVikas Chaudhary flashaddr = memaddr = ha->hw.flt_region_bootload; 1105f4f5df23SVikas Chaudhary size = (image_start - flashaddr)/8; 1106f4f5df23SVikas Chaudhary 1107f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", 1108f4f5df23SVikas Chaudhary ha->host_no, __func__, flashaddr, image_start)); 1109f4f5df23SVikas Chaudhary 1110f4f5df23SVikas Chaudhary for (i = 0; i < size; i++) { 1111f4f5df23SVikas Chaudhary if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1112f4f5df23SVikas Chaudhary (qla4_8xxx_rom_fast_read(ha, flashaddr + 4, 1113f4f5df23SVikas Chaudhary (int *)&high))) { 1114f4f5df23SVikas Chaudhary return -1; 1115f4f5df23SVikas Chaudhary } 1116f4f5df23SVikas Chaudhary data = ((u64)high << 32) | low ; 1117f4f5df23SVikas Chaudhary qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8); 1118f4f5df23SVikas Chaudhary flashaddr += 8; 1119f4f5df23SVikas Chaudhary memaddr += 8; 1120f4f5df23SVikas Chaudhary 1121f4f5df23SVikas Chaudhary if (i%0x1000 == 0) 1122f4f5df23SVikas Chaudhary msleep(1); 1123f4f5df23SVikas Chaudhary 1124f4f5df23SVikas Chaudhary } 1125f4f5df23SVikas Chaudhary 1126f4f5df23SVikas Chaudhary udelay(100); 1127f4f5df23SVikas Chaudhary 1128f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1129f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1130f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1131f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1132f4f5df23SVikas Chaudhary 1133f4f5df23SVikas Chaudhary return 0; 1134f4f5df23SVikas Chaudhary } 1135f4f5df23SVikas Chaudhary 1136f4f5df23SVikas Chaudhary static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) 1137f4f5df23SVikas Chaudhary { 1138f4f5df23SVikas Chaudhary u32 rst; 1139f4f5df23SVikas Chaudhary 1140f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1141f4f5df23SVikas Chaudhary if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { 1142f4f5df23SVikas Chaudhary printk(KERN_WARNING "%s: Error during CRB Initialization\n", 1143f4f5df23SVikas Chaudhary __func__); 1144f4f5df23SVikas Chaudhary return QLA_ERROR; 1145f4f5df23SVikas Chaudhary } 1146f4f5df23SVikas Chaudhary 1147f4f5df23SVikas Chaudhary udelay(500); 1148f4f5df23SVikas Chaudhary 1149f4f5df23SVikas Chaudhary /* at this point, QM is in reset. This could be a problem if there are 1150f4f5df23SVikas Chaudhary * incoming d* transition queue messages. QM/PCIE could wedge. 1151f4f5df23SVikas Chaudhary * To get around this, QM is brought out of reset. 1152f4f5df23SVikas Chaudhary */ 1153f4f5df23SVikas Chaudhary 1154f4f5df23SVikas Chaudhary rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 1155f4f5df23SVikas Chaudhary /* unreset qm */ 1156f4f5df23SVikas Chaudhary rst &= ~(1 << 28); 1157f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 1158f4f5df23SVikas Chaudhary 1159f4f5df23SVikas Chaudhary if (qla4_8xxx_load_from_flash(ha, image_start)) { 1160f4f5df23SVikas Chaudhary printk("%s: Error trying to load fw from flash!\n", __func__); 1161f4f5df23SVikas Chaudhary return QLA_ERROR; 1162f4f5df23SVikas Chaudhary } 1163f4f5df23SVikas Chaudhary 1164f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1165f4f5df23SVikas Chaudhary } 1166f4f5df23SVikas Chaudhary 1167f4f5df23SVikas Chaudhary int 1168f4f5df23SVikas Chaudhary qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha, 1169f4f5df23SVikas Chaudhary u64 off, void *data, int size) 1170f4f5df23SVikas Chaudhary { 1171f4f5df23SVikas Chaudhary int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1172f4f5df23SVikas Chaudhary int shift_amount; 1173f4f5df23SVikas Chaudhary uint32_t temp; 1174f4f5df23SVikas Chaudhary uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1175f4f5df23SVikas Chaudhary 1176f4f5df23SVikas Chaudhary /* 1177f4f5df23SVikas Chaudhary * If not MN, go check for MS or invalid. 1178f4f5df23SVikas Chaudhary */ 1179f4f5df23SVikas Chaudhary 1180f4f5df23SVikas Chaudhary if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1181f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_QDR_NET; 1182f4f5df23SVikas Chaudhary else { 1183f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_DDR_NET; 1184f4f5df23SVikas Chaudhary if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0) 1185f4f5df23SVikas Chaudhary return qla4_8xxx_pci_mem_read_direct(ha, 1186f4f5df23SVikas Chaudhary off, data, size); 1187f4f5df23SVikas Chaudhary } 1188f4f5df23SVikas Chaudhary 1189f4f5df23SVikas Chaudhary 1190f4f5df23SVikas Chaudhary off8 = off & 0xfffffff0; 1191f4f5df23SVikas Chaudhary off0[0] = off & 0xf; 1192f4f5df23SVikas Chaudhary sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1193f4f5df23SVikas Chaudhary shift_amount = 4; 1194f4f5df23SVikas Chaudhary 1195f4f5df23SVikas Chaudhary loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1196f4f5df23SVikas Chaudhary off0[1] = 0; 1197f4f5df23SVikas Chaudhary sz[1] = size - sz[0]; 1198f4f5df23SVikas Chaudhary 1199f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1200f4f5df23SVikas Chaudhary temp = off8 + (i << shift_amount); 1201f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1202f4f5df23SVikas Chaudhary temp = 0; 1203f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1204f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_ENABLE; 1205f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1206f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1207f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1208f4f5df23SVikas Chaudhary 1209f4f5df23SVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1210f4f5df23SVikas Chaudhary temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1211f4f5df23SVikas Chaudhary if ((temp & MIU_TA_CTL_BUSY) == 0) 1212f4f5df23SVikas Chaudhary break; 1213f4f5df23SVikas Chaudhary } 1214f4f5df23SVikas Chaudhary 1215f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1216f4f5df23SVikas Chaudhary if (printk_ratelimit()) 1217f4f5df23SVikas Chaudhary ql4_printk(KERN_ERR, ha, 1218f4f5df23SVikas Chaudhary "failed to read through agent\n"); 1219f4f5df23SVikas Chaudhary break; 1220f4f5df23SVikas Chaudhary } 1221f4f5df23SVikas Chaudhary 1222f4f5df23SVikas Chaudhary start = off0[i] >> 2; 1223f4f5df23SVikas Chaudhary end = (off0[i] + sz[i] - 1) >> 2; 1224f4f5df23SVikas Chaudhary for (k = start; k <= end; k++) { 1225f4f5df23SVikas Chaudhary temp = qla4_8xxx_rd_32(ha, 1226f4f5df23SVikas Chaudhary mem_crb + MIU_TEST_AGT_RDDATA(k)); 1227f4f5df23SVikas Chaudhary word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1228f4f5df23SVikas Chaudhary } 1229f4f5df23SVikas Chaudhary } 1230f4f5df23SVikas Chaudhary 1231f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) 1232f4f5df23SVikas Chaudhary return -1; 1233f4f5df23SVikas Chaudhary 1234f4f5df23SVikas Chaudhary if ((off0[0] & 7) == 0) { 1235f4f5df23SVikas Chaudhary val = word[0]; 1236f4f5df23SVikas Chaudhary } else { 1237f4f5df23SVikas Chaudhary val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1238f4f5df23SVikas Chaudhary ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1239f4f5df23SVikas Chaudhary } 1240f4f5df23SVikas Chaudhary 1241f4f5df23SVikas Chaudhary switch (size) { 1242f4f5df23SVikas Chaudhary case 1: 1243f4f5df23SVikas Chaudhary *(uint8_t *)data = val; 1244f4f5df23SVikas Chaudhary break; 1245f4f5df23SVikas Chaudhary case 2: 1246f4f5df23SVikas Chaudhary *(uint16_t *)data = val; 1247f4f5df23SVikas Chaudhary break; 1248f4f5df23SVikas Chaudhary case 4: 1249f4f5df23SVikas Chaudhary *(uint32_t *)data = val; 1250f4f5df23SVikas Chaudhary break; 1251f4f5df23SVikas Chaudhary case 8: 1252f4f5df23SVikas Chaudhary *(uint64_t *)data = val; 1253f4f5df23SVikas Chaudhary break; 1254f4f5df23SVikas Chaudhary } 1255f4f5df23SVikas Chaudhary return 0; 1256f4f5df23SVikas Chaudhary } 1257f4f5df23SVikas Chaudhary 1258f4f5df23SVikas Chaudhary int 1259f4f5df23SVikas Chaudhary qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha, 1260f4f5df23SVikas Chaudhary u64 off, void *data, int size) 1261f4f5df23SVikas Chaudhary { 1262f4f5df23SVikas Chaudhary int i, j, ret = 0, loop, sz[2], off0; 1263f4f5df23SVikas Chaudhary int scale, shift_amount, startword; 1264f4f5df23SVikas Chaudhary uint32_t temp; 1265f4f5df23SVikas Chaudhary uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1266f4f5df23SVikas Chaudhary 1267f4f5df23SVikas Chaudhary /* 1268f4f5df23SVikas Chaudhary * If not MN, go check for MS or invalid. 1269f4f5df23SVikas Chaudhary */ 1270f4f5df23SVikas Chaudhary if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1271f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_QDR_NET; 1272f4f5df23SVikas Chaudhary else { 1273f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_DDR_NET; 1274f4f5df23SVikas Chaudhary if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0) 1275f4f5df23SVikas Chaudhary return qla4_8xxx_pci_mem_write_direct(ha, 1276f4f5df23SVikas Chaudhary off, data, size); 1277f4f5df23SVikas Chaudhary } 1278f4f5df23SVikas Chaudhary 1279f4f5df23SVikas Chaudhary off0 = off & 0x7; 1280f4f5df23SVikas Chaudhary sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1281f4f5df23SVikas Chaudhary sz[1] = size - sz[0]; 1282f4f5df23SVikas Chaudhary 1283f4f5df23SVikas Chaudhary off8 = off & 0xfffffff0; 1284f4f5df23SVikas Chaudhary loop = (((off & 0xf) + size - 1) >> 4) + 1; 1285f4f5df23SVikas Chaudhary shift_amount = 4; 1286f4f5df23SVikas Chaudhary scale = 2; 1287f4f5df23SVikas Chaudhary startword = (off & 0xf)/8; 1288f4f5df23SVikas Chaudhary 1289f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1290f4f5df23SVikas Chaudhary if (qla4_8xxx_pci_mem_read_2M(ha, off8 + 1291f4f5df23SVikas Chaudhary (i << shift_amount), &word[i * scale], 8)) 1292f4f5df23SVikas Chaudhary return -1; 1293f4f5df23SVikas Chaudhary } 1294f4f5df23SVikas Chaudhary 1295f4f5df23SVikas Chaudhary switch (size) { 1296f4f5df23SVikas Chaudhary case 1: 1297f4f5df23SVikas Chaudhary tmpw = *((uint8_t *)data); 1298f4f5df23SVikas Chaudhary break; 1299f4f5df23SVikas Chaudhary case 2: 1300f4f5df23SVikas Chaudhary tmpw = *((uint16_t *)data); 1301f4f5df23SVikas Chaudhary break; 1302f4f5df23SVikas Chaudhary case 4: 1303f4f5df23SVikas Chaudhary tmpw = *((uint32_t *)data); 1304f4f5df23SVikas Chaudhary break; 1305f4f5df23SVikas Chaudhary case 8: 1306f4f5df23SVikas Chaudhary default: 1307f4f5df23SVikas Chaudhary tmpw = *((uint64_t *)data); 1308f4f5df23SVikas Chaudhary break; 1309f4f5df23SVikas Chaudhary } 1310f4f5df23SVikas Chaudhary 1311f4f5df23SVikas Chaudhary if (sz[0] == 8) 1312f4f5df23SVikas Chaudhary word[startword] = tmpw; 1313f4f5df23SVikas Chaudhary else { 1314f4f5df23SVikas Chaudhary word[startword] &= 1315f4f5df23SVikas Chaudhary ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1316f4f5df23SVikas Chaudhary word[startword] |= tmpw << (off0 * 8); 1317f4f5df23SVikas Chaudhary } 1318f4f5df23SVikas Chaudhary 1319f4f5df23SVikas Chaudhary if (sz[1] != 0) { 1320f4f5df23SVikas Chaudhary word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1321f4f5df23SVikas Chaudhary word[startword+1] |= tmpw >> (sz[0] * 8); 1322f4f5df23SVikas Chaudhary } 1323f4f5df23SVikas Chaudhary 1324f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1325f4f5df23SVikas Chaudhary temp = off8 + (i << shift_amount); 1326f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1327f4f5df23SVikas Chaudhary temp = 0; 1328f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1329f4f5df23SVikas Chaudhary temp = word[i * scale] & 0xffffffff; 1330f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1331f4f5df23SVikas Chaudhary temp = (word[i * scale] >> 32) & 0xffffffff; 1332f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1333f4f5df23SVikas Chaudhary temp = word[i*scale + 1] & 0xffffffff; 1334f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, 1335f4f5df23SVikas Chaudhary temp); 1336f4f5df23SVikas Chaudhary temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1337f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, 1338f4f5df23SVikas Chaudhary temp); 1339f4f5df23SVikas Chaudhary 1340f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1341f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1342f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1343f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1344f4f5df23SVikas Chaudhary 1345f4f5df23SVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1346f4f5df23SVikas Chaudhary temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1347f4f5df23SVikas Chaudhary if ((temp & MIU_TA_CTL_BUSY) == 0) 1348f4f5df23SVikas Chaudhary break; 1349f4f5df23SVikas Chaudhary } 1350f4f5df23SVikas Chaudhary 1351f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1352f4f5df23SVikas Chaudhary if (printk_ratelimit()) 1353f4f5df23SVikas Chaudhary ql4_printk(KERN_ERR, ha, 1354f4f5df23SVikas Chaudhary "failed to write through agent\n"); 1355f4f5df23SVikas Chaudhary ret = -1; 1356f4f5df23SVikas Chaudhary break; 1357f4f5df23SVikas Chaudhary } 1358f4f5df23SVikas Chaudhary } 1359f4f5df23SVikas Chaudhary 1360f4f5df23SVikas Chaudhary return ret; 1361f4f5df23SVikas Chaudhary } 1362f4f5df23SVikas Chaudhary 1363f4f5df23SVikas Chaudhary static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) 1364f4f5df23SVikas Chaudhary { 1365f4f5df23SVikas Chaudhary u32 val = 0; 1366f4f5df23SVikas Chaudhary int retries = 60; 1367f4f5df23SVikas Chaudhary 1368f4f5df23SVikas Chaudhary if (!pegtune_val) { 1369f4f5df23SVikas Chaudhary do { 1370f4f5df23SVikas Chaudhary val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE); 1371f4f5df23SVikas Chaudhary if ((val == PHAN_INITIALIZE_COMPLETE) || 1372f4f5df23SVikas Chaudhary (val == PHAN_INITIALIZE_ACK)) 1373f4f5df23SVikas Chaudhary return 0; 1374f4f5df23SVikas Chaudhary set_current_state(TASK_UNINTERRUPTIBLE); 1375f4f5df23SVikas Chaudhary schedule_timeout(500); 1376f4f5df23SVikas Chaudhary 1377f4f5df23SVikas Chaudhary } while (--retries); 1378f4f5df23SVikas Chaudhary 1379f4f5df23SVikas Chaudhary qla4_8xxx_check_for_bad_spd(ha); 1380f4f5df23SVikas Chaudhary 1381f4f5df23SVikas Chaudhary if (!retries) { 1382f4f5df23SVikas Chaudhary pegtune_val = qla4_8xxx_rd_32(ha, 1383f4f5df23SVikas Chaudhary QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1384f4f5df23SVikas Chaudhary printk(KERN_WARNING "%s: init failed, " 1385f4f5df23SVikas Chaudhary "pegtune_val = %x\n", __func__, pegtune_val); 1386f4f5df23SVikas Chaudhary return -1; 1387f4f5df23SVikas Chaudhary } 1388f4f5df23SVikas Chaudhary } 1389f4f5df23SVikas Chaudhary return 0; 1390f4f5df23SVikas Chaudhary } 1391f4f5df23SVikas Chaudhary 1392f4f5df23SVikas Chaudhary static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha) 1393f4f5df23SVikas Chaudhary { 1394f4f5df23SVikas Chaudhary uint32_t state = 0; 1395f4f5df23SVikas Chaudhary int loops = 0; 1396f4f5df23SVikas Chaudhary 1397f4f5df23SVikas Chaudhary /* Window 1 call */ 1398f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1399f4f5df23SVikas Chaudhary state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE); 1400f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1401f4f5df23SVikas Chaudhary 1402f4f5df23SVikas Chaudhary while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { 1403f4f5df23SVikas Chaudhary udelay(100); 1404f4f5df23SVikas Chaudhary /* Window 1 call */ 1405f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1406f4f5df23SVikas Chaudhary state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE); 1407f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1408f4f5df23SVikas Chaudhary 1409f4f5df23SVikas Chaudhary loops++; 1410f4f5df23SVikas Chaudhary } 1411f4f5df23SVikas Chaudhary 1412f4f5df23SVikas Chaudhary if (loops >= 30000) { 1413f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 1414f4f5df23SVikas Chaudhary "Receive Peg initialization not complete: 0x%x.\n", state)); 1415f4f5df23SVikas Chaudhary return QLA_ERROR; 1416f4f5df23SVikas Chaudhary } 1417f4f5df23SVikas Chaudhary 1418f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1419f4f5df23SVikas Chaudhary } 1420f4f5df23SVikas Chaudhary 1421626115cdSAndrew Morton void 1422f4f5df23SVikas Chaudhary qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) 1423f4f5df23SVikas Chaudhary { 1424f4f5df23SVikas Chaudhary uint32_t drv_active; 1425f4f5df23SVikas Chaudhary 1426f4f5df23SVikas Chaudhary drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1427f4f5df23SVikas Chaudhary drv_active |= (1 << (ha->func_num * 4)); 1428f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1429f4f5df23SVikas Chaudhary } 1430f4f5df23SVikas Chaudhary 1431f4f5df23SVikas Chaudhary void 1432f4f5df23SVikas Chaudhary qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) 1433f4f5df23SVikas Chaudhary { 1434f4f5df23SVikas Chaudhary uint32_t drv_active; 1435f4f5df23SVikas Chaudhary 1436f4f5df23SVikas Chaudhary drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1437f4f5df23SVikas Chaudhary drv_active &= ~(1 << (ha->func_num * 4)); 1438f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1439f4f5df23SVikas Chaudhary } 1440f4f5df23SVikas Chaudhary 1441f4f5df23SVikas Chaudhary static inline int 1442f4f5df23SVikas Chaudhary qla4_8xxx_need_reset(struct scsi_qla_host *ha) 1443f4f5df23SVikas Chaudhary { 14442232be0dSLalit Chandivade uint32_t drv_state, drv_active; 1445f4f5df23SVikas Chaudhary int rval; 1446f4f5df23SVikas Chaudhary 14472232be0dSLalit Chandivade drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1448f4f5df23SVikas Chaudhary drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1449f4f5df23SVikas Chaudhary rval = drv_state & (1 << (ha->func_num * 4)); 14502232be0dSLalit Chandivade if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 14512232be0dSLalit Chandivade rval = 1; 14522232be0dSLalit Chandivade 1453f4f5df23SVikas Chaudhary return rval; 1454f4f5df23SVikas Chaudhary } 1455f4f5df23SVikas Chaudhary 1456f4f5df23SVikas Chaudhary static inline void 1457f4f5df23SVikas Chaudhary qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) 1458f4f5df23SVikas Chaudhary { 1459f4f5df23SVikas Chaudhary uint32_t drv_state; 1460f4f5df23SVikas Chaudhary 1461f4f5df23SVikas Chaudhary drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1462f4f5df23SVikas Chaudhary drv_state |= (1 << (ha->func_num * 4)); 1463f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1464f4f5df23SVikas Chaudhary } 1465f4f5df23SVikas Chaudhary 1466f4f5df23SVikas Chaudhary static inline void 1467f4f5df23SVikas Chaudhary qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) 1468f4f5df23SVikas Chaudhary { 1469f4f5df23SVikas Chaudhary uint32_t drv_state; 1470f4f5df23SVikas Chaudhary 1471f4f5df23SVikas Chaudhary drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1472f4f5df23SVikas Chaudhary drv_state &= ~(1 << (ha->func_num * 4)); 1473f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1474f4f5df23SVikas Chaudhary } 1475f4f5df23SVikas Chaudhary 1476f4f5df23SVikas Chaudhary static inline void 1477f4f5df23SVikas Chaudhary qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) 1478f4f5df23SVikas Chaudhary { 1479f4f5df23SVikas Chaudhary uint32_t qsnt_state; 1480f4f5df23SVikas Chaudhary 1481f4f5df23SVikas Chaudhary qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1482f4f5df23SVikas Chaudhary qsnt_state |= (2 << (ha->func_num * 4)); 1483f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 1484f4f5df23SVikas Chaudhary } 1485f4f5df23SVikas Chaudhary 1486f4f5df23SVikas Chaudhary 1487f4f5df23SVikas Chaudhary static int 1488f4f5df23SVikas Chaudhary qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) 1489f4f5df23SVikas Chaudhary { 1490f4f5df23SVikas Chaudhary int pcie_cap; 1491f4f5df23SVikas Chaudhary uint16_t lnk; 1492f4f5df23SVikas Chaudhary 1493f4f5df23SVikas Chaudhary /* scrub dma mask expansion register */ 1494f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 1495f4f5df23SVikas Chaudhary 1496f4f5df23SVikas Chaudhary /* Overwrite stale initialization register values */ 1497f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1498f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0); 1499f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 1500f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 1501f4f5df23SVikas Chaudhary 1502f4f5df23SVikas Chaudhary if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) { 1503f4f5df23SVikas Chaudhary printk("%s: Error trying to start fw!\n", __func__); 1504f4f5df23SVikas Chaudhary return QLA_ERROR; 1505f4f5df23SVikas Chaudhary } 1506f4f5df23SVikas Chaudhary 1507f4f5df23SVikas Chaudhary /* Handshake with the card before we register the devices. */ 1508f4f5df23SVikas Chaudhary if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { 1509f4f5df23SVikas Chaudhary printk("%s: Error during card handshake!\n", __func__); 1510f4f5df23SVikas Chaudhary return QLA_ERROR; 1511f4f5df23SVikas Chaudhary } 1512f4f5df23SVikas Chaudhary 1513f4f5df23SVikas Chaudhary /* Negotiated Link width */ 1514f4f5df23SVikas Chaudhary pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1515f4f5df23SVikas Chaudhary pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 1516f4f5df23SVikas Chaudhary ha->link_width = (lnk >> 4) & 0x3f; 1517f4f5df23SVikas Chaudhary 1518f4f5df23SVikas Chaudhary /* Synchronize with Receive peg */ 1519f4f5df23SVikas Chaudhary return qla4_8xxx_rcvpeg_ready(ha); 1520f4f5df23SVikas Chaudhary } 1521f4f5df23SVikas Chaudhary 1522f4f5df23SVikas Chaudhary static int 1523f4f5df23SVikas Chaudhary qla4_8xxx_try_start_fw(struct scsi_qla_host *ha) 1524f4f5df23SVikas Chaudhary { 1525f4f5df23SVikas Chaudhary int rval = QLA_ERROR; 1526f4f5df23SVikas Chaudhary 1527f4f5df23SVikas Chaudhary /* 1528f4f5df23SVikas Chaudhary * FW Load priority: 1529f4f5df23SVikas Chaudhary * 1) Operational firmware residing in flash. 1530f4f5df23SVikas Chaudhary * 2) Fail 1531f4f5df23SVikas Chaudhary */ 1532f4f5df23SVikas Chaudhary 1533f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1534f4f5df23SVikas Chaudhary "FW: Retrieving flash offsets from FLT/FDT ...\n"); 1535f4f5df23SVikas Chaudhary rval = qla4_8xxx_get_flash_info(ha); 1536f4f5df23SVikas Chaudhary if (rval != QLA_SUCCESS) 1537f4f5df23SVikas Chaudhary return rval; 1538f4f5df23SVikas Chaudhary 1539f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1540f4f5df23SVikas Chaudhary "FW: Attempting to load firmware from flash...\n"); 1541f4f5df23SVikas Chaudhary rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw); 1542f4f5df23SVikas Chaudhary if (rval == QLA_SUCCESS) 1543f4f5df23SVikas Chaudhary return rval; 1544f4f5df23SVikas Chaudhary 1545f4f5df23SVikas Chaudhary ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash FAILED...\n"); 1546f4f5df23SVikas Chaudhary 1547f4f5df23SVikas Chaudhary return rval; 1548f4f5df23SVikas Chaudhary } 1549f4f5df23SVikas Chaudhary 1550f4f5df23SVikas Chaudhary /** 1551f4f5df23SVikas Chaudhary * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw 1552f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 1553f4f5df23SVikas Chaudhary * 1554f4f5df23SVikas Chaudhary * Note: IDC lock must be held upon entry 1555f4f5df23SVikas Chaudhary **/ 1556f4f5df23SVikas Chaudhary static int 1557f4f5df23SVikas Chaudhary qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) 1558f4f5df23SVikas Chaudhary { 1559f4f5df23SVikas Chaudhary int rval, i, timeout; 1560f4f5df23SVikas Chaudhary uint32_t old_count, count; 1561f4f5df23SVikas Chaudhary 1562f4f5df23SVikas Chaudhary if (qla4_8xxx_need_reset(ha)) 1563f4f5df23SVikas Chaudhary goto dev_initialize; 1564f4f5df23SVikas Chaudhary 1565f4f5df23SVikas Chaudhary old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 1566f4f5df23SVikas Chaudhary 1567f4f5df23SVikas Chaudhary for (i = 0; i < 10; i++) { 1568f4f5df23SVikas Chaudhary timeout = msleep_interruptible(200); 1569f4f5df23SVikas Chaudhary if (timeout) { 1570f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 1571f4f5df23SVikas Chaudhary QLA82XX_DEV_FAILED); 1572f4f5df23SVikas Chaudhary return QLA_ERROR; 1573f4f5df23SVikas Chaudhary } 1574f4f5df23SVikas Chaudhary 1575f4f5df23SVikas Chaudhary count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 1576f4f5df23SVikas Chaudhary if (count != old_count) 1577f4f5df23SVikas Chaudhary goto dev_ready; 1578f4f5df23SVikas Chaudhary } 1579f4f5df23SVikas Chaudhary 1580f4f5df23SVikas Chaudhary dev_initialize: 1581f4f5df23SVikas Chaudhary /* set to DEV_INITIALIZING */ 1582f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 1583f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 1584f4f5df23SVikas Chaudhary 1585f4f5df23SVikas Chaudhary /* Driver that sets device state to initializating sets IDC version */ 1586f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 1587f4f5df23SVikas Chaudhary 1588f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1589f4f5df23SVikas Chaudhary rval = qla4_8xxx_try_start_fw(ha); 1590f4f5df23SVikas Chaudhary qla4_8xxx_idc_lock(ha); 1591f4f5df23SVikas Chaudhary 1592f4f5df23SVikas Chaudhary if (rval != QLA_SUCCESS) { 1593f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 1594f4f5df23SVikas Chaudhary qla4_8xxx_clear_drv_active(ha); 1595f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 1596f4f5df23SVikas Chaudhary return rval; 1597f4f5df23SVikas Chaudhary } 1598f4f5df23SVikas Chaudhary 1599f4f5df23SVikas Chaudhary dev_ready: 1600f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 1601f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 1602f4f5df23SVikas Chaudhary 1603f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1604f4f5df23SVikas Chaudhary } 1605f4f5df23SVikas Chaudhary 1606f4f5df23SVikas Chaudhary /** 1607f4f5df23SVikas Chaudhary * qla4_8xxx_need_reset_handler - Code to start reset sequence 1608f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 1609f4f5df23SVikas Chaudhary * 1610f4f5df23SVikas Chaudhary * Note: IDC lock must be held upon entry 1611f4f5df23SVikas Chaudhary **/ 1612f4f5df23SVikas Chaudhary static void 1613f4f5df23SVikas Chaudhary qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha) 1614f4f5df23SVikas Chaudhary { 1615f4f5df23SVikas Chaudhary uint32_t dev_state, drv_state, drv_active; 1616f4f5df23SVikas Chaudhary unsigned long reset_timeout; 1617f4f5df23SVikas Chaudhary 1618f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1619f4f5df23SVikas Chaudhary "Performing ISP error recovery\n"); 1620f4f5df23SVikas Chaudhary 1621f4f5df23SVikas Chaudhary if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { 1622f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1623f4f5df23SVikas Chaudhary ha->isp_ops->disable_intrs(ha); 1624f4f5df23SVikas Chaudhary qla4_8xxx_idc_lock(ha); 1625f4f5df23SVikas Chaudhary } 1626f4f5df23SVikas Chaudhary 1627f4f5df23SVikas Chaudhary qla4_8xxx_set_rst_ready(ha); 1628f4f5df23SVikas Chaudhary 1629f4f5df23SVikas Chaudhary /* wait for 10 seconds for reset ack from all functions */ 1630f4f5df23SVikas Chaudhary reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 1631f4f5df23SVikas Chaudhary 1632f4f5df23SVikas Chaudhary drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1633f4f5df23SVikas Chaudhary drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1634f4f5df23SVikas Chaudhary 1635f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1636f4f5df23SVikas Chaudhary "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 1637f4f5df23SVikas Chaudhary __func__, ha->host_no, drv_state, drv_active); 1638f4f5df23SVikas Chaudhary 1639f4f5df23SVikas Chaudhary while (drv_state != drv_active) { 1640f4f5df23SVikas Chaudhary if (time_after_eq(jiffies, reset_timeout)) { 1641f4f5df23SVikas Chaudhary printk("%s: RESET TIMEOUT!\n", DRIVER_NAME); 1642f4f5df23SVikas Chaudhary break; 1643f4f5df23SVikas Chaudhary } 1644f4f5df23SVikas Chaudhary 1645f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1646f4f5df23SVikas Chaudhary msleep(1000); 1647f4f5df23SVikas Chaudhary qla4_8xxx_idc_lock(ha); 1648f4f5df23SVikas Chaudhary 1649f4f5df23SVikas Chaudhary drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1650f4f5df23SVikas Chaudhary drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1651f4f5df23SVikas Chaudhary } 1652f4f5df23SVikas Chaudhary 1653f4f5df23SVikas Chaudhary dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 1654f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state, 1655f4f5df23SVikas Chaudhary dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 1656f4f5df23SVikas Chaudhary 1657f4f5df23SVikas Chaudhary /* Force to DEV_COLD unless someone else is starting a reset */ 1658f4f5df23SVikas Chaudhary if (dev_state != QLA82XX_DEV_INITIALIZING) { 1659f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 1660f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 1661f4f5df23SVikas Chaudhary } 1662f4f5df23SVikas Chaudhary } 1663f4f5df23SVikas Chaudhary 1664f4f5df23SVikas Chaudhary /** 1665f4f5df23SVikas Chaudhary * qla4_8xxx_need_qsnt_handler - Code to start qsnt 1666f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 1667f4f5df23SVikas Chaudhary **/ 1668f4f5df23SVikas Chaudhary void 1669f4f5df23SVikas Chaudhary qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 1670f4f5df23SVikas Chaudhary { 1671f4f5df23SVikas Chaudhary qla4_8xxx_idc_lock(ha); 1672f4f5df23SVikas Chaudhary qla4_8xxx_set_qsnt_ready(ha); 1673f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1674f4f5df23SVikas Chaudhary } 1675f4f5df23SVikas Chaudhary 1676f4f5df23SVikas Chaudhary /** 1677f4f5df23SVikas Chaudhary * qla4_8xxx_device_state_handler - Adapter state machine 1678f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 1679f4f5df23SVikas Chaudhary * 1680f4f5df23SVikas Chaudhary * Note: IDC lock must be UNLOCKED upon entry 1681f4f5df23SVikas Chaudhary **/ 1682f4f5df23SVikas Chaudhary int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) 1683f4f5df23SVikas Chaudhary { 1684f4f5df23SVikas Chaudhary uint32_t dev_state; 1685f4f5df23SVikas Chaudhary int rval = QLA_SUCCESS; 1686f4f5df23SVikas Chaudhary unsigned long dev_init_timeout; 1687f4f5df23SVikas Chaudhary 1688f4f5df23SVikas Chaudhary if (!test_bit(AF_INIT_DONE, &ha->flags)) 1689f4f5df23SVikas Chaudhary qla4_8xxx_set_drv_active(ha); 1690f4f5df23SVikas Chaudhary 1691f4f5df23SVikas Chaudhary dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 1692f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state, 1693f4f5df23SVikas Chaudhary dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 1694f4f5df23SVikas Chaudhary 1695f4f5df23SVikas Chaudhary /* wait for 30 seconds for device to go ready */ 1696f4f5df23SVikas Chaudhary dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 1697f4f5df23SVikas Chaudhary 1698f4f5df23SVikas Chaudhary while (1) { 1699f4f5df23SVikas Chaudhary qla4_8xxx_idc_lock(ha); 1700f4f5df23SVikas Chaudhary 1701f4f5df23SVikas Chaudhary if (time_after_eq(jiffies, dev_init_timeout)) { 1702f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, "Device init failed!\n"); 1703f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 1704f4f5df23SVikas Chaudhary QLA82XX_DEV_FAILED); 1705f4f5df23SVikas Chaudhary } 1706f4f5df23SVikas Chaudhary 1707f4f5df23SVikas Chaudhary dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 1708f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1709f4f5df23SVikas Chaudhary "2:Device state is 0x%x = %s\n", dev_state, 1710f4f5df23SVikas Chaudhary dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 1711f4f5df23SVikas Chaudhary 1712f4f5df23SVikas Chaudhary /* NOTE: Make sure idc unlocked upon exit of switch statement */ 1713f4f5df23SVikas Chaudhary switch (dev_state) { 1714f4f5df23SVikas Chaudhary case QLA82XX_DEV_READY: 1715f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1716f4f5df23SVikas Chaudhary goto exit; 1717f4f5df23SVikas Chaudhary case QLA82XX_DEV_COLD: 1718f4f5df23SVikas Chaudhary rval = qla4_8xxx_device_bootstrap(ha); 1719f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1720f4f5df23SVikas Chaudhary goto exit; 1721f4f5df23SVikas Chaudhary case QLA82XX_DEV_INITIALIZING: 1722f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1723f4f5df23SVikas Chaudhary msleep(1000); 1724f4f5df23SVikas Chaudhary break; 1725f4f5df23SVikas Chaudhary case QLA82XX_DEV_NEED_RESET: 1726f4f5df23SVikas Chaudhary if (!ql4xdontresethba) { 1727f4f5df23SVikas Chaudhary qla4_8xxx_need_reset_handler(ha); 1728f4f5df23SVikas Chaudhary /* Update timeout value after need 1729f4f5df23SVikas Chaudhary * reset handler */ 1730f4f5df23SVikas Chaudhary dev_init_timeout = jiffies + 1731f4f5df23SVikas Chaudhary (ha->nx_dev_init_timeout * HZ); 1732f4f5df23SVikas Chaudhary } 1733f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1734f4f5df23SVikas Chaudhary break; 1735f4f5df23SVikas Chaudhary case QLA82XX_DEV_NEED_QUIESCENT: 1736f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1737f4f5df23SVikas Chaudhary /* idc locked/unlocked in handler */ 1738f4f5df23SVikas Chaudhary qla4_8xxx_need_qsnt_handler(ha); 1739f4f5df23SVikas Chaudhary qla4_8xxx_idc_lock(ha); 1740f4f5df23SVikas Chaudhary /* fall thru needs idc_locked */ 1741f4f5df23SVikas Chaudhary case QLA82XX_DEV_QUIESCENT: 1742f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1743f4f5df23SVikas Chaudhary msleep(1000); 1744f4f5df23SVikas Chaudhary break; 1745f4f5df23SVikas Chaudhary case QLA82XX_DEV_FAILED: 1746f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1747f4f5df23SVikas Chaudhary qla4xxx_dead_adapter_cleanup(ha); 1748f4f5df23SVikas Chaudhary rval = QLA_ERROR; 1749f4f5df23SVikas Chaudhary goto exit; 1750f4f5df23SVikas Chaudhary default: 1751f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 1752f4f5df23SVikas Chaudhary qla4xxx_dead_adapter_cleanup(ha); 1753f4f5df23SVikas Chaudhary rval = QLA_ERROR; 1754f4f5df23SVikas Chaudhary goto exit; 1755f4f5df23SVikas Chaudhary } 1756f4f5df23SVikas Chaudhary } 1757f4f5df23SVikas Chaudhary exit: 1758f4f5df23SVikas Chaudhary return rval; 1759f4f5df23SVikas Chaudhary } 1760f4f5df23SVikas Chaudhary 1761f4f5df23SVikas Chaudhary int qla4_8xxx_load_risc(struct scsi_qla_host *ha) 1762f4f5df23SVikas Chaudhary { 1763f4f5df23SVikas Chaudhary int retval; 1764f4f5df23SVikas Chaudhary retval = qla4_8xxx_device_state_handler(ha); 1765f4f5df23SVikas Chaudhary 1766f4f5df23SVikas Chaudhary if (retval == QLA_SUCCESS && 1767f4f5df23SVikas Chaudhary !test_bit(AF_INIT_DONE, &ha->flags)) { 1768f4f5df23SVikas Chaudhary retval = qla4xxx_request_irqs(ha); 1769f4f5df23SVikas Chaudhary if (retval != QLA_SUCCESS) { 1770f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1771f4f5df23SVikas Chaudhary "Failed to reserve interrupt %d already in use.\n", 1772f4f5df23SVikas Chaudhary ha->pdev->irq); 1773f4f5df23SVikas Chaudhary } else { 1774f4f5df23SVikas Chaudhary set_bit(AF_IRQ_ATTACHED, &ha->flags); 1775f4f5df23SVikas Chaudhary ha->host->irq = ha->pdev->irq; 1776f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "%s: irq %d attached\n", 1777f4f5df23SVikas Chaudhary __func__, ha->pdev->irq); 1778f4f5df23SVikas Chaudhary } 1779f4f5df23SVikas Chaudhary } 1780f4f5df23SVikas Chaudhary return retval; 1781f4f5df23SVikas Chaudhary } 1782f4f5df23SVikas Chaudhary 1783f4f5df23SVikas Chaudhary /*****************************************************************************/ 1784f4f5df23SVikas Chaudhary /* Flash Manipulation Routines */ 1785f4f5df23SVikas Chaudhary /*****************************************************************************/ 1786f4f5df23SVikas Chaudhary 1787f4f5df23SVikas Chaudhary #define OPTROM_BURST_SIZE 0x1000 1788f4f5df23SVikas Chaudhary #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 1789f4f5df23SVikas Chaudhary 1790f4f5df23SVikas Chaudhary #define FARX_DATA_FLAG BIT_31 1791f4f5df23SVikas Chaudhary #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 1792f4f5df23SVikas Chaudhary #define FARX_ACCESS_FLASH_DATA 0x7FF00000 1793f4f5df23SVikas Chaudhary 1794f4f5df23SVikas Chaudhary static inline uint32_t 1795f4f5df23SVikas Chaudhary flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 1796f4f5df23SVikas Chaudhary { 1797f4f5df23SVikas Chaudhary return hw->flash_conf_off | faddr; 1798f4f5df23SVikas Chaudhary } 1799f4f5df23SVikas Chaudhary 1800f4f5df23SVikas Chaudhary static inline uint32_t 1801f4f5df23SVikas Chaudhary flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 1802f4f5df23SVikas Chaudhary { 1803f4f5df23SVikas Chaudhary return hw->flash_data_off | faddr; 1804f4f5df23SVikas Chaudhary } 1805f4f5df23SVikas Chaudhary 1806f4f5df23SVikas Chaudhary static uint32_t * 1807f4f5df23SVikas Chaudhary qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, 1808f4f5df23SVikas Chaudhary uint32_t faddr, uint32_t length) 1809f4f5df23SVikas Chaudhary { 1810f4f5df23SVikas Chaudhary uint32_t i; 1811f4f5df23SVikas Chaudhary uint32_t val; 1812f4f5df23SVikas Chaudhary int loops = 0; 1813f4f5df23SVikas Chaudhary while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) { 1814f4f5df23SVikas Chaudhary udelay(100); 1815f4f5df23SVikas Chaudhary cond_resched(); 1816f4f5df23SVikas Chaudhary loops++; 1817f4f5df23SVikas Chaudhary } 1818f4f5df23SVikas Chaudhary if (loops >= 50000) { 1819f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); 1820f4f5df23SVikas Chaudhary return dwptr; 1821f4f5df23SVikas Chaudhary } 1822f4f5df23SVikas Chaudhary 1823f4f5df23SVikas Chaudhary /* Dword reads to flash. */ 1824f4f5df23SVikas Chaudhary for (i = 0; i < length/4; i++, faddr += 4) { 1825f4f5df23SVikas Chaudhary if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) { 1826f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1827f4f5df23SVikas Chaudhary "Do ROM fast read failed\n"); 1828f4f5df23SVikas Chaudhary goto done_read; 1829f4f5df23SVikas Chaudhary } 1830f4f5df23SVikas Chaudhary dwptr[i] = __constant_cpu_to_le32(val); 1831f4f5df23SVikas Chaudhary } 1832f4f5df23SVikas Chaudhary 1833f4f5df23SVikas Chaudhary done_read: 1834f4f5df23SVikas Chaudhary qla4_8xxx_rom_unlock(ha); 1835f4f5df23SVikas Chaudhary return dwptr; 1836f4f5df23SVikas Chaudhary } 1837f4f5df23SVikas Chaudhary 1838f4f5df23SVikas Chaudhary /** 1839f4f5df23SVikas Chaudhary * Address and length are byte address 1840f4f5df23SVikas Chaudhary **/ 1841f4f5df23SVikas Chaudhary static uint8_t * 1842f4f5df23SVikas Chaudhary qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1843f4f5df23SVikas Chaudhary uint32_t offset, uint32_t length) 1844f4f5df23SVikas Chaudhary { 1845f4f5df23SVikas Chaudhary qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length); 1846f4f5df23SVikas Chaudhary return buf; 1847f4f5df23SVikas Chaudhary } 1848f4f5df23SVikas Chaudhary 1849f4f5df23SVikas Chaudhary static int 1850f4f5df23SVikas Chaudhary qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) 1851f4f5df23SVikas Chaudhary { 1852f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "DEF", "PCI" }; 1853f4f5df23SVikas Chaudhary 1854f4f5df23SVikas Chaudhary /* 1855f4f5df23SVikas Chaudhary * FLT-location structure resides after the last PCI region. 1856f4f5df23SVikas Chaudhary */ 1857f4f5df23SVikas Chaudhary 1858f4f5df23SVikas Chaudhary /* Begin with sane defaults. */ 1859f4f5df23SVikas Chaudhary loc = locations[0]; 1860f4f5df23SVikas Chaudhary *start = FA_FLASH_LAYOUT_ADDR_82; 1861f4f5df23SVikas Chaudhary 1862f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 1863f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1864f4f5df23SVikas Chaudhary } 1865f4f5df23SVikas Chaudhary 1866f4f5df23SVikas Chaudhary static void 1867f4f5df23SVikas Chaudhary qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) 1868f4f5df23SVikas Chaudhary { 1869f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "DEF", "FLT" }; 1870f4f5df23SVikas Chaudhary uint16_t *wptr; 1871f4f5df23SVikas Chaudhary uint16_t cnt, chksum; 1872f4f5df23SVikas Chaudhary uint32_t start; 1873f4f5df23SVikas Chaudhary struct qla_flt_header *flt; 1874f4f5df23SVikas Chaudhary struct qla_flt_region *region; 1875f4f5df23SVikas Chaudhary struct ql82xx_hw_data *hw = &ha->hw; 1876f4f5df23SVikas Chaudhary 1877f4f5df23SVikas Chaudhary hw->flt_region_flt = flt_addr; 1878f4f5df23SVikas Chaudhary wptr = (uint16_t *)ha->request_ring; 1879f4f5df23SVikas Chaudhary flt = (struct qla_flt_header *)ha->request_ring; 1880f4f5df23SVikas Chaudhary region = (struct qla_flt_region *)&flt[1]; 1881f4f5df23SVikas Chaudhary qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 1882f4f5df23SVikas Chaudhary flt_addr << 2, OPTROM_BURST_SIZE); 1883f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le16(0xffff)) 1884f4f5df23SVikas Chaudhary goto no_flash_data; 1885f4f5df23SVikas Chaudhary if (flt->version != __constant_cpu_to_le16(1)) { 1886f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " 1887f4f5df23SVikas Chaudhary "version=0x%x length=0x%x checksum=0x%x.\n", 1888f4f5df23SVikas Chaudhary le16_to_cpu(flt->version), le16_to_cpu(flt->length), 1889f4f5df23SVikas Chaudhary le16_to_cpu(flt->checksum))); 1890f4f5df23SVikas Chaudhary goto no_flash_data; 1891f4f5df23SVikas Chaudhary } 1892f4f5df23SVikas Chaudhary 1893f4f5df23SVikas Chaudhary cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 1894f4f5df23SVikas Chaudhary for (chksum = 0; cnt; cnt--) 1895f4f5df23SVikas Chaudhary chksum += le16_to_cpu(*wptr++); 1896f4f5df23SVikas Chaudhary if (chksum) { 1897f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 1898f4f5df23SVikas Chaudhary "version=0x%x length=0x%x checksum=0x%x.\n", 1899f4f5df23SVikas Chaudhary le16_to_cpu(flt->version), le16_to_cpu(flt->length), 1900f4f5df23SVikas Chaudhary chksum)); 1901f4f5df23SVikas Chaudhary goto no_flash_data; 1902f4f5df23SVikas Chaudhary } 1903f4f5df23SVikas Chaudhary 1904f4f5df23SVikas Chaudhary loc = locations[1]; 1905f4f5df23SVikas Chaudhary cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 1906f4f5df23SVikas Chaudhary for ( ; cnt; cnt--, region++) { 1907f4f5df23SVikas Chaudhary /* Store addresses as DWORD offsets. */ 1908f4f5df23SVikas Chaudhary start = le32_to_cpu(region->start) >> 2; 1909f4f5df23SVikas Chaudhary 1910f4f5df23SVikas Chaudhary DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 1911f4f5df23SVikas Chaudhary "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 1912f4f5df23SVikas Chaudhary le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 1913f4f5df23SVikas Chaudhary 1914f4f5df23SVikas Chaudhary switch (le32_to_cpu(region->code) & 0xff) { 1915f4f5df23SVikas Chaudhary case FLT_REG_FDT: 1916f4f5df23SVikas Chaudhary hw->flt_region_fdt = start; 1917f4f5df23SVikas Chaudhary break; 1918f4f5df23SVikas Chaudhary case FLT_REG_BOOT_CODE_82: 1919f4f5df23SVikas Chaudhary hw->flt_region_boot = start; 1920f4f5df23SVikas Chaudhary break; 1921f4f5df23SVikas Chaudhary case FLT_REG_FW_82: 1922f4f5df23SVikas Chaudhary hw->flt_region_fw = start; 1923f4f5df23SVikas Chaudhary break; 1924f4f5df23SVikas Chaudhary case FLT_REG_BOOTLOAD_82: 1925f4f5df23SVikas Chaudhary hw->flt_region_bootload = start; 1926f4f5df23SVikas Chaudhary break; 1927f4f5df23SVikas Chaudhary } 1928f4f5df23SVikas Chaudhary } 1929f4f5df23SVikas Chaudhary goto done; 1930f4f5df23SVikas Chaudhary 1931f4f5df23SVikas Chaudhary no_flash_data: 1932f4f5df23SVikas Chaudhary /* Use hardcoded defaults. */ 1933f4f5df23SVikas Chaudhary loc = locations[0]; 1934f4f5df23SVikas Chaudhary 1935f4f5df23SVikas Chaudhary hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; 1936f4f5df23SVikas Chaudhary hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; 1937f4f5df23SVikas Chaudhary hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; 1938f4f5df23SVikas Chaudhary hw->flt_region_fw = FA_RISC_CODE_ADDR_82; 1939f4f5df23SVikas Chaudhary done: 1940f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x " 1941f4f5df23SVikas Chaudhary "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt, 1942f4f5df23SVikas Chaudhary hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload, 1943f4f5df23SVikas Chaudhary hw->flt_region_fw)); 1944f4f5df23SVikas Chaudhary } 1945f4f5df23SVikas Chaudhary 1946f4f5df23SVikas Chaudhary static void 1947f4f5df23SVikas Chaudhary qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha) 1948f4f5df23SVikas Chaudhary { 1949f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_4K 0x1000 1950f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_32K 0x8000 1951f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_64K 0x10000 1952f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "MID", "FDT" }; 1953f4f5df23SVikas Chaudhary uint16_t cnt, chksum; 1954f4f5df23SVikas Chaudhary uint16_t *wptr; 1955f4f5df23SVikas Chaudhary struct qla_fdt_layout *fdt; 19563c3e2108SVikas Chaudhary uint16_t mid = 0; 19573c3e2108SVikas Chaudhary uint16_t fid = 0; 1958f4f5df23SVikas Chaudhary struct ql82xx_hw_data *hw = &ha->hw; 1959f4f5df23SVikas Chaudhary 1960f4f5df23SVikas Chaudhary hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; 1961f4f5df23SVikas Chaudhary hw->flash_data_off = FARX_ACCESS_FLASH_DATA; 1962f4f5df23SVikas Chaudhary 1963f4f5df23SVikas Chaudhary wptr = (uint16_t *)ha->request_ring; 1964f4f5df23SVikas Chaudhary fdt = (struct qla_fdt_layout *)ha->request_ring; 1965f4f5df23SVikas Chaudhary qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 1966f4f5df23SVikas Chaudhary hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); 1967f4f5df23SVikas Chaudhary 1968f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le16(0xffff)) 1969f4f5df23SVikas Chaudhary goto no_flash_data; 1970f4f5df23SVikas Chaudhary 1971f4f5df23SVikas Chaudhary if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 1972f4f5df23SVikas Chaudhary fdt->sig[3] != 'D') 1973f4f5df23SVikas Chaudhary goto no_flash_data; 1974f4f5df23SVikas Chaudhary 1975f4f5df23SVikas Chaudhary for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 1976f4f5df23SVikas Chaudhary cnt++) 1977f4f5df23SVikas Chaudhary chksum += le16_to_cpu(*wptr++); 1978f4f5df23SVikas Chaudhary 1979f4f5df23SVikas Chaudhary if (chksum) { 1980f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 1981f4f5df23SVikas Chaudhary "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 1982f4f5df23SVikas Chaudhary le16_to_cpu(fdt->version))); 1983f4f5df23SVikas Chaudhary goto no_flash_data; 1984f4f5df23SVikas Chaudhary } 1985f4f5df23SVikas Chaudhary 1986f4f5df23SVikas Chaudhary loc = locations[1]; 1987f4f5df23SVikas Chaudhary mid = le16_to_cpu(fdt->man_id); 1988f4f5df23SVikas Chaudhary fid = le16_to_cpu(fdt->id); 1989f4f5df23SVikas Chaudhary hw->fdt_wrt_disable = fdt->wrt_disable_bits; 1990f4f5df23SVikas Chaudhary hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); 1991f4f5df23SVikas Chaudhary hw->fdt_block_size = le32_to_cpu(fdt->block_size); 1992f4f5df23SVikas Chaudhary 1993f4f5df23SVikas Chaudhary if (fdt->unprotect_sec_cmd) { 1994f4f5df23SVikas Chaudhary hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | 1995f4f5df23SVikas Chaudhary fdt->unprotect_sec_cmd); 1996f4f5df23SVikas Chaudhary hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 1997f4f5df23SVikas Chaudhary flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : 1998f4f5df23SVikas Chaudhary flash_conf_addr(hw, 0x0336); 1999f4f5df23SVikas Chaudhary } 2000f4f5df23SVikas Chaudhary goto done; 2001f4f5df23SVikas Chaudhary 2002f4f5df23SVikas Chaudhary no_flash_data: 2003f4f5df23SVikas Chaudhary loc = locations[0]; 2004f4f5df23SVikas Chaudhary hw->fdt_block_size = FLASH_BLK_SIZE_64K; 2005f4f5df23SVikas Chaudhary done: 2006f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 2007f4f5df23SVikas Chaudhary "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 2008f4f5df23SVikas Chaudhary hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, 2009f4f5df23SVikas Chaudhary hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, 2010f4f5df23SVikas Chaudhary hw->fdt_block_size)); 2011f4f5df23SVikas Chaudhary } 2012f4f5df23SVikas Chaudhary 2013f4f5df23SVikas Chaudhary static void 2014f4f5df23SVikas Chaudhary qla4_8xxx_get_idc_param(struct scsi_qla_host *ha) 2015f4f5df23SVikas Chaudhary { 2016f4f5df23SVikas Chaudhary #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 2017f4f5df23SVikas Chaudhary uint32_t *wptr; 2018f4f5df23SVikas Chaudhary 2019f4f5df23SVikas Chaudhary if (!is_qla8022(ha)) 2020f4f5df23SVikas Chaudhary return; 2021f4f5df23SVikas Chaudhary wptr = (uint32_t *)ha->request_ring; 2022f4f5df23SVikas Chaudhary qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2023f4f5df23SVikas Chaudhary QLA82XX_IDC_PARAM_ADDR , 8); 2024f4f5df23SVikas Chaudhary 2025f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 2026f4f5df23SVikas Chaudhary ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; 2027f4f5df23SVikas Chaudhary ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; 2028f4f5df23SVikas Chaudhary } else { 2029f4f5df23SVikas Chaudhary ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 2030f4f5df23SVikas Chaudhary ha->nx_reset_timeout = le32_to_cpu(*wptr); 2031f4f5df23SVikas Chaudhary } 2032f4f5df23SVikas Chaudhary 2033f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_DEBUG, ha, 2034f4f5df23SVikas Chaudhary "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); 2035f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_DEBUG, ha, 2036f4f5df23SVikas Chaudhary "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); 2037f4f5df23SVikas Chaudhary return; 2038f4f5df23SVikas Chaudhary } 2039f4f5df23SVikas Chaudhary 2040f4f5df23SVikas Chaudhary int 2041f4f5df23SVikas Chaudhary qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 2042f4f5df23SVikas Chaudhary { 2043f4f5df23SVikas Chaudhary int ret; 2044f4f5df23SVikas Chaudhary uint32_t flt_addr; 2045f4f5df23SVikas Chaudhary 2046f4f5df23SVikas Chaudhary ret = qla4_8xxx_find_flt_start(ha, &flt_addr); 2047f4f5df23SVikas Chaudhary if (ret != QLA_SUCCESS) 2048f4f5df23SVikas Chaudhary return ret; 2049f4f5df23SVikas Chaudhary 2050f4f5df23SVikas Chaudhary qla4_8xxx_get_flt_info(ha, flt_addr); 2051f4f5df23SVikas Chaudhary qla4_8xxx_get_fdt_info(ha); 2052f4f5df23SVikas Chaudhary qla4_8xxx_get_idc_param(ha); 2053f4f5df23SVikas Chaudhary 2054f4f5df23SVikas Chaudhary return QLA_SUCCESS; 2055f4f5df23SVikas Chaudhary } 2056f4f5df23SVikas Chaudhary 2057f4f5df23SVikas Chaudhary /** 2058f4f5df23SVikas Chaudhary * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance 2059f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 2060f4f5df23SVikas Chaudhary * 2061f4f5df23SVikas Chaudhary * Remarks: 2062f4f5df23SVikas Chaudhary * For iSCSI, throws away all I/O and AENs into bit bucket, so they will 2063f4f5df23SVikas Chaudhary * not be available after successful return. Driver must cleanup potential 2064f4f5df23SVikas Chaudhary * outstanding I/O's after calling this funcion. 2065f4f5df23SVikas Chaudhary **/ 2066f4f5df23SVikas Chaudhary int 2067f4f5df23SVikas Chaudhary qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) 2068f4f5df23SVikas Chaudhary { 2069f4f5df23SVikas Chaudhary int status; 2070f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 2071f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 2072f4f5df23SVikas Chaudhary 2073f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2074f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 2075f4f5df23SVikas Chaudhary 2076f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_STOP_FW; 2077f4f5df23SVikas Chaudhary status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, 2078f4f5df23SVikas Chaudhary &mbox_cmd[0], &mbox_sts[0]); 2079f4f5df23SVikas Chaudhary 2080f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, 2081f4f5df23SVikas Chaudhary __func__, status)); 2082f4f5df23SVikas Chaudhary return status; 2083f4f5df23SVikas Chaudhary } 2084f4f5df23SVikas Chaudhary 2085f4f5df23SVikas Chaudhary /** 2086f4f5df23SVikas Chaudhary * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands. 2087f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 2088f4f5df23SVikas Chaudhary **/ 2089f4f5df23SVikas Chaudhary int 2090f4f5df23SVikas Chaudhary qla4_8xxx_isp_reset(struct scsi_qla_host *ha) 2091f4f5df23SVikas Chaudhary { 2092f4f5df23SVikas Chaudhary int rval; 2093f4f5df23SVikas Chaudhary uint32_t dev_state; 2094f4f5df23SVikas Chaudhary 2095f4f5df23SVikas Chaudhary qla4_8xxx_idc_lock(ha); 2096f4f5df23SVikas Chaudhary dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2097f4f5df23SVikas Chaudhary 2098f4f5df23SVikas Chaudhary if (dev_state == QLA82XX_DEV_READY) { 2099f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 2100f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2101f4f5df23SVikas Chaudhary QLA82XX_DEV_NEED_RESET); 2102f4f5df23SVikas Chaudhary } else 2103f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); 2104f4f5df23SVikas Chaudhary 2105f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 2106f4f5df23SVikas Chaudhary 2107f4f5df23SVikas Chaudhary rval = qla4_8xxx_device_state_handler(ha); 2108f4f5df23SVikas Chaudhary 2109f4f5df23SVikas Chaudhary qla4_8xxx_idc_lock(ha); 2110f4f5df23SVikas Chaudhary qla4_8xxx_clear_rst_ready(ha); 2111f4f5df23SVikas Chaudhary qla4_8xxx_idc_unlock(ha); 2112f4f5df23SVikas Chaudhary 211321033639SNilesh Javali if (rval == QLA_SUCCESS) 211421033639SNilesh Javali clear_bit(AF_FW_RECOVERY, &ha->flags); 211521033639SNilesh Javali 2116f4f5df23SVikas Chaudhary return rval; 2117f4f5df23SVikas Chaudhary } 2118f4f5df23SVikas Chaudhary 2119f4f5df23SVikas Chaudhary /** 2120f4f5df23SVikas Chaudhary * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number 2121f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 2122f4f5df23SVikas Chaudhary * 2123f4f5df23SVikas Chaudhary **/ 2124f4f5df23SVikas Chaudhary int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) 2125f4f5df23SVikas Chaudhary { 2126f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 2127f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 2128f4f5df23SVikas Chaudhary struct mbx_sys_info *sys_info; 2129f4f5df23SVikas Chaudhary dma_addr_t sys_info_dma; 2130f4f5df23SVikas Chaudhary int status = QLA_ERROR; 2131f4f5df23SVikas Chaudhary 2132f4f5df23SVikas Chaudhary sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), 2133f4f5df23SVikas Chaudhary &sys_info_dma, GFP_KERNEL); 2134f4f5df23SVikas Chaudhary if (sys_info == NULL) { 2135f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", 2136f4f5df23SVikas Chaudhary ha->host_no, __func__)); 2137f4f5df23SVikas Chaudhary return status; 2138f4f5df23SVikas Chaudhary } 2139f4f5df23SVikas Chaudhary 2140f4f5df23SVikas Chaudhary memset(sys_info, 0, sizeof(*sys_info)); 2141f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2142f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 2143f4f5df23SVikas Chaudhary 2144f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; 2145f4f5df23SVikas Chaudhary mbox_cmd[1] = LSDW(sys_info_dma); 2146f4f5df23SVikas Chaudhary mbox_cmd[2] = MSDW(sys_info_dma); 2147f4f5df23SVikas Chaudhary mbox_cmd[4] = sizeof(*sys_info); 2148f4f5df23SVikas Chaudhary 2149f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], 2150f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 2151f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", 2152f4f5df23SVikas Chaudhary ha->host_no, __func__)); 2153f4f5df23SVikas Chaudhary goto exit_validate_mac82; 2154f4f5df23SVikas Chaudhary } 2155f4f5df23SVikas Chaudhary 21562ccdf0dcSVikas Chaudhary /* Make sure we receive the minimum required data to cache internally */ 21572ccdf0dcSVikas Chaudhary if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) { 2158f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" 2159f4f5df23SVikas Chaudhary " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); 2160f4f5df23SVikas Chaudhary goto exit_validate_mac82; 2161f4f5df23SVikas Chaudhary 2162f4f5df23SVikas Chaudhary } 2163f4f5df23SVikas Chaudhary 2164f4f5df23SVikas Chaudhary /* Save M.A.C. address & serial_number */ 2165f4f5df23SVikas Chaudhary memcpy(ha->my_mac, &sys_info->mac_addr[0], 2166f4f5df23SVikas Chaudhary min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); 2167f4f5df23SVikas Chaudhary memcpy(ha->serial_number, &sys_info->serial_number, 2168f4f5df23SVikas Chaudhary min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); 2169f4f5df23SVikas Chaudhary 2170f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: " 2171f4f5df23SVikas Chaudhary "mac %02x:%02x:%02x:%02x:%02x:%02x " 2172f4f5df23SVikas Chaudhary "serial %s\n", ha->host_no, __func__, 2173f4f5df23SVikas Chaudhary ha->my_mac[0], ha->my_mac[1], ha->my_mac[2], 2174f4f5df23SVikas Chaudhary ha->my_mac[3], ha->my_mac[4], ha->my_mac[5], 2175f4f5df23SVikas Chaudhary ha->serial_number)); 2176f4f5df23SVikas Chaudhary 2177f4f5df23SVikas Chaudhary status = QLA_SUCCESS; 2178f4f5df23SVikas Chaudhary 2179f4f5df23SVikas Chaudhary exit_validate_mac82: 2180f4f5df23SVikas Chaudhary dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, 2181f4f5df23SVikas Chaudhary sys_info_dma); 2182f4f5df23SVikas Chaudhary return status; 2183f4f5df23SVikas Chaudhary } 2184f4f5df23SVikas Chaudhary 2185f4f5df23SVikas Chaudhary /* Interrupt handling helpers. */ 2186f4f5df23SVikas Chaudhary 2187f4f5df23SVikas Chaudhary static int 2188f4f5df23SVikas Chaudhary qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha) 2189f4f5df23SVikas Chaudhary { 2190f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 2191f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 2192f4f5df23SVikas Chaudhary 2193f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 2194f4f5df23SVikas Chaudhary 2195f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2196f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 2197f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 2198f4f5df23SVikas Chaudhary mbox_cmd[1] = INTR_ENABLE; 2199f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 2200f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 2201f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 2202f4f5df23SVikas Chaudhary "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 2203f4f5df23SVikas Chaudhary __func__, mbox_sts[0])); 2204f4f5df23SVikas Chaudhary return QLA_ERROR; 2205f4f5df23SVikas Chaudhary } 2206f4f5df23SVikas Chaudhary return QLA_SUCCESS; 2207f4f5df23SVikas Chaudhary } 2208f4f5df23SVikas Chaudhary 2209f4f5df23SVikas Chaudhary static int 2210f4f5df23SVikas Chaudhary qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha) 2211f4f5df23SVikas Chaudhary { 2212f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 2213f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 2214f4f5df23SVikas Chaudhary 2215f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 2216f4f5df23SVikas Chaudhary 2217f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2218f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 2219f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 2220f4f5df23SVikas Chaudhary mbox_cmd[1] = INTR_DISABLE; 2221f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 2222f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 2223f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 2224f4f5df23SVikas Chaudhary "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 2225f4f5df23SVikas Chaudhary __func__, mbox_sts[0])); 2226f4f5df23SVikas Chaudhary return QLA_ERROR; 2227f4f5df23SVikas Chaudhary } 2228f4f5df23SVikas Chaudhary 2229f4f5df23SVikas Chaudhary return QLA_SUCCESS; 2230f4f5df23SVikas Chaudhary } 2231f4f5df23SVikas Chaudhary 2232f4f5df23SVikas Chaudhary void 2233f4f5df23SVikas Chaudhary qla4_8xxx_enable_intrs(struct scsi_qla_host *ha) 2234f4f5df23SVikas Chaudhary { 2235f4f5df23SVikas Chaudhary qla4_8xxx_mbx_intr_enable(ha); 2236f4f5df23SVikas Chaudhary 2237f4f5df23SVikas Chaudhary spin_lock_irq(&ha->hardware_lock); 2238f4f5df23SVikas Chaudhary /* BIT 10 - reset */ 2239f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2240f4f5df23SVikas Chaudhary spin_unlock_irq(&ha->hardware_lock); 2241f4f5df23SVikas Chaudhary set_bit(AF_INTERRUPTS_ON, &ha->flags); 2242f4f5df23SVikas Chaudhary } 2243f4f5df23SVikas Chaudhary 2244f4f5df23SVikas Chaudhary void 2245f4f5df23SVikas Chaudhary qla4_8xxx_disable_intrs(struct scsi_qla_host *ha) 2246f4f5df23SVikas Chaudhary { 2247f4f5df23SVikas Chaudhary if (test_bit(AF_INTERRUPTS_ON, &ha->flags)) 2248f4f5df23SVikas Chaudhary qla4_8xxx_mbx_intr_disable(ha); 2249f4f5df23SVikas Chaudhary 2250f4f5df23SVikas Chaudhary spin_lock_irq(&ha->hardware_lock); 2251f4f5df23SVikas Chaudhary /* BIT 10 - set */ 2252f4f5df23SVikas Chaudhary qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2253f4f5df23SVikas Chaudhary spin_unlock_irq(&ha->hardware_lock); 2254f4f5df23SVikas Chaudhary clear_bit(AF_INTERRUPTS_ON, &ha->flags); 2255f4f5df23SVikas Chaudhary } 2256f4f5df23SVikas Chaudhary 2257f4f5df23SVikas Chaudhary struct ql4_init_msix_entry { 2258f4f5df23SVikas Chaudhary uint16_t entry; 2259f4f5df23SVikas Chaudhary uint16_t index; 2260f4f5df23SVikas Chaudhary const char *name; 2261f4f5df23SVikas Chaudhary irq_handler_t handler; 2262f4f5df23SVikas Chaudhary }; 2263f4f5df23SVikas Chaudhary 2264f4f5df23SVikas Chaudhary static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = { 2265f4f5df23SVikas Chaudhary { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT, 2266f4f5df23SVikas Chaudhary "qla4xxx (default)", 2267f4f5df23SVikas Chaudhary (irq_handler_t)qla4_8xxx_default_intr_handler }, 2268f4f5df23SVikas Chaudhary { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q, 2269f4f5df23SVikas Chaudhary "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q }, 2270f4f5df23SVikas Chaudhary }; 2271f4f5df23SVikas Chaudhary 2272f4f5df23SVikas Chaudhary void 2273f4f5df23SVikas Chaudhary qla4_8xxx_disable_msix(struct scsi_qla_host *ha) 2274f4f5df23SVikas Chaudhary { 2275f4f5df23SVikas Chaudhary int i; 2276f4f5df23SVikas Chaudhary struct ql4_msix_entry *qentry; 2277f4f5df23SVikas Chaudhary 2278f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 2279f4f5df23SVikas Chaudhary qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 2280f4f5df23SVikas Chaudhary if (qentry->have_irq) { 2281f4f5df23SVikas Chaudhary free_irq(qentry->msix_vector, ha); 2282f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 2283f4f5df23SVikas Chaudhary __func__, qla4_8xxx_msix_entries[i].name)); 2284f4f5df23SVikas Chaudhary } 2285f4f5df23SVikas Chaudhary } 2286f4f5df23SVikas Chaudhary pci_disable_msix(ha->pdev); 2287f4f5df23SVikas Chaudhary clear_bit(AF_MSIX_ENABLED, &ha->flags); 2288f4f5df23SVikas Chaudhary } 2289f4f5df23SVikas Chaudhary 2290f4f5df23SVikas Chaudhary int 2291f4f5df23SVikas Chaudhary qla4_8xxx_enable_msix(struct scsi_qla_host *ha) 2292f4f5df23SVikas Chaudhary { 2293f4f5df23SVikas Chaudhary int i, ret; 2294f4f5df23SVikas Chaudhary struct msix_entry entries[QLA_MSIX_ENTRIES]; 2295f4f5df23SVikas Chaudhary struct ql4_msix_entry *qentry; 2296f4f5df23SVikas Chaudhary 2297f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) 2298f4f5df23SVikas Chaudhary entries[i].entry = qla4_8xxx_msix_entries[i].entry; 2299f4f5df23SVikas Chaudhary 2300f4f5df23SVikas Chaudhary ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries)); 2301f4f5df23SVikas Chaudhary if (ret) { 2302f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 2303f4f5df23SVikas Chaudhary "MSI-X: Failed to enable support -- %d/%d\n", 2304f4f5df23SVikas Chaudhary QLA_MSIX_ENTRIES, ret); 2305f4f5df23SVikas Chaudhary goto msix_out; 2306f4f5df23SVikas Chaudhary } 2307f4f5df23SVikas Chaudhary set_bit(AF_MSIX_ENABLED, &ha->flags); 2308f4f5df23SVikas Chaudhary 2309f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 2310f4f5df23SVikas Chaudhary qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 2311f4f5df23SVikas Chaudhary qentry->msix_vector = entries[i].vector; 2312f4f5df23SVikas Chaudhary qentry->msix_entry = entries[i].entry; 2313f4f5df23SVikas Chaudhary qentry->have_irq = 0; 2314f4f5df23SVikas Chaudhary ret = request_irq(qentry->msix_vector, 2315f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].handler, 0, 2316f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].name, ha); 2317f4f5df23SVikas Chaudhary if (ret) { 2318f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 2319f4f5df23SVikas Chaudhary "MSI-X: Unable to register handler -- %x/%d.\n", 2320f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].index, ret); 2321f4f5df23SVikas Chaudhary qla4_8xxx_disable_msix(ha); 2322f4f5df23SVikas Chaudhary goto msix_out; 2323f4f5df23SVikas Chaudhary } 2324f4f5df23SVikas Chaudhary qentry->have_irq = 1; 2325f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 2326f4f5df23SVikas Chaudhary __func__, qla4_8xxx_msix_entries[i].name)); 2327f4f5df23SVikas Chaudhary } 2328f4f5df23SVikas Chaudhary msix_out: 2329f4f5df23SVikas Chaudhary return ret; 2330f4f5df23SVikas Chaudhary } 2331