1f4f5df23SVikas Chaudhary /* 2f4f5df23SVikas Chaudhary * QLogic iSCSI HBA Driver 37d01d069SVikas Chaudhary * Copyright (c) 2003-2010 QLogic Corporation 4f4f5df23SVikas Chaudhary * 5f4f5df23SVikas Chaudhary * See LICENSE.qla4xxx for copyright and licensing details. 6f4f5df23SVikas Chaudhary */ 7f4f5df23SVikas Chaudhary #include <linux/delay.h> 8a6751ccbSJiri Slaby #include <linux/io.h> 9f4f5df23SVikas Chaudhary #include <linux/pci.h> 10068237c8STej Parkash #include <linux/ratelimit.h> 11f4f5df23SVikas Chaudhary #include "ql4_def.h" 12f4f5df23SVikas Chaudhary #include "ql4_glbl.h" 13f4f5df23SVikas Chaudhary 14797a796aSHitoshi Mitake #include <asm-generic/io-64-nonatomic-lo-hi.h> 15797a796aSHitoshi Mitake 16f4f5df23SVikas Chaudhary #define MASK(n) DMA_BIT_MASK(n) 17f4f5df23SVikas Chaudhary #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 18f4f5df23SVikas Chaudhary #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 19f4f5df23SVikas Chaudhary #define MS_WIN(addr) (addr & 0x0ffc0000) 20f4f5df23SVikas Chaudhary #define QLA82XX_PCI_MN_2M (0) 21f4f5df23SVikas Chaudhary #define QLA82XX_PCI_MS_2M (0x80000) 22f4f5df23SVikas Chaudhary #define QLA82XX_PCI_OCM0_2M (0xc0000) 23f4f5df23SVikas Chaudhary #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 24f4f5df23SVikas Chaudhary #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 25f4f5df23SVikas Chaudhary 26f4f5df23SVikas Chaudhary /* CRB window related */ 27f4f5df23SVikas Chaudhary #define CRB_BLK(off) ((off >> 20) & 0x3f) 28f4f5df23SVikas Chaudhary #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 29f4f5df23SVikas Chaudhary #define CRB_WINDOW_2M (0x130060) 307664a1fdSVikas Chaudhary #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 31f4f5df23SVikas Chaudhary ((off) & 0xf0000)) 32f4f5df23SVikas Chaudhary #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 33f4f5df23SVikas Chaudhary #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 34f4f5df23SVikas Chaudhary #define CRB_INDIRECT_2M (0x1e0000UL) 35f4f5df23SVikas Chaudhary 36f4f5df23SVikas Chaudhary static inline void __iomem * 37f4f5df23SVikas Chaudhary qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) 38f4f5df23SVikas Chaudhary { 39f4f5df23SVikas Chaudhary if ((off < ha->first_page_group_end) && 40f4f5df23SVikas Chaudhary (off >= ha->first_page_group_start)) 41f4f5df23SVikas Chaudhary return (void __iomem *)(ha->nx_pcibase + off); 42f4f5df23SVikas Chaudhary 43f4f5df23SVikas Chaudhary return NULL; 44f4f5df23SVikas Chaudhary } 45f4f5df23SVikas Chaudhary 46f4f5df23SVikas Chaudhary #define MAX_CRB_XFORM 60 47f4f5df23SVikas Chaudhary static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 48f4f5df23SVikas Chaudhary static int qla4_8xxx_crb_table_initialized; 49f4f5df23SVikas Chaudhary 50f4f5df23SVikas Chaudhary #define qla4_8xxx_crb_addr_transform(name) \ 51f4f5df23SVikas Chaudhary (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 52f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 53f4f5df23SVikas Chaudhary static void 54f8086f4fSVikas Chaudhary qla4_82xx_crb_addr_transform_setup(void) 55f4f5df23SVikas Chaudhary { 56f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(XDMA); 57f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(TIMR); 58f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SRE); 59f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN3); 60f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN2); 61f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN1); 62f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN0); 63f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS3); 64f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS2); 65f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS1); 66f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS0); 67f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX7); 68f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX6); 69f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX5); 70f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX4); 71f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX3); 72f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX2); 73f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX1); 74f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX0); 75f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(ROMUSB); 76f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SN); 77f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(QMN); 78f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(QMS); 79f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGNI); 80f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGND); 81f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN3); 82f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN2); 83f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN1); 84f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN0); 85f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGSI); 86f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGSD); 87f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS3); 88f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS2); 89f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS1); 90f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS0); 91f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PS); 92f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PH); 93f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(NIU); 94f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(I2Q); 95f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(EG); 96f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(MN); 97f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(MS); 98f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS2); 99f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS1); 100f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS0); 101f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAM); 102f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(C2C1); 103f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(C2C0); 104f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SMB); 105f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(OCM0); 106f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(I2C0); 107f4f5df23SVikas Chaudhary 108f4f5df23SVikas Chaudhary qla4_8xxx_crb_table_initialized = 1; 109f4f5df23SVikas Chaudhary } 110f4f5df23SVikas Chaudhary 111f4f5df23SVikas Chaudhary static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 112f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 0: PCI */ 113f4f5df23SVikas Chaudhary {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 114f4f5df23SVikas Chaudhary {1, 0x0110000, 0x0120000, 0x130000}, 115f4f5df23SVikas Chaudhary {1, 0x0120000, 0x0122000, 0x124000}, 116f4f5df23SVikas Chaudhary {1, 0x0130000, 0x0132000, 0x126000}, 117f4f5df23SVikas Chaudhary {1, 0x0140000, 0x0142000, 0x128000}, 118f4f5df23SVikas Chaudhary {1, 0x0150000, 0x0152000, 0x12a000}, 119f4f5df23SVikas Chaudhary {1, 0x0160000, 0x0170000, 0x110000}, 120f4f5df23SVikas Chaudhary {1, 0x0170000, 0x0172000, 0x12e000}, 121f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 122f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 123f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 124f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 125f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 126f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 127f4f5df23SVikas Chaudhary {1, 0x01e0000, 0x01e0800, 0x122000}, 128f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000} } }, 129f4f5df23SVikas Chaudhary {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 130f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 3: */ 131f4f5df23SVikas Chaudhary {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 132f4f5df23SVikas Chaudhary {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 133f4f5df23SVikas Chaudhary {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 134f4f5df23SVikas Chaudhary {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 135f4f5df23SVikas Chaudhary {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 136f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 137f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 138f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 139f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 140f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 141f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 142f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 143f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 144f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 145f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 146f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 147f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 148f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 149f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 150f4f5df23SVikas Chaudhary {1, 0x08f0000, 0x08f2000, 0x172000} } }, 151f4f5df23SVikas Chaudhary {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 152f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 153f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 154f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 155f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 156f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 157f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 158f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 159f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 160f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 161f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 162f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 163f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 164f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 165f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 166f4f5df23SVikas Chaudhary {1, 0x09f0000, 0x09f2000, 0x176000} } }, 167f4f5df23SVikas Chaudhary {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 168f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 169f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 170f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 171f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 172f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 173f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 174f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 175f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 176f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 177f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 178f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 179f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 180f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 181f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 182f4f5df23SVikas Chaudhary {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 183f4f5df23SVikas Chaudhary {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 184f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 185f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 186f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 187f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 188f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 189f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 190f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 191f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 192f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 193f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 194f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 195f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 196f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 197f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 198f4f5df23SVikas Chaudhary {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 199f4f5df23SVikas Chaudhary {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 200f4f5df23SVikas Chaudhary {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 201f4f5df23SVikas Chaudhary {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 202f4f5df23SVikas Chaudhary {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 203f4f5df23SVikas Chaudhary {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 204f4f5df23SVikas Chaudhary {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 205f4f5df23SVikas Chaudhary {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 206f4f5df23SVikas Chaudhary {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 207f4f5df23SVikas Chaudhary {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 208f4f5df23SVikas Chaudhary {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 209f4f5df23SVikas Chaudhary {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 210f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 23: */ 211f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 24: */ 212f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 25: */ 213f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 26: */ 214f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 27: */ 215f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 28: */ 216f4f5df23SVikas Chaudhary {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 217f4f5df23SVikas Chaudhary {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 218f4f5df23SVikas Chaudhary {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 219f4f5df23SVikas Chaudhary {{{0} } }, /* 32: PCI */ 220f4f5df23SVikas Chaudhary {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 221f4f5df23SVikas Chaudhary {1, 0x2110000, 0x2120000, 0x130000}, 222f4f5df23SVikas Chaudhary {1, 0x2120000, 0x2122000, 0x124000}, 223f4f5df23SVikas Chaudhary {1, 0x2130000, 0x2132000, 0x126000}, 224f4f5df23SVikas Chaudhary {1, 0x2140000, 0x2142000, 0x128000}, 225f4f5df23SVikas Chaudhary {1, 0x2150000, 0x2152000, 0x12a000}, 226f4f5df23SVikas Chaudhary {1, 0x2160000, 0x2170000, 0x110000}, 227f4f5df23SVikas Chaudhary {1, 0x2170000, 0x2172000, 0x12e000}, 228f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 229f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 230f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 231f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 232f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 233f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 234f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 235f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000} } }, 236f4f5df23SVikas Chaudhary {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 237f4f5df23SVikas Chaudhary {{{0} } }, /* 35: */ 238f4f5df23SVikas Chaudhary {{{0} } }, /* 36: */ 239f4f5df23SVikas Chaudhary {{{0} } }, /* 37: */ 240f4f5df23SVikas Chaudhary {{{0} } }, /* 38: */ 241f4f5df23SVikas Chaudhary {{{0} } }, /* 39: */ 242f4f5df23SVikas Chaudhary {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 243f4f5df23SVikas Chaudhary {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 244f4f5df23SVikas Chaudhary {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 245f4f5df23SVikas Chaudhary {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 246f4f5df23SVikas Chaudhary {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 247f4f5df23SVikas Chaudhary {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 248f4f5df23SVikas Chaudhary {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 249f4f5df23SVikas Chaudhary {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 250f4f5df23SVikas Chaudhary {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 251f4f5df23SVikas Chaudhary {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 252f4f5df23SVikas Chaudhary {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 253f4f5df23SVikas Chaudhary {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 254f4f5df23SVikas Chaudhary {{{0} } }, /* 52: */ 255f4f5df23SVikas Chaudhary {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 256f4f5df23SVikas Chaudhary {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 257f4f5df23SVikas Chaudhary {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 258f4f5df23SVikas Chaudhary {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 259f4f5df23SVikas Chaudhary {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 260f4f5df23SVikas Chaudhary {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 261f4f5df23SVikas Chaudhary {{{0} } }, /* 59: I2C0 */ 262f4f5df23SVikas Chaudhary {{{0} } }, /* 60: I2C1 */ 263f4f5df23SVikas Chaudhary {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ 264f4f5df23SVikas Chaudhary {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 265f4f5df23SVikas Chaudhary {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 266f4f5df23SVikas Chaudhary }; 267f4f5df23SVikas Chaudhary 268f4f5df23SVikas Chaudhary /* 269f4f5df23SVikas Chaudhary * top 12 bits of crb internal address (hub, agent) 270f4f5df23SVikas Chaudhary */ 2717664a1fdSVikas Chaudhary static unsigned qla4_82xx_crb_hub_agt[64] = { 272f4f5df23SVikas Chaudhary 0, 273f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 274f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 275f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 276f4f5df23SVikas Chaudhary 0, 277f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 278f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 279f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 280f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 281f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 282f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 283f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 284f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 285f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 286f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 287f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 288f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 289f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 290f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 291f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 292f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 293f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 294f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 295f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 296f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 297f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 298f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 299f4f5df23SVikas Chaudhary 0, 300f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 301f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 302f4f5df23SVikas Chaudhary 0, 303f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 304f4f5df23SVikas Chaudhary 0, 305f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 306f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 307f4f5df23SVikas Chaudhary 0, 308f4f5df23SVikas Chaudhary 0, 309f4f5df23SVikas Chaudhary 0, 310f4f5df23SVikas Chaudhary 0, 311f4f5df23SVikas Chaudhary 0, 312f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 313f4f5df23SVikas Chaudhary 0, 314f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 315f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 316f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 317f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 318f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 319f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 320f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 321f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 322f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 323f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 324f4f5df23SVikas Chaudhary 0, 325f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 326f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 327f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 328f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 329f4f5df23SVikas Chaudhary 0, 330f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 331f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 332f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 333f4f5df23SVikas Chaudhary 0, 334f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 335f4f5df23SVikas Chaudhary 0, 336f4f5df23SVikas Chaudhary }; 337f4f5df23SVikas Chaudhary 338f4f5df23SVikas Chaudhary /* Device states */ 339f4f5df23SVikas Chaudhary static char *qdev_state[] = { 340f4f5df23SVikas Chaudhary "Unknown", 341f4f5df23SVikas Chaudhary "Cold", 342f4f5df23SVikas Chaudhary "Initializing", 343f4f5df23SVikas Chaudhary "Ready", 344f4f5df23SVikas Chaudhary "Need Reset", 345f4f5df23SVikas Chaudhary "Need Quiescent", 346f4f5df23SVikas Chaudhary "Failed", 347f4f5df23SVikas Chaudhary "Quiescent", 348f4f5df23SVikas Chaudhary }; 349f4f5df23SVikas Chaudhary 350f4f5df23SVikas Chaudhary /* 351f4f5df23SVikas Chaudhary * In: 'off' is offset from CRB space in 128M pci map 352f4f5df23SVikas Chaudhary * Out: 'off' is 2M pci map addr 353f4f5df23SVikas Chaudhary * side effect: lock crb window 354f4f5df23SVikas Chaudhary */ 355f4f5df23SVikas Chaudhary static void 356f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) 357f4f5df23SVikas Chaudhary { 358f4f5df23SVikas Chaudhary u32 win_read; 359f4f5df23SVikas Chaudhary 360f4f5df23SVikas Chaudhary ha->crb_win = CRB_HI(*off); 361f4f5df23SVikas Chaudhary writel(ha->crb_win, 362f4f5df23SVikas Chaudhary (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 363f4f5df23SVikas Chaudhary 364f4f5df23SVikas Chaudhary /* Read back value to make sure write has gone through before trying 365f4f5df23SVikas Chaudhary * to use it. */ 366f4f5df23SVikas Chaudhary win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 367f4f5df23SVikas Chaudhary if (win_read != ha->crb_win) { 368f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 369f4f5df23SVikas Chaudhary "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," 370f4f5df23SVikas Chaudhary " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 371f4f5df23SVikas Chaudhary } 372f4f5df23SVikas Chaudhary *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 373f4f5df23SVikas Chaudhary } 374f4f5df23SVikas Chaudhary 375f4f5df23SVikas Chaudhary void 376f8086f4fSVikas Chaudhary qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) 377f4f5df23SVikas Chaudhary { 378f4f5df23SVikas Chaudhary unsigned long flags = 0; 379f4f5df23SVikas Chaudhary int rv; 380f4f5df23SVikas Chaudhary 381f8086f4fSVikas Chaudhary rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); 382f4f5df23SVikas Chaudhary 383f4f5df23SVikas Chaudhary BUG_ON(rv == -1); 384f4f5df23SVikas Chaudhary 385f4f5df23SVikas Chaudhary if (rv == 1) { 386f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 387f8086f4fSVikas Chaudhary qla4_82xx_crb_win_lock(ha); 388f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(ha, &off); 389f4f5df23SVikas Chaudhary } 390f4f5df23SVikas Chaudhary 391f4f5df23SVikas Chaudhary writel(data, (void __iomem *)off); 392f4f5df23SVikas Chaudhary 393f4f5df23SVikas Chaudhary if (rv == 1) { 394f8086f4fSVikas Chaudhary qla4_82xx_crb_win_unlock(ha); 395f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 396f4f5df23SVikas Chaudhary } 397f4f5df23SVikas Chaudhary } 398f4f5df23SVikas Chaudhary 399f4f5df23SVikas Chaudhary int 400f8086f4fSVikas Chaudhary qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off) 401f4f5df23SVikas Chaudhary { 402f4f5df23SVikas Chaudhary unsigned long flags = 0; 403f4f5df23SVikas Chaudhary int rv; 404f4f5df23SVikas Chaudhary u32 data; 405f4f5df23SVikas Chaudhary 406f8086f4fSVikas Chaudhary rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); 407f4f5df23SVikas Chaudhary 408f4f5df23SVikas Chaudhary BUG_ON(rv == -1); 409f4f5df23SVikas Chaudhary 410f4f5df23SVikas Chaudhary if (rv == 1) { 411f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 412f8086f4fSVikas Chaudhary qla4_82xx_crb_win_lock(ha); 413f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(ha, &off); 414f4f5df23SVikas Chaudhary } 415f4f5df23SVikas Chaudhary data = readl((void __iomem *)off); 416f4f5df23SVikas Chaudhary 417f4f5df23SVikas Chaudhary if (rv == 1) { 418f8086f4fSVikas Chaudhary qla4_82xx_crb_win_unlock(ha); 419f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 420f4f5df23SVikas Chaudhary } 421f4f5df23SVikas Chaudhary return data; 422f4f5df23SVikas Chaudhary } 423f4f5df23SVikas Chaudhary 424068237c8STej Parkash /* Minidump related functions */ 425068237c8STej Parkash static int qla4_8xxx_md_rw_32(struct scsi_qla_host *ha, uint32_t off, 426068237c8STej Parkash u32 data, uint8_t flag) 427068237c8STej Parkash { 428068237c8STej Parkash uint32_t win_read, off_value, rval = QLA_SUCCESS; 429068237c8STej Parkash 430068237c8STej Parkash off_value = off & 0xFFFF0000; 431068237c8STej Parkash writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 432068237c8STej Parkash 433068237c8STej Parkash /* Read back value to make sure write has gone through before trying 434068237c8STej Parkash * to use it. 435068237c8STej Parkash */ 436068237c8STej Parkash win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 437068237c8STej Parkash if (win_read != off_value) { 438068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 439068237c8STej Parkash "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 440068237c8STej Parkash __func__, off_value, win_read, off)); 441068237c8STej Parkash return QLA_ERROR; 442068237c8STej Parkash } 443068237c8STej Parkash 444068237c8STej Parkash off_value = off & 0x0000FFFF; 445068237c8STej Parkash 446068237c8STej Parkash if (flag) 447068237c8STej Parkash writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M + 448068237c8STej Parkash ha->nx_pcibase)); 449068237c8STej Parkash else 450068237c8STej Parkash rval = readl((void __iomem *)(off_value + CRB_INDIRECT_2M + 451068237c8STej Parkash ha->nx_pcibase)); 452068237c8STej Parkash 453068237c8STej Parkash return rval; 454068237c8STej Parkash } 455068237c8STej Parkash 456f4f5df23SVikas Chaudhary #define CRB_WIN_LOCK_TIMEOUT 100000000 457f4f5df23SVikas Chaudhary 458f8086f4fSVikas Chaudhary int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha) 459f4f5df23SVikas Chaudhary { 460f4f5df23SVikas Chaudhary int i; 461f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 462f4f5df23SVikas Chaudhary 463f4f5df23SVikas Chaudhary while (!done) { 464f4f5df23SVikas Chaudhary /* acquire semaphore3 from PCI HW block */ 465f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 466f4f5df23SVikas Chaudhary if (done == 1) 467f4f5df23SVikas Chaudhary break; 468f4f5df23SVikas Chaudhary if (timeout >= CRB_WIN_LOCK_TIMEOUT) 469f4f5df23SVikas Chaudhary return -1; 470f4f5df23SVikas Chaudhary 471f4f5df23SVikas Chaudhary timeout++; 472f4f5df23SVikas Chaudhary 473f4f5df23SVikas Chaudhary /* Yield CPU */ 474f4f5df23SVikas Chaudhary if (!in_interrupt()) 475f4f5df23SVikas Chaudhary schedule(); 476f4f5df23SVikas Chaudhary else { 477f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 478f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 479f4f5df23SVikas Chaudhary } 480f4f5df23SVikas Chaudhary } 481f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); 482f4f5df23SVikas Chaudhary return 0; 483f4f5df23SVikas Chaudhary } 484f4f5df23SVikas Chaudhary 485f8086f4fSVikas Chaudhary void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha) 486f4f5df23SVikas Chaudhary { 487f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 488f4f5df23SVikas Chaudhary } 489f4f5df23SVikas Chaudhary 490f4f5df23SVikas Chaudhary #define IDC_LOCK_TIMEOUT 100000000 491f4f5df23SVikas Chaudhary 492f4f5df23SVikas Chaudhary /** 493f8086f4fSVikas Chaudhary * qla4_82xx_idc_lock - hw_lock 494f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 495f4f5df23SVikas Chaudhary * 496f4f5df23SVikas Chaudhary * General purpose lock used to synchronize access to 497f4f5df23SVikas Chaudhary * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. 498f4f5df23SVikas Chaudhary **/ 499f8086f4fSVikas Chaudhary int qla4_82xx_idc_lock(struct scsi_qla_host *ha) 500f4f5df23SVikas Chaudhary { 501f4f5df23SVikas Chaudhary int i; 502f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 503f4f5df23SVikas Chaudhary 504f4f5df23SVikas Chaudhary while (!done) { 505f4f5df23SVikas Chaudhary /* acquire semaphore5 from PCI HW block */ 506f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 507f4f5df23SVikas Chaudhary if (done == 1) 508f4f5df23SVikas Chaudhary break; 509f4f5df23SVikas Chaudhary if (timeout >= IDC_LOCK_TIMEOUT) 510f4f5df23SVikas Chaudhary return -1; 511f4f5df23SVikas Chaudhary 512f4f5df23SVikas Chaudhary timeout++; 513f4f5df23SVikas Chaudhary 514f4f5df23SVikas Chaudhary /* Yield CPU */ 515f4f5df23SVikas Chaudhary if (!in_interrupt()) 516f4f5df23SVikas Chaudhary schedule(); 517f4f5df23SVikas Chaudhary else { 518f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 519f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 520f4f5df23SVikas Chaudhary } 521f4f5df23SVikas Chaudhary } 522f4f5df23SVikas Chaudhary return 0; 523f4f5df23SVikas Chaudhary } 524f4f5df23SVikas Chaudhary 525f8086f4fSVikas Chaudhary void qla4_82xx_idc_unlock(struct scsi_qla_host *ha) 526f4f5df23SVikas Chaudhary { 527f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 528f4f5df23SVikas Chaudhary } 529f4f5df23SVikas Chaudhary 530f4f5df23SVikas Chaudhary int 531f8086f4fSVikas Chaudhary qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) 532f4f5df23SVikas Chaudhary { 533f4f5df23SVikas Chaudhary struct crb_128M_2M_sub_block_map *m; 534f4f5df23SVikas Chaudhary 535f4f5df23SVikas Chaudhary if (*off >= QLA82XX_CRB_MAX) 536f4f5df23SVikas Chaudhary return -1; 537f4f5df23SVikas Chaudhary 538f4f5df23SVikas Chaudhary if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 539f4f5df23SVikas Chaudhary *off = (*off - QLA82XX_PCI_CAMQM) + 540f4f5df23SVikas Chaudhary QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 541f4f5df23SVikas Chaudhary return 0; 542f4f5df23SVikas Chaudhary } 543f4f5df23SVikas Chaudhary 544f4f5df23SVikas Chaudhary if (*off < QLA82XX_PCI_CRBSPACE) 545f4f5df23SVikas Chaudhary return -1; 546f4f5df23SVikas Chaudhary 547f4f5df23SVikas Chaudhary *off -= QLA82XX_PCI_CRBSPACE; 548f4f5df23SVikas Chaudhary /* 549f4f5df23SVikas Chaudhary * Try direct map 550f4f5df23SVikas Chaudhary */ 551f4f5df23SVikas Chaudhary 552f4f5df23SVikas Chaudhary m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 553f4f5df23SVikas Chaudhary 554f4f5df23SVikas Chaudhary if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 555f4f5df23SVikas Chaudhary *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 556f4f5df23SVikas Chaudhary return 0; 557f4f5df23SVikas Chaudhary } 558f4f5df23SVikas Chaudhary 559f4f5df23SVikas Chaudhary /* 560f4f5df23SVikas Chaudhary * Not in direct map, use crb window 561f4f5df23SVikas Chaudhary */ 562f4f5df23SVikas Chaudhary return 1; 563f4f5df23SVikas Chaudhary } 564f4f5df23SVikas Chaudhary 565f4f5df23SVikas Chaudhary /* PCI Windowing for DDR regions. */ 566f4f5df23SVikas Chaudhary #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 567f4f5df23SVikas Chaudhary (((addr) <= (high)) && ((addr) >= (low))) 568f4f5df23SVikas Chaudhary 569f4f5df23SVikas Chaudhary /* 570f4f5df23SVikas Chaudhary * check memory access boundary. 571f4f5df23SVikas Chaudhary * used by test agent. support ddr access only for now 572f4f5df23SVikas Chaudhary */ 573f4f5df23SVikas Chaudhary static unsigned long 574f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha, 575f4f5df23SVikas Chaudhary unsigned long long addr, int size) 576f4f5df23SVikas Chaudhary { 577f4f5df23SVikas Chaudhary if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 578f4f5df23SVikas Chaudhary QLA82XX_ADDR_DDR_NET_MAX) || 579f4f5df23SVikas Chaudhary !QLA82XX_ADDR_IN_RANGE(addr + size - 1, 580f4f5df23SVikas Chaudhary QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) || 581f4f5df23SVikas Chaudhary ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { 582f4f5df23SVikas Chaudhary return 0; 583f4f5df23SVikas Chaudhary } 584f4f5df23SVikas Chaudhary return 1; 585f4f5df23SVikas Chaudhary } 586f4f5df23SVikas Chaudhary 5877664a1fdSVikas Chaudhary static int qla4_82xx_pci_set_window_warning_count; 588f4f5df23SVikas Chaudhary 589f4f5df23SVikas Chaudhary static unsigned long 590f8086f4fSVikas Chaudhary qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) 591f4f5df23SVikas Chaudhary { 592f4f5df23SVikas Chaudhary int window; 593f4f5df23SVikas Chaudhary u32 win_read; 594f4f5df23SVikas Chaudhary 595f4f5df23SVikas Chaudhary if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 596f4f5df23SVikas Chaudhary QLA82XX_ADDR_DDR_NET_MAX)) { 597f4f5df23SVikas Chaudhary /* DDR network side */ 598f4f5df23SVikas Chaudhary window = MN_WIN(addr); 599f4f5df23SVikas Chaudhary ha->ddr_mn_window = window; 600f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->mn_win_crb | 601f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 602f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | 603f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE); 604f4f5df23SVikas Chaudhary if ((win_read << 17) != window) { 605f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 606f4f5df23SVikas Chaudhary "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 607f4f5df23SVikas Chaudhary __func__, window, win_read); 608f4f5df23SVikas Chaudhary } 609f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 610f4f5df23SVikas Chaudhary } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 611f4f5df23SVikas Chaudhary QLA82XX_ADDR_OCM0_MAX)) { 612f4f5df23SVikas Chaudhary unsigned int temp1; 613f4f5df23SVikas Chaudhary /* if bits 19:18&17:11 are on */ 614f4f5df23SVikas Chaudhary if ((addr & 0x00ff800) == 0xff800) { 615f4f5df23SVikas Chaudhary printk("%s: QM access not handled.\n", __func__); 616f4f5df23SVikas Chaudhary addr = -1UL; 617f4f5df23SVikas Chaudhary } 618f4f5df23SVikas Chaudhary 619f4f5df23SVikas Chaudhary window = OCM_WIN(addr); 620f4f5df23SVikas Chaudhary ha->ddr_mn_window = window; 621f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->mn_win_crb | 622f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 623f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | 624f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE); 625f4f5df23SVikas Chaudhary temp1 = ((window & 0x1FF) << 7) | 626f4f5df23SVikas Chaudhary ((window & 0x0FFFE0000) >> 17); 627f4f5df23SVikas Chaudhary if (win_read != temp1) { 628f4f5df23SVikas Chaudhary printk("%s: Written OCMwin (0x%x) != Read" 629f4f5df23SVikas Chaudhary " OCMwin (0x%x)\n", __func__, temp1, win_read); 630f4f5df23SVikas Chaudhary } 631f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 632f4f5df23SVikas Chaudhary 633f4f5df23SVikas Chaudhary } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 634f4f5df23SVikas Chaudhary QLA82XX_P3_ADDR_QDR_NET_MAX)) { 635f4f5df23SVikas Chaudhary /* QDR network side */ 636f4f5df23SVikas Chaudhary window = MS_WIN(addr); 637f4f5df23SVikas Chaudhary ha->qdr_sn_window = window; 638f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->ms_win_crb | 639f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 640f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, 641f4f5df23SVikas Chaudhary ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 642f4f5df23SVikas Chaudhary if (win_read != window) { 643f4f5df23SVikas Chaudhary printk("%s: Written MSwin (0x%x) != Read " 644f4f5df23SVikas Chaudhary "MSwin (0x%x)\n", __func__, window, win_read); 645f4f5df23SVikas Chaudhary } 646f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 647f4f5df23SVikas Chaudhary 648f4f5df23SVikas Chaudhary } else { 649f4f5df23SVikas Chaudhary /* 650f4f5df23SVikas Chaudhary * peg gdb frequently accesses memory that doesn't exist, 651f4f5df23SVikas Chaudhary * this limits the chit chat so debugging isn't slowed down. 652f4f5df23SVikas Chaudhary */ 6537664a1fdSVikas Chaudhary if ((qla4_82xx_pci_set_window_warning_count++ < 8) || 6547664a1fdSVikas Chaudhary (qla4_82xx_pci_set_window_warning_count%64 == 0)) { 655f4f5df23SVikas Chaudhary printk("%s: Warning:%s Unknown address range!\n", 656f4f5df23SVikas Chaudhary __func__, DRIVER_NAME); 657f4f5df23SVikas Chaudhary } 658f4f5df23SVikas Chaudhary addr = -1UL; 659f4f5df23SVikas Chaudhary } 660f4f5df23SVikas Chaudhary return addr; 661f4f5df23SVikas Chaudhary } 662f4f5df23SVikas Chaudhary 663f4f5df23SVikas Chaudhary /* check if address is in the same windows as the previous access */ 664f8086f4fSVikas Chaudhary static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha, 665f4f5df23SVikas Chaudhary unsigned long long addr) 666f4f5df23SVikas Chaudhary { 667f4f5df23SVikas Chaudhary int window; 668f4f5df23SVikas Chaudhary unsigned long long qdr_max; 669f4f5df23SVikas Chaudhary 670f4f5df23SVikas Chaudhary qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 671f4f5df23SVikas Chaudhary 672f4f5df23SVikas Chaudhary if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 673f4f5df23SVikas Chaudhary QLA82XX_ADDR_DDR_NET_MAX)) { 674f4f5df23SVikas Chaudhary /* DDR network side */ 675f4f5df23SVikas Chaudhary BUG(); /* MN access can not come here */ 676f4f5df23SVikas Chaudhary } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 677f4f5df23SVikas Chaudhary QLA82XX_ADDR_OCM0_MAX)) { 678f4f5df23SVikas Chaudhary return 1; 679f4f5df23SVikas Chaudhary } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 680f4f5df23SVikas Chaudhary QLA82XX_ADDR_OCM1_MAX)) { 681f4f5df23SVikas Chaudhary return 1; 682f4f5df23SVikas Chaudhary } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 683f4f5df23SVikas Chaudhary qdr_max)) { 684f4f5df23SVikas Chaudhary /* QDR network side */ 685f4f5df23SVikas Chaudhary window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 686f4f5df23SVikas Chaudhary if (ha->qdr_sn_window == window) 687f4f5df23SVikas Chaudhary return 1; 688f4f5df23SVikas Chaudhary } 689f4f5df23SVikas Chaudhary 690f4f5df23SVikas Chaudhary return 0; 691f4f5df23SVikas Chaudhary } 692f4f5df23SVikas Chaudhary 693f8086f4fSVikas Chaudhary static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha, 694f4f5df23SVikas Chaudhary u64 off, void *data, int size) 695f4f5df23SVikas Chaudhary { 696f4f5df23SVikas Chaudhary unsigned long flags; 697f4f5df23SVikas Chaudhary void __iomem *addr; 698f4f5df23SVikas Chaudhary int ret = 0; 699f4f5df23SVikas Chaudhary u64 start; 700f4f5df23SVikas Chaudhary void __iomem *mem_ptr = NULL; 701f4f5df23SVikas Chaudhary unsigned long mem_base; 702f4f5df23SVikas Chaudhary unsigned long mem_page; 703f4f5df23SVikas Chaudhary 704f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 705f4f5df23SVikas Chaudhary 706f4f5df23SVikas Chaudhary /* 707f4f5df23SVikas Chaudhary * If attempting to access unknown address or straddle hw windows, 708f4f5df23SVikas Chaudhary * do not access. 709f4f5df23SVikas Chaudhary */ 710f8086f4fSVikas Chaudhary start = qla4_82xx_pci_set_window(ha, off); 711f4f5df23SVikas Chaudhary if ((start == -1UL) || 712f8086f4fSVikas Chaudhary (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 713f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 714f4f5df23SVikas Chaudhary printk(KERN_ERR"%s out of bound pci memory access. " 715f4f5df23SVikas Chaudhary "offset is 0x%llx\n", DRIVER_NAME, off); 716f4f5df23SVikas Chaudhary return -1; 717f4f5df23SVikas Chaudhary } 718f4f5df23SVikas Chaudhary 719f4f5df23SVikas Chaudhary addr = qla4_8xxx_pci_base_offsetfset(ha, start); 720f4f5df23SVikas Chaudhary if (!addr) { 721f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 722f4f5df23SVikas Chaudhary mem_base = pci_resource_start(ha->pdev, 0); 723f4f5df23SVikas Chaudhary mem_page = start & PAGE_MASK; 724f4f5df23SVikas Chaudhary /* Map two pages whenever user tries to access addresses in two 725f4f5df23SVikas Chaudhary consecutive pages. 726f4f5df23SVikas Chaudhary */ 727f4f5df23SVikas Chaudhary if (mem_page != ((start + size - 1) & PAGE_MASK)) 728f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 729f4f5df23SVikas Chaudhary else 730f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 731f4f5df23SVikas Chaudhary 732f4f5df23SVikas Chaudhary if (mem_ptr == NULL) { 733f4f5df23SVikas Chaudhary *(u8 *)data = 0; 734f4f5df23SVikas Chaudhary return -1; 735f4f5df23SVikas Chaudhary } 736f4f5df23SVikas Chaudhary addr = mem_ptr; 737f4f5df23SVikas Chaudhary addr += start & (PAGE_SIZE - 1); 738f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 739f4f5df23SVikas Chaudhary } 740f4f5df23SVikas Chaudhary 741f4f5df23SVikas Chaudhary switch (size) { 742f4f5df23SVikas Chaudhary case 1: 743f4f5df23SVikas Chaudhary *(u8 *)data = readb(addr); 744f4f5df23SVikas Chaudhary break; 745f4f5df23SVikas Chaudhary case 2: 746f4f5df23SVikas Chaudhary *(u16 *)data = readw(addr); 747f4f5df23SVikas Chaudhary break; 748f4f5df23SVikas Chaudhary case 4: 749f4f5df23SVikas Chaudhary *(u32 *)data = readl(addr); 750f4f5df23SVikas Chaudhary break; 751f4f5df23SVikas Chaudhary case 8: 752f4f5df23SVikas Chaudhary *(u64 *)data = readq(addr); 753f4f5df23SVikas Chaudhary break; 754f4f5df23SVikas Chaudhary default: 755f4f5df23SVikas Chaudhary ret = -1; 756f4f5df23SVikas Chaudhary break; 757f4f5df23SVikas Chaudhary } 758f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 759f4f5df23SVikas Chaudhary 760f4f5df23SVikas Chaudhary if (mem_ptr) 761f4f5df23SVikas Chaudhary iounmap(mem_ptr); 762f4f5df23SVikas Chaudhary return ret; 763f4f5df23SVikas Chaudhary } 764f4f5df23SVikas Chaudhary 765f4f5df23SVikas Chaudhary static int 766f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, 767f4f5df23SVikas Chaudhary void *data, int size) 768f4f5df23SVikas Chaudhary { 769f4f5df23SVikas Chaudhary unsigned long flags; 770f4f5df23SVikas Chaudhary void __iomem *addr; 771f4f5df23SVikas Chaudhary int ret = 0; 772f4f5df23SVikas Chaudhary u64 start; 773f4f5df23SVikas Chaudhary void __iomem *mem_ptr = NULL; 774f4f5df23SVikas Chaudhary unsigned long mem_base; 775f4f5df23SVikas Chaudhary unsigned long mem_page; 776f4f5df23SVikas Chaudhary 777f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 778f4f5df23SVikas Chaudhary 779f4f5df23SVikas Chaudhary /* 780f4f5df23SVikas Chaudhary * If attempting to access unknown address or straddle hw windows, 781f4f5df23SVikas Chaudhary * do not access. 782f4f5df23SVikas Chaudhary */ 783f8086f4fSVikas Chaudhary start = qla4_82xx_pci_set_window(ha, off); 784f4f5df23SVikas Chaudhary if ((start == -1UL) || 785f8086f4fSVikas Chaudhary (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 786f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 787f4f5df23SVikas Chaudhary printk(KERN_ERR"%s out of bound pci memory access. " 788f4f5df23SVikas Chaudhary "offset is 0x%llx\n", DRIVER_NAME, off); 789f4f5df23SVikas Chaudhary return -1; 790f4f5df23SVikas Chaudhary } 791f4f5df23SVikas Chaudhary 792f4f5df23SVikas Chaudhary addr = qla4_8xxx_pci_base_offsetfset(ha, start); 793f4f5df23SVikas Chaudhary if (!addr) { 794f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 795f4f5df23SVikas Chaudhary mem_base = pci_resource_start(ha->pdev, 0); 796f4f5df23SVikas Chaudhary mem_page = start & PAGE_MASK; 797f4f5df23SVikas Chaudhary /* Map two pages whenever user tries to access addresses in two 798f4f5df23SVikas Chaudhary consecutive pages. 799f4f5df23SVikas Chaudhary */ 800f4f5df23SVikas Chaudhary if (mem_page != ((start + size - 1) & PAGE_MASK)) 801f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 802f4f5df23SVikas Chaudhary else 803f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 804f4f5df23SVikas Chaudhary if (mem_ptr == NULL) 805f4f5df23SVikas Chaudhary return -1; 806f4f5df23SVikas Chaudhary 807f4f5df23SVikas Chaudhary addr = mem_ptr; 808f4f5df23SVikas Chaudhary addr += start & (PAGE_SIZE - 1); 809f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 810f4f5df23SVikas Chaudhary } 811f4f5df23SVikas Chaudhary 812f4f5df23SVikas Chaudhary switch (size) { 813f4f5df23SVikas Chaudhary case 1: 814f4f5df23SVikas Chaudhary writeb(*(u8 *)data, addr); 815f4f5df23SVikas Chaudhary break; 816f4f5df23SVikas Chaudhary case 2: 817f4f5df23SVikas Chaudhary writew(*(u16 *)data, addr); 818f4f5df23SVikas Chaudhary break; 819f4f5df23SVikas Chaudhary case 4: 820f4f5df23SVikas Chaudhary writel(*(u32 *)data, addr); 821f4f5df23SVikas Chaudhary break; 822f4f5df23SVikas Chaudhary case 8: 823f4f5df23SVikas Chaudhary writeq(*(u64 *)data, addr); 824f4f5df23SVikas Chaudhary break; 825f4f5df23SVikas Chaudhary default: 826f4f5df23SVikas Chaudhary ret = -1; 827f4f5df23SVikas Chaudhary break; 828f4f5df23SVikas Chaudhary } 829f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 830f4f5df23SVikas Chaudhary if (mem_ptr) 831f4f5df23SVikas Chaudhary iounmap(mem_ptr); 832f4f5df23SVikas Chaudhary return ret; 833f4f5df23SVikas Chaudhary } 834f4f5df23SVikas Chaudhary 835f4f5df23SVikas Chaudhary #define MTU_FUDGE_FACTOR 100 836f4f5df23SVikas Chaudhary 837f4f5df23SVikas Chaudhary static unsigned long 838f8086f4fSVikas Chaudhary qla4_82xx_decode_crb_addr(unsigned long addr) 839f4f5df23SVikas Chaudhary { 840f4f5df23SVikas Chaudhary int i; 841f4f5df23SVikas Chaudhary unsigned long base_addr, offset, pci_base; 842f4f5df23SVikas Chaudhary 843f4f5df23SVikas Chaudhary if (!qla4_8xxx_crb_table_initialized) 844f8086f4fSVikas Chaudhary qla4_82xx_crb_addr_transform_setup(); 845f4f5df23SVikas Chaudhary 846f4f5df23SVikas Chaudhary pci_base = ADDR_ERROR; 847f4f5df23SVikas Chaudhary base_addr = addr & 0xfff00000; 848f4f5df23SVikas Chaudhary offset = addr & 0x000fffff; 849f4f5df23SVikas Chaudhary 850f4f5df23SVikas Chaudhary for (i = 0; i < MAX_CRB_XFORM; i++) { 851f4f5df23SVikas Chaudhary if (crb_addr_xform[i] == base_addr) { 852f4f5df23SVikas Chaudhary pci_base = i << 20; 853f4f5df23SVikas Chaudhary break; 854f4f5df23SVikas Chaudhary } 855f4f5df23SVikas Chaudhary } 856f4f5df23SVikas Chaudhary if (pci_base == ADDR_ERROR) 857f4f5df23SVikas Chaudhary return pci_base; 858f4f5df23SVikas Chaudhary else 859f4f5df23SVikas Chaudhary return pci_base + offset; 860f4f5df23SVikas Chaudhary } 861f4f5df23SVikas Chaudhary 862f4f5df23SVikas Chaudhary static long rom_max_timeout = 100; 8637664a1fdSVikas Chaudhary static long qla4_82xx_rom_lock_timeout = 100; 864f4f5df23SVikas Chaudhary 865f4f5df23SVikas Chaudhary static int 866f8086f4fSVikas Chaudhary qla4_82xx_rom_lock(struct scsi_qla_host *ha) 867f4f5df23SVikas Chaudhary { 868f4f5df23SVikas Chaudhary int i; 869f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 870f4f5df23SVikas Chaudhary 871f4f5df23SVikas Chaudhary while (!done) { 872f4f5df23SVikas Chaudhary /* acquire semaphore2 from PCI HW block */ 873f4f5df23SVikas Chaudhary 874f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 875f4f5df23SVikas Chaudhary if (done == 1) 876f4f5df23SVikas Chaudhary break; 8777664a1fdSVikas Chaudhary if (timeout >= qla4_82xx_rom_lock_timeout) 878f4f5df23SVikas Chaudhary return -1; 879f4f5df23SVikas Chaudhary 880f4f5df23SVikas Chaudhary timeout++; 881f4f5df23SVikas Chaudhary 882f4f5df23SVikas Chaudhary /* Yield CPU */ 883f4f5df23SVikas Chaudhary if (!in_interrupt()) 884f4f5df23SVikas Chaudhary schedule(); 885f4f5df23SVikas Chaudhary else { 886f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 887f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 888f4f5df23SVikas Chaudhary } 889f4f5df23SVikas Chaudhary } 890f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 891f4f5df23SVikas Chaudhary return 0; 892f4f5df23SVikas Chaudhary } 893f4f5df23SVikas Chaudhary 894f4f5df23SVikas Chaudhary static void 895f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(struct scsi_qla_host *ha) 896f4f5df23SVikas Chaudhary { 897f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 898f4f5df23SVikas Chaudhary } 899f4f5df23SVikas Chaudhary 900f4f5df23SVikas Chaudhary static int 901f8086f4fSVikas Chaudhary qla4_82xx_wait_rom_done(struct scsi_qla_host *ha) 902f4f5df23SVikas Chaudhary { 903f4f5df23SVikas Chaudhary long timeout = 0; 904f4f5df23SVikas Chaudhary long done = 0 ; 905f4f5df23SVikas Chaudhary 906f4f5df23SVikas Chaudhary while (done == 0) { 907f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 908f4f5df23SVikas Chaudhary done &= 2; 909f4f5df23SVikas Chaudhary timeout++; 910f4f5df23SVikas Chaudhary if (timeout >= rom_max_timeout) { 911f4f5df23SVikas Chaudhary printk("%s: Timeout reached waiting for rom done", 912f4f5df23SVikas Chaudhary DRIVER_NAME); 913f4f5df23SVikas Chaudhary return -1; 914f4f5df23SVikas Chaudhary } 915f4f5df23SVikas Chaudhary } 916f4f5df23SVikas Chaudhary return 0; 917f4f5df23SVikas Chaudhary } 918f4f5df23SVikas Chaudhary 919f4f5df23SVikas Chaudhary static int 920f8086f4fSVikas Chaudhary qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 921f4f5df23SVikas Chaudhary { 922f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 923f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 924f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 925f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 926f8086f4fSVikas Chaudhary if (qla4_82xx_wait_rom_done(ha)) { 927f4f5df23SVikas Chaudhary printk("%s: Error waiting for rom done\n", DRIVER_NAME); 928f4f5df23SVikas Chaudhary return -1; 929f4f5df23SVikas Chaudhary } 930f4f5df23SVikas Chaudhary /* reset abyte_cnt and dummy_byte_cnt */ 931f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 932f4f5df23SVikas Chaudhary udelay(10); 933f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 934f4f5df23SVikas Chaudhary 935f8086f4fSVikas Chaudhary *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 936f4f5df23SVikas Chaudhary return 0; 937f4f5df23SVikas Chaudhary } 938f4f5df23SVikas Chaudhary 939f4f5df23SVikas Chaudhary static int 940f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 941f4f5df23SVikas Chaudhary { 942f4f5df23SVikas Chaudhary int ret, loops = 0; 943f4f5df23SVikas Chaudhary 944f8086f4fSVikas Chaudhary while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { 945f4f5df23SVikas Chaudhary udelay(100); 946f4f5df23SVikas Chaudhary loops++; 947f4f5df23SVikas Chaudhary } 948f4f5df23SVikas Chaudhary if (loops >= 50000) { 949f8086f4fSVikas Chaudhary ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n", 950f8086f4fSVikas Chaudhary DRIVER_NAME); 951f4f5df23SVikas Chaudhary return -1; 952f4f5df23SVikas Chaudhary } 953f8086f4fSVikas Chaudhary ret = qla4_82xx_do_rom_fast_read(ha, addr, valp); 954f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 955f4f5df23SVikas Chaudhary return ret; 956f4f5df23SVikas Chaudhary } 957f4f5df23SVikas Chaudhary 958f4f5df23SVikas Chaudhary /** 959f4f5df23SVikas Chaudhary * This routine does CRB initialize sequence 960f4f5df23SVikas Chaudhary * to put the ISP into operational state 961f4f5df23SVikas Chaudhary **/ 962f4f5df23SVikas Chaudhary static int 963f8086f4fSVikas Chaudhary qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) 964f4f5df23SVikas Chaudhary { 965f4f5df23SVikas Chaudhary int addr, val; 966f4f5df23SVikas Chaudhary int i ; 967f4f5df23SVikas Chaudhary struct crb_addr_pair *buf; 968f4f5df23SVikas Chaudhary unsigned long off; 969f4f5df23SVikas Chaudhary unsigned offset, n; 970f4f5df23SVikas Chaudhary 971f4f5df23SVikas Chaudhary struct crb_addr_pair { 972f4f5df23SVikas Chaudhary long addr; 973f4f5df23SVikas Chaudhary long data; 974f4f5df23SVikas Chaudhary }; 975f4f5df23SVikas Chaudhary 976f4f5df23SVikas Chaudhary /* Halt all the indiviual PEGs and other blocks of the ISP */ 977f8086f4fSVikas Chaudhary qla4_82xx_rom_lock(ha); 978a1fc26baSSwapnil Nagle 979cb74428eSVikas Chaudhary /* disable all I2Q */ 980f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 981f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 982f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 983f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 984f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 985f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 986cb74428eSVikas Chaudhary 987cb74428eSVikas Chaudhary /* disable all niu interrupts */ 988f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 989a1fc26baSSwapnil Nagle /* disable xge rx/tx */ 990f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 991a1fc26baSSwapnil Nagle /* disable xg1 rx/tx */ 992f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 993cb74428eSVikas Chaudhary /* disable sideband mac */ 994f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 995cb74428eSVikas Chaudhary /* disable ap0 mac */ 996f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 997cb74428eSVikas Chaudhary /* disable ap1 mac */ 998f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 999a1fc26baSSwapnil Nagle 1000a1fc26baSSwapnil Nagle /* halt sre */ 1001f8086f4fSVikas Chaudhary val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1002f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1003a1fc26baSSwapnil Nagle 1004a1fc26baSSwapnil Nagle /* halt epg */ 1005f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1006a1fc26baSSwapnil Nagle 1007a1fc26baSSwapnil Nagle /* halt timers */ 1008f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1009f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1010f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1011f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1012f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1013f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1014a1fc26baSSwapnil Nagle 1015a1fc26baSSwapnil Nagle /* halt pegs */ 1016f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1017f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1018f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1019f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1020f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1021cb74428eSVikas Chaudhary msleep(5); 1022a1fc26baSSwapnil Nagle 1023a1fc26baSSwapnil Nagle /* big hammer */ 1024f4f5df23SVikas Chaudhary if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 1025f4f5df23SVikas Chaudhary /* don't reset CAM block on reset */ 1026f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1027f4f5df23SVikas Chaudhary else 1028f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1029f4f5df23SVikas Chaudhary 1030f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 1031f4f5df23SVikas Chaudhary 1032f4f5df23SVikas Chaudhary /* Read the signature value from the flash. 1033f4f5df23SVikas Chaudhary * Offset 0: Contain signature (0xcafecafe) 1034f4f5df23SVikas Chaudhary * Offset 4: Offset and number of addr/value pairs 1035f4f5df23SVikas Chaudhary * that present in CRB initialize sequence 1036f4f5df23SVikas Chaudhary */ 1037f8086f4fSVikas Chaudhary if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1038f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(ha, 4, &n) != 0) { 1039f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1040f4f5df23SVikas Chaudhary "[ERROR] Reading crb_init area: n: %08x\n", n); 1041f4f5df23SVikas Chaudhary return -1; 1042f4f5df23SVikas Chaudhary } 1043f4f5df23SVikas Chaudhary 1044f4f5df23SVikas Chaudhary /* Offset in flash = lower 16 bits 1045f4f5df23SVikas Chaudhary * Number of enteries = upper 16 bits 1046f4f5df23SVikas Chaudhary */ 1047f4f5df23SVikas Chaudhary offset = n & 0xffffU; 1048f4f5df23SVikas Chaudhary n = (n >> 16) & 0xffffU; 1049f4f5df23SVikas Chaudhary 1050f4f5df23SVikas Chaudhary /* number of addr/value pair should not exceed 1024 enteries */ 1051f4f5df23SVikas Chaudhary if (n >= 1024) { 1052f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1053f4f5df23SVikas Chaudhary "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1054f4f5df23SVikas Chaudhary DRIVER_NAME, __func__, n); 1055f4f5df23SVikas Chaudhary return -1; 1056f4f5df23SVikas Chaudhary } 1057f4f5df23SVikas Chaudhary 1058f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1059f4f5df23SVikas Chaudhary "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); 1060f4f5df23SVikas Chaudhary 1061f4f5df23SVikas Chaudhary buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1062f4f5df23SVikas Chaudhary if (buf == NULL) { 1063f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1064f4f5df23SVikas Chaudhary "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); 1065f4f5df23SVikas Chaudhary return -1; 1066f4f5df23SVikas Chaudhary } 1067f4f5df23SVikas Chaudhary 1068f4f5df23SVikas Chaudhary for (i = 0; i < n; i++) { 1069f8086f4fSVikas Chaudhary if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1070f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 1071f4f5df23SVikas Chaudhary 0) { 1072f4f5df23SVikas Chaudhary kfree(buf); 1073f4f5df23SVikas Chaudhary return -1; 1074f4f5df23SVikas Chaudhary } 1075f4f5df23SVikas Chaudhary 1076f4f5df23SVikas Chaudhary buf[i].addr = addr; 1077f4f5df23SVikas Chaudhary buf[i].data = val; 1078f4f5df23SVikas Chaudhary } 1079f4f5df23SVikas Chaudhary 1080f4f5df23SVikas Chaudhary for (i = 0; i < n; i++) { 1081f4f5df23SVikas Chaudhary /* Translate internal CRB initialization 1082f4f5df23SVikas Chaudhary * address to PCI bus address 1083f4f5df23SVikas Chaudhary */ 1084f8086f4fSVikas Chaudhary off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1085f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE; 1086f4f5df23SVikas Chaudhary /* Not all CRB addr/value pair to be written, 1087f4f5df23SVikas Chaudhary * some of them are skipped 1088f4f5df23SVikas Chaudhary */ 1089f4f5df23SVikas Chaudhary 1090f4f5df23SVikas Chaudhary /* skip if LS bit is set*/ 1091f4f5df23SVikas Chaudhary if (off & 0x1) { 1092f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_WARNING, ha, 1093f4f5df23SVikas Chaudhary "Skip CRB init replay for offset = 0x%lx\n", off)); 1094f4f5df23SVikas Chaudhary continue; 1095f4f5df23SVikas Chaudhary } 1096f4f5df23SVikas Chaudhary 1097f4f5df23SVikas Chaudhary /* skipping cold reboot MAGIC */ 1098f4f5df23SVikas Chaudhary if (off == QLA82XX_CAM_RAM(0x1fc)) 1099f4f5df23SVikas Chaudhary continue; 1100f4f5df23SVikas Chaudhary 1101f4f5df23SVikas Chaudhary /* do not reset PCI */ 1102f4f5df23SVikas Chaudhary if (off == (ROMUSB_GLB + 0xbc)) 1103f4f5df23SVikas Chaudhary continue; 1104f4f5df23SVikas Chaudhary 1105f4f5df23SVikas Chaudhary /* skip core clock, so that firmware can increase the clock */ 1106f4f5df23SVikas Chaudhary if (off == (ROMUSB_GLB + 0xc8)) 1107f4f5df23SVikas Chaudhary continue; 1108f4f5df23SVikas Chaudhary 1109f4f5df23SVikas Chaudhary /* skip the function enable register */ 1110f4f5df23SVikas Chaudhary if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1111f4f5df23SVikas Chaudhary continue; 1112f4f5df23SVikas Chaudhary 1113f4f5df23SVikas Chaudhary if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1114f4f5df23SVikas Chaudhary continue; 1115f4f5df23SVikas Chaudhary 1116f4f5df23SVikas Chaudhary if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1117f4f5df23SVikas Chaudhary continue; 1118f4f5df23SVikas Chaudhary 1119f4f5df23SVikas Chaudhary if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1120f4f5df23SVikas Chaudhary continue; 1121f4f5df23SVikas Chaudhary 1122f4f5df23SVikas Chaudhary if (off == ADDR_ERROR) { 1123f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1124f4f5df23SVikas Chaudhary "%s: [ERROR] Unknown addr: 0x%08lx\n", 1125f4f5df23SVikas Chaudhary DRIVER_NAME, buf[i].addr); 1126f4f5df23SVikas Chaudhary continue; 1127f4f5df23SVikas Chaudhary } 1128f4f5df23SVikas Chaudhary 1129f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, off, buf[i].data); 1130f4f5df23SVikas Chaudhary 1131f4f5df23SVikas Chaudhary /* ISP requires much bigger delay to settle down, 1132f4f5df23SVikas Chaudhary * else crb_window returns 0xffffffff 1133f4f5df23SVikas Chaudhary */ 1134f4f5df23SVikas Chaudhary if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1135f4f5df23SVikas Chaudhary msleep(1000); 1136f4f5df23SVikas Chaudhary 1137f4f5df23SVikas Chaudhary /* ISP requires millisec delay between 1138f4f5df23SVikas Chaudhary * successive CRB register updation 1139f4f5df23SVikas Chaudhary */ 1140f4f5df23SVikas Chaudhary msleep(1); 1141f4f5df23SVikas Chaudhary } 1142f4f5df23SVikas Chaudhary 1143f4f5df23SVikas Chaudhary kfree(buf); 1144f4f5df23SVikas Chaudhary 1145f4f5df23SVikas Chaudhary /* Resetting the data and instruction cache */ 1146f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1147f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1148f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1149f4f5df23SVikas Chaudhary 1150f4f5df23SVikas Chaudhary /* Clear all protocol processing engines */ 1151f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1152f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1153f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1154f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1155f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1156f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1157f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1158f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1159f4f5df23SVikas Chaudhary 1160f4f5df23SVikas Chaudhary return 0; 1161f4f5df23SVikas Chaudhary } 1162f4f5df23SVikas Chaudhary 1163f4f5df23SVikas Chaudhary static int 1164f8086f4fSVikas Chaudhary qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) 1165f4f5df23SVikas Chaudhary { 11664cd83cbeSLalit Chandivade int i, rval = 0; 1167f4f5df23SVikas Chaudhary long size = 0; 1168f4f5df23SVikas Chaudhary long flashaddr, memaddr; 1169f4f5df23SVikas Chaudhary u64 data; 1170f4f5df23SVikas Chaudhary u32 high, low; 1171f4f5df23SVikas Chaudhary 1172f4f5df23SVikas Chaudhary flashaddr = memaddr = ha->hw.flt_region_bootload; 1173f4f5df23SVikas Chaudhary size = (image_start - flashaddr) / 8; 1174f4f5df23SVikas Chaudhary 1175f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", 1176f4f5df23SVikas Chaudhary ha->host_no, __func__, flashaddr, image_start)); 1177f4f5df23SVikas Chaudhary 1178f4f5df23SVikas Chaudhary for (i = 0; i < size; i++) { 1179f8086f4fSVikas Chaudhary if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1180f8086f4fSVikas Chaudhary (qla4_82xx_rom_fast_read(ha, flashaddr + 4, 1181f4f5df23SVikas Chaudhary (int *)&high))) { 11824cd83cbeSLalit Chandivade rval = -1; 11834cd83cbeSLalit Chandivade goto exit_load_from_flash; 1184f4f5df23SVikas Chaudhary } 1185f4f5df23SVikas Chaudhary data = ((u64)high << 32) | low ; 1186f8086f4fSVikas Chaudhary rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 11874cd83cbeSLalit Chandivade if (rval) 11884cd83cbeSLalit Chandivade goto exit_load_from_flash; 11894cd83cbeSLalit Chandivade 1190f4f5df23SVikas Chaudhary flashaddr += 8; 1191f4f5df23SVikas Chaudhary memaddr += 8; 1192f4f5df23SVikas Chaudhary 1193f4f5df23SVikas Chaudhary if (i % 0x1000 == 0) 1194f4f5df23SVikas Chaudhary msleep(1); 1195f4f5df23SVikas Chaudhary 1196f4f5df23SVikas Chaudhary } 1197f4f5df23SVikas Chaudhary 1198f4f5df23SVikas Chaudhary udelay(100); 1199f4f5df23SVikas Chaudhary 1200f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1201f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1202f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1203f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1204f4f5df23SVikas Chaudhary 12054cd83cbeSLalit Chandivade exit_load_from_flash: 12064cd83cbeSLalit Chandivade return rval; 1207f4f5df23SVikas Chaudhary } 1208f4f5df23SVikas Chaudhary 1209f8086f4fSVikas Chaudhary static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) 1210f4f5df23SVikas Chaudhary { 1211f4f5df23SVikas Chaudhary u32 rst; 1212f4f5df23SVikas Chaudhary 1213f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1214f8086f4fSVikas Chaudhary if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { 1215f4f5df23SVikas Chaudhary printk(KERN_WARNING "%s: Error during CRB Initialization\n", 1216f4f5df23SVikas Chaudhary __func__); 1217f4f5df23SVikas Chaudhary return QLA_ERROR; 1218f4f5df23SVikas Chaudhary } 1219f4f5df23SVikas Chaudhary 1220f4f5df23SVikas Chaudhary udelay(500); 1221f4f5df23SVikas Chaudhary 1222f4f5df23SVikas Chaudhary /* at this point, QM is in reset. This could be a problem if there are 1223f4f5df23SVikas Chaudhary * incoming d* transition queue messages. QM/PCIE could wedge. 1224f4f5df23SVikas Chaudhary * To get around this, QM is brought out of reset. 1225f4f5df23SVikas Chaudhary */ 1226f4f5df23SVikas Chaudhary 1227f8086f4fSVikas Chaudhary rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 1228f4f5df23SVikas Chaudhary /* unreset qm */ 1229f4f5df23SVikas Chaudhary rst &= ~(1 << 28); 1230f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 1231f4f5df23SVikas Chaudhary 1232f8086f4fSVikas Chaudhary if (qla4_82xx_load_from_flash(ha, image_start)) { 1233f4f5df23SVikas Chaudhary printk("%s: Error trying to load fw from flash!\n", __func__); 1234f4f5df23SVikas Chaudhary return QLA_ERROR; 1235f4f5df23SVikas Chaudhary } 1236f4f5df23SVikas Chaudhary 1237f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1238f4f5df23SVikas Chaudhary } 1239f4f5df23SVikas Chaudhary 1240f4f5df23SVikas Chaudhary int 1241f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha, 1242f4f5df23SVikas Chaudhary u64 off, void *data, int size) 1243f4f5df23SVikas Chaudhary { 1244f4f5df23SVikas Chaudhary int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1245f4f5df23SVikas Chaudhary int shift_amount; 1246f4f5df23SVikas Chaudhary uint32_t temp; 1247f4f5df23SVikas Chaudhary uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1248f4f5df23SVikas Chaudhary 1249f4f5df23SVikas Chaudhary /* 1250f4f5df23SVikas Chaudhary * If not MN, go check for MS or invalid. 1251f4f5df23SVikas Chaudhary */ 1252f4f5df23SVikas Chaudhary 1253f4f5df23SVikas Chaudhary if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1254f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_QDR_NET; 1255f4f5df23SVikas Chaudhary else { 1256f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_DDR_NET; 1257f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) 1258f8086f4fSVikas Chaudhary return qla4_82xx_pci_mem_read_direct(ha, 1259f4f5df23SVikas Chaudhary off, data, size); 1260f4f5df23SVikas Chaudhary } 1261f4f5df23SVikas Chaudhary 1262f4f5df23SVikas Chaudhary 1263f4f5df23SVikas Chaudhary off8 = off & 0xfffffff0; 1264f4f5df23SVikas Chaudhary off0[0] = off & 0xf; 1265f4f5df23SVikas Chaudhary sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1266f4f5df23SVikas Chaudhary shift_amount = 4; 1267f4f5df23SVikas Chaudhary 1268f4f5df23SVikas Chaudhary loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1269f4f5df23SVikas Chaudhary off0[1] = 0; 1270f4f5df23SVikas Chaudhary sz[1] = size - sz[0]; 1271f4f5df23SVikas Chaudhary 1272f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1273f4f5df23SVikas Chaudhary temp = off8 + (i << shift_amount); 1274f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1275f4f5df23SVikas Chaudhary temp = 0; 1276f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1277f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_ENABLE; 1278f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1279f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1280f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1281f4f5df23SVikas Chaudhary 1282f4f5df23SVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1283f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1284f4f5df23SVikas Chaudhary if ((temp & MIU_TA_CTL_BUSY) == 0) 1285f4f5df23SVikas Chaudhary break; 1286f4f5df23SVikas Chaudhary } 1287f4f5df23SVikas Chaudhary 1288f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1289068237c8STej Parkash printk_ratelimited(KERN_ERR 1290068237c8STej Parkash "%s: failed to read through agent\n", 1291068237c8STej Parkash __func__); 1292f4f5df23SVikas Chaudhary break; 1293f4f5df23SVikas Chaudhary } 1294f4f5df23SVikas Chaudhary 1295f4f5df23SVikas Chaudhary start = off0[i] >> 2; 1296f4f5df23SVikas Chaudhary end = (off0[i] + sz[i] - 1) >> 2; 1297f4f5df23SVikas Chaudhary for (k = start; k <= end; k++) { 1298f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, 1299f4f5df23SVikas Chaudhary mem_crb + MIU_TEST_AGT_RDDATA(k)); 1300f4f5df23SVikas Chaudhary word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1301f4f5df23SVikas Chaudhary } 1302f4f5df23SVikas Chaudhary } 1303f4f5df23SVikas Chaudhary 1304f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) 1305f4f5df23SVikas Chaudhary return -1; 1306f4f5df23SVikas Chaudhary 1307f4f5df23SVikas Chaudhary if ((off0[0] & 7) == 0) { 1308f4f5df23SVikas Chaudhary val = word[0]; 1309f4f5df23SVikas Chaudhary } else { 1310f4f5df23SVikas Chaudhary val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1311f4f5df23SVikas Chaudhary ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1312f4f5df23SVikas Chaudhary } 1313f4f5df23SVikas Chaudhary 1314f4f5df23SVikas Chaudhary switch (size) { 1315f4f5df23SVikas Chaudhary case 1: 1316f4f5df23SVikas Chaudhary *(uint8_t *)data = val; 1317f4f5df23SVikas Chaudhary break; 1318f4f5df23SVikas Chaudhary case 2: 1319f4f5df23SVikas Chaudhary *(uint16_t *)data = val; 1320f4f5df23SVikas Chaudhary break; 1321f4f5df23SVikas Chaudhary case 4: 1322f4f5df23SVikas Chaudhary *(uint32_t *)data = val; 1323f4f5df23SVikas Chaudhary break; 1324f4f5df23SVikas Chaudhary case 8: 1325f4f5df23SVikas Chaudhary *(uint64_t *)data = val; 1326f4f5df23SVikas Chaudhary break; 1327f4f5df23SVikas Chaudhary } 1328f4f5df23SVikas Chaudhary return 0; 1329f4f5df23SVikas Chaudhary } 1330f4f5df23SVikas Chaudhary 1331f4f5df23SVikas Chaudhary int 1332f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, 1333f4f5df23SVikas Chaudhary u64 off, void *data, int size) 1334f4f5df23SVikas Chaudhary { 1335f4f5df23SVikas Chaudhary int i, j, ret = 0, loop, sz[2], off0; 1336f4f5df23SVikas Chaudhary int scale, shift_amount, startword; 1337f4f5df23SVikas Chaudhary uint32_t temp; 1338f4f5df23SVikas Chaudhary uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1339f4f5df23SVikas Chaudhary 1340f4f5df23SVikas Chaudhary /* 1341f4f5df23SVikas Chaudhary * If not MN, go check for MS or invalid. 1342f4f5df23SVikas Chaudhary */ 1343f4f5df23SVikas Chaudhary if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1344f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_QDR_NET; 1345f4f5df23SVikas Chaudhary else { 1346f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_DDR_NET; 1347f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) 1348f8086f4fSVikas Chaudhary return qla4_82xx_pci_mem_write_direct(ha, 1349f4f5df23SVikas Chaudhary off, data, size); 1350f4f5df23SVikas Chaudhary } 1351f4f5df23SVikas Chaudhary 1352f4f5df23SVikas Chaudhary off0 = off & 0x7; 1353f4f5df23SVikas Chaudhary sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1354f4f5df23SVikas Chaudhary sz[1] = size - sz[0]; 1355f4f5df23SVikas Chaudhary 1356f4f5df23SVikas Chaudhary off8 = off & 0xfffffff0; 1357f4f5df23SVikas Chaudhary loop = (((off & 0xf) + size - 1) >> 4) + 1; 1358f4f5df23SVikas Chaudhary shift_amount = 4; 1359f4f5df23SVikas Chaudhary scale = 2; 1360f4f5df23SVikas Chaudhary startword = (off & 0xf)/8; 1361f4f5df23SVikas Chaudhary 1362f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1363f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_read_2M(ha, off8 + 1364f4f5df23SVikas Chaudhary (i << shift_amount), &word[i * scale], 8)) 1365f4f5df23SVikas Chaudhary return -1; 1366f4f5df23SVikas Chaudhary } 1367f4f5df23SVikas Chaudhary 1368f4f5df23SVikas Chaudhary switch (size) { 1369f4f5df23SVikas Chaudhary case 1: 1370f4f5df23SVikas Chaudhary tmpw = *((uint8_t *)data); 1371f4f5df23SVikas Chaudhary break; 1372f4f5df23SVikas Chaudhary case 2: 1373f4f5df23SVikas Chaudhary tmpw = *((uint16_t *)data); 1374f4f5df23SVikas Chaudhary break; 1375f4f5df23SVikas Chaudhary case 4: 1376f4f5df23SVikas Chaudhary tmpw = *((uint32_t *)data); 1377f4f5df23SVikas Chaudhary break; 1378f4f5df23SVikas Chaudhary case 8: 1379f4f5df23SVikas Chaudhary default: 1380f4f5df23SVikas Chaudhary tmpw = *((uint64_t *)data); 1381f4f5df23SVikas Chaudhary break; 1382f4f5df23SVikas Chaudhary } 1383f4f5df23SVikas Chaudhary 1384f4f5df23SVikas Chaudhary if (sz[0] == 8) 1385f4f5df23SVikas Chaudhary word[startword] = tmpw; 1386f4f5df23SVikas Chaudhary else { 1387f4f5df23SVikas Chaudhary word[startword] &= 1388f4f5df23SVikas Chaudhary ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1389f4f5df23SVikas Chaudhary word[startword] |= tmpw << (off0 * 8); 1390f4f5df23SVikas Chaudhary } 1391f4f5df23SVikas Chaudhary 1392f4f5df23SVikas Chaudhary if (sz[1] != 0) { 1393f4f5df23SVikas Chaudhary word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1394f4f5df23SVikas Chaudhary word[startword+1] |= tmpw >> (sz[0] * 8); 1395f4f5df23SVikas Chaudhary } 1396f4f5df23SVikas Chaudhary 1397f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1398f4f5df23SVikas Chaudhary temp = off8 + (i << shift_amount); 1399f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1400f4f5df23SVikas Chaudhary temp = 0; 1401f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1402f4f5df23SVikas Chaudhary temp = word[i * scale] & 0xffffffff; 1403f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1404f4f5df23SVikas Chaudhary temp = (word[i * scale] >> 32) & 0xffffffff; 1405f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1406f4f5df23SVikas Chaudhary temp = word[i*scale + 1] & 0xffffffff; 1407f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, 1408f4f5df23SVikas Chaudhary temp); 1409f4f5df23SVikas Chaudhary temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1410f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, 1411f4f5df23SVikas Chaudhary temp); 1412f4f5df23SVikas Chaudhary 1413f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1414f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1415f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1416f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1417f4f5df23SVikas Chaudhary 1418f4f5df23SVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1419f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1420f4f5df23SVikas Chaudhary if ((temp & MIU_TA_CTL_BUSY) == 0) 1421f4f5df23SVikas Chaudhary break; 1422f4f5df23SVikas Chaudhary } 1423f4f5df23SVikas Chaudhary 1424f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1425f4f5df23SVikas Chaudhary if (printk_ratelimit()) 1426f4f5df23SVikas Chaudhary ql4_printk(KERN_ERR, ha, 1427068237c8STej Parkash "%s: failed to read through agent\n", 1428068237c8STej Parkash __func__); 1429f4f5df23SVikas Chaudhary ret = -1; 1430f4f5df23SVikas Chaudhary break; 1431f4f5df23SVikas Chaudhary } 1432f4f5df23SVikas Chaudhary } 1433f4f5df23SVikas Chaudhary 1434f4f5df23SVikas Chaudhary return ret; 1435f4f5df23SVikas Chaudhary } 1436f4f5df23SVikas Chaudhary 1437f8086f4fSVikas Chaudhary static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) 1438f4f5df23SVikas Chaudhary { 1439f4f5df23SVikas Chaudhary u32 val = 0; 1440f4f5df23SVikas Chaudhary int retries = 60; 1441f4f5df23SVikas Chaudhary 1442f4f5df23SVikas Chaudhary if (!pegtune_val) { 1443f4f5df23SVikas Chaudhary do { 1444f8086f4fSVikas Chaudhary val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE); 1445f4f5df23SVikas Chaudhary if ((val == PHAN_INITIALIZE_COMPLETE) || 1446f4f5df23SVikas Chaudhary (val == PHAN_INITIALIZE_ACK)) 1447f4f5df23SVikas Chaudhary return 0; 1448f4f5df23SVikas Chaudhary set_current_state(TASK_UNINTERRUPTIBLE); 1449f4f5df23SVikas Chaudhary schedule_timeout(500); 1450f4f5df23SVikas Chaudhary 1451f4f5df23SVikas Chaudhary } while (--retries); 1452f4f5df23SVikas Chaudhary 1453f4f5df23SVikas Chaudhary if (!retries) { 1454f8086f4fSVikas Chaudhary pegtune_val = qla4_82xx_rd_32(ha, 1455f4f5df23SVikas Chaudhary QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1456f4f5df23SVikas Chaudhary printk(KERN_WARNING "%s: init failed, " 1457f4f5df23SVikas Chaudhary "pegtune_val = %x\n", __func__, pegtune_val); 1458f4f5df23SVikas Chaudhary return -1; 1459f4f5df23SVikas Chaudhary } 1460f4f5df23SVikas Chaudhary } 1461f4f5df23SVikas Chaudhary return 0; 1462f4f5df23SVikas Chaudhary } 1463f4f5df23SVikas Chaudhary 1464f8086f4fSVikas Chaudhary static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha) 1465f4f5df23SVikas Chaudhary { 1466f4f5df23SVikas Chaudhary uint32_t state = 0; 1467f4f5df23SVikas Chaudhary int loops = 0; 1468f4f5df23SVikas Chaudhary 1469f4f5df23SVikas Chaudhary /* Window 1 call */ 1470f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1471f8086f4fSVikas Chaudhary state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); 1472f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1473f4f5df23SVikas Chaudhary 1474f4f5df23SVikas Chaudhary while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { 1475f4f5df23SVikas Chaudhary udelay(100); 1476f4f5df23SVikas Chaudhary /* Window 1 call */ 1477f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1478f8086f4fSVikas Chaudhary state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); 1479f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1480f4f5df23SVikas Chaudhary 1481f4f5df23SVikas Chaudhary loops++; 1482f4f5df23SVikas Chaudhary } 1483f4f5df23SVikas Chaudhary 1484f4f5df23SVikas Chaudhary if (loops >= 30000) { 1485f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 1486f4f5df23SVikas Chaudhary "Receive Peg initialization not complete: 0x%x.\n", state)); 1487f4f5df23SVikas Chaudhary return QLA_ERROR; 1488f4f5df23SVikas Chaudhary } 1489f4f5df23SVikas Chaudhary 1490f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1491f4f5df23SVikas Chaudhary } 1492f4f5df23SVikas Chaudhary 1493626115cdSAndrew Morton void 1494f4f5df23SVikas Chaudhary qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) 1495f4f5df23SVikas Chaudhary { 1496f4f5df23SVikas Chaudhary uint32_t drv_active; 1497f4f5df23SVikas Chaudhary 1498f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1499f4f5df23SVikas Chaudhary drv_active |= (1 << (ha->func_num * 4)); 1500068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1501068237c8STej Parkash __func__, ha->host_no, drv_active); 1502f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1503f4f5df23SVikas Chaudhary } 1504f4f5df23SVikas Chaudhary 1505f4f5df23SVikas Chaudhary void 1506f4f5df23SVikas Chaudhary qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) 1507f4f5df23SVikas Chaudhary { 1508f4f5df23SVikas Chaudhary uint32_t drv_active; 1509f4f5df23SVikas Chaudhary 1510f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1511f4f5df23SVikas Chaudhary drv_active &= ~(1 << (ha->func_num * 4)); 1512068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1513068237c8STej Parkash __func__, ha->host_no, drv_active); 1514f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1515f4f5df23SVikas Chaudhary } 1516f4f5df23SVikas Chaudhary 1517f4f5df23SVikas Chaudhary static inline int 1518f4f5df23SVikas Chaudhary qla4_8xxx_need_reset(struct scsi_qla_host *ha) 1519f4f5df23SVikas Chaudhary { 15202232be0dSLalit Chandivade uint32_t drv_state, drv_active; 1521f4f5df23SVikas Chaudhary int rval; 1522f4f5df23SVikas Chaudhary 1523f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1524f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1525f4f5df23SVikas Chaudhary rval = drv_state & (1 << (ha->func_num * 4)); 15262232be0dSLalit Chandivade if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 15272232be0dSLalit Chandivade rval = 1; 15282232be0dSLalit Chandivade 1529f4f5df23SVikas Chaudhary return rval; 1530f4f5df23SVikas Chaudhary } 1531f4f5df23SVikas Chaudhary 1532f4f5df23SVikas Chaudhary static inline void 1533f4f5df23SVikas Chaudhary qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) 1534f4f5df23SVikas Chaudhary { 1535f4f5df23SVikas Chaudhary uint32_t drv_state; 1536f4f5df23SVikas Chaudhary 1537f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1538f4f5df23SVikas Chaudhary drv_state |= (1 << (ha->func_num * 4)); 1539068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1540068237c8STej Parkash __func__, ha->host_no, drv_state); 1541f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1542f4f5df23SVikas Chaudhary } 1543f4f5df23SVikas Chaudhary 1544f4f5df23SVikas Chaudhary static inline void 1545f4f5df23SVikas Chaudhary qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) 1546f4f5df23SVikas Chaudhary { 1547f4f5df23SVikas Chaudhary uint32_t drv_state; 1548f4f5df23SVikas Chaudhary 1549f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1550f4f5df23SVikas Chaudhary drv_state &= ~(1 << (ha->func_num * 4)); 1551068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1552068237c8STej Parkash __func__, ha->host_no, drv_state); 1553f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1554f4f5df23SVikas Chaudhary } 1555f4f5df23SVikas Chaudhary 1556f4f5df23SVikas Chaudhary static inline void 1557f4f5df23SVikas Chaudhary qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) 1558f4f5df23SVikas Chaudhary { 1559f4f5df23SVikas Chaudhary uint32_t qsnt_state; 1560f4f5df23SVikas Chaudhary 1561f8086f4fSVikas Chaudhary qsnt_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1562f4f5df23SVikas Chaudhary qsnt_state |= (2 << (ha->func_num * 4)); 1563f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 1564f4f5df23SVikas Chaudhary } 1565f4f5df23SVikas Chaudhary 1566f4f5df23SVikas Chaudhary 1567f4f5df23SVikas Chaudhary static int 1568f8086f4fSVikas Chaudhary qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) 1569f4f5df23SVikas Chaudhary { 1570f4f5df23SVikas Chaudhary int pcie_cap; 1571f4f5df23SVikas Chaudhary uint16_t lnk; 1572f4f5df23SVikas Chaudhary 1573f4f5df23SVikas Chaudhary /* scrub dma mask expansion register */ 1574f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 1575f4f5df23SVikas Chaudhary 1576f4f5df23SVikas Chaudhary /* Overwrite stale initialization register values */ 1577f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1578f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 1579f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 1580f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 1581f4f5df23SVikas Chaudhary 1582f8086f4fSVikas Chaudhary if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) { 1583f4f5df23SVikas Chaudhary printk("%s: Error trying to start fw!\n", __func__); 1584f4f5df23SVikas Chaudhary return QLA_ERROR; 1585f4f5df23SVikas Chaudhary } 1586f4f5df23SVikas Chaudhary 1587f4f5df23SVikas Chaudhary /* Handshake with the card before we register the devices. */ 1588f8086f4fSVikas Chaudhary if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { 1589f4f5df23SVikas Chaudhary printk("%s: Error during card handshake!\n", __func__); 1590f4f5df23SVikas Chaudhary return QLA_ERROR; 1591f4f5df23SVikas Chaudhary } 1592f4f5df23SVikas Chaudhary 1593f4f5df23SVikas Chaudhary /* Negotiated Link width */ 1594983bfb5bSJon Mason pcie_cap = pci_pcie_cap(ha->pdev); 1595f4f5df23SVikas Chaudhary pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 1596f4f5df23SVikas Chaudhary ha->link_width = (lnk >> 4) & 0x3f; 1597f4f5df23SVikas Chaudhary 1598f4f5df23SVikas Chaudhary /* Synchronize with Receive peg */ 1599f8086f4fSVikas Chaudhary return qla4_82xx_rcvpeg_ready(ha); 1600f4f5df23SVikas Chaudhary } 1601f4f5df23SVikas Chaudhary 1602f4f5df23SVikas Chaudhary static int 1603f8086f4fSVikas Chaudhary qla4_82xx_try_start_fw(struct scsi_qla_host *ha) 1604f4f5df23SVikas Chaudhary { 1605f4f5df23SVikas Chaudhary int rval = QLA_ERROR; 1606f4f5df23SVikas Chaudhary 1607f4f5df23SVikas Chaudhary /* 1608f4f5df23SVikas Chaudhary * FW Load priority: 1609f4f5df23SVikas Chaudhary * 1) Operational firmware residing in flash. 1610f4f5df23SVikas Chaudhary * 2) Fail 1611f4f5df23SVikas Chaudhary */ 1612f4f5df23SVikas Chaudhary 1613f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1614f4f5df23SVikas Chaudhary "FW: Retrieving flash offsets from FLT/FDT ...\n"); 1615f4f5df23SVikas Chaudhary rval = qla4_8xxx_get_flash_info(ha); 1616f4f5df23SVikas Chaudhary if (rval != QLA_SUCCESS) 1617f4f5df23SVikas Chaudhary return rval; 1618f4f5df23SVikas Chaudhary 1619f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1620f4f5df23SVikas Chaudhary "FW: Attempting to load firmware from flash...\n"); 1621f8086f4fSVikas Chaudhary rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw); 1622f4f5df23SVikas Chaudhary 1623f581a3f7SVikas Chaudhary if (rval != QLA_SUCCESS) { 1624f581a3f7SVikas Chaudhary ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" 1625f581a3f7SVikas Chaudhary " FAILED...\n"); 1626f581a3f7SVikas Chaudhary return rval; 1627f581a3f7SVikas Chaudhary } 1628f4f5df23SVikas Chaudhary 1629f4f5df23SVikas Chaudhary return rval; 1630f4f5df23SVikas Chaudhary } 1631f4f5df23SVikas Chaudhary 1632f8086f4fSVikas Chaudhary static void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha) 1633b25ee66fSShyam Sundar { 1634f8086f4fSVikas Chaudhary if (qla4_82xx_rom_lock(ha)) { 1635b25ee66fSShyam Sundar /* Someone else is holding the lock. */ 1636b25ee66fSShyam Sundar dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); 1637b25ee66fSShyam Sundar } 1638b25ee66fSShyam Sundar 1639b25ee66fSShyam Sundar /* 1640b25ee66fSShyam Sundar * Either we got the lock, or someone 1641b25ee66fSShyam Sundar * else died while holding it. 1642b25ee66fSShyam Sundar * In either case, unlock. 1643b25ee66fSShyam Sundar */ 1644f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 1645b25ee66fSShyam Sundar } 1646b25ee66fSShyam Sundar 1647068237c8STej Parkash static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha, 16487664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1649068237c8STej Parkash uint32_t **d_ptr) 1650068237c8STej Parkash { 1651068237c8STej Parkash uint32_t r_addr, r_stride, loop_cnt, i, r_value; 16527664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_crb *crb_hdr; 1653068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1654068237c8STej Parkash 1655068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 16567664a1fdSVikas Chaudhary crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr; 1657068237c8STej Parkash r_addr = crb_hdr->addr; 1658068237c8STej Parkash r_stride = crb_hdr->crb_strd.addr_stride; 1659068237c8STej Parkash loop_cnt = crb_hdr->op_count; 1660068237c8STej Parkash 1661068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 1662068237c8STej Parkash r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1663068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_addr); 1664068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1665068237c8STej Parkash r_addr += r_stride; 1666068237c8STej Parkash } 1667068237c8STej Parkash *d_ptr = data_ptr; 1668068237c8STej Parkash } 1669068237c8STej Parkash 1670068237c8STej Parkash static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha, 16717664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1672068237c8STej Parkash uint32_t **d_ptr) 1673068237c8STej Parkash { 1674068237c8STej Parkash uint32_t addr, r_addr, c_addr, t_r_addr; 1675068237c8STej Parkash uint32_t i, k, loop_count, t_value, r_cnt, r_value; 1676068237c8STej Parkash unsigned long p_wait, w_time, p_mask; 1677068237c8STej Parkash uint32_t c_value_w, c_value_r; 16787664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_cache *cache_hdr; 1679068237c8STej Parkash int rval = QLA_ERROR; 1680068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1681068237c8STej Parkash 1682068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 16837664a1fdSVikas Chaudhary cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; 1684068237c8STej Parkash 1685068237c8STej Parkash loop_count = cache_hdr->op_count; 1686068237c8STej Parkash r_addr = cache_hdr->read_addr; 1687068237c8STej Parkash c_addr = cache_hdr->control_addr; 1688068237c8STej Parkash c_value_w = cache_hdr->cache_ctrl.write_value; 1689068237c8STej Parkash 1690068237c8STej Parkash t_r_addr = cache_hdr->tag_reg_addr; 1691068237c8STej Parkash t_value = cache_hdr->addr_ctrl.init_tag_value; 1692068237c8STej Parkash r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 1693068237c8STej Parkash p_wait = cache_hdr->cache_ctrl.poll_wait; 1694068237c8STej Parkash p_mask = cache_hdr->cache_ctrl.poll_mask; 1695068237c8STej Parkash 1696068237c8STej Parkash for (i = 0; i < loop_count; i++) { 1697068237c8STej Parkash qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1); 1698068237c8STej Parkash 1699068237c8STej Parkash if (c_value_w) 1700068237c8STej Parkash qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1); 1701068237c8STej Parkash 1702068237c8STej Parkash if (p_mask) { 1703068237c8STej Parkash w_time = jiffies + p_wait; 1704068237c8STej Parkash do { 1705068237c8STej Parkash c_value_r = qla4_8xxx_md_rw_32(ha, c_addr, 1706068237c8STej Parkash 0, 0); 1707068237c8STej Parkash if ((c_value_r & p_mask) == 0) { 1708068237c8STej Parkash break; 1709068237c8STej Parkash } else if (time_after_eq(jiffies, w_time)) { 1710068237c8STej Parkash /* capturing dump failed */ 1711068237c8STej Parkash return rval; 1712068237c8STej Parkash } 1713068237c8STej Parkash } while (1); 1714068237c8STej Parkash } 1715068237c8STej Parkash 1716068237c8STej Parkash addr = r_addr; 1717068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 1718068237c8STej Parkash r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1719068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1720068237c8STej Parkash addr += cache_hdr->read_ctrl.read_addr_stride; 1721068237c8STej Parkash } 1722068237c8STej Parkash 1723068237c8STej Parkash t_value += cache_hdr->addr_ctrl.tag_value_stride; 1724068237c8STej Parkash } 1725068237c8STej Parkash *d_ptr = data_ptr; 1726068237c8STej Parkash return QLA_SUCCESS; 1727068237c8STej Parkash } 1728068237c8STej Parkash 1729068237c8STej Parkash static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, 17307664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr) 1731068237c8STej Parkash { 17327664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_crb *crb_entry; 1733068237c8STej Parkash uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS; 1734068237c8STej Parkash uint32_t crb_addr; 1735068237c8STej Parkash unsigned long wtime; 1736068237c8STej Parkash struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 1737068237c8STej Parkash int i; 1738068237c8STej Parkash 1739068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 1740068237c8STej Parkash tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 1741068237c8STej Parkash ha->fw_dump_tmplt_hdr; 17427664a1fdSVikas Chaudhary crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr; 1743068237c8STej Parkash 1744068237c8STej Parkash crb_addr = crb_entry->addr; 1745068237c8STej Parkash for (i = 0; i < crb_entry->op_count; i++) { 1746068237c8STej Parkash opcode = crb_entry->crb_ctrl.opcode; 1747068237c8STej Parkash if (opcode & QLA82XX_DBG_OPCODE_WR) { 1748068237c8STej Parkash qla4_8xxx_md_rw_32(ha, crb_addr, 1749068237c8STej Parkash crb_entry->value_1, 1); 1750068237c8STej Parkash opcode &= ~QLA82XX_DBG_OPCODE_WR; 1751068237c8STej Parkash } 1752068237c8STej Parkash if (opcode & QLA82XX_DBG_OPCODE_RW) { 1753068237c8STej Parkash read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1754068237c8STej Parkash qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1755068237c8STej Parkash opcode &= ~QLA82XX_DBG_OPCODE_RW; 1756068237c8STej Parkash } 1757068237c8STej Parkash if (opcode & QLA82XX_DBG_OPCODE_AND) { 1758068237c8STej Parkash read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1759068237c8STej Parkash read_value &= crb_entry->value_2; 1760068237c8STej Parkash opcode &= ~QLA82XX_DBG_OPCODE_AND; 1761068237c8STej Parkash if (opcode & QLA82XX_DBG_OPCODE_OR) { 1762068237c8STej Parkash read_value |= crb_entry->value_3; 1763068237c8STej Parkash opcode &= ~QLA82XX_DBG_OPCODE_OR; 1764068237c8STej Parkash } 1765068237c8STej Parkash qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1766068237c8STej Parkash } 1767068237c8STej Parkash if (opcode & QLA82XX_DBG_OPCODE_OR) { 1768068237c8STej Parkash read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1769068237c8STej Parkash read_value |= crb_entry->value_3; 1770068237c8STej Parkash qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1); 1771068237c8STej Parkash opcode &= ~QLA82XX_DBG_OPCODE_OR; 1772068237c8STej Parkash } 1773068237c8STej Parkash if (opcode & QLA82XX_DBG_OPCODE_POLL) { 1774068237c8STej Parkash poll_time = crb_entry->crb_strd.poll_timeout; 1775068237c8STej Parkash wtime = jiffies + poll_time; 1776068237c8STej Parkash read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0); 1777068237c8STej Parkash 1778068237c8STej Parkash do { 1779068237c8STej Parkash if ((read_value & crb_entry->value_2) == 1780068237c8STej Parkash crb_entry->value_1) 1781068237c8STej Parkash break; 1782068237c8STej Parkash else if (time_after_eq(jiffies, wtime)) { 1783068237c8STej Parkash /* capturing dump failed */ 1784068237c8STej Parkash rval = QLA_ERROR; 1785068237c8STej Parkash break; 1786068237c8STej Parkash } else 1787068237c8STej Parkash read_value = qla4_8xxx_md_rw_32(ha, 1788068237c8STej Parkash crb_addr, 0, 0); 1789068237c8STej Parkash } while (1); 1790068237c8STej Parkash opcode &= ~QLA82XX_DBG_OPCODE_POLL; 1791068237c8STej Parkash } 1792068237c8STej Parkash 1793068237c8STej Parkash if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 1794068237c8STej Parkash if (crb_entry->crb_strd.state_index_a) { 1795068237c8STej Parkash index = crb_entry->crb_strd.state_index_a; 1796068237c8STej Parkash addr = tmplt_hdr->saved_state_array[index]; 1797068237c8STej Parkash } else { 1798068237c8STej Parkash addr = crb_addr; 1799068237c8STej Parkash } 1800068237c8STej Parkash 1801068237c8STej Parkash read_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1802068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 1803068237c8STej Parkash tmplt_hdr->saved_state_array[index] = read_value; 1804068237c8STej Parkash opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 1805068237c8STej Parkash } 1806068237c8STej Parkash 1807068237c8STej Parkash if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 1808068237c8STej Parkash if (crb_entry->crb_strd.state_index_a) { 1809068237c8STej Parkash index = crb_entry->crb_strd.state_index_a; 1810068237c8STej Parkash addr = tmplt_hdr->saved_state_array[index]; 1811068237c8STej Parkash } else { 1812068237c8STej Parkash addr = crb_addr; 1813068237c8STej Parkash } 1814068237c8STej Parkash 1815068237c8STej Parkash if (crb_entry->crb_ctrl.state_index_v) { 1816068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 1817068237c8STej Parkash read_value = 1818068237c8STej Parkash tmplt_hdr->saved_state_array[index]; 1819068237c8STej Parkash } else { 1820068237c8STej Parkash read_value = crb_entry->value_1; 1821068237c8STej Parkash } 1822068237c8STej Parkash 1823068237c8STej Parkash qla4_8xxx_md_rw_32(ha, addr, read_value, 1); 1824068237c8STej Parkash opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 1825068237c8STej Parkash } 1826068237c8STej Parkash 1827068237c8STej Parkash if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 1828068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 1829068237c8STej Parkash read_value = tmplt_hdr->saved_state_array[index]; 1830068237c8STej Parkash read_value <<= crb_entry->crb_ctrl.shl; 1831068237c8STej Parkash read_value >>= crb_entry->crb_ctrl.shr; 1832068237c8STej Parkash if (crb_entry->value_2) 1833068237c8STej Parkash read_value &= crb_entry->value_2; 1834068237c8STej Parkash read_value |= crb_entry->value_3; 1835068237c8STej Parkash read_value += crb_entry->value_1; 1836068237c8STej Parkash tmplt_hdr->saved_state_array[index] = read_value; 1837068237c8STej Parkash opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 1838068237c8STej Parkash } 1839068237c8STej Parkash crb_addr += crb_entry->crb_strd.addr_stride; 1840068237c8STej Parkash } 1841068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); 1842068237c8STej Parkash return rval; 1843068237c8STej Parkash } 1844068237c8STej Parkash 1845068237c8STej Parkash static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha, 18467664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1847068237c8STej Parkash uint32_t **d_ptr) 1848068237c8STej Parkash { 1849068237c8STej Parkash uint32_t r_addr, r_stride, loop_cnt, i, r_value; 18507664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdocm *ocm_hdr; 1851068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1852068237c8STej Parkash 1853068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 18547664a1fdSVikas Chaudhary ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr; 1855068237c8STej Parkash r_addr = ocm_hdr->read_addr; 1856068237c8STej Parkash r_stride = ocm_hdr->read_addr_stride; 1857068237c8STej Parkash loop_cnt = ocm_hdr->op_count; 1858068237c8STej Parkash 1859068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 1860068237c8STej Parkash "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", 1861068237c8STej Parkash __func__, r_addr, r_stride, loop_cnt)); 1862068237c8STej Parkash 1863068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 1864068237c8STej Parkash r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); 1865068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1866068237c8STej Parkash r_addr += r_stride; 1867068237c8STej Parkash } 1868068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n", 186926fdf922SVikas Chaudhary __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)))); 1870068237c8STej Parkash *d_ptr = data_ptr; 1871068237c8STej Parkash } 1872068237c8STej Parkash 1873068237c8STej Parkash static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha, 18747664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1875068237c8STej Parkash uint32_t **d_ptr) 1876068237c8STej Parkash { 1877068237c8STej Parkash uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 18787664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_mux *mux_hdr; 1879068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1880068237c8STej Parkash 1881068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 18827664a1fdSVikas Chaudhary mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr; 1883068237c8STej Parkash r_addr = mux_hdr->read_addr; 1884068237c8STej Parkash s_addr = mux_hdr->select_addr; 1885068237c8STej Parkash s_stride = mux_hdr->select_value_stride; 1886068237c8STej Parkash s_value = mux_hdr->select_value; 1887068237c8STej Parkash loop_cnt = mux_hdr->op_count; 1888068237c8STej Parkash 1889068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 1890068237c8STej Parkash qla4_8xxx_md_rw_32(ha, s_addr, s_value, 1); 1891068237c8STej Parkash r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1892068237c8STej Parkash *data_ptr++ = cpu_to_le32(s_value); 1893068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1894068237c8STej Parkash s_value += s_stride; 1895068237c8STej Parkash } 1896068237c8STej Parkash *d_ptr = data_ptr; 1897068237c8STej Parkash } 1898068237c8STej Parkash 1899068237c8STej Parkash static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha, 19007664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1901068237c8STej Parkash uint32_t **d_ptr) 1902068237c8STej Parkash { 1903068237c8STej Parkash uint32_t addr, r_addr, c_addr, t_r_addr; 1904068237c8STej Parkash uint32_t i, k, loop_count, t_value, r_cnt, r_value; 1905068237c8STej Parkash uint32_t c_value_w; 19067664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_cache *cache_hdr; 1907068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1908068237c8STej Parkash 19097664a1fdSVikas Chaudhary cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; 1910068237c8STej Parkash loop_count = cache_hdr->op_count; 1911068237c8STej Parkash r_addr = cache_hdr->read_addr; 1912068237c8STej Parkash c_addr = cache_hdr->control_addr; 1913068237c8STej Parkash c_value_w = cache_hdr->cache_ctrl.write_value; 1914068237c8STej Parkash 1915068237c8STej Parkash t_r_addr = cache_hdr->tag_reg_addr; 1916068237c8STej Parkash t_value = cache_hdr->addr_ctrl.init_tag_value; 1917068237c8STej Parkash r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 1918068237c8STej Parkash 1919068237c8STej Parkash for (i = 0; i < loop_count; i++) { 1920068237c8STej Parkash qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1); 1921068237c8STej Parkash qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1); 1922068237c8STej Parkash addr = r_addr; 1923068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 1924068237c8STej Parkash r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0); 1925068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1926068237c8STej Parkash addr += cache_hdr->read_ctrl.read_addr_stride; 1927068237c8STej Parkash } 1928068237c8STej Parkash t_value += cache_hdr->addr_ctrl.tag_value_stride; 1929068237c8STej Parkash } 1930068237c8STej Parkash *d_ptr = data_ptr; 1931068237c8STej Parkash } 1932068237c8STej Parkash 1933068237c8STej Parkash static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha, 19347664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1935068237c8STej Parkash uint32_t **d_ptr) 1936068237c8STej Parkash { 1937068237c8STej Parkash uint32_t s_addr, r_addr; 1938068237c8STej Parkash uint32_t r_stride, r_value, r_cnt, qid = 0; 1939068237c8STej Parkash uint32_t i, k, loop_cnt; 19407664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_queue *q_hdr; 1941068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1942068237c8STej Parkash 1943068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 19447664a1fdSVikas Chaudhary q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr; 1945068237c8STej Parkash s_addr = q_hdr->select_addr; 1946068237c8STej Parkash r_cnt = q_hdr->rd_strd.read_addr_cnt; 1947068237c8STej Parkash r_stride = q_hdr->rd_strd.read_addr_stride; 1948068237c8STej Parkash loop_cnt = q_hdr->op_count; 1949068237c8STej Parkash 1950068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 1951068237c8STej Parkash qla4_8xxx_md_rw_32(ha, s_addr, qid, 1); 1952068237c8STej Parkash r_addr = q_hdr->read_addr; 1953068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 1954068237c8STej Parkash r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0); 1955068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1956068237c8STej Parkash r_addr += r_stride; 1957068237c8STej Parkash } 1958068237c8STej Parkash qid += q_hdr->q_strd.queue_id_stride; 1959068237c8STej Parkash } 1960068237c8STej Parkash *d_ptr = data_ptr; 1961068237c8STej Parkash } 1962068237c8STej Parkash 1963068237c8STej Parkash #define MD_DIRECT_ROM_WINDOW 0x42110030 1964068237c8STej Parkash #define MD_DIRECT_ROM_READ_BASE 0x42150000 1965068237c8STej Parkash 1966f8086f4fSVikas Chaudhary static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha, 19677664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1968068237c8STej Parkash uint32_t **d_ptr) 1969068237c8STej Parkash { 1970068237c8STej Parkash uint32_t r_addr, r_value; 1971068237c8STej Parkash uint32_t i, loop_cnt; 19727664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdrom *rom_hdr; 1973068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1974068237c8STej Parkash 1975068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 19767664a1fdSVikas Chaudhary rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; 1977068237c8STej Parkash r_addr = rom_hdr->read_addr; 1978068237c8STej Parkash loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 1979068237c8STej Parkash 1980068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 1981068237c8STej Parkash "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n", 1982068237c8STej Parkash __func__, r_addr, loop_cnt)); 1983068237c8STej Parkash 1984068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 1985068237c8STej Parkash qla4_8xxx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, 1986068237c8STej Parkash (r_addr & 0xFFFF0000), 1); 1987068237c8STej Parkash r_value = qla4_8xxx_md_rw_32(ha, 1988068237c8STej Parkash MD_DIRECT_ROM_READ_BASE + 1989068237c8STej Parkash (r_addr & 0x0000FFFF), 0, 0); 1990068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1991068237c8STej Parkash r_addr += sizeof(uint32_t); 1992068237c8STej Parkash } 1993068237c8STej Parkash *d_ptr = data_ptr; 1994068237c8STej Parkash } 1995068237c8STej Parkash 1996068237c8STej Parkash #define MD_MIU_TEST_AGT_CTRL 0x41000090 1997068237c8STej Parkash #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 1998068237c8STej Parkash #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 1999068237c8STej Parkash 2000068237c8STej Parkash static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 20017664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2002068237c8STej Parkash uint32_t **d_ptr) 2003068237c8STej Parkash { 2004068237c8STej Parkash uint32_t r_addr, r_value, r_data; 2005068237c8STej Parkash uint32_t i, j, loop_cnt; 20067664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdmem *m_hdr; 2007068237c8STej Parkash unsigned long flags; 2008068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2009068237c8STej Parkash 2010068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 20117664a1fdSVikas Chaudhary m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr; 2012068237c8STej Parkash r_addr = m_hdr->read_addr; 2013068237c8STej Parkash loop_cnt = m_hdr->read_data_size/16; 2014068237c8STej Parkash 2015068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2016068237c8STej Parkash "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", 2017068237c8STej Parkash __func__, r_addr, m_hdr->read_data_size)); 2018068237c8STej Parkash 2019068237c8STej Parkash if (r_addr & 0xf) { 2020068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2021068237c8STej Parkash "[%s]: Read addr 0x%x not 16 bytes alligned\n", 2022068237c8STej Parkash __func__, r_addr)); 2023068237c8STej Parkash return QLA_ERROR; 2024068237c8STej Parkash } 2025068237c8STej Parkash 2026068237c8STej Parkash if (m_hdr->read_data_size % 16) { 2027068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2028068237c8STej Parkash "[%s]: Read data[0x%x] not multiple of 16 bytes\n", 2029068237c8STej Parkash __func__, m_hdr->read_data_size)); 2030068237c8STej Parkash return QLA_ERROR; 2031068237c8STej Parkash } 2032068237c8STej Parkash 2033068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2034068237c8STej Parkash "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 2035068237c8STej Parkash __func__, r_addr, m_hdr->read_data_size, loop_cnt)); 2036068237c8STej Parkash 2037068237c8STej Parkash write_lock_irqsave(&ha->hw_lock, flags); 2038068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 2039068237c8STej Parkash qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1); 2040068237c8STej Parkash r_value = 0; 2041068237c8STej Parkash qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1); 2042068237c8STej Parkash r_value = MIU_TA_CTL_ENABLE; 2043068237c8STej Parkash qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 2044068237c8STej Parkash r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 2045068237c8STej Parkash qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1); 2046068237c8STej Parkash 2047068237c8STej Parkash for (j = 0; j < MAX_CTL_CHECK; j++) { 2048068237c8STej Parkash r_value = qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, 2049068237c8STej Parkash 0, 0); 2050068237c8STej Parkash if ((r_value & MIU_TA_CTL_BUSY) == 0) 2051068237c8STej Parkash break; 2052068237c8STej Parkash } 2053068237c8STej Parkash 2054068237c8STej Parkash if (j >= MAX_CTL_CHECK) { 2055068237c8STej Parkash printk_ratelimited(KERN_ERR 2056068237c8STej Parkash "%s: failed to read through agent\n", 2057068237c8STej Parkash __func__); 2058068237c8STej Parkash write_unlock_irqrestore(&ha->hw_lock, flags); 2059068237c8STej Parkash return QLA_SUCCESS; 2060068237c8STej Parkash } 2061068237c8STej Parkash 2062068237c8STej Parkash for (j = 0; j < 4; j++) { 2063068237c8STej Parkash r_data = qla4_8xxx_md_rw_32(ha, 2064068237c8STej Parkash MD_MIU_TEST_AGT_RDDATA[j], 2065068237c8STej Parkash 0, 0); 2066068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_data); 2067068237c8STej Parkash } 2068068237c8STej Parkash 2069068237c8STej Parkash r_addr += 16; 2070068237c8STej Parkash } 2071068237c8STej Parkash write_unlock_irqrestore(&ha->hw_lock, flags); 2072068237c8STej Parkash 2073068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n", 2074068237c8STej Parkash __func__, (loop_cnt * 16))); 2075068237c8STej Parkash 2076068237c8STej Parkash *d_ptr = data_ptr; 2077068237c8STej Parkash return QLA_SUCCESS; 2078068237c8STej Parkash } 2079068237c8STej Parkash 20805e9bcec7SVikas Chaudhary static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha, 20817664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2082068237c8STej Parkash int index) 2083068237c8STej Parkash { 2084068237c8STej Parkash entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 2085068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2086068237c8STej Parkash "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", 2087068237c8STej Parkash ha->host_no, index, entry_hdr->entry_type, 2088068237c8STej Parkash entry_hdr->d_ctrl.entry_capture_mask)); 2089068237c8STej Parkash } 2090068237c8STej Parkash 2091068237c8STej Parkash /** 2092f8086f4fSVikas Chaudhary * qla4_8xxx_collect_md_data - Retrieve firmware minidump data. 2093068237c8STej Parkash * @ha: pointer to adapter structure 2094068237c8STej Parkash **/ 2095068237c8STej Parkash static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) 2096068237c8STej Parkash { 2097068237c8STej Parkash int num_entry_hdr = 0; 20987664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr; 2099068237c8STej Parkash struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 2100068237c8STej Parkash uint32_t *data_ptr; 2101068237c8STej Parkash uint32_t data_collected = 0; 2102068237c8STej Parkash int i, rval = QLA_ERROR; 2103068237c8STej Parkash uint64_t now; 2104068237c8STej Parkash uint32_t timestamp; 2105068237c8STej Parkash 2106068237c8STej Parkash if (!ha->fw_dump) { 2107068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n", 2108068237c8STej Parkash __func__, ha->host_no); 2109068237c8STej Parkash return rval; 2110068237c8STej Parkash } 2111068237c8STej Parkash 2112068237c8STej Parkash tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 2113068237c8STej Parkash ha->fw_dump_tmplt_hdr; 2114068237c8STej Parkash data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump + 2115068237c8STej Parkash ha->fw_dump_tmplt_size); 2116068237c8STej Parkash data_collected += ha->fw_dump_tmplt_size; 2117068237c8STej Parkash 2118068237c8STej Parkash num_entry_hdr = tmplt_hdr->num_of_entries; 2119068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n", 2120068237c8STej Parkash __func__, data_ptr); 2121068237c8STej Parkash ql4_printk(KERN_INFO, ha, 2122068237c8STej Parkash "[%s]: no of entry headers in Template: 0x%x\n", 2123068237c8STej Parkash __func__, num_entry_hdr); 2124068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n", 2125068237c8STej Parkash __func__, ha->fw_dump_capture_mask); 2126068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n", 2127068237c8STej Parkash __func__, ha->fw_dump_size, ha->fw_dump_size); 2128068237c8STej Parkash 2129068237c8STej Parkash /* Update current timestamp before taking dump */ 2130068237c8STej Parkash now = get_jiffies_64(); 2131068237c8STej Parkash timestamp = (u32)(jiffies_to_msecs(now) / 1000); 2132068237c8STej Parkash tmplt_hdr->driver_timestamp = timestamp; 2133068237c8STej Parkash 21347664a1fdSVikas Chaudhary entry_hdr = (struct qla8xxx_minidump_entry_hdr *) 2135068237c8STej Parkash (((uint8_t *)ha->fw_dump_tmplt_hdr) + 2136068237c8STej Parkash tmplt_hdr->first_entry_offset); 2137068237c8STej Parkash 2138068237c8STej Parkash /* Walk through the entry headers - validate/perform required action */ 2139068237c8STej Parkash for (i = 0; i < num_entry_hdr; i++) { 2140068237c8STej Parkash if (data_collected >= ha->fw_dump_size) { 2141068237c8STej Parkash ql4_printk(KERN_INFO, ha, 2142068237c8STej Parkash "Data collected: [0x%x], Total Dump size: [0x%x]\n", 2143068237c8STej Parkash data_collected, ha->fw_dump_size); 2144068237c8STej Parkash return rval; 2145068237c8STej Parkash } 2146068237c8STej Parkash 2147068237c8STej Parkash if (!(entry_hdr->d_ctrl.entry_capture_mask & 2148068237c8STej Parkash ha->fw_dump_capture_mask)) { 2149068237c8STej Parkash entry_hdr->d_ctrl.driver_flags |= 2150068237c8STej Parkash QLA82XX_DBG_SKIPPED_FLAG; 2151068237c8STej Parkash goto skip_nxt_entry; 2152068237c8STej Parkash } 2153068237c8STej Parkash 2154068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2155068237c8STej Parkash "Data collected: [0x%x], Dump size left:[0x%x]\n", 2156068237c8STej Parkash data_collected, 2157068237c8STej Parkash (ha->fw_dump_size - data_collected))); 2158068237c8STej Parkash 2159068237c8STej Parkash /* Decode the entry type and take required action to capture 2160068237c8STej Parkash * debug data 2161068237c8STej Parkash */ 2162068237c8STej Parkash switch (entry_hdr->entry_type) { 2163068237c8STej Parkash case QLA82XX_RDEND: 21645e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2165068237c8STej Parkash break; 2166068237c8STej Parkash case QLA82XX_CNTRL: 2167068237c8STej Parkash rval = qla4_8xxx_minidump_process_control(ha, 2168068237c8STej Parkash entry_hdr); 2169068237c8STej Parkash if (rval != QLA_SUCCESS) { 21705e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2171068237c8STej Parkash goto md_failed; 2172068237c8STej Parkash } 2173068237c8STej Parkash break; 2174068237c8STej Parkash case QLA82XX_RDCRB: 2175068237c8STej Parkash qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, 2176068237c8STej Parkash &data_ptr); 2177068237c8STej Parkash break; 2178068237c8STej Parkash case QLA82XX_RDMEM: 2179068237c8STej Parkash rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 2180068237c8STej Parkash &data_ptr); 2181068237c8STej Parkash if (rval != QLA_SUCCESS) { 21825e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2183068237c8STej Parkash goto md_failed; 2184068237c8STej Parkash } 2185068237c8STej Parkash break; 2186068237c8STej Parkash case QLA82XX_BOARD: 2187068237c8STej Parkash case QLA82XX_RDROM: 2188f8086f4fSVikas Chaudhary qla4_82xx_minidump_process_rdrom(ha, entry_hdr, 2189068237c8STej Parkash &data_ptr); 2190068237c8STej Parkash break; 2191068237c8STej Parkash case QLA82XX_L2DTG: 2192068237c8STej Parkash case QLA82XX_L2ITG: 2193068237c8STej Parkash case QLA82XX_L2DAT: 2194068237c8STej Parkash case QLA82XX_L2INS: 2195068237c8STej Parkash rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, 2196068237c8STej Parkash &data_ptr); 2197068237c8STej Parkash if (rval != QLA_SUCCESS) { 21985e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2199068237c8STej Parkash goto md_failed; 2200068237c8STej Parkash } 2201068237c8STej Parkash break; 2202068237c8STej Parkash case QLA82XX_L1DAT: 2203068237c8STej Parkash case QLA82XX_L1INS: 2204068237c8STej Parkash qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, 2205068237c8STej Parkash &data_ptr); 2206068237c8STej Parkash break; 2207068237c8STej Parkash case QLA82XX_RDOCM: 2208068237c8STej Parkash qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, 2209068237c8STej Parkash &data_ptr); 2210068237c8STej Parkash break; 2211068237c8STej Parkash case QLA82XX_RDMUX: 2212068237c8STej Parkash qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, 2213068237c8STej Parkash &data_ptr); 2214068237c8STej Parkash break; 2215068237c8STej Parkash case QLA82XX_QUEUE: 2216068237c8STej Parkash qla4_8xxx_minidump_process_queue(ha, entry_hdr, 2217068237c8STej Parkash &data_ptr); 2218068237c8STej Parkash break; 2219068237c8STej Parkash case QLA82XX_RDNOP: 2220068237c8STej Parkash default: 22215e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2222068237c8STej Parkash break; 2223068237c8STej Parkash } 2224068237c8STej Parkash 2225068237c8STej Parkash data_collected = (uint8_t *)data_ptr - 2226068237c8STej Parkash ((uint8_t *)((uint8_t *)ha->fw_dump + 2227068237c8STej Parkash ha->fw_dump_tmplt_size)); 2228068237c8STej Parkash skip_nxt_entry: 2229068237c8STej Parkash /* next entry in the template */ 22307664a1fdSVikas Chaudhary entry_hdr = (struct qla8xxx_minidump_entry_hdr *) 2231068237c8STej Parkash (((uint8_t *)entry_hdr) + 2232068237c8STej Parkash entry_hdr->entry_size); 2233068237c8STej Parkash } 2234068237c8STej Parkash 2235068237c8STej Parkash if ((data_collected + ha->fw_dump_tmplt_size) != ha->fw_dump_size) { 2236068237c8STej Parkash ql4_printk(KERN_INFO, ha, 2237068237c8STej Parkash "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n", 2238068237c8STej Parkash data_collected, ha->fw_dump_size); 2239068237c8STej Parkash goto md_failed; 2240068237c8STej Parkash } 2241068237c8STej Parkash 2242068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n", 2243068237c8STej Parkash __func__, i)); 2244068237c8STej Parkash md_failed: 2245068237c8STej Parkash return rval; 2246068237c8STej Parkash } 2247068237c8STej Parkash 2248068237c8STej Parkash /** 2249068237c8STej Parkash * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready. 2250068237c8STej Parkash * @ha: pointer to adapter structure 2251068237c8STej Parkash **/ 2252068237c8STej Parkash static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code) 2253068237c8STej Parkash { 2254068237c8STej Parkash char event_string[40]; 2255068237c8STej Parkash char *envp[] = { event_string, NULL }; 2256068237c8STej Parkash 2257068237c8STej Parkash switch (code) { 2258068237c8STej Parkash case QL4_UEVENT_CODE_FW_DUMP: 2259068237c8STej Parkash snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 2260068237c8STej Parkash ha->host_no); 2261068237c8STej Parkash break; 2262068237c8STej Parkash default: 2263068237c8STej Parkash /*do nothing*/ 2264068237c8STej Parkash break; 2265068237c8STej Parkash } 2266068237c8STej Parkash 2267068237c8STej Parkash kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp); 2268068237c8STej Parkash } 2269068237c8STej Parkash 2270f4f5df23SVikas Chaudhary /** 2271f4f5df23SVikas Chaudhary * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw 2272f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 2273f4f5df23SVikas Chaudhary * 2274f4f5df23SVikas Chaudhary * Note: IDC lock must be held upon entry 2275f4f5df23SVikas Chaudhary **/ 2276f4f5df23SVikas Chaudhary static int 2277f4f5df23SVikas Chaudhary qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) 2278f4f5df23SVikas Chaudhary { 2279b25ee66fSShyam Sundar int rval = QLA_ERROR; 2280b25ee66fSShyam Sundar int i, timeout; 2281f4f5df23SVikas Chaudhary uint32_t old_count, count; 2282b25ee66fSShyam Sundar int need_reset = 0, peg_stuck = 1; 2283f4f5df23SVikas Chaudhary 2284b25ee66fSShyam Sundar need_reset = qla4_8xxx_need_reset(ha); 2285f4f5df23SVikas Chaudhary 2286f8086f4fSVikas Chaudhary old_count = qla4_82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2287f4f5df23SVikas Chaudhary 2288f4f5df23SVikas Chaudhary for (i = 0; i < 10; i++) { 2289f4f5df23SVikas Chaudhary timeout = msleep_interruptible(200); 2290f4f5df23SVikas Chaudhary if (timeout) { 2291f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2292f4f5df23SVikas Chaudhary QLA82XX_DEV_FAILED); 2293b25ee66fSShyam Sundar return rval; 2294f4f5df23SVikas Chaudhary } 2295f4f5df23SVikas Chaudhary 2296f8086f4fSVikas Chaudhary count = qla4_82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 2297f4f5df23SVikas Chaudhary if (count != old_count) 2298b25ee66fSShyam Sundar peg_stuck = 0; 2299b25ee66fSShyam Sundar } 2300b25ee66fSShyam Sundar 2301b25ee66fSShyam Sundar if (need_reset) { 2302b25ee66fSShyam Sundar /* We are trying to perform a recovery here. */ 2303b25ee66fSShyam Sundar if (peg_stuck) 2304f8086f4fSVikas Chaudhary qla4_82xx_rom_lock_recovery(ha); 2305b25ee66fSShyam Sundar goto dev_initialize; 2306b25ee66fSShyam Sundar } else { 2307b25ee66fSShyam Sundar /* Start of day for this ha context. */ 2308b25ee66fSShyam Sundar if (peg_stuck) { 2309b25ee66fSShyam Sundar /* Either we are the first or recovery in progress. */ 2310f8086f4fSVikas Chaudhary qla4_82xx_rom_lock_recovery(ha); 2311b25ee66fSShyam Sundar goto dev_initialize; 2312b25ee66fSShyam Sundar } else { 2313b25ee66fSShyam Sundar /* Firmware already running. */ 2314b25ee66fSShyam Sundar rval = QLA_SUCCESS; 2315f4f5df23SVikas Chaudhary goto dev_ready; 2316f4f5df23SVikas Chaudhary } 2317b25ee66fSShyam Sundar } 2318f4f5df23SVikas Chaudhary 2319f4f5df23SVikas Chaudhary dev_initialize: 2320f4f5df23SVikas Chaudhary /* set to DEV_INITIALIZING */ 2321f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 2322f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 2323f4f5df23SVikas Chaudhary 2324f4f5df23SVikas Chaudhary /* Driver that sets device state to initializating sets IDC version */ 2325f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 2326f4f5df23SVikas Chaudhary 2327f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2328068237c8STej Parkash if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) && 2329068237c8STej Parkash !test_and_set_bit(AF_82XX_FW_DUMPED, &ha->flags)) { 2330068237c8STej Parkash if (!qla4_8xxx_collect_md_data(ha)) { 2331068237c8STej Parkash qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP); 2332068237c8STej Parkash } else { 2333068237c8STej Parkash ql4_printk(KERN_INFO, ha, "Unable to collect minidump\n"); 2334068237c8STej Parkash clear_bit(AF_82XX_FW_DUMPED, &ha->flags); 2335068237c8STej Parkash } 2336068237c8STej Parkash } 2337f8086f4fSVikas Chaudhary rval = qla4_82xx_try_start_fw(ha); 2338f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2339f4f5df23SVikas Chaudhary 2340f4f5df23SVikas Chaudhary if (rval != QLA_SUCCESS) { 2341f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 2342f4f5df23SVikas Chaudhary qla4_8xxx_clear_drv_active(ha); 2343f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 2344f4f5df23SVikas Chaudhary return rval; 2345f4f5df23SVikas Chaudhary } 2346f4f5df23SVikas Chaudhary 2347f4f5df23SVikas Chaudhary dev_ready: 2348f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 2349f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 2350f4f5df23SVikas Chaudhary 2351b25ee66fSShyam Sundar return rval; 2352f4f5df23SVikas Chaudhary } 2353f4f5df23SVikas Chaudhary 2354f4f5df23SVikas Chaudhary /** 2355f8086f4fSVikas Chaudhary * qla4_82xx_need_reset_handler - Code to start reset sequence 2356f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 2357f4f5df23SVikas Chaudhary * 2358f4f5df23SVikas Chaudhary * Note: IDC lock must be held upon entry 2359f4f5df23SVikas Chaudhary **/ 2360f4f5df23SVikas Chaudhary static void 2361f8086f4fSVikas Chaudhary qla4_82xx_need_reset_handler(struct scsi_qla_host *ha) 2362f4f5df23SVikas Chaudhary { 2363f4f5df23SVikas Chaudhary uint32_t dev_state, drv_state, drv_active; 2364068237c8STej Parkash uint32_t active_mask = 0xFFFFFFFF; 2365f4f5df23SVikas Chaudhary unsigned long reset_timeout; 2366f4f5df23SVikas Chaudhary 2367f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 2368f4f5df23SVikas Chaudhary "Performing ISP error recovery\n"); 2369f4f5df23SVikas Chaudhary 2370f4f5df23SVikas Chaudhary if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { 2371f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2372f4f5df23SVikas Chaudhary ha->isp_ops->disable_intrs(ha); 2373f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2374f4f5df23SVikas Chaudhary } 2375f4f5df23SVikas Chaudhary 2376068237c8STej Parkash if (!test_bit(AF_82XX_RST_OWNER, &ha->flags)) { 2377068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2378068237c8STej Parkash "%s(%ld): reset acknowledged\n", 2379068237c8STej Parkash __func__, ha->host_no)); 2380f4f5df23SVikas Chaudhary qla4_8xxx_set_rst_ready(ha); 2381068237c8STej Parkash } else { 2382068237c8STej Parkash active_mask = (~(1 << (ha->func_num * 4))); 2383068237c8STej Parkash } 2384f4f5df23SVikas Chaudhary 2385f4f5df23SVikas Chaudhary /* wait for 10 seconds for reset ack from all functions */ 2386f4f5df23SVikas Chaudhary reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 2387f4f5df23SVikas Chaudhary 2388f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2389f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2390f4f5df23SVikas Chaudhary 2391f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 2392f4f5df23SVikas Chaudhary "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 2393f4f5df23SVikas Chaudhary __func__, ha->host_no, drv_state, drv_active); 2394f4f5df23SVikas Chaudhary 2395068237c8STej Parkash while (drv_state != (drv_active & active_mask)) { 2396f4f5df23SVikas Chaudhary if (time_after_eq(jiffies, reset_timeout)) { 2397068237c8STej Parkash ql4_printk(KERN_INFO, ha, 2398068237c8STej Parkash "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", 2399068237c8STej Parkash DRIVER_NAME, drv_state, drv_active); 2400f4f5df23SVikas Chaudhary break; 2401f4f5df23SVikas Chaudhary } 2402f4f5df23SVikas Chaudhary 2403068237c8STej Parkash /* 2404068237c8STej Parkash * When reset_owner times out, check which functions 2405068237c8STej Parkash * acked/did not ack 2406068237c8STej Parkash */ 2407068237c8STej Parkash if (test_bit(AF_82XX_RST_OWNER, &ha->flags)) { 2408068237c8STej Parkash ql4_printk(KERN_INFO, ha, 2409068237c8STej Parkash "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 2410068237c8STej Parkash __func__, ha->host_no, drv_state, 2411068237c8STej Parkash drv_active); 2412068237c8STej Parkash } 2413f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2414f4f5df23SVikas Chaudhary msleep(1000); 2415f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2416f4f5df23SVikas Chaudhary 2417f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2418f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2419f4f5df23SVikas Chaudhary } 2420f4f5df23SVikas Chaudhary 2421068237c8STej Parkash /* Clear RESET OWNER as we are not going to use it any further */ 2422068237c8STej Parkash clear_bit(AF_82XX_RST_OWNER, &ha->flags); 2423068237c8STej Parkash 2424f8086f4fSVikas Chaudhary dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2425068237c8STej Parkash ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, 2426f4f5df23SVikas Chaudhary dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 2427f4f5df23SVikas Chaudhary 2428f4f5df23SVikas Chaudhary /* Force to DEV_COLD unless someone else is starting a reset */ 2429f4f5df23SVikas Chaudhary if (dev_state != QLA82XX_DEV_INITIALIZING) { 2430f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 2431f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 2432068237c8STej Parkash qla4_8xxx_set_rst_ready(ha); 2433f4f5df23SVikas Chaudhary } 2434f4f5df23SVikas Chaudhary } 2435f4f5df23SVikas Chaudhary 2436f4f5df23SVikas Chaudhary /** 2437f4f5df23SVikas Chaudhary * qla4_8xxx_need_qsnt_handler - Code to start qsnt 2438f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 2439f4f5df23SVikas Chaudhary **/ 2440f4f5df23SVikas Chaudhary void 2441f4f5df23SVikas Chaudhary qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 2442f4f5df23SVikas Chaudhary { 2443f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2444f4f5df23SVikas Chaudhary qla4_8xxx_set_qsnt_ready(ha); 2445f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2446f4f5df23SVikas Chaudhary } 2447f4f5df23SVikas Chaudhary 2448f4f5df23SVikas Chaudhary /** 2449f4f5df23SVikas Chaudhary * qla4_8xxx_device_state_handler - Adapter state machine 2450f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 2451f4f5df23SVikas Chaudhary * 2452f4f5df23SVikas Chaudhary * Note: IDC lock must be UNLOCKED upon entry 2453f4f5df23SVikas Chaudhary **/ 2454f4f5df23SVikas Chaudhary int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) 2455f4f5df23SVikas Chaudhary { 2456f4f5df23SVikas Chaudhary uint32_t dev_state; 2457f4f5df23SVikas Chaudhary int rval = QLA_SUCCESS; 2458f4f5df23SVikas Chaudhary unsigned long dev_init_timeout; 2459f4f5df23SVikas Chaudhary 2460e3f37d16SNilesh Javali if (!test_bit(AF_INIT_DONE, &ha->flags)) { 2461f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2462f4f5df23SVikas Chaudhary qla4_8xxx_set_drv_active(ha); 2463f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2464e3f37d16SNilesh Javali } 2465f4f5df23SVikas Chaudhary 2466f8086f4fSVikas Chaudhary dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2467068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 2468068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 2469068237c8STej Parkash qdev_state[dev_state] : "Unknown")); 2470f4f5df23SVikas Chaudhary 2471f4f5df23SVikas Chaudhary /* wait for 30 seconds for device to go ready */ 2472f4f5df23SVikas Chaudhary dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 2473f4f5df23SVikas Chaudhary 2474f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2475e3f37d16SNilesh Javali while (1) { 2476f4f5df23SVikas Chaudhary 2477f4f5df23SVikas Chaudhary if (time_after_eq(jiffies, dev_init_timeout)) { 2478068237c8STej Parkash ql4_printk(KERN_WARNING, ha, 2479068237c8STej Parkash "%s: Device Init Failed 0x%x = %s\n", 2480068237c8STej Parkash DRIVER_NAME, 2481068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 2482068237c8STej Parkash qdev_state[dev_state] : "Unknown"); 2483f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2484f4f5df23SVikas Chaudhary QLA82XX_DEV_FAILED); 2485f4f5df23SVikas Chaudhary } 2486f4f5df23SVikas Chaudhary 2487f8086f4fSVikas Chaudhary dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2488068237c8STej Parkash ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 2489068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 2490068237c8STej Parkash qdev_state[dev_state] : "Unknown"); 2491f4f5df23SVikas Chaudhary 2492f4f5df23SVikas Chaudhary /* NOTE: Make sure idc unlocked upon exit of switch statement */ 2493f4f5df23SVikas Chaudhary switch (dev_state) { 2494f4f5df23SVikas Chaudhary case QLA82XX_DEV_READY: 2495f4f5df23SVikas Chaudhary goto exit; 2496f4f5df23SVikas Chaudhary case QLA82XX_DEV_COLD: 2497f4f5df23SVikas Chaudhary rval = qla4_8xxx_device_bootstrap(ha); 2498f4f5df23SVikas Chaudhary goto exit; 2499f4f5df23SVikas Chaudhary case QLA82XX_DEV_INITIALIZING: 2500f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2501f4f5df23SVikas Chaudhary msleep(1000); 2502f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2503f4f5df23SVikas Chaudhary break; 2504f4f5df23SVikas Chaudhary case QLA82XX_DEV_NEED_RESET: 2505f4f5df23SVikas Chaudhary if (!ql4xdontresethba) { 2506f8086f4fSVikas Chaudhary qla4_82xx_need_reset_handler(ha); 2507f4f5df23SVikas Chaudhary /* Update timeout value after need 2508f4f5df23SVikas Chaudhary * reset handler */ 2509f4f5df23SVikas Chaudhary dev_init_timeout = jiffies + 2510f4f5df23SVikas Chaudhary (ha->nx_dev_init_timeout * HZ); 25119acf7533SMike Hernandez } else { 2512f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 25139acf7533SMike Hernandez msleep(1000); 2514f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2515f4f5df23SVikas Chaudhary } 2516f4f5df23SVikas Chaudhary break; 2517f4f5df23SVikas Chaudhary case QLA82XX_DEV_NEED_QUIESCENT: 2518f4f5df23SVikas Chaudhary /* idc locked/unlocked in handler */ 2519f4f5df23SVikas Chaudhary qla4_8xxx_need_qsnt_handler(ha); 2520e3f37d16SNilesh Javali break; 2521f4f5df23SVikas Chaudhary case QLA82XX_DEV_QUIESCENT: 2522f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2523f4f5df23SVikas Chaudhary msleep(1000); 2524f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2525f4f5df23SVikas Chaudhary break; 2526f4f5df23SVikas Chaudhary case QLA82XX_DEV_FAILED: 2527f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2528f4f5df23SVikas Chaudhary qla4xxx_dead_adapter_cleanup(ha); 2529f4f5df23SVikas Chaudhary rval = QLA_ERROR; 2530f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2531f4f5df23SVikas Chaudhary goto exit; 2532f4f5df23SVikas Chaudhary default: 2533f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2534f4f5df23SVikas Chaudhary qla4xxx_dead_adapter_cleanup(ha); 2535f4f5df23SVikas Chaudhary rval = QLA_ERROR; 2536f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2537f4f5df23SVikas Chaudhary goto exit; 2538f4f5df23SVikas Chaudhary } 2539f4f5df23SVikas Chaudhary } 2540f4f5df23SVikas Chaudhary exit: 2541f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2542f4f5df23SVikas Chaudhary return rval; 2543f4f5df23SVikas Chaudhary } 2544f4f5df23SVikas Chaudhary 2545f4f5df23SVikas Chaudhary int qla4_8xxx_load_risc(struct scsi_qla_host *ha) 2546f4f5df23SVikas Chaudhary { 2547f4f5df23SVikas Chaudhary int retval; 254878764999SSarang Radke 254978764999SSarang Radke /* clear the interrupt */ 25507664a1fdSVikas Chaudhary writel(0, &ha->qla4_82xx_reg->host_int); 25517664a1fdSVikas Chaudhary readl(&ha->qla4_82xx_reg->host_int); 255278764999SSarang Radke 2553f4f5df23SVikas Chaudhary retval = qla4_8xxx_device_state_handler(ha); 2554f4f5df23SVikas Chaudhary 2555f581a3f7SVikas Chaudhary if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags)) 2556f4f5df23SVikas Chaudhary retval = qla4xxx_request_irqs(ha); 2557f581a3f7SVikas Chaudhary 2558f4f5df23SVikas Chaudhary return retval; 2559f4f5df23SVikas Chaudhary } 2560f4f5df23SVikas Chaudhary 2561f4f5df23SVikas Chaudhary /*****************************************************************************/ 2562f4f5df23SVikas Chaudhary /* Flash Manipulation Routines */ 2563f4f5df23SVikas Chaudhary /*****************************************************************************/ 2564f4f5df23SVikas Chaudhary 2565f4f5df23SVikas Chaudhary #define OPTROM_BURST_SIZE 0x1000 2566f4f5df23SVikas Chaudhary #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 2567f4f5df23SVikas Chaudhary 2568f4f5df23SVikas Chaudhary #define FARX_DATA_FLAG BIT_31 2569f4f5df23SVikas Chaudhary #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 2570f4f5df23SVikas Chaudhary #define FARX_ACCESS_FLASH_DATA 0x7FF00000 2571f4f5df23SVikas Chaudhary 2572f4f5df23SVikas Chaudhary static inline uint32_t 2573f4f5df23SVikas Chaudhary flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 2574f4f5df23SVikas Chaudhary { 2575f4f5df23SVikas Chaudhary return hw->flash_conf_off | faddr; 2576f4f5df23SVikas Chaudhary } 2577f4f5df23SVikas Chaudhary 2578f4f5df23SVikas Chaudhary static inline uint32_t 2579f4f5df23SVikas Chaudhary flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 2580f4f5df23SVikas Chaudhary { 2581f4f5df23SVikas Chaudhary return hw->flash_data_off | faddr; 2582f4f5df23SVikas Chaudhary } 2583f4f5df23SVikas Chaudhary 2584f4f5df23SVikas Chaudhary static uint32_t * 2585f8086f4fSVikas Chaudhary qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, 2586f4f5df23SVikas Chaudhary uint32_t faddr, uint32_t length) 2587f4f5df23SVikas Chaudhary { 2588f4f5df23SVikas Chaudhary uint32_t i; 2589f4f5df23SVikas Chaudhary uint32_t val; 2590f4f5df23SVikas Chaudhary int loops = 0; 2591f8086f4fSVikas Chaudhary while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { 2592f4f5df23SVikas Chaudhary udelay(100); 2593f4f5df23SVikas Chaudhary cond_resched(); 2594f4f5df23SVikas Chaudhary loops++; 2595f4f5df23SVikas Chaudhary } 2596f4f5df23SVikas Chaudhary if (loops >= 50000) { 2597f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); 2598f4f5df23SVikas Chaudhary return dwptr; 2599f4f5df23SVikas Chaudhary } 2600f4f5df23SVikas Chaudhary 2601f4f5df23SVikas Chaudhary /* Dword reads to flash. */ 2602f4f5df23SVikas Chaudhary for (i = 0; i < length/4; i++, faddr += 4) { 2603f8086f4fSVikas Chaudhary if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) { 2604f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 2605f4f5df23SVikas Chaudhary "Do ROM fast read failed\n"); 2606f4f5df23SVikas Chaudhary goto done_read; 2607f4f5df23SVikas Chaudhary } 2608f4f5df23SVikas Chaudhary dwptr[i] = __constant_cpu_to_le32(val); 2609f4f5df23SVikas Chaudhary } 2610f4f5df23SVikas Chaudhary 2611f4f5df23SVikas Chaudhary done_read: 2612f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 2613f4f5df23SVikas Chaudhary return dwptr; 2614f4f5df23SVikas Chaudhary } 2615f4f5df23SVikas Chaudhary 2616f4f5df23SVikas Chaudhary /** 2617f4f5df23SVikas Chaudhary * Address and length are byte address 2618f4f5df23SVikas Chaudhary **/ 2619f4f5df23SVikas Chaudhary static uint8_t * 2620f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 2621f4f5df23SVikas Chaudhary uint32_t offset, uint32_t length) 2622f4f5df23SVikas Chaudhary { 2623f8086f4fSVikas Chaudhary qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length); 2624f4f5df23SVikas Chaudhary return buf; 2625f4f5df23SVikas Chaudhary } 2626f4f5df23SVikas Chaudhary 2627f4f5df23SVikas Chaudhary static int 2628f4f5df23SVikas Chaudhary qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) 2629f4f5df23SVikas Chaudhary { 2630f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "DEF", "PCI" }; 2631f4f5df23SVikas Chaudhary 2632f4f5df23SVikas Chaudhary /* 2633f4f5df23SVikas Chaudhary * FLT-location structure resides after the last PCI region. 2634f4f5df23SVikas Chaudhary */ 2635f4f5df23SVikas Chaudhary 2636f4f5df23SVikas Chaudhary /* Begin with sane defaults. */ 2637f4f5df23SVikas Chaudhary loc = locations[0]; 2638f4f5df23SVikas Chaudhary *start = FA_FLASH_LAYOUT_ADDR_82; 2639f4f5df23SVikas Chaudhary 2640f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 2641f4f5df23SVikas Chaudhary return QLA_SUCCESS; 2642f4f5df23SVikas Chaudhary } 2643f4f5df23SVikas Chaudhary 2644f4f5df23SVikas Chaudhary static void 2645f4f5df23SVikas Chaudhary qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) 2646f4f5df23SVikas Chaudhary { 2647f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "DEF", "FLT" }; 2648f4f5df23SVikas Chaudhary uint16_t *wptr; 2649f4f5df23SVikas Chaudhary uint16_t cnt, chksum; 2650f4f5df23SVikas Chaudhary uint32_t start; 2651f4f5df23SVikas Chaudhary struct qla_flt_header *flt; 2652f4f5df23SVikas Chaudhary struct qla_flt_region *region; 2653f4f5df23SVikas Chaudhary struct ql82xx_hw_data *hw = &ha->hw; 2654f4f5df23SVikas Chaudhary 2655f4f5df23SVikas Chaudhary hw->flt_region_flt = flt_addr; 2656f4f5df23SVikas Chaudhary wptr = (uint16_t *)ha->request_ring; 2657f4f5df23SVikas Chaudhary flt = (struct qla_flt_header *)ha->request_ring; 2658f4f5df23SVikas Chaudhary region = (struct qla_flt_region *)&flt[1]; 2659f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2660f4f5df23SVikas Chaudhary flt_addr << 2, OPTROM_BURST_SIZE); 2661f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le16(0xffff)) 2662f4f5df23SVikas Chaudhary goto no_flash_data; 2663f4f5df23SVikas Chaudhary if (flt->version != __constant_cpu_to_le16(1)) { 2664f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " 2665f4f5df23SVikas Chaudhary "version=0x%x length=0x%x checksum=0x%x.\n", 2666f4f5df23SVikas Chaudhary le16_to_cpu(flt->version), le16_to_cpu(flt->length), 2667f4f5df23SVikas Chaudhary le16_to_cpu(flt->checksum))); 2668f4f5df23SVikas Chaudhary goto no_flash_data; 2669f4f5df23SVikas Chaudhary } 2670f4f5df23SVikas Chaudhary 2671f4f5df23SVikas Chaudhary cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 2672f4f5df23SVikas Chaudhary for (chksum = 0; cnt; cnt--) 2673f4f5df23SVikas Chaudhary chksum += le16_to_cpu(*wptr++); 2674f4f5df23SVikas Chaudhary if (chksum) { 2675f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 2676f4f5df23SVikas Chaudhary "version=0x%x length=0x%x checksum=0x%x.\n", 2677f4f5df23SVikas Chaudhary le16_to_cpu(flt->version), le16_to_cpu(flt->length), 2678f4f5df23SVikas Chaudhary chksum)); 2679f4f5df23SVikas Chaudhary goto no_flash_data; 2680f4f5df23SVikas Chaudhary } 2681f4f5df23SVikas Chaudhary 2682f4f5df23SVikas Chaudhary loc = locations[1]; 2683f4f5df23SVikas Chaudhary cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 2684f4f5df23SVikas Chaudhary for ( ; cnt; cnt--, region++) { 2685f4f5df23SVikas Chaudhary /* Store addresses as DWORD offsets. */ 2686f4f5df23SVikas Chaudhary start = le32_to_cpu(region->start) >> 2; 2687f4f5df23SVikas Chaudhary 2688f4f5df23SVikas Chaudhary DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 2689f4f5df23SVikas Chaudhary "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 2690f4f5df23SVikas Chaudhary le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 2691f4f5df23SVikas Chaudhary 2692f4f5df23SVikas Chaudhary switch (le32_to_cpu(region->code) & 0xff) { 2693f4f5df23SVikas Chaudhary case FLT_REG_FDT: 2694f4f5df23SVikas Chaudhary hw->flt_region_fdt = start; 2695f4f5df23SVikas Chaudhary break; 2696f4f5df23SVikas Chaudhary case FLT_REG_BOOT_CODE_82: 2697f4f5df23SVikas Chaudhary hw->flt_region_boot = start; 2698f4f5df23SVikas Chaudhary break; 2699f4f5df23SVikas Chaudhary case FLT_REG_FW_82: 270093823956SNilesh Javali case FLT_REG_FW_82_1: 2701f4f5df23SVikas Chaudhary hw->flt_region_fw = start; 2702f4f5df23SVikas Chaudhary break; 2703f4f5df23SVikas Chaudhary case FLT_REG_BOOTLOAD_82: 2704f4f5df23SVikas Chaudhary hw->flt_region_bootload = start; 2705f4f5df23SVikas Chaudhary break; 27062a991c21SManish Rangankar case FLT_REG_ISCSI_PARAM: 27072a991c21SManish Rangankar hw->flt_iscsi_param = start; 27082a991c21SManish Rangankar break; 27094549415aSLalit Chandivade case FLT_REG_ISCSI_CHAP: 27104549415aSLalit Chandivade hw->flt_region_chap = start; 27114549415aSLalit Chandivade hw->flt_chap_size = le32_to_cpu(region->size); 27124549415aSLalit Chandivade break; 2713f4f5df23SVikas Chaudhary } 2714f4f5df23SVikas Chaudhary } 2715f4f5df23SVikas Chaudhary goto done; 2716f4f5df23SVikas Chaudhary 2717f4f5df23SVikas Chaudhary no_flash_data: 2718f4f5df23SVikas Chaudhary /* Use hardcoded defaults. */ 2719f4f5df23SVikas Chaudhary loc = locations[0]; 2720f4f5df23SVikas Chaudhary 2721f4f5df23SVikas Chaudhary hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; 2722f4f5df23SVikas Chaudhary hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; 2723f4f5df23SVikas Chaudhary hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; 2724f4f5df23SVikas Chaudhary hw->flt_region_fw = FA_RISC_CODE_ADDR_82; 27254549415aSLalit Chandivade hw->flt_region_chap = FA_FLASH_ISCSI_CHAP; 27264549415aSLalit Chandivade hw->flt_chap_size = FA_FLASH_CHAP_SIZE; 27274549415aSLalit Chandivade 2728f4f5df23SVikas Chaudhary done: 2729f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x " 2730f4f5df23SVikas Chaudhary "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt, 2731f4f5df23SVikas Chaudhary hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload, 2732f4f5df23SVikas Chaudhary hw->flt_region_fw)); 2733f4f5df23SVikas Chaudhary } 2734f4f5df23SVikas Chaudhary 2735f4f5df23SVikas Chaudhary static void 2736f8086f4fSVikas Chaudhary qla4_82xx_get_fdt_info(struct scsi_qla_host *ha) 2737f4f5df23SVikas Chaudhary { 2738f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_4K 0x1000 2739f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_32K 0x8000 2740f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_64K 0x10000 2741f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "MID", "FDT" }; 2742f4f5df23SVikas Chaudhary uint16_t cnt, chksum; 2743f4f5df23SVikas Chaudhary uint16_t *wptr; 2744f4f5df23SVikas Chaudhary struct qla_fdt_layout *fdt; 27453c3e2108SVikas Chaudhary uint16_t mid = 0; 27463c3e2108SVikas Chaudhary uint16_t fid = 0; 2747f4f5df23SVikas Chaudhary struct ql82xx_hw_data *hw = &ha->hw; 2748f4f5df23SVikas Chaudhary 2749f4f5df23SVikas Chaudhary hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2750f4f5df23SVikas Chaudhary hw->flash_data_off = FARX_ACCESS_FLASH_DATA; 2751f4f5df23SVikas Chaudhary 2752f4f5df23SVikas Chaudhary wptr = (uint16_t *)ha->request_ring; 2753f4f5df23SVikas Chaudhary fdt = (struct qla_fdt_layout *)ha->request_ring; 2754f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2755f4f5df23SVikas Chaudhary hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); 2756f4f5df23SVikas Chaudhary 2757f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le16(0xffff)) 2758f4f5df23SVikas Chaudhary goto no_flash_data; 2759f4f5df23SVikas Chaudhary 2760f4f5df23SVikas Chaudhary if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 2761f4f5df23SVikas Chaudhary fdt->sig[3] != 'D') 2762f4f5df23SVikas Chaudhary goto no_flash_data; 2763f4f5df23SVikas Chaudhary 2764f4f5df23SVikas Chaudhary for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 2765f4f5df23SVikas Chaudhary cnt++) 2766f4f5df23SVikas Chaudhary chksum += le16_to_cpu(*wptr++); 2767f4f5df23SVikas Chaudhary 2768f4f5df23SVikas Chaudhary if (chksum) { 2769f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 2770f4f5df23SVikas Chaudhary "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 2771f4f5df23SVikas Chaudhary le16_to_cpu(fdt->version))); 2772f4f5df23SVikas Chaudhary goto no_flash_data; 2773f4f5df23SVikas Chaudhary } 2774f4f5df23SVikas Chaudhary 2775f4f5df23SVikas Chaudhary loc = locations[1]; 2776f4f5df23SVikas Chaudhary mid = le16_to_cpu(fdt->man_id); 2777f4f5df23SVikas Chaudhary fid = le16_to_cpu(fdt->id); 2778f4f5df23SVikas Chaudhary hw->fdt_wrt_disable = fdt->wrt_disable_bits; 2779f4f5df23SVikas Chaudhary hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); 2780f4f5df23SVikas Chaudhary hw->fdt_block_size = le32_to_cpu(fdt->block_size); 2781f4f5df23SVikas Chaudhary 2782f4f5df23SVikas Chaudhary if (fdt->unprotect_sec_cmd) { 2783f4f5df23SVikas Chaudhary hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | 2784f4f5df23SVikas Chaudhary fdt->unprotect_sec_cmd); 2785f4f5df23SVikas Chaudhary hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 2786f4f5df23SVikas Chaudhary flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : 2787f4f5df23SVikas Chaudhary flash_conf_addr(hw, 0x0336); 2788f4f5df23SVikas Chaudhary } 2789f4f5df23SVikas Chaudhary goto done; 2790f4f5df23SVikas Chaudhary 2791f4f5df23SVikas Chaudhary no_flash_data: 2792f4f5df23SVikas Chaudhary loc = locations[0]; 2793f4f5df23SVikas Chaudhary hw->fdt_block_size = FLASH_BLK_SIZE_64K; 2794f4f5df23SVikas Chaudhary done: 2795f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 2796f4f5df23SVikas Chaudhary "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 2797f4f5df23SVikas Chaudhary hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, 2798f4f5df23SVikas Chaudhary hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, 2799f4f5df23SVikas Chaudhary hw->fdt_block_size)); 2800f4f5df23SVikas Chaudhary } 2801f4f5df23SVikas Chaudhary 2802f4f5df23SVikas Chaudhary static void 2803f8086f4fSVikas Chaudhary qla4_82xx_get_idc_param(struct scsi_qla_host *ha) 2804f4f5df23SVikas Chaudhary { 2805f4f5df23SVikas Chaudhary #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 2806f4f5df23SVikas Chaudhary uint32_t *wptr; 2807f4f5df23SVikas Chaudhary 2808f4f5df23SVikas Chaudhary if (!is_qla8022(ha)) 2809f4f5df23SVikas Chaudhary return; 2810f4f5df23SVikas Chaudhary wptr = (uint32_t *)ha->request_ring; 2811f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2812f4f5df23SVikas Chaudhary QLA82XX_IDC_PARAM_ADDR , 8); 2813f4f5df23SVikas Chaudhary 2814f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 2815f4f5df23SVikas Chaudhary ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; 2816f4f5df23SVikas Chaudhary ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; 2817f4f5df23SVikas Chaudhary } else { 2818f4f5df23SVikas Chaudhary ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 2819f4f5df23SVikas Chaudhary ha->nx_reset_timeout = le32_to_cpu(*wptr); 2820f4f5df23SVikas Chaudhary } 2821f4f5df23SVikas Chaudhary 2822f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_DEBUG, ha, 2823f4f5df23SVikas Chaudhary "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); 2824f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_DEBUG, ha, 2825f4f5df23SVikas Chaudhary "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); 2826f4f5df23SVikas Chaudhary return; 2827f4f5df23SVikas Chaudhary } 2828f4f5df23SVikas Chaudhary 2829f4f5df23SVikas Chaudhary int 2830f4f5df23SVikas Chaudhary qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 2831f4f5df23SVikas Chaudhary { 2832f4f5df23SVikas Chaudhary int ret; 2833f4f5df23SVikas Chaudhary uint32_t flt_addr; 2834f4f5df23SVikas Chaudhary 2835f4f5df23SVikas Chaudhary ret = qla4_8xxx_find_flt_start(ha, &flt_addr); 2836f4f5df23SVikas Chaudhary if (ret != QLA_SUCCESS) 2837f4f5df23SVikas Chaudhary return ret; 2838f4f5df23SVikas Chaudhary 2839f4f5df23SVikas Chaudhary qla4_8xxx_get_flt_info(ha, flt_addr); 2840f8086f4fSVikas Chaudhary qla4_82xx_get_fdt_info(ha); 2841f8086f4fSVikas Chaudhary qla4_82xx_get_idc_param(ha); 2842f4f5df23SVikas Chaudhary 2843f4f5df23SVikas Chaudhary return QLA_SUCCESS; 2844f4f5df23SVikas Chaudhary } 2845f4f5df23SVikas Chaudhary 2846f4f5df23SVikas Chaudhary /** 2847f4f5df23SVikas Chaudhary * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance 2848f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 2849f4f5df23SVikas Chaudhary * 2850f4f5df23SVikas Chaudhary * Remarks: 2851f4f5df23SVikas Chaudhary * For iSCSI, throws away all I/O and AENs into bit bucket, so they will 2852f4f5df23SVikas Chaudhary * not be available after successful return. Driver must cleanup potential 2853f4f5df23SVikas Chaudhary * outstanding I/O's after calling this funcion. 2854f4f5df23SVikas Chaudhary **/ 2855f4f5df23SVikas Chaudhary int 2856f4f5df23SVikas Chaudhary qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) 2857f4f5df23SVikas Chaudhary { 2858f4f5df23SVikas Chaudhary int status; 2859f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 2860f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 2861f4f5df23SVikas Chaudhary 2862f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2863f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 2864f4f5df23SVikas Chaudhary 2865f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_STOP_FW; 2866f4f5df23SVikas Chaudhary status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, 2867f4f5df23SVikas Chaudhary &mbox_cmd[0], &mbox_sts[0]); 2868f4f5df23SVikas Chaudhary 2869f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, 2870f4f5df23SVikas Chaudhary __func__, status)); 2871f4f5df23SVikas Chaudhary return status; 2872f4f5df23SVikas Chaudhary } 2873f4f5df23SVikas Chaudhary 2874f4f5df23SVikas Chaudhary /** 2875f8086f4fSVikas Chaudhary * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands. 2876f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 2877f4f5df23SVikas Chaudhary **/ 2878f4f5df23SVikas Chaudhary int 2879f8086f4fSVikas Chaudhary qla4_82xx_isp_reset(struct scsi_qla_host *ha) 2880f4f5df23SVikas Chaudhary { 2881f4f5df23SVikas Chaudhary int rval; 2882f4f5df23SVikas Chaudhary uint32_t dev_state; 2883f4f5df23SVikas Chaudhary 2884f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2885f8086f4fSVikas Chaudhary dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2886f4f5df23SVikas Chaudhary 2887f4f5df23SVikas Chaudhary if (dev_state == QLA82XX_DEV_READY) { 2888f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 2889f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2890f4f5df23SVikas Chaudhary QLA82XX_DEV_NEED_RESET); 2891068237c8STej Parkash set_bit(AF_82XX_RST_OWNER, &ha->flags); 2892f4f5df23SVikas Chaudhary } else 2893f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); 2894f4f5df23SVikas Chaudhary 2895f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2896f4f5df23SVikas Chaudhary 2897f4f5df23SVikas Chaudhary rval = qla4_8xxx_device_state_handler(ha); 2898f4f5df23SVikas Chaudhary 2899f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2900f4f5df23SVikas Chaudhary qla4_8xxx_clear_rst_ready(ha); 2901f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2902f4f5df23SVikas Chaudhary 2903068237c8STej Parkash if (rval == QLA_SUCCESS) { 2904f8086f4fSVikas Chaudhary ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n"); 290521033639SNilesh Javali clear_bit(AF_FW_RECOVERY, &ha->flags); 2906068237c8STej Parkash } 290721033639SNilesh Javali 2908f4f5df23SVikas Chaudhary return rval; 2909f4f5df23SVikas Chaudhary } 2910f4f5df23SVikas Chaudhary 2911f4f5df23SVikas Chaudhary /** 2912f4f5df23SVikas Chaudhary * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number 2913f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 2914f4f5df23SVikas Chaudhary * 2915f4f5df23SVikas Chaudhary **/ 2916f4f5df23SVikas Chaudhary int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) 2917f4f5df23SVikas Chaudhary { 2918f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 2919f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 2920f4f5df23SVikas Chaudhary struct mbx_sys_info *sys_info; 2921f4f5df23SVikas Chaudhary dma_addr_t sys_info_dma; 2922f4f5df23SVikas Chaudhary int status = QLA_ERROR; 2923f4f5df23SVikas Chaudhary 2924f4f5df23SVikas Chaudhary sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), 2925f4f5df23SVikas Chaudhary &sys_info_dma, GFP_KERNEL); 2926f4f5df23SVikas Chaudhary if (sys_info == NULL) { 2927f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", 2928f4f5df23SVikas Chaudhary ha->host_no, __func__)); 2929f4f5df23SVikas Chaudhary return status; 2930f4f5df23SVikas Chaudhary } 2931f4f5df23SVikas Chaudhary 2932f4f5df23SVikas Chaudhary memset(sys_info, 0, sizeof(*sys_info)); 2933f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2934f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 2935f4f5df23SVikas Chaudhary 2936f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; 2937f4f5df23SVikas Chaudhary mbox_cmd[1] = LSDW(sys_info_dma); 2938f4f5df23SVikas Chaudhary mbox_cmd[2] = MSDW(sys_info_dma); 2939f4f5df23SVikas Chaudhary mbox_cmd[4] = sizeof(*sys_info); 2940f4f5df23SVikas Chaudhary 2941f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], 2942f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 2943f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", 2944f4f5df23SVikas Chaudhary ha->host_no, __func__)); 2945f4f5df23SVikas Chaudhary goto exit_validate_mac82; 2946f4f5df23SVikas Chaudhary } 2947f4f5df23SVikas Chaudhary 29482ccdf0dcSVikas Chaudhary /* Make sure we receive the minimum required data to cache internally */ 29492ccdf0dcSVikas Chaudhary if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) { 2950f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" 2951f4f5df23SVikas Chaudhary " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); 2952f4f5df23SVikas Chaudhary goto exit_validate_mac82; 2953f4f5df23SVikas Chaudhary 2954f4f5df23SVikas Chaudhary } 2955f4f5df23SVikas Chaudhary 2956f4f5df23SVikas Chaudhary /* Save M.A.C. address & serial_number */ 29572a991c21SManish Rangankar ha->port_num = sys_info->port_num; 2958f4f5df23SVikas Chaudhary memcpy(ha->my_mac, &sys_info->mac_addr[0], 2959f4f5df23SVikas Chaudhary min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); 2960f4f5df23SVikas Chaudhary memcpy(ha->serial_number, &sys_info->serial_number, 2961f4f5df23SVikas Chaudhary min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); 296291ec7cecSVikas Chaudhary memcpy(ha->model_name, &sys_info->board_id_str, 296391ec7cecSVikas Chaudhary min(sizeof(ha->model_name), sizeof(sys_info->board_id_str))); 296491ec7cecSVikas Chaudhary ha->phy_port_cnt = sys_info->phys_port_cnt; 296591ec7cecSVikas Chaudhary ha->phy_port_num = sys_info->port_num; 296691ec7cecSVikas Chaudhary ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt; 2967f4f5df23SVikas Chaudhary 2968f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: " 2969f4f5df23SVikas Chaudhary "mac %02x:%02x:%02x:%02x:%02x:%02x " 2970f4f5df23SVikas Chaudhary "serial %s\n", ha->host_no, __func__, 2971f4f5df23SVikas Chaudhary ha->my_mac[0], ha->my_mac[1], ha->my_mac[2], 2972f4f5df23SVikas Chaudhary ha->my_mac[3], ha->my_mac[4], ha->my_mac[5], 2973f4f5df23SVikas Chaudhary ha->serial_number)); 2974f4f5df23SVikas Chaudhary 2975f4f5df23SVikas Chaudhary status = QLA_SUCCESS; 2976f4f5df23SVikas Chaudhary 2977f4f5df23SVikas Chaudhary exit_validate_mac82: 2978f4f5df23SVikas Chaudhary dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, 2979f4f5df23SVikas Chaudhary sys_info_dma); 2980f4f5df23SVikas Chaudhary return status; 2981f4f5df23SVikas Chaudhary } 2982f4f5df23SVikas Chaudhary 2983f4f5df23SVikas Chaudhary /* Interrupt handling helpers. */ 2984f4f5df23SVikas Chaudhary 2985f4f5df23SVikas Chaudhary static int 2986f4f5df23SVikas Chaudhary qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha) 2987f4f5df23SVikas Chaudhary { 2988f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 2989f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 2990f4f5df23SVikas Chaudhary 2991f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 2992f4f5df23SVikas Chaudhary 2993f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2994f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 2995f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 2996f4f5df23SVikas Chaudhary mbox_cmd[1] = INTR_ENABLE; 2997f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 2998f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 2999f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 3000f4f5df23SVikas Chaudhary "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 3001f4f5df23SVikas Chaudhary __func__, mbox_sts[0])); 3002f4f5df23SVikas Chaudhary return QLA_ERROR; 3003f4f5df23SVikas Chaudhary } 3004f4f5df23SVikas Chaudhary return QLA_SUCCESS; 3005f4f5df23SVikas Chaudhary } 3006f4f5df23SVikas Chaudhary 3007f4f5df23SVikas Chaudhary static int 3008f4f5df23SVikas Chaudhary qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha) 3009f4f5df23SVikas Chaudhary { 3010f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 3011f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 3012f4f5df23SVikas Chaudhary 3013f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 3014f4f5df23SVikas Chaudhary 3015f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 3016f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 3017f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 3018f4f5df23SVikas Chaudhary mbox_cmd[1] = INTR_DISABLE; 3019f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 3020f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 3021f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 3022f4f5df23SVikas Chaudhary "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 3023f4f5df23SVikas Chaudhary __func__, mbox_sts[0])); 3024f4f5df23SVikas Chaudhary return QLA_ERROR; 3025f4f5df23SVikas Chaudhary } 3026f4f5df23SVikas Chaudhary 3027f4f5df23SVikas Chaudhary return QLA_SUCCESS; 3028f4f5df23SVikas Chaudhary } 3029f4f5df23SVikas Chaudhary 3030f4f5df23SVikas Chaudhary void 3031f8086f4fSVikas Chaudhary qla4_82xx_enable_intrs(struct scsi_qla_host *ha) 3032f4f5df23SVikas Chaudhary { 3033f4f5df23SVikas Chaudhary qla4_8xxx_mbx_intr_enable(ha); 3034f4f5df23SVikas Chaudhary 3035f4f5df23SVikas Chaudhary spin_lock_irq(&ha->hardware_lock); 3036f4f5df23SVikas Chaudhary /* BIT 10 - reset */ 3037f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 3038f4f5df23SVikas Chaudhary spin_unlock_irq(&ha->hardware_lock); 3039f4f5df23SVikas Chaudhary set_bit(AF_INTERRUPTS_ON, &ha->flags); 3040f4f5df23SVikas Chaudhary } 3041f4f5df23SVikas Chaudhary 3042f4f5df23SVikas Chaudhary void 3043f8086f4fSVikas Chaudhary qla4_82xx_disable_intrs(struct scsi_qla_host *ha) 3044f4f5df23SVikas Chaudhary { 30455fa8b573SSarang Radke if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) 3046f4f5df23SVikas Chaudhary qla4_8xxx_mbx_intr_disable(ha); 3047f4f5df23SVikas Chaudhary 3048f4f5df23SVikas Chaudhary spin_lock_irq(&ha->hardware_lock); 3049f4f5df23SVikas Chaudhary /* BIT 10 - set */ 3050f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 3051f4f5df23SVikas Chaudhary spin_unlock_irq(&ha->hardware_lock); 3052f4f5df23SVikas Chaudhary } 3053f4f5df23SVikas Chaudhary 3054f4f5df23SVikas Chaudhary struct ql4_init_msix_entry { 3055f4f5df23SVikas Chaudhary uint16_t entry; 3056f4f5df23SVikas Chaudhary uint16_t index; 3057f4f5df23SVikas Chaudhary const char *name; 3058f4f5df23SVikas Chaudhary irq_handler_t handler; 3059f4f5df23SVikas Chaudhary }; 3060f4f5df23SVikas Chaudhary 3061f4f5df23SVikas Chaudhary static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = { 3062f4f5df23SVikas Chaudhary { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT, 3063f4f5df23SVikas Chaudhary "qla4xxx (default)", 3064f4f5df23SVikas Chaudhary (irq_handler_t)qla4_8xxx_default_intr_handler }, 3065f4f5df23SVikas Chaudhary { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q, 3066f4f5df23SVikas Chaudhary "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q }, 3067f4f5df23SVikas Chaudhary }; 3068f4f5df23SVikas Chaudhary 3069f4f5df23SVikas Chaudhary void 3070f4f5df23SVikas Chaudhary qla4_8xxx_disable_msix(struct scsi_qla_host *ha) 3071f4f5df23SVikas Chaudhary { 3072f4f5df23SVikas Chaudhary int i; 3073f4f5df23SVikas Chaudhary struct ql4_msix_entry *qentry; 3074f4f5df23SVikas Chaudhary 3075f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 3076f4f5df23SVikas Chaudhary qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 3077f4f5df23SVikas Chaudhary if (qentry->have_irq) { 3078f4f5df23SVikas Chaudhary free_irq(qentry->msix_vector, ha); 3079f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 3080f4f5df23SVikas Chaudhary __func__, qla4_8xxx_msix_entries[i].name)); 3081f4f5df23SVikas Chaudhary } 3082f4f5df23SVikas Chaudhary } 3083f4f5df23SVikas Chaudhary pci_disable_msix(ha->pdev); 3084f4f5df23SVikas Chaudhary clear_bit(AF_MSIX_ENABLED, &ha->flags); 3085f4f5df23SVikas Chaudhary } 3086f4f5df23SVikas Chaudhary 3087f4f5df23SVikas Chaudhary int 3088f4f5df23SVikas Chaudhary qla4_8xxx_enable_msix(struct scsi_qla_host *ha) 3089f4f5df23SVikas Chaudhary { 3090f4f5df23SVikas Chaudhary int i, ret; 3091f4f5df23SVikas Chaudhary struct msix_entry entries[QLA_MSIX_ENTRIES]; 3092f4f5df23SVikas Chaudhary struct ql4_msix_entry *qentry; 3093f4f5df23SVikas Chaudhary 3094f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) 3095f4f5df23SVikas Chaudhary entries[i].entry = qla4_8xxx_msix_entries[i].entry; 3096f4f5df23SVikas Chaudhary 3097f4f5df23SVikas Chaudhary ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries)); 3098f4f5df23SVikas Chaudhary if (ret) { 3099f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 3100f4f5df23SVikas Chaudhary "MSI-X: Failed to enable support -- %d/%d\n", 3101f4f5df23SVikas Chaudhary QLA_MSIX_ENTRIES, ret); 3102f4f5df23SVikas Chaudhary goto msix_out; 3103f4f5df23SVikas Chaudhary } 3104f4f5df23SVikas Chaudhary set_bit(AF_MSIX_ENABLED, &ha->flags); 3105f4f5df23SVikas Chaudhary 3106f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 3107f4f5df23SVikas Chaudhary qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 3108f4f5df23SVikas Chaudhary qentry->msix_vector = entries[i].vector; 3109f4f5df23SVikas Chaudhary qentry->msix_entry = entries[i].entry; 3110f4f5df23SVikas Chaudhary qentry->have_irq = 0; 3111f4f5df23SVikas Chaudhary ret = request_irq(qentry->msix_vector, 3112f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].handler, 0, 3113f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].name, ha); 3114f4f5df23SVikas Chaudhary if (ret) { 3115f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 3116f4f5df23SVikas Chaudhary "MSI-X: Unable to register handler -- %x/%d.\n", 3117f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].index, ret); 3118f4f5df23SVikas Chaudhary qla4_8xxx_disable_msix(ha); 3119f4f5df23SVikas Chaudhary goto msix_out; 3120f4f5df23SVikas Chaudhary } 3121f4f5df23SVikas Chaudhary qentry->have_irq = 1; 3122f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 3123f4f5df23SVikas Chaudhary __func__, qla4_8xxx_msix_entries[i].name)); 3124f4f5df23SVikas Chaudhary } 3125f4f5df23SVikas Chaudhary msix_out: 3126f4f5df23SVikas Chaudhary return ret; 3127f4f5df23SVikas Chaudhary } 3128