1f4f5df23SVikas Chaudhary /* 2f4f5df23SVikas Chaudhary * QLogic iSCSI HBA Driver 34a4f51e9SVikas Chaudhary * Copyright (c) 2003-2013 QLogic Corporation 4f4f5df23SVikas Chaudhary * 5f4f5df23SVikas Chaudhary * See LICENSE.qla4xxx for copyright and licensing details. 6f4f5df23SVikas Chaudhary */ 7f4f5df23SVikas Chaudhary #include <linux/delay.h> 8a6751ccbSJiri Slaby #include <linux/io.h> 9f4f5df23SVikas Chaudhary #include <linux/pci.h> 10068237c8STej Parkash #include <linux/ratelimit.h> 11f4f5df23SVikas Chaudhary #include "ql4_def.h" 12f4f5df23SVikas Chaudhary #include "ql4_glbl.h" 136e7b4292SVikas Chaudhary #include "ql4_inline.h" 14f4f5df23SVikas Chaudhary 15797a796aSHitoshi Mitake #include <asm-generic/io-64-nonatomic-lo-hi.h> 16797a796aSHitoshi Mitake 17f4f5df23SVikas Chaudhary #define MASK(n) DMA_BIT_MASK(n) 18f4f5df23SVikas Chaudhary #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 19f4f5df23SVikas Chaudhary #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 20f4f5df23SVikas Chaudhary #define MS_WIN(addr) (addr & 0x0ffc0000) 21f4f5df23SVikas Chaudhary #define QLA82XX_PCI_MN_2M (0) 22f4f5df23SVikas Chaudhary #define QLA82XX_PCI_MS_2M (0x80000) 23f4f5df23SVikas Chaudhary #define QLA82XX_PCI_OCM0_2M (0xc0000) 24f4f5df23SVikas Chaudhary #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 25f4f5df23SVikas Chaudhary #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 26f4f5df23SVikas Chaudhary 27f4f5df23SVikas Chaudhary /* CRB window related */ 28f4f5df23SVikas Chaudhary #define CRB_BLK(off) ((off >> 20) & 0x3f) 29f4f5df23SVikas Chaudhary #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30f4f5df23SVikas Chaudhary #define CRB_WINDOW_2M (0x130060) 317664a1fdSVikas Chaudhary #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 32f4f5df23SVikas Chaudhary ((off) & 0xf0000)) 33f4f5df23SVikas Chaudhary #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 34f4f5df23SVikas Chaudhary #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35f4f5df23SVikas Chaudhary #define CRB_INDIRECT_2M (0x1e0000UL) 36f4f5df23SVikas Chaudhary 37f4f5df23SVikas Chaudhary static inline void __iomem * 38f4f5df23SVikas Chaudhary qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) 39f4f5df23SVikas Chaudhary { 40f4f5df23SVikas Chaudhary if ((off < ha->first_page_group_end) && 41f4f5df23SVikas Chaudhary (off >= ha->first_page_group_start)) 42f4f5df23SVikas Chaudhary return (void __iomem *)(ha->nx_pcibase + off); 43f4f5df23SVikas Chaudhary 44f4f5df23SVikas Chaudhary return NULL; 45f4f5df23SVikas Chaudhary } 46f4f5df23SVikas Chaudhary 47f4f5df23SVikas Chaudhary #define MAX_CRB_XFORM 60 48f4f5df23SVikas Chaudhary static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 49f4f5df23SVikas Chaudhary static int qla4_8xxx_crb_table_initialized; 50f4f5df23SVikas Chaudhary 51f4f5df23SVikas Chaudhary #define qla4_8xxx_crb_addr_transform(name) \ 52f4f5df23SVikas Chaudhary (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 53f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 54f4f5df23SVikas Chaudhary static void 55f8086f4fSVikas Chaudhary qla4_82xx_crb_addr_transform_setup(void) 56f4f5df23SVikas Chaudhary { 57f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(XDMA); 58f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(TIMR); 59f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SRE); 60f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN3); 61f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN2); 62f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN1); 63f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN0); 64f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS3); 65f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS2); 66f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS1); 67f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS0); 68f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX7); 69f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX6); 70f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX5); 71f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX4); 72f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX3); 73f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX2); 74f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX1); 75f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX0); 76f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(ROMUSB); 77f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SN); 78f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(QMN); 79f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(QMS); 80f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGNI); 81f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGND); 82f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN3); 83f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN2); 84f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN1); 85f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN0); 86f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGSI); 87f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGSD); 88f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS3); 89f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS2); 90f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS1); 91f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS0); 92f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PS); 93f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PH); 94f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(NIU); 95f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(I2Q); 96f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(EG); 97f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(MN); 98f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(MS); 99f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS2); 100f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS1); 101f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS0); 102f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAM); 103f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(C2C1); 104f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(C2C0); 105f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SMB); 106f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(OCM0); 107f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(I2C0); 108f4f5df23SVikas Chaudhary 109f4f5df23SVikas Chaudhary qla4_8xxx_crb_table_initialized = 1; 110f4f5df23SVikas Chaudhary } 111f4f5df23SVikas Chaudhary 112f4f5df23SVikas Chaudhary static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 113f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 0: PCI */ 114f4f5df23SVikas Chaudhary {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 115f4f5df23SVikas Chaudhary {1, 0x0110000, 0x0120000, 0x130000}, 116f4f5df23SVikas Chaudhary {1, 0x0120000, 0x0122000, 0x124000}, 117f4f5df23SVikas Chaudhary {1, 0x0130000, 0x0132000, 0x126000}, 118f4f5df23SVikas Chaudhary {1, 0x0140000, 0x0142000, 0x128000}, 119f4f5df23SVikas Chaudhary {1, 0x0150000, 0x0152000, 0x12a000}, 120f4f5df23SVikas Chaudhary {1, 0x0160000, 0x0170000, 0x110000}, 121f4f5df23SVikas Chaudhary {1, 0x0170000, 0x0172000, 0x12e000}, 122f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 123f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 124f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 125f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 126f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 127f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 128f4f5df23SVikas Chaudhary {1, 0x01e0000, 0x01e0800, 0x122000}, 129f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000} } }, 130f4f5df23SVikas Chaudhary {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 131f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 3: */ 132f4f5df23SVikas Chaudhary {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 133f4f5df23SVikas Chaudhary {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 134f4f5df23SVikas Chaudhary {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 135f4f5df23SVikas Chaudhary {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 136f4f5df23SVikas Chaudhary {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 137f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 138f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 139f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 140f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 141f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 142f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 143f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 144f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 145f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 146f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 147f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 148f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 149f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 150f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 151f4f5df23SVikas Chaudhary {1, 0x08f0000, 0x08f2000, 0x172000} } }, 152f4f5df23SVikas Chaudhary {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 153f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 154f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 155f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 156f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 157f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 158f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 159f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 160f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 161f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 162f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 163f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 164f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 165f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 166f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 167f4f5df23SVikas Chaudhary {1, 0x09f0000, 0x09f2000, 0x176000} } }, 168f4f5df23SVikas Chaudhary {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 169f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 170f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 171f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 172f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 173f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 174f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 175f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 176f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 177f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 178f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 179f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 180f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 181f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 182f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 183f4f5df23SVikas Chaudhary {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 184f4f5df23SVikas Chaudhary {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 185f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 186f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 187f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 188f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 189f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 190f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 191f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 192f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 193f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 194f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 195f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 196f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 197f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 198f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 199f4f5df23SVikas Chaudhary {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 200f4f5df23SVikas Chaudhary {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 201f4f5df23SVikas Chaudhary {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 202f4f5df23SVikas Chaudhary {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 203f4f5df23SVikas Chaudhary {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 204f4f5df23SVikas Chaudhary {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 205f4f5df23SVikas Chaudhary {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 206f4f5df23SVikas Chaudhary {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 207f4f5df23SVikas Chaudhary {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 208f4f5df23SVikas Chaudhary {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 209f4f5df23SVikas Chaudhary {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 210f4f5df23SVikas Chaudhary {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 211f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 23: */ 212f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 24: */ 213f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 25: */ 214f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 26: */ 215f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 27: */ 216f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 28: */ 217f4f5df23SVikas Chaudhary {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 218f4f5df23SVikas Chaudhary {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 219f4f5df23SVikas Chaudhary {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 220f4f5df23SVikas Chaudhary {{{0} } }, /* 32: PCI */ 221f4f5df23SVikas Chaudhary {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 222f4f5df23SVikas Chaudhary {1, 0x2110000, 0x2120000, 0x130000}, 223f4f5df23SVikas Chaudhary {1, 0x2120000, 0x2122000, 0x124000}, 224f4f5df23SVikas Chaudhary {1, 0x2130000, 0x2132000, 0x126000}, 225f4f5df23SVikas Chaudhary {1, 0x2140000, 0x2142000, 0x128000}, 226f4f5df23SVikas Chaudhary {1, 0x2150000, 0x2152000, 0x12a000}, 227f4f5df23SVikas Chaudhary {1, 0x2160000, 0x2170000, 0x110000}, 228f4f5df23SVikas Chaudhary {1, 0x2170000, 0x2172000, 0x12e000}, 229f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 230f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 231f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 232f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 233f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 234f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 235f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 236f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000} } }, 237f4f5df23SVikas Chaudhary {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 238f4f5df23SVikas Chaudhary {{{0} } }, /* 35: */ 239f4f5df23SVikas Chaudhary {{{0} } }, /* 36: */ 240f4f5df23SVikas Chaudhary {{{0} } }, /* 37: */ 241f4f5df23SVikas Chaudhary {{{0} } }, /* 38: */ 242f4f5df23SVikas Chaudhary {{{0} } }, /* 39: */ 243f4f5df23SVikas Chaudhary {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 244f4f5df23SVikas Chaudhary {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 245f4f5df23SVikas Chaudhary {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 246f4f5df23SVikas Chaudhary {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 247f4f5df23SVikas Chaudhary {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 248f4f5df23SVikas Chaudhary {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 249f4f5df23SVikas Chaudhary {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 250f4f5df23SVikas Chaudhary {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 251f4f5df23SVikas Chaudhary {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 252f4f5df23SVikas Chaudhary {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 253f4f5df23SVikas Chaudhary {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 254f4f5df23SVikas Chaudhary {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 255f4f5df23SVikas Chaudhary {{{0} } }, /* 52: */ 256f4f5df23SVikas Chaudhary {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 257f4f5df23SVikas Chaudhary {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 258f4f5df23SVikas Chaudhary {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 259f4f5df23SVikas Chaudhary {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 260f4f5df23SVikas Chaudhary {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 261f4f5df23SVikas Chaudhary {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 262f4f5df23SVikas Chaudhary {{{0} } }, /* 59: I2C0 */ 263f4f5df23SVikas Chaudhary {{{0} } }, /* 60: I2C1 */ 264f4f5df23SVikas Chaudhary {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ 265f4f5df23SVikas Chaudhary {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 266f4f5df23SVikas Chaudhary {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 267f4f5df23SVikas Chaudhary }; 268f4f5df23SVikas Chaudhary 269f4f5df23SVikas Chaudhary /* 270f4f5df23SVikas Chaudhary * top 12 bits of crb internal address (hub, agent) 271f4f5df23SVikas Chaudhary */ 2727664a1fdSVikas Chaudhary static unsigned qla4_82xx_crb_hub_agt[64] = { 273f4f5df23SVikas Chaudhary 0, 274f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 275f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 276f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 277f4f5df23SVikas Chaudhary 0, 278f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 279f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 280f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 281f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 282f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 283f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 284f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 285f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 286f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 287f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 288f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 289f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 290f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 291f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 292f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 293f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 294f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 295f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 296f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 297f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 298f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 299f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 300f4f5df23SVikas Chaudhary 0, 301f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 302f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 303f4f5df23SVikas Chaudhary 0, 304f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 305f4f5df23SVikas Chaudhary 0, 306f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 307f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 308f4f5df23SVikas Chaudhary 0, 309f4f5df23SVikas Chaudhary 0, 310f4f5df23SVikas Chaudhary 0, 311f4f5df23SVikas Chaudhary 0, 312f4f5df23SVikas Chaudhary 0, 313f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 314f4f5df23SVikas Chaudhary 0, 315f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 316f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 317f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 318f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 319f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 320f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 321f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 322f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 323f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 324f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 325f4f5df23SVikas Chaudhary 0, 326f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 327f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 328f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 329f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 330f4f5df23SVikas Chaudhary 0, 331f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 332f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 333f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 334f4f5df23SVikas Chaudhary 0, 335f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 336f4f5df23SVikas Chaudhary 0, 337f4f5df23SVikas Chaudhary }; 338f4f5df23SVikas Chaudhary 339f4f5df23SVikas Chaudhary /* Device states */ 340f4f5df23SVikas Chaudhary static char *qdev_state[] = { 341f4f5df23SVikas Chaudhary "Unknown", 342f4f5df23SVikas Chaudhary "Cold", 343f4f5df23SVikas Chaudhary "Initializing", 344f4f5df23SVikas Chaudhary "Ready", 345f4f5df23SVikas Chaudhary "Need Reset", 346f4f5df23SVikas Chaudhary "Need Quiescent", 347f4f5df23SVikas Chaudhary "Failed", 348f4f5df23SVikas Chaudhary "Quiescent", 349f4f5df23SVikas Chaudhary }; 350f4f5df23SVikas Chaudhary 351f4f5df23SVikas Chaudhary /* 352f4f5df23SVikas Chaudhary * In: 'off' is offset from CRB space in 128M pci map 353f4f5df23SVikas Chaudhary * Out: 'off' is 2M pci map addr 354f4f5df23SVikas Chaudhary * side effect: lock crb window 355f4f5df23SVikas Chaudhary */ 356f4f5df23SVikas Chaudhary static void 357f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) 358f4f5df23SVikas Chaudhary { 359f4f5df23SVikas Chaudhary u32 win_read; 360f4f5df23SVikas Chaudhary 361f4f5df23SVikas Chaudhary ha->crb_win = CRB_HI(*off); 362f4f5df23SVikas Chaudhary writel(ha->crb_win, 363f4f5df23SVikas Chaudhary (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 364f4f5df23SVikas Chaudhary 365f4f5df23SVikas Chaudhary /* Read back value to make sure write has gone through before trying 366f4f5df23SVikas Chaudhary * to use it. */ 367f4f5df23SVikas Chaudhary win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 368f4f5df23SVikas Chaudhary if (win_read != ha->crb_win) { 369f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 370f4f5df23SVikas Chaudhary "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," 371f4f5df23SVikas Chaudhary " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 372f4f5df23SVikas Chaudhary } 373f4f5df23SVikas Chaudhary *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 374f4f5df23SVikas Chaudhary } 375f4f5df23SVikas Chaudhary 376f4f5df23SVikas Chaudhary void 377f8086f4fSVikas Chaudhary qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) 378f4f5df23SVikas Chaudhary { 379f4f5df23SVikas Chaudhary unsigned long flags = 0; 380f4f5df23SVikas Chaudhary int rv; 381f4f5df23SVikas Chaudhary 382f8086f4fSVikas Chaudhary rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); 383f4f5df23SVikas Chaudhary 384f4f5df23SVikas Chaudhary BUG_ON(rv == -1); 385f4f5df23SVikas Chaudhary 386f4f5df23SVikas Chaudhary if (rv == 1) { 387f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 388f8086f4fSVikas Chaudhary qla4_82xx_crb_win_lock(ha); 389f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(ha, &off); 390f4f5df23SVikas Chaudhary } 391f4f5df23SVikas Chaudhary 392f4f5df23SVikas Chaudhary writel(data, (void __iomem *)off); 393f4f5df23SVikas Chaudhary 394f4f5df23SVikas Chaudhary if (rv == 1) { 395f8086f4fSVikas Chaudhary qla4_82xx_crb_win_unlock(ha); 396f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 397f4f5df23SVikas Chaudhary } 398f4f5df23SVikas Chaudhary } 399f4f5df23SVikas Chaudhary 40033693c7aSVikas Chaudhary uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off) 401f4f5df23SVikas Chaudhary { 402f4f5df23SVikas Chaudhary unsigned long flags = 0; 403f4f5df23SVikas Chaudhary int rv; 404f4f5df23SVikas Chaudhary u32 data; 405f4f5df23SVikas Chaudhary 406f8086f4fSVikas Chaudhary rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); 407f4f5df23SVikas Chaudhary 408f4f5df23SVikas Chaudhary BUG_ON(rv == -1); 409f4f5df23SVikas Chaudhary 410f4f5df23SVikas Chaudhary if (rv == 1) { 411f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 412f8086f4fSVikas Chaudhary qla4_82xx_crb_win_lock(ha); 413f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(ha, &off); 414f4f5df23SVikas Chaudhary } 415f4f5df23SVikas Chaudhary data = readl((void __iomem *)off); 416f4f5df23SVikas Chaudhary 417f4f5df23SVikas Chaudhary if (rv == 1) { 418f8086f4fSVikas Chaudhary qla4_82xx_crb_win_unlock(ha); 419f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 420f4f5df23SVikas Chaudhary } 421f4f5df23SVikas Chaudhary return data; 422f4f5df23SVikas Chaudhary } 423f4f5df23SVikas Chaudhary 424068237c8STej Parkash /* Minidump related functions */ 42533693c7aSVikas Chaudhary int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data) 426068237c8STej Parkash { 42733693c7aSVikas Chaudhary uint32_t win_read, off_value; 42833693c7aSVikas Chaudhary int rval = QLA_SUCCESS; 42933693c7aSVikas Chaudhary 43033693c7aSVikas Chaudhary off_value = off & 0xFFFF0000; 43133693c7aSVikas Chaudhary writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 43233693c7aSVikas Chaudhary 43333693c7aSVikas Chaudhary /* 43433693c7aSVikas Chaudhary * Read back value to make sure write has gone through before trying 43533693c7aSVikas Chaudhary * to use it. 43633693c7aSVikas Chaudhary */ 43733693c7aSVikas Chaudhary win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 43833693c7aSVikas Chaudhary if (win_read != off_value) { 43933693c7aSVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 44033693c7aSVikas Chaudhary "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 44133693c7aSVikas Chaudhary __func__, off_value, win_read, off)); 44233693c7aSVikas Chaudhary rval = QLA_ERROR; 44333693c7aSVikas Chaudhary } else { 44433693c7aSVikas Chaudhary off_value = off & 0x0000FFFF; 44533693c7aSVikas Chaudhary *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M + 44633693c7aSVikas Chaudhary ha->nx_pcibase)); 44733693c7aSVikas Chaudhary } 44833693c7aSVikas Chaudhary return rval; 44933693c7aSVikas Chaudhary } 45033693c7aSVikas Chaudhary 45133693c7aSVikas Chaudhary int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data) 45233693c7aSVikas Chaudhary { 45333693c7aSVikas Chaudhary uint32_t win_read, off_value; 45433693c7aSVikas Chaudhary int rval = QLA_SUCCESS; 455068237c8STej Parkash 456068237c8STej Parkash off_value = off & 0xFFFF0000; 457068237c8STej Parkash writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 458068237c8STej Parkash 459068237c8STej Parkash /* Read back value to make sure write has gone through before trying 460068237c8STej Parkash * to use it. 461068237c8STej Parkash */ 462068237c8STej Parkash win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 463068237c8STej Parkash if (win_read != off_value) { 464068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 465068237c8STej Parkash "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 466068237c8STej Parkash __func__, off_value, win_read, off)); 46733693c7aSVikas Chaudhary rval = QLA_ERROR; 46833693c7aSVikas Chaudhary } else { 469068237c8STej Parkash off_value = off & 0x0000FFFF; 470068237c8STej Parkash writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M + 471068237c8STej Parkash ha->nx_pcibase)); 47233693c7aSVikas Chaudhary } 473068237c8STej Parkash return rval; 474068237c8STej Parkash } 475068237c8STej Parkash 476f4f5df23SVikas Chaudhary #define CRB_WIN_LOCK_TIMEOUT 100000000 477f4f5df23SVikas Chaudhary 478f8086f4fSVikas Chaudhary int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha) 479f4f5df23SVikas Chaudhary { 480f4f5df23SVikas Chaudhary int i; 481f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 482f4f5df23SVikas Chaudhary 483f4f5df23SVikas Chaudhary while (!done) { 484f4f5df23SVikas Chaudhary /* acquire semaphore3 from PCI HW block */ 485f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 486f4f5df23SVikas Chaudhary if (done == 1) 487f4f5df23SVikas Chaudhary break; 488f4f5df23SVikas Chaudhary if (timeout >= CRB_WIN_LOCK_TIMEOUT) 489f4f5df23SVikas Chaudhary return -1; 490f4f5df23SVikas Chaudhary 491f4f5df23SVikas Chaudhary timeout++; 492f4f5df23SVikas Chaudhary 493f4f5df23SVikas Chaudhary /* Yield CPU */ 494f4f5df23SVikas Chaudhary if (!in_interrupt()) 495f4f5df23SVikas Chaudhary schedule(); 496f4f5df23SVikas Chaudhary else { 497f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 498f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 499f4f5df23SVikas Chaudhary } 500f4f5df23SVikas Chaudhary } 501f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); 502f4f5df23SVikas Chaudhary return 0; 503f4f5df23SVikas Chaudhary } 504f4f5df23SVikas Chaudhary 505f8086f4fSVikas Chaudhary void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha) 506f4f5df23SVikas Chaudhary { 507f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 508f4f5df23SVikas Chaudhary } 509f4f5df23SVikas Chaudhary 510f4f5df23SVikas Chaudhary #define IDC_LOCK_TIMEOUT 100000000 511f4f5df23SVikas Chaudhary 512f4f5df23SVikas Chaudhary /** 513f8086f4fSVikas Chaudhary * qla4_82xx_idc_lock - hw_lock 514f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 515f4f5df23SVikas Chaudhary * 516f4f5df23SVikas Chaudhary * General purpose lock used to synchronize access to 517f4f5df23SVikas Chaudhary * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. 518f4f5df23SVikas Chaudhary **/ 519f8086f4fSVikas Chaudhary int qla4_82xx_idc_lock(struct scsi_qla_host *ha) 520f4f5df23SVikas Chaudhary { 521f4f5df23SVikas Chaudhary int i; 522f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 523f4f5df23SVikas Chaudhary 524f4f5df23SVikas Chaudhary while (!done) { 525f4f5df23SVikas Chaudhary /* acquire semaphore5 from PCI HW block */ 526f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 527f4f5df23SVikas Chaudhary if (done == 1) 528f4f5df23SVikas Chaudhary break; 529f4f5df23SVikas Chaudhary if (timeout >= IDC_LOCK_TIMEOUT) 530f4f5df23SVikas Chaudhary return -1; 531f4f5df23SVikas Chaudhary 532f4f5df23SVikas Chaudhary timeout++; 533f4f5df23SVikas Chaudhary 534f4f5df23SVikas Chaudhary /* Yield CPU */ 535f4f5df23SVikas Chaudhary if (!in_interrupt()) 536f4f5df23SVikas Chaudhary schedule(); 537f4f5df23SVikas Chaudhary else { 538f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 539f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 540f4f5df23SVikas Chaudhary } 541f4f5df23SVikas Chaudhary } 542f4f5df23SVikas Chaudhary return 0; 543f4f5df23SVikas Chaudhary } 544f4f5df23SVikas Chaudhary 545f8086f4fSVikas Chaudhary void qla4_82xx_idc_unlock(struct scsi_qla_host *ha) 546f4f5df23SVikas Chaudhary { 547f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 548f4f5df23SVikas Chaudhary } 549f4f5df23SVikas Chaudhary 550f4f5df23SVikas Chaudhary int 551f8086f4fSVikas Chaudhary qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) 552f4f5df23SVikas Chaudhary { 553f4f5df23SVikas Chaudhary struct crb_128M_2M_sub_block_map *m; 554f4f5df23SVikas Chaudhary 555f4f5df23SVikas Chaudhary if (*off >= QLA82XX_CRB_MAX) 556f4f5df23SVikas Chaudhary return -1; 557f4f5df23SVikas Chaudhary 558f4f5df23SVikas Chaudhary if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 559f4f5df23SVikas Chaudhary *off = (*off - QLA82XX_PCI_CAMQM) + 560f4f5df23SVikas Chaudhary QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 561f4f5df23SVikas Chaudhary return 0; 562f4f5df23SVikas Chaudhary } 563f4f5df23SVikas Chaudhary 564f4f5df23SVikas Chaudhary if (*off < QLA82XX_PCI_CRBSPACE) 565f4f5df23SVikas Chaudhary return -1; 566f4f5df23SVikas Chaudhary 567f4f5df23SVikas Chaudhary *off -= QLA82XX_PCI_CRBSPACE; 568f4f5df23SVikas Chaudhary /* 569f4f5df23SVikas Chaudhary * Try direct map 570f4f5df23SVikas Chaudhary */ 571f4f5df23SVikas Chaudhary 572f4f5df23SVikas Chaudhary m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 573f4f5df23SVikas Chaudhary 574f4f5df23SVikas Chaudhary if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 575f4f5df23SVikas Chaudhary *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 576f4f5df23SVikas Chaudhary return 0; 577f4f5df23SVikas Chaudhary } 578f4f5df23SVikas Chaudhary 579f4f5df23SVikas Chaudhary /* 580f4f5df23SVikas Chaudhary * Not in direct map, use crb window 581f4f5df23SVikas Chaudhary */ 582f4f5df23SVikas Chaudhary return 1; 583f4f5df23SVikas Chaudhary } 584f4f5df23SVikas Chaudhary 585f4f5df23SVikas Chaudhary /* 586f4f5df23SVikas Chaudhary * check memory access boundary. 587f4f5df23SVikas Chaudhary * used by test agent. support ddr access only for now 588f4f5df23SVikas Chaudhary */ 589f4f5df23SVikas Chaudhary static unsigned long 590f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha, 591f4f5df23SVikas Chaudhary unsigned long long addr, int size) 592f4f5df23SVikas Chaudhary { 593de8c72daSVikas Chaudhary if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 594de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX) || 595de8c72daSVikas Chaudhary !QLA8XXX_ADDR_IN_RANGE(addr + size - 1, 596de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) || 597f4f5df23SVikas Chaudhary ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { 598f4f5df23SVikas Chaudhary return 0; 599f4f5df23SVikas Chaudhary } 600f4f5df23SVikas Chaudhary return 1; 601f4f5df23SVikas Chaudhary } 602f4f5df23SVikas Chaudhary 6037664a1fdSVikas Chaudhary static int qla4_82xx_pci_set_window_warning_count; 604f4f5df23SVikas Chaudhary 605f4f5df23SVikas Chaudhary static unsigned long 606f8086f4fSVikas Chaudhary qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) 607f4f5df23SVikas Chaudhary { 608f4f5df23SVikas Chaudhary int window; 609f4f5df23SVikas Chaudhary u32 win_read; 610f4f5df23SVikas Chaudhary 611de8c72daSVikas Chaudhary if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 612de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX)) { 613f4f5df23SVikas Chaudhary /* DDR network side */ 614f4f5df23SVikas Chaudhary window = MN_WIN(addr); 615f4f5df23SVikas Chaudhary ha->ddr_mn_window = window; 616f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->mn_win_crb | 617f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 618f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | 619f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE); 620f4f5df23SVikas Chaudhary if ((win_read << 17) != window) { 621f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 622f4f5df23SVikas Chaudhary "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 623f4f5df23SVikas Chaudhary __func__, window, win_read); 624f4f5df23SVikas Chaudhary } 625f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 626de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, 627de8c72daSVikas Chaudhary QLA8XXX_ADDR_OCM0_MAX)) { 628f4f5df23SVikas Chaudhary unsigned int temp1; 629f4f5df23SVikas Chaudhary /* if bits 19:18&17:11 are on */ 630f4f5df23SVikas Chaudhary if ((addr & 0x00ff800) == 0xff800) { 631f4f5df23SVikas Chaudhary printk("%s: QM access not handled.\n", __func__); 632f4f5df23SVikas Chaudhary addr = -1UL; 633f4f5df23SVikas Chaudhary } 634f4f5df23SVikas Chaudhary 635f4f5df23SVikas Chaudhary window = OCM_WIN(addr); 636f4f5df23SVikas Chaudhary ha->ddr_mn_window = window; 637f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->mn_win_crb | 638f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 639f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | 640f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE); 641f4f5df23SVikas Chaudhary temp1 = ((window & 0x1FF) << 7) | 642f4f5df23SVikas Chaudhary ((window & 0x0FFFE0000) >> 17); 643f4f5df23SVikas Chaudhary if (win_read != temp1) { 644f4f5df23SVikas Chaudhary printk("%s: Written OCMwin (0x%x) != Read" 645f4f5df23SVikas Chaudhary " OCMwin (0x%x)\n", __func__, temp1, win_read); 646f4f5df23SVikas Chaudhary } 647f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 648f4f5df23SVikas Chaudhary 649de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 650f4f5df23SVikas Chaudhary QLA82XX_P3_ADDR_QDR_NET_MAX)) { 651f4f5df23SVikas Chaudhary /* QDR network side */ 652f4f5df23SVikas Chaudhary window = MS_WIN(addr); 653f4f5df23SVikas Chaudhary ha->qdr_sn_window = window; 654f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->ms_win_crb | 655f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 656f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, 657f4f5df23SVikas Chaudhary ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 658f4f5df23SVikas Chaudhary if (win_read != window) { 659f4f5df23SVikas Chaudhary printk("%s: Written MSwin (0x%x) != Read " 660f4f5df23SVikas Chaudhary "MSwin (0x%x)\n", __func__, window, win_read); 661f4f5df23SVikas Chaudhary } 662f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 663f4f5df23SVikas Chaudhary 664f4f5df23SVikas Chaudhary } else { 665f4f5df23SVikas Chaudhary /* 666f4f5df23SVikas Chaudhary * peg gdb frequently accesses memory that doesn't exist, 667f4f5df23SVikas Chaudhary * this limits the chit chat so debugging isn't slowed down. 668f4f5df23SVikas Chaudhary */ 6697664a1fdSVikas Chaudhary if ((qla4_82xx_pci_set_window_warning_count++ < 8) || 6707664a1fdSVikas Chaudhary (qla4_82xx_pci_set_window_warning_count%64 == 0)) { 671f4f5df23SVikas Chaudhary printk("%s: Warning:%s Unknown address range!\n", 672f4f5df23SVikas Chaudhary __func__, DRIVER_NAME); 673f4f5df23SVikas Chaudhary } 674f4f5df23SVikas Chaudhary addr = -1UL; 675f4f5df23SVikas Chaudhary } 676f4f5df23SVikas Chaudhary return addr; 677f4f5df23SVikas Chaudhary } 678f4f5df23SVikas Chaudhary 679f4f5df23SVikas Chaudhary /* check if address is in the same windows as the previous access */ 680f8086f4fSVikas Chaudhary static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha, 681f4f5df23SVikas Chaudhary unsigned long long addr) 682f4f5df23SVikas Chaudhary { 683f4f5df23SVikas Chaudhary int window; 684f4f5df23SVikas Chaudhary unsigned long long qdr_max; 685f4f5df23SVikas Chaudhary 686f4f5df23SVikas Chaudhary qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 687f4f5df23SVikas Chaudhary 688de8c72daSVikas Chaudhary if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 689de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX)) { 690f4f5df23SVikas Chaudhary /* DDR network side */ 691f4f5df23SVikas Chaudhary BUG(); /* MN access can not come here */ 692de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, 693de8c72daSVikas Chaudhary QLA8XXX_ADDR_OCM0_MAX)) { 694f4f5df23SVikas Chaudhary return 1; 695de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1, 696de8c72daSVikas Chaudhary QLA8XXX_ADDR_OCM1_MAX)) { 697f4f5df23SVikas Chaudhary return 1; 698de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 699f4f5df23SVikas Chaudhary qdr_max)) { 700f4f5df23SVikas Chaudhary /* QDR network side */ 701de8c72daSVikas Chaudhary window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f; 702f4f5df23SVikas Chaudhary if (ha->qdr_sn_window == window) 703f4f5df23SVikas Chaudhary return 1; 704f4f5df23SVikas Chaudhary } 705f4f5df23SVikas Chaudhary 706f4f5df23SVikas Chaudhary return 0; 707f4f5df23SVikas Chaudhary } 708f4f5df23SVikas Chaudhary 709f8086f4fSVikas Chaudhary static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha, 710f4f5df23SVikas Chaudhary u64 off, void *data, int size) 711f4f5df23SVikas Chaudhary { 712f4f5df23SVikas Chaudhary unsigned long flags; 713f4f5df23SVikas Chaudhary void __iomem *addr; 714f4f5df23SVikas Chaudhary int ret = 0; 715f4f5df23SVikas Chaudhary u64 start; 716f4f5df23SVikas Chaudhary void __iomem *mem_ptr = NULL; 717f4f5df23SVikas Chaudhary unsigned long mem_base; 718f4f5df23SVikas Chaudhary unsigned long mem_page; 719f4f5df23SVikas Chaudhary 720f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 721f4f5df23SVikas Chaudhary 722f4f5df23SVikas Chaudhary /* 723f4f5df23SVikas Chaudhary * If attempting to access unknown address or straddle hw windows, 724f4f5df23SVikas Chaudhary * do not access. 725f4f5df23SVikas Chaudhary */ 726f8086f4fSVikas Chaudhary start = qla4_82xx_pci_set_window(ha, off); 727f4f5df23SVikas Chaudhary if ((start == -1UL) || 728f8086f4fSVikas Chaudhary (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 729f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 730f4f5df23SVikas Chaudhary printk(KERN_ERR"%s out of bound pci memory access. " 731f4f5df23SVikas Chaudhary "offset is 0x%llx\n", DRIVER_NAME, off); 732f4f5df23SVikas Chaudhary return -1; 733f4f5df23SVikas Chaudhary } 734f4f5df23SVikas Chaudhary 735f4f5df23SVikas Chaudhary addr = qla4_8xxx_pci_base_offsetfset(ha, start); 736f4f5df23SVikas Chaudhary if (!addr) { 737f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 738f4f5df23SVikas Chaudhary mem_base = pci_resource_start(ha->pdev, 0); 739f4f5df23SVikas Chaudhary mem_page = start & PAGE_MASK; 740f4f5df23SVikas Chaudhary /* Map two pages whenever user tries to access addresses in two 741f4f5df23SVikas Chaudhary consecutive pages. 742f4f5df23SVikas Chaudhary */ 743f4f5df23SVikas Chaudhary if (mem_page != ((start + size - 1) & PAGE_MASK)) 744f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 745f4f5df23SVikas Chaudhary else 746f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 747f4f5df23SVikas Chaudhary 748f4f5df23SVikas Chaudhary if (mem_ptr == NULL) { 749f4f5df23SVikas Chaudhary *(u8 *)data = 0; 750f4f5df23SVikas Chaudhary return -1; 751f4f5df23SVikas Chaudhary } 752f4f5df23SVikas Chaudhary addr = mem_ptr; 753f4f5df23SVikas Chaudhary addr += start & (PAGE_SIZE - 1); 754f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 755f4f5df23SVikas Chaudhary } 756f4f5df23SVikas Chaudhary 757f4f5df23SVikas Chaudhary switch (size) { 758f4f5df23SVikas Chaudhary case 1: 759f4f5df23SVikas Chaudhary *(u8 *)data = readb(addr); 760f4f5df23SVikas Chaudhary break; 761f4f5df23SVikas Chaudhary case 2: 762f4f5df23SVikas Chaudhary *(u16 *)data = readw(addr); 763f4f5df23SVikas Chaudhary break; 764f4f5df23SVikas Chaudhary case 4: 765f4f5df23SVikas Chaudhary *(u32 *)data = readl(addr); 766f4f5df23SVikas Chaudhary break; 767f4f5df23SVikas Chaudhary case 8: 768f4f5df23SVikas Chaudhary *(u64 *)data = readq(addr); 769f4f5df23SVikas Chaudhary break; 770f4f5df23SVikas Chaudhary default: 771f4f5df23SVikas Chaudhary ret = -1; 772f4f5df23SVikas Chaudhary break; 773f4f5df23SVikas Chaudhary } 774f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 775f4f5df23SVikas Chaudhary 776f4f5df23SVikas Chaudhary if (mem_ptr) 777f4f5df23SVikas Chaudhary iounmap(mem_ptr); 778f4f5df23SVikas Chaudhary return ret; 779f4f5df23SVikas Chaudhary } 780f4f5df23SVikas Chaudhary 781f4f5df23SVikas Chaudhary static int 782f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, 783f4f5df23SVikas Chaudhary void *data, int size) 784f4f5df23SVikas Chaudhary { 785f4f5df23SVikas Chaudhary unsigned long flags; 786f4f5df23SVikas Chaudhary void __iomem *addr; 787f4f5df23SVikas Chaudhary int ret = 0; 788f4f5df23SVikas Chaudhary u64 start; 789f4f5df23SVikas Chaudhary void __iomem *mem_ptr = NULL; 790f4f5df23SVikas Chaudhary unsigned long mem_base; 791f4f5df23SVikas Chaudhary unsigned long mem_page; 792f4f5df23SVikas Chaudhary 793f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 794f4f5df23SVikas Chaudhary 795f4f5df23SVikas Chaudhary /* 796f4f5df23SVikas Chaudhary * If attempting to access unknown address or straddle hw windows, 797f4f5df23SVikas Chaudhary * do not access. 798f4f5df23SVikas Chaudhary */ 799f8086f4fSVikas Chaudhary start = qla4_82xx_pci_set_window(ha, off); 800f4f5df23SVikas Chaudhary if ((start == -1UL) || 801f8086f4fSVikas Chaudhary (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 802f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 803f4f5df23SVikas Chaudhary printk(KERN_ERR"%s out of bound pci memory access. " 804f4f5df23SVikas Chaudhary "offset is 0x%llx\n", DRIVER_NAME, off); 805f4f5df23SVikas Chaudhary return -1; 806f4f5df23SVikas Chaudhary } 807f4f5df23SVikas Chaudhary 808f4f5df23SVikas Chaudhary addr = qla4_8xxx_pci_base_offsetfset(ha, start); 809f4f5df23SVikas Chaudhary if (!addr) { 810f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 811f4f5df23SVikas Chaudhary mem_base = pci_resource_start(ha->pdev, 0); 812f4f5df23SVikas Chaudhary mem_page = start & PAGE_MASK; 813f4f5df23SVikas Chaudhary /* Map two pages whenever user tries to access addresses in two 814f4f5df23SVikas Chaudhary consecutive pages. 815f4f5df23SVikas Chaudhary */ 816f4f5df23SVikas Chaudhary if (mem_page != ((start + size - 1) & PAGE_MASK)) 817f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 818f4f5df23SVikas Chaudhary else 819f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 820f4f5df23SVikas Chaudhary if (mem_ptr == NULL) 821f4f5df23SVikas Chaudhary return -1; 822f4f5df23SVikas Chaudhary 823f4f5df23SVikas Chaudhary addr = mem_ptr; 824f4f5df23SVikas Chaudhary addr += start & (PAGE_SIZE - 1); 825f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 826f4f5df23SVikas Chaudhary } 827f4f5df23SVikas Chaudhary 828f4f5df23SVikas Chaudhary switch (size) { 829f4f5df23SVikas Chaudhary case 1: 830f4f5df23SVikas Chaudhary writeb(*(u8 *)data, addr); 831f4f5df23SVikas Chaudhary break; 832f4f5df23SVikas Chaudhary case 2: 833f4f5df23SVikas Chaudhary writew(*(u16 *)data, addr); 834f4f5df23SVikas Chaudhary break; 835f4f5df23SVikas Chaudhary case 4: 836f4f5df23SVikas Chaudhary writel(*(u32 *)data, addr); 837f4f5df23SVikas Chaudhary break; 838f4f5df23SVikas Chaudhary case 8: 839f4f5df23SVikas Chaudhary writeq(*(u64 *)data, addr); 840f4f5df23SVikas Chaudhary break; 841f4f5df23SVikas Chaudhary default: 842f4f5df23SVikas Chaudhary ret = -1; 843f4f5df23SVikas Chaudhary break; 844f4f5df23SVikas Chaudhary } 845f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 846f4f5df23SVikas Chaudhary if (mem_ptr) 847f4f5df23SVikas Chaudhary iounmap(mem_ptr); 848f4f5df23SVikas Chaudhary return ret; 849f4f5df23SVikas Chaudhary } 850f4f5df23SVikas Chaudhary 851f4f5df23SVikas Chaudhary #define MTU_FUDGE_FACTOR 100 852f4f5df23SVikas Chaudhary 853f4f5df23SVikas Chaudhary static unsigned long 854f8086f4fSVikas Chaudhary qla4_82xx_decode_crb_addr(unsigned long addr) 855f4f5df23SVikas Chaudhary { 856f4f5df23SVikas Chaudhary int i; 857f4f5df23SVikas Chaudhary unsigned long base_addr, offset, pci_base; 858f4f5df23SVikas Chaudhary 859f4f5df23SVikas Chaudhary if (!qla4_8xxx_crb_table_initialized) 860f8086f4fSVikas Chaudhary qla4_82xx_crb_addr_transform_setup(); 861f4f5df23SVikas Chaudhary 862f4f5df23SVikas Chaudhary pci_base = ADDR_ERROR; 863f4f5df23SVikas Chaudhary base_addr = addr & 0xfff00000; 864f4f5df23SVikas Chaudhary offset = addr & 0x000fffff; 865f4f5df23SVikas Chaudhary 866f4f5df23SVikas Chaudhary for (i = 0; i < MAX_CRB_XFORM; i++) { 867f4f5df23SVikas Chaudhary if (crb_addr_xform[i] == base_addr) { 868f4f5df23SVikas Chaudhary pci_base = i << 20; 869f4f5df23SVikas Chaudhary break; 870f4f5df23SVikas Chaudhary } 871f4f5df23SVikas Chaudhary } 872f4f5df23SVikas Chaudhary if (pci_base == ADDR_ERROR) 873f4f5df23SVikas Chaudhary return pci_base; 874f4f5df23SVikas Chaudhary else 875f4f5df23SVikas Chaudhary return pci_base + offset; 876f4f5df23SVikas Chaudhary } 877f4f5df23SVikas Chaudhary 878f4f5df23SVikas Chaudhary static long rom_max_timeout = 100; 8797664a1fdSVikas Chaudhary static long qla4_82xx_rom_lock_timeout = 100; 880f4f5df23SVikas Chaudhary 881f4f5df23SVikas Chaudhary static int 882f8086f4fSVikas Chaudhary qla4_82xx_rom_lock(struct scsi_qla_host *ha) 883f4f5df23SVikas Chaudhary { 884f4f5df23SVikas Chaudhary int i; 885f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 886f4f5df23SVikas Chaudhary 887f4f5df23SVikas Chaudhary while (!done) { 888f4f5df23SVikas Chaudhary /* acquire semaphore2 from PCI HW block */ 889f4f5df23SVikas Chaudhary 890f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 891f4f5df23SVikas Chaudhary if (done == 1) 892f4f5df23SVikas Chaudhary break; 8937664a1fdSVikas Chaudhary if (timeout >= qla4_82xx_rom_lock_timeout) 894f4f5df23SVikas Chaudhary return -1; 895f4f5df23SVikas Chaudhary 896f4f5df23SVikas Chaudhary timeout++; 897f4f5df23SVikas Chaudhary 898f4f5df23SVikas Chaudhary /* Yield CPU */ 899f4f5df23SVikas Chaudhary if (!in_interrupt()) 900f4f5df23SVikas Chaudhary schedule(); 901f4f5df23SVikas Chaudhary else { 902f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 903f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 904f4f5df23SVikas Chaudhary } 905f4f5df23SVikas Chaudhary } 906f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 907f4f5df23SVikas Chaudhary return 0; 908f4f5df23SVikas Chaudhary } 909f4f5df23SVikas Chaudhary 910f4f5df23SVikas Chaudhary static void 911f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(struct scsi_qla_host *ha) 912f4f5df23SVikas Chaudhary { 913f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 914f4f5df23SVikas Chaudhary } 915f4f5df23SVikas Chaudhary 916f4f5df23SVikas Chaudhary static int 917f8086f4fSVikas Chaudhary qla4_82xx_wait_rom_done(struct scsi_qla_host *ha) 918f4f5df23SVikas Chaudhary { 919f4f5df23SVikas Chaudhary long timeout = 0; 920f4f5df23SVikas Chaudhary long done = 0 ; 921f4f5df23SVikas Chaudhary 922f4f5df23SVikas Chaudhary while (done == 0) { 923f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 924f4f5df23SVikas Chaudhary done &= 2; 925f4f5df23SVikas Chaudhary timeout++; 926f4f5df23SVikas Chaudhary if (timeout >= rom_max_timeout) { 927f4f5df23SVikas Chaudhary printk("%s: Timeout reached waiting for rom done", 928f4f5df23SVikas Chaudhary DRIVER_NAME); 929f4f5df23SVikas Chaudhary return -1; 930f4f5df23SVikas Chaudhary } 931f4f5df23SVikas Chaudhary } 932f4f5df23SVikas Chaudhary return 0; 933f4f5df23SVikas Chaudhary } 934f4f5df23SVikas Chaudhary 935f4f5df23SVikas Chaudhary static int 936f8086f4fSVikas Chaudhary qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 937f4f5df23SVikas Chaudhary { 938f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 939f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 940f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 941f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 942f8086f4fSVikas Chaudhary if (qla4_82xx_wait_rom_done(ha)) { 943f4f5df23SVikas Chaudhary printk("%s: Error waiting for rom done\n", DRIVER_NAME); 944f4f5df23SVikas Chaudhary return -1; 945f4f5df23SVikas Chaudhary } 946f4f5df23SVikas Chaudhary /* reset abyte_cnt and dummy_byte_cnt */ 947f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 948f4f5df23SVikas Chaudhary udelay(10); 949f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 950f4f5df23SVikas Chaudhary 951f8086f4fSVikas Chaudhary *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 952f4f5df23SVikas Chaudhary return 0; 953f4f5df23SVikas Chaudhary } 954f4f5df23SVikas Chaudhary 955f4f5df23SVikas Chaudhary static int 956f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 957f4f5df23SVikas Chaudhary { 958f4f5df23SVikas Chaudhary int ret, loops = 0; 959f4f5df23SVikas Chaudhary 960f8086f4fSVikas Chaudhary while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { 961f4f5df23SVikas Chaudhary udelay(100); 962f4f5df23SVikas Chaudhary loops++; 963f4f5df23SVikas Chaudhary } 964f4f5df23SVikas Chaudhary if (loops >= 50000) { 965f8086f4fSVikas Chaudhary ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n", 966f8086f4fSVikas Chaudhary DRIVER_NAME); 967f4f5df23SVikas Chaudhary return -1; 968f4f5df23SVikas Chaudhary } 969f8086f4fSVikas Chaudhary ret = qla4_82xx_do_rom_fast_read(ha, addr, valp); 970f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 971f4f5df23SVikas Chaudhary return ret; 972f4f5df23SVikas Chaudhary } 973f4f5df23SVikas Chaudhary 974f4f5df23SVikas Chaudhary /** 975f4f5df23SVikas Chaudhary * This routine does CRB initialize sequence 976f4f5df23SVikas Chaudhary * to put the ISP into operational state 977f4f5df23SVikas Chaudhary **/ 978f4f5df23SVikas Chaudhary static int 979f8086f4fSVikas Chaudhary qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) 980f4f5df23SVikas Chaudhary { 981f4f5df23SVikas Chaudhary int addr, val; 982f4f5df23SVikas Chaudhary int i ; 983f4f5df23SVikas Chaudhary struct crb_addr_pair *buf; 984f4f5df23SVikas Chaudhary unsigned long off; 985f4f5df23SVikas Chaudhary unsigned offset, n; 986f4f5df23SVikas Chaudhary 987f4f5df23SVikas Chaudhary struct crb_addr_pair { 988f4f5df23SVikas Chaudhary long addr; 989f4f5df23SVikas Chaudhary long data; 990f4f5df23SVikas Chaudhary }; 991f4f5df23SVikas Chaudhary 992f4f5df23SVikas Chaudhary /* Halt all the indiviual PEGs and other blocks of the ISP */ 993f8086f4fSVikas Chaudhary qla4_82xx_rom_lock(ha); 994a1fc26baSSwapnil Nagle 995cb74428eSVikas Chaudhary /* disable all I2Q */ 996f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 997f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 998f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 999f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1000f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1001f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1002cb74428eSVikas Chaudhary 1003cb74428eSVikas Chaudhary /* disable all niu interrupts */ 1004f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1005a1fc26baSSwapnil Nagle /* disable xge rx/tx */ 1006f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1007a1fc26baSSwapnil Nagle /* disable xg1 rx/tx */ 1008f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1009cb74428eSVikas Chaudhary /* disable sideband mac */ 1010f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1011cb74428eSVikas Chaudhary /* disable ap0 mac */ 1012f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1013cb74428eSVikas Chaudhary /* disable ap1 mac */ 1014f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1015a1fc26baSSwapnil Nagle 1016a1fc26baSSwapnil Nagle /* halt sre */ 1017f8086f4fSVikas Chaudhary val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1018f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1019a1fc26baSSwapnil Nagle 1020a1fc26baSSwapnil Nagle /* halt epg */ 1021f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1022a1fc26baSSwapnil Nagle 1023a1fc26baSSwapnil Nagle /* halt timers */ 1024f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1025f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1026f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1027f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1028f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1029f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1030a1fc26baSSwapnil Nagle 1031a1fc26baSSwapnil Nagle /* halt pegs */ 1032f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1033f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1034f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1035f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1036f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1037cb74428eSVikas Chaudhary msleep(5); 1038a1fc26baSSwapnil Nagle 1039a1fc26baSSwapnil Nagle /* big hammer */ 1040f4f5df23SVikas Chaudhary if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 1041f4f5df23SVikas Chaudhary /* don't reset CAM block on reset */ 1042f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1043f4f5df23SVikas Chaudhary else 1044f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1045f4f5df23SVikas Chaudhary 1046f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 1047f4f5df23SVikas Chaudhary 1048f4f5df23SVikas Chaudhary /* Read the signature value from the flash. 1049f4f5df23SVikas Chaudhary * Offset 0: Contain signature (0xcafecafe) 1050f4f5df23SVikas Chaudhary * Offset 4: Offset and number of addr/value pairs 1051f4f5df23SVikas Chaudhary * that present in CRB initialize sequence 1052f4f5df23SVikas Chaudhary */ 1053f8086f4fSVikas Chaudhary if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1054f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(ha, 4, &n) != 0) { 1055f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1056f4f5df23SVikas Chaudhary "[ERROR] Reading crb_init area: n: %08x\n", n); 1057f4f5df23SVikas Chaudhary return -1; 1058f4f5df23SVikas Chaudhary } 1059f4f5df23SVikas Chaudhary 1060f4f5df23SVikas Chaudhary /* Offset in flash = lower 16 bits 1061f4f5df23SVikas Chaudhary * Number of enteries = upper 16 bits 1062f4f5df23SVikas Chaudhary */ 1063f4f5df23SVikas Chaudhary offset = n & 0xffffU; 1064f4f5df23SVikas Chaudhary n = (n >> 16) & 0xffffU; 1065f4f5df23SVikas Chaudhary 1066f4f5df23SVikas Chaudhary /* number of addr/value pair should not exceed 1024 enteries */ 1067f4f5df23SVikas Chaudhary if (n >= 1024) { 1068f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1069f4f5df23SVikas Chaudhary "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1070f4f5df23SVikas Chaudhary DRIVER_NAME, __func__, n); 1071f4f5df23SVikas Chaudhary return -1; 1072f4f5df23SVikas Chaudhary } 1073f4f5df23SVikas Chaudhary 1074f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1075f4f5df23SVikas Chaudhary "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); 1076f4f5df23SVikas Chaudhary 1077f4f5df23SVikas Chaudhary buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1078f4f5df23SVikas Chaudhary if (buf == NULL) { 1079f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1080f4f5df23SVikas Chaudhary "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); 1081f4f5df23SVikas Chaudhary return -1; 1082f4f5df23SVikas Chaudhary } 1083f4f5df23SVikas Chaudhary 1084f4f5df23SVikas Chaudhary for (i = 0; i < n; i++) { 1085f8086f4fSVikas Chaudhary if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1086f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 1087f4f5df23SVikas Chaudhary 0) { 1088f4f5df23SVikas Chaudhary kfree(buf); 1089f4f5df23SVikas Chaudhary return -1; 1090f4f5df23SVikas Chaudhary } 1091f4f5df23SVikas Chaudhary 1092f4f5df23SVikas Chaudhary buf[i].addr = addr; 1093f4f5df23SVikas Chaudhary buf[i].data = val; 1094f4f5df23SVikas Chaudhary } 1095f4f5df23SVikas Chaudhary 1096f4f5df23SVikas Chaudhary for (i = 0; i < n; i++) { 1097f4f5df23SVikas Chaudhary /* Translate internal CRB initialization 1098f4f5df23SVikas Chaudhary * address to PCI bus address 1099f4f5df23SVikas Chaudhary */ 1100f8086f4fSVikas Chaudhary off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1101f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE; 1102f4f5df23SVikas Chaudhary /* Not all CRB addr/value pair to be written, 1103f4f5df23SVikas Chaudhary * some of them are skipped 1104f4f5df23SVikas Chaudhary */ 1105f4f5df23SVikas Chaudhary 1106f4f5df23SVikas Chaudhary /* skip if LS bit is set*/ 1107f4f5df23SVikas Chaudhary if (off & 0x1) { 1108f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_WARNING, ha, 1109f4f5df23SVikas Chaudhary "Skip CRB init replay for offset = 0x%lx\n", off)); 1110f4f5df23SVikas Chaudhary continue; 1111f4f5df23SVikas Chaudhary } 1112f4f5df23SVikas Chaudhary 1113f4f5df23SVikas Chaudhary /* skipping cold reboot MAGIC */ 1114f4f5df23SVikas Chaudhary if (off == QLA82XX_CAM_RAM(0x1fc)) 1115f4f5df23SVikas Chaudhary continue; 1116f4f5df23SVikas Chaudhary 1117f4f5df23SVikas Chaudhary /* do not reset PCI */ 1118f4f5df23SVikas Chaudhary if (off == (ROMUSB_GLB + 0xbc)) 1119f4f5df23SVikas Chaudhary continue; 1120f4f5df23SVikas Chaudhary 1121f4f5df23SVikas Chaudhary /* skip core clock, so that firmware can increase the clock */ 1122f4f5df23SVikas Chaudhary if (off == (ROMUSB_GLB + 0xc8)) 1123f4f5df23SVikas Chaudhary continue; 1124f4f5df23SVikas Chaudhary 1125f4f5df23SVikas Chaudhary /* skip the function enable register */ 1126f4f5df23SVikas Chaudhary if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1127f4f5df23SVikas Chaudhary continue; 1128f4f5df23SVikas Chaudhary 1129f4f5df23SVikas Chaudhary if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1130f4f5df23SVikas Chaudhary continue; 1131f4f5df23SVikas Chaudhary 1132f4f5df23SVikas Chaudhary if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1133f4f5df23SVikas Chaudhary continue; 1134f4f5df23SVikas Chaudhary 1135f4f5df23SVikas Chaudhary if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1136f4f5df23SVikas Chaudhary continue; 1137f4f5df23SVikas Chaudhary 1138f4f5df23SVikas Chaudhary if (off == ADDR_ERROR) { 1139f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1140f4f5df23SVikas Chaudhary "%s: [ERROR] Unknown addr: 0x%08lx\n", 1141f4f5df23SVikas Chaudhary DRIVER_NAME, buf[i].addr); 1142f4f5df23SVikas Chaudhary continue; 1143f4f5df23SVikas Chaudhary } 1144f4f5df23SVikas Chaudhary 1145f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, off, buf[i].data); 1146f4f5df23SVikas Chaudhary 1147f4f5df23SVikas Chaudhary /* ISP requires much bigger delay to settle down, 1148f4f5df23SVikas Chaudhary * else crb_window returns 0xffffffff 1149f4f5df23SVikas Chaudhary */ 1150f4f5df23SVikas Chaudhary if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1151f4f5df23SVikas Chaudhary msleep(1000); 1152f4f5df23SVikas Chaudhary 1153f4f5df23SVikas Chaudhary /* ISP requires millisec delay between 1154f4f5df23SVikas Chaudhary * successive CRB register updation 1155f4f5df23SVikas Chaudhary */ 1156f4f5df23SVikas Chaudhary msleep(1); 1157f4f5df23SVikas Chaudhary } 1158f4f5df23SVikas Chaudhary 1159f4f5df23SVikas Chaudhary kfree(buf); 1160f4f5df23SVikas Chaudhary 1161f4f5df23SVikas Chaudhary /* Resetting the data and instruction cache */ 1162f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1163f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1164f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1165f4f5df23SVikas Chaudhary 1166f4f5df23SVikas Chaudhary /* Clear all protocol processing engines */ 1167f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1168f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1169f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1170f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1171f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1172f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1173f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1174f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1175f4f5df23SVikas Chaudhary 1176f4f5df23SVikas Chaudhary return 0; 1177f4f5df23SVikas Chaudhary } 1178f4f5df23SVikas Chaudhary 1179f4f5df23SVikas Chaudhary static int 1180f8086f4fSVikas Chaudhary qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) 1181f4f5df23SVikas Chaudhary { 11824cd83cbeSLalit Chandivade int i, rval = 0; 1183f4f5df23SVikas Chaudhary long size = 0; 1184f4f5df23SVikas Chaudhary long flashaddr, memaddr; 1185f4f5df23SVikas Chaudhary u64 data; 1186f4f5df23SVikas Chaudhary u32 high, low; 1187f4f5df23SVikas Chaudhary 1188f4f5df23SVikas Chaudhary flashaddr = memaddr = ha->hw.flt_region_bootload; 1189f4f5df23SVikas Chaudhary size = (image_start - flashaddr) / 8; 1190f4f5df23SVikas Chaudhary 1191f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", 1192f4f5df23SVikas Chaudhary ha->host_no, __func__, flashaddr, image_start)); 1193f4f5df23SVikas Chaudhary 1194f4f5df23SVikas Chaudhary for (i = 0; i < size; i++) { 1195f8086f4fSVikas Chaudhary if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1196f8086f4fSVikas Chaudhary (qla4_82xx_rom_fast_read(ha, flashaddr + 4, 1197f4f5df23SVikas Chaudhary (int *)&high))) { 11984cd83cbeSLalit Chandivade rval = -1; 11994cd83cbeSLalit Chandivade goto exit_load_from_flash; 1200f4f5df23SVikas Chaudhary } 1201f4f5df23SVikas Chaudhary data = ((u64)high << 32) | low ; 1202f8086f4fSVikas Chaudhary rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 12034cd83cbeSLalit Chandivade if (rval) 12044cd83cbeSLalit Chandivade goto exit_load_from_flash; 12054cd83cbeSLalit Chandivade 1206f4f5df23SVikas Chaudhary flashaddr += 8; 1207f4f5df23SVikas Chaudhary memaddr += 8; 1208f4f5df23SVikas Chaudhary 1209f4f5df23SVikas Chaudhary if (i % 0x1000 == 0) 1210f4f5df23SVikas Chaudhary msleep(1); 1211f4f5df23SVikas Chaudhary 1212f4f5df23SVikas Chaudhary } 1213f4f5df23SVikas Chaudhary 1214f4f5df23SVikas Chaudhary udelay(100); 1215f4f5df23SVikas Chaudhary 1216f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1217f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1218f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1219f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1220f4f5df23SVikas Chaudhary 12214cd83cbeSLalit Chandivade exit_load_from_flash: 12224cd83cbeSLalit Chandivade return rval; 1223f4f5df23SVikas Chaudhary } 1224f4f5df23SVikas Chaudhary 1225f8086f4fSVikas Chaudhary static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) 1226f4f5df23SVikas Chaudhary { 1227f4f5df23SVikas Chaudhary u32 rst; 1228f4f5df23SVikas Chaudhary 1229f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1230f8086f4fSVikas Chaudhary if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { 1231f4f5df23SVikas Chaudhary printk(KERN_WARNING "%s: Error during CRB Initialization\n", 1232f4f5df23SVikas Chaudhary __func__); 1233f4f5df23SVikas Chaudhary return QLA_ERROR; 1234f4f5df23SVikas Chaudhary } 1235f4f5df23SVikas Chaudhary 1236f4f5df23SVikas Chaudhary udelay(500); 1237f4f5df23SVikas Chaudhary 1238f4f5df23SVikas Chaudhary /* at this point, QM is in reset. This could be a problem if there are 1239f4f5df23SVikas Chaudhary * incoming d* transition queue messages. QM/PCIE could wedge. 1240f4f5df23SVikas Chaudhary * To get around this, QM is brought out of reset. 1241f4f5df23SVikas Chaudhary */ 1242f4f5df23SVikas Chaudhary 1243f8086f4fSVikas Chaudhary rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 1244f4f5df23SVikas Chaudhary /* unreset qm */ 1245f4f5df23SVikas Chaudhary rst &= ~(1 << 28); 1246f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 1247f4f5df23SVikas Chaudhary 1248f8086f4fSVikas Chaudhary if (qla4_82xx_load_from_flash(ha, image_start)) { 1249f4f5df23SVikas Chaudhary printk("%s: Error trying to load fw from flash!\n", __func__); 1250f4f5df23SVikas Chaudhary return QLA_ERROR; 1251f4f5df23SVikas Chaudhary } 1252f4f5df23SVikas Chaudhary 1253f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1254f4f5df23SVikas Chaudhary } 1255f4f5df23SVikas Chaudhary 1256f4f5df23SVikas Chaudhary int 1257f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha, 1258f4f5df23SVikas Chaudhary u64 off, void *data, int size) 1259f4f5df23SVikas Chaudhary { 1260f4f5df23SVikas Chaudhary int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1261f4f5df23SVikas Chaudhary int shift_amount; 1262f4f5df23SVikas Chaudhary uint32_t temp; 1263f4f5df23SVikas Chaudhary uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1264f4f5df23SVikas Chaudhary 1265f4f5df23SVikas Chaudhary /* 1266f4f5df23SVikas Chaudhary * If not MN, go check for MS or invalid. 1267f4f5df23SVikas Chaudhary */ 1268f4f5df23SVikas Chaudhary 1269de8c72daSVikas Chaudhary if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1270f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_QDR_NET; 1271f4f5df23SVikas Chaudhary else { 1272f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_DDR_NET; 1273f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) 1274f8086f4fSVikas Chaudhary return qla4_82xx_pci_mem_read_direct(ha, 1275f4f5df23SVikas Chaudhary off, data, size); 1276f4f5df23SVikas Chaudhary } 1277f4f5df23SVikas Chaudhary 1278f4f5df23SVikas Chaudhary 1279f4f5df23SVikas Chaudhary off8 = off & 0xfffffff0; 1280f4f5df23SVikas Chaudhary off0[0] = off & 0xf; 1281f4f5df23SVikas Chaudhary sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1282f4f5df23SVikas Chaudhary shift_amount = 4; 1283f4f5df23SVikas Chaudhary 1284f4f5df23SVikas Chaudhary loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1285f4f5df23SVikas Chaudhary off0[1] = 0; 1286f4f5df23SVikas Chaudhary sz[1] = size - sz[0]; 1287f4f5df23SVikas Chaudhary 1288f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1289f4f5df23SVikas Chaudhary temp = off8 + (i << shift_amount); 1290f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1291f4f5df23SVikas Chaudhary temp = 0; 1292f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1293f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_ENABLE; 1294f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1295c38fa3abSVikas Chaudhary temp = MIU_TA_CTL_START_ENABLE; 1296f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1297f4f5df23SVikas Chaudhary 1298f4f5df23SVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1299f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1300f4f5df23SVikas Chaudhary if ((temp & MIU_TA_CTL_BUSY) == 0) 1301f4f5df23SVikas Chaudhary break; 1302f4f5df23SVikas Chaudhary } 1303f4f5df23SVikas Chaudhary 1304f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1305068237c8STej Parkash printk_ratelimited(KERN_ERR 1306068237c8STej Parkash "%s: failed to read through agent\n", 1307068237c8STej Parkash __func__); 1308f4f5df23SVikas Chaudhary break; 1309f4f5df23SVikas Chaudhary } 1310f4f5df23SVikas Chaudhary 1311f4f5df23SVikas Chaudhary start = off0[i] >> 2; 1312f4f5df23SVikas Chaudhary end = (off0[i] + sz[i] - 1) >> 2; 1313f4f5df23SVikas Chaudhary for (k = start; k <= end; k++) { 1314f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, 1315f4f5df23SVikas Chaudhary mem_crb + MIU_TEST_AGT_RDDATA(k)); 1316f4f5df23SVikas Chaudhary word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1317f4f5df23SVikas Chaudhary } 1318f4f5df23SVikas Chaudhary } 1319f4f5df23SVikas Chaudhary 1320f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) 1321f4f5df23SVikas Chaudhary return -1; 1322f4f5df23SVikas Chaudhary 1323f4f5df23SVikas Chaudhary if ((off0[0] & 7) == 0) { 1324f4f5df23SVikas Chaudhary val = word[0]; 1325f4f5df23SVikas Chaudhary } else { 1326f4f5df23SVikas Chaudhary val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1327f4f5df23SVikas Chaudhary ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1328f4f5df23SVikas Chaudhary } 1329f4f5df23SVikas Chaudhary 1330f4f5df23SVikas Chaudhary switch (size) { 1331f4f5df23SVikas Chaudhary case 1: 1332f4f5df23SVikas Chaudhary *(uint8_t *)data = val; 1333f4f5df23SVikas Chaudhary break; 1334f4f5df23SVikas Chaudhary case 2: 1335f4f5df23SVikas Chaudhary *(uint16_t *)data = val; 1336f4f5df23SVikas Chaudhary break; 1337f4f5df23SVikas Chaudhary case 4: 1338f4f5df23SVikas Chaudhary *(uint32_t *)data = val; 1339f4f5df23SVikas Chaudhary break; 1340f4f5df23SVikas Chaudhary case 8: 1341f4f5df23SVikas Chaudhary *(uint64_t *)data = val; 1342f4f5df23SVikas Chaudhary break; 1343f4f5df23SVikas Chaudhary } 1344f4f5df23SVikas Chaudhary return 0; 1345f4f5df23SVikas Chaudhary } 1346f4f5df23SVikas Chaudhary 1347f4f5df23SVikas Chaudhary int 1348f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, 1349f4f5df23SVikas Chaudhary u64 off, void *data, int size) 1350f4f5df23SVikas Chaudhary { 1351f4f5df23SVikas Chaudhary int i, j, ret = 0, loop, sz[2], off0; 1352f4f5df23SVikas Chaudhary int scale, shift_amount, startword; 1353f4f5df23SVikas Chaudhary uint32_t temp; 1354f4f5df23SVikas Chaudhary uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1355f4f5df23SVikas Chaudhary 1356f4f5df23SVikas Chaudhary /* 1357f4f5df23SVikas Chaudhary * If not MN, go check for MS or invalid. 1358f4f5df23SVikas Chaudhary */ 1359de8c72daSVikas Chaudhary if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1360f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_QDR_NET; 1361f4f5df23SVikas Chaudhary else { 1362f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_DDR_NET; 1363f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) 1364f8086f4fSVikas Chaudhary return qla4_82xx_pci_mem_write_direct(ha, 1365f4f5df23SVikas Chaudhary off, data, size); 1366f4f5df23SVikas Chaudhary } 1367f4f5df23SVikas Chaudhary 1368f4f5df23SVikas Chaudhary off0 = off & 0x7; 1369f4f5df23SVikas Chaudhary sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1370f4f5df23SVikas Chaudhary sz[1] = size - sz[0]; 1371f4f5df23SVikas Chaudhary 1372f4f5df23SVikas Chaudhary off8 = off & 0xfffffff0; 1373f4f5df23SVikas Chaudhary loop = (((off & 0xf) + size - 1) >> 4) + 1; 1374f4f5df23SVikas Chaudhary shift_amount = 4; 1375f4f5df23SVikas Chaudhary scale = 2; 1376f4f5df23SVikas Chaudhary startword = (off & 0xf)/8; 1377f4f5df23SVikas Chaudhary 1378f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1379f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_read_2M(ha, off8 + 1380f4f5df23SVikas Chaudhary (i << shift_amount), &word[i * scale], 8)) 1381f4f5df23SVikas Chaudhary return -1; 1382f4f5df23SVikas Chaudhary } 1383f4f5df23SVikas Chaudhary 1384f4f5df23SVikas Chaudhary switch (size) { 1385f4f5df23SVikas Chaudhary case 1: 1386f4f5df23SVikas Chaudhary tmpw = *((uint8_t *)data); 1387f4f5df23SVikas Chaudhary break; 1388f4f5df23SVikas Chaudhary case 2: 1389f4f5df23SVikas Chaudhary tmpw = *((uint16_t *)data); 1390f4f5df23SVikas Chaudhary break; 1391f4f5df23SVikas Chaudhary case 4: 1392f4f5df23SVikas Chaudhary tmpw = *((uint32_t *)data); 1393f4f5df23SVikas Chaudhary break; 1394f4f5df23SVikas Chaudhary case 8: 1395f4f5df23SVikas Chaudhary default: 1396f4f5df23SVikas Chaudhary tmpw = *((uint64_t *)data); 1397f4f5df23SVikas Chaudhary break; 1398f4f5df23SVikas Chaudhary } 1399f4f5df23SVikas Chaudhary 1400f4f5df23SVikas Chaudhary if (sz[0] == 8) 1401f4f5df23SVikas Chaudhary word[startword] = tmpw; 1402f4f5df23SVikas Chaudhary else { 1403f4f5df23SVikas Chaudhary word[startword] &= 1404f4f5df23SVikas Chaudhary ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1405f4f5df23SVikas Chaudhary word[startword] |= tmpw << (off0 * 8); 1406f4f5df23SVikas Chaudhary } 1407f4f5df23SVikas Chaudhary 1408f4f5df23SVikas Chaudhary if (sz[1] != 0) { 1409f4f5df23SVikas Chaudhary word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1410f4f5df23SVikas Chaudhary word[startword+1] |= tmpw >> (sz[0] * 8); 1411f4f5df23SVikas Chaudhary } 1412f4f5df23SVikas Chaudhary 1413f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1414f4f5df23SVikas Chaudhary temp = off8 + (i << shift_amount); 1415f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1416f4f5df23SVikas Chaudhary temp = 0; 1417f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1418f4f5df23SVikas Chaudhary temp = word[i * scale] & 0xffffffff; 1419f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1420f4f5df23SVikas Chaudhary temp = (word[i * scale] >> 32) & 0xffffffff; 1421f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1422f4f5df23SVikas Chaudhary temp = word[i*scale + 1] & 0xffffffff; 1423f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, 1424f4f5df23SVikas Chaudhary temp); 1425f4f5df23SVikas Chaudhary temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1426f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, 1427f4f5df23SVikas Chaudhary temp); 1428f4f5df23SVikas Chaudhary 1429c38fa3abSVikas Chaudhary temp = MIU_TA_CTL_WRITE_ENABLE; 1430f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1431c38fa3abSVikas Chaudhary temp = MIU_TA_CTL_WRITE_START; 1432f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1433f4f5df23SVikas Chaudhary 1434f4f5df23SVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1435f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1436f4f5df23SVikas Chaudhary if ((temp & MIU_TA_CTL_BUSY) == 0) 1437f4f5df23SVikas Chaudhary break; 1438f4f5df23SVikas Chaudhary } 1439f4f5df23SVikas Chaudhary 1440f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1441f4f5df23SVikas Chaudhary if (printk_ratelimit()) 1442f4f5df23SVikas Chaudhary ql4_printk(KERN_ERR, ha, 1443068237c8STej Parkash "%s: failed to read through agent\n", 1444068237c8STej Parkash __func__); 1445f4f5df23SVikas Chaudhary ret = -1; 1446f4f5df23SVikas Chaudhary break; 1447f4f5df23SVikas Chaudhary } 1448f4f5df23SVikas Chaudhary } 1449f4f5df23SVikas Chaudhary 1450f4f5df23SVikas Chaudhary return ret; 1451f4f5df23SVikas Chaudhary } 1452f4f5df23SVikas Chaudhary 1453f8086f4fSVikas Chaudhary static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) 1454f4f5df23SVikas Chaudhary { 1455f4f5df23SVikas Chaudhary u32 val = 0; 1456f4f5df23SVikas Chaudhary int retries = 60; 1457f4f5df23SVikas Chaudhary 1458f4f5df23SVikas Chaudhary if (!pegtune_val) { 1459f4f5df23SVikas Chaudhary do { 1460f8086f4fSVikas Chaudhary val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE); 1461f4f5df23SVikas Chaudhary if ((val == PHAN_INITIALIZE_COMPLETE) || 1462f4f5df23SVikas Chaudhary (val == PHAN_INITIALIZE_ACK)) 1463f4f5df23SVikas Chaudhary return 0; 1464f4f5df23SVikas Chaudhary set_current_state(TASK_UNINTERRUPTIBLE); 1465f4f5df23SVikas Chaudhary schedule_timeout(500); 1466f4f5df23SVikas Chaudhary 1467f4f5df23SVikas Chaudhary } while (--retries); 1468f4f5df23SVikas Chaudhary 1469f4f5df23SVikas Chaudhary if (!retries) { 1470f8086f4fSVikas Chaudhary pegtune_val = qla4_82xx_rd_32(ha, 1471f4f5df23SVikas Chaudhary QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1472f4f5df23SVikas Chaudhary printk(KERN_WARNING "%s: init failed, " 1473f4f5df23SVikas Chaudhary "pegtune_val = %x\n", __func__, pegtune_val); 1474f4f5df23SVikas Chaudhary return -1; 1475f4f5df23SVikas Chaudhary } 1476f4f5df23SVikas Chaudhary } 1477f4f5df23SVikas Chaudhary return 0; 1478f4f5df23SVikas Chaudhary } 1479f4f5df23SVikas Chaudhary 1480f8086f4fSVikas Chaudhary static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha) 1481f4f5df23SVikas Chaudhary { 1482f4f5df23SVikas Chaudhary uint32_t state = 0; 1483f4f5df23SVikas Chaudhary int loops = 0; 1484f4f5df23SVikas Chaudhary 1485f4f5df23SVikas Chaudhary /* Window 1 call */ 1486f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1487f8086f4fSVikas Chaudhary state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); 1488f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1489f4f5df23SVikas Chaudhary 1490f4f5df23SVikas Chaudhary while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { 1491f4f5df23SVikas Chaudhary udelay(100); 1492f4f5df23SVikas Chaudhary /* Window 1 call */ 1493f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1494f8086f4fSVikas Chaudhary state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); 1495f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1496f4f5df23SVikas Chaudhary 1497f4f5df23SVikas Chaudhary loops++; 1498f4f5df23SVikas Chaudhary } 1499f4f5df23SVikas Chaudhary 1500f4f5df23SVikas Chaudhary if (loops >= 30000) { 1501f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 1502f4f5df23SVikas Chaudhary "Receive Peg initialization not complete: 0x%x.\n", state)); 1503f4f5df23SVikas Chaudhary return QLA_ERROR; 1504f4f5df23SVikas Chaudhary } 1505f4f5df23SVikas Chaudhary 1506f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1507f4f5df23SVikas Chaudhary } 1508f4f5df23SVikas Chaudhary 1509626115cdSAndrew Morton void 1510f4f5df23SVikas Chaudhary qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) 1511f4f5df23SVikas Chaudhary { 1512f4f5df23SVikas Chaudhary uint32_t drv_active; 1513f4f5df23SVikas Chaudhary 151433693c7aSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 15156e7b4292SVikas Chaudhary 15166e7b4292SVikas Chaudhary /* 1517b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 15186e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 15196e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 15206e7b4292SVikas Chaudhary */ 1521b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 15226e7b4292SVikas Chaudhary drv_active |= (1 << ha->func_num); 15236e7b4292SVikas Chaudhary else 1524f4f5df23SVikas Chaudhary drv_active |= (1 << (ha->func_num * 4)); 15256e7b4292SVikas Chaudhary 1526068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1527068237c8STej Parkash __func__, ha->host_no, drv_active); 152833693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); 1529f4f5df23SVikas Chaudhary } 1530f4f5df23SVikas Chaudhary 1531f4f5df23SVikas Chaudhary void 1532f4f5df23SVikas Chaudhary qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) 1533f4f5df23SVikas Chaudhary { 1534f4f5df23SVikas Chaudhary uint32_t drv_active; 1535f4f5df23SVikas Chaudhary 153633693c7aSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 15376e7b4292SVikas Chaudhary 15386e7b4292SVikas Chaudhary /* 1539b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 15406e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 15416e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 15426e7b4292SVikas Chaudhary */ 1543b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 15446e7b4292SVikas Chaudhary drv_active &= ~(1 << (ha->func_num)); 15456e7b4292SVikas Chaudhary else 1546f4f5df23SVikas Chaudhary drv_active &= ~(1 << (ha->func_num * 4)); 15476e7b4292SVikas Chaudhary 1548068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1549068237c8STej Parkash __func__, ha->host_no, drv_active); 155033693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); 1551f4f5df23SVikas Chaudhary } 1552f4f5df23SVikas Chaudhary 155333693c7aSVikas Chaudhary inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha) 1554f4f5df23SVikas Chaudhary { 15552232be0dSLalit Chandivade uint32_t drv_state, drv_active; 1556f4f5df23SVikas Chaudhary int rval; 1557f4f5df23SVikas Chaudhary 155833693c7aSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 155933693c7aSVikas Chaudhary drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 15606e7b4292SVikas Chaudhary 15616e7b4292SVikas Chaudhary /* 1562b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 15636e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 15646e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 15656e7b4292SVikas Chaudhary */ 1566b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 15676e7b4292SVikas Chaudhary rval = drv_state & (1 << ha->func_num); 15686e7b4292SVikas Chaudhary else 1569f4f5df23SVikas Chaudhary rval = drv_state & (1 << (ha->func_num * 4)); 15706e7b4292SVikas Chaudhary 15712232be0dSLalit Chandivade if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 15722232be0dSLalit Chandivade rval = 1; 15732232be0dSLalit Chandivade 1574f4f5df23SVikas Chaudhary return rval; 1575f4f5df23SVikas Chaudhary } 1576f4f5df23SVikas Chaudhary 15776e7b4292SVikas Chaudhary void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) 1578f4f5df23SVikas Chaudhary { 1579f4f5df23SVikas Chaudhary uint32_t drv_state; 1580f4f5df23SVikas Chaudhary 158133693c7aSVikas Chaudhary drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 15826e7b4292SVikas Chaudhary 15836e7b4292SVikas Chaudhary /* 1584b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 15856e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 15866e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 15876e7b4292SVikas Chaudhary */ 1588b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 15896e7b4292SVikas Chaudhary drv_state |= (1 << ha->func_num); 15906e7b4292SVikas Chaudhary else 1591f4f5df23SVikas Chaudhary drv_state |= (1 << (ha->func_num * 4)); 15926e7b4292SVikas Chaudhary 1593068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1594068237c8STej Parkash __func__, ha->host_no, drv_state); 159533693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); 1596f4f5df23SVikas Chaudhary } 1597f4f5df23SVikas Chaudhary 15986e7b4292SVikas Chaudhary void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) 1599f4f5df23SVikas Chaudhary { 1600f4f5df23SVikas Chaudhary uint32_t drv_state; 1601f4f5df23SVikas Chaudhary 160233693c7aSVikas Chaudhary drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 16036e7b4292SVikas Chaudhary 16046e7b4292SVikas Chaudhary /* 1605b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 16066e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 16076e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 16086e7b4292SVikas Chaudhary */ 1609b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 16106e7b4292SVikas Chaudhary drv_state &= ~(1 << ha->func_num); 16116e7b4292SVikas Chaudhary else 1612f4f5df23SVikas Chaudhary drv_state &= ~(1 << (ha->func_num * 4)); 16136e7b4292SVikas Chaudhary 1614068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1615068237c8STej Parkash __func__, ha->host_no, drv_state); 161633693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); 1617f4f5df23SVikas Chaudhary } 1618f4f5df23SVikas Chaudhary 1619f4f5df23SVikas Chaudhary static inline void 1620f4f5df23SVikas Chaudhary qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) 1621f4f5df23SVikas Chaudhary { 1622f4f5df23SVikas Chaudhary uint32_t qsnt_state; 1623f4f5df23SVikas Chaudhary 162433693c7aSVikas Chaudhary qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 16256e7b4292SVikas Chaudhary 16266e7b4292SVikas Chaudhary /* 1627b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 16286e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 16296e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function. 16306e7b4292SVikas Chaudhary */ 1631b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 16326e7b4292SVikas Chaudhary qsnt_state |= (1 << ha->func_num); 16336e7b4292SVikas Chaudhary else 1634f4f5df23SVikas Chaudhary qsnt_state |= (2 << (ha->func_num * 4)); 16356e7b4292SVikas Chaudhary 163633693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state); 1637f4f5df23SVikas Chaudhary } 1638f4f5df23SVikas Chaudhary 1639f4f5df23SVikas Chaudhary 1640f4f5df23SVikas Chaudhary static int 1641f8086f4fSVikas Chaudhary qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) 1642f4f5df23SVikas Chaudhary { 1643f4f5df23SVikas Chaudhary uint16_t lnk; 1644f4f5df23SVikas Chaudhary 1645f4f5df23SVikas Chaudhary /* scrub dma mask expansion register */ 1646f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 1647f4f5df23SVikas Chaudhary 1648f4f5df23SVikas Chaudhary /* Overwrite stale initialization register values */ 1649f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1650f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 1651f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 1652f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 1653f4f5df23SVikas Chaudhary 1654f8086f4fSVikas Chaudhary if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) { 1655f4f5df23SVikas Chaudhary printk("%s: Error trying to start fw!\n", __func__); 1656f4f5df23SVikas Chaudhary return QLA_ERROR; 1657f4f5df23SVikas Chaudhary } 1658f4f5df23SVikas Chaudhary 1659f4f5df23SVikas Chaudhary /* Handshake with the card before we register the devices. */ 1660f8086f4fSVikas Chaudhary if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { 1661f4f5df23SVikas Chaudhary printk("%s: Error during card handshake!\n", __func__); 1662f4f5df23SVikas Chaudhary return QLA_ERROR; 1663f4f5df23SVikas Chaudhary } 1664f4f5df23SVikas Chaudhary 1665f4f5df23SVikas Chaudhary /* Negotiated Link width */ 16665548bfd0SJiang Liu pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 1667f4f5df23SVikas Chaudhary ha->link_width = (lnk >> 4) & 0x3f; 1668f4f5df23SVikas Chaudhary 1669f4f5df23SVikas Chaudhary /* Synchronize with Receive peg */ 1670f8086f4fSVikas Chaudhary return qla4_82xx_rcvpeg_ready(ha); 1671f4f5df23SVikas Chaudhary } 1672f4f5df23SVikas Chaudhary 167333693c7aSVikas Chaudhary int qla4_82xx_try_start_fw(struct scsi_qla_host *ha) 1674f4f5df23SVikas Chaudhary { 1675f4f5df23SVikas Chaudhary int rval = QLA_ERROR; 1676f4f5df23SVikas Chaudhary 1677f4f5df23SVikas Chaudhary /* 1678f4f5df23SVikas Chaudhary * FW Load priority: 1679f4f5df23SVikas Chaudhary * 1) Operational firmware residing in flash. 1680f4f5df23SVikas Chaudhary * 2) Fail 1681f4f5df23SVikas Chaudhary */ 1682f4f5df23SVikas Chaudhary 1683f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1684f4f5df23SVikas Chaudhary "FW: Retrieving flash offsets from FLT/FDT ...\n"); 1685f4f5df23SVikas Chaudhary rval = qla4_8xxx_get_flash_info(ha); 1686f4f5df23SVikas Chaudhary if (rval != QLA_SUCCESS) 1687f4f5df23SVikas Chaudhary return rval; 1688f4f5df23SVikas Chaudhary 1689f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1690f4f5df23SVikas Chaudhary "FW: Attempting to load firmware from flash...\n"); 1691f8086f4fSVikas Chaudhary rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw); 1692f4f5df23SVikas Chaudhary 1693f581a3f7SVikas Chaudhary if (rval != QLA_SUCCESS) { 1694f581a3f7SVikas Chaudhary ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" 1695f581a3f7SVikas Chaudhary " FAILED...\n"); 1696f581a3f7SVikas Chaudhary return rval; 1697f581a3f7SVikas Chaudhary } 1698f4f5df23SVikas Chaudhary 1699f4f5df23SVikas Chaudhary return rval; 1700f4f5df23SVikas Chaudhary } 1701f4f5df23SVikas Chaudhary 170233693c7aSVikas Chaudhary void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha) 1703b25ee66fSShyam Sundar { 1704f8086f4fSVikas Chaudhary if (qla4_82xx_rom_lock(ha)) { 1705b25ee66fSShyam Sundar /* Someone else is holding the lock. */ 1706b25ee66fSShyam Sundar dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); 1707b25ee66fSShyam Sundar } 1708b25ee66fSShyam Sundar 1709b25ee66fSShyam Sundar /* 1710b25ee66fSShyam Sundar * Either we got the lock, or someone 1711b25ee66fSShyam Sundar * else died while holding it. 1712b25ee66fSShyam Sundar * In either case, unlock. 1713b25ee66fSShyam Sundar */ 1714f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 1715b25ee66fSShyam Sundar } 1716b25ee66fSShyam Sundar 1717068237c8STej Parkash static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha, 17187664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1719068237c8STej Parkash uint32_t **d_ptr) 1720068237c8STej Parkash { 1721068237c8STej Parkash uint32_t r_addr, r_stride, loop_cnt, i, r_value; 17227664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_crb *crb_hdr; 1723068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1724068237c8STej Parkash 1725068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 17267664a1fdSVikas Chaudhary crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr; 1727068237c8STej Parkash r_addr = crb_hdr->addr; 1728068237c8STej Parkash r_stride = crb_hdr->crb_strd.addr_stride; 1729068237c8STej Parkash loop_cnt = crb_hdr->op_count; 1730068237c8STej Parkash 1731068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 173233693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 1733068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_addr); 1734068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1735068237c8STej Parkash r_addr += r_stride; 1736068237c8STej Parkash } 1737068237c8STej Parkash *d_ptr = data_ptr; 1738068237c8STej Parkash } 1739068237c8STej Parkash 174041f79bdeSSantosh Vernekar static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha) 174141f79bdeSSantosh Vernekar { 174241f79bdeSSantosh Vernekar int rval = QLA_SUCCESS; 174341f79bdeSSantosh Vernekar uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 174441f79bdeSSantosh Vernekar uint64_t dma_base_addr = 0; 174541f79bdeSSantosh Vernekar struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL; 174641f79bdeSSantosh Vernekar 174741f79bdeSSantosh Vernekar tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 174841f79bdeSSantosh Vernekar ha->fw_dump_tmplt_hdr; 174941f79bdeSSantosh Vernekar dma_eng_num = 175041f79bdeSSantosh Vernekar tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX]; 175141f79bdeSSantosh Vernekar dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS + 175241f79bdeSSantosh Vernekar (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET); 175341f79bdeSSantosh Vernekar 175441f79bdeSSantosh Vernekar /* Read the pex-dma's command-status-and-control register. */ 175541f79bdeSSantosh Vernekar rval = ha->isp_ops->rd_reg_indirect(ha, 175641f79bdeSSantosh Vernekar (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL), 175741f79bdeSSantosh Vernekar &cmd_sts_and_cntrl); 175841f79bdeSSantosh Vernekar 175941f79bdeSSantosh Vernekar if (rval) 176041f79bdeSSantosh Vernekar return QLA_ERROR; 176141f79bdeSSantosh Vernekar 176241f79bdeSSantosh Vernekar /* Check if requested pex-dma engine is available. */ 176341f79bdeSSantosh Vernekar if (cmd_sts_and_cntrl & BIT_31) 176441f79bdeSSantosh Vernekar return QLA_SUCCESS; 176541f79bdeSSantosh Vernekar else 176641f79bdeSSantosh Vernekar return QLA_ERROR; 176741f79bdeSSantosh Vernekar } 176841f79bdeSSantosh Vernekar 176941f79bdeSSantosh Vernekar static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha, 177041f79bdeSSantosh Vernekar struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr) 177141f79bdeSSantosh Vernekar { 177241f79bdeSSantosh Vernekar int rval = QLA_SUCCESS, wait = 0; 177341f79bdeSSantosh Vernekar uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 177441f79bdeSSantosh Vernekar uint64_t dma_base_addr = 0; 177541f79bdeSSantosh Vernekar struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL; 177641f79bdeSSantosh Vernekar 177741f79bdeSSantosh Vernekar tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 177841f79bdeSSantosh Vernekar ha->fw_dump_tmplt_hdr; 177941f79bdeSSantosh Vernekar dma_eng_num = 178041f79bdeSSantosh Vernekar tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX]; 178141f79bdeSSantosh Vernekar dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS + 178241f79bdeSSantosh Vernekar (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET); 178341f79bdeSSantosh Vernekar 178441f79bdeSSantosh Vernekar rval = ha->isp_ops->wr_reg_indirect(ha, 178541f79bdeSSantosh Vernekar dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW, 178641f79bdeSSantosh Vernekar m_hdr->desc_card_addr); 178741f79bdeSSantosh Vernekar if (rval) 178841f79bdeSSantosh Vernekar goto error_exit; 178941f79bdeSSantosh Vernekar 179041f79bdeSSantosh Vernekar rval = ha->isp_ops->wr_reg_indirect(ha, 179141f79bdeSSantosh Vernekar dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0); 179241f79bdeSSantosh Vernekar if (rval) 179341f79bdeSSantosh Vernekar goto error_exit; 179441f79bdeSSantosh Vernekar 179541f79bdeSSantosh Vernekar rval = ha->isp_ops->wr_reg_indirect(ha, 179641f79bdeSSantosh Vernekar dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL, 179741f79bdeSSantosh Vernekar m_hdr->start_dma_cmd); 179841f79bdeSSantosh Vernekar if (rval) 179941f79bdeSSantosh Vernekar goto error_exit; 180041f79bdeSSantosh Vernekar 180141f79bdeSSantosh Vernekar /* Wait for dma operation to complete. */ 180241f79bdeSSantosh Vernekar for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) { 180341f79bdeSSantosh Vernekar rval = ha->isp_ops->rd_reg_indirect(ha, 180441f79bdeSSantosh Vernekar (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL), 180541f79bdeSSantosh Vernekar &cmd_sts_and_cntrl); 180641f79bdeSSantosh Vernekar if (rval) 180741f79bdeSSantosh Vernekar goto error_exit; 180841f79bdeSSantosh Vernekar 180941f79bdeSSantosh Vernekar if ((cmd_sts_and_cntrl & BIT_1) == 0) 181041f79bdeSSantosh Vernekar break; 181141f79bdeSSantosh Vernekar else 181241f79bdeSSantosh Vernekar udelay(10); 181341f79bdeSSantosh Vernekar } 181441f79bdeSSantosh Vernekar 181541f79bdeSSantosh Vernekar /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */ 181641f79bdeSSantosh Vernekar if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) { 181741f79bdeSSantosh Vernekar rval = QLA_ERROR; 181841f79bdeSSantosh Vernekar goto error_exit; 181941f79bdeSSantosh Vernekar } 182041f79bdeSSantosh Vernekar 182141f79bdeSSantosh Vernekar error_exit: 182241f79bdeSSantosh Vernekar return rval; 182341f79bdeSSantosh Vernekar } 182441f79bdeSSantosh Vernekar 182541f79bdeSSantosh Vernekar static int qla4_83xx_minidump_pex_dma_read(struct scsi_qla_host *ha, 182641f79bdeSSantosh Vernekar struct qla8xxx_minidump_entry_hdr *entry_hdr, 182741f79bdeSSantosh Vernekar uint32_t **d_ptr) 182841f79bdeSSantosh Vernekar { 182941f79bdeSSantosh Vernekar int rval = QLA_SUCCESS; 183041f79bdeSSantosh Vernekar struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL; 183141f79bdeSSantosh Vernekar uint32_t size, read_size; 183241f79bdeSSantosh Vernekar uint8_t *data_ptr = (uint8_t *)*d_ptr; 183341f79bdeSSantosh Vernekar void *rdmem_buffer = NULL; 183441f79bdeSSantosh Vernekar dma_addr_t rdmem_dma; 183541f79bdeSSantosh Vernekar struct qla4_83xx_pex_dma_descriptor dma_desc; 183641f79bdeSSantosh Vernekar 183741f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 183841f79bdeSSantosh Vernekar 183941f79bdeSSantosh Vernekar rval = qla4_83xx_check_dma_engine_state(ha); 184041f79bdeSSantosh Vernekar if (rval != QLA_SUCCESS) { 184141f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 184241f79bdeSSantosh Vernekar "%s: DMA engine not available. Fallback to rdmem-read.\n", 184341f79bdeSSantosh Vernekar __func__)); 184441f79bdeSSantosh Vernekar return QLA_ERROR; 184541f79bdeSSantosh Vernekar } 184641f79bdeSSantosh Vernekar 184741f79bdeSSantosh Vernekar m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr; 184841f79bdeSSantosh Vernekar rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, 184941f79bdeSSantosh Vernekar QLA83XX_PEX_DMA_READ_SIZE, 185041f79bdeSSantosh Vernekar &rdmem_dma, GFP_KERNEL); 185141f79bdeSSantosh Vernekar if (!rdmem_buffer) { 185241f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 185341f79bdeSSantosh Vernekar "%s: Unable to allocate rdmem dma buffer\n", 185441f79bdeSSantosh Vernekar __func__)); 185541f79bdeSSantosh Vernekar return QLA_ERROR; 185641f79bdeSSantosh Vernekar } 185741f79bdeSSantosh Vernekar 185841f79bdeSSantosh Vernekar /* Prepare pex-dma descriptor to be written to MS memory. */ 185941f79bdeSSantosh Vernekar /* dma-desc-cmd layout: 186041f79bdeSSantosh Vernekar * 0-3: dma-desc-cmd 0-3 186141f79bdeSSantosh Vernekar * 4-7: pcid function number 186241f79bdeSSantosh Vernekar * 8-15: dma-desc-cmd 8-15 186341f79bdeSSantosh Vernekar */ 186441f79bdeSSantosh Vernekar dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); 186541f79bdeSSantosh Vernekar dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); 186641f79bdeSSantosh Vernekar dma_desc.dma_bus_addr = rdmem_dma; 186741f79bdeSSantosh Vernekar 186841f79bdeSSantosh Vernekar size = 0; 186941f79bdeSSantosh Vernekar read_size = 0; 187041f79bdeSSantosh Vernekar /* 187141f79bdeSSantosh Vernekar * Perform rdmem operation using pex-dma. 187241f79bdeSSantosh Vernekar * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE. 187341f79bdeSSantosh Vernekar */ 187441f79bdeSSantosh Vernekar while (read_size < m_hdr->read_data_size) { 187541f79bdeSSantosh Vernekar if (m_hdr->read_data_size - read_size >= 187641f79bdeSSantosh Vernekar QLA83XX_PEX_DMA_READ_SIZE) 187741f79bdeSSantosh Vernekar size = QLA83XX_PEX_DMA_READ_SIZE; 187841f79bdeSSantosh Vernekar else { 187941f79bdeSSantosh Vernekar size = (m_hdr->read_data_size - read_size); 188041f79bdeSSantosh Vernekar 188141f79bdeSSantosh Vernekar if (rdmem_buffer) 188241f79bdeSSantosh Vernekar dma_free_coherent(&ha->pdev->dev, 188341f79bdeSSantosh Vernekar QLA83XX_PEX_DMA_READ_SIZE, 188441f79bdeSSantosh Vernekar rdmem_buffer, rdmem_dma); 188541f79bdeSSantosh Vernekar 188641f79bdeSSantosh Vernekar rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size, 188741f79bdeSSantosh Vernekar &rdmem_dma, 188841f79bdeSSantosh Vernekar GFP_KERNEL); 188941f79bdeSSantosh Vernekar if (!rdmem_buffer) { 189041f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 189141f79bdeSSantosh Vernekar "%s: Unable to allocate rdmem dma buffer\n", 189241f79bdeSSantosh Vernekar __func__)); 189341f79bdeSSantosh Vernekar return QLA_ERROR; 189441f79bdeSSantosh Vernekar } 189541f79bdeSSantosh Vernekar dma_desc.dma_bus_addr = rdmem_dma; 189641f79bdeSSantosh Vernekar } 189741f79bdeSSantosh Vernekar 189841f79bdeSSantosh Vernekar dma_desc.src_addr = m_hdr->read_addr + read_size; 189941f79bdeSSantosh Vernekar dma_desc.cmd.read_data_size = size; 190041f79bdeSSantosh Vernekar 190141f79bdeSSantosh Vernekar /* Prepare: Write pex-dma descriptor to MS memory. */ 190241f79bdeSSantosh Vernekar rval = qla4_83xx_ms_mem_write_128b(ha, 190341f79bdeSSantosh Vernekar (uint64_t)m_hdr->desc_card_addr, 190441f79bdeSSantosh Vernekar (uint32_t *)&dma_desc, 190541f79bdeSSantosh Vernekar (sizeof(struct qla4_83xx_pex_dma_descriptor)/16)); 190641f79bdeSSantosh Vernekar if (rval == -1) { 190741f79bdeSSantosh Vernekar ql4_printk(KERN_INFO, ha, 190841f79bdeSSantosh Vernekar "%s: Error writing rdmem-dma-init to MS !!!\n", 190941f79bdeSSantosh Vernekar __func__); 191041f79bdeSSantosh Vernekar goto error_exit; 191141f79bdeSSantosh Vernekar } 191241f79bdeSSantosh Vernekar 191341f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 191441f79bdeSSantosh Vernekar "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n", 191541f79bdeSSantosh Vernekar __func__, size)); 191641f79bdeSSantosh Vernekar /* Execute: Start pex-dma operation. */ 191741f79bdeSSantosh Vernekar rval = qla4_83xx_start_pex_dma(ha, m_hdr); 191841f79bdeSSantosh Vernekar if (rval != QLA_SUCCESS) { 191941f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 192041f79bdeSSantosh Vernekar "scsi(%ld): start-pex-dma failed rval=0x%x\n", 192141f79bdeSSantosh Vernekar ha->host_no, rval)); 192241f79bdeSSantosh Vernekar goto error_exit; 192341f79bdeSSantosh Vernekar } 192441f79bdeSSantosh Vernekar 192541f79bdeSSantosh Vernekar memcpy(data_ptr, rdmem_buffer, size); 192641f79bdeSSantosh Vernekar data_ptr += size; 192741f79bdeSSantosh Vernekar read_size += size; 192841f79bdeSSantosh Vernekar } 192941f79bdeSSantosh Vernekar 193041f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); 193141f79bdeSSantosh Vernekar 193241f79bdeSSantosh Vernekar *d_ptr = (uint32_t *)data_ptr; 193341f79bdeSSantosh Vernekar 193441f79bdeSSantosh Vernekar error_exit: 193541f79bdeSSantosh Vernekar if (rdmem_buffer) 193641f79bdeSSantosh Vernekar dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer, 193741f79bdeSSantosh Vernekar rdmem_dma); 193841f79bdeSSantosh Vernekar 193941f79bdeSSantosh Vernekar return rval; 194041f79bdeSSantosh Vernekar } 194141f79bdeSSantosh Vernekar 1942068237c8STej Parkash static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha, 19437664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1944068237c8STej Parkash uint32_t **d_ptr) 1945068237c8STej Parkash { 1946068237c8STej Parkash uint32_t addr, r_addr, c_addr, t_r_addr; 1947068237c8STej Parkash uint32_t i, k, loop_count, t_value, r_cnt, r_value; 1948068237c8STej Parkash unsigned long p_wait, w_time, p_mask; 1949068237c8STej Parkash uint32_t c_value_w, c_value_r; 19507664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_cache *cache_hdr; 1951068237c8STej Parkash int rval = QLA_ERROR; 1952068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1953068237c8STej Parkash 1954068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 19557664a1fdSVikas Chaudhary cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; 1956068237c8STej Parkash 1957068237c8STej Parkash loop_count = cache_hdr->op_count; 1958068237c8STej Parkash r_addr = cache_hdr->read_addr; 1959068237c8STej Parkash c_addr = cache_hdr->control_addr; 1960068237c8STej Parkash c_value_w = cache_hdr->cache_ctrl.write_value; 1961068237c8STej Parkash 1962068237c8STej Parkash t_r_addr = cache_hdr->tag_reg_addr; 1963068237c8STej Parkash t_value = cache_hdr->addr_ctrl.init_tag_value; 1964068237c8STej Parkash r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 1965068237c8STej Parkash p_wait = cache_hdr->cache_ctrl.poll_wait; 1966068237c8STej Parkash p_mask = cache_hdr->cache_ctrl.poll_mask; 1967068237c8STej Parkash 1968068237c8STej Parkash for (i = 0; i < loop_count; i++) { 196933693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); 1970068237c8STej Parkash 1971068237c8STej Parkash if (c_value_w) 197233693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); 1973068237c8STej Parkash 1974068237c8STej Parkash if (p_mask) { 1975068237c8STej Parkash w_time = jiffies + p_wait; 1976068237c8STej Parkash do { 197733693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, c_addr, 197833693c7aSVikas Chaudhary &c_value_r); 1979068237c8STej Parkash if ((c_value_r & p_mask) == 0) { 1980068237c8STej Parkash break; 1981068237c8STej Parkash } else if (time_after_eq(jiffies, w_time)) { 1982068237c8STej Parkash /* capturing dump failed */ 1983068237c8STej Parkash return rval; 1984068237c8STej Parkash } 1985068237c8STej Parkash } while (1); 1986068237c8STej Parkash } 1987068237c8STej Parkash 1988068237c8STej Parkash addr = r_addr; 1989068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 199033693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); 1991068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1992068237c8STej Parkash addr += cache_hdr->read_ctrl.read_addr_stride; 1993068237c8STej Parkash } 1994068237c8STej Parkash 1995068237c8STej Parkash t_value += cache_hdr->addr_ctrl.tag_value_stride; 1996068237c8STej Parkash } 1997068237c8STej Parkash *d_ptr = data_ptr; 1998068237c8STej Parkash return QLA_SUCCESS; 1999068237c8STej Parkash } 2000068237c8STej Parkash 2001068237c8STej Parkash static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, 20027664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr) 2003068237c8STej Parkash { 20047664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_crb *crb_entry; 2005068237c8STej Parkash uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS; 2006068237c8STej Parkash uint32_t crb_addr; 2007068237c8STej Parkash unsigned long wtime; 2008068237c8STej Parkash struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 2009068237c8STej Parkash int i; 2010068237c8STej Parkash 2011068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2012068237c8STej Parkash tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 2013068237c8STej Parkash ha->fw_dump_tmplt_hdr; 20147664a1fdSVikas Chaudhary crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr; 2015068237c8STej Parkash 2016068237c8STej Parkash crb_addr = crb_entry->addr; 2017068237c8STej Parkash for (i = 0; i < crb_entry->op_count; i++) { 2018068237c8STej Parkash opcode = crb_entry->crb_ctrl.opcode; 2019de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_WR) { 202033693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, 202133693c7aSVikas Chaudhary crb_entry->value_1); 2022de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_WR; 2023068237c8STej Parkash } 2024de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_RW) { 202533693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 202633693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2027de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_RW; 2028068237c8STej Parkash } 2029de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_AND) { 203033693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2031068237c8STej Parkash read_value &= crb_entry->value_2; 2032de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_AND; 2033de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_OR) { 2034068237c8STej Parkash read_value |= crb_entry->value_3; 2035de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_OR; 2036068237c8STej Parkash } 203733693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2038068237c8STej Parkash } 2039de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_OR) { 204033693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2041068237c8STej Parkash read_value |= crb_entry->value_3; 204233693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2043de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_OR; 2044068237c8STej Parkash } 2045de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_POLL) { 2046068237c8STej Parkash poll_time = crb_entry->crb_strd.poll_timeout; 2047068237c8STej Parkash wtime = jiffies + poll_time; 204833693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2049068237c8STej Parkash 2050068237c8STej Parkash do { 2051068237c8STej Parkash if ((read_value & crb_entry->value_2) == 205233693c7aSVikas Chaudhary crb_entry->value_1) { 2053068237c8STej Parkash break; 205433693c7aSVikas Chaudhary } else if (time_after_eq(jiffies, wtime)) { 2055068237c8STej Parkash /* capturing dump failed */ 2056068237c8STej Parkash rval = QLA_ERROR; 2057068237c8STej Parkash break; 205833693c7aSVikas Chaudhary } else { 205933693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, 206033693c7aSVikas Chaudhary crb_addr, &read_value); 206133693c7aSVikas Chaudhary } 2062068237c8STej Parkash } while (1); 2063de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_POLL; 2064068237c8STej Parkash } 2065068237c8STej Parkash 2066de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) { 2067068237c8STej Parkash if (crb_entry->crb_strd.state_index_a) { 2068068237c8STej Parkash index = crb_entry->crb_strd.state_index_a; 2069068237c8STej Parkash addr = tmplt_hdr->saved_state_array[index]; 2070068237c8STej Parkash } else { 2071068237c8STej Parkash addr = crb_addr; 2072068237c8STej Parkash } 2073068237c8STej Parkash 207433693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr, &read_value); 2075068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 2076068237c8STej Parkash tmplt_hdr->saved_state_array[index] = read_value; 2077de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE; 2078068237c8STej Parkash } 2079068237c8STej Parkash 2080de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) { 2081068237c8STej Parkash if (crb_entry->crb_strd.state_index_a) { 2082068237c8STej Parkash index = crb_entry->crb_strd.state_index_a; 2083068237c8STej Parkash addr = tmplt_hdr->saved_state_array[index]; 2084068237c8STej Parkash } else { 2085068237c8STej Parkash addr = crb_addr; 2086068237c8STej Parkash } 2087068237c8STej Parkash 2088068237c8STej Parkash if (crb_entry->crb_ctrl.state_index_v) { 2089068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 2090068237c8STej Parkash read_value = 2091068237c8STej Parkash tmplt_hdr->saved_state_array[index]; 2092068237c8STej Parkash } else { 2093068237c8STej Parkash read_value = crb_entry->value_1; 2094068237c8STej Parkash } 2095068237c8STej Parkash 209633693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr, read_value); 2097de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE; 2098068237c8STej Parkash } 2099068237c8STej Parkash 2100de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) { 2101068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 2102068237c8STej Parkash read_value = tmplt_hdr->saved_state_array[index]; 2103068237c8STej Parkash read_value <<= crb_entry->crb_ctrl.shl; 2104068237c8STej Parkash read_value >>= crb_entry->crb_ctrl.shr; 2105068237c8STej Parkash if (crb_entry->value_2) 2106068237c8STej Parkash read_value &= crb_entry->value_2; 2107068237c8STej Parkash read_value |= crb_entry->value_3; 2108068237c8STej Parkash read_value += crb_entry->value_1; 2109068237c8STej Parkash tmplt_hdr->saved_state_array[index] = read_value; 2110de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE; 2111068237c8STej Parkash } 2112068237c8STej Parkash crb_addr += crb_entry->crb_strd.addr_stride; 2113068237c8STej Parkash } 2114068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); 2115068237c8STej Parkash return rval; 2116068237c8STej Parkash } 2117068237c8STej Parkash 2118068237c8STej Parkash static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha, 21197664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2120068237c8STej Parkash uint32_t **d_ptr) 2121068237c8STej Parkash { 2122068237c8STej Parkash uint32_t r_addr, r_stride, loop_cnt, i, r_value; 21237664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdocm *ocm_hdr; 2124068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2125068237c8STej Parkash 2126068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 21277664a1fdSVikas Chaudhary ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr; 2128068237c8STej Parkash r_addr = ocm_hdr->read_addr; 2129068237c8STej Parkash r_stride = ocm_hdr->read_addr_stride; 2130068237c8STej Parkash loop_cnt = ocm_hdr->op_count; 2131068237c8STej Parkash 2132068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2133068237c8STej Parkash "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", 2134068237c8STej Parkash __func__, r_addr, r_stride, loop_cnt)); 2135068237c8STej Parkash 2136068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 2137068237c8STej Parkash r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); 2138068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2139068237c8STej Parkash r_addr += r_stride; 2140068237c8STej Parkash } 2141068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n", 214226fdf922SVikas Chaudhary __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)))); 2143068237c8STej Parkash *d_ptr = data_ptr; 2144068237c8STej Parkash } 2145068237c8STej Parkash 2146068237c8STej Parkash static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha, 21477664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2148068237c8STej Parkash uint32_t **d_ptr) 2149068237c8STej Parkash { 2150068237c8STej Parkash uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 21517664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_mux *mux_hdr; 2152068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2153068237c8STej Parkash 2154068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 21557664a1fdSVikas Chaudhary mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr; 2156068237c8STej Parkash r_addr = mux_hdr->read_addr; 2157068237c8STej Parkash s_addr = mux_hdr->select_addr; 2158068237c8STej Parkash s_stride = mux_hdr->select_value_stride; 2159068237c8STej Parkash s_value = mux_hdr->select_value; 2160068237c8STej Parkash loop_cnt = mux_hdr->op_count; 2161068237c8STej Parkash 2162068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 216333693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); 216433693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 2165068237c8STej Parkash *data_ptr++ = cpu_to_le32(s_value); 2166068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2167068237c8STej Parkash s_value += s_stride; 2168068237c8STej Parkash } 2169068237c8STej Parkash *d_ptr = data_ptr; 2170068237c8STej Parkash } 2171068237c8STej Parkash 2172068237c8STej Parkash static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha, 21737664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2174068237c8STej Parkash uint32_t **d_ptr) 2175068237c8STej Parkash { 2176068237c8STej Parkash uint32_t addr, r_addr, c_addr, t_r_addr; 2177068237c8STej Parkash uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2178068237c8STej Parkash uint32_t c_value_w; 21797664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_cache *cache_hdr; 2180068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2181068237c8STej Parkash 21827664a1fdSVikas Chaudhary cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; 2183068237c8STej Parkash loop_count = cache_hdr->op_count; 2184068237c8STej Parkash r_addr = cache_hdr->read_addr; 2185068237c8STej Parkash c_addr = cache_hdr->control_addr; 2186068237c8STej Parkash c_value_w = cache_hdr->cache_ctrl.write_value; 2187068237c8STej Parkash 2188068237c8STej Parkash t_r_addr = cache_hdr->tag_reg_addr; 2189068237c8STej Parkash t_value = cache_hdr->addr_ctrl.init_tag_value; 2190068237c8STej Parkash r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2191068237c8STej Parkash 2192068237c8STej Parkash for (i = 0; i < loop_count; i++) { 219333693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); 219433693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); 2195068237c8STej Parkash addr = r_addr; 2196068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 219733693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); 2198068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2199068237c8STej Parkash addr += cache_hdr->read_ctrl.read_addr_stride; 2200068237c8STej Parkash } 2201068237c8STej Parkash t_value += cache_hdr->addr_ctrl.tag_value_stride; 2202068237c8STej Parkash } 2203068237c8STej Parkash *d_ptr = data_ptr; 2204068237c8STej Parkash } 2205068237c8STej Parkash 2206068237c8STej Parkash static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha, 22077664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2208068237c8STej Parkash uint32_t **d_ptr) 2209068237c8STej Parkash { 2210068237c8STej Parkash uint32_t s_addr, r_addr; 2211068237c8STej Parkash uint32_t r_stride, r_value, r_cnt, qid = 0; 2212068237c8STej Parkash uint32_t i, k, loop_cnt; 22137664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_queue *q_hdr; 2214068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2215068237c8STej Parkash 2216068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 22177664a1fdSVikas Chaudhary q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr; 2218068237c8STej Parkash s_addr = q_hdr->select_addr; 2219068237c8STej Parkash r_cnt = q_hdr->rd_strd.read_addr_cnt; 2220068237c8STej Parkash r_stride = q_hdr->rd_strd.read_addr_stride; 2221068237c8STej Parkash loop_cnt = q_hdr->op_count; 2222068237c8STej Parkash 2223068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 222433693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, s_addr, qid); 2225068237c8STej Parkash r_addr = q_hdr->read_addr; 2226068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 222733693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 2228068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2229068237c8STej Parkash r_addr += r_stride; 2230068237c8STej Parkash } 2231068237c8STej Parkash qid += q_hdr->q_strd.queue_id_stride; 2232068237c8STej Parkash } 2233068237c8STej Parkash *d_ptr = data_ptr; 2234068237c8STej Parkash } 2235068237c8STej Parkash 2236068237c8STej Parkash #define MD_DIRECT_ROM_WINDOW 0x42110030 2237068237c8STej Parkash #define MD_DIRECT_ROM_READ_BASE 0x42150000 2238068237c8STej Parkash 2239f8086f4fSVikas Chaudhary static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha, 22407664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2241068237c8STej Parkash uint32_t **d_ptr) 2242068237c8STej Parkash { 2243068237c8STej Parkash uint32_t r_addr, r_value; 2244068237c8STej Parkash uint32_t i, loop_cnt; 22457664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdrom *rom_hdr; 2246068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2247068237c8STej Parkash 2248068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 22497664a1fdSVikas Chaudhary rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; 2250068237c8STej Parkash r_addr = rom_hdr->read_addr; 2251068237c8STej Parkash loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 2252068237c8STej Parkash 2253068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2254068237c8STej Parkash "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n", 2255068237c8STej Parkash __func__, r_addr, loop_cnt)); 2256068237c8STej Parkash 2257068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 225833693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW, 225933693c7aSVikas Chaudhary (r_addr & 0xFFFF0000)); 226033693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, 226133693c7aSVikas Chaudhary MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF), 226233693c7aSVikas Chaudhary &r_value); 2263068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2264068237c8STej Parkash r_addr += sizeof(uint32_t); 2265068237c8STej Parkash } 2266068237c8STej Parkash *d_ptr = data_ptr; 2267068237c8STej Parkash } 2268068237c8STej Parkash 2269068237c8STej Parkash #define MD_MIU_TEST_AGT_CTRL 0x41000090 2270068237c8STej Parkash #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 2271068237c8STej Parkash #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 2272068237c8STej Parkash 227341f79bdeSSantosh Vernekar static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 22747664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2275068237c8STej Parkash uint32_t **d_ptr) 2276068237c8STej Parkash { 2277068237c8STej Parkash uint32_t r_addr, r_value, r_data; 2278068237c8STej Parkash uint32_t i, j, loop_cnt; 22797664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdmem *m_hdr; 2280068237c8STej Parkash unsigned long flags; 2281068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2282068237c8STej Parkash 2283068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 22847664a1fdSVikas Chaudhary m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr; 2285068237c8STej Parkash r_addr = m_hdr->read_addr; 2286068237c8STej Parkash loop_cnt = m_hdr->read_data_size/16; 2287068237c8STej Parkash 2288068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2289068237c8STej Parkash "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", 2290068237c8STej Parkash __func__, r_addr, m_hdr->read_data_size)); 2291068237c8STej Parkash 2292068237c8STej Parkash if (r_addr & 0xf) { 2293068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2294cf2fbdd2SMasanari Iida "[%s]: Read addr 0x%x not 16 bytes aligned\n", 2295068237c8STej Parkash __func__, r_addr)); 2296068237c8STej Parkash return QLA_ERROR; 2297068237c8STej Parkash } 2298068237c8STej Parkash 2299068237c8STej Parkash if (m_hdr->read_data_size % 16) { 2300068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2301068237c8STej Parkash "[%s]: Read data[0x%x] not multiple of 16 bytes\n", 2302068237c8STej Parkash __func__, m_hdr->read_data_size)); 2303068237c8STej Parkash return QLA_ERROR; 2304068237c8STej Parkash } 2305068237c8STej Parkash 2306068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2307068237c8STej Parkash "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 2308068237c8STej Parkash __func__, r_addr, m_hdr->read_data_size, loop_cnt)); 2309068237c8STej Parkash 2310068237c8STej Parkash write_lock_irqsave(&ha->hw_lock, flags); 2311068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 231233693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO, 231333693c7aSVikas Chaudhary r_addr); 2314068237c8STej Parkash r_value = 0; 231533693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 231633693c7aSVikas Chaudhary r_value); 2317068237c8STej Parkash r_value = MIU_TA_CTL_ENABLE; 231833693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); 2319c38fa3abSVikas Chaudhary r_value = MIU_TA_CTL_START_ENABLE; 232033693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); 2321068237c8STej Parkash 2322068237c8STej Parkash for (j = 0; j < MAX_CTL_CHECK; j++) { 232333693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, 232433693c7aSVikas Chaudhary &r_value); 2325068237c8STej Parkash if ((r_value & MIU_TA_CTL_BUSY) == 0) 2326068237c8STej Parkash break; 2327068237c8STej Parkash } 2328068237c8STej Parkash 2329068237c8STej Parkash if (j >= MAX_CTL_CHECK) { 2330068237c8STej Parkash printk_ratelimited(KERN_ERR 2331068237c8STej Parkash "%s: failed to read through agent\n", 2332068237c8STej Parkash __func__); 2333068237c8STej Parkash write_unlock_irqrestore(&ha->hw_lock, flags); 2334068237c8STej Parkash return QLA_SUCCESS; 2335068237c8STej Parkash } 2336068237c8STej Parkash 2337068237c8STej Parkash for (j = 0; j < 4; j++) { 233833693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, 2339068237c8STej Parkash MD_MIU_TEST_AGT_RDDATA[j], 234033693c7aSVikas Chaudhary &r_data); 2341068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_data); 2342068237c8STej Parkash } 2343068237c8STej Parkash 2344068237c8STej Parkash r_addr += 16; 2345068237c8STej Parkash } 2346068237c8STej Parkash write_unlock_irqrestore(&ha->hw_lock, flags); 2347068237c8STej Parkash 2348068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n", 2349068237c8STej Parkash __func__, (loop_cnt * 16))); 2350068237c8STej Parkash 2351068237c8STej Parkash *d_ptr = data_ptr; 2352068237c8STej Parkash return QLA_SUCCESS; 2353068237c8STej Parkash } 2354068237c8STej Parkash 235541f79bdeSSantosh Vernekar static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 235641f79bdeSSantosh Vernekar struct qla8xxx_minidump_entry_hdr *entry_hdr, 235741f79bdeSSantosh Vernekar uint32_t **d_ptr) 235841f79bdeSSantosh Vernekar { 235941f79bdeSSantosh Vernekar uint32_t *data_ptr = *d_ptr; 236041f79bdeSSantosh Vernekar int rval = QLA_SUCCESS; 236141f79bdeSSantosh Vernekar 236241f79bdeSSantosh Vernekar if (is_qla8032(ha) || is_qla8042(ha)) { 236341f79bdeSSantosh Vernekar rval = qla4_83xx_minidump_pex_dma_read(ha, entry_hdr, 236441f79bdeSSantosh Vernekar &data_ptr); 236541f79bdeSSantosh Vernekar if (rval != QLA_SUCCESS) { 236641f79bdeSSantosh Vernekar rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 236741f79bdeSSantosh Vernekar &data_ptr); 236841f79bdeSSantosh Vernekar } 236941f79bdeSSantosh Vernekar } else { 237041f79bdeSSantosh Vernekar rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 237141f79bdeSSantosh Vernekar &data_ptr); 237241f79bdeSSantosh Vernekar } 237341f79bdeSSantosh Vernekar *d_ptr = data_ptr; 237441f79bdeSSantosh Vernekar return rval; 237541f79bdeSSantosh Vernekar } 237641f79bdeSSantosh Vernekar 23775e9bcec7SVikas Chaudhary static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha, 23787664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2379068237c8STej Parkash int index) 2380068237c8STej Parkash { 2381de8c72daSVikas Chaudhary entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG; 2382068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2383068237c8STej Parkash "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", 2384068237c8STej Parkash ha->host_no, index, entry_hdr->entry_type, 2385068237c8STej Parkash entry_hdr->d_ctrl.entry_capture_mask)); 2386068237c8STej Parkash } 2387068237c8STej Parkash 23886e7b4292SVikas Chaudhary /* ISP83xx functions to process new minidump entries... */ 23896e7b4292SVikas Chaudhary static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha, 23906e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 23916e7b4292SVikas Chaudhary uint32_t **d_ptr) 23926e7b4292SVikas Chaudhary { 23936e7b4292SVikas Chaudhary uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; 23946e7b4292SVikas Chaudhary uint16_t s_stride, i; 23956e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 23966e7b4292SVikas Chaudhary uint32_t rval = QLA_SUCCESS; 23976e7b4292SVikas Chaudhary struct qla83xx_minidump_entry_pollrd *pollrd_hdr; 23986e7b4292SVikas Chaudhary 23996e7b4292SVikas Chaudhary pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr; 24006e7b4292SVikas Chaudhary s_addr = le32_to_cpu(pollrd_hdr->select_addr); 24016e7b4292SVikas Chaudhary r_addr = le32_to_cpu(pollrd_hdr->read_addr); 24026e7b4292SVikas Chaudhary s_value = le32_to_cpu(pollrd_hdr->select_value); 24036e7b4292SVikas Chaudhary s_stride = le32_to_cpu(pollrd_hdr->select_value_stride); 24046e7b4292SVikas Chaudhary 24056e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); 24066e7b4292SVikas Chaudhary poll_mask = le32_to_cpu(pollrd_hdr->poll_mask); 24076e7b4292SVikas Chaudhary 24086e7b4292SVikas Chaudhary for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) { 24096e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); 24106e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); 24116e7b4292SVikas Chaudhary while (1) { 24126e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value); 24136e7b4292SVikas Chaudhary 24146e7b4292SVikas Chaudhary if ((r_value & poll_mask) != 0) { 24156e7b4292SVikas Chaudhary break; 24166e7b4292SVikas Chaudhary } else { 24176e7b4292SVikas Chaudhary msleep(1); 24186e7b4292SVikas Chaudhary if (--poll_wait == 0) { 24196e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", 24206e7b4292SVikas Chaudhary __func__); 24216e7b4292SVikas Chaudhary rval = QLA_ERROR; 24226e7b4292SVikas Chaudhary goto exit_process_pollrd; 24236e7b4292SVikas Chaudhary } 24246e7b4292SVikas Chaudhary } 24256e7b4292SVikas Chaudhary } 24266e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 24276e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(s_value); 24286e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(r_value); 24296e7b4292SVikas Chaudhary s_value += s_stride; 24306e7b4292SVikas Chaudhary } 24316e7b4292SVikas Chaudhary 24326e7b4292SVikas Chaudhary *d_ptr = data_ptr; 24336e7b4292SVikas Chaudhary 24346e7b4292SVikas Chaudhary exit_process_pollrd: 24356e7b4292SVikas Chaudhary return rval; 24366e7b4292SVikas Chaudhary } 24376e7b4292SVikas Chaudhary 24386e7b4292SVikas Chaudhary static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha, 24396e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 24406e7b4292SVikas Chaudhary uint32_t **d_ptr) 24416e7b4292SVikas Chaudhary { 24426e7b4292SVikas Chaudhary uint32_t sel_val1, sel_val2, t_sel_val, data, i; 24436e7b4292SVikas Chaudhary uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; 24446e7b4292SVikas Chaudhary struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr; 24456e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 24466e7b4292SVikas Chaudhary 24476e7b4292SVikas Chaudhary rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr; 24486e7b4292SVikas Chaudhary sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1); 24496e7b4292SVikas Chaudhary sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2); 24506e7b4292SVikas Chaudhary sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1); 24516e7b4292SVikas Chaudhary sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2); 24526e7b4292SVikas Chaudhary sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask); 24536e7b4292SVikas Chaudhary read_addr = le32_to_cpu(rdmux2_hdr->read_addr); 24546e7b4292SVikas Chaudhary 24556e7b4292SVikas Chaudhary for (i = 0; i < rdmux2_hdr->op_count; i++) { 24566e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1); 24576e7b4292SVikas Chaudhary t_sel_val = sel_val1 & sel_val_mask; 24586e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(t_sel_val); 24596e7b4292SVikas Chaudhary 24606e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); 24616e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); 24626e7b4292SVikas Chaudhary 24636e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(data); 24646e7b4292SVikas Chaudhary 24656e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2); 24666e7b4292SVikas Chaudhary t_sel_val = sel_val2 & sel_val_mask; 24676e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(t_sel_val); 24686e7b4292SVikas Chaudhary 24696e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); 24706e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); 24716e7b4292SVikas Chaudhary 24726e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(data); 24736e7b4292SVikas Chaudhary 24746e7b4292SVikas Chaudhary sel_val1 += rdmux2_hdr->select_value_stride; 24756e7b4292SVikas Chaudhary sel_val2 += rdmux2_hdr->select_value_stride; 24766e7b4292SVikas Chaudhary } 24776e7b4292SVikas Chaudhary 24786e7b4292SVikas Chaudhary *d_ptr = data_ptr; 24796e7b4292SVikas Chaudhary } 24806e7b4292SVikas Chaudhary 24816e7b4292SVikas Chaudhary static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha, 24826e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 24836e7b4292SVikas Chaudhary uint32_t **d_ptr) 24846e7b4292SVikas Chaudhary { 24856e7b4292SVikas Chaudhary uint32_t poll_wait, poll_mask, r_value, data; 24866e7b4292SVikas Chaudhary uint32_t addr_1, addr_2, value_1, value_2; 24876e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 24886e7b4292SVikas Chaudhary uint32_t rval = QLA_SUCCESS; 24896e7b4292SVikas Chaudhary struct qla83xx_minidump_entry_pollrdmwr *poll_hdr; 24906e7b4292SVikas Chaudhary 24916e7b4292SVikas Chaudhary poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr; 24926e7b4292SVikas Chaudhary addr_1 = le32_to_cpu(poll_hdr->addr_1); 24936e7b4292SVikas Chaudhary addr_2 = le32_to_cpu(poll_hdr->addr_2); 24946e7b4292SVikas Chaudhary value_1 = le32_to_cpu(poll_hdr->value_1); 24956e7b4292SVikas Chaudhary value_2 = le32_to_cpu(poll_hdr->value_2); 24966e7b4292SVikas Chaudhary poll_mask = le32_to_cpu(poll_hdr->poll_mask); 24976e7b4292SVikas Chaudhary 24986e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1); 24996e7b4292SVikas Chaudhary 25006e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(poll_hdr->poll_wait); 25016e7b4292SVikas Chaudhary while (1) { 25026e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); 25036e7b4292SVikas Chaudhary 25046e7b4292SVikas Chaudhary if ((r_value & poll_mask) != 0) { 25056e7b4292SVikas Chaudhary break; 25066e7b4292SVikas Chaudhary } else { 25076e7b4292SVikas Chaudhary msleep(1); 25086e7b4292SVikas Chaudhary if (--poll_wait == 0) { 25096e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n", 25106e7b4292SVikas Chaudhary __func__); 25116e7b4292SVikas Chaudhary rval = QLA_ERROR; 25126e7b4292SVikas Chaudhary goto exit_process_pollrdmwr; 25136e7b4292SVikas Chaudhary } 25146e7b4292SVikas Chaudhary } 25156e7b4292SVikas Chaudhary } 25166e7b4292SVikas Chaudhary 25176e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr_2, &data); 25186e7b4292SVikas Chaudhary data &= le32_to_cpu(poll_hdr->modify_mask); 25196e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr_2, data); 25206e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2); 25216e7b4292SVikas Chaudhary 25226e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(poll_hdr->poll_wait); 25236e7b4292SVikas Chaudhary while (1) { 25246e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); 25256e7b4292SVikas Chaudhary 25266e7b4292SVikas Chaudhary if ((r_value & poll_mask) != 0) { 25276e7b4292SVikas Chaudhary break; 25286e7b4292SVikas Chaudhary } else { 25296e7b4292SVikas Chaudhary msleep(1); 25306e7b4292SVikas Chaudhary if (--poll_wait == 0) { 25316e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n", 25326e7b4292SVikas Chaudhary __func__); 25336e7b4292SVikas Chaudhary rval = QLA_ERROR; 25346e7b4292SVikas Chaudhary goto exit_process_pollrdmwr; 25356e7b4292SVikas Chaudhary } 25366e7b4292SVikas Chaudhary } 25376e7b4292SVikas Chaudhary } 25386e7b4292SVikas Chaudhary 25396e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(addr_2); 25406e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(data); 25416e7b4292SVikas Chaudhary *d_ptr = data_ptr; 25426e7b4292SVikas Chaudhary 25436e7b4292SVikas Chaudhary exit_process_pollrdmwr: 25446e7b4292SVikas Chaudhary return rval; 25456e7b4292SVikas Chaudhary } 25466e7b4292SVikas Chaudhary 25476e7b4292SVikas Chaudhary static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha, 25486e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 25496e7b4292SVikas Chaudhary uint32_t **d_ptr) 25506e7b4292SVikas Chaudhary { 25516e7b4292SVikas Chaudhary uint32_t fl_addr, u32_count, rval; 25526e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_rdrom *rom_hdr; 25536e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 25546e7b4292SVikas Chaudhary 25556e7b4292SVikas Chaudhary rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; 25566e7b4292SVikas Chaudhary fl_addr = le32_to_cpu(rom_hdr->read_addr); 25576e7b4292SVikas Chaudhary u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t); 25586e7b4292SVikas Chaudhary 25596e7b4292SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n", 25606e7b4292SVikas Chaudhary __func__, fl_addr, u32_count)); 25616e7b4292SVikas Chaudhary 25626e7b4292SVikas Chaudhary rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr, 25636e7b4292SVikas Chaudhary (u8 *)(data_ptr), u32_count); 25646e7b4292SVikas Chaudhary 25656e7b4292SVikas Chaudhary if (rval == QLA_ERROR) { 25666e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n", 25676e7b4292SVikas Chaudhary __func__, u32_count); 25686e7b4292SVikas Chaudhary goto exit_process_rdrom; 25696e7b4292SVikas Chaudhary } 25706e7b4292SVikas Chaudhary 25716e7b4292SVikas Chaudhary data_ptr += u32_count; 25726e7b4292SVikas Chaudhary *d_ptr = data_ptr; 25736e7b4292SVikas Chaudhary 25746e7b4292SVikas Chaudhary exit_process_rdrom: 25756e7b4292SVikas Chaudhary return rval; 25766e7b4292SVikas Chaudhary } 25776e7b4292SVikas Chaudhary 2578068237c8STej Parkash /** 2579f8086f4fSVikas Chaudhary * qla4_8xxx_collect_md_data - Retrieve firmware minidump data. 2580068237c8STej Parkash * @ha: pointer to adapter structure 2581068237c8STej Parkash **/ 2582068237c8STej Parkash static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) 2583068237c8STej Parkash { 2584068237c8STej Parkash int num_entry_hdr = 0; 25857664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr; 2586068237c8STej Parkash struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 2587068237c8STej Parkash uint32_t *data_ptr; 2588068237c8STej Parkash uint32_t data_collected = 0; 2589068237c8STej Parkash int i, rval = QLA_ERROR; 2590068237c8STej Parkash uint64_t now; 2591068237c8STej Parkash uint32_t timestamp; 2592068237c8STej Parkash 2593068237c8STej Parkash if (!ha->fw_dump) { 2594068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n", 2595068237c8STej Parkash __func__, ha->host_no); 2596068237c8STej Parkash return rval; 2597068237c8STej Parkash } 2598068237c8STej Parkash 2599068237c8STej Parkash tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 2600068237c8STej Parkash ha->fw_dump_tmplt_hdr; 2601068237c8STej Parkash data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump + 2602068237c8STej Parkash ha->fw_dump_tmplt_size); 2603068237c8STej Parkash data_collected += ha->fw_dump_tmplt_size; 2604068237c8STej Parkash 2605068237c8STej Parkash num_entry_hdr = tmplt_hdr->num_of_entries; 2606068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n", 2607068237c8STej Parkash __func__, data_ptr); 2608068237c8STej Parkash ql4_printk(KERN_INFO, ha, 2609068237c8STej Parkash "[%s]: no of entry headers in Template: 0x%x\n", 2610068237c8STej Parkash __func__, num_entry_hdr); 2611068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n", 2612068237c8STej Parkash __func__, ha->fw_dump_capture_mask); 2613068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n", 2614068237c8STej Parkash __func__, ha->fw_dump_size, ha->fw_dump_size); 2615068237c8STej Parkash 2616068237c8STej Parkash /* Update current timestamp before taking dump */ 2617068237c8STej Parkash now = get_jiffies_64(); 2618068237c8STej Parkash timestamp = (u32)(jiffies_to_msecs(now) / 1000); 2619068237c8STej Parkash tmplt_hdr->driver_timestamp = timestamp; 2620068237c8STej Parkash 26217664a1fdSVikas Chaudhary entry_hdr = (struct qla8xxx_minidump_entry_hdr *) 2622068237c8STej Parkash (((uint8_t *)ha->fw_dump_tmplt_hdr) + 2623068237c8STej Parkash tmplt_hdr->first_entry_offset); 2624068237c8STej Parkash 2625b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 26266e7b4292SVikas Chaudhary tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] = 26276e7b4292SVikas Chaudhary tmplt_hdr->ocm_window_reg[ha->func_num]; 26286e7b4292SVikas Chaudhary 2629068237c8STej Parkash /* Walk through the entry headers - validate/perform required action */ 2630068237c8STej Parkash for (i = 0; i < num_entry_hdr; i++) { 2631068237c8STej Parkash if (data_collected >= ha->fw_dump_size) { 2632068237c8STej Parkash ql4_printk(KERN_INFO, ha, 2633068237c8STej Parkash "Data collected: [0x%x], Total Dump size: [0x%x]\n", 2634068237c8STej Parkash data_collected, ha->fw_dump_size); 2635068237c8STej Parkash return rval; 2636068237c8STej Parkash } 2637068237c8STej Parkash 2638068237c8STej Parkash if (!(entry_hdr->d_ctrl.entry_capture_mask & 2639068237c8STej Parkash ha->fw_dump_capture_mask)) { 2640068237c8STej Parkash entry_hdr->d_ctrl.driver_flags |= 2641de8c72daSVikas Chaudhary QLA8XXX_DBG_SKIPPED_FLAG; 2642068237c8STej Parkash goto skip_nxt_entry; 2643068237c8STej Parkash } 2644068237c8STej Parkash 2645068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2646068237c8STej Parkash "Data collected: [0x%x], Dump size left:[0x%x]\n", 2647068237c8STej Parkash data_collected, 2648068237c8STej Parkash (ha->fw_dump_size - data_collected))); 2649068237c8STej Parkash 2650068237c8STej Parkash /* Decode the entry type and take required action to capture 2651068237c8STej Parkash * debug data 2652068237c8STej Parkash */ 2653068237c8STej Parkash switch (entry_hdr->entry_type) { 2654de8c72daSVikas Chaudhary case QLA8XXX_RDEND: 26555e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2656068237c8STej Parkash break; 2657de8c72daSVikas Chaudhary case QLA8XXX_CNTRL: 2658068237c8STej Parkash rval = qla4_8xxx_minidump_process_control(ha, 2659068237c8STej Parkash entry_hdr); 2660068237c8STej Parkash if (rval != QLA_SUCCESS) { 26615e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2662068237c8STej Parkash goto md_failed; 2663068237c8STej Parkash } 2664068237c8STej Parkash break; 2665de8c72daSVikas Chaudhary case QLA8XXX_RDCRB: 2666068237c8STej Parkash qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, 2667068237c8STej Parkash &data_ptr); 2668068237c8STej Parkash break; 2669de8c72daSVikas Chaudhary case QLA8XXX_RDMEM: 2670068237c8STej Parkash rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 2671068237c8STej Parkash &data_ptr); 2672068237c8STej Parkash if (rval != QLA_SUCCESS) { 26735e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2674068237c8STej Parkash goto md_failed; 2675068237c8STej Parkash } 2676068237c8STej Parkash break; 2677de8c72daSVikas Chaudhary case QLA8XXX_BOARD: 2678de8c72daSVikas Chaudhary case QLA8XXX_RDROM: 26796e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 2680f8086f4fSVikas Chaudhary qla4_82xx_minidump_process_rdrom(ha, entry_hdr, 2681068237c8STej Parkash &data_ptr); 2682b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 26836e7b4292SVikas Chaudhary rval = qla4_83xx_minidump_process_rdrom(ha, 26846e7b4292SVikas Chaudhary entry_hdr, 26856e7b4292SVikas Chaudhary &data_ptr); 26866e7b4292SVikas Chaudhary if (rval != QLA_SUCCESS) 26876e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, 26886e7b4292SVikas Chaudhary entry_hdr, 26896e7b4292SVikas Chaudhary i); 26906e7b4292SVikas Chaudhary } 2691068237c8STej Parkash break; 2692de8c72daSVikas Chaudhary case QLA8XXX_L2DTG: 2693de8c72daSVikas Chaudhary case QLA8XXX_L2ITG: 2694de8c72daSVikas Chaudhary case QLA8XXX_L2DAT: 2695de8c72daSVikas Chaudhary case QLA8XXX_L2INS: 2696068237c8STej Parkash rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, 2697068237c8STej Parkash &data_ptr); 2698068237c8STej Parkash if (rval != QLA_SUCCESS) { 26995e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2700068237c8STej Parkash goto md_failed; 2701068237c8STej Parkash } 2702068237c8STej Parkash break; 27036e7b4292SVikas Chaudhary case QLA8XXX_L1DTG: 27046e7b4292SVikas Chaudhary case QLA8XXX_L1ITG: 2705de8c72daSVikas Chaudhary case QLA8XXX_L1DAT: 2706de8c72daSVikas Chaudhary case QLA8XXX_L1INS: 2707068237c8STej Parkash qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, 2708068237c8STej Parkash &data_ptr); 2709068237c8STej Parkash break; 2710de8c72daSVikas Chaudhary case QLA8XXX_RDOCM: 2711068237c8STej Parkash qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, 2712068237c8STej Parkash &data_ptr); 2713068237c8STej Parkash break; 2714de8c72daSVikas Chaudhary case QLA8XXX_RDMUX: 2715068237c8STej Parkash qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, 2716068237c8STej Parkash &data_ptr); 2717068237c8STej Parkash break; 2718de8c72daSVikas Chaudhary case QLA8XXX_QUEUE: 2719068237c8STej Parkash qla4_8xxx_minidump_process_queue(ha, entry_hdr, 2720068237c8STej Parkash &data_ptr); 2721068237c8STej Parkash break; 27226e7b4292SVikas Chaudhary case QLA83XX_POLLRD: 2723b37ca418SVikas Chaudhary if (is_qla8022(ha)) { 27246e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 27256e7b4292SVikas Chaudhary break; 27266e7b4292SVikas Chaudhary } 27276e7b4292SVikas Chaudhary rval = qla83xx_minidump_process_pollrd(ha, entry_hdr, 27286e7b4292SVikas Chaudhary &data_ptr); 27296e7b4292SVikas Chaudhary if (rval != QLA_SUCCESS) 27306e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 27316e7b4292SVikas Chaudhary break; 27326e7b4292SVikas Chaudhary case QLA83XX_RDMUX2: 2733b37ca418SVikas Chaudhary if (is_qla8022(ha)) { 27346e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 27356e7b4292SVikas Chaudhary break; 27366e7b4292SVikas Chaudhary } 27376e7b4292SVikas Chaudhary qla83xx_minidump_process_rdmux2(ha, entry_hdr, 27386e7b4292SVikas Chaudhary &data_ptr); 27396e7b4292SVikas Chaudhary break; 27406e7b4292SVikas Chaudhary case QLA83XX_POLLRDMWR: 2741b37ca418SVikas Chaudhary if (is_qla8022(ha)) { 27426e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 27436e7b4292SVikas Chaudhary break; 27446e7b4292SVikas Chaudhary } 27456e7b4292SVikas Chaudhary rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr, 27466e7b4292SVikas Chaudhary &data_ptr); 27476e7b4292SVikas Chaudhary if (rval != QLA_SUCCESS) 27486e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 27496e7b4292SVikas Chaudhary break; 2750de8c72daSVikas Chaudhary case QLA8XXX_RDNOP: 2751068237c8STej Parkash default: 27525e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 2753068237c8STej Parkash break; 2754068237c8STej Parkash } 2755068237c8STej Parkash 2756068237c8STej Parkash data_collected = (uint8_t *)data_ptr - 2757068237c8STej Parkash ((uint8_t *)((uint8_t *)ha->fw_dump + 2758068237c8STej Parkash ha->fw_dump_tmplt_size)); 2759068237c8STej Parkash skip_nxt_entry: 2760068237c8STej Parkash /* next entry in the template */ 27617664a1fdSVikas Chaudhary entry_hdr = (struct qla8xxx_minidump_entry_hdr *) 2762068237c8STej Parkash (((uint8_t *)entry_hdr) + 2763068237c8STej Parkash entry_hdr->entry_size); 2764068237c8STej Parkash } 2765068237c8STej Parkash 2766068237c8STej Parkash if ((data_collected + ha->fw_dump_tmplt_size) != ha->fw_dump_size) { 2767068237c8STej Parkash ql4_printk(KERN_INFO, ha, 2768068237c8STej Parkash "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n", 2769068237c8STej Parkash data_collected, ha->fw_dump_size); 2770068237c8STej Parkash goto md_failed; 2771068237c8STej Parkash } 2772068237c8STej Parkash 2773068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n", 2774068237c8STej Parkash __func__, i)); 2775068237c8STej Parkash md_failed: 2776068237c8STej Parkash return rval; 2777068237c8STej Parkash } 2778068237c8STej Parkash 2779068237c8STej Parkash /** 2780068237c8STej Parkash * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready. 2781068237c8STej Parkash * @ha: pointer to adapter structure 2782068237c8STej Parkash **/ 2783068237c8STej Parkash static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code) 2784068237c8STej Parkash { 2785068237c8STej Parkash char event_string[40]; 2786068237c8STej Parkash char *envp[] = { event_string, NULL }; 2787068237c8STej Parkash 2788068237c8STej Parkash switch (code) { 2789068237c8STej Parkash case QL4_UEVENT_CODE_FW_DUMP: 2790068237c8STej Parkash snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 2791068237c8STej Parkash ha->host_no); 2792068237c8STej Parkash break; 2793068237c8STej Parkash default: 2794068237c8STej Parkash /*do nothing*/ 2795068237c8STej Parkash break; 2796068237c8STej Parkash } 2797068237c8STej Parkash 2798068237c8STej Parkash kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp); 2799068237c8STej Parkash } 2800068237c8STej Parkash 28016e7b4292SVikas Chaudhary void qla4_8xxx_get_minidump(struct scsi_qla_host *ha) 2802aec07caeSVikas Chaudhary { 2803aec07caeSVikas Chaudhary if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) && 2804aec07caeSVikas Chaudhary !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) { 2805aec07caeSVikas Chaudhary if (!qla4_8xxx_collect_md_data(ha)) { 2806aec07caeSVikas Chaudhary qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP); 2807aec07caeSVikas Chaudhary set_bit(AF_82XX_FW_DUMPED, &ha->flags); 2808aec07caeSVikas Chaudhary } else { 2809aec07caeSVikas Chaudhary ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n", 2810aec07caeSVikas Chaudhary __func__); 2811aec07caeSVikas Chaudhary } 2812aec07caeSVikas Chaudhary } 2813aec07caeSVikas Chaudhary } 2814aec07caeSVikas Chaudhary 2815f4f5df23SVikas Chaudhary /** 2816f4f5df23SVikas Chaudhary * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw 2817f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 2818f4f5df23SVikas Chaudhary * 2819f4f5df23SVikas Chaudhary * Note: IDC lock must be held upon entry 2820f4f5df23SVikas Chaudhary **/ 28216e7b4292SVikas Chaudhary int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) 2822f4f5df23SVikas Chaudhary { 2823b25ee66fSShyam Sundar int rval = QLA_ERROR; 2824b25ee66fSShyam Sundar int i, timeout; 28256e7b4292SVikas Chaudhary uint32_t old_count, count, idc_ctrl; 2826b25ee66fSShyam Sundar int need_reset = 0, peg_stuck = 1; 2827f4f5df23SVikas Chaudhary 282833693c7aSVikas Chaudhary need_reset = ha->isp_ops->need_reset(ha); 282933693c7aSVikas Chaudhary old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER); 2830f4f5df23SVikas Chaudhary 2831f4f5df23SVikas Chaudhary for (i = 0; i < 10; i++) { 2832f4f5df23SVikas Chaudhary timeout = msleep_interruptible(200); 2833f4f5df23SVikas Chaudhary if (timeout) { 283433693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 2835de8c72daSVikas Chaudhary QLA8XXX_DEV_FAILED); 2836b25ee66fSShyam Sundar return rval; 2837f4f5df23SVikas Chaudhary } 2838f4f5df23SVikas Chaudhary 283933693c7aSVikas Chaudhary count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER); 2840f4f5df23SVikas Chaudhary if (count != old_count) 2841b25ee66fSShyam Sundar peg_stuck = 0; 2842b25ee66fSShyam Sundar } 2843b25ee66fSShyam Sundar 2844b25ee66fSShyam Sundar if (need_reset) { 2845b25ee66fSShyam Sundar /* We are trying to perform a recovery here. */ 2846b25ee66fSShyam Sundar if (peg_stuck) 284733693c7aSVikas Chaudhary ha->isp_ops->rom_lock_recovery(ha); 2848b25ee66fSShyam Sundar goto dev_initialize; 2849b25ee66fSShyam Sundar } else { 2850b25ee66fSShyam Sundar /* Start of day for this ha context. */ 2851b25ee66fSShyam Sundar if (peg_stuck) { 2852b25ee66fSShyam Sundar /* Either we are the first or recovery in progress. */ 285333693c7aSVikas Chaudhary ha->isp_ops->rom_lock_recovery(ha); 2854b25ee66fSShyam Sundar goto dev_initialize; 2855b25ee66fSShyam Sundar } else { 2856b25ee66fSShyam Sundar /* Firmware already running. */ 2857b25ee66fSShyam Sundar rval = QLA_SUCCESS; 2858f4f5df23SVikas Chaudhary goto dev_ready; 2859f4f5df23SVikas Chaudhary } 2860b25ee66fSShyam Sundar } 2861f4f5df23SVikas Chaudhary 2862f4f5df23SVikas Chaudhary dev_initialize: 2863f4f5df23SVikas Chaudhary /* set to DEV_INITIALIZING */ 2864f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 286533693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 286633693c7aSVikas Chaudhary QLA8XXX_DEV_INITIALIZING); 2867f4f5df23SVikas Chaudhary 28686e7b4292SVikas Chaudhary /* 2869b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, if IDC_CTRL GRACEFUL_RESET_BIT1 is set, 2870b37ca418SVikas Chaudhary * reset it after device goes to INIT state. 28716e7b4292SVikas Chaudhary */ 2872b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) { 28736e7b4292SVikas Chaudhary idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL); 28746e7b4292SVikas Chaudhary if (idc_ctrl & GRACEFUL_RESET_BIT1) { 28756e7b4292SVikas Chaudhary qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, 28766e7b4292SVikas Chaudhary (idc_ctrl & ~GRACEFUL_RESET_BIT1)); 28776e7b4292SVikas Chaudhary set_bit(AF_83XX_NO_FW_DUMP, &ha->flags); 2878068237c8STej Parkash } 2879068237c8STej Parkash } 28806e7b4292SVikas Chaudhary 288133693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 28826e7b4292SVikas Chaudhary 28836e7b4292SVikas Chaudhary if (is_qla8022(ha)) 2884aec07caeSVikas Chaudhary qla4_8xxx_get_minidump(ha); 28856e7b4292SVikas Chaudhary 288633693c7aSVikas Chaudhary rval = ha->isp_ops->restart_firmware(ha); 288733693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 2888f4f5df23SVikas Chaudhary 2889f4f5df23SVikas Chaudhary if (rval != QLA_SUCCESS) { 2890f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 2891f4f5df23SVikas Chaudhary qla4_8xxx_clear_drv_active(ha); 289233693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 289333693c7aSVikas Chaudhary QLA8XXX_DEV_FAILED); 2894f4f5df23SVikas Chaudhary return rval; 2895f4f5df23SVikas Chaudhary } 2896f4f5df23SVikas Chaudhary 2897f4f5df23SVikas Chaudhary dev_ready: 2898f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 289933693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 2900f4f5df23SVikas Chaudhary 2901b25ee66fSShyam Sundar return rval; 2902f4f5df23SVikas Chaudhary } 2903f4f5df23SVikas Chaudhary 2904f4f5df23SVikas Chaudhary /** 2905f8086f4fSVikas Chaudhary * qla4_82xx_need_reset_handler - Code to start reset sequence 2906f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 2907f4f5df23SVikas Chaudhary * 2908f4f5df23SVikas Chaudhary * Note: IDC lock must be held upon entry 2909f4f5df23SVikas Chaudhary **/ 2910f4f5df23SVikas Chaudhary static void 2911f8086f4fSVikas Chaudhary qla4_82xx_need_reset_handler(struct scsi_qla_host *ha) 2912f4f5df23SVikas Chaudhary { 2913f4f5df23SVikas Chaudhary uint32_t dev_state, drv_state, drv_active; 2914068237c8STej Parkash uint32_t active_mask = 0xFFFFFFFF; 2915f4f5df23SVikas Chaudhary unsigned long reset_timeout; 2916f4f5df23SVikas Chaudhary 2917f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 2918f4f5df23SVikas Chaudhary "Performing ISP error recovery\n"); 2919f4f5df23SVikas Chaudhary 2920f4f5df23SVikas Chaudhary if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { 2921f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2922f4f5df23SVikas Chaudhary ha->isp_ops->disable_intrs(ha); 2923f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2924f4f5df23SVikas Chaudhary } 2925f4f5df23SVikas Chaudhary 2926de8c72daSVikas Chaudhary if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { 2927068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2928068237c8STej Parkash "%s(%ld): reset acknowledged\n", 2929068237c8STej Parkash __func__, ha->host_no)); 2930f4f5df23SVikas Chaudhary qla4_8xxx_set_rst_ready(ha); 2931068237c8STej Parkash } else { 2932068237c8STej Parkash active_mask = (~(1 << (ha->func_num * 4))); 2933068237c8STej Parkash } 2934f4f5df23SVikas Chaudhary 2935f4f5df23SVikas Chaudhary /* wait for 10 seconds for reset ack from all functions */ 2936f4f5df23SVikas Chaudhary reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 2937f4f5df23SVikas Chaudhary 2938f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2939f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2940f4f5df23SVikas Chaudhary 2941f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 2942f4f5df23SVikas Chaudhary "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 2943f4f5df23SVikas Chaudhary __func__, ha->host_no, drv_state, drv_active); 2944f4f5df23SVikas Chaudhary 2945068237c8STej Parkash while (drv_state != (drv_active & active_mask)) { 2946f4f5df23SVikas Chaudhary if (time_after_eq(jiffies, reset_timeout)) { 2947068237c8STej Parkash ql4_printk(KERN_INFO, ha, 2948068237c8STej Parkash "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", 2949068237c8STej Parkash DRIVER_NAME, drv_state, drv_active); 2950f4f5df23SVikas Chaudhary break; 2951f4f5df23SVikas Chaudhary } 2952f4f5df23SVikas Chaudhary 2953068237c8STej Parkash /* 2954068237c8STej Parkash * When reset_owner times out, check which functions 2955068237c8STej Parkash * acked/did not ack 2956068237c8STej Parkash */ 2957de8c72daSVikas Chaudhary if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { 2958068237c8STej Parkash ql4_printk(KERN_INFO, ha, 2959068237c8STej Parkash "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 2960068237c8STej Parkash __func__, ha->host_no, drv_state, 2961068237c8STej Parkash drv_active); 2962068237c8STej Parkash } 2963f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 2964f4f5df23SVikas Chaudhary msleep(1000); 2965f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 2966f4f5df23SVikas Chaudhary 2967f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 2968f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 2969f4f5df23SVikas Chaudhary } 2970f4f5df23SVikas Chaudhary 2971068237c8STej Parkash /* Clear RESET OWNER as we are not going to use it any further */ 2972de8c72daSVikas Chaudhary clear_bit(AF_8XXX_RST_OWNER, &ha->flags); 2973068237c8STej Parkash 2974f8086f4fSVikas Chaudhary dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2975068237c8STej Parkash ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, 2976f4f5df23SVikas Chaudhary dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 2977f4f5df23SVikas Chaudhary 2978f4f5df23SVikas Chaudhary /* Force to DEV_COLD unless someone else is starting a reset */ 2979de8c72daSVikas Chaudhary if (dev_state != QLA8XXX_DEV_INITIALIZING) { 2980f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 2981de8c72daSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 2982068237c8STej Parkash qla4_8xxx_set_rst_ready(ha); 2983f4f5df23SVikas Chaudhary } 2984f4f5df23SVikas Chaudhary } 2985f4f5df23SVikas Chaudhary 2986f4f5df23SVikas Chaudhary /** 2987f4f5df23SVikas Chaudhary * qla4_8xxx_need_qsnt_handler - Code to start qsnt 2988f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 2989f4f5df23SVikas Chaudhary **/ 2990f4f5df23SVikas Chaudhary void 2991f4f5df23SVikas Chaudhary qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 2992f4f5df23SVikas Chaudhary { 299333693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 2994f4f5df23SVikas Chaudhary qla4_8xxx_set_qsnt_ready(ha); 299533693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 2996f4f5df23SVikas Chaudhary } 2997f4f5df23SVikas Chaudhary 299883dbdf6fSVikas Chaudhary static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha) 299983dbdf6fSVikas Chaudhary { 300083dbdf6fSVikas Chaudhary int idc_ver; 300183dbdf6fSVikas Chaudhary uint32_t drv_active; 300283dbdf6fSVikas Chaudhary 300383dbdf6fSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 300483dbdf6fSVikas Chaudhary if (drv_active == (1 << (ha->func_num * 4))) { 300583dbdf6fSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, 300683dbdf6fSVikas Chaudhary QLA82XX_IDC_VERSION); 300783dbdf6fSVikas Chaudhary ql4_printk(KERN_INFO, ha, 300883dbdf6fSVikas Chaudhary "%s: IDC version updated to %d\n", __func__, 300983dbdf6fSVikas Chaudhary QLA82XX_IDC_VERSION); 301083dbdf6fSVikas Chaudhary } else { 301183dbdf6fSVikas Chaudhary idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 301283dbdf6fSVikas Chaudhary if (QLA82XX_IDC_VERSION != idc_ver) { 301383dbdf6fSVikas Chaudhary ql4_printk(KERN_INFO, ha, 301483dbdf6fSVikas Chaudhary "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", 301583dbdf6fSVikas Chaudhary __func__, QLA82XX_IDC_VERSION, idc_ver); 301683dbdf6fSVikas Chaudhary } 301783dbdf6fSVikas Chaudhary } 301883dbdf6fSVikas Chaudhary } 301983dbdf6fSVikas Chaudhary 30206e7b4292SVikas Chaudhary static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha) 302183dbdf6fSVikas Chaudhary { 30226e7b4292SVikas Chaudhary int idc_ver; 30236e7b4292SVikas Chaudhary uint32_t drv_active; 30246e7b4292SVikas Chaudhary int rval = QLA_SUCCESS; 30256e7b4292SVikas Chaudhary 30266e7b4292SVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 30276e7b4292SVikas Chaudhary if (drv_active == (1 << ha->func_num)) { 30286e7b4292SVikas Chaudhary idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 30296e7b4292SVikas Chaudhary idc_ver &= (~0xFF); 30306e7b4292SVikas Chaudhary idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE; 30316e7b4292SVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver); 30326e7b4292SVikas Chaudhary ql4_printk(KERN_INFO, ha, 30336e7b4292SVikas Chaudhary "%s: IDC version updated to %d\n", __func__, 3034ecca5120SVikas Chaudhary idc_ver); 30356e7b4292SVikas Chaudhary } else { 30366e7b4292SVikas Chaudhary idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 30376e7b4292SVikas Chaudhary idc_ver &= 0xFF; 30386e7b4292SVikas Chaudhary if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) { 30396e7b4292SVikas Chaudhary ql4_printk(KERN_INFO, ha, 30406e7b4292SVikas Chaudhary "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", 30416e7b4292SVikas Chaudhary __func__, QLA83XX_IDC_VER_MAJ_VALUE, 30426e7b4292SVikas Chaudhary idc_ver); 30436e7b4292SVikas Chaudhary rval = QLA_ERROR; 30446e7b4292SVikas Chaudhary goto exit_set_idc_ver; 30456e7b4292SVikas Chaudhary } 30466e7b4292SVikas Chaudhary } 30476e7b4292SVikas Chaudhary 30486e7b4292SVikas Chaudhary /* Update IDC_MINOR_VERSION */ 30496e7b4292SVikas Chaudhary idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR); 30506e7b4292SVikas Chaudhary idc_ver &= ~(0x03 << (ha->func_num * 2)); 30516e7b4292SVikas Chaudhary idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2)); 30526e7b4292SVikas Chaudhary qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver); 30536e7b4292SVikas Chaudhary 30546e7b4292SVikas Chaudhary exit_set_idc_ver: 30556e7b4292SVikas Chaudhary return rval; 30566e7b4292SVikas Chaudhary } 30576e7b4292SVikas Chaudhary 305839c95826SVikas Chaudhary int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha) 30596e7b4292SVikas Chaudhary { 30606e7b4292SVikas Chaudhary uint32_t drv_active; 30616e7b4292SVikas Chaudhary int rval = QLA_SUCCESS; 30626e7b4292SVikas Chaudhary 30636e7b4292SVikas Chaudhary if (test_bit(AF_INIT_DONE, &ha->flags)) 30646e7b4292SVikas Chaudhary goto exit_update_idc_reg; 30656e7b4292SVikas Chaudhary 306683dbdf6fSVikas Chaudhary ha->isp_ops->idc_lock(ha); 306783dbdf6fSVikas Chaudhary qla4_8xxx_set_drv_active(ha); 30686e7b4292SVikas Chaudhary 30696e7b4292SVikas Chaudhary /* 30706e7b4292SVikas Chaudhary * If we are the first driver to load and 30716e7b4292SVikas Chaudhary * ql4xdontresethba is not set, clear IDC_CTRL BIT0. 30726e7b4292SVikas Chaudhary */ 3073b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) { 30746e7b4292SVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 30756e7b4292SVikas Chaudhary if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba) 30766e7b4292SVikas Chaudhary qla4_83xx_clear_idc_dontreset(ha); 307783dbdf6fSVikas Chaudhary } 30786e7b4292SVikas Chaudhary 30796e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 30806e7b4292SVikas Chaudhary qla4_82xx_set_idc_ver(ha); 3081b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 30826e7b4292SVikas Chaudhary rval = qla4_83xx_set_idc_ver(ha); 30836e7b4292SVikas Chaudhary if (rval == QLA_ERROR) 30846e7b4292SVikas Chaudhary qla4_8xxx_clear_drv_active(ha); 30856e7b4292SVikas Chaudhary } 30866e7b4292SVikas Chaudhary 30876e7b4292SVikas Chaudhary ha->isp_ops->idc_unlock(ha); 30886e7b4292SVikas Chaudhary 30896e7b4292SVikas Chaudhary exit_update_idc_reg: 30906e7b4292SVikas Chaudhary return rval; 3091f4f5df23SVikas Chaudhary } 3092f4f5df23SVikas Chaudhary 3093f4f5df23SVikas Chaudhary /** 3094f4f5df23SVikas Chaudhary * qla4_8xxx_device_state_handler - Adapter state machine 3095f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 3096f4f5df23SVikas Chaudhary * 3097f4f5df23SVikas Chaudhary * Note: IDC lock must be UNLOCKED upon entry 3098f4f5df23SVikas Chaudhary **/ 3099f4f5df23SVikas Chaudhary int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) 3100f4f5df23SVikas Chaudhary { 3101f4f5df23SVikas Chaudhary uint32_t dev_state; 3102f4f5df23SVikas Chaudhary int rval = QLA_SUCCESS; 3103f4f5df23SVikas Chaudhary unsigned long dev_init_timeout; 3104f4f5df23SVikas Chaudhary 31056e7b4292SVikas Chaudhary rval = qla4_8xxx_update_idc_reg(ha); 31066e7b4292SVikas Chaudhary if (rval == QLA_ERROR) 31076e7b4292SVikas Chaudhary goto exit_state_handler; 3108f4f5df23SVikas Chaudhary 310933693c7aSVikas Chaudhary dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); 3110068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 3111068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 3112068237c8STej Parkash qdev_state[dev_state] : "Unknown")); 3113f4f5df23SVikas Chaudhary 3114f4f5df23SVikas Chaudhary /* wait for 30 seconds for device to go ready */ 3115f4f5df23SVikas Chaudhary dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3116f4f5df23SVikas Chaudhary 311733693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3118e3f37d16SNilesh Javali while (1) { 3119f4f5df23SVikas Chaudhary 3120f4f5df23SVikas Chaudhary if (time_after_eq(jiffies, dev_init_timeout)) { 3121068237c8STej Parkash ql4_printk(KERN_WARNING, ha, 3122068237c8STej Parkash "%s: Device Init Failed 0x%x = %s\n", 3123068237c8STej Parkash DRIVER_NAME, 3124068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 3125068237c8STej Parkash qdev_state[dev_state] : "Unknown"); 312633693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 3127de8c72daSVikas Chaudhary QLA8XXX_DEV_FAILED); 3128f4f5df23SVikas Chaudhary } 3129f4f5df23SVikas Chaudhary 313033693c7aSVikas Chaudhary dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); 3131068237c8STej Parkash ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 3132068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 3133068237c8STej Parkash qdev_state[dev_state] : "Unknown"); 3134f4f5df23SVikas Chaudhary 3135f4f5df23SVikas Chaudhary /* NOTE: Make sure idc unlocked upon exit of switch statement */ 3136f4f5df23SVikas Chaudhary switch (dev_state) { 3137de8c72daSVikas Chaudhary case QLA8XXX_DEV_READY: 3138f4f5df23SVikas Chaudhary goto exit; 3139de8c72daSVikas Chaudhary case QLA8XXX_DEV_COLD: 3140f4f5df23SVikas Chaudhary rval = qla4_8xxx_device_bootstrap(ha); 3141f4f5df23SVikas Chaudhary goto exit; 3142de8c72daSVikas Chaudhary case QLA8XXX_DEV_INITIALIZING: 314333693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3144f4f5df23SVikas Chaudhary msleep(1000); 314533693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3146f4f5df23SVikas Chaudhary break; 3147de8c72daSVikas Chaudhary case QLA8XXX_DEV_NEED_RESET: 31486e7b4292SVikas Chaudhary /* 3149b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, if NEED_RESET is set by any 3150b37ca418SVikas Chaudhary * driver, it should be honored, irrespective of 3151b37ca418SVikas Chaudhary * IDC_CTRL DONTRESET_BIT0 31526e7b4292SVikas Chaudhary */ 3153b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) { 31546e7b4292SVikas Chaudhary qla4_83xx_need_reset_handler(ha); 31556e7b4292SVikas Chaudhary } else if (is_qla8022(ha)) { 3156f4f5df23SVikas Chaudhary if (!ql4xdontresethba) { 3157f8086f4fSVikas Chaudhary qla4_82xx_need_reset_handler(ha); 3158f4f5df23SVikas Chaudhary /* Update timeout value after need 3159f4f5df23SVikas Chaudhary * reset handler */ 3160f4f5df23SVikas Chaudhary dev_init_timeout = jiffies + 3161f4f5df23SVikas Chaudhary (ha->nx_dev_init_timeout * HZ); 31629acf7533SMike Hernandez } else { 316333693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 31649acf7533SMike Hernandez msleep(1000); 316533693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3166f4f5df23SVikas Chaudhary } 3167f4f5df23SVikas Chaudhary } 3168f4f5df23SVikas Chaudhary break; 3169de8c72daSVikas Chaudhary case QLA8XXX_DEV_NEED_QUIESCENT: 3170f4f5df23SVikas Chaudhary /* idc locked/unlocked in handler */ 3171f4f5df23SVikas Chaudhary qla4_8xxx_need_qsnt_handler(ha); 3172e3f37d16SNilesh Javali break; 3173de8c72daSVikas Chaudhary case QLA8XXX_DEV_QUIESCENT: 317433693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3175f4f5df23SVikas Chaudhary msleep(1000); 317633693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3177f4f5df23SVikas Chaudhary break; 3178de8c72daSVikas Chaudhary case QLA8XXX_DEV_FAILED: 317933693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3180f4f5df23SVikas Chaudhary qla4xxx_dead_adapter_cleanup(ha); 3181f4f5df23SVikas Chaudhary rval = QLA_ERROR; 318233693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3183f4f5df23SVikas Chaudhary goto exit; 3184f4f5df23SVikas Chaudhary default: 318533693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3186f4f5df23SVikas Chaudhary qla4xxx_dead_adapter_cleanup(ha); 3187f4f5df23SVikas Chaudhary rval = QLA_ERROR; 318833693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3189f4f5df23SVikas Chaudhary goto exit; 3190f4f5df23SVikas Chaudhary } 3191f4f5df23SVikas Chaudhary } 3192f4f5df23SVikas Chaudhary exit: 319333693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 31946e7b4292SVikas Chaudhary exit_state_handler: 3195f4f5df23SVikas Chaudhary return rval; 3196f4f5df23SVikas Chaudhary } 3197f4f5df23SVikas Chaudhary 3198f4f5df23SVikas Chaudhary int qla4_8xxx_load_risc(struct scsi_qla_host *ha) 3199f4f5df23SVikas Chaudhary { 3200f4f5df23SVikas Chaudhary int retval; 320178764999SSarang Radke 320278764999SSarang Radke /* clear the interrupt */ 3203b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) { 32046e7b4292SVikas Chaudhary writel(0, &ha->qla4_83xx_reg->risc_intr); 32056e7b4292SVikas Chaudhary readl(&ha->qla4_83xx_reg->risc_intr); 32066e7b4292SVikas Chaudhary } else if (is_qla8022(ha)) { 32077664a1fdSVikas Chaudhary writel(0, &ha->qla4_82xx_reg->host_int); 32087664a1fdSVikas Chaudhary readl(&ha->qla4_82xx_reg->host_int); 32096e7b4292SVikas Chaudhary } 321078764999SSarang Radke 3211f4f5df23SVikas Chaudhary retval = qla4_8xxx_device_state_handler(ha); 3212f4f5df23SVikas Chaudhary 3213137257daSPoornima Vonti if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags)) 3214f4f5df23SVikas Chaudhary retval = qla4xxx_request_irqs(ha); 3215f581a3f7SVikas Chaudhary 3216f4f5df23SVikas Chaudhary return retval; 3217f4f5df23SVikas Chaudhary } 3218f4f5df23SVikas Chaudhary 3219f4f5df23SVikas Chaudhary /*****************************************************************************/ 3220f4f5df23SVikas Chaudhary /* Flash Manipulation Routines */ 3221f4f5df23SVikas Chaudhary /*****************************************************************************/ 3222f4f5df23SVikas Chaudhary 3223f4f5df23SVikas Chaudhary #define OPTROM_BURST_SIZE 0x1000 3224f4f5df23SVikas Chaudhary #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3225f4f5df23SVikas Chaudhary 3226f4f5df23SVikas Chaudhary #define FARX_DATA_FLAG BIT_31 3227f4f5df23SVikas Chaudhary #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 3228f4f5df23SVikas Chaudhary #define FARX_ACCESS_FLASH_DATA 0x7FF00000 3229f4f5df23SVikas Chaudhary 3230f4f5df23SVikas Chaudhary static inline uint32_t 3231f4f5df23SVikas Chaudhary flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 3232f4f5df23SVikas Chaudhary { 3233f4f5df23SVikas Chaudhary return hw->flash_conf_off | faddr; 3234f4f5df23SVikas Chaudhary } 3235f4f5df23SVikas Chaudhary 3236f4f5df23SVikas Chaudhary static inline uint32_t 3237f4f5df23SVikas Chaudhary flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 3238f4f5df23SVikas Chaudhary { 3239f4f5df23SVikas Chaudhary return hw->flash_data_off | faddr; 3240f4f5df23SVikas Chaudhary } 3241f4f5df23SVikas Chaudhary 3242f4f5df23SVikas Chaudhary static uint32_t * 3243f8086f4fSVikas Chaudhary qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, 3244f4f5df23SVikas Chaudhary uint32_t faddr, uint32_t length) 3245f4f5df23SVikas Chaudhary { 3246f4f5df23SVikas Chaudhary uint32_t i; 3247f4f5df23SVikas Chaudhary uint32_t val; 3248f4f5df23SVikas Chaudhary int loops = 0; 3249f8086f4fSVikas Chaudhary while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { 3250f4f5df23SVikas Chaudhary udelay(100); 3251f4f5df23SVikas Chaudhary cond_resched(); 3252f4f5df23SVikas Chaudhary loops++; 3253f4f5df23SVikas Chaudhary } 3254f4f5df23SVikas Chaudhary if (loops >= 50000) { 3255f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); 3256f4f5df23SVikas Chaudhary return dwptr; 3257f4f5df23SVikas Chaudhary } 3258f4f5df23SVikas Chaudhary 3259f4f5df23SVikas Chaudhary /* Dword reads to flash. */ 3260f4f5df23SVikas Chaudhary for (i = 0; i < length/4; i++, faddr += 4) { 3261f8086f4fSVikas Chaudhary if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) { 3262f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 3263f4f5df23SVikas Chaudhary "Do ROM fast read failed\n"); 3264f4f5df23SVikas Chaudhary goto done_read; 3265f4f5df23SVikas Chaudhary } 3266f4f5df23SVikas Chaudhary dwptr[i] = __constant_cpu_to_le32(val); 3267f4f5df23SVikas Chaudhary } 3268f4f5df23SVikas Chaudhary 3269f4f5df23SVikas Chaudhary done_read: 3270f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 3271f4f5df23SVikas Chaudhary return dwptr; 3272f4f5df23SVikas Chaudhary } 3273f4f5df23SVikas Chaudhary 3274f4f5df23SVikas Chaudhary /** 3275f4f5df23SVikas Chaudhary * Address and length are byte address 3276f4f5df23SVikas Chaudhary **/ 3277f4f5df23SVikas Chaudhary static uint8_t * 3278f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 3279f4f5df23SVikas Chaudhary uint32_t offset, uint32_t length) 3280f4f5df23SVikas Chaudhary { 3281f8086f4fSVikas Chaudhary qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length); 3282f4f5df23SVikas Chaudhary return buf; 3283f4f5df23SVikas Chaudhary } 3284f4f5df23SVikas Chaudhary 3285f4f5df23SVikas Chaudhary static int 3286f4f5df23SVikas Chaudhary qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) 3287f4f5df23SVikas Chaudhary { 3288f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "DEF", "PCI" }; 3289f4f5df23SVikas Chaudhary 3290f4f5df23SVikas Chaudhary /* 3291f4f5df23SVikas Chaudhary * FLT-location structure resides after the last PCI region. 3292f4f5df23SVikas Chaudhary */ 3293f4f5df23SVikas Chaudhary 3294f4f5df23SVikas Chaudhary /* Begin with sane defaults. */ 3295f4f5df23SVikas Chaudhary loc = locations[0]; 3296f4f5df23SVikas Chaudhary *start = FA_FLASH_LAYOUT_ADDR_82; 3297f4f5df23SVikas Chaudhary 3298f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 3299f4f5df23SVikas Chaudhary return QLA_SUCCESS; 3300f4f5df23SVikas Chaudhary } 3301f4f5df23SVikas Chaudhary 3302f4f5df23SVikas Chaudhary static void 3303f4f5df23SVikas Chaudhary qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) 3304f4f5df23SVikas Chaudhary { 3305f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "DEF", "FLT" }; 3306f4f5df23SVikas Chaudhary uint16_t *wptr; 3307f4f5df23SVikas Chaudhary uint16_t cnt, chksum; 33086e7b4292SVikas Chaudhary uint32_t start, status; 3309f4f5df23SVikas Chaudhary struct qla_flt_header *flt; 3310f4f5df23SVikas Chaudhary struct qla_flt_region *region; 3311f4f5df23SVikas Chaudhary struct ql82xx_hw_data *hw = &ha->hw; 3312f4f5df23SVikas Chaudhary 3313f4f5df23SVikas Chaudhary hw->flt_region_flt = flt_addr; 3314f4f5df23SVikas Chaudhary wptr = (uint16_t *)ha->request_ring; 3315f4f5df23SVikas Chaudhary flt = (struct qla_flt_header *)ha->request_ring; 3316f4f5df23SVikas Chaudhary region = (struct qla_flt_region *)&flt[1]; 33176e7b4292SVikas Chaudhary 33186e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 3319f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3320f4f5df23SVikas Chaudhary flt_addr << 2, OPTROM_BURST_SIZE); 3321b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 33226e7b4292SVikas Chaudhary status = qla4_83xx_flash_read_u32(ha, flt_addr << 2, 33236e7b4292SVikas Chaudhary (uint8_t *)ha->request_ring, 33246e7b4292SVikas Chaudhary 0x400); 33256e7b4292SVikas Chaudhary if (status != QLA_SUCCESS) 33266e7b4292SVikas Chaudhary goto no_flash_data; 33276e7b4292SVikas Chaudhary } 33286e7b4292SVikas Chaudhary 3329f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le16(0xffff)) 3330f4f5df23SVikas Chaudhary goto no_flash_data; 3331f4f5df23SVikas Chaudhary if (flt->version != __constant_cpu_to_le16(1)) { 3332f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " 3333f4f5df23SVikas Chaudhary "version=0x%x length=0x%x checksum=0x%x.\n", 3334f4f5df23SVikas Chaudhary le16_to_cpu(flt->version), le16_to_cpu(flt->length), 3335f4f5df23SVikas Chaudhary le16_to_cpu(flt->checksum))); 3336f4f5df23SVikas Chaudhary goto no_flash_data; 3337f4f5df23SVikas Chaudhary } 3338f4f5df23SVikas Chaudhary 3339f4f5df23SVikas Chaudhary cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 3340f4f5df23SVikas Chaudhary for (chksum = 0; cnt; cnt--) 3341f4f5df23SVikas Chaudhary chksum += le16_to_cpu(*wptr++); 3342f4f5df23SVikas Chaudhary if (chksum) { 3343f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 3344f4f5df23SVikas Chaudhary "version=0x%x length=0x%x checksum=0x%x.\n", 3345f4f5df23SVikas Chaudhary le16_to_cpu(flt->version), le16_to_cpu(flt->length), 3346f4f5df23SVikas Chaudhary chksum)); 3347f4f5df23SVikas Chaudhary goto no_flash_data; 3348f4f5df23SVikas Chaudhary } 3349f4f5df23SVikas Chaudhary 3350f4f5df23SVikas Chaudhary loc = locations[1]; 3351f4f5df23SVikas Chaudhary cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 3352f4f5df23SVikas Chaudhary for ( ; cnt; cnt--, region++) { 3353f4f5df23SVikas Chaudhary /* Store addresses as DWORD offsets. */ 3354f4f5df23SVikas Chaudhary start = le32_to_cpu(region->start) >> 2; 3355f4f5df23SVikas Chaudhary 3356f4f5df23SVikas Chaudhary DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 3357f4f5df23SVikas Chaudhary "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 3358f4f5df23SVikas Chaudhary le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 3359f4f5df23SVikas Chaudhary 3360f4f5df23SVikas Chaudhary switch (le32_to_cpu(region->code) & 0xff) { 3361f4f5df23SVikas Chaudhary case FLT_REG_FDT: 3362f4f5df23SVikas Chaudhary hw->flt_region_fdt = start; 3363f4f5df23SVikas Chaudhary break; 3364f4f5df23SVikas Chaudhary case FLT_REG_BOOT_CODE_82: 3365f4f5df23SVikas Chaudhary hw->flt_region_boot = start; 3366f4f5df23SVikas Chaudhary break; 3367f4f5df23SVikas Chaudhary case FLT_REG_FW_82: 336893823956SNilesh Javali case FLT_REG_FW_82_1: 3369f4f5df23SVikas Chaudhary hw->flt_region_fw = start; 3370f4f5df23SVikas Chaudhary break; 3371f4f5df23SVikas Chaudhary case FLT_REG_BOOTLOAD_82: 3372f4f5df23SVikas Chaudhary hw->flt_region_bootload = start; 3373f4f5df23SVikas Chaudhary break; 33742a991c21SManish Rangankar case FLT_REG_ISCSI_PARAM: 33752a991c21SManish Rangankar hw->flt_iscsi_param = start; 33762a991c21SManish Rangankar break; 33774549415aSLalit Chandivade case FLT_REG_ISCSI_CHAP: 33784549415aSLalit Chandivade hw->flt_region_chap = start; 33794549415aSLalit Chandivade hw->flt_chap_size = le32_to_cpu(region->size); 33804549415aSLalit Chandivade break; 33811e9e2be3SAdheer Chandravanshi case FLT_REG_ISCSI_DDB: 33821e9e2be3SAdheer Chandravanshi hw->flt_region_ddb = start; 33831e9e2be3SAdheer Chandravanshi hw->flt_ddb_size = le32_to_cpu(region->size); 33841e9e2be3SAdheer Chandravanshi break; 3385f4f5df23SVikas Chaudhary } 3386f4f5df23SVikas Chaudhary } 3387f4f5df23SVikas Chaudhary goto done; 3388f4f5df23SVikas Chaudhary 3389f4f5df23SVikas Chaudhary no_flash_data: 3390f4f5df23SVikas Chaudhary /* Use hardcoded defaults. */ 3391f4f5df23SVikas Chaudhary loc = locations[0]; 3392f4f5df23SVikas Chaudhary 3393f4f5df23SVikas Chaudhary hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; 3394f4f5df23SVikas Chaudhary hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; 3395f4f5df23SVikas Chaudhary hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; 3396f4f5df23SVikas Chaudhary hw->flt_region_fw = FA_RISC_CODE_ADDR_82; 33979a16f65bSVikas Chaudhary hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2; 33984549415aSLalit Chandivade hw->flt_chap_size = FA_FLASH_CHAP_SIZE; 33991e9e2be3SAdheer Chandravanshi hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2; 34001e9e2be3SAdheer Chandravanshi hw->flt_ddb_size = FA_FLASH_DDB_SIZE; 34014549415aSLalit Chandivade 3402f4f5df23SVikas Chaudhary done: 34039a16f65bSVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 34041e9e2be3SAdheer Chandravanshi "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n", 34059a16f65bSVikas Chaudhary loc, hw->flt_region_flt, hw->flt_region_fdt, 34069a16f65bSVikas Chaudhary hw->flt_region_boot, hw->flt_region_bootload, 34071e9e2be3SAdheer Chandravanshi hw->flt_region_fw, hw->flt_region_chap, 34081e9e2be3SAdheer Chandravanshi hw->flt_chap_size, hw->flt_region_ddb, 34091e9e2be3SAdheer Chandravanshi hw->flt_ddb_size)); 3410f4f5df23SVikas Chaudhary } 3411f4f5df23SVikas Chaudhary 3412f4f5df23SVikas Chaudhary static void 3413f8086f4fSVikas Chaudhary qla4_82xx_get_fdt_info(struct scsi_qla_host *ha) 3414f4f5df23SVikas Chaudhary { 3415f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_4K 0x1000 3416f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_32K 0x8000 3417f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_64K 0x10000 3418f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "MID", "FDT" }; 3419f4f5df23SVikas Chaudhary uint16_t cnt, chksum; 3420f4f5df23SVikas Chaudhary uint16_t *wptr; 3421f4f5df23SVikas Chaudhary struct qla_fdt_layout *fdt; 34223c3e2108SVikas Chaudhary uint16_t mid = 0; 34233c3e2108SVikas Chaudhary uint16_t fid = 0; 3424f4f5df23SVikas Chaudhary struct ql82xx_hw_data *hw = &ha->hw; 3425f4f5df23SVikas Chaudhary 3426f4f5df23SVikas Chaudhary hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3427f4f5df23SVikas Chaudhary hw->flash_data_off = FARX_ACCESS_FLASH_DATA; 3428f4f5df23SVikas Chaudhary 3429f4f5df23SVikas Chaudhary wptr = (uint16_t *)ha->request_ring; 3430f4f5df23SVikas Chaudhary fdt = (struct qla_fdt_layout *)ha->request_ring; 3431f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3432f4f5df23SVikas Chaudhary hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); 3433f4f5df23SVikas Chaudhary 3434f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le16(0xffff)) 3435f4f5df23SVikas Chaudhary goto no_flash_data; 3436f4f5df23SVikas Chaudhary 3437f4f5df23SVikas Chaudhary if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 3438f4f5df23SVikas Chaudhary fdt->sig[3] != 'D') 3439f4f5df23SVikas Chaudhary goto no_flash_data; 3440f4f5df23SVikas Chaudhary 3441f4f5df23SVikas Chaudhary for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 3442f4f5df23SVikas Chaudhary cnt++) 3443f4f5df23SVikas Chaudhary chksum += le16_to_cpu(*wptr++); 3444f4f5df23SVikas Chaudhary 3445f4f5df23SVikas Chaudhary if (chksum) { 3446f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 3447f4f5df23SVikas Chaudhary "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 3448f4f5df23SVikas Chaudhary le16_to_cpu(fdt->version))); 3449f4f5df23SVikas Chaudhary goto no_flash_data; 3450f4f5df23SVikas Chaudhary } 3451f4f5df23SVikas Chaudhary 3452f4f5df23SVikas Chaudhary loc = locations[1]; 3453f4f5df23SVikas Chaudhary mid = le16_to_cpu(fdt->man_id); 3454f4f5df23SVikas Chaudhary fid = le16_to_cpu(fdt->id); 3455f4f5df23SVikas Chaudhary hw->fdt_wrt_disable = fdt->wrt_disable_bits; 3456f4f5df23SVikas Chaudhary hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); 3457f4f5df23SVikas Chaudhary hw->fdt_block_size = le32_to_cpu(fdt->block_size); 3458f4f5df23SVikas Chaudhary 3459f4f5df23SVikas Chaudhary if (fdt->unprotect_sec_cmd) { 3460f4f5df23SVikas Chaudhary hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | 3461f4f5df23SVikas Chaudhary fdt->unprotect_sec_cmd); 3462f4f5df23SVikas Chaudhary hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 3463f4f5df23SVikas Chaudhary flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : 3464f4f5df23SVikas Chaudhary flash_conf_addr(hw, 0x0336); 3465f4f5df23SVikas Chaudhary } 3466f4f5df23SVikas Chaudhary goto done; 3467f4f5df23SVikas Chaudhary 3468f4f5df23SVikas Chaudhary no_flash_data: 3469f4f5df23SVikas Chaudhary loc = locations[0]; 3470f4f5df23SVikas Chaudhary hw->fdt_block_size = FLASH_BLK_SIZE_64K; 3471f4f5df23SVikas Chaudhary done: 3472f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 3473f4f5df23SVikas Chaudhary "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 3474f4f5df23SVikas Chaudhary hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, 3475f4f5df23SVikas Chaudhary hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, 3476f4f5df23SVikas Chaudhary hw->fdt_block_size)); 3477f4f5df23SVikas Chaudhary } 3478f4f5df23SVikas Chaudhary 3479f4f5df23SVikas Chaudhary static void 3480f8086f4fSVikas Chaudhary qla4_82xx_get_idc_param(struct scsi_qla_host *ha) 3481f4f5df23SVikas Chaudhary { 3482f4f5df23SVikas Chaudhary #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 3483f4f5df23SVikas Chaudhary uint32_t *wptr; 3484f4f5df23SVikas Chaudhary 3485f4f5df23SVikas Chaudhary if (!is_qla8022(ha)) 3486f4f5df23SVikas Chaudhary return; 3487f4f5df23SVikas Chaudhary wptr = (uint32_t *)ha->request_ring; 3488f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3489f4f5df23SVikas Chaudhary QLA82XX_IDC_PARAM_ADDR , 8); 3490f4f5df23SVikas Chaudhary 3491f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 3492f4f5df23SVikas Chaudhary ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; 3493f4f5df23SVikas Chaudhary ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; 3494f4f5df23SVikas Chaudhary } else { 3495f4f5df23SVikas Chaudhary ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 3496f4f5df23SVikas Chaudhary ha->nx_reset_timeout = le32_to_cpu(*wptr); 3497f4f5df23SVikas Chaudhary } 3498f4f5df23SVikas Chaudhary 3499f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_DEBUG, ha, 3500f4f5df23SVikas Chaudhary "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); 3501f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_DEBUG, ha, 3502f4f5df23SVikas Chaudhary "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); 3503f4f5df23SVikas Chaudhary return; 3504f4f5df23SVikas Chaudhary } 3505f4f5df23SVikas Chaudhary 350633693c7aSVikas Chaudhary void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, 350733693c7aSVikas Chaudhary int in_count) 350833693c7aSVikas Chaudhary { 350933693c7aSVikas Chaudhary int i; 351033693c7aSVikas Chaudhary 351133693c7aSVikas Chaudhary /* Load all mailbox registers, except mailbox 0. */ 351233693c7aSVikas Chaudhary for (i = 1; i < in_count; i++) 351333693c7aSVikas Chaudhary writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]); 351433693c7aSVikas Chaudhary 351533693c7aSVikas Chaudhary /* Wakeup firmware */ 351633693c7aSVikas Chaudhary writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]); 351733693c7aSVikas Chaudhary readl(&ha->qla4_82xx_reg->mailbox_in[0]); 351833693c7aSVikas Chaudhary writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint); 351933693c7aSVikas Chaudhary readl(&ha->qla4_82xx_reg->hint); 352033693c7aSVikas Chaudhary } 352133693c7aSVikas Chaudhary 352233693c7aSVikas Chaudhary void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count) 352333693c7aSVikas Chaudhary { 352433693c7aSVikas Chaudhary int intr_status; 352533693c7aSVikas Chaudhary 352633693c7aSVikas Chaudhary intr_status = readl(&ha->qla4_82xx_reg->host_int); 352733693c7aSVikas Chaudhary if (intr_status & ISRX_82XX_RISC_INT) { 352833693c7aSVikas Chaudhary ha->mbox_status_count = out_count; 352933693c7aSVikas Chaudhary intr_status = readl(&ha->qla4_82xx_reg->host_status); 353033693c7aSVikas Chaudhary ha->isp_ops->interrupt_service_routine(ha, intr_status); 353133693c7aSVikas Chaudhary 353233693c7aSVikas Chaudhary if (test_bit(AF_INTERRUPTS_ON, &ha->flags) && 353333693c7aSVikas Chaudhary test_bit(AF_INTx_ENABLED, &ha->flags)) 353433693c7aSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 353533693c7aSVikas Chaudhary 0xfbff); 353633693c7aSVikas Chaudhary } 353733693c7aSVikas Chaudhary } 353833693c7aSVikas Chaudhary 3539f4f5df23SVikas Chaudhary int 3540f4f5df23SVikas Chaudhary qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 3541f4f5df23SVikas Chaudhary { 3542f4f5df23SVikas Chaudhary int ret; 3543f4f5df23SVikas Chaudhary uint32_t flt_addr; 3544f4f5df23SVikas Chaudhary 3545f4f5df23SVikas Chaudhary ret = qla4_8xxx_find_flt_start(ha, &flt_addr); 3546f4f5df23SVikas Chaudhary if (ret != QLA_SUCCESS) 3547f4f5df23SVikas Chaudhary return ret; 3548f4f5df23SVikas Chaudhary 3549f4f5df23SVikas Chaudhary qla4_8xxx_get_flt_info(ha, flt_addr); 35506e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 3551f8086f4fSVikas Chaudhary qla4_82xx_get_fdt_info(ha); 3552f8086f4fSVikas Chaudhary qla4_82xx_get_idc_param(ha); 3553b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 35546e7b4292SVikas Chaudhary qla4_83xx_get_idc_param(ha); 35556e7b4292SVikas Chaudhary } 3556f4f5df23SVikas Chaudhary 3557f4f5df23SVikas Chaudhary return QLA_SUCCESS; 3558f4f5df23SVikas Chaudhary } 3559f4f5df23SVikas Chaudhary 3560f4f5df23SVikas Chaudhary /** 3561f4f5df23SVikas Chaudhary * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance 3562f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 3563f4f5df23SVikas Chaudhary * 3564f4f5df23SVikas Chaudhary * Remarks: 3565f4f5df23SVikas Chaudhary * For iSCSI, throws away all I/O and AENs into bit bucket, so they will 3566f4f5df23SVikas Chaudhary * not be available after successful return. Driver must cleanup potential 3567f4f5df23SVikas Chaudhary * outstanding I/O's after calling this funcion. 3568f4f5df23SVikas Chaudhary **/ 3569f4f5df23SVikas Chaudhary int 3570f4f5df23SVikas Chaudhary qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) 3571f4f5df23SVikas Chaudhary { 3572f4f5df23SVikas Chaudhary int status; 3573f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 3574f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 3575f4f5df23SVikas Chaudhary 3576f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 3577f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 3578f4f5df23SVikas Chaudhary 3579f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_STOP_FW; 3580f4f5df23SVikas Chaudhary status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, 3581f4f5df23SVikas Chaudhary &mbox_cmd[0], &mbox_sts[0]); 3582f4f5df23SVikas Chaudhary 3583f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, 3584f4f5df23SVikas Chaudhary __func__, status)); 3585f4f5df23SVikas Chaudhary return status; 3586f4f5df23SVikas Chaudhary } 3587f4f5df23SVikas Chaudhary 3588f4f5df23SVikas Chaudhary /** 3589f8086f4fSVikas Chaudhary * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands. 3590f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 3591f4f5df23SVikas Chaudhary **/ 3592f4f5df23SVikas Chaudhary int 3593f8086f4fSVikas Chaudhary qla4_82xx_isp_reset(struct scsi_qla_host *ha) 3594f4f5df23SVikas Chaudhary { 3595f4f5df23SVikas Chaudhary int rval; 3596f4f5df23SVikas Chaudhary uint32_t dev_state; 3597f4f5df23SVikas Chaudhary 3598f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 3599f8086f4fSVikas Chaudhary dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3600f4f5df23SVikas Chaudhary 3601de8c72daSVikas Chaudhary if (dev_state == QLA8XXX_DEV_READY) { 3602f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 3603f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3604de8c72daSVikas Chaudhary QLA8XXX_DEV_NEED_RESET); 3605de8c72daSVikas Chaudhary set_bit(AF_8XXX_RST_OWNER, &ha->flags); 3606f4f5df23SVikas Chaudhary } else 3607f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); 3608f4f5df23SVikas Chaudhary 3609f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 3610f4f5df23SVikas Chaudhary 3611f4f5df23SVikas Chaudhary rval = qla4_8xxx_device_state_handler(ha); 3612f4f5df23SVikas Chaudhary 3613f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 3614f4f5df23SVikas Chaudhary qla4_8xxx_clear_rst_ready(ha); 3615f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 3616f4f5df23SVikas Chaudhary 3617068237c8STej Parkash if (rval == QLA_SUCCESS) { 3618f8086f4fSVikas Chaudhary ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n"); 361921033639SNilesh Javali clear_bit(AF_FW_RECOVERY, &ha->flags); 3620068237c8STej Parkash } 362121033639SNilesh Javali 3622f4f5df23SVikas Chaudhary return rval; 3623f4f5df23SVikas Chaudhary } 3624f4f5df23SVikas Chaudhary 3625f4f5df23SVikas Chaudhary /** 3626f4f5df23SVikas Chaudhary * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number 3627f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 3628f4f5df23SVikas Chaudhary * 3629f4f5df23SVikas Chaudhary **/ 3630f4f5df23SVikas Chaudhary int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) 3631f4f5df23SVikas Chaudhary { 3632f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 3633f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 3634f4f5df23SVikas Chaudhary struct mbx_sys_info *sys_info; 3635f4f5df23SVikas Chaudhary dma_addr_t sys_info_dma; 3636f4f5df23SVikas Chaudhary int status = QLA_ERROR; 3637f4f5df23SVikas Chaudhary 3638f4f5df23SVikas Chaudhary sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), 3639f4f5df23SVikas Chaudhary &sys_info_dma, GFP_KERNEL); 3640f4f5df23SVikas Chaudhary if (sys_info == NULL) { 3641f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", 3642f4f5df23SVikas Chaudhary ha->host_no, __func__)); 3643f4f5df23SVikas Chaudhary return status; 3644f4f5df23SVikas Chaudhary } 3645f4f5df23SVikas Chaudhary 3646f4f5df23SVikas Chaudhary memset(sys_info, 0, sizeof(*sys_info)); 3647f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 3648f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 3649f4f5df23SVikas Chaudhary 3650f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; 3651f4f5df23SVikas Chaudhary mbox_cmd[1] = LSDW(sys_info_dma); 3652f4f5df23SVikas Chaudhary mbox_cmd[2] = MSDW(sys_info_dma); 3653f4f5df23SVikas Chaudhary mbox_cmd[4] = sizeof(*sys_info); 3654f4f5df23SVikas Chaudhary 3655f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], 3656f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 3657f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", 3658f4f5df23SVikas Chaudhary ha->host_no, __func__)); 3659f4f5df23SVikas Chaudhary goto exit_validate_mac82; 3660f4f5df23SVikas Chaudhary } 3661f4f5df23SVikas Chaudhary 36622ccdf0dcSVikas Chaudhary /* Make sure we receive the minimum required data to cache internally */ 3663b37ca418SVikas Chaudhary if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) < 3664e19dd66fSNilesh Javali offsetof(struct mbx_sys_info, reserved)) { 3665f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" 3666f4f5df23SVikas Chaudhary " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); 3667f4f5df23SVikas Chaudhary goto exit_validate_mac82; 3668f4f5df23SVikas Chaudhary } 3669f4f5df23SVikas Chaudhary 3670f4f5df23SVikas Chaudhary /* Save M.A.C. address & serial_number */ 36712a991c21SManish Rangankar ha->port_num = sys_info->port_num; 3672f4f5df23SVikas Chaudhary memcpy(ha->my_mac, &sys_info->mac_addr[0], 3673f4f5df23SVikas Chaudhary min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); 3674f4f5df23SVikas Chaudhary memcpy(ha->serial_number, &sys_info->serial_number, 3675f4f5df23SVikas Chaudhary min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); 367691ec7cecSVikas Chaudhary memcpy(ha->model_name, &sys_info->board_id_str, 367791ec7cecSVikas Chaudhary min(sizeof(ha->model_name), sizeof(sys_info->board_id_str))); 367891ec7cecSVikas Chaudhary ha->phy_port_cnt = sys_info->phys_port_cnt; 367991ec7cecSVikas Chaudhary ha->phy_port_num = sys_info->port_num; 368091ec7cecSVikas Chaudhary ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt; 3681f4f5df23SVikas Chaudhary 3682f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: " 3683f4f5df23SVikas Chaudhary "mac %02x:%02x:%02x:%02x:%02x:%02x " 3684f4f5df23SVikas Chaudhary "serial %s\n", ha->host_no, __func__, 3685f4f5df23SVikas Chaudhary ha->my_mac[0], ha->my_mac[1], ha->my_mac[2], 3686f4f5df23SVikas Chaudhary ha->my_mac[3], ha->my_mac[4], ha->my_mac[5], 3687f4f5df23SVikas Chaudhary ha->serial_number)); 3688f4f5df23SVikas Chaudhary 3689f4f5df23SVikas Chaudhary status = QLA_SUCCESS; 3690f4f5df23SVikas Chaudhary 3691f4f5df23SVikas Chaudhary exit_validate_mac82: 3692f4f5df23SVikas Chaudhary dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, 3693f4f5df23SVikas Chaudhary sys_info_dma); 3694f4f5df23SVikas Chaudhary return status; 3695f4f5df23SVikas Chaudhary } 3696f4f5df23SVikas Chaudhary 3697f4f5df23SVikas Chaudhary /* Interrupt handling helpers. */ 3698f4f5df23SVikas Chaudhary 36995c19b92aSVikas Chaudhary int qla4_8xxx_intr_enable(struct scsi_qla_host *ha) 3700f4f5df23SVikas Chaudhary { 3701f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 3702f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 3703f4f5df23SVikas Chaudhary 3704f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 3705f4f5df23SVikas Chaudhary 3706f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 3707f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 3708f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 3709f4f5df23SVikas Chaudhary mbox_cmd[1] = INTR_ENABLE; 3710f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 3711f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 3712f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 3713f4f5df23SVikas Chaudhary "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 3714f4f5df23SVikas Chaudhary __func__, mbox_sts[0])); 3715f4f5df23SVikas Chaudhary return QLA_ERROR; 3716f4f5df23SVikas Chaudhary } 3717f4f5df23SVikas Chaudhary return QLA_SUCCESS; 3718f4f5df23SVikas Chaudhary } 3719f4f5df23SVikas Chaudhary 37205c19b92aSVikas Chaudhary int qla4_8xxx_intr_disable(struct scsi_qla_host *ha) 3721f4f5df23SVikas Chaudhary { 3722f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 3723f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 3724f4f5df23SVikas Chaudhary 3725f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 3726f4f5df23SVikas Chaudhary 3727f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 3728f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 3729f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 3730f4f5df23SVikas Chaudhary mbox_cmd[1] = INTR_DISABLE; 3731f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 3732f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 3733f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 3734f4f5df23SVikas Chaudhary "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 3735f4f5df23SVikas Chaudhary __func__, mbox_sts[0])); 3736f4f5df23SVikas Chaudhary return QLA_ERROR; 3737f4f5df23SVikas Chaudhary } 3738f4f5df23SVikas Chaudhary 3739f4f5df23SVikas Chaudhary return QLA_SUCCESS; 3740f4f5df23SVikas Chaudhary } 3741f4f5df23SVikas Chaudhary 3742f4f5df23SVikas Chaudhary void 3743f8086f4fSVikas Chaudhary qla4_82xx_enable_intrs(struct scsi_qla_host *ha) 3744f4f5df23SVikas Chaudhary { 37455c19b92aSVikas Chaudhary qla4_8xxx_intr_enable(ha); 3746f4f5df23SVikas Chaudhary 3747f4f5df23SVikas Chaudhary spin_lock_irq(&ha->hardware_lock); 3748f4f5df23SVikas Chaudhary /* BIT 10 - reset */ 3749f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 3750f4f5df23SVikas Chaudhary spin_unlock_irq(&ha->hardware_lock); 3751f4f5df23SVikas Chaudhary set_bit(AF_INTERRUPTS_ON, &ha->flags); 3752f4f5df23SVikas Chaudhary } 3753f4f5df23SVikas Chaudhary 3754f4f5df23SVikas Chaudhary void 3755f8086f4fSVikas Chaudhary qla4_82xx_disable_intrs(struct scsi_qla_host *ha) 3756f4f5df23SVikas Chaudhary { 37575fa8b573SSarang Radke if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) 37585c19b92aSVikas Chaudhary qla4_8xxx_intr_disable(ha); 3759f4f5df23SVikas Chaudhary 3760f4f5df23SVikas Chaudhary spin_lock_irq(&ha->hardware_lock); 3761f4f5df23SVikas Chaudhary /* BIT 10 - set */ 3762f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 3763f4f5df23SVikas Chaudhary spin_unlock_irq(&ha->hardware_lock); 3764f4f5df23SVikas Chaudhary } 3765f4f5df23SVikas Chaudhary 3766f4f5df23SVikas Chaudhary struct ql4_init_msix_entry { 3767f4f5df23SVikas Chaudhary uint16_t entry; 3768f4f5df23SVikas Chaudhary uint16_t index; 3769f4f5df23SVikas Chaudhary const char *name; 3770f4f5df23SVikas Chaudhary irq_handler_t handler; 3771f4f5df23SVikas Chaudhary }; 3772f4f5df23SVikas Chaudhary 3773f4f5df23SVikas Chaudhary static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = { 3774f4f5df23SVikas Chaudhary { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT, 3775f4f5df23SVikas Chaudhary "qla4xxx (default)", 3776f4f5df23SVikas Chaudhary (irq_handler_t)qla4_8xxx_default_intr_handler }, 3777f4f5df23SVikas Chaudhary { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q, 3778f4f5df23SVikas Chaudhary "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q }, 3779f4f5df23SVikas Chaudhary }; 3780f4f5df23SVikas Chaudhary 3781f4f5df23SVikas Chaudhary void 3782f4f5df23SVikas Chaudhary qla4_8xxx_disable_msix(struct scsi_qla_host *ha) 3783f4f5df23SVikas Chaudhary { 3784f4f5df23SVikas Chaudhary int i; 3785f4f5df23SVikas Chaudhary struct ql4_msix_entry *qentry; 3786f4f5df23SVikas Chaudhary 3787f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 3788f4f5df23SVikas Chaudhary qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 3789f4f5df23SVikas Chaudhary if (qentry->have_irq) { 3790f4f5df23SVikas Chaudhary free_irq(qentry->msix_vector, ha); 3791f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 3792f4f5df23SVikas Chaudhary __func__, qla4_8xxx_msix_entries[i].name)); 3793f4f5df23SVikas Chaudhary } 3794f4f5df23SVikas Chaudhary } 3795f4f5df23SVikas Chaudhary pci_disable_msix(ha->pdev); 3796f4f5df23SVikas Chaudhary clear_bit(AF_MSIX_ENABLED, &ha->flags); 3797f4f5df23SVikas Chaudhary } 3798f4f5df23SVikas Chaudhary 3799f4f5df23SVikas Chaudhary int 3800f4f5df23SVikas Chaudhary qla4_8xxx_enable_msix(struct scsi_qla_host *ha) 3801f4f5df23SVikas Chaudhary { 3802f4f5df23SVikas Chaudhary int i, ret; 3803f4f5df23SVikas Chaudhary struct msix_entry entries[QLA_MSIX_ENTRIES]; 3804f4f5df23SVikas Chaudhary struct ql4_msix_entry *qentry; 3805f4f5df23SVikas Chaudhary 3806f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) 3807f4f5df23SVikas Chaudhary entries[i].entry = qla4_8xxx_msix_entries[i].entry; 3808f4f5df23SVikas Chaudhary 3809f4f5df23SVikas Chaudhary ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries)); 3810f4f5df23SVikas Chaudhary if (ret) { 3811f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 3812f4f5df23SVikas Chaudhary "MSI-X: Failed to enable support -- %d/%d\n", 3813f4f5df23SVikas Chaudhary QLA_MSIX_ENTRIES, ret); 3814f4f5df23SVikas Chaudhary goto msix_out; 3815f4f5df23SVikas Chaudhary } 3816f4f5df23SVikas Chaudhary set_bit(AF_MSIX_ENABLED, &ha->flags); 3817f4f5df23SVikas Chaudhary 3818f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 3819f4f5df23SVikas Chaudhary qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 3820f4f5df23SVikas Chaudhary qentry->msix_vector = entries[i].vector; 3821f4f5df23SVikas Chaudhary qentry->msix_entry = entries[i].entry; 3822f4f5df23SVikas Chaudhary qentry->have_irq = 0; 3823f4f5df23SVikas Chaudhary ret = request_irq(qentry->msix_vector, 3824f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].handler, 0, 3825f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].name, ha); 3826f4f5df23SVikas Chaudhary if (ret) { 3827f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 3828f4f5df23SVikas Chaudhary "MSI-X: Unable to register handler -- %x/%d.\n", 3829f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].index, ret); 3830f4f5df23SVikas Chaudhary qla4_8xxx_disable_msix(ha); 3831f4f5df23SVikas Chaudhary goto msix_out; 3832f4f5df23SVikas Chaudhary } 3833f4f5df23SVikas Chaudhary qentry->have_irq = 1; 3834f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 3835f4f5df23SVikas Chaudhary __func__, qla4_8xxx_msix_entries[i].name)); 3836f4f5df23SVikas Chaudhary } 3837f4f5df23SVikas Chaudhary msix_out: 3838f4f5df23SVikas Chaudhary return ret; 3839f4f5df23SVikas Chaudhary } 3840