1e3976af5SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2f4f5df23SVikas Chaudhary /* 3f4f5df23SVikas Chaudhary * QLogic iSCSI HBA Driver 44a4f51e9SVikas Chaudhary * Copyright (c) 2003-2013 QLogic Corporation 5f4f5df23SVikas Chaudhary */ 6f4f5df23SVikas Chaudhary #include <linux/delay.h> 7a6751ccbSJiri Slaby #include <linux/io.h> 8f4f5df23SVikas Chaudhary #include <linux/pci.h> 9068237c8STej Parkash #include <linux/ratelimit.h> 10f4f5df23SVikas Chaudhary #include "ql4_def.h" 11f4f5df23SVikas Chaudhary #include "ql4_glbl.h" 126e7b4292SVikas Chaudhary #include "ql4_inline.h" 13f4f5df23SVikas Chaudhary 142f8e2c87SChristoph Hellwig #include <linux/io-64-nonatomic-lo-hi.h> 15797a796aSHitoshi Mitake 16b1829789STej Parkash #define TIMEOUT_100_MS 100 17f4f5df23SVikas Chaudhary #define MASK(n) DMA_BIT_MASK(n) 18f4f5df23SVikas Chaudhary #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 19f4f5df23SVikas Chaudhary #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 20f4f5df23SVikas Chaudhary #define MS_WIN(addr) (addr & 0x0ffc0000) 21f4f5df23SVikas Chaudhary #define QLA82XX_PCI_MN_2M (0) 22f4f5df23SVikas Chaudhary #define QLA82XX_PCI_MS_2M (0x80000) 23f4f5df23SVikas Chaudhary #define QLA82XX_PCI_OCM0_2M (0xc0000) 24f4f5df23SVikas Chaudhary #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 25f4f5df23SVikas Chaudhary #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 26f4f5df23SVikas Chaudhary 27f4f5df23SVikas Chaudhary /* CRB window related */ 28f4f5df23SVikas Chaudhary #define CRB_BLK(off) ((off >> 20) & 0x3f) 29f4f5df23SVikas Chaudhary #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 30f4f5df23SVikas Chaudhary #define CRB_WINDOW_2M (0x130060) 317664a1fdSVikas Chaudhary #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 32f4f5df23SVikas Chaudhary ((off) & 0xf0000)) 33f4f5df23SVikas Chaudhary #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 34f4f5df23SVikas Chaudhary #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 35f4f5df23SVikas Chaudhary #define CRB_INDIRECT_2M (0x1e0000UL) 36f4f5df23SVikas Chaudhary 37f4f5df23SVikas Chaudhary static inline void __iomem * 38f4f5df23SVikas Chaudhary qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) 39f4f5df23SVikas Chaudhary { 40f4f5df23SVikas Chaudhary if ((off < ha->first_page_group_end) && 41f4f5df23SVikas Chaudhary (off >= ha->first_page_group_start)) 42f4f5df23SVikas Chaudhary return (void __iomem *)(ha->nx_pcibase + off); 43f4f5df23SVikas Chaudhary 44f4f5df23SVikas Chaudhary return NULL; 45f4f5df23SVikas Chaudhary } 46f4f5df23SVikas Chaudhary 47bb83e59dSBart Van Assche static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8, 48bb83e59dSBart Van Assche 0x410000AC, 0x410000B8, 0x410000BC }; 49f4f5df23SVikas Chaudhary #define MAX_CRB_XFORM 60 50f4f5df23SVikas Chaudhary static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 51f4f5df23SVikas Chaudhary static int qla4_8xxx_crb_table_initialized; 52f4f5df23SVikas Chaudhary 53f4f5df23SVikas Chaudhary #define qla4_8xxx_crb_addr_transform(name) \ 54f4f5df23SVikas Chaudhary (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 55f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 56f4f5df23SVikas Chaudhary static void 57f8086f4fSVikas Chaudhary qla4_82xx_crb_addr_transform_setup(void) 58f4f5df23SVikas Chaudhary { 59f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(XDMA); 60f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(TIMR); 61f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SRE); 62f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN3); 63f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN2); 64f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN1); 65f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN0); 66f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS3); 67f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS2); 68f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS1); 69f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS0); 70f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX7); 71f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX6); 72f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX5); 73f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX4); 74f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX3); 75f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX2); 76f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX1); 77f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX0); 78f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(ROMUSB); 79f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SN); 80f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(QMN); 81f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(QMS); 82f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGNI); 83f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGND); 84f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN3); 85f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN2); 86f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN1); 87f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN0); 88f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGSI); 89f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGSD); 90f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS3); 91f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS2); 92f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS1); 93f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS0); 94f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PS); 95f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PH); 96f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(NIU); 97f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(I2Q); 98f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(EG); 99f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(MN); 100f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(MS); 101f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS2); 102f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS1); 103f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS0); 104f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAM); 105f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(C2C1); 106f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(C2C0); 107f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SMB); 108f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(OCM0); 109f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(I2C0); 110f4f5df23SVikas Chaudhary 111f4f5df23SVikas Chaudhary qla4_8xxx_crb_table_initialized = 1; 112f4f5df23SVikas Chaudhary } 113f4f5df23SVikas Chaudhary 114f4f5df23SVikas Chaudhary static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 115f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 0: PCI */ 116f4f5df23SVikas Chaudhary {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 117f4f5df23SVikas Chaudhary {1, 0x0110000, 0x0120000, 0x130000}, 118f4f5df23SVikas Chaudhary {1, 0x0120000, 0x0122000, 0x124000}, 119f4f5df23SVikas Chaudhary {1, 0x0130000, 0x0132000, 0x126000}, 120f4f5df23SVikas Chaudhary {1, 0x0140000, 0x0142000, 0x128000}, 121f4f5df23SVikas Chaudhary {1, 0x0150000, 0x0152000, 0x12a000}, 122f4f5df23SVikas Chaudhary {1, 0x0160000, 0x0170000, 0x110000}, 123f4f5df23SVikas Chaudhary {1, 0x0170000, 0x0172000, 0x12e000}, 124f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 125f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 126f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 127f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 128f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 129f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 130f4f5df23SVikas Chaudhary {1, 0x01e0000, 0x01e0800, 0x122000}, 131f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000} } }, 132f4f5df23SVikas Chaudhary {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 133f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 3: */ 134f4f5df23SVikas Chaudhary {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 135f4f5df23SVikas Chaudhary {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 136f4f5df23SVikas Chaudhary {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 137f4f5df23SVikas Chaudhary {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 138f4f5df23SVikas Chaudhary {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 139f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 140f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 141f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 142f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 143f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 144f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 145f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 146f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 147f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 148f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 149f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 150f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 151f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 152f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 153f4f5df23SVikas Chaudhary {1, 0x08f0000, 0x08f2000, 0x172000} } }, 154f4f5df23SVikas Chaudhary {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 155f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 156f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 157f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 158f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 159f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 160f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 161f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 162f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 163f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 164f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 165f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 166f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 167f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 168f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 169f4f5df23SVikas Chaudhary {1, 0x09f0000, 0x09f2000, 0x176000} } }, 170f4f5df23SVikas Chaudhary {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 171f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 172f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 173f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 174f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 175f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 176f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 177f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 178f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 179f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 180f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 181f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 182f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 183f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 184f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 185f4f5df23SVikas Chaudhary {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 186f4f5df23SVikas Chaudhary {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 187f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 188f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 189f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 190f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 191f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 192f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 193f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 194f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 195f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 196f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 197f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 198f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 199f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 200f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 201f4f5df23SVikas Chaudhary {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 202f4f5df23SVikas Chaudhary {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 203f4f5df23SVikas Chaudhary {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 204f4f5df23SVikas Chaudhary {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 205f4f5df23SVikas Chaudhary {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 206f4f5df23SVikas Chaudhary {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 207f4f5df23SVikas Chaudhary {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 208f4f5df23SVikas Chaudhary {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 209f4f5df23SVikas Chaudhary {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 210f4f5df23SVikas Chaudhary {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 211f4f5df23SVikas Chaudhary {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 212f4f5df23SVikas Chaudhary {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 213f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 23: */ 214f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 24: */ 215f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 25: */ 216f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 26: */ 217f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 27: */ 218f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 28: */ 219f4f5df23SVikas Chaudhary {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 220f4f5df23SVikas Chaudhary {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 221f4f5df23SVikas Chaudhary {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 222f4f5df23SVikas Chaudhary {{{0} } }, /* 32: PCI */ 223f4f5df23SVikas Chaudhary {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 224f4f5df23SVikas Chaudhary {1, 0x2110000, 0x2120000, 0x130000}, 225f4f5df23SVikas Chaudhary {1, 0x2120000, 0x2122000, 0x124000}, 226f4f5df23SVikas Chaudhary {1, 0x2130000, 0x2132000, 0x126000}, 227f4f5df23SVikas Chaudhary {1, 0x2140000, 0x2142000, 0x128000}, 228f4f5df23SVikas Chaudhary {1, 0x2150000, 0x2152000, 0x12a000}, 229f4f5df23SVikas Chaudhary {1, 0x2160000, 0x2170000, 0x110000}, 230f4f5df23SVikas Chaudhary {1, 0x2170000, 0x2172000, 0x12e000}, 231f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 232f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 233f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 234f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 235f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 236f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 237f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 238f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000} } }, 239f4f5df23SVikas Chaudhary {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 240f4f5df23SVikas Chaudhary {{{0} } }, /* 35: */ 241f4f5df23SVikas Chaudhary {{{0} } }, /* 36: */ 242f4f5df23SVikas Chaudhary {{{0} } }, /* 37: */ 243f4f5df23SVikas Chaudhary {{{0} } }, /* 38: */ 244f4f5df23SVikas Chaudhary {{{0} } }, /* 39: */ 245f4f5df23SVikas Chaudhary {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 246f4f5df23SVikas Chaudhary {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 247f4f5df23SVikas Chaudhary {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 248f4f5df23SVikas Chaudhary {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 249f4f5df23SVikas Chaudhary {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 250f4f5df23SVikas Chaudhary {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 251f4f5df23SVikas Chaudhary {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 252f4f5df23SVikas Chaudhary {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 253f4f5df23SVikas Chaudhary {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 254f4f5df23SVikas Chaudhary {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 255f4f5df23SVikas Chaudhary {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 256f4f5df23SVikas Chaudhary {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 257f4f5df23SVikas Chaudhary {{{0} } }, /* 52: */ 258f4f5df23SVikas Chaudhary {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 259f4f5df23SVikas Chaudhary {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 260f4f5df23SVikas Chaudhary {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 261f4f5df23SVikas Chaudhary {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 262f4f5df23SVikas Chaudhary {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 263f4f5df23SVikas Chaudhary {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 264f4f5df23SVikas Chaudhary {{{0} } }, /* 59: I2C0 */ 265f4f5df23SVikas Chaudhary {{{0} } }, /* 60: I2C1 */ 266f4f5df23SVikas Chaudhary {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ 267f4f5df23SVikas Chaudhary {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 268f4f5df23SVikas Chaudhary {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 269f4f5df23SVikas Chaudhary }; 270f4f5df23SVikas Chaudhary 271f4f5df23SVikas Chaudhary /* 272f4f5df23SVikas Chaudhary * top 12 bits of crb internal address (hub, agent) 273f4f5df23SVikas Chaudhary */ 2747664a1fdSVikas Chaudhary static unsigned qla4_82xx_crb_hub_agt[64] = { 275f4f5df23SVikas Chaudhary 0, 276f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 277f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 278f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 279f4f5df23SVikas Chaudhary 0, 280f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 281f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 282f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 283f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 284f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 285f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 286f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 287f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 288f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 289f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 290f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 291f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 292f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 293f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 294f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 295f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 296f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 297f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 298f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 299f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 300f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 301f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 302f4f5df23SVikas Chaudhary 0, 303f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 304f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 305f4f5df23SVikas Chaudhary 0, 306f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 307f4f5df23SVikas Chaudhary 0, 308f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 309f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 310f4f5df23SVikas Chaudhary 0, 311f4f5df23SVikas Chaudhary 0, 312f4f5df23SVikas Chaudhary 0, 313f4f5df23SVikas Chaudhary 0, 314f4f5df23SVikas Chaudhary 0, 315f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 316f4f5df23SVikas Chaudhary 0, 317f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 318f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 319f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 320f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 321f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 322f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 323f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 324f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 325f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 326f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 327f4f5df23SVikas Chaudhary 0, 328f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 329f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 330f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 331f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 332f4f5df23SVikas Chaudhary 0, 333f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 334f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 335f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 336f4f5df23SVikas Chaudhary 0, 337f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 338f4f5df23SVikas Chaudhary 0, 339f4f5df23SVikas Chaudhary }; 340f4f5df23SVikas Chaudhary 341f4f5df23SVikas Chaudhary /* Device states */ 342f4f5df23SVikas Chaudhary static char *qdev_state[] = { 343f4f5df23SVikas Chaudhary "Unknown", 344f4f5df23SVikas Chaudhary "Cold", 345f4f5df23SVikas Chaudhary "Initializing", 346f4f5df23SVikas Chaudhary "Ready", 347f4f5df23SVikas Chaudhary "Need Reset", 348f4f5df23SVikas Chaudhary "Need Quiescent", 349f4f5df23SVikas Chaudhary "Failed", 350f4f5df23SVikas Chaudhary "Quiescent", 351f4f5df23SVikas Chaudhary }; 352f4f5df23SVikas Chaudhary 353f4f5df23SVikas Chaudhary /* 354f4f5df23SVikas Chaudhary * In: 'off' is offset from CRB space in 128M pci map 355f4f5df23SVikas Chaudhary * Out: 'off' is 2M pci map addr 356f4f5df23SVikas Chaudhary * side effect: lock crb window 357f4f5df23SVikas Chaudhary */ 358f4f5df23SVikas Chaudhary static void 359f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) 360f4f5df23SVikas Chaudhary { 361f4f5df23SVikas Chaudhary u32 win_read; 362f4f5df23SVikas Chaudhary 363f4f5df23SVikas Chaudhary ha->crb_win = CRB_HI(*off); 364f4f5df23SVikas Chaudhary writel(ha->crb_win, 365f4f5df23SVikas Chaudhary (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 366f4f5df23SVikas Chaudhary 367f4f5df23SVikas Chaudhary /* Read back value to make sure write has gone through before trying 368f4f5df23SVikas Chaudhary * to use it. */ 369f4f5df23SVikas Chaudhary win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 370f4f5df23SVikas Chaudhary if (win_read != ha->crb_win) { 371f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 372f4f5df23SVikas Chaudhary "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," 373f4f5df23SVikas Chaudhary " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 374f4f5df23SVikas Chaudhary } 375f4f5df23SVikas Chaudhary *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 376f4f5df23SVikas Chaudhary } 377f4f5df23SVikas Chaudhary 378a93c3835SAhmed S. Darwish #define CRB_WIN_LOCK_TIMEOUT 100000000 379a93c3835SAhmed S. Darwish 380a93c3835SAhmed S. Darwish /* 381a93c3835SAhmed S. Darwish * Context: atomic 382a93c3835SAhmed S. Darwish */ 383a93c3835SAhmed S. Darwish static int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha) 384a93c3835SAhmed S. Darwish { 385a93c3835SAhmed S. Darwish int done = 0, timeout = 0; 386a93c3835SAhmed S. Darwish 387a93c3835SAhmed S. Darwish while (!done) { 388a93c3835SAhmed S. Darwish /* acquire semaphore3 from PCI HW block */ 389a93c3835SAhmed S. Darwish done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 390a93c3835SAhmed S. Darwish if (done == 1) 391a93c3835SAhmed S. Darwish break; 392a93c3835SAhmed S. Darwish if (timeout >= CRB_WIN_LOCK_TIMEOUT) 393a93c3835SAhmed S. Darwish return -1; 394a93c3835SAhmed S. Darwish 395a93c3835SAhmed S. Darwish timeout++; 396a93c3835SAhmed S. Darwish udelay(10); 397a93c3835SAhmed S. Darwish } 398a93c3835SAhmed S. Darwish qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); 399a93c3835SAhmed S. Darwish return 0; 400a93c3835SAhmed S. Darwish } 401a93c3835SAhmed S. Darwish 402a93c3835SAhmed S. Darwish void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha) 403a93c3835SAhmed S. Darwish { 404a93c3835SAhmed S. Darwish qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 405a93c3835SAhmed S. Darwish } 406a93c3835SAhmed S. Darwish 407f4f5df23SVikas Chaudhary void 408f8086f4fSVikas Chaudhary qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) 409f4f5df23SVikas Chaudhary { 410f4f5df23SVikas Chaudhary unsigned long flags = 0; 411f4f5df23SVikas Chaudhary int rv; 412f4f5df23SVikas Chaudhary 413f8086f4fSVikas Chaudhary rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); 414f4f5df23SVikas Chaudhary 415f4f5df23SVikas Chaudhary BUG_ON(rv == -1); 416f4f5df23SVikas Chaudhary 417f4f5df23SVikas Chaudhary if (rv == 1) { 418f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 419f8086f4fSVikas Chaudhary qla4_82xx_crb_win_lock(ha); 420f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(ha, &off); 421f4f5df23SVikas Chaudhary } 422f4f5df23SVikas Chaudhary 423f4f5df23SVikas Chaudhary writel(data, (void __iomem *)off); 424f4f5df23SVikas Chaudhary 425f4f5df23SVikas Chaudhary if (rv == 1) { 426f8086f4fSVikas Chaudhary qla4_82xx_crb_win_unlock(ha); 427f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 428f4f5df23SVikas Chaudhary } 429f4f5df23SVikas Chaudhary } 430f4f5df23SVikas Chaudhary 43133693c7aSVikas Chaudhary uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off) 432f4f5df23SVikas Chaudhary { 433f4f5df23SVikas Chaudhary unsigned long flags = 0; 434f4f5df23SVikas Chaudhary int rv; 435f4f5df23SVikas Chaudhary u32 data; 436f4f5df23SVikas Chaudhary 437f8086f4fSVikas Chaudhary rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); 438f4f5df23SVikas Chaudhary 439f4f5df23SVikas Chaudhary BUG_ON(rv == -1); 440f4f5df23SVikas Chaudhary 441f4f5df23SVikas Chaudhary if (rv == 1) { 442f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 443f8086f4fSVikas Chaudhary qla4_82xx_crb_win_lock(ha); 444f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(ha, &off); 445f4f5df23SVikas Chaudhary } 446f4f5df23SVikas Chaudhary data = readl((void __iomem *)off); 447f4f5df23SVikas Chaudhary 448f4f5df23SVikas Chaudhary if (rv == 1) { 449f8086f4fSVikas Chaudhary qla4_82xx_crb_win_unlock(ha); 450f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 451f4f5df23SVikas Chaudhary } 452f4f5df23SVikas Chaudhary return data; 453f4f5df23SVikas Chaudhary } 454f4f5df23SVikas Chaudhary 455068237c8STej Parkash /* Minidump related functions */ 45633693c7aSVikas Chaudhary int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data) 457068237c8STej Parkash { 45833693c7aSVikas Chaudhary uint32_t win_read, off_value; 45933693c7aSVikas Chaudhary int rval = QLA_SUCCESS; 46033693c7aSVikas Chaudhary 46133693c7aSVikas Chaudhary off_value = off & 0xFFFF0000; 46233693c7aSVikas Chaudhary writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 46333693c7aSVikas Chaudhary 46433693c7aSVikas Chaudhary /* 46533693c7aSVikas Chaudhary * Read back value to make sure write has gone through before trying 46633693c7aSVikas Chaudhary * to use it. 46733693c7aSVikas Chaudhary */ 46833693c7aSVikas Chaudhary win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 46933693c7aSVikas Chaudhary if (win_read != off_value) { 47033693c7aSVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 47133693c7aSVikas Chaudhary "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 47233693c7aSVikas Chaudhary __func__, off_value, win_read, off)); 47333693c7aSVikas Chaudhary rval = QLA_ERROR; 47433693c7aSVikas Chaudhary } else { 47533693c7aSVikas Chaudhary off_value = off & 0x0000FFFF; 47633693c7aSVikas Chaudhary *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M + 47733693c7aSVikas Chaudhary ha->nx_pcibase)); 47833693c7aSVikas Chaudhary } 47933693c7aSVikas Chaudhary return rval; 48033693c7aSVikas Chaudhary } 48133693c7aSVikas Chaudhary 48233693c7aSVikas Chaudhary int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data) 48333693c7aSVikas Chaudhary { 48433693c7aSVikas Chaudhary uint32_t win_read, off_value; 48533693c7aSVikas Chaudhary int rval = QLA_SUCCESS; 486068237c8STej Parkash 487068237c8STej Parkash off_value = off & 0xFFFF0000; 488068237c8STej Parkash writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 489068237c8STej Parkash 490068237c8STej Parkash /* Read back value to make sure write has gone through before trying 491068237c8STej Parkash * to use it. 492068237c8STej Parkash */ 493068237c8STej Parkash win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 494068237c8STej Parkash if (win_read != off_value) { 495068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 496068237c8STej Parkash "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 497068237c8STej Parkash __func__, off_value, win_read, off)); 49833693c7aSVikas Chaudhary rval = QLA_ERROR; 49933693c7aSVikas Chaudhary } else { 500068237c8STej Parkash off_value = off & 0x0000FFFF; 501068237c8STej Parkash writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M + 502068237c8STej Parkash ha->nx_pcibase)); 50333693c7aSVikas Chaudhary } 504068237c8STej Parkash return rval; 505068237c8STej Parkash } 506068237c8STej Parkash 507f4f5df23SVikas Chaudhary #define IDC_LOCK_TIMEOUT 100000000 508f4f5df23SVikas Chaudhary 509f4f5df23SVikas Chaudhary /** 510f8086f4fSVikas Chaudhary * qla4_82xx_idc_lock - hw_lock 511f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 512f4f5df23SVikas Chaudhary * 513f4f5df23SVikas Chaudhary * General purpose lock used to synchronize access to 514f4f5df23SVikas Chaudhary * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. 5153627668cSAhmed S. Darwish * 5163627668cSAhmed S. Darwish * Context: task, can sleep 517f4f5df23SVikas Chaudhary **/ 518f8086f4fSVikas Chaudhary int qla4_82xx_idc_lock(struct scsi_qla_host *ha) 519f4f5df23SVikas Chaudhary { 520f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 521f4f5df23SVikas Chaudhary 5223627668cSAhmed S. Darwish might_sleep(); 5233627668cSAhmed S. Darwish 524f4f5df23SVikas Chaudhary while (!done) { 525f4f5df23SVikas Chaudhary /* acquire semaphore5 from PCI HW block */ 526f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 527f4f5df23SVikas Chaudhary if (done == 1) 528f4f5df23SVikas Chaudhary break; 529f4f5df23SVikas Chaudhary if (timeout >= IDC_LOCK_TIMEOUT) 530f4f5df23SVikas Chaudhary return -1; 531f4f5df23SVikas Chaudhary 532f4f5df23SVikas Chaudhary timeout++; 5333627668cSAhmed S. Darwish msleep(100); 534f4f5df23SVikas Chaudhary } 535f4f5df23SVikas Chaudhary return 0; 536f4f5df23SVikas Chaudhary } 537f4f5df23SVikas Chaudhary 538f8086f4fSVikas Chaudhary void qla4_82xx_idc_unlock(struct scsi_qla_host *ha) 539f4f5df23SVikas Chaudhary { 540f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 541f4f5df23SVikas Chaudhary } 542f4f5df23SVikas Chaudhary 543f4f5df23SVikas Chaudhary int 544f8086f4fSVikas Chaudhary qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) 545f4f5df23SVikas Chaudhary { 546f4f5df23SVikas Chaudhary struct crb_128M_2M_sub_block_map *m; 547f4f5df23SVikas Chaudhary 548f4f5df23SVikas Chaudhary if (*off >= QLA82XX_CRB_MAX) 549f4f5df23SVikas Chaudhary return -1; 550f4f5df23SVikas Chaudhary 551f4f5df23SVikas Chaudhary if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 552f4f5df23SVikas Chaudhary *off = (*off - QLA82XX_PCI_CAMQM) + 553f4f5df23SVikas Chaudhary QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 554f4f5df23SVikas Chaudhary return 0; 555f4f5df23SVikas Chaudhary } 556f4f5df23SVikas Chaudhary 557f4f5df23SVikas Chaudhary if (*off < QLA82XX_PCI_CRBSPACE) 558f4f5df23SVikas Chaudhary return -1; 559f4f5df23SVikas Chaudhary 560f4f5df23SVikas Chaudhary *off -= QLA82XX_PCI_CRBSPACE; 561f4f5df23SVikas Chaudhary /* 562f4f5df23SVikas Chaudhary * Try direct map 563f4f5df23SVikas Chaudhary */ 564f4f5df23SVikas Chaudhary 565f4f5df23SVikas Chaudhary m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 566f4f5df23SVikas Chaudhary 567f4f5df23SVikas Chaudhary if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 568f4f5df23SVikas Chaudhary *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 569f4f5df23SVikas Chaudhary return 0; 570f4f5df23SVikas Chaudhary } 571f4f5df23SVikas Chaudhary 572f4f5df23SVikas Chaudhary /* 573f4f5df23SVikas Chaudhary * Not in direct map, use crb window 574f4f5df23SVikas Chaudhary */ 575f4f5df23SVikas Chaudhary return 1; 576f4f5df23SVikas Chaudhary } 577f4f5df23SVikas Chaudhary 578f4f5df23SVikas Chaudhary /* 579f4f5df23SVikas Chaudhary * check memory access boundary. 580f4f5df23SVikas Chaudhary * used by test agent. support ddr access only for now 581f4f5df23SVikas Chaudhary */ 582f4f5df23SVikas Chaudhary static unsigned long 583f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha, 584f4f5df23SVikas Chaudhary unsigned long long addr, int size) 585f4f5df23SVikas Chaudhary { 586de8c72daSVikas Chaudhary if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 587de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX) || 588de8c72daSVikas Chaudhary !QLA8XXX_ADDR_IN_RANGE(addr + size - 1, 589de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) || 590f4f5df23SVikas Chaudhary ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { 591f4f5df23SVikas Chaudhary return 0; 592f4f5df23SVikas Chaudhary } 593f4f5df23SVikas Chaudhary return 1; 594f4f5df23SVikas Chaudhary } 595f4f5df23SVikas Chaudhary 5967664a1fdSVikas Chaudhary static int qla4_82xx_pci_set_window_warning_count; 597f4f5df23SVikas Chaudhary 598f4f5df23SVikas Chaudhary static unsigned long 599f8086f4fSVikas Chaudhary qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) 600f4f5df23SVikas Chaudhary { 601f4f5df23SVikas Chaudhary int window; 602f4f5df23SVikas Chaudhary u32 win_read; 603f4f5df23SVikas Chaudhary 604de8c72daSVikas Chaudhary if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 605de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX)) { 606f4f5df23SVikas Chaudhary /* DDR network side */ 607f4f5df23SVikas Chaudhary window = MN_WIN(addr); 608f4f5df23SVikas Chaudhary ha->ddr_mn_window = window; 609f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->mn_win_crb | 610f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 611f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | 612f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE); 613f4f5df23SVikas Chaudhary if ((win_read << 17) != window) { 614f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 615f4f5df23SVikas Chaudhary "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 616f4f5df23SVikas Chaudhary __func__, window, win_read); 617f4f5df23SVikas Chaudhary } 618f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 619de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, 620de8c72daSVikas Chaudhary QLA8XXX_ADDR_OCM0_MAX)) { 621f4f5df23SVikas Chaudhary unsigned int temp1; 622f4f5df23SVikas Chaudhary /* if bits 19:18&17:11 are on */ 623f4f5df23SVikas Chaudhary if ((addr & 0x00ff800) == 0xff800) { 624f4f5df23SVikas Chaudhary printk("%s: QM access not handled.\n", __func__); 625f4f5df23SVikas Chaudhary addr = -1UL; 626f4f5df23SVikas Chaudhary } 627f4f5df23SVikas Chaudhary 628f4f5df23SVikas Chaudhary window = OCM_WIN(addr); 629f4f5df23SVikas Chaudhary ha->ddr_mn_window = window; 630f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->mn_win_crb | 631f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 632f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | 633f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE); 634f4f5df23SVikas Chaudhary temp1 = ((window & 0x1FF) << 7) | 635f4f5df23SVikas Chaudhary ((window & 0x0FFFE0000) >> 17); 636f4f5df23SVikas Chaudhary if (win_read != temp1) { 637f4f5df23SVikas Chaudhary printk("%s: Written OCMwin (0x%x) != Read" 638f4f5df23SVikas Chaudhary " OCMwin (0x%x)\n", __func__, temp1, win_read); 639f4f5df23SVikas Chaudhary } 640f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 641f4f5df23SVikas Chaudhary 642de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 643f4f5df23SVikas Chaudhary QLA82XX_P3_ADDR_QDR_NET_MAX)) { 644f4f5df23SVikas Chaudhary /* QDR network side */ 645f4f5df23SVikas Chaudhary window = MS_WIN(addr); 646f4f5df23SVikas Chaudhary ha->qdr_sn_window = window; 647f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->ms_win_crb | 648f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 649f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, 650f4f5df23SVikas Chaudhary ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 651f4f5df23SVikas Chaudhary if (win_read != window) { 652f4f5df23SVikas Chaudhary printk("%s: Written MSwin (0x%x) != Read " 653f4f5df23SVikas Chaudhary "MSwin (0x%x)\n", __func__, window, win_read); 654f4f5df23SVikas Chaudhary } 655f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 656f4f5df23SVikas Chaudhary 657f4f5df23SVikas Chaudhary } else { 658f4f5df23SVikas Chaudhary /* 659f4f5df23SVikas Chaudhary * peg gdb frequently accesses memory that doesn't exist, 660f4f5df23SVikas Chaudhary * this limits the chit chat so debugging isn't slowed down. 661f4f5df23SVikas Chaudhary */ 6627664a1fdSVikas Chaudhary if ((qla4_82xx_pci_set_window_warning_count++ < 8) || 6637664a1fdSVikas Chaudhary (qla4_82xx_pci_set_window_warning_count%64 == 0)) { 664f4f5df23SVikas Chaudhary printk("%s: Warning:%s Unknown address range!\n", 665f4f5df23SVikas Chaudhary __func__, DRIVER_NAME); 666f4f5df23SVikas Chaudhary } 667f4f5df23SVikas Chaudhary addr = -1UL; 668f4f5df23SVikas Chaudhary } 669f4f5df23SVikas Chaudhary return addr; 670f4f5df23SVikas Chaudhary } 671f4f5df23SVikas Chaudhary 672f4f5df23SVikas Chaudhary /* check if address is in the same windows as the previous access */ 673f8086f4fSVikas Chaudhary static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha, 674f4f5df23SVikas Chaudhary unsigned long long addr) 675f4f5df23SVikas Chaudhary { 676f4f5df23SVikas Chaudhary int window; 677f4f5df23SVikas Chaudhary unsigned long long qdr_max; 678f4f5df23SVikas Chaudhary 679f4f5df23SVikas Chaudhary qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 680f4f5df23SVikas Chaudhary 681de8c72daSVikas Chaudhary if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 682de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX)) { 683f4f5df23SVikas Chaudhary /* DDR network side */ 684f4f5df23SVikas Chaudhary BUG(); /* MN access can not come here */ 685de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, 686de8c72daSVikas Chaudhary QLA8XXX_ADDR_OCM0_MAX)) { 687f4f5df23SVikas Chaudhary return 1; 688de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1, 689de8c72daSVikas Chaudhary QLA8XXX_ADDR_OCM1_MAX)) { 690f4f5df23SVikas Chaudhary return 1; 691de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 692f4f5df23SVikas Chaudhary qdr_max)) { 693f4f5df23SVikas Chaudhary /* QDR network side */ 694de8c72daSVikas Chaudhary window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f; 695f4f5df23SVikas Chaudhary if (ha->qdr_sn_window == window) 696f4f5df23SVikas Chaudhary return 1; 697f4f5df23SVikas Chaudhary } 698f4f5df23SVikas Chaudhary 699f4f5df23SVikas Chaudhary return 0; 700f4f5df23SVikas Chaudhary } 701f4f5df23SVikas Chaudhary 702f8086f4fSVikas Chaudhary static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha, 703f4f5df23SVikas Chaudhary u64 off, void *data, int size) 704f4f5df23SVikas Chaudhary { 705f4f5df23SVikas Chaudhary unsigned long flags; 706f4f5df23SVikas Chaudhary void __iomem *addr; 707f4f5df23SVikas Chaudhary int ret = 0; 708f4f5df23SVikas Chaudhary u64 start; 709f4f5df23SVikas Chaudhary void __iomem *mem_ptr = NULL; 710f4f5df23SVikas Chaudhary unsigned long mem_base; 711f4f5df23SVikas Chaudhary unsigned long mem_page; 712f4f5df23SVikas Chaudhary 713f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 714f4f5df23SVikas Chaudhary 715f4f5df23SVikas Chaudhary /* 716f4f5df23SVikas Chaudhary * If attempting to access unknown address or straddle hw windows, 717f4f5df23SVikas Chaudhary * do not access. 718f4f5df23SVikas Chaudhary */ 719f8086f4fSVikas Chaudhary start = qla4_82xx_pci_set_window(ha, off); 720f4f5df23SVikas Chaudhary if ((start == -1UL) || 721f8086f4fSVikas Chaudhary (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 722f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 723f4f5df23SVikas Chaudhary printk(KERN_ERR"%s out of bound pci memory access. " 724f4f5df23SVikas Chaudhary "offset is 0x%llx\n", DRIVER_NAME, off); 725f4f5df23SVikas Chaudhary return -1; 726f4f5df23SVikas Chaudhary } 727f4f5df23SVikas Chaudhary 728f4f5df23SVikas Chaudhary addr = qla4_8xxx_pci_base_offsetfset(ha, start); 729f4f5df23SVikas Chaudhary if (!addr) { 730f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 731f4f5df23SVikas Chaudhary mem_base = pci_resource_start(ha->pdev, 0); 732f4f5df23SVikas Chaudhary mem_page = start & PAGE_MASK; 733f4f5df23SVikas Chaudhary /* Map two pages whenever user tries to access addresses in two 734f4f5df23SVikas Chaudhary consecutive pages. 735f4f5df23SVikas Chaudhary */ 736f4f5df23SVikas Chaudhary if (mem_page != ((start + size - 1) & PAGE_MASK)) 737f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 738f4f5df23SVikas Chaudhary else 739f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 740f4f5df23SVikas Chaudhary 741f4f5df23SVikas Chaudhary if (mem_ptr == NULL) { 742f4f5df23SVikas Chaudhary *(u8 *)data = 0; 743f4f5df23SVikas Chaudhary return -1; 744f4f5df23SVikas Chaudhary } 745f4f5df23SVikas Chaudhary addr = mem_ptr; 746f4f5df23SVikas Chaudhary addr += start & (PAGE_SIZE - 1); 747f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 748f4f5df23SVikas Chaudhary } 749f4f5df23SVikas Chaudhary 750f4f5df23SVikas Chaudhary switch (size) { 751f4f5df23SVikas Chaudhary case 1: 752f4f5df23SVikas Chaudhary *(u8 *)data = readb(addr); 753f4f5df23SVikas Chaudhary break; 754f4f5df23SVikas Chaudhary case 2: 755f4f5df23SVikas Chaudhary *(u16 *)data = readw(addr); 756f4f5df23SVikas Chaudhary break; 757f4f5df23SVikas Chaudhary case 4: 758f4f5df23SVikas Chaudhary *(u32 *)data = readl(addr); 759f4f5df23SVikas Chaudhary break; 760f4f5df23SVikas Chaudhary case 8: 761f4f5df23SVikas Chaudhary *(u64 *)data = readq(addr); 762f4f5df23SVikas Chaudhary break; 763f4f5df23SVikas Chaudhary default: 764f4f5df23SVikas Chaudhary ret = -1; 765f4f5df23SVikas Chaudhary break; 766f4f5df23SVikas Chaudhary } 767f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 768f4f5df23SVikas Chaudhary 769f4f5df23SVikas Chaudhary if (mem_ptr) 770f4f5df23SVikas Chaudhary iounmap(mem_ptr); 771f4f5df23SVikas Chaudhary return ret; 772f4f5df23SVikas Chaudhary } 773f4f5df23SVikas Chaudhary 774f4f5df23SVikas Chaudhary static int 775f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, 776f4f5df23SVikas Chaudhary void *data, int size) 777f4f5df23SVikas Chaudhary { 778f4f5df23SVikas Chaudhary unsigned long flags; 779f4f5df23SVikas Chaudhary void __iomem *addr; 780f4f5df23SVikas Chaudhary int ret = 0; 781f4f5df23SVikas Chaudhary u64 start; 782f4f5df23SVikas Chaudhary void __iomem *mem_ptr = NULL; 783f4f5df23SVikas Chaudhary unsigned long mem_base; 784f4f5df23SVikas Chaudhary unsigned long mem_page; 785f4f5df23SVikas Chaudhary 786f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 787f4f5df23SVikas Chaudhary 788f4f5df23SVikas Chaudhary /* 789f4f5df23SVikas Chaudhary * If attempting to access unknown address or straddle hw windows, 790f4f5df23SVikas Chaudhary * do not access. 791f4f5df23SVikas Chaudhary */ 792f8086f4fSVikas Chaudhary start = qla4_82xx_pci_set_window(ha, off); 793f4f5df23SVikas Chaudhary if ((start == -1UL) || 794f8086f4fSVikas Chaudhary (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 795f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 796f4f5df23SVikas Chaudhary printk(KERN_ERR"%s out of bound pci memory access. " 797f4f5df23SVikas Chaudhary "offset is 0x%llx\n", DRIVER_NAME, off); 798f4f5df23SVikas Chaudhary return -1; 799f4f5df23SVikas Chaudhary } 800f4f5df23SVikas Chaudhary 801f4f5df23SVikas Chaudhary addr = qla4_8xxx_pci_base_offsetfset(ha, start); 802f4f5df23SVikas Chaudhary if (!addr) { 803f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 804f4f5df23SVikas Chaudhary mem_base = pci_resource_start(ha->pdev, 0); 805f4f5df23SVikas Chaudhary mem_page = start & PAGE_MASK; 806f4f5df23SVikas Chaudhary /* Map two pages whenever user tries to access addresses in two 807f4f5df23SVikas Chaudhary consecutive pages. 808f4f5df23SVikas Chaudhary */ 809f4f5df23SVikas Chaudhary if (mem_page != ((start + size - 1) & PAGE_MASK)) 810f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 811f4f5df23SVikas Chaudhary else 812f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 813f4f5df23SVikas Chaudhary if (mem_ptr == NULL) 814f4f5df23SVikas Chaudhary return -1; 815f4f5df23SVikas Chaudhary 816f4f5df23SVikas Chaudhary addr = mem_ptr; 817f4f5df23SVikas Chaudhary addr += start & (PAGE_SIZE - 1); 818f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 819f4f5df23SVikas Chaudhary } 820f4f5df23SVikas Chaudhary 821f4f5df23SVikas Chaudhary switch (size) { 822f4f5df23SVikas Chaudhary case 1: 823f4f5df23SVikas Chaudhary writeb(*(u8 *)data, addr); 824f4f5df23SVikas Chaudhary break; 825f4f5df23SVikas Chaudhary case 2: 826f4f5df23SVikas Chaudhary writew(*(u16 *)data, addr); 827f4f5df23SVikas Chaudhary break; 828f4f5df23SVikas Chaudhary case 4: 829f4f5df23SVikas Chaudhary writel(*(u32 *)data, addr); 830f4f5df23SVikas Chaudhary break; 831f4f5df23SVikas Chaudhary case 8: 832f4f5df23SVikas Chaudhary writeq(*(u64 *)data, addr); 833f4f5df23SVikas Chaudhary break; 834f4f5df23SVikas Chaudhary default: 835f4f5df23SVikas Chaudhary ret = -1; 836f4f5df23SVikas Chaudhary break; 837f4f5df23SVikas Chaudhary } 838f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 839f4f5df23SVikas Chaudhary if (mem_ptr) 840f4f5df23SVikas Chaudhary iounmap(mem_ptr); 841f4f5df23SVikas Chaudhary return ret; 842f4f5df23SVikas Chaudhary } 843f4f5df23SVikas Chaudhary 844f4f5df23SVikas Chaudhary #define MTU_FUDGE_FACTOR 100 845f4f5df23SVikas Chaudhary 846f4f5df23SVikas Chaudhary static unsigned long 847f8086f4fSVikas Chaudhary qla4_82xx_decode_crb_addr(unsigned long addr) 848f4f5df23SVikas Chaudhary { 849f4f5df23SVikas Chaudhary int i; 850f4f5df23SVikas Chaudhary unsigned long base_addr, offset, pci_base; 851f4f5df23SVikas Chaudhary 852f4f5df23SVikas Chaudhary if (!qla4_8xxx_crb_table_initialized) 853f8086f4fSVikas Chaudhary qla4_82xx_crb_addr_transform_setup(); 854f4f5df23SVikas Chaudhary 855f4f5df23SVikas Chaudhary pci_base = ADDR_ERROR; 856f4f5df23SVikas Chaudhary base_addr = addr & 0xfff00000; 857f4f5df23SVikas Chaudhary offset = addr & 0x000fffff; 858f4f5df23SVikas Chaudhary 859f4f5df23SVikas Chaudhary for (i = 0; i < MAX_CRB_XFORM; i++) { 860f4f5df23SVikas Chaudhary if (crb_addr_xform[i] == base_addr) { 861f4f5df23SVikas Chaudhary pci_base = i << 20; 862f4f5df23SVikas Chaudhary break; 863f4f5df23SVikas Chaudhary } 864f4f5df23SVikas Chaudhary } 865f4f5df23SVikas Chaudhary if (pci_base == ADDR_ERROR) 866f4f5df23SVikas Chaudhary return pci_base; 867f4f5df23SVikas Chaudhary else 868f4f5df23SVikas Chaudhary return pci_base + offset; 869f4f5df23SVikas Chaudhary } 870f4f5df23SVikas Chaudhary 871f4f5df23SVikas Chaudhary static long rom_max_timeout = 100; 8727664a1fdSVikas Chaudhary static long qla4_82xx_rom_lock_timeout = 100; 873f4f5df23SVikas Chaudhary 874014aced1SAhmed S. Darwish /* 875014aced1SAhmed S. Darwish * Context: task, can_sleep 876014aced1SAhmed S. Darwish */ 877f4f5df23SVikas Chaudhary static int 878f8086f4fSVikas Chaudhary qla4_82xx_rom_lock(struct scsi_qla_host *ha) 879f4f5df23SVikas Chaudhary { 880f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 881f4f5df23SVikas Chaudhary 882014aced1SAhmed S. Darwish might_sleep(); 883014aced1SAhmed S. Darwish 884f4f5df23SVikas Chaudhary while (!done) { 885f4f5df23SVikas Chaudhary /* acquire semaphore2 from PCI HW block */ 886f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 887f4f5df23SVikas Chaudhary if (done == 1) 888f4f5df23SVikas Chaudhary break; 8897664a1fdSVikas Chaudhary if (timeout >= qla4_82xx_rom_lock_timeout) 890f4f5df23SVikas Chaudhary return -1; 891f4f5df23SVikas Chaudhary 892f4f5df23SVikas Chaudhary timeout++; 893014aced1SAhmed S. Darwish msleep(20); 894f4f5df23SVikas Chaudhary } 895f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 896f4f5df23SVikas Chaudhary return 0; 897f4f5df23SVikas Chaudhary } 898f4f5df23SVikas Chaudhary 899f4f5df23SVikas Chaudhary static void 900f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(struct scsi_qla_host *ha) 901f4f5df23SVikas Chaudhary { 902f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 903f4f5df23SVikas Chaudhary } 904f4f5df23SVikas Chaudhary 905f4f5df23SVikas Chaudhary static int 906f8086f4fSVikas Chaudhary qla4_82xx_wait_rom_done(struct scsi_qla_host *ha) 907f4f5df23SVikas Chaudhary { 908f4f5df23SVikas Chaudhary long timeout = 0; 909f4f5df23SVikas Chaudhary long done = 0 ; 910f4f5df23SVikas Chaudhary 911f4f5df23SVikas Chaudhary while (done == 0) { 912f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 913f4f5df23SVikas Chaudhary done &= 2; 914f4f5df23SVikas Chaudhary timeout++; 915f4f5df23SVikas Chaudhary if (timeout >= rom_max_timeout) { 916f4f5df23SVikas Chaudhary printk("%s: Timeout reached waiting for rom done", 917f4f5df23SVikas Chaudhary DRIVER_NAME); 918f4f5df23SVikas Chaudhary return -1; 919f4f5df23SVikas Chaudhary } 920f4f5df23SVikas Chaudhary } 921f4f5df23SVikas Chaudhary return 0; 922f4f5df23SVikas Chaudhary } 923f4f5df23SVikas Chaudhary 924f4f5df23SVikas Chaudhary static int 925f8086f4fSVikas Chaudhary qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 926f4f5df23SVikas Chaudhary { 927f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 928f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 929f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 930f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 931f8086f4fSVikas Chaudhary if (qla4_82xx_wait_rom_done(ha)) { 932f4f5df23SVikas Chaudhary printk("%s: Error waiting for rom done\n", DRIVER_NAME); 933f4f5df23SVikas Chaudhary return -1; 934f4f5df23SVikas Chaudhary } 935f4f5df23SVikas Chaudhary /* reset abyte_cnt and dummy_byte_cnt */ 936f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 937f4f5df23SVikas Chaudhary udelay(10); 938f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 939f4f5df23SVikas Chaudhary 940f8086f4fSVikas Chaudhary *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 941f4f5df23SVikas Chaudhary return 0; 942f4f5df23SVikas Chaudhary } 943f4f5df23SVikas Chaudhary 944f4f5df23SVikas Chaudhary static int 945f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 946f4f5df23SVikas Chaudhary { 947f4f5df23SVikas Chaudhary int ret, loops = 0; 948f4f5df23SVikas Chaudhary 949f8086f4fSVikas Chaudhary while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { 950f4f5df23SVikas Chaudhary udelay(100); 951f4f5df23SVikas Chaudhary loops++; 952f4f5df23SVikas Chaudhary } 953f4f5df23SVikas Chaudhary if (loops >= 50000) { 954f8086f4fSVikas Chaudhary ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n", 955f8086f4fSVikas Chaudhary DRIVER_NAME); 956f4f5df23SVikas Chaudhary return -1; 957f4f5df23SVikas Chaudhary } 958f8086f4fSVikas Chaudhary ret = qla4_82xx_do_rom_fast_read(ha, addr, valp); 959f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 960f4f5df23SVikas Chaudhary return ret; 961f4f5df23SVikas Chaudhary } 962f4f5df23SVikas Chaudhary 963653557dfSLee Jones /* 964f4f5df23SVikas Chaudhary * This routine does CRB initialize sequence 965f4f5df23SVikas Chaudhary * to put the ISP into operational state 966653557dfSLee Jones */ 967f4f5df23SVikas Chaudhary static int 968f8086f4fSVikas Chaudhary qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) 969f4f5df23SVikas Chaudhary { 970f4f5df23SVikas Chaudhary int addr, val; 971f4f5df23SVikas Chaudhary int i ; 972f4f5df23SVikas Chaudhary struct crb_addr_pair *buf; 973f4f5df23SVikas Chaudhary unsigned long off; 974f4f5df23SVikas Chaudhary unsigned offset, n; 975f4f5df23SVikas Chaudhary 976f4f5df23SVikas Chaudhary struct crb_addr_pair { 977f4f5df23SVikas Chaudhary long addr; 978f4f5df23SVikas Chaudhary long data; 979f4f5df23SVikas Chaudhary }; 980f4f5df23SVikas Chaudhary 981f4f5df23SVikas Chaudhary /* Halt all the indiviual PEGs and other blocks of the ISP */ 982f8086f4fSVikas Chaudhary qla4_82xx_rom_lock(ha); 983a1fc26baSSwapnil Nagle 984cb74428eSVikas Chaudhary /* disable all I2Q */ 985f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 986f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 987f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 988f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 989f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 990f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 991cb74428eSVikas Chaudhary 992cb74428eSVikas Chaudhary /* disable all niu interrupts */ 993f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 994a1fc26baSSwapnil Nagle /* disable xge rx/tx */ 995f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 996a1fc26baSSwapnil Nagle /* disable xg1 rx/tx */ 997f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 998cb74428eSVikas Chaudhary /* disable sideband mac */ 999f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1000cb74428eSVikas Chaudhary /* disable ap0 mac */ 1001f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1002cb74428eSVikas Chaudhary /* disable ap1 mac */ 1003f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1004a1fc26baSSwapnil Nagle 1005a1fc26baSSwapnil Nagle /* halt sre */ 1006f8086f4fSVikas Chaudhary val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1007f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1008a1fc26baSSwapnil Nagle 1009a1fc26baSSwapnil Nagle /* halt epg */ 1010f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1011a1fc26baSSwapnil Nagle 1012a1fc26baSSwapnil Nagle /* halt timers */ 1013f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1014f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1015f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1016f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1017f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1018f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1019a1fc26baSSwapnil Nagle 1020a1fc26baSSwapnil Nagle /* halt pegs */ 1021f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1022f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1023f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1024f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1025f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1026cb74428eSVikas Chaudhary msleep(5); 1027a1fc26baSSwapnil Nagle 1028a1fc26baSSwapnil Nagle /* big hammer */ 1029f4f5df23SVikas Chaudhary if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 1030f4f5df23SVikas Chaudhary /* don't reset CAM block on reset */ 1031f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1032f4f5df23SVikas Chaudhary else 1033f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1034f4f5df23SVikas Chaudhary 1035f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 1036f4f5df23SVikas Chaudhary 1037f4f5df23SVikas Chaudhary /* Read the signature value from the flash. 1038f4f5df23SVikas Chaudhary * Offset 0: Contain signature (0xcafecafe) 1039f4f5df23SVikas Chaudhary * Offset 4: Offset and number of addr/value pairs 1040f4f5df23SVikas Chaudhary * that present in CRB initialize sequence 1041f4f5df23SVikas Chaudhary */ 1042f8086f4fSVikas Chaudhary if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1043f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(ha, 4, &n) != 0) { 1044f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1045f4f5df23SVikas Chaudhary "[ERROR] Reading crb_init area: n: %08x\n", n); 1046f4f5df23SVikas Chaudhary return -1; 1047f4f5df23SVikas Chaudhary } 1048f4f5df23SVikas Chaudhary 1049f4f5df23SVikas Chaudhary /* Offset in flash = lower 16 bits 1050f4f5df23SVikas Chaudhary * Number of enteries = upper 16 bits 1051f4f5df23SVikas Chaudhary */ 1052f4f5df23SVikas Chaudhary offset = n & 0xffffU; 1053f4f5df23SVikas Chaudhary n = (n >> 16) & 0xffffU; 1054f4f5df23SVikas Chaudhary 1055f4f5df23SVikas Chaudhary /* number of addr/value pair should not exceed 1024 enteries */ 1056f4f5df23SVikas Chaudhary if (n >= 1024) { 1057f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1058f4f5df23SVikas Chaudhary "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1059f4f5df23SVikas Chaudhary DRIVER_NAME, __func__, n); 1060f4f5df23SVikas Chaudhary return -1; 1061f4f5df23SVikas Chaudhary } 1062f4f5df23SVikas Chaudhary 1063f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1064f4f5df23SVikas Chaudhary "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); 1065f4f5df23SVikas Chaudhary 10666da2ec56SKees Cook buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL); 1067f4f5df23SVikas Chaudhary if (buf == NULL) { 1068f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1069f4f5df23SVikas Chaudhary "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); 1070f4f5df23SVikas Chaudhary return -1; 1071f4f5df23SVikas Chaudhary } 1072f4f5df23SVikas Chaudhary 1073f4f5df23SVikas Chaudhary for (i = 0; i < n; i++) { 1074f8086f4fSVikas Chaudhary if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1075f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 1076f4f5df23SVikas Chaudhary 0) { 1077f4f5df23SVikas Chaudhary kfree(buf); 1078f4f5df23SVikas Chaudhary return -1; 1079f4f5df23SVikas Chaudhary } 1080f4f5df23SVikas Chaudhary 1081f4f5df23SVikas Chaudhary buf[i].addr = addr; 1082f4f5df23SVikas Chaudhary buf[i].data = val; 1083f4f5df23SVikas Chaudhary } 1084f4f5df23SVikas Chaudhary 1085f4f5df23SVikas Chaudhary for (i = 0; i < n; i++) { 1086f4f5df23SVikas Chaudhary /* Translate internal CRB initialization 1087f4f5df23SVikas Chaudhary * address to PCI bus address 1088f4f5df23SVikas Chaudhary */ 1089f8086f4fSVikas Chaudhary off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1090f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE; 1091f4f5df23SVikas Chaudhary /* Not all CRB addr/value pair to be written, 1092f4f5df23SVikas Chaudhary * some of them are skipped 1093f4f5df23SVikas Chaudhary */ 1094f4f5df23SVikas Chaudhary 1095f4f5df23SVikas Chaudhary /* skip if LS bit is set*/ 1096f4f5df23SVikas Chaudhary if (off & 0x1) { 1097f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_WARNING, ha, 1098f4f5df23SVikas Chaudhary "Skip CRB init replay for offset = 0x%lx\n", off)); 1099f4f5df23SVikas Chaudhary continue; 1100f4f5df23SVikas Chaudhary } 1101f4f5df23SVikas Chaudhary 1102f4f5df23SVikas Chaudhary /* skipping cold reboot MAGIC */ 1103f4f5df23SVikas Chaudhary if (off == QLA82XX_CAM_RAM(0x1fc)) 1104f4f5df23SVikas Chaudhary continue; 1105f4f5df23SVikas Chaudhary 1106f4f5df23SVikas Chaudhary /* do not reset PCI */ 1107f4f5df23SVikas Chaudhary if (off == (ROMUSB_GLB + 0xbc)) 1108f4f5df23SVikas Chaudhary continue; 1109f4f5df23SVikas Chaudhary 1110f4f5df23SVikas Chaudhary /* skip core clock, so that firmware can increase the clock */ 1111f4f5df23SVikas Chaudhary if (off == (ROMUSB_GLB + 0xc8)) 1112f4f5df23SVikas Chaudhary continue; 1113f4f5df23SVikas Chaudhary 1114f4f5df23SVikas Chaudhary /* skip the function enable register */ 1115f4f5df23SVikas Chaudhary if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1116f4f5df23SVikas Chaudhary continue; 1117f4f5df23SVikas Chaudhary 1118f4f5df23SVikas Chaudhary if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1119f4f5df23SVikas Chaudhary continue; 1120f4f5df23SVikas Chaudhary 1121f4f5df23SVikas Chaudhary if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1122f4f5df23SVikas Chaudhary continue; 1123f4f5df23SVikas Chaudhary 1124f4f5df23SVikas Chaudhary if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1125f4f5df23SVikas Chaudhary continue; 1126f4f5df23SVikas Chaudhary 1127f4f5df23SVikas Chaudhary if (off == ADDR_ERROR) { 1128f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1129f4f5df23SVikas Chaudhary "%s: [ERROR] Unknown addr: 0x%08lx\n", 1130f4f5df23SVikas Chaudhary DRIVER_NAME, buf[i].addr); 1131f4f5df23SVikas Chaudhary continue; 1132f4f5df23SVikas Chaudhary } 1133f4f5df23SVikas Chaudhary 1134f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, off, buf[i].data); 1135f4f5df23SVikas Chaudhary 1136f4f5df23SVikas Chaudhary /* ISP requires much bigger delay to settle down, 1137f4f5df23SVikas Chaudhary * else crb_window returns 0xffffffff 1138f4f5df23SVikas Chaudhary */ 1139f4f5df23SVikas Chaudhary if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1140f4f5df23SVikas Chaudhary msleep(1000); 1141f4f5df23SVikas Chaudhary 1142f4f5df23SVikas Chaudhary /* ISP requires millisec delay between 1143f4f5df23SVikas Chaudhary * successive CRB register updation 1144f4f5df23SVikas Chaudhary */ 1145f4f5df23SVikas Chaudhary msleep(1); 1146f4f5df23SVikas Chaudhary } 1147f4f5df23SVikas Chaudhary 1148f4f5df23SVikas Chaudhary kfree(buf); 1149f4f5df23SVikas Chaudhary 1150f4f5df23SVikas Chaudhary /* Resetting the data and instruction cache */ 1151f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1152f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1153f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1154f4f5df23SVikas Chaudhary 1155f4f5df23SVikas Chaudhary /* Clear all protocol processing engines */ 1156f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1157f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1158f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1159f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1160f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1161f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1162f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1163f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1164f4f5df23SVikas Chaudhary 1165f4f5df23SVikas Chaudhary return 0; 1166f4f5df23SVikas Chaudhary } 1167f4f5df23SVikas Chaudhary 1168dd3b854eSVikas Chaudhary /** 1169dd3b854eSVikas Chaudhary * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory 1170dd3b854eSVikas Chaudhary * @ha: Pointer to adapter structure 1171dd3b854eSVikas Chaudhary * @addr: Flash address to write to 1172dd3b854eSVikas Chaudhary * @data: Data to be written 1173dd3b854eSVikas Chaudhary * @count: word_count to be written 1174dd3b854eSVikas Chaudhary * 1175dd3b854eSVikas Chaudhary * Return: On success return QLA_SUCCESS 1176dd3b854eSVikas Chaudhary * On error return QLA_ERROR 1177dd3b854eSVikas Chaudhary **/ 1178dd3b854eSVikas Chaudhary int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr, 1179dd3b854eSVikas Chaudhary uint32_t *data, uint32_t count) 1180dd3b854eSVikas Chaudhary { 1181dd3b854eSVikas Chaudhary int i, j; 1182dd3b854eSVikas Chaudhary uint32_t agt_ctrl; 1183dd3b854eSVikas Chaudhary unsigned long flags; 1184dd3b854eSVikas Chaudhary int ret_val = QLA_SUCCESS; 1185dd3b854eSVikas Chaudhary 1186dd3b854eSVikas Chaudhary /* Only 128-bit aligned access */ 1187dd3b854eSVikas Chaudhary if (addr & 0xF) { 1188dd3b854eSVikas Chaudhary ret_val = QLA_ERROR; 1189dd3b854eSVikas Chaudhary goto exit_ms_mem_write; 1190dd3b854eSVikas Chaudhary } 1191dd3b854eSVikas Chaudhary 1192dd3b854eSVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 1193dd3b854eSVikas Chaudhary 1194dd3b854eSVikas Chaudhary /* Write address */ 1195dd3b854eSVikas Chaudhary ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0); 1196dd3b854eSVikas Chaudhary if (ret_val == QLA_ERROR) { 1197dd3b854eSVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n", 1198dd3b854eSVikas Chaudhary __func__); 1199dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1200dd3b854eSVikas Chaudhary } 1201dd3b854eSVikas Chaudhary 1202dd3b854eSVikas Chaudhary for (i = 0; i < count; i++, addr += 16) { 1203dd3b854eSVikas Chaudhary if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 1204dd3b854eSVikas Chaudhary QLA8XXX_ADDR_QDR_NET_MAX)) || 1205dd3b854eSVikas Chaudhary (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 1206dd3b854eSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX)))) { 1207dd3b854eSVikas Chaudhary ret_val = QLA_ERROR; 1208dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1209dd3b854eSVikas Chaudhary } 1210dd3b854eSVikas Chaudhary 1211dd3b854eSVikas Chaudhary ret_val = ha->isp_ops->wr_reg_indirect(ha, 1212dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_ADDR_LO, 1213dd3b854eSVikas Chaudhary addr); 1214dd3b854eSVikas Chaudhary /* Write data */ 1215dd3b854eSVikas Chaudhary ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1216dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_WRDATA_LO, 1217dd3b854eSVikas Chaudhary *data++); 1218dd3b854eSVikas Chaudhary ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1219dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_WRDATA_HI, 1220dd3b854eSVikas Chaudhary *data++); 1221dd3b854eSVikas Chaudhary ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1222dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_WRDATA_ULO, 1223dd3b854eSVikas Chaudhary *data++); 1224dd3b854eSVikas Chaudhary ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1225dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_WRDATA_UHI, 1226dd3b854eSVikas Chaudhary *data++); 1227dd3b854eSVikas Chaudhary if (ret_val == QLA_ERROR) { 1228dd3b854eSVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n", 1229dd3b854eSVikas Chaudhary __func__); 1230dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1231dd3b854eSVikas Chaudhary } 1232dd3b854eSVikas Chaudhary 1233dd3b854eSVikas Chaudhary /* Check write status */ 1234dd3b854eSVikas Chaudhary ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, 1235dd3b854eSVikas Chaudhary MIU_TA_CTL_WRITE_ENABLE); 1236dd3b854eSVikas Chaudhary ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1237dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_CTRL, 1238dd3b854eSVikas Chaudhary MIU_TA_CTL_WRITE_START); 1239dd3b854eSVikas Chaudhary if (ret_val == QLA_ERROR) { 1240dd3b854eSVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n", 1241dd3b854eSVikas Chaudhary __func__); 1242dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1243dd3b854eSVikas Chaudhary } 1244dd3b854eSVikas Chaudhary 1245dd3b854eSVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1246dd3b854eSVikas Chaudhary ret_val = ha->isp_ops->rd_reg_indirect(ha, 1247dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_CTRL, 1248dd3b854eSVikas Chaudhary &agt_ctrl); 1249dd3b854eSVikas Chaudhary if (ret_val == QLA_ERROR) { 1250dd3b854eSVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n", 1251dd3b854eSVikas Chaudhary __func__); 1252dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1253dd3b854eSVikas Chaudhary } 1254dd3b854eSVikas Chaudhary if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0) 1255dd3b854eSVikas Chaudhary break; 1256dd3b854eSVikas Chaudhary } 1257dd3b854eSVikas Chaudhary 1258dd3b854eSVikas Chaudhary /* Status check failed */ 1259dd3b854eSVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1260dd3b854eSVikas Chaudhary printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n", 1261dd3b854eSVikas Chaudhary __func__); 1262dd3b854eSVikas Chaudhary ret_val = QLA_ERROR; 1263dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1264dd3b854eSVikas Chaudhary } 1265dd3b854eSVikas Chaudhary } 1266dd3b854eSVikas Chaudhary 1267dd3b854eSVikas Chaudhary exit_ms_mem_write_unlock: 1268dd3b854eSVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 1269dd3b854eSVikas Chaudhary 1270dd3b854eSVikas Chaudhary exit_ms_mem_write: 1271dd3b854eSVikas Chaudhary return ret_val; 1272dd3b854eSVikas Chaudhary } 1273dd3b854eSVikas Chaudhary 1274f4f5df23SVikas Chaudhary static int 1275f8086f4fSVikas Chaudhary qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) 1276f4f5df23SVikas Chaudhary { 12774cd83cbeSLalit Chandivade int i, rval = 0; 1278f4f5df23SVikas Chaudhary long size = 0; 1279f4f5df23SVikas Chaudhary long flashaddr, memaddr; 1280f4f5df23SVikas Chaudhary u64 data; 1281f4f5df23SVikas Chaudhary u32 high, low; 1282f4f5df23SVikas Chaudhary 1283f4f5df23SVikas Chaudhary flashaddr = memaddr = ha->hw.flt_region_bootload; 1284f4f5df23SVikas Chaudhary size = (image_start - flashaddr) / 8; 1285f4f5df23SVikas Chaudhary 1286f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", 1287f4f5df23SVikas Chaudhary ha->host_no, __func__, flashaddr, image_start)); 1288f4f5df23SVikas Chaudhary 1289f4f5df23SVikas Chaudhary for (i = 0; i < size; i++) { 1290f8086f4fSVikas Chaudhary if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1291f8086f4fSVikas Chaudhary (qla4_82xx_rom_fast_read(ha, flashaddr + 4, 1292f4f5df23SVikas Chaudhary (int *)&high))) { 12934cd83cbeSLalit Chandivade rval = -1; 12944cd83cbeSLalit Chandivade goto exit_load_from_flash; 1295f4f5df23SVikas Chaudhary } 1296f4f5df23SVikas Chaudhary data = ((u64)high << 32) | low ; 1297f8086f4fSVikas Chaudhary rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 12984cd83cbeSLalit Chandivade if (rval) 12994cd83cbeSLalit Chandivade goto exit_load_from_flash; 13004cd83cbeSLalit Chandivade 1301f4f5df23SVikas Chaudhary flashaddr += 8; 1302f4f5df23SVikas Chaudhary memaddr += 8; 1303f4f5df23SVikas Chaudhary 1304f4f5df23SVikas Chaudhary if (i % 0x1000 == 0) 1305f4f5df23SVikas Chaudhary msleep(1); 1306f4f5df23SVikas Chaudhary 1307f4f5df23SVikas Chaudhary } 1308f4f5df23SVikas Chaudhary 1309f4f5df23SVikas Chaudhary udelay(100); 1310f4f5df23SVikas Chaudhary 1311f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1312f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1313f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1314f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1315f4f5df23SVikas Chaudhary 13164cd83cbeSLalit Chandivade exit_load_from_flash: 13174cd83cbeSLalit Chandivade return rval; 1318f4f5df23SVikas Chaudhary } 1319f4f5df23SVikas Chaudhary 1320f8086f4fSVikas Chaudhary static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) 1321f4f5df23SVikas Chaudhary { 1322f4f5df23SVikas Chaudhary u32 rst; 1323f4f5df23SVikas Chaudhary 1324f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1325f8086f4fSVikas Chaudhary if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { 1326f4f5df23SVikas Chaudhary printk(KERN_WARNING "%s: Error during CRB Initialization\n", 1327f4f5df23SVikas Chaudhary __func__); 1328f4f5df23SVikas Chaudhary return QLA_ERROR; 1329f4f5df23SVikas Chaudhary } 1330f4f5df23SVikas Chaudhary 1331f4f5df23SVikas Chaudhary udelay(500); 1332f4f5df23SVikas Chaudhary 1333f4f5df23SVikas Chaudhary /* at this point, QM is in reset. This could be a problem if there are 1334f4f5df23SVikas Chaudhary * incoming d* transition queue messages. QM/PCIE could wedge. 1335f4f5df23SVikas Chaudhary * To get around this, QM is brought out of reset. 1336f4f5df23SVikas Chaudhary */ 1337f4f5df23SVikas Chaudhary 1338f8086f4fSVikas Chaudhary rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 1339f4f5df23SVikas Chaudhary /* unreset qm */ 1340f4f5df23SVikas Chaudhary rst &= ~(1 << 28); 1341f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 1342f4f5df23SVikas Chaudhary 1343f8086f4fSVikas Chaudhary if (qla4_82xx_load_from_flash(ha, image_start)) { 1344f4f5df23SVikas Chaudhary printk("%s: Error trying to load fw from flash!\n", __func__); 1345f4f5df23SVikas Chaudhary return QLA_ERROR; 1346f4f5df23SVikas Chaudhary } 1347f4f5df23SVikas Chaudhary 1348f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1349f4f5df23SVikas Chaudhary } 1350f4f5df23SVikas Chaudhary 1351f4f5df23SVikas Chaudhary int 1352f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha, 1353f4f5df23SVikas Chaudhary u64 off, void *data, int size) 1354f4f5df23SVikas Chaudhary { 1355f4f5df23SVikas Chaudhary int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1356f4f5df23SVikas Chaudhary int shift_amount; 1357f4f5df23SVikas Chaudhary uint32_t temp; 1358f4f5df23SVikas Chaudhary uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1359f4f5df23SVikas Chaudhary 1360f4f5df23SVikas Chaudhary /* 1361f4f5df23SVikas Chaudhary * If not MN, go check for MS or invalid. 1362f4f5df23SVikas Chaudhary */ 1363f4f5df23SVikas Chaudhary 1364de8c72daSVikas Chaudhary if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1365f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_QDR_NET; 1366f4f5df23SVikas Chaudhary else { 1367f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_DDR_NET; 1368f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) 1369f8086f4fSVikas Chaudhary return qla4_82xx_pci_mem_read_direct(ha, 1370f4f5df23SVikas Chaudhary off, data, size); 1371f4f5df23SVikas Chaudhary } 1372f4f5df23SVikas Chaudhary 1373f4f5df23SVikas Chaudhary 1374f4f5df23SVikas Chaudhary off8 = off & 0xfffffff0; 1375f4f5df23SVikas Chaudhary off0[0] = off & 0xf; 1376f4f5df23SVikas Chaudhary sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1377f4f5df23SVikas Chaudhary shift_amount = 4; 1378f4f5df23SVikas Chaudhary 1379f4f5df23SVikas Chaudhary loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1380f4f5df23SVikas Chaudhary off0[1] = 0; 1381f4f5df23SVikas Chaudhary sz[1] = size - sz[0]; 1382f4f5df23SVikas Chaudhary 1383f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1384f4f5df23SVikas Chaudhary temp = off8 + (i << shift_amount); 1385f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1386f4f5df23SVikas Chaudhary temp = 0; 1387f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1388f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_ENABLE; 1389f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1390c38fa3abSVikas Chaudhary temp = MIU_TA_CTL_START_ENABLE; 1391f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1392f4f5df23SVikas Chaudhary 1393f4f5df23SVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1394f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1395f4f5df23SVikas Chaudhary if ((temp & MIU_TA_CTL_BUSY) == 0) 1396f4f5df23SVikas Chaudhary break; 1397f4f5df23SVikas Chaudhary } 1398f4f5df23SVikas Chaudhary 1399f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1400068237c8STej Parkash printk_ratelimited(KERN_ERR 1401068237c8STej Parkash "%s: failed to read through agent\n", 1402068237c8STej Parkash __func__); 1403f4f5df23SVikas Chaudhary break; 1404f4f5df23SVikas Chaudhary } 1405f4f5df23SVikas Chaudhary 1406f4f5df23SVikas Chaudhary start = off0[i] >> 2; 1407f4f5df23SVikas Chaudhary end = (off0[i] + sz[i] - 1) >> 2; 1408f4f5df23SVikas Chaudhary for (k = start; k <= end; k++) { 1409f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, 1410f4f5df23SVikas Chaudhary mem_crb + MIU_TEST_AGT_RDDATA(k)); 1411f4f5df23SVikas Chaudhary word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1412f4f5df23SVikas Chaudhary } 1413f4f5df23SVikas Chaudhary } 1414f4f5df23SVikas Chaudhary 1415f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) 1416f4f5df23SVikas Chaudhary return -1; 1417f4f5df23SVikas Chaudhary 1418f4f5df23SVikas Chaudhary if ((off0[0] & 7) == 0) { 1419f4f5df23SVikas Chaudhary val = word[0]; 1420f4f5df23SVikas Chaudhary } else { 1421f4f5df23SVikas Chaudhary val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1422f4f5df23SVikas Chaudhary ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1423f4f5df23SVikas Chaudhary } 1424f4f5df23SVikas Chaudhary 1425f4f5df23SVikas Chaudhary switch (size) { 1426f4f5df23SVikas Chaudhary case 1: 1427f4f5df23SVikas Chaudhary *(uint8_t *)data = val; 1428f4f5df23SVikas Chaudhary break; 1429f4f5df23SVikas Chaudhary case 2: 1430f4f5df23SVikas Chaudhary *(uint16_t *)data = val; 1431f4f5df23SVikas Chaudhary break; 1432f4f5df23SVikas Chaudhary case 4: 1433f4f5df23SVikas Chaudhary *(uint32_t *)data = val; 1434f4f5df23SVikas Chaudhary break; 1435f4f5df23SVikas Chaudhary case 8: 1436f4f5df23SVikas Chaudhary *(uint64_t *)data = val; 1437f4f5df23SVikas Chaudhary break; 1438f4f5df23SVikas Chaudhary } 1439f4f5df23SVikas Chaudhary return 0; 1440f4f5df23SVikas Chaudhary } 1441f4f5df23SVikas Chaudhary 1442f4f5df23SVikas Chaudhary int 1443f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, 1444f4f5df23SVikas Chaudhary u64 off, void *data, int size) 1445f4f5df23SVikas Chaudhary { 1446f4f5df23SVikas Chaudhary int i, j, ret = 0, loop, sz[2], off0; 1447f4f5df23SVikas Chaudhary int scale, shift_amount, startword; 1448f4f5df23SVikas Chaudhary uint32_t temp; 1449f4f5df23SVikas Chaudhary uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1450f4f5df23SVikas Chaudhary 1451f4f5df23SVikas Chaudhary /* 1452f4f5df23SVikas Chaudhary * If not MN, go check for MS or invalid. 1453f4f5df23SVikas Chaudhary */ 1454de8c72daSVikas Chaudhary if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1455f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_QDR_NET; 1456f4f5df23SVikas Chaudhary else { 1457f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_DDR_NET; 1458f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) 1459f8086f4fSVikas Chaudhary return qla4_82xx_pci_mem_write_direct(ha, 1460f4f5df23SVikas Chaudhary off, data, size); 1461f4f5df23SVikas Chaudhary } 1462f4f5df23SVikas Chaudhary 1463f4f5df23SVikas Chaudhary off0 = off & 0x7; 1464f4f5df23SVikas Chaudhary sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1465f4f5df23SVikas Chaudhary sz[1] = size - sz[0]; 1466f4f5df23SVikas Chaudhary 1467f4f5df23SVikas Chaudhary off8 = off & 0xfffffff0; 1468f4f5df23SVikas Chaudhary loop = (((off & 0xf) + size - 1) >> 4) + 1; 1469f4f5df23SVikas Chaudhary shift_amount = 4; 1470f4f5df23SVikas Chaudhary scale = 2; 1471f4f5df23SVikas Chaudhary startword = (off & 0xf)/8; 1472f4f5df23SVikas Chaudhary 1473f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1474f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_read_2M(ha, off8 + 1475f4f5df23SVikas Chaudhary (i << shift_amount), &word[i * scale], 8)) 1476f4f5df23SVikas Chaudhary return -1; 1477f4f5df23SVikas Chaudhary } 1478f4f5df23SVikas Chaudhary 1479f4f5df23SVikas Chaudhary switch (size) { 1480f4f5df23SVikas Chaudhary case 1: 1481f4f5df23SVikas Chaudhary tmpw = *((uint8_t *)data); 1482f4f5df23SVikas Chaudhary break; 1483f4f5df23SVikas Chaudhary case 2: 1484f4f5df23SVikas Chaudhary tmpw = *((uint16_t *)data); 1485f4f5df23SVikas Chaudhary break; 1486f4f5df23SVikas Chaudhary case 4: 1487f4f5df23SVikas Chaudhary tmpw = *((uint32_t *)data); 1488f4f5df23SVikas Chaudhary break; 1489f4f5df23SVikas Chaudhary case 8: 1490f4f5df23SVikas Chaudhary default: 1491f4f5df23SVikas Chaudhary tmpw = *((uint64_t *)data); 1492f4f5df23SVikas Chaudhary break; 1493f4f5df23SVikas Chaudhary } 1494f4f5df23SVikas Chaudhary 1495f4f5df23SVikas Chaudhary if (sz[0] == 8) 1496f4f5df23SVikas Chaudhary word[startword] = tmpw; 1497f4f5df23SVikas Chaudhary else { 1498f4f5df23SVikas Chaudhary word[startword] &= 1499f4f5df23SVikas Chaudhary ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1500f4f5df23SVikas Chaudhary word[startword] |= tmpw << (off0 * 8); 1501f4f5df23SVikas Chaudhary } 1502f4f5df23SVikas Chaudhary 1503f4f5df23SVikas Chaudhary if (sz[1] != 0) { 1504f4f5df23SVikas Chaudhary word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1505f4f5df23SVikas Chaudhary word[startword+1] |= tmpw >> (sz[0] * 8); 1506f4f5df23SVikas Chaudhary } 1507f4f5df23SVikas Chaudhary 1508f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1509f4f5df23SVikas Chaudhary temp = off8 + (i << shift_amount); 1510f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1511f4f5df23SVikas Chaudhary temp = 0; 1512f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1513f4f5df23SVikas Chaudhary temp = word[i * scale] & 0xffffffff; 1514f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1515f4f5df23SVikas Chaudhary temp = (word[i * scale] >> 32) & 0xffffffff; 1516f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1517f4f5df23SVikas Chaudhary temp = word[i*scale + 1] & 0xffffffff; 1518f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, 1519f4f5df23SVikas Chaudhary temp); 1520f4f5df23SVikas Chaudhary temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1521f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, 1522f4f5df23SVikas Chaudhary temp); 1523f4f5df23SVikas Chaudhary 1524c38fa3abSVikas Chaudhary temp = MIU_TA_CTL_WRITE_ENABLE; 1525f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1526c38fa3abSVikas Chaudhary temp = MIU_TA_CTL_WRITE_START; 1527f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1528f4f5df23SVikas Chaudhary 1529f4f5df23SVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1530f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1531f4f5df23SVikas Chaudhary if ((temp & MIU_TA_CTL_BUSY) == 0) 1532f4f5df23SVikas Chaudhary break; 1533f4f5df23SVikas Chaudhary } 1534f4f5df23SVikas Chaudhary 1535f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1536f4f5df23SVikas Chaudhary if (printk_ratelimit()) 1537f4f5df23SVikas Chaudhary ql4_printk(KERN_ERR, ha, 1538068237c8STej Parkash "%s: failed to read through agent\n", 1539068237c8STej Parkash __func__); 1540f4f5df23SVikas Chaudhary ret = -1; 1541f4f5df23SVikas Chaudhary break; 1542f4f5df23SVikas Chaudhary } 1543f4f5df23SVikas Chaudhary } 1544f4f5df23SVikas Chaudhary 1545f4f5df23SVikas Chaudhary return ret; 1546f4f5df23SVikas Chaudhary } 1547f4f5df23SVikas Chaudhary 1548f8086f4fSVikas Chaudhary static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) 1549f4f5df23SVikas Chaudhary { 1550f4f5df23SVikas Chaudhary u32 val = 0; 1551f4f5df23SVikas Chaudhary int retries = 60; 1552f4f5df23SVikas Chaudhary 1553f4f5df23SVikas Chaudhary if (!pegtune_val) { 1554f4f5df23SVikas Chaudhary do { 1555f8086f4fSVikas Chaudhary val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE); 1556f4f5df23SVikas Chaudhary if ((val == PHAN_INITIALIZE_COMPLETE) || 1557f4f5df23SVikas Chaudhary (val == PHAN_INITIALIZE_ACK)) 1558f4f5df23SVikas Chaudhary return 0; 1559f4f5df23SVikas Chaudhary set_current_state(TASK_UNINTERRUPTIBLE); 1560f4f5df23SVikas Chaudhary schedule_timeout(500); 1561f4f5df23SVikas Chaudhary 1562f4f5df23SVikas Chaudhary } while (--retries); 1563f4f5df23SVikas Chaudhary 1564f4f5df23SVikas Chaudhary if (!retries) { 1565f8086f4fSVikas Chaudhary pegtune_val = qla4_82xx_rd_32(ha, 1566f4f5df23SVikas Chaudhary QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1567f4f5df23SVikas Chaudhary printk(KERN_WARNING "%s: init failed, " 1568f4f5df23SVikas Chaudhary "pegtune_val = %x\n", __func__, pegtune_val); 1569f4f5df23SVikas Chaudhary return -1; 1570f4f5df23SVikas Chaudhary } 1571f4f5df23SVikas Chaudhary } 1572f4f5df23SVikas Chaudhary return 0; 1573f4f5df23SVikas Chaudhary } 1574f4f5df23SVikas Chaudhary 1575f8086f4fSVikas Chaudhary static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha) 1576f4f5df23SVikas Chaudhary { 1577f4f5df23SVikas Chaudhary uint32_t state = 0; 1578f4f5df23SVikas Chaudhary int loops = 0; 1579f4f5df23SVikas Chaudhary 1580f4f5df23SVikas Chaudhary /* Window 1 call */ 1581f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1582f8086f4fSVikas Chaudhary state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); 1583f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1584f4f5df23SVikas Chaudhary 1585f4f5df23SVikas Chaudhary while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { 1586f4f5df23SVikas Chaudhary udelay(100); 1587f4f5df23SVikas Chaudhary /* Window 1 call */ 1588f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1589f8086f4fSVikas Chaudhary state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); 1590f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1591f4f5df23SVikas Chaudhary 1592f4f5df23SVikas Chaudhary loops++; 1593f4f5df23SVikas Chaudhary } 1594f4f5df23SVikas Chaudhary 1595f4f5df23SVikas Chaudhary if (loops >= 30000) { 1596f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 1597f4f5df23SVikas Chaudhary "Receive Peg initialization not complete: 0x%x.\n", state)); 1598f4f5df23SVikas Chaudhary return QLA_ERROR; 1599f4f5df23SVikas Chaudhary } 1600f4f5df23SVikas Chaudhary 1601f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1602f4f5df23SVikas Chaudhary } 1603f4f5df23SVikas Chaudhary 1604626115cdSAndrew Morton void 1605f4f5df23SVikas Chaudhary qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) 1606f4f5df23SVikas Chaudhary { 1607f4f5df23SVikas Chaudhary uint32_t drv_active; 1608f4f5df23SVikas Chaudhary 160933693c7aSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 16106e7b4292SVikas Chaudhary 16116e7b4292SVikas Chaudhary /* 1612b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 16136e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 16146e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 16156e7b4292SVikas Chaudhary */ 1616b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 16176e7b4292SVikas Chaudhary drv_active |= (1 << ha->func_num); 16186e7b4292SVikas Chaudhary else 1619f4f5df23SVikas Chaudhary drv_active |= (1 << (ha->func_num * 4)); 16206e7b4292SVikas Chaudhary 1621068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1622068237c8STej Parkash __func__, ha->host_no, drv_active); 162333693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); 1624f4f5df23SVikas Chaudhary } 1625f4f5df23SVikas Chaudhary 1626f4f5df23SVikas Chaudhary void 1627f4f5df23SVikas Chaudhary qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) 1628f4f5df23SVikas Chaudhary { 1629f4f5df23SVikas Chaudhary uint32_t drv_active; 1630f4f5df23SVikas Chaudhary 163133693c7aSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 16326e7b4292SVikas Chaudhary 16336e7b4292SVikas Chaudhary /* 1634b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 16356e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 16366e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 16376e7b4292SVikas Chaudhary */ 1638b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 16396e7b4292SVikas Chaudhary drv_active &= ~(1 << (ha->func_num)); 16406e7b4292SVikas Chaudhary else 1641f4f5df23SVikas Chaudhary drv_active &= ~(1 << (ha->func_num * 4)); 16426e7b4292SVikas Chaudhary 1643068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1644068237c8STej Parkash __func__, ha->host_no, drv_active); 164533693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); 1646f4f5df23SVikas Chaudhary } 1647f4f5df23SVikas Chaudhary 164833693c7aSVikas Chaudhary inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha) 1649f4f5df23SVikas Chaudhary { 16502232be0dSLalit Chandivade uint32_t drv_state, drv_active; 1651f4f5df23SVikas Chaudhary int rval; 1652f4f5df23SVikas Chaudhary 165333693c7aSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 165433693c7aSVikas Chaudhary drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 16556e7b4292SVikas Chaudhary 16566e7b4292SVikas Chaudhary /* 1657b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 16586e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 16596e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 16606e7b4292SVikas Chaudhary */ 1661b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 16626e7b4292SVikas Chaudhary rval = drv_state & (1 << ha->func_num); 16636e7b4292SVikas Chaudhary else 1664f4f5df23SVikas Chaudhary rval = drv_state & (1 << (ha->func_num * 4)); 16656e7b4292SVikas Chaudhary 16662232be0dSLalit Chandivade if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 16672232be0dSLalit Chandivade rval = 1; 16682232be0dSLalit Chandivade 1669f4f5df23SVikas Chaudhary return rval; 1670f4f5df23SVikas Chaudhary } 1671f4f5df23SVikas Chaudhary 16726e7b4292SVikas Chaudhary void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) 1673f4f5df23SVikas Chaudhary { 1674f4f5df23SVikas Chaudhary uint32_t drv_state; 1675f4f5df23SVikas Chaudhary 167633693c7aSVikas Chaudhary drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 16776e7b4292SVikas Chaudhary 16786e7b4292SVikas Chaudhary /* 1679b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 16806e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 16816e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 16826e7b4292SVikas Chaudhary */ 1683b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 16846e7b4292SVikas Chaudhary drv_state |= (1 << ha->func_num); 16856e7b4292SVikas Chaudhary else 1686f4f5df23SVikas Chaudhary drv_state |= (1 << (ha->func_num * 4)); 16876e7b4292SVikas Chaudhary 1688068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1689068237c8STej Parkash __func__, ha->host_no, drv_state); 169033693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); 1691f4f5df23SVikas Chaudhary } 1692f4f5df23SVikas Chaudhary 16936e7b4292SVikas Chaudhary void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) 1694f4f5df23SVikas Chaudhary { 1695f4f5df23SVikas Chaudhary uint32_t drv_state; 1696f4f5df23SVikas Chaudhary 169733693c7aSVikas Chaudhary drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 16986e7b4292SVikas Chaudhary 16996e7b4292SVikas Chaudhary /* 1700b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 17016e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 17026e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 17036e7b4292SVikas Chaudhary */ 1704b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 17056e7b4292SVikas Chaudhary drv_state &= ~(1 << ha->func_num); 17066e7b4292SVikas Chaudhary else 1707f4f5df23SVikas Chaudhary drv_state &= ~(1 << (ha->func_num * 4)); 17086e7b4292SVikas Chaudhary 1709068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1710068237c8STej Parkash __func__, ha->host_no, drv_state); 171133693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); 1712f4f5df23SVikas Chaudhary } 1713f4f5df23SVikas Chaudhary 1714f4f5df23SVikas Chaudhary static inline void 1715f4f5df23SVikas Chaudhary qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) 1716f4f5df23SVikas Chaudhary { 1717f4f5df23SVikas Chaudhary uint32_t qsnt_state; 1718f4f5df23SVikas Chaudhary 171933693c7aSVikas Chaudhary qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 17206e7b4292SVikas Chaudhary 17216e7b4292SVikas Chaudhary /* 1722b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 17236e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 17246e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function. 17256e7b4292SVikas Chaudhary */ 1726b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 17276e7b4292SVikas Chaudhary qsnt_state |= (1 << ha->func_num); 17286e7b4292SVikas Chaudhary else 1729f4f5df23SVikas Chaudhary qsnt_state |= (2 << (ha->func_num * 4)); 17306e7b4292SVikas Chaudhary 173133693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state); 1732f4f5df23SVikas Chaudhary } 1733f4f5df23SVikas Chaudhary 1734f4f5df23SVikas Chaudhary 1735f4f5df23SVikas Chaudhary static int 1736f8086f4fSVikas Chaudhary qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) 1737f4f5df23SVikas Chaudhary { 1738f4f5df23SVikas Chaudhary uint16_t lnk; 1739f4f5df23SVikas Chaudhary 1740f4f5df23SVikas Chaudhary /* scrub dma mask expansion register */ 1741f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 1742f4f5df23SVikas Chaudhary 1743f4f5df23SVikas Chaudhary /* Overwrite stale initialization register values */ 1744f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1745f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 1746f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 1747f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 1748f4f5df23SVikas Chaudhary 1749f8086f4fSVikas Chaudhary if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) { 1750f4f5df23SVikas Chaudhary printk("%s: Error trying to start fw!\n", __func__); 1751f4f5df23SVikas Chaudhary return QLA_ERROR; 1752f4f5df23SVikas Chaudhary } 1753f4f5df23SVikas Chaudhary 1754f4f5df23SVikas Chaudhary /* Handshake with the card before we register the devices. */ 1755f8086f4fSVikas Chaudhary if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { 1756f4f5df23SVikas Chaudhary printk("%s: Error during card handshake!\n", __func__); 1757f4f5df23SVikas Chaudhary return QLA_ERROR; 1758f4f5df23SVikas Chaudhary } 1759f4f5df23SVikas Chaudhary 1760f4f5df23SVikas Chaudhary /* Negotiated Link width */ 17615548bfd0SJiang Liu pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 1762f4f5df23SVikas Chaudhary ha->link_width = (lnk >> 4) & 0x3f; 1763f4f5df23SVikas Chaudhary 1764f4f5df23SVikas Chaudhary /* Synchronize with Receive peg */ 1765f8086f4fSVikas Chaudhary return qla4_82xx_rcvpeg_ready(ha); 1766f4f5df23SVikas Chaudhary } 1767f4f5df23SVikas Chaudhary 176833693c7aSVikas Chaudhary int qla4_82xx_try_start_fw(struct scsi_qla_host *ha) 1769f4f5df23SVikas Chaudhary { 1770*3a5b9fa2SColin Ian King int rval; 1771f4f5df23SVikas Chaudhary 1772f4f5df23SVikas Chaudhary /* 1773f4f5df23SVikas Chaudhary * FW Load priority: 1774f4f5df23SVikas Chaudhary * 1) Operational firmware residing in flash. 1775f4f5df23SVikas Chaudhary * 2) Fail 1776f4f5df23SVikas Chaudhary */ 1777f4f5df23SVikas Chaudhary 1778f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1779f4f5df23SVikas Chaudhary "FW: Retrieving flash offsets from FLT/FDT ...\n"); 1780f4f5df23SVikas Chaudhary rval = qla4_8xxx_get_flash_info(ha); 1781f4f5df23SVikas Chaudhary if (rval != QLA_SUCCESS) 1782f4f5df23SVikas Chaudhary return rval; 1783f4f5df23SVikas Chaudhary 1784f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1785f4f5df23SVikas Chaudhary "FW: Attempting to load firmware from flash...\n"); 1786f8086f4fSVikas Chaudhary rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw); 1787f4f5df23SVikas Chaudhary 1788f581a3f7SVikas Chaudhary if (rval != QLA_SUCCESS) { 1789f581a3f7SVikas Chaudhary ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" 1790f581a3f7SVikas Chaudhary " FAILED...\n"); 1791f581a3f7SVikas Chaudhary return rval; 1792f581a3f7SVikas Chaudhary } 1793f4f5df23SVikas Chaudhary 1794f4f5df23SVikas Chaudhary return rval; 1795f4f5df23SVikas Chaudhary } 1796f4f5df23SVikas Chaudhary 179733693c7aSVikas Chaudhary void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha) 1798b25ee66fSShyam Sundar { 1799f8086f4fSVikas Chaudhary if (qla4_82xx_rom_lock(ha)) { 1800b25ee66fSShyam Sundar /* Someone else is holding the lock. */ 1801b25ee66fSShyam Sundar dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); 1802b25ee66fSShyam Sundar } 1803b25ee66fSShyam Sundar 1804b25ee66fSShyam Sundar /* 1805b25ee66fSShyam Sundar * Either we got the lock, or someone 1806b25ee66fSShyam Sundar * else died while holding it. 1807b25ee66fSShyam Sundar * In either case, unlock. 1808b25ee66fSShyam Sundar */ 1809f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 1810b25ee66fSShyam Sundar } 1811b25ee66fSShyam Sundar 1812b1829789STej Parkash static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha, 1813b1829789STej Parkash uint32_t addr1, uint32_t mask) 1814b1829789STej Parkash { 1815b1829789STej Parkash unsigned long timeout; 1816b1829789STej Parkash uint32_t rval = QLA_SUCCESS; 1817b1829789STej Parkash uint32_t temp; 1818b1829789STej Parkash 1819b1829789STej Parkash timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); 1820b1829789STej Parkash do { 1821b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 1822b1829789STej Parkash if ((temp & mask) != 0) 1823b1829789STej Parkash break; 1824b1829789STej Parkash 1825b1829789STej Parkash if (time_after_eq(jiffies, timeout)) { 1826b1829789STej Parkash ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n"); 1827b1829789STej Parkash return QLA_ERROR; 1828b1829789STej Parkash } 1829b1829789STej Parkash } while (1); 1830b1829789STej Parkash 1831b1829789STej Parkash return rval; 1832b1829789STej Parkash } 1833b1829789STej Parkash 183402ccda2aSBaoyou Xie static uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1, 1835b1829789STej Parkash uint32_t addr3, uint32_t mask, uint32_t addr, 1836b1829789STej Parkash uint32_t *data_ptr) 1837b1829789STej Parkash { 1838b1829789STej Parkash int rval = QLA_SUCCESS; 1839b1829789STej Parkash uint32_t temp; 1840b1829789STej Parkash uint32_t data; 1841b1829789STej Parkash 1842b1829789STej Parkash rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1843b1829789STej Parkash if (rval) 1844b1829789STej Parkash goto exit_ipmdio_rd_reg; 1845b1829789STej Parkash 1846b1829789STej Parkash temp = (0x40000000 | addr); 1847b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, temp); 1848b1829789STej Parkash 1849b1829789STej Parkash rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1850b1829789STej Parkash if (rval) 1851b1829789STej Parkash goto exit_ipmdio_rd_reg; 1852b1829789STej Parkash 1853b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr3, &data); 1854b1829789STej Parkash *data_ptr = data; 1855b1829789STej Parkash 1856b1829789STej Parkash exit_ipmdio_rd_reg: 1857b1829789STej Parkash return rval; 1858b1829789STej Parkash } 1859b1829789STej Parkash 1860b1829789STej Parkash 1861b1829789STej Parkash static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha, 1862b1829789STej Parkash uint32_t addr1, 1863b1829789STej Parkash uint32_t addr2, 1864b1829789STej Parkash uint32_t addr3, 1865b1829789STej Parkash uint32_t mask) 1866b1829789STej Parkash { 1867b1829789STej Parkash unsigned long timeout; 1868b1829789STej Parkash uint32_t temp; 1869b1829789STej Parkash uint32_t rval = QLA_SUCCESS; 1870b1829789STej Parkash 1871b1829789STej Parkash timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); 1872b1829789STej Parkash do { 1873b1829789STej Parkash ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp); 1874b1829789STej Parkash if ((temp & 0x1) != 1) 1875b1829789STej Parkash break; 1876b1829789STej Parkash if (time_after_eq(jiffies, timeout)) { 1877b1829789STej Parkash ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n"); 1878b1829789STej Parkash return QLA_ERROR; 1879b1829789STej Parkash } 1880b1829789STej Parkash } while (1); 1881b1829789STej Parkash 1882b1829789STej Parkash return rval; 1883b1829789STej Parkash } 1884b1829789STej Parkash 1885b1829789STej Parkash static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha, 1886b1829789STej Parkash uint32_t addr1, uint32_t addr3, 1887b1829789STej Parkash uint32_t mask, uint32_t addr, 1888b1829789STej Parkash uint32_t value) 1889b1829789STej Parkash { 1890b1829789STej Parkash int rval = QLA_SUCCESS; 1891b1829789STej Parkash 1892b1829789STej Parkash rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1893b1829789STej Parkash if (rval) 1894b1829789STej Parkash goto exit_ipmdio_wr_reg; 1895b1829789STej Parkash 1896b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr3, value); 1897b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, addr); 1898b1829789STej Parkash 1899b1829789STej Parkash rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1900b1829789STej Parkash if (rval) 1901b1829789STej Parkash goto exit_ipmdio_wr_reg; 1902b1829789STej Parkash 1903b1829789STej Parkash exit_ipmdio_wr_reg: 1904b1829789STej Parkash return rval; 1905b1829789STej Parkash } 1906b1829789STej Parkash 1907068237c8STej Parkash static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha, 19087664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1909068237c8STej Parkash uint32_t **d_ptr) 1910068237c8STej Parkash { 1911068237c8STej Parkash uint32_t r_addr, r_stride, loop_cnt, i, r_value; 19127664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_crb *crb_hdr; 1913068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1914068237c8STej Parkash 1915068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 19167664a1fdSVikas Chaudhary crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr; 1917068237c8STej Parkash r_addr = crb_hdr->addr; 1918068237c8STej Parkash r_stride = crb_hdr->crb_strd.addr_stride; 1919068237c8STej Parkash loop_cnt = crb_hdr->op_count; 1920068237c8STej Parkash 1921068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 192233693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 1923068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_addr); 1924068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1925068237c8STej Parkash r_addr += r_stride; 1926068237c8STej Parkash } 1927068237c8STej Parkash *d_ptr = data_ptr; 1928068237c8STej Parkash } 1929068237c8STej Parkash 193041f79bdeSSantosh Vernekar static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha) 193141f79bdeSSantosh Vernekar { 193241f79bdeSSantosh Vernekar int rval = QLA_SUCCESS; 193341f79bdeSSantosh Vernekar uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 193441f79bdeSSantosh Vernekar uint64_t dma_base_addr = 0; 193541f79bdeSSantosh Vernekar struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL; 193641f79bdeSSantosh Vernekar 193741f79bdeSSantosh Vernekar tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 193841f79bdeSSantosh Vernekar ha->fw_dump_tmplt_hdr; 193941f79bdeSSantosh Vernekar dma_eng_num = 194041f79bdeSSantosh Vernekar tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX]; 194141f79bdeSSantosh Vernekar dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS + 194241f79bdeSSantosh Vernekar (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET); 194341f79bdeSSantosh Vernekar 194441f79bdeSSantosh Vernekar /* Read the pex-dma's command-status-and-control register. */ 194541f79bdeSSantosh Vernekar rval = ha->isp_ops->rd_reg_indirect(ha, 194641f79bdeSSantosh Vernekar (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL), 194741f79bdeSSantosh Vernekar &cmd_sts_and_cntrl); 194841f79bdeSSantosh Vernekar 194941f79bdeSSantosh Vernekar if (rval) 195041f79bdeSSantosh Vernekar return QLA_ERROR; 195141f79bdeSSantosh Vernekar 195241f79bdeSSantosh Vernekar /* Check if requested pex-dma engine is available. */ 195341f79bdeSSantosh Vernekar if (cmd_sts_and_cntrl & BIT_31) 195441f79bdeSSantosh Vernekar return QLA_SUCCESS; 195541f79bdeSSantosh Vernekar else 195641f79bdeSSantosh Vernekar return QLA_ERROR; 195741f79bdeSSantosh Vernekar } 195841f79bdeSSantosh Vernekar 195941f79bdeSSantosh Vernekar static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha, 196041f79bdeSSantosh Vernekar struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr) 196141f79bdeSSantosh Vernekar { 196241f79bdeSSantosh Vernekar int rval = QLA_SUCCESS, wait = 0; 196341f79bdeSSantosh Vernekar uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 196441f79bdeSSantosh Vernekar uint64_t dma_base_addr = 0; 196541f79bdeSSantosh Vernekar struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL; 196641f79bdeSSantosh Vernekar 196741f79bdeSSantosh Vernekar tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 196841f79bdeSSantosh Vernekar ha->fw_dump_tmplt_hdr; 196941f79bdeSSantosh Vernekar dma_eng_num = 197041f79bdeSSantosh Vernekar tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX]; 197141f79bdeSSantosh Vernekar dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS + 197241f79bdeSSantosh Vernekar (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET); 197341f79bdeSSantosh Vernekar 197441f79bdeSSantosh Vernekar rval = ha->isp_ops->wr_reg_indirect(ha, 197541f79bdeSSantosh Vernekar dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW, 197641f79bdeSSantosh Vernekar m_hdr->desc_card_addr); 197741f79bdeSSantosh Vernekar if (rval) 197841f79bdeSSantosh Vernekar goto error_exit; 197941f79bdeSSantosh Vernekar 198041f79bdeSSantosh Vernekar rval = ha->isp_ops->wr_reg_indirect(ha, 198141f79bdeSSantosh Vernekar dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0); 198241f79bdeSSantosh Vernekar if (rval) 198341f79bdeSSantosh Vernekar goto error_exit; 198441f79bdeSSantosh Vernekar 198541f79bdeSSantosh Vernekar rval = ha->isp_ops->wr_reg_indirect(ha, 198641f79bdeSSantosh Vernekar dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL, 198741f79bdeSSantosh Vernekar m_hdr->start_dma_cmd); 198841f79bdeSSantosh Vernekar if (rval) 198941f79bdeSSantosh Vernekar goto error_exit; 199041f79bdeSSantosh Vernekar 199141f79bdeSSantosh Vernekar /* Wait for dma operation to complete. */ 199241f79bdeSSantosh Vernekar for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) { 199341f79bdeSSantosh Vernekar rval = ha->isp_ops->rd_reg_indirect(ha, 199441f79bdeSSantosh Vernekar (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL), 199541f79bdeSSantosh Vernekar &cmd_sts_and_cntrl); 199641f79bdeSSantosh Vernekar if (rval) 199741f79bdeSSantosh Vernekar goto error_exit; 199841f79bdeSSantosh Vernekar 199941f79bdeSSantosh Vernekar if ((cmd_sts_and_cntrl & BIT_1) == 0) 200041f79bdeSSantosh Vernekar break; 200141f79bdeSSantosh Vernekar else 200241f79bdeSSantosh Vernekar udelay(10); 200341f79bdeSSantosh Vernekar } 200441f79bdeSSantosh Vernekar 200541f79bdeSSantosh Vernekar /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */ 200641f79bdeSSantosh Vernekar if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) { 200741f79bdeSSantosh Vernekar rval = QLA_ERROR; 200841f79bdeSSantosh Vernekar goto error_exit; 200941f79bdeSSantosh Vernekar } 201041f79bdeSSantosh Vernekar 201141f79bdeSSantosh Vernekar error_exit: 201241f79bdeSSantosh Vernekar return rval; 201341f79bdeSSantosh Vernekar } 201441f79bdeSSantosh Vernekar 20153c3cab17STej Parkash static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha, 201641f79bdeSSantosh Vernekar struct qla8xxx_minidump_entry_hdr *entry_hdr, 201741f79bdeSSantosh Vernekar uint32_t **d_ptr) 201841f79bdeSSantosh Vernekar { 201941f79bdeSSantosh Vernekar int rval = QLA_SUCCESS; 202041f79bdeSSantosh Vernekar struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL; 202141f79bdeSSantosh Vernekar uint32_t size, read_size; 202241f79bdeSSantosh Vernekar uint8_t *data_ptr = (uint8_t *)*d_ptr; 202341f79bdeSSantosh Vernekar void *rdmem_buffer = NULL; 202441f79bdeSSantosh Vernekar dma_addr_t rdmem_dma; 202541f79bdeSSantosh Vernekar struct qla4_83xx_pex_dma_descriptor dma_desc; 202641f79bdeSSantosh Vernekar 202741f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 202841f79bdeSSantosh Vernekar 202941f79bdeSSantosh Vernekar rval = qla4_83xx_check_dma_engine_state(ha); 203041f79bdeSSantosh Vernekar if (rval != QLA_SUCCESS) { 203141f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 203241f79bdeSSantosh Vernekar "%s: DMA engine not available. Fallback to rdmem-read.\n", 203341f79bdeSSantosh Vernekar __func__)); 203441f79bdeSSantosh Vernekar return QLA_ERROR; 203541f79bdeSSantosh Vernekar } 203641f79bdeSSantosh Vernekar 203741f79bdeSSantosh Vernekar m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr; 203841f79bdeSSantosh Vernekar rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, 203941f79bdeSSantosh Vernekar QLA83XX_PEX_DMA_READ_SIZE, 204041f79bdeSSantosh Vernekar &rdmem_dma, GFP_KERNEL); 204141f79bdeSSantosh Vernekar if (!rdmem_buffer) { 204241f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 204341f79bdeSSantosh Vernekar "%s: Unable to allocate rdmem dma buffer\n", 204441f79bdeSSantosh Vernekar __func__)); 204541f79bdeSSantosh Vernekar return QLA_ERROR; 204641f79bdeSSantosh Vernekar } 204741f79bdeSSantosh Vernekar 204841f79bdeSSantosh Vernekar /* Prepare pex-dma descriptor to be written to MS memory. */ 204941f79bdeSSantosh Vernekar /* dma-desc-cmd layout: 205041f79bdeSSantosh Vernekar * 0-3: dma-desc-cmd 0-3 205141f79bdeSSantosh Vernekar * 4-7: pcid function number 205241f79bdeSSantosh Vernekar * 8-15: dma-desc-cmd 8-15 205341f79bdeSSantosh Vernekar */ 205441f79bdeSSantosh Vernekar dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); 205541f79bdeSSantosh Vernekar dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); 205641f79bdeSSantosh Vernekar dma_desc.dma_bus_addr = rdmem_dma; 205741f79bdeSSantosh Vernekar 205841f79bdeSSantosh Vernekar size = 0; 205941f79bdeSSantosh Vernekar read_size = 0; 206041f79bdeSSantosh Vernekar /* 206141f79bdeSSantosh Vernekar * Perform rdmem operation using pex-dma. 206241f79bdeSSantosh Vernekar * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE. 206341f79bdeSSantosh Vernekar */ 206441f79bdeSSantosh Vernekar while (read_size < m_hdr->read_data_size) { 206541f79bdeSSantosh Vernekar if (m_hdr->read_data_size - read_size >= 206641f79bdeSSantosh Vernekar QLA83XX_PEX_DMA_READ_SIZE) 206741f79bdeSSantosh Vernekar size = QLA83XX_PEX_DMA_READ_SIZE; 206841f79bdeSSantosh Vernekar else { 206941f79bdeSSantosh Vernekar size = (m_hdr->read_data_size - read_size); 207041f79bdeSSantosh Vernekar 207141f79bdeSSantosh Vernekar if (rdmem_buffer) 207241f79bdeSSantosh Vernekar dma_free_coherent(&ha->pdev->dev, 207341f79bdeSSantosh Vernekar QLA83XX_PEX_DMA_READ_SIZE, 207441f79bdeSSantosh Vernekar rdmem_buffer, rdmem_dma); 207541f79bdeSSantosh Vernekar 207641f79bdeSSantosh Vernekar rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size, 207741f79bdeSSantosh Vernekar &rdmem_dma, 207841f79bdeSSantosh Vernekar GFP_KERNEL); 207941f79bdeSSantosh Vernekar if (!rdmem_buffer) { 208041f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 208141f79bdeSSantosh Vernekar "%s: Unable to allocate rdmem dma buffer\n", 208241f79bdeSSantosh Vernekar __func__)); 208341f79bdeSSantosh Vernekar return QLA_ERROR; 208441f79bdeSSantosh Vernekar } 208541f79bdeSSantosh Vernekar dma_desc.dma_bus_addr = rdmem_dma; 208641f79bdeSSantosh Vernekar } 208741f79bdeSSantosh Vernekar 208841f79bdeSSantosh Vernekar dma_desc.src_addr = m_hdr->read_addr + read_size; 208941f79bdeSSantosh Vernekar dma_desc.cmd.read_data_size = size; 209041f79bdeSSantosh Vernekar 209141f79bdeSSantosh Vernekar /* Prepare: Write pex-dma descriptor to MS memory. */ 20923c3cab17STej Parkash rval = qla4_8xxx_ms_mem_write_128b(ha, 209341f79bdeSSantosh Vernekar (uint64_t)m_hdr->desc_card_addr, 209441f79bdeSSantosh Vernekar (uint32_t *)&dma_desc, 209541f79bdeSSantosh Vernekar (sizeof(struct qla4_83xx_pex_dma_descriptor)/16)); 20969c4f8d92SVikas Chaudhary if (rval != QLA_SUCCESS) { 209741f79bdeSSantosh Vernekar ql4_printk(KERN_INFO, ha, 209841f79bdeSSantosh Vernekar "%s: Error writing rdmem-dma-init to MS !!!\n", 209941f79bdeSSantosh Vernekar __func__); 210041f79bdeSSantosh Vernekar goto error_exit; 210141f79bdeSSantosh Vernekar } 210241f79bdeSSantosh Vernekar 210341f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 210441f79bdeSSantosh Vernekar "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n", 210541f79bdeSSantosh Vernekar __func__, size)); 210641f79bdeSSantosh Vernekar /* Execute: Start pex-dma operation. */ 210741f79bdeSSantosh Vernekar rval = qla4_83xx_start_pex_dma(ha, m_hdr); 210841f79bdeSSantosh Vernekar if (rval != QLA_SUCCESS) { 210941f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 211041f79bdeSSantosh Vernekar "scsi(%ld): start-pex-dma failed rval=0x%x\n", 211141f79bdeSSantosh Vernekar ha->host_no, rval)); 211241f79bdeSSantosh Vernekar goto error_exit; 211341f79bdeSSantosh Vernekar } 211441f79bdeSSantosh Vernekar 211541f79bdeSSantosh Vernekar memcpy(data_ptr, rdmem_buffer, size); 211641f79bdeSSantosh Vernekar data_ptr += size; 211741f79bdeSSantosh Vernekar read_size += size; 211841f79bdeSSantosh Vernekar } 211941f79bdeSSantosh Vernekar 212041f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); 212141f79bdeSSantosh Vernekar 212241f79bdeSSantosh Vernekar *d_ptr = (uint32_t *)data_ptr; 212341f79bdeSSantosh Vernekar 212441f79bdeSSantosh Vernekar error_exit: 212541f79bdeSSantosh Vernekar if (rdmem_buffer) 212641f79bdeSSantosh Vernekar dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer, 212741f79bdeSSantosh Vernekar rdmem_dma); 212841f79bdeSSantosh Vernekar 212941f79bdeSSantosh Vernekar return rval; 213041f79bdeSSantosh Vernekar } 213141f79bdeSSantosh Vernekar 2132068237c8STej Parkash static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha, 21337664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2134068237c8STej Parkash uint32_t **d_ptr) 2135068237c8STej Parkash { 2136068237c8STej Parkash uint32_t addr, r_addr, c_addr, t_r_addr; 2137068237c8STej Parkash uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2138068237c8STej Parkash unsigned long p_wait, w_time, p_mask; 2139068237c8STej Parkash uint32_t c_value_w, c_value_r; 21407664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_cache *cache_hdr; 2141068237c8STej Parkash int rval = QLA_ERROR; 2142068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2143068237c8STej Parkash 2144068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 21457664a1fdSVikas Chaudhary cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; 2146068237c8STej Parkash 2147068237c8STej Parkash loop_count = cache_hdr->op_count; 2148068237c8STej Parkash r_addr = cache_hdr->read_addr; 2149068237c8STej Parkash c_addr = cache_hdr->control_addr; 2150068237c8STej Parkash c_value_w = cache_hdr->cache_ctrl.write_value; 2151068237c8STej Parkash 2152068237c8STej Parkash t_r_addr = cache_hdr->tag_reg_addr; 2153068237c8STej Parkash t_value = cache_hdr->addr_ctrl.init_tag_value; 2154068237c8STej Parkash r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2155068237c8STej Parkash p_wait = cache_hdr->cache_ctrl.poll_wait; 2156068237c8STej Parkash p_mask = cache_hdr->cache_ctrl.poll_mask; 2157068237c8STej Parkash 2158068237c8STej Parkash for (i = 0; i < loop_count; i++) { 215933693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); 2160068237c8STej Parkash 2161068237c8STej Parkash if (c_value_w) 216233693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); 2163068237c8STej Parkash 2164068237c8STej Parkash if (p_mask) { 2165068237c8STej Parkash w_time = jiffies + p_wait; 2166068237c8STej Parkash do { 216733693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, c_addr, 216833693c7aSVikas Chaudhary &c_value_r); 2169068237c8STej Parkash if ((c_value_r & p_mask) == 0) { 2170068237c8STej Parkash break; 2171068237c8STej Parkash } else if (time_after_eq(jiffies, w_time)) { 2172068237c8STej Parkash /* capturing dump failed */ 2173068237c8STej Parkash return rval; 2174068237c8STej Parkash } 2175068237c8STej Parkash } while (1); 2176068237c8STej Parkash } 2177068237c8STej Parkash 2178068237c8STej Parkash addr = r_addr; 2179068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 218033693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); 2181068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2182068237c8STej Parkash addr += cache_hdr->read_ctrl.read_addr_stride; 2183068237c8STej Parkash } 2184068237c8STej Parkash 2185068237c8STej Parkash t_value += cache_hdr->addr_ctrl.tag_value_stride; 2186068237c8STej Parkash } 2187068237c8STej Parkash *d_ptr = data_ptr; 2188068237c8STej Parkash return QLA_SUCCESS; 2189068237c8STej Parkash } 2190068237c8STej Parkash 2191068237c8STej Parkash static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, 21927664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr) 2193068237c8STej Parkash { 21947664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_crb *crb_entry; 2195068237c8STej Parkash uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS; 2196068237c8STej Parkash uint32_t crb_addr; 2197068237c8STej Parkash unsigned long wtime; 2198068237c8STej Parkash struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 2199068237c8STej Parkash int i; 2200068237c8STej Parkash 2201068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2202068237c8STej Parkash tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 2203068237c8STej Parkash ha->fw_dump_tmplt_hdr; 22047664a1fdSVikas Chaudhary crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr; 2205068237c8STej Parkash 2206068237c8STej Parkash crb_addr = crb_entry->addr; 2207068237c8STej Parkash for (i = 0; i < crb_entry->op_count; i++) { 2208068237c8STej Parkash opcode = crb_entry->crb_ctrl.opcode; 2209de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_WR) { 221033693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, 221133693c7aSVikas Chaudhary crb_entry->value_1); 2212de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_WR; 2213068237c8STej Parkash } 2214de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_RW) { 221533693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 221633693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2217de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_RW; 2218068237c8STej Parkash } 2219de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_AND) { 222033693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2221068237c8STej Parkash read_value &= crb_entry->value_2; 2222de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_AND; 2223de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_OR) { 2224068237c8STej Parkash read_value |= crb_entry->value_3; 2225de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_OR; 2226068237c8STej Parkash } 222733693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2228068237c8STej Parkash } 2229de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_OR) { 223033693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2231068237c8STej Parkash read_value |= crb_entry->value_3; 223233693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2233de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_OR; 2234068237c8STej Parkash } 2235de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_POLL) { 2236068237c8STej Parkash poll_time = crb_entry->crb_strd.poll_timeout; 2237068237c8STej Parkash wtime = jiffies + poll_time; 223833693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2239068237c8STej Parkash 2240068237c8STej Parkash do { 2241068237c8STej Parkash if ((read_value & crb_entry->value_2) == 224233693c7aSVikas Chaudhary crb_entry->value_1) { 2243068237c8STej Parkash break; 224433693c7aSVikas Chaudhary } else if (time_after_eq(jiffies, wtime)) { 2245068237c8STej Parkash /* capturing dump failed */ 2246068237c8STej Parkash rval = QLA_ERROR; 2247068237c8STej Parkash break; 224833693c7aSVikas Chaudhary } else { 224933693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, 225033693c7aSVikas Chaudhary crb_addr, &read_value); 225133693c7aSVikas Chaudhary } 2252068237c8STej Parkash } while (1); 2253de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_POLL; 2254068237c8STej Parkash } 2255068237c8STej Parkash 2256de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) { 2257068237c8STej Parkash if (crb_entry->crb_strd.state_index_a) { 2258068237c8STej Parkash index = crb_entry->crb_strd.state_index_a; 2259068237c8STej Parkash addr = tmplt_hdr->saved_state_array[index]; 2260068237c8STej Parkash } else { 2261068237c8STej Parkash addr = crb_addr; 2262068237c8STej Parkash } 2263068237c8STej Parkash 226433693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr, &read_value); 2265068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 2266068237c8STej Parkash tmplt_hdr->saved_state_array[index] = read_value; 2267de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE; 2268068237c8STej Parkash } 2269068237c8STej Parkash 2270de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) { 2271068237c8STej Parkash if (crb_entry->crb_strd.state_index_a) { 2272068237c8STej Parkash index = crb_entry->crb_strd.state_index_a; 2273068237c8STej Parkash addr = tmplt_hdr->saved_state_array[index]; 2274068237c8STej Parkash } else { 2275068237c8STej Parkash addr = crb_addr; 2276068237c8STej Parkash } 2277068237c8STej Parkash 2278068237c8STej Parkash if (crb_entry->crb_ctrl.state_index_v) { 2279068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 2280068237c8STej Parkash read_value = 2281068237c8STej Parkash tmplt_hdr->saved_state_array[index]; 2282068237c8STej Parkash } else { 2283068237c8STej Parkash read_value = crb_entry->value_1; 2284068237c8STej Parkash } 2285068237c8STej Parkash 228633693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr, read_value); 2287de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE; 2288068237c8STej Parkash } 2289068237c8STej Parkash 2290de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) { 2291068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 2292068237c8STej Parkash read_value = tmplt_hdr->saved_state_array[index]; 2293068237c8STej Parkash read_value <<= crb_entry->crb_ctrl.shl; 2294068237c8STej Parkash read_value >>= crb_entry->crb_ctrl.shr; 2295068237c8STej Parkash if (crb_entry->value_2) 2296068237c8STej Parkash read_value &= crb_entry->value_2; 2297068237c8STej Parkash read_value |= crb_entry->value_3; 2298068237c8STej Parkash read_value += crb_entry->value_1; 2299068237c8STej Parkash tmplt_hdr->saved_state_array[index] = read_value; 2300de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE; 2301068237c8STej Parkash } 2302068237c8STej Parkash crb_addr += crb_entry->crb_strd.addr_stride; 2303068237c8STej Parkash } 2304068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); 2305068237c8STej Parkash return rval; 2306068237c8STej Parkash } 2307068237c8STej Parkash 2308068237c8STej Parkash static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha, 23097664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2310068237c8STej Parkash uint32_t **d_ptr) 2311068237c8STej Parkash { 2312068237c8STej Parkash uint32_t r_addr, r_stride, loop_cnt, i, r_value; 23137664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdocm *ocm_hdr; 2314068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2315068237c8STej Parkash 2316068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 23177664a1fdSVikas Chaudhary ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr; 2318068237c8STej Parkash r_addr = ocm_hdr->read_addr; 2319068237c8STej Parkash r_stride = ocm_hdr->read_addr_stride; 2320068237c8STej Parkash loop_cnt = ocm_hdr->op_count; 2321068237c8STej Parkash 2322068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2323068237c8STej Parkash "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", 2324068237c8STej Parkash __func__, r_addr, r_stride, loop_cnt)); 2325068237c8STej Parkash 2326068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 2327068237c8STej Parkash r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); 2328068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2329068237c8STej Parkash r_addr += r_stride; 2330068237c8STej Parkash } 2331068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n", 233226fdf922SVikas Chaudhary __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)))); 2333068237c8STej Parkash *d_ptr = data_ptr; 2334068237c8STej Parkash } 2335068237c8STej Parkash 2336068237c8STej Parkash static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha, 23377664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2338068237c8STej Parkash uint32_t **d_ptr) 2339068237c8STej Parkash { 2340068237c8STej Parkash uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 23417664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_mux *mux_hdr; 2342068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2343068237c8STej Parkash 2344068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 23457664a1fdSVikas Chaudhary mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr; 2346068237c8STej Parkash r_addr = mux_hdr->read_addr; 2347068237c8STej Parkash s_addr = mux_hdr->select_addr; 2348068237c8STej Parkash s_stride = mux_hdr->select_value_stride; 2349068237c8STej Parkash s_value = mux_hdr->select_value; 2350068237c8STej Parkash loop_cnt = mux_hdr->op_count; 2351068237c8STej Parkash 2352068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 235333693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); 235433693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 2355068237c8STej Parkash *data_ptr++ = cpu_to_le32(s_value); 2356068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2357068237c8STej Parkash s_value += s_stride; 2358068237c8STej Parkash } 2359068237c8STej Parkash *d_ptr = data_ptr; 2360068237c8STej Parkash } 2361068237c8STej Parkash 2362068237c8STej Parkash static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha, 23637664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2364068237c8STej Parkash uint32_t **d_ptr) 2365068237c8STej Parkash { 2366068237c8STej Parkash uint32_t addr, r_addr, c_addr, t_r_addr; 2367068237c8STej Parkash uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2368068237c8STej Parkash uint32_t c_value_w; 23697664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_cache *cache_hdr; 2370068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2371068237c8STej Parkash 23727664a1fdSVikas Chaudhary cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; 2373068237c8STej Parkash loop_count = cache_hdr->op_count; 2374068237c8STej Parkash r_addr = cache_hdr->read_addr; 2375068237c8STej Parkash c_addr = cache_hdr->control_addr; 2376068237c8STej Parkash c_value_w = cache_hdr->cache_ctrl.write_value; 2377068237c8STej Parkash 2378068237c8STej Parkash t_r_addr = cache_hdr->tag_reg_addr; 2379068237c8STej Parkash t_value = cache_hdr->addr_ctrl.init_tag_value; 2380068237c8STej Parkash r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2381068237c8STej Parkash 2382068237c8STej Parkash for (i = 0; i < loop_count; i++) { 238333693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); 238433693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); 2385068237c8STej Parkash addr = r_addr; 2386068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 238733693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); 2388068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2389068237c8STej Parkash addr += cache_hdr->read_ctrl.read_addr_stride; 2390068237c8STej Parkash } 2391068237c8STej Parkash t_value += cache_hdr->addr_ctrl.tag_value_stride; 2392068237c8STej Parkash } 2393068237c8STej Parkash *d_ptr = data_ptr; 2394068237c8STej Parkash } 2395068237c8STej Parkash 2396068237c8STej Parkash static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha, 23977664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2398068237c8STej Parkash uint32_t **d_ptr) 2399068237c8STej Parkash { 2400068237c8STej Parkash uint32_t s_addr, r_addr; 2401068237c8STej Parkash uint32_t r_stride, r_value, r_cnt, qid = 0; 2402068237c8STej Parkash uint32_t i, k, loop_cnt; 24037664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_queue *q_hdr; 2404068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2405068237c8STej Parkash 2406068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 24077664a1fdSVikas Chaudhary q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr; 2408068237c8STej Parkash s_addr = q_hdr->select_addr; 2409068237c8STej Parkash r_cnt = q_hdr->rd_strd.read_addr_cnt; 2410068237c8STej Parkash r_stride = q_hdr->rd_strd.read_addr_stride; 2411068237c8STej Parkash loop_cnt = q_hdr->op_count; 2412068237c8STej Parkash 2413068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 241433693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, s_addr, qid); 2415068237c8STej Parkash r_addr = q_hdr->read_addr; 2416068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 241733693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 2418068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2419068237c8STej Parkash r_addr += r_stride; 2420068237c8STej Parkash } 2421068237c8STej Parkash qid += q_hdr->q_strd.queue_id_stride; 2422068237c8STej Parkash } 2423068237c8STej Parkash *d_ptr = data_ptr; 2424068237c8STej Parkash } 2425068237c8STej Parkash 2426068237c8STej Parkash #define MD_DIRECT_ROM_WINDOW 0x42110030 2427068237c8STej Parkash #define MD_DIRECT_ROM_READ_BASE 0x42150000 2428068237c8STej Parkash 2429f8086f4fSVikas Chaudhary static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha, 24307664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2431068237c8STej Parkash uint32_t **d_ptr) 2432068237c8STej Parkash { 2433068237c8STej Parkash uint32_t r_addr, r_value; 2434068237c8STej Parkash uint32_t i, loop_cnt; 24357664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdrom *rom_hdr; 2436068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2437068237c8STej Parkash 2438068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 24397664a1fdSVikas Chaudhary rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; 2440068237c8STej Parkash r_addr = rom_hdr->read_addr; 2441068237c8STej Parkash loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 2442068237c8STej Parkash 2443068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2444068237c8STej Parkash "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n", 2445068237c8STej Parkash __func__, r_addr, loop_cnt)); 2446068237c8STej Parkash 2447068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 244833693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW, 244933693c7aSVikas Chaudhary (r_addr & 0xFFFF0000)); 245033693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, 245133693c7aSVikas Chaudhary MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF), 245233693c7aSVikas Chaudhary &r_value); 2453068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2454068237c8STej Parkash r_addr += sizeof(uint32_t); 2455068237c8STej Parkash } 2456068237c8STej Parkash *d_ptr = data_ptr; 2457068237c8STej Parkash } 2458068237c8STej Parkash 2459068237c8STej Parkash #define MD_MIU_TEST_AGT_CTRL 0x41000090 2460068237c8STej Parkash #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 2461068237c8STej Parkash #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 2462068237c8STej Parkash 246341f79bdeSSantosh Vernekar static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 24647664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2465068237c8STej Parkash uint32_t **d_ptr) 2466068237c8STej Parkash { 2467068237c8STej Parkash uint32_t r_addr, r_value, r_data; 2468068237c8STej Parkash uint32_t i, j, loop_cnt; 24697664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdmem *m_hdr; 2470068237c8STej Parkash unsigned long flags; 2471068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2472068237c8STej Parkash 2473068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 24747664a1fdSVikas Chaudhary m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr; 2475068237c8STej Parkash r_addr = m_hdr->read_addr; 2476068237c8STej Parkash loop_cnt = m_hdr->read_data_size/16; 2477068237c8STej Parkash 2478068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2479068237c8STej Parkash "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", 2480068237c8STej Parkash __func__, r_addr, m_hdr->read_data_size)); 2481068237c8STej Parkash 2482068237c8STej Parkash if (r_addr & 0xf) { 2483068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2484cf2fbdd2SMasanari Iida "[%s]: Read addr 0x%x not 16 bytes aligned\n", 2485068237c8STej Parkash __func__, r_addr)); 2486068237c8STej Parkash return QLA_ERROR; 2487068237c8STej Parkash } 2488068237c8STej Parkash 2489068237c8STej Parkash if (m_hdr->read_data_size % 16) { 2490068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2491068237c8STej Parkash "[%s]: Read data[0x%x] not multiple of 16 bytes\n", 2492068237c8STej Parkash __func__, m_hdr->read_data_size)); 2493068237c8STej Parkash return QLA_ERROR; 2494068237c8STej Parkash } 2495068237c8STej Parkash 2496068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2497068237c8STej Parkash "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 2498068237c8STej Parkash __func__, r_addr, m_hdr->read_data_size, loop_cnt)); 2499068237c8STej Parkash 2500068237c8STej Parkash write_lock_irqsave(&ha->hw_lock, flags); 2501068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 250233693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO, 250333693c7aSVikas Chaudhary r_addr); 2504068237c8STej Parkash r_value = 0; 250533693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 250633693c7aSVikas Chaudhary r_value); 2507068237c8STej Parkash r_value = MIU_TA_CTL_ENABLE; 250833693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); 2509c38fa3abSVikas Chaudhary r_value = MIU_TA_CTL_START_ENABLE; 251033693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); 2511068237c8STej Parkash 2512068237c8STej Parkash for (j = 0; j < MAX_CTL_CHECK; j++) { 251333693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, 251433693c7aSVikas Chaudhary &r_value); 2515068237c8STej Parkash if ((r_value & MIU_TA_CTL_BUSY) == 0) 2516068237c8STej Parkash break; 2517068237c8STej Parkash } 2518068237c8STej Parkash 2519068237c8STej Parkash if (j >= MAX_CTL_CHECK) { 2520068237c8STej Parkash printk_ratelimited(KERN_ERR 2521068237c8STej Parkash "%s: failed to read through agent\n", 2522068237c8STej Parkash __func__); 2523068237c8STej Parkash write_unlock_irqrestore(&ha->hw_lock, flags); 2524068237c8STej Parkash return QLA_SUCCESS; 2525068237c8STej Parkash } 2526068237c8STej Parkash 2527068237c8STej Parkash for (j = 0; j < 4; j++) { 252833693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, 2529068237c8STej Parkash MD_MIU_TEST_AGT_RDDATA[j], 253033693c7aSVikas Chaudhary &r_data); 2531068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_data); 2532068237c8STej Parkash } 2533068237c8STej Parkash 2534068237c8STej Parkash r_addr += 16; 2535068237c8STej Parkash } 2536068237c8STej Parkash write_unlock_irqrestore(&ha->hw_lock, flags); 2537068237c8STej Parkash 2538068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n", 2539068237c8STej Parkash __func__, (loop_cnt * 16))); 2540068237c8STej Parkash 2541068237c8STej Parkash *d_ptr = data_ptr; 2542068237c8STej Parkash return QLA_SUCCESS; 2543068237c8STej Parkash } 2544068237c8STej Parkash 254541f79bdeSSantosh Vernekar static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 254641f79bdeSSantosh Vernekar struct qla8xxx_minidump_entry_hdr *entry_hdr, 254741f79bdeSSantosh Vernekar uint32_t **d_ptr) 254841f79bdeSSantosh Vernekar { 254941f79bdeSSantosh Vernekar uint32_t *data_ptr = *d_ptr; 255041f79bdeSSantosh Vernekar int rval = QLA_SUCCESS; 255141f79bdeSSantosh Vernekar 25523c3cab17STej Parkash rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr); 25533c3cab17STej Parkash if (rval != QLA_SUCCESS) 255441f79bdeSSantosh Vernekar rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 255541f79bdeSSantosh Vernekar &data_ptr); 255641f79bdeSSantosh Vernekar *d_ptr = data_ptr; 255741f79bdeSSantosh Vernekar return rval; 255841f79bdeSSantosh Vernekar } 255941f79bdeSSantosh Vernekar 25605e9bcec7SVikas Chaudhary static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha, 25617664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2562068237c8STej Parkash int index) 2563068237c8STej Parkash { 2564de8c72daSVikas Chaudhary entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG; 2565068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2566068237c8STej Parkash "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", 2567068237c8STej Parkash ha->host_no, index, entry_hdr->entry_type, 2568068237c8STej Parkash entry_hdr->d_ctrl.entry_capture_mask)); 256958e2bbe9STej Parkash /* If driver encounters a new entry type that it cannot process, 257058e2bbe9STej Parkash * it should just skip the entry and adjust the total buffer size by 257158e2bbe9STej Parkash * from subtracting the skipped bytes from it 257258e2bbe9STej Parkash */ 257358e2bbe9STej Parkash ha->fw_dump_skip_size += entry_hdr->entry_capture_size; 2574068237c8STej Parkash } 2575068237c8STej Parkash 25766e7b4292SVikas Chaudhary /* ISP83xx functions to process new minidump entries... */ 25776e7b4292SVikas Chaudhary static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha, 25786e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 25796e7b4292SVikas Chaudhary uint32_t **d_ptr) 25806e7b4292SVikas Chaudhary { 25816e7b4292SVikas Chaudhary uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; 25826e7b4292SVikas Chaudhary uint16_t s_stride, i; 25836e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 25846e7b4292SVikas Chaudhary uint32_t rval = QLA_SUCCESS; 25856e7b4292SVikas Chaudhary struct qla83xx_minidump_entry_pollrd *pollrd_hdr; 25866e7b4292SVikas Chaudhary 25876e7b4292SVikas Chaudhary pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr; 25886e7b4292SVikas Chaudhary s_addr = le32_to_cpu(pollrd_hdr->select_addr); 25896e7b4292SVikas Chaudhary r_addr = le32_to_cpu(pollrd_hdr->read_addr); 25906e7b4292SVikas Chaudhary s_value = le32_to_cpu(pollrd_hdr->select_value); 25916e7b4292SVikas Chaudhary s_stride = le32_to_cpu(pollrd_hdr->select_value_stride); 25926e7b4292SVikas Chaudhary 25936e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); 25946e7b4292SVikas Chaudhary poll_mask = le32_to_cpu(pollrd_hdr->poll_mask); 25956e7b4292SVikas Chaudhary 25966e7b4292SVikas Chaudhary for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) { 25976e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); 25986e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); 25996e7b4292SVikas Chaudhary while (1) { 26006e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value); 26016e7b4292SVikas Chaudhary 26026e7b4292SVikas Chaudhary if ((r_value & poll_mask) != 0) { 26036e7b4292SVikas Chaudhary break; 26046e7b4292SVikas Chaudhary } else { 26056e7b4292SVikas Chaudhary msleep(1); 26066e7b4292SVikas Chaudhary if (--poll_wait == 0) { 26076e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", 26086e7b4292SVikas Chaudhary __func__); 26096e7b4292SVikas Chaudhary rval = QLA_ERROR; 26106e7b4292SVikas Chaudhary goto exit_process_pollrd; 26116e7b4292SVikas Chaudhary } 26126e7b4292SVikas Chaudhary } 26136e7b4292SVikas Chaudhary } 26146e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 26156e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(s_value); 26166e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(r_value); 26176e7b4292SVikas Chaudhary s_value += s_stride; 26186e7b4292SVikas Chaudhary } 26196e7b4292SVikas Chaudhary 26206e7b4292SVikas Chaudhary *d_ptr = data_ptr; 26216e7b4292SVikas Chaudhary 26226e7b4292SVikas Chaudhary exit_process_pollrd: 26236e7b4292SVikas Chaudhary return rval; 26246e7b4292SVikas Chaudhary } 26256e7b4292SVikas Chaudhary 2626b1829789STej Parkash static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha, 2627b1829789STej Parkash struct qla8xxx_minidump_entry_hdr *entry_hdr, 2628b1829789STej Parkash uint32_t **d_ptr) 2629b1829789STej Parkash { 2630b1829789STej Parkash int loop_cnt; 2631b1829789STej Parkash uint32_t addr1, addr2, value, data, temp, wrval; 2632b1829789STej Parkash uint8_t stride, stride2; 2633b1829789STej Parkash uint16_t count; 2634f67e8164SLee Jones uint32_t poll, mask, modify_mask; 2635b1829789STej Parkash uint32_t wait_count = 0; 2636b1829789STej Parkash uint32_t *data_ptr = *d_ptr; 2637b1829789STej Parkash struct qla8044_minidump_entry_rddfe *rddfe; 2638b1829789STej Parkash uint32_t rval = QLA_SUCCESS; 2639b1829789STej Parkash 2640b1829789STej Parkash rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr; 2641b1829789STej Parkash addr1 = le32_to_cpu(rddfe->addr_1); 2642b1829789STej Parkash value = le32_to_cpu(rddfe->value); 2643b1829789STej Parkash stride = le32_to_cpu(rddfe->stride); 2644b1829789STej Parkash stride2 = le32_to_cpu(rddfe->stride2); 2645b1829789STej Parkash count = le32_to_cpu(rddfe->count); 2646b1829789STej Parkash 2647b1829789STej Parkash poll = le32_to_cpu(rddfe->poll); 2648b1829789STej Parkash mask = le32_to_cpu(rddfe->mask); 2649b1829789STej Parkash modify_mask = le32_to_cpu(rddfe->modify_mask); 2650b1829789STej Parkash 2651b1829789STej Parkash addr2 = addr1 + stride; 2652b1829789STej Parkash 2653b1829789STej Parkash for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) { 2654b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value)); 2655b1829789STej Parkash 2656b1829789STej Parkash wait_count = 0; 2657b1829789STej Parkash while (wait_count < poll) { 2658b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 2659b1829789STej Parkash if ((temp & mask) != 0) 2660b1829789STej Parkash break; 2661b1829789STej Parkash wait_count++; 2662b1829789STej Parkash } 2663b1829789STej Parkash 2664b1829789STej Parkash if (wait_count == poll) { 2665b1829789STej Parkash ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__); 2666b1829789STej Parkash rval = QLA_ERROR; 2667b1829789STej Parkash goto exit_process_rddfe; 2668b1829789STej Parkash } else { 2669b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr2, &temp); 2670b1829789STej Parkash temp = temp & modify_mask; 2671b1829789STej Parkash temp = (temp | ((loop_cnt << 16) | loop_cnt)); 2672b1829789STej Parkash wrval = ((temp << 16) | temp); 2673b1829789STej Parkash 2674b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr2, wrval); 2675b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, value); 2676b1829789STej Parkash 2677b1829789STej Parkash wait_count = 0; 2678b1829789STej Parkash while (wait_count < poll) { 2679b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 2680b1829789STej Parkash if ((temp & mask) != 0) 2681b1829789STej Parkash break; 2682b1829789STej Parkash wait_count++; 2683b1829789STej Parkash } 2684b1829789STej Parkash if (wait_count == poll) { 2685b1829789STej Parkash ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", 2686b1829789STej Parkash __func__); 2687b1829789STej Parkash rval = QLA_ERROR; 2688b1829789STej Parkash goto exit_process_rddfe; 2689b1829789STej Parkash } 2690b1829789STej Parkash 2691b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, 2692b1829789STej Parkash ((0x40000000 | value) + 2693b1829789STej Parkash stride2)); 2694b1829789STej Parkash wait_count = 0; 2695b1829789STej Parkash while (wait_count < poll) { 2696b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 2697b1829789STej Parkash if ((temp & mask) != 0) 2698b1829789STej Parkash break; 2699b1829789STej Parkash wait_count++; 2700b1829789STej Parkash } 2701b1829789STej Parkash 2702b1829789STej Parkash if (wait_count == poll) { 2703b1829789STej Parkash ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", 2704b1829789STej Parkash __func__); 2705b1829789STej Parkash rval = QLA_ERROR; 2706b1829789STej Parkash goto exit_process_rddfe; 2707b1829789STej Parkash } 2708b1829789STej Parkash 2709b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr2, &data); 2710b1829789STej Parkash 2711b1829789STej Parkash *data_ptr++ = cpu_to_le32(wrval); 2712b1829789STej Parkash *data_ptr++ = cpu_to_le32(data); 2713b1829789STej Parkash } 2714b1829789STej Parkash } 2715b1829789STej Parkash 2716b1829789STej Parkash *d_ptr = data_ptr; 2717b1829789STej Parkash exit_process_rddfe: 2718b1829789STej Parkash return rval; 2719b1829789STej Parkash } 2720b1829789STej Parkash 2721b1829789STej Parkash static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha, 2722b1829789STej Parkash struct qla8xxx_minidump_entry_hdr *entry_hdr, 2723b1829789STej Parkash uint32_t **d_ptr) 2724b1829789STej Parkash { 2725b1829789STej Parkash int rval = QLA_SUCCESS; 2726b1829789STej Parkash uint32_t addr1, addr2, value1, value2, data, selval; 2727b1829789STej Parkash uint8_t stride1, stride2; 2728b1829789STej Parkash uint32_t addr3, addr4, addr5, addr6, addr7; 2729b1829789STej Parkash uint16_t count, loop_cnt; 2730f67e8164SLee Jones uint32_t mask; 2731b1829789STej Parkash uint32_t *data_ptr = *d_ptr; 2732b1829789STej Parkash struct qla8044_minidump_entry_rdmdio *rdmdio; 2733b1829789STej Parkash 2734b1829789STej Parkash rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr; 2735b1829789STej Parkash addr1 = le32_to_cpu(rdmdio->addr_1); 2736b1829789STej Parkash addr2 = le32_to_cpu(rdmdio->addr_2); 2737b1829789STej Parkash value1 = le32_to_cpu(rdmdio->value_1); 2738b1829789STej Parkash stride1 = le32_to_cpu(rdmdio->stride_1); 2739b1829789STej Parkash stride2 = le32_to_cpu(rdmdio->stride_2); 2740b1829789STej Parkash count = le32_to_cpu(rdmdio->count); 2741b1829789STej Parkash 2742b1829789STej Parkash mask = le32_to_cpu(rdmdio->mask); 2743b1829789STej Parkash value2 = le32_to_cpu(rdmdio->value_2); 2744b1829789STej Parkash 2745b1829789STej Parkash addr3 = addr1 + stride1; 2746b1829789STej Parkash 2747b1829789STej Parkash for (loop_cnt = 0; loop_cnt < count; loop_cnt++) { 2748b1829789STej Parkash rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2, 2749b1829789STej Parkash addr3, mask); 2750b1829789STej Parkash if (rval) 2751b1829789STej Parkash goto exit_process_rdmdio; 2752b1829789STej Parkash 2753b1829789STej Parkash addr4 = addr2 - stride1; 2754b1829789STej Parkash rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4, 2755b1829789STej Parkash value2); 2756b1829789STej Parkash if (rval) 2757b1829789STej Parkash goto exit_process_rdmdio; 2758b1829789STej Parkash 2759b1829789STej Parkash addr5 = addr2 - (2 * stride1); 2760b1829789STej Parkash rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5, 2761b1829789STej Parkash value1); 2762b1829789STej Parkash if (rval) 2763b1829789STej Parkash goto exit_process_rdmdio; 2764b1829789STej Parkash 2765b1829789STej Parkash addr6 = addr2 - (3 * stride1); 2766b1829789STej Parkash rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, 2767b1829789STej Parkash addr6, 0x2); 2768b1829789STej Parkash if (rval) 2769b1829789STej Parkash goto exit_process_rdmdio; 2770b1829789STej Parkash 2771b1829789STej Parkash rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2, 2772b1829789STej Parkash addr3, mask); 2773b1829789STej Parkash if (rval) 2774b1829789STej Parkash goto exit_process_rdmdio; 2775b1829789STej Parkash 2776b1829789STej Parkash addr7 = addr2 - (4 * stride1); 2777b1829789STej Parkash rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, 2778b1829789STej Parkash mask, addr7, &data); 2779b1829789STej Parkash if (rval) 2780b1829789STej Parkash goto exit_process_rdmdio; 2781b1829789STej Parkash 2782b1829789STej Parkash selval = (value2 << 18) | (value1 << 2) | 2; 2783b1829789STej Parkash 2784b1829789STej Parkash stride2 = le32_to_cpu(rdmdio->stride_2); 2785b1829789STej Parkash *data_ptr++ = cpu_to_le32(selval); 2786b1829789STej Parkash *data_ptr++ = cpu_to_le32(data); 2787b1829789STej Parkash 2788b1829789STej Parkash value1 = value1 + stride2; 2789b1829789STej Parkash *d_ptr = data_ptr; 2790b1829789STej Parkash } 2791b1829789STej Parkash 2792b1829789STej Parkash exit_process_rdmdio: 2793b1829789STej Parkash return rval; 2794b1829789STej Parkash } 2795b1829789STej Parkash 2796b1829789STej Parkash static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha, 2797b1829789STej Parkash struct qla8xxx_minidump_entry_hdr *entry_hdr, 2798b1829789STej Parkash uint32_t **d_ptr) 2799b1829789STej Parkash { 2800f67e8164SLee Jones uint32_t addr1, addr2, value1, value2, poll, r_value; 2801b1829789STej Parkash struct qla8044_minidump_entry_pollwr *pollwr_hdr; 2802b1829789STej Parkash uint32_t wait_count = 0; 2803b1829789STej Parkash uint32_t rval = QLA_SUCCESS; 2804b1829789STej Parkash 2805b1829789STej Parkash pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr; 2806b1829789STej Parkash addr1 = le32_to_cpu(pollwr_hdr->addr_1); 2807b1829789STej Parkash addr2 = le32_to_cpu(pollwr_hdr->addr_2); 2808b1829789STej Parkash value1 = le32_to_cpu(pollwr_hdr->value_1); 2809b1829789STej Parkash value2 = le32_to_cpu(pollwr_hdr->value_2); 2810b1829789STej Parkash 2811b1829789STej Parkash poll = le32_to_cpu(pollwr_hdr->poll); 2812b1829789STej Parkash 2813b1829789STej Parkash while (wait_count < poll) { 2814b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value); 2815b1829789STej Parkash 2816b1829789STej Parkash if ((r_value & poll) != 0) 2817b1829789STej Parkash break; 2818b1829789STej Parkash 2819b1829789STej Parkash wait_count++; 2820b1829789STej Parkash } 2821b1829789STej Parkash 2822b1829789STej Parkash if (wait_count == poll) { 2823b1829789STej Parkash ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__); 2824b1829789STej Parkash rval = QLA_ERROR; 2825b1829789STej Parkash goto exit_process_pollwr; 2826b1829789STej Parkash } 2827b1829789STej Parkash 2828b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr2, value2); 2829b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, value1); 2830b1829789STej Parkash 2831b1829789STej Parkash wait_count = 0; 2832b1829789STej Parkash while (wait_count < poll) { 2833b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value); 2834b1829789STej Parkash 2835b1829789STej Parkash if ((r_value & poll) != 0) 2836b1829789STej Parkash break; 2837b1829789STej Parkash wait_count++; 2838b1829789STej Parkash } 2839b1829789STej Parkash 2840b1829789STej Parkash exit_process_pollwr: 2841b1829789STej Parkash return rval; 2842b1829789STej Parkash } 2843b1829789STej Parkash 28446e7b4292SVikas Chaudhary static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha, 28456e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 28466e7b4292SVikas Chaudhary uint32_t **d_ptr) 28476e7b4292SVikas Chaudhary { 28486e7b4292SVikas Chaudhary uint32_t sel_val1, sel_val2, t_sel_val, data, i; 28496e7b4292SVikas Chaudhary uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; 28506e7b4292SVikas Chaudhary struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr; 28516e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 28526e7b4292SVikas Chaudhary 28536e7b4292SVikas Chaudhary rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr; 28546e7b4292SVikas Chaudhary sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1); 28556e7b4292SVikas Chaudhary sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2); 28566e7b4292SVikas Chaudhary sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1); 28576e7b4292SVikas Chaudhary sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2); 28586e7b4292SVikas Chaudhary sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask); 28596e7b4292SVikas Chaudhary read_addr = le32_to_cpu(rdmux2_hdr->read_addr); 28606e7b4292SVikas Chaudhary 28616e7b4292SVikas Chaudhary for (i = 0; i < rdmux2_hdr->op_count; i++) { 28626e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1); 28636e7b4292SVikas Chaudhary t_sel_val = sel_val1 & sel_val_mask; 28646e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(t_sel_val); 28656e7b4292SVikas Chaudhary 28666e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); 28676e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); 28686e7b4292SVikas Chaudhary 28696e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(data); 28706e7b4292SVikas Chaudhary 28716e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2); 28726e7b4292SVikas Chaudhary t_sel_val = sel_val2 & sel_val_mask; 28736e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(t_sel_val); 28746e7b4292SVikas Chaudhary 28756e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); 28766e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); 28776e7b4292SVikas Chaudhary 28786e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(data); 28796e7b4292SVikas Chaudhary 28806e7b4292SVikas Chaudhary sel_val1 += rdmux2_hdr->select_value_stride; 28816e7b4292SVikas Chaudhary sel_val2 += rdmux2_hdr->select_value_stride; 28826e7b4292SVikas Chaudhary } 28836e7b4292SVikas Chaudhary 28846e7b4292SVikas Chaudhary *d_ptr = data_ptr; 28856e7b4292SVikas Chaudhary } 28866e7b4292SVikas Chaudhary 28876e7b4292SVikas Chaudhary static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha, 28886e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 28896e7b4292SVikas Chaudhary uint32_t **d_ptr) 28906e7b4292SVikas Chaudhary { 28916e7b4292SVikas Chaudhary uint32_t poll_wait, poll_mask, r_value, data; 28926e7b4292SVikas Chaudhary uint32_t addr_1, addr_2, value_1, value_2; 28936e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 28946e7b4292SVikas Chaudhary uint32_t rval = QLA_SUCCESS; 28956e7b4292SVikas Chaudhary struct qla83xx_minidump_entry_pollrdmwr *poll_hdr; 28966e7b4292SVikas Chaudhary 28976e7b4292SVikas Chaudhary poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr; 28986e7b4292SVikas Chaudhary addr_1 = le32_to_cpu(poll_hdr->addr_1); 28996e7b4292SVikas Chaudhary addr_2 = le32_to_cpu(poll_hdr->addr_2); 29006e7b4292SVikas Chaudhary value_1 = le32_to_cpu(poll_hdr->value_1); 29016e7b4292SVikas Chaudhary value_2 = le32_to_cpu(poll_hdr->value_2); 29026e7b4292SVikas Chaudhary poll_mask = le32_to_cpu(poll_hdr->poll_mask); 29036e7b4292SVikas Chaudhary 29046e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1); 29056e7b4292SVikas Chaudhary 29066e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(poll_hdr->poll_wait); 29076e7b4292SVikas Chaudhary while (1) { 29086e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); 29096e7b4292SVikas Chaudhary 29106e7b4292SVikas Chaudhary if ((r_value & poll_mask) != 0) { 29116e7b4292SVikas Chaudhary break; 29126e7b4292SVikas Chaudhary } else { 29136e7b4292SVikas Chaudhary msleep(1); 29146e7b4292SVikas Chaudhary if (--poll_wait == 0) { 29156e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n", 29166e7b4292SVikas Chaudhary __func__); 29176e7b4292SVikas Chaudhary rval = QLA_ERROR; 29186e7b4292SVikas Chaudhary goto exit_process_pollrdmwr; 29196e7b4292SVikas Chaudhary } 29206e7b4292SVikas Chaudhary } 29216e7b4292SVikas Chaudhary } 29226e7b4292SVikas Chaudhary 29236e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr_2, &data); 29246e7b4292SVikas Chaudhary data &= le32_to_cpu(poll_hdr->modify_mask); 29256e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr_2, data); 29266e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2); 29276e7b4292SVikas Chaudhary 29286e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(poll_hdr->poll_wait); 29296e7b4292SVikas Chaudhary while (1) { 29306e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); 29316e7b4292SVikas Chaudhary 29326e7b4292SVikas Chaudhary if ((r_value & poll_mask) != 0) { 29336e7b4292SVikas Chaudhary break; 29346e7b4292SVikas Chaudhary } else { 29356e7b4292SVikas Chaudhary msleep(1); 29366e7b4292SVikas Chaudhary if (--poll_wait == 0) { 29376e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n", 29386e7b4292SVikas Chaudhary __func__); 29396e7b4292SVikas Chaudhary rval = QLA_ERROR; 29406e7b4292SVikas Chaudhary goto exit_process_pollrdmwr; 29416e7b4292SVikas Chaudhary } 29426e7b4292SVikas Chaudhary } 29436e7b4292SVikas Chaudhary } 29446e7b4292SVikas Chaudhary 29456e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(addr_2); 29466e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(data); 29476e7b4292SVikas Chaudhary *d_ptr = data_ptr; 29486e7b4292SVikas Chaudhary 29496e7b4292SVikas Chaudhary exit_process_pollrdmwr: 29506e7b4292SVikas Chaudhary return rval; 29516e7b4292SVikas Chaudhary } 29526e7b4292SVikas Chaudhary 29536e7b4292SVikas Chaudhary static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha, 29546e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 29556e7b4292SVikas Chaudhary uint32_t **d_ptr) 29566e7b4292SVikas Chaudhary { 29576e7b4292SVikas Chaudhary uint32_t fl_addr, u32_count, rval; 29586e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_rdrom *rom_hdr; 29596e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 29606e7b4292SVikas Chaudhary 29616e7b4292SVikas Chaudhary rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; 29626e7b4292SVikas Chaudhary fl_addr = le32_to_cpu(rom_hdr->read_addr); 29636e7b4292SVikas Chaudhary u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t); 29646e7b4292SVikas Chaudhary 29656e7b4292SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n", 29666e7b4292SVikas Chaudhary __func__, fl_addr, u32_count)); 29676e7b4292SVikas Chaudhary 29686e7b4292SVikas Chaudhary rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr, 29696e7b4292SVikas Chaudhary (u8 *)(data_ptr), u32_count); 29706e7b4292SVikas Chaudhary 29716e7b4292SVikas Chaudhary if (rval == QLA_ERROR) { 29726e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n", 29736e7b4292SVikas Chaudhary __func__, u32_count); 29746e7b4292SVikas Chaudhary goto exit_process_rdrom; 29756e7b4292SVikas Chaudhary } 29766e7b4292SVikas Chaudhary 29776e7b4292SVikas Chaudhary data_ptr += u32_count; 29786e7b4292SVikas Chaudhary *d_ptr = data_ptr; 29796e7b4292SVikas Chaudhary 29806e7b4292SVikas Chaudhary exit_process_rdrom: 29816e7b4292SVikas Chaudhary return rval; 29826e7b4292SVikas Chaudhary } 29836e7b4292SVikas Chaudhary 2984068237c8STej Parkash /** 2985f8086f4fSVikas Chaudhary * qla4_8xxx_collect_md_data - Retrieve firmware minidump data. 2986068237c8STej Parkash * @ha: pointer to adapter structure 2987068237c8STej Parkash **/ 2988068237c8STej Parkash static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) 2989068237c8STej Parkash { 2990068237c8STej Parkash int num_entry_hdr = 0; 29917664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr; 2992068237c8STej Parkash struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 2993068237c8STej Parkash uint32_t *data_ptr; 2994068237c8STej Parkash uint32_t data_collected = 0; 2995068237c8STej Parkash int i, rval = QLA_ERROR; 2996068237c8STej Parkash uint64_t now; 2997068237c8STej Parkash uint32_t timestamp; 2998068237c8STej Parkash 299958e2bbe9STej Parkash ha->fw_dump_skip_size = 0; 3000068237c8STej Parkash if (!ha->fw_dump) { 3001068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n", 3002068237c8STej Parkash __func__, ha->host_no); 3003068237c8STej Parkash return rval; 3004068237c8STej Parkash } 3005068237c8STej Parkash 3006068237c8STej Parkash tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 3007068237c8STej Parkash ha->fw_dump_tmplt_hdr; 3008068237c8STej Parkash data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump + 3009068237c8STej Parkash ha->fw_dump_tmplt_size); 3010068237c8STej Parkash data_collected += ha->fw_dump_tmplt_size; 3011068237c8STej Parkash 3012068237c8STej Parkash num_entry_hdr = tmplt_hdr->num_of_entries; 3013068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n", 3014068237c8STej Parkash __func__, data_ptr); 3015068237c8STej Parkash ql4_printk(KERN_INFO, ha, 3016068237c8STej Parkash "[%s]: no of entry headers in Template: 0x%x\n", 3017068237c8STej Parkash __func__, num_entry_hdr); 3018068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n", 3019068237c8STej Parkash __func__, ha->fw_dump_capture_mask); 3020068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n", 3021068237c8STej Parkash __func__, ha->fw_dump_size, ha->fw_dump_size); 3022068237c8STej Parkash 3023068237c8STej Parkash /* Update current timestamp before taking dump */ 3024068237c8STej Parkash now = get_jiffies_64(); 3025068237c8STej Parkash timestamp = (u32)(jiffies_to_msecs(now) / 1000); 3026068237c8STej Parkash tmplt_hdr->driver_timestamp = timestamp; 3027068237c8STej Parkash 30287664a1fdSVikas Chaudhary entry_hdr = (struct qla8xxx_minidump_entry_hdr *) 3029068237c8STej Parkash (((uint8_t *)ha->fw_dump_tmplt_hdr) + 3030068237c8STej Parkash tmplt_hdr->first_entry_offset); 3031068237c8STej Parkash 3032b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 30336e7b4292SVikas Chaudhary tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] = 30346e7b4292SVikas Chaudhary tmplt_hdr->ocm_window_reg[ha->func_num]; 30356e7b4292SVikas Chaudhary 3036068237c8STej Parkash /* Walk through the entry headers - validate/perform required action */ 3037068237c8STej Parkash for (i = 0; i < num_entry_hdr; i++) { 30384812d070SSantosh Vernekar if (data_collected > ha->fw_dump_size) { 3039068237c8STej Parkash ql4_printk(KERN_INFO, ha, 3040068237c8STej Parkash "Data collected: [0x%x], Total Dump size: [0x%x]\n", 3041068237c8STej Parkash data_collected, ha->fw_dump_size); 3042068237c8STej Parkash return rval; 3043068237c8STej Parkash } 3044068237c8STej Parkash 3045068237c8STej Parkash if (!(entry_hdr->d_ctrl.entry_capture_mask & 3046068237c8STej Parkash ha->fw_dump_capture_mask)) { 3047068237c8STej Parkash entry_hdr->d_ctrl.driver_flags |= 3048de8c72daSVikas Chaudhary QLA8XXX_DBG_SKIPPED_FLAG; 3049068237c8STej Parkash goto skip_nxt_entry; 3050068237c8STej Parkash } 3051068237c8STej Parkash 3052068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 3053068237c8STej Parkash "Data collected: [0x%x], Dump size left:[0x%x]\n", 3054068237c8STej Parkash data_collected, 3055068237c8STej Parkash (ha->fw_dump_size - data_collected))); 3056068237c8STej Parkash 3057068237c8STej Parkash /* Decode the entry type and take required action to capture 3058068237c8STej Parkash * debug data 3059068237c8STej Parkash */ 3060068237c8STej Parkash switch (entry_hdr->entry_type) { 3061de8c72daSVikas Chaudhary case QLA8XXX_RDEND: 30625e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3063068237c8STej Parkash break; 3064de8c72daSVikas Chaudhary case QLA8XXX_CNTRL: 3065068237c8STej Parkash rval = qla4_8xxx_minidump_process_control(ha, 3066068237c8STej Parkash entry_hdr); 3067068237c8STej Parkash if (rval != QLA_SUCCESS) { 30685e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3069068237c8STej Parkash goto md_failed; 3070068237c8STej Parkash } 3071068237c8STej Parkash break; 3072de8c72daSVikas Chaudhary case QLA8XXX_RDCRB: 3073068237c8STej Parkash qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, 3074068237c8STej Parkash &data_ptr); 3075068237c8STej Parkash break; 3076de8c72daSVikas Chaudhary case QLA8XXX_RDMEM: 3077068237c8STej Parkash rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 3078068237c8STej Parkash &data_ptr); 3079068237c8STej Parkash if (rval != QLA_SUCCESS) { 30805e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3081068237c8STej Parkash goto md_failed; 3082068237c8STej Parkash } 3083068237c8STej Parkash break; 3084de8c72daSVikas Chaudhary case QLA8XXX_BOARD: 3085de8c72daSVikas Chaudhary case QLA8XXX_RDROM: 30866e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 3087f8086f4fSVikas Chaudhary qla4_82xx_minidump_process_rdrom(ha, entry_hdr, 3088068237c8STej Parkash &data_ptr); 3089b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 30906e7b4292SVikas Chaudhary rval = qla4_83xx_minidump_process_rdrom(ha, 30916e7b4292SVikas Chaudhary entry_hdr, 30926e7b4292SVikas Chaudhary &data_ptr); 30936e7b4292SVikas Chaudhary if (rval != QLA_SUCCESS) 30946e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, 30956e7b4292SVikas Chaudhary entry_hdr, 30966e7b4292SVikas Chaudhary i); 30976e7b4292SVikas Chaudhary } 3098068237c8STej Parkash break; 3099de8c72daSVikas Chaudhary case QLA8XXX_L2DTG: 3100de8c72daSVikas Chaudhary case QLA8XXX_L2ITG: 3101de8c72daSVikas Chaudhary case QLA8XXX_L2DAT: 3102de8c72daSVikas Chaudhary case QLA8XXX_L2INS: 3103068237c8STej Parkash rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, 3104068237c8STej Parkash &data_ptr); 3105068237c8STej Parkash if (rval != QLA_SUCCESS) { 31065e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3107068237c8STej Parkash goto md_failed; 3108068237c8STej Parkash } 3109068237c8STej Parkash break; 31106e7b4292SVikas Chaudhary case QLA8XXX_L1DTG: 31116e7b4292SVikas Chaudhary case QLA8XXX_L1ITG: 3112de8c72daSVikas Chaudhary case QLA8XXX_L1DAT: 3113de8c72daSVikas Chaudhary case QLA8XXX_L1INS: 3114068237c8STej Parkash qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, 3115068237c8STej Parkash &data_ptr); 3116068237c8STej Parkash break; 3117de8c72daSVikas Chaudhary case QLA8XXX_RDOCM: 3118068237c8STej Parkash qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, 3119068237c8STej Parkash &data_ptr); 3120068237c8STej Parkash break; 3121de8c72daSVikas Chaudhary case QLA8XXX_RDMUX: 3122068237c8STej Parkash qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, 3123068237c8STej Parkash &data_ptr); 3124068237c8STej Parkash break; 3125de8c72daSVikas Chaudhary case QLA8XXX_QUEUE: 3126068237c8STej Parkash qla4_8xxx_minidump_process_queue(ha, entry_hdr, 3127068237c8STej Parkash &data_ptr); 3128068237c8STej Parkash break; 31296e7b4292SVikas Chaudhary case QLA83XX_POLLRD: 3130b37ca418SVikas Chaudhary if (is_qla8022(ha)) { 31316e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 31326e7b4292SVikas Chaudhary break; 31336e7b4292SVikas Chaudhary } 31346e7b4292SVikas Chaudhary rval = qla83xx_minidump_process_pollrd(ha, entry_hdr, 31356e7b4292SVikas Chaudhary &data_ptr); 31366e7b4292SVikas Chaudhary if (rval != QLA_SUCCESS) 31376e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 31386e7b4292SVikas Chaudhary break; 31396e7b4292SVikas Chaudhary case QLA83XX_RDMUX2: 3140b37ca418SVikas Chaudhary if (is_qla8022(ha)) { 31416e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 31426e7b4292SVikas Chaudhary break; 31436e7b4292SVikas Chaudhary } 31446e7b4292SVikas Chaudhary qla83xx_minidump_process_rdmux2(ha, entry_hdr, 31456e7b4292SVikas Chaudhary &data_ptr); 31466e7b4292SVikas Chaudhary break; 31476e7b4292SVikas Chaudhary case QLA83XX_POLLRDMWR: 3148b37ca418SVikas Chaudhary if (is_qla8022(ha)) { 31496e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 31506e7b4292SVikas Chaudhary break; 31516e7b4292SVikas Chaudhary } 31526e7b4292SVikas Chaudhary rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr, 31536e7b4292SVikas Chaudhary &data_ptr); 31546e7b4292SVikas Chaudhary if (rval != QLA_SUCCESS) 31556e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 31566e7b4292SVikas Chaudhary break; 3157b1829789STej Parkash case QLA8044_RDDFE: 3158b1829789STej Parkash rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr, 3159b1829789STej Parkash &data_ptr); 3160b1829789STej Parkash if (rval != QLA_SUCCESS) 3161b1829789STej Parkash qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3162b1829789STej Parkash break; 3163b1829789STej Parkash case QLA8044_RDMDIO: 3164b1829789STej Parkash rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr, 3165b1829789STej Parkash &data_ptr); 3166b1829789STej Parkash if (rval != QLA_SUCCESS) 3167b1829789STej Parkash qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3168b1829789STej Parkash break; 3169b1829789STej Parkash case QLA8044_POLLWR: 3170b1829789STej Parkash rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr, 3171b1829789STej Parkash &data_ptr); 3172b1829789STej Parkash if (rval != QLA_SUCCESS) 3173b1829789STej Parkash qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3174b1829789STej Parkash break; 3175de8c72daSVikas Chaudhary case QLA8XXX_RDNOP: 3176068237c8STej Parkash default: 31775e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3178068237c8STej Parkash break; 3179068237c8STej Parkash } 3180068237c8STej Parkash 31814812d070SSantosh Vernekar data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump; 3182068237c8STej Parkash skip_nxt_entry: 3183068237c8STej Parkash /* next entry in the template */ 31847664a1fdSVikas Chaudhary entry_hdr = (struct qla8xxx_minidump_entry_hdr *) 3185068237c8STej Parkash (((uint8_t *)entry_hdr) + 3186068237c8STej Parkash entry_hdr->entry_size); 3187068237c8STej Parkash } 3188068237c8STej Parkash 318958e2bbe9STej Parkash if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) { 3190068237c8STej Parkash ql4_printk(KERN_INFO, ha, 3191068237c8STej Parkash "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n", 3192068237c8STej Parkash data_collected, ha->fw_dump_size); 319335a9c2abSVikas Chaudhary rval = QLA_ERROR; 3194068237c8STej Parkash goto md_failed; 3195068237c8STej Parkash } 3196068237c8STej Parkash 3197068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n", 3198068237c8STej Parkash __func__, i)); 3199068237c8STej Parkash md_failed: 3200068237c8STej Parkash return rval; 3201068237c8STej Parkash } 3202068237c8STej Parkash 3203068237c8STej Parkash /** 3204068237c8STej Parkash * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready. 3205068237c8STej Parkash * @ha: pointer to adapter structure 3206653557dfSLee Jones * @code: uevent code to act upon 3207068237c8STej Parkash **/ 3208068237c8STej Parkash static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code) 3209068237c8STej Parkash { 3210068237c8STej Parkash char event_string[40]; 3211068237c8STej Parkash char *envp[] = { event_string, NULL }; 3212068237c8STej Parkash 3213068237c8STej Parkash switch (code) { 3214068237c8STej Parkash case QL4_UEVENT_CODE_FW_DUMP: 32155ccdd101SYe Bin snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 3216068237c8STej Parkash ha->host_no); 3217068237c8STej Parkash break; 3218068237c8STej Parkash default: 3219068237c8STej Parkash /*do nothing*/ 3220068237c8STej Parkash break; 3221068237c8STej Parkash } 3222068237c8STej Parkash 3223068237c8STej Parkash kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp); 3224068237c8STej Parkash } 3225068237c8STej Parkash 32266e7b4292SVikas Chaudhary void qla4_8xxx_get_minidump(struct scsi_qla_host *ha) 3227aec07caeSVikas Chaudhary { 3228aec07caeSVikas Chaudhary if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) && 3229aec07caeSVikas Chaudhary !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) { 3230aec07caeSVikas Chaudhary if (!qla4_8xxx_collect_md_data(ha)) { 3231aec07caeSVikas Chaudhary qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP); 3232aec07caeSVikas Chaudhary set_bit(AF_82XX_FW_DUMPED, &ha->flags); 3233aec07caeSVikas Chaudhary } else { 3234aec07caeSVikas Chaudhary ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n", 3235aec07caeSVikas Chaudhary __func__); 3236aec07caeSVikas Chaudhary } 3237aec07caeSVikas Chaudhary } 3238aec07caeSVikas Chaudhary } 3239aec07caeSVikas Chaudhary 3240f4f5df23SVikas Chaudhary /** 3241f4f5df23SVikas Chaudhary * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw 3242f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 3243f4f5df23SVikas Chaudhary * 3244f4f5df23SVikas Chaudhary * Note: IDC lock must be held upon entry 3245f4f5df23SVikas Chaudhary **/ 32466e7b4292SVikas Chaudhary int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) 3247f4f5df23SVikas Chaudhary { 3248b25ee66fSShyam Sundar int rval = QLA_ERROR; 324932436aaaSVikas Chaudhary int i; 325080645dc0SVikas Chaudhary uint32_t old_count, count; 32514ebbb5cfSVikas Chaudhary int need_reset = 0; 3252f4f5df23SVikas Chaudhary 325333693c7aSVikas Chaudhary need_reset = ha->isp_ops->need_reset(ha); 3254b25ee66fSShyam Sundar 3255b25ee66fSShyam Sundar if (need_reset) { 3256b25ee66fSShyam Sundar /* We are trying to perform a recovery here. */ 32574ebbb5cfSVikas Chaudhary if (test_bit(AF_FW_RECOVERY, &ha->flags)) 325833693c7aSVikas Chaudhary ha->isp_ops->rom_lock_recovery(ha); 3259b25ee66fSShyam Sundar } else { 32604ebbb5cfSVikas Chaudhary old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER); 32614ebbb5cfSVikas Chaudhary for (i = 0; i < 10; i++) { 32624ebbb5cfSVikas Chaudhary msleep(200); 32634ebbb5cfSVikas Chaudhary count = qla4_8xxx_rd_direct(ha, 32644ebbb5cfSVikas Chaudhary QLA8XXX_PEG_ALIVE_COUNTER); 32654ebbb5cfSVikas Chaudhary if (count != old_count) { 3266b25ee66fSShyam Sundar rval = QLA_SUCCESS; 3267f4f5df23SVikas Chaudhary goto dev_ready; 3268f4f5df23SVikas Chaudhary } 3269b25ee66fSShyam Sundar } 32704ebbb5cfSVikas Chaudhary ha->isp_ops->rom_lock_recovery(ha); 32714ebbb5cfSVikas Chaudhary } 3272f4f5df23SVikas Chaudhary 3273f4f5df23SVikas Chaudhary /* set to DEV_INITIALIZING */ 3274f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 327533693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 327633693c7aSVikas Chaudhary QLA8XXX_DEV_INITIALIZING); 3277f4f5df23SVikas Chaudhary 327833693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 32796e7b4292SVikas Chaudhary 32806e7b4292SVikas Chaudhary if (is_qla8022(ha)) 3281aec07caeSVikas Chaudhary qla4_8xxx_get_minidump(ha); 32826e7b4292SVikas Chaudhary 328333693c7aSVikas Chaudhary rval = ha->isp_ops->restart_firmware(ha); 328433693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3285f4f5df23SVikas Chaudhary 3286f4f5df23SVikas Chaudhary if (rval != QLA_SUCCESS) { 3287f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 3288f4f5df23SVikas Chaudhary qla4_8xxx_clear_drv_active(ha); 328933693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 329033693c7aSVikas Chaudhary QLA8XXX_DEV_FAILED); 3291f4f5df23SVikas Chaudhary return rval; 3292f4f5df23SVikas Chaudhary } 3293f4f5df23SVikas Chaudhary 3294f4f5df23SVikas Chaudhary dev_ready: 3295f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 329633693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 3297f4f5df23SVikas Chaudhary 3298b25ee66fSShyam Sundar return rval; 3299f4f5df23SVikas Chaudhary } 3300f4f5df23SVikas Chaudhary 3301f4f5df23SVikas Chaudhary /** 3302f8086f4fSVikas Chaudhary * qla4_82xx_need_reset_handler - Code to start reset sequence 3303f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 3304f4f5df23SVikas Chaudhary * 3305f4f5df23SVikas Chaudhary * Note: IDC lock must be held upon entry 3306f4f5df23SVikas Chaudhary **/ 3307f4f5df23SVikas Chaudhary static void 3308f8086f4fSVikas Chaudhary qla4_82xx_need_reset_handler(struct scsi_qla_host *ha) 3309f4f5df23SVikas Chaudhary { 3310f4f5df23SVikas Chaudhary uint32_t dev_state, drv_state, drv_active; 3311068237c8STej Parkash uint32_t active_mask = 0xFFFFFFFF; 3312f4f5df23SVikas Chaudhary unsigned long reset_timeout; 3313f4f5df23SVikas Chaudhary 3314f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 3315f4f5df23SVikas Chaudhary "Performing ISP error recovery\n"); 3316f4f5df23SVikas Chaudhary 3317f4f5df23SVikas Chaudhary if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { 3318f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 3319f4f5df23SVikas Chaudhary ha->isp_ops->disable_intrs(ha); 3320f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 3321f4f5df23SVikas Chaudhary } 3322f4f5df23SVikas Chaudhary 3323de8c72daSVikas Chaudhary if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { 3324068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 3325068237c8STej Parkash "%s(%ld): reset acknowledged\n", 3326068237c8STej Parkash __func__, ha->host_no)); 3327f4f5df23SVikas Chaudhary qla4_8xxx_set_rst_ready(ha); 3328068237c8STej Parkash } else { 3329068237c8STej Parkash active_mask = (~(1 << (ha->func_num * 4))); 3330068237c8STej Parkash } 3331f4f5df23SVikas Chaudhary 3332f4f5df23SVikas Chaudhary /* wait for 10 seconds for reset ack from all functions */ 3333f4f5df23SVikas Chaudhary reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3334f4f5df23SVikas Chaudhary 3335f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3336f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3337f4f5df23SVikas Chaudhary 3338f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 3339f4f5df23SVikas Chaudhary "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 3340f4f5df23SVikas Chaudhary __func__, ha->host_no, drv_state, drv_active); 3341f4f5df23SVikas Chaudhary 3342068237c8STej Parkash while (drv_state != (drv_active & active_mask)) { 3343f4f5df23SVikas Chaudhary if (time_after_eq(jiffies, reset_timeout)) { 3344068237c8STej Parkash ql4_printk(KERN_INFO, ha, 3345068237c8STej Parkash "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", 3346068237c8STej Parkash DRIVER_NAME, drv_state, drv_active); 3347f4f5df23SVikas Chaudhary break; 3348f4f5df23SVikas Chaudhary } 3349f4f5df23SVikas Chaudhary 3350068237c8STej Parkash /* 3351068237c8STej Parkash * When reset_owner times out, check which functions 3352068237c8STej Parkash * acked/did not ack 3353068237c8STej Parkash */ 3354de8c72daSVikas Chaudhary if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { 3355068237c8STej Parkash ql4_printk(KERN_INFO, ha, 3356068237c8STej Parkash "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 3357068237c8STej Parkash __func__, ha->host_no, drv_state, 3358068237c8STej Parkash drv_active); 3359068237c8STej Parkash } 3360f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 3361f4f5df23SVikas Chaudhary msleep(1000); 3362f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 3363f4f5df23SVikas Chaudhary 3364f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3365f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3366f4f5df23SVikas Chaudhary } 3367f4f5df23SVikas Chaudhary 3368068237c8STej Parkash /* Clear RESET OWNER as we are not going to use it any further */ 3369de8c72daSVikas Chaudhary clear_bit(AF_8XXX_RST_OWNER, &ha->flags); 3370068237c8STej Parkash 3371f8086f4fSVikas Chaudhary dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3372068237c8STej Parkash ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, 3373f4f5df23SVikas Chaudhary dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3374f4f5df23SVikas Chaudhary 3375f4f5df23SVikas Chaudhary /* Force to DEV_COLD unless someone else is starting a reset */ 3376de8c72daSVikas Chaudhary if (dev_state != QLA8XXX_DEV_INITIALIZING) { 3377f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 3378de8c72daSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3379068237c8STej Parkash qla4_8xxx_set_rst_ready(ha); 3380f4f5df23SVikas Chaudhary } 3381f4f5df23SVikas Chaudhary } 3382f4f5df23SVikas Chaudhary 3383f4f5df23SVikas Chaudhary /** 3384f4f5df23SVikas Chaudhary * qla4_8xxx_need_qsnt_handler - Code to start qsnt 3385f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 3386f4f5df23SVikas Chaudhary **/ 3387f4f5df23SVikas Chaudhary void 3388f4f5df23SVikas Chaudhary qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 3389f4f5df23SVikas Chaudhary { 339033693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3391f4f5df23SVikas Chaudhary qla4_8xxx_set_qsnt_ready(ha); 339233693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3393f4f5df23SVikas Chaudhary } 3394f4f5df23SVikas Chaudhary 339583dbdf6fSVikas Chaudhary static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha) 339683dbdf6fSVikas Chaudhary { 339783dbdf6fSVikas Chaudhary int idc_ver; 339883dbdf6fSVikas Chaudhary uint32_t drv_active; 339983dbdf6fSVikas Chaudhary 340083dbdf6fSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 340183dbdf6fSVikas Chaudhary if (drv_active == (1 << (ha->func_num * 4))) { 340283dbdf6fSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, 340383dbdf6fSVikas Chaudhary QLA82XX_IDC_VERSION); 340483dbdf6fSVikas Chaudhary ql4_printk(KERN_INFO, ha, 340583dbdf6fSVikas Chaudhary "%s: IDC version updated to %d\n", __func__, 340683dbdf6fSVikas Chaudhary QLA82XX_IDC_VERSION); 340783dbdf6fSVikas Chaudhary } else { 340883dbdf6fSVikas Chaudhary idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 340983dbdf6fSVikas Chaudhary if (QLA82XX_IDC_VERSION != idc_ver) { 341083dbdf6fSVikas Chaudhary ql4_printk(KERN_INFO, ha, 341183dbdf6fSVikas Chaudhary "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", 341283dbdf6fSVikas Chaudhary __func__, QLA82XX_IDC_VERSION, idc_ver); 341383dbdf6fSVikas Chaudhary } 341483dbdf6fSVikas Chaudhary } 341583dbdf6fSVikas Chaudhary } 341683dbdf6fSVikas Chaudhary 34176e7b4292SVikas Chaudhary static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha) 341883dbdf6fSVikas Chaudhary { 34196e7b4292SVikas Chaudhary int idc_ver; 34206e7b4292SVikas Chaudhary uint32_t drv_active; 34216e7b4292SVikas Chaudhary int rval = QLA_SUCCESS; 34226e7b4292SVikas Chaudhary 34236e7b4292SVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 34246e7b4292SVikas Chaudhary if (drv_active == (1 << ha->func_num)) { 34256e7b4292SVikas Chaudhary idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 34266e7b4292SVikas Chaudhary idc_ver &= (~0xFF); 34276e7b4292SVikas Chaudhary idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE; 34286e7b4292SVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver); 34296e7b4292SVikas Chaudhary ql4_printk(KERN_INFO, ha, 34306e7b4292SVikas Chaudhary "%s: IDC version updated to %d\n", __func__, 3431ecca5120SVikas Chaudhary idc_ver); 34326e7b4292SVikas Chaudhary } else { 34336e7b4292SVikas Chaudhary idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 34346e7b4292SVikas Chaudhary idc_ver &= 0xFF; 34356e7b4292SVikas Chaudhary if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) { 34366e7b4292SVikas Chaudhary ql4_printk(KERN_INFO, ha, 34376e7b4292SVikas Chaudhary "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", 34386e7b4292SVikas Chaudhary __func__, QLA83XX_IDC_VER_MAJ_VALUE, 34396e7b4292SVikas Chaudhary idc_ver); 34406e7b4292SVikas Chaudhary rval = QLA_ERROR; 34416e7b4292SVikas Chaudhary goto exit_set_idc_ver; 34426e7b4292SVikas Chaudhary } 34436e7b4292SVikas Chaudhary } 34446e7b4292SVikas Chaudhary 34456e7b4292SVikas Chaudhary /* Update IDC_MINOR_VERSION */ 34466e7b4292SVikas Chaudhary idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR); 34476e7b4292SVikas Chaudhary idc_ver &= ~(0x03 << (ha->func_num * 2)); 34486e7b4292SVikas Chaudhary idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2)); 34496e7b4292SVikas Chaudhary qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver); 34506e7b4292SVikas Chaudhary 34516e7b4292SVikas Chaudhary exit_set_idc_ver: 34526e7b4292SVikas Chaudhary return rval; 34536e7b4292SVikas Chaudhary } 34546e7b4292SVikas Chaudhary 345539c95826SVikas Chaudhary int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha) 34566e7b4292SVikas Chaudhary { 34576e7b4292SVikas Chaudhary uint32_t drv_active; 34586e7b4292SVikas Chaudhary int rval = QLA_SUCCESS; 34596e7b4292SVikas Chaudhary 34606e7b4292SVikas Chaudhary if (test_bit(AF_INIT_DONE, &ha->flags)) 34616e7b4292SVikas Chaudhary goto exit_update_idc_reg; 34626e7b4292SVikas Chaudhary 346383dbdf6fSVikas Chaudhary ha->isp_ops->idc_lock(ha); 346483dbdf6fSVikas Chaudhary qla4_8xxx_set_drv_active(ha); 34656e7b4292SVikas Chaudhary 34666e7b4292SVikas Chaudhary /* 34676e7b4292SVikas Chaudhary * If we are the first driver to load and 34686e7b4292SVikas Chaudhary * ql4xdontresethba is not set, clear IDC_CTRL BIT0. 34696e7b4292SVikas Chaudhary */ 3470b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) { 34716e7b4292SVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 34726e7b4292SVikas Chaudhary if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba) 34736e7b4292SVikas Chaudhary qla4_83xx_clear_idc_dontreset(ha); 347483dbdf6fSVikas Chaudhary } 34756e7b4292SVikas Chaudhary 34766e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 34776e7b4292SVikas Chaudhary qla4_82xx_set_idc_ver(ha); 3478b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 34796e7b4292SVikas Chaudhary rval = qla4_83xx_set_idc_ver(ha); 34806e7b4292SVikas Chaudhary if (rval == QLA_ERROR) 34816e7b4292SVikas Chaudhary qla4_8xxx_clear_drv_active(ha); 34826e7b4292SVikas Chaudhary } 34836e7b4292SVikas Chaudhary 34846e7b4292SVikas Chaudhary ha->isp_ops->idc_unlock(ha); 34856e7b4292SVikas Chaudhary 34866e7b4292SVikas Chaudhary exit_update_idc_reg: 34876e7b4292SVikas Chaudhary return rval; 3488f4f5df23SVikas Chaudhary } 3489f4f5df23SVikas Chaudhary 3490f4f5df23SVikas Chaudhary /** 3491f4f5df23SVikas Chaudhary * qla4_8xxx_device_state_handler - Adapter state machine 3492f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 3493f4f5df23SVikas Chaudhary * 3494f4f5df23SVikas Chaudhary * Note: IDC lock must be UNLOCKED upon entry 3495f4f5df23SVikas Chaudhary **/ 3496f4f5df23SVikas Chaudhary int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) 3497f4f5df23SVikas Chaudhary { 3498f4f5df23SVikas Chaudhary uint32_t dev_state; 3499f4f5df23SVikas Chaudhary int rval = QLA_SUCCESS; 3500f4f5df23SVikas Chaudhary unsigned long dev_init_timeout; 3501f4f5df23SVikas Chaudhary 35026e7b4292SVikas Chaudhary rval = qla4_8xxx_update_idc_reg(ha); 35036e7b4292SVikas Chaudhary if (rval == QLA_ERROR) 35046e7b4292SVikas Chaudhary goto exit_state_handler; 3505f4f5df23SVikas Chaudhary 350633693c7aSVikas Chaudhary dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); 3507068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 3508068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 3509068237c8STej Parkash qdev_state[dev_state] : "Unknown")); 3510f4f5df23SVikas Chaudhary 3511f4f5df23SVikas Chaudhary /* wait for 30 seconds for device to go ready */ 3512f4f5df23SVikas Chaudhary dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3513f4f5df23SVikas Chaudhary 351433693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3515e3f37d16SNilesh Javali while (1) { 3516f4f5df23SVikas Chaudhary 3517f4f5df23SVikas Chaudhary if (time_after_eq(jiffies, dev_init_timeout)) { 3518068237c8STej Parkash ql4_printk(KERN_WARNING, ha, 3519068237c8STej Parkash "%s: Device Init Failed 0x%x = %s\n", 3520068237c8STej Parkash DRIVER_NAME, 3521068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 3522068237c8STej Parkash qdev_state[dev_state] : "Unknown"); 352333693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 3524de8c72daSVikas Chaudhary QLA8XXX_DEV_FAILED); 3525f4f5df23SVikas Chaudhary } 3526f4f5df23SVikas Chaudhary 352733693c7aSVikas Chaudhary dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); 3528068237c8STej Parkash ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 3529068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 3530068237c8STej Parkash qdev_state[dev_state] : "Unknown"); 3531f4f5df23SVikas Chaudhary 3532f4f5df23SVikas Chaudhary /* NOTE: Make sure idc unlocked upon exit of switch statement */ 3533f4f5df23SVikas Chaudhary switch (dev_state) { 3534de8c72daSVikas Chaudhary case QLA8XXX_DEV_READY: 3535f4f5df23SVikas Chaudhary goto exit; 3536de8c72daSVikas Chaudhary case QLA8XXX_DEV_COLD: 3537f4f5df23SVikas Chaudhary rval = qla4_8xxx_device_bootstrap(ha); 3538f4f5df23SVikas Chaudhary goto exit; 3539de8c72daSVikas Chaudhary case QLA8XXX_DEV_INITIALIZING: 354033693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3541f4f5df23SVikas Chaudhary msleep(1000); 354233693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3543f4f5df23SVikas Chaudhary break; 3544de8c72daSVikas Chaudhary case QLA8XXX_DEV_NEED_RESET: 35456e7b4292SVikas Chaudhary /* 3546b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, if NEED_RESET is set by any 3547b37ca418SVikas Chaudhary * driver, it should be honored, irrespective of 3548b37ca418SVikas Chaudhary * IDC_CTRL DONTRESET_BIT0 35496e7b4292SVikas Chaudhary */ 3550b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) { 35516e7b4292SVikas Chaudhary qla4_83xx_need_reset_handler(ha); 35526e7b4292SVikas Chaudhary } else if (is_qla8022(ha)) { 3553f4f5df23SVikas Chaudhary if (!ql4xdontresethba) { 3554f8086f4fSVikas Chaudhary qla4_82xx_need_reset_handler(ha); 3555f4f5df23SVikas Chaudhary /* Update timeout value after need 3556f4f5df23SVikas Chaudhary * reset handler */ 3557f4f5df23SVikas Chaudhary dev_init_timeout = jiffies + 3558f4f5df23SVikas Chaudhary (ha->nx_dev_init_timeout * HZ); 35599acf7533SMike Hernandez } else { 356033693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 35619acf7533SMike Hernandez msleep(1000); 356233693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3563f4f5df23SVikas Chaudhary } 3564f4f5df23SVikas Chaudhary } 3565f4f5df23SVikas Chaudhary break; 3566de8c72daSVikas Chaudhary case QLA8XXX_DEV_NEED_QUIESCENT: 3567f4f5df23SVikas Chaudhary /* idc locked/unlocked in handler */ 3568f4f5df23SVikas Chaudhary qla4_8xxx_need_qsnt_handler(ha); 3569e3f37d16SNilesh Javali break; 3570de8c72daSVikas Chaudhary case QLA8XXX_DEV_QUIESCENT: 357133693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3572f4f5df23SVikas Chaudhary msleep(1000); 357333693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3574f4f5df23SVikas Chaudhary break; 3575de8c72daSVikas Chaudhary case QLA8XXX_DEV_FAILED: 357633693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3577f4f5df23SVikas Chaudhary qla4xxx_dead_adapter_cleanup(ha); 3578f4f5df23SVikas Chaudhary rval = QLA_ERROR; 357933693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3580f4f5df23SVikas Chaudhary goto exit; 3581f4f5df23SVikas Chaudhary default: 358233693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3583f4f5df23SVikas Chaudhary qla4xxx_dead_adapter_cleanup(ha); 3584f4f5df23SVikas Chaudhary rval = QLA_ERROR; 358533693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3586f4f5df23SVikas Chaudhary goto exit; 3587f4f5df23SVikas Chaudhary } 3588f4f5df23SVikas Chaudhary } 3589f4f5df23SVikas Chaudhary exit: 359033693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 35916e7b4292SVikas Chaudhary exit_state_handler: 3592f4f5df23SVikas Chaudhary return rval; 3593f4f5df23SVikas Chaudhary } 3594f4f5df23SVikas Chaudhary 3595f4f5df23SVikas Chaudhary int qla4_8xxx_load_risc(struct scsi_qla_host *ha) 3596f4f5df23SVikas Chaudhary { 3597f4f5df23SVikas Chaudhary int retval; 359878764999SSarang Radke 359978764999SSarang Radke /* clear the interrupt */ 3600b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) { 36016e7b4292SVikas Chaudhary writel(0, &ha->qla4_83xx_reg->risc_intr); 36026e7b4292SVikas Chaudhary readl(&ha->qla4_83xx_reg->risc_intr); 36036e7b4292SVikas Chaudhary } else if (is_qla8022(ha)) { 36047664a1fdSVikas Chaudhary writel(0, &ha->qla4_82xx_reg->host_int); 36057664a1fdSVikas Chaudhary readl(&ha->qla4_82xx_reg->host_int); 36066e7b4292SVikas Chaudhary } 360778764999SSarang Radke 3608f4f5df23SVikas Chaudhary retval = qla4_8xxx_device_state_handler(ha); 3609f4f5df23SVikas Chaudhary 36101b3d399cSTej Parkash /* Initialize request and response queues. */ 36111b3d399cSTej Parkash if (retval == QLA_SUCCESS) 36121b3d399cSTej Parkash qla4xxx_init_rings(ha); 36131b3d399cSTej Parkash 3614137257daSPoornima Vonti if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags)) 3615f4f5df23SVikas Chaudhary retval = qla4xxx_request_irqs(ha); 3616f581a3f7SVikas Chaudhary 3617f4f5df23SVikas Chaudhary return retval; 3618f4f5df23SVikas Chaudhary } 3619f4f5df23SVikas Chaudhary 3620f4f5df23SVikas Chaudhary /*****************************************************************************/ 3621f4f5df23SVikas Chaudhary /* Flash Manipulation Routines */ 3622f4f5df23SVikas Chaudhary /*****************************************************************************/ 3623f4f5df23SVikas Chaudhary 3624f4f5df23SVikas Chaudhary #define OPTROM_BURST_SIZE 0x1000 3625f4f5df23SVikas Chaudhary #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3626f4f5df23SVikas Chaudhary 3627f4f5df23SVikas Chaudhary #define FARX_DATA_FLAG BIT_31 3628f4f5df23SVikas Chaudhary #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 3629f4f5df23SVikas Chaudhary #define FARX_ACCESS_FLASH_DATA 0x7FF00000 3630f4f5df23SVikas Chaudhary 3631f4f5df23SVikas Chaudhary static inline uint32_t 3632f4f5df23SVikas Chaudhary flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 3633f4f5df23SVikas Chaudhary { 3634f4f5df23SVikas Chaudhary return hw->flash_conf_off | faddr; 3635f4f5df23SVikas Chaudhary } 3636f4f5df23SVikas Chaudhary 3637f4f5df23SVikas Chaudhary static inline uint32_t 3638f4f5df23SVikas Chaudhary flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 3639f4f5df23SVikas Chaudhary { 3640f4f5df23SVikas Chaudhary return hw->flash_data_off | faddr; 3641f4f5df23SVikas Chaudhary } 3642f4f5df23SVikas Chaudhary 3643f4f5df23SVikas Chaudhary static uint32_t * 3644f8086f4fSVikas Chaudhary qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, 3645f4f5df23SVikas Chaudhary uint32_t faddr, uint32_t length) 3646f4f5df23SVikas Chaudhary { 3647f4f5df23SVikas Chaudhary uint32_t i; 3648f4f5df23SVikas Chaudhary uint32_t val; 3649f4f5df23SVikas Chaudhary int loops = 0; 3650f8086f4fSVikas Chaudhary while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { 3651f4f5df23SVikas Chaudhary udelay(100); 3652f4f5df23SVikas Chaudhary cond_resched(); 3653f4f5df23SVikas Chaudhary loops++; 3654f4f5df23SVikas Chaudhary } 3655f4f5df23SVikas Chaudhary if (loops >= 50000) { 3656f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); 3657f4f5df23SVikas Chaudhary return dwptr; 3658f4f5df23SVikas Chaudhary } 3659f4f5df23SVikas Chaudhary 3660f4f5df23SVikas Chaudhary /* Dword reads to flash. */ 3661f4f5df23SVikas Chaudhary for (i = 0; i < length/4; i++, faddr += 4) { 3662f8086f4fSVikas Chaudhary if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) { 3663f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 3664f4f5df23SVikas Chaudhary "Do ROM fast read failed\n"); 3665f4f5df23SVikas Chaudhary goto done_read; 3666f4f5df23SVikas Chaudhary } 3667f4f5df23SVikas Chaudhary dwptr[i] = __constant_cpu_to_le32(val); 3668f4f5df23SVikas Chaudhary } 3669f4f5df23SVikas Chaudhary 3670f4f5df23SVikas Chaudhary done_read: 3671f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 3672f4f5df23SVikas Chaudhary return dwptr; 3673f4f5df23SVikas Chaudhary } 3674f4f5df23SVikas Chaudhary 3675653557dfSLee Jones /* 3676f4f5df23SVikas Chaudhary * Address and length are byte address 3677653557dfSLee Jones */ 3678f4f5df23SVikas Chaudhary static uint8_t * 3679f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 3680f4f5df23SVikas Chaudhary uint32_t offset, uint32_t length) 3681f4f5df23SVikas Chaudhary { 3682f8086f4fSVikas Chaudhary qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length); 3683f4f5df23SVikas Chaudhary return buf; 3684f4f5df23SVikas Chaudhary } 3685f4f5df23SVikas Chaudhary 3686f4f5df23SVikas Chaudhary static int 3687f4f5df23SVikas Chaudhary qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) 3688f4f5df23SVikas Chaudhary { 3689f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "DEF", "PCI" }; 3690f4f5df23SVikas Chaudhary 3691f4f5df23SVikas Chaudhary /* 3692f4f5df23SVikas Chaudhary * FLT-location structure resides after the last PCI region. 3693f4f5df23SVikas Chaudhary */ 3694f4f5df23SVikas Chaudhary 3695f4f5df23SVikas Chaudhary /* Begin with sane defaults. */ 3696f4f5df23SVikas Chaudhary loc = locations[0]; 3697f4f5df23SVikas Chaudhary *start = FA_FLASH_LAYOUT_ADDR_82; 3698f4f5df23SVikas Chaudhary 3699f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 3700f4f5df23SVikas Chaudhary return QLA_SUCCESS; 3701f4f5df23SVikas Chaudhary } 3702f4f5df23SVikas Chaudhary 3703f4f5df23SVikas Chaudhary static void 3704f4f5df23SVikas Chaudhary qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) 3705f4f5df23SVikas Chaudhary { 3706f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "DEF", "FLT" }; 3707f4f5df23SVikas Chaudhary uint16_t *wptr; 3708f4f5df23SVikas Chaudhary uint16_t cnt, chksum; 37096e7b4292SVikas Chaudhary uint32_t start, status; 3710f4f5df23SVikas Chaudhary struct qla_flt_header *flt; 3711f4f5df23SVikas Chaudhary struct qla_flt_region *region; 3712f4f5df23SVikas Chaudhary struct ql82xx_hw_data *hw = &ha->hw; 3713f4f5df23SVikas Chaudhary 3714f4f5df23SVikas Chaudhary hw->flt_region_flt = flt_addr; 3715f4f5df23SVikas Chaudhary wptr = (uint16_t *)ha->request_ring; 3716f4f5df23SVikas Chaudhary flt = (struct qla_flt_header *)ha->request_ring; 3717f4f5df23SVikas Chaudhary region = (struct qla_flt_region *)&flt[1]; 37186e7b4292SVikas Chaudhary 37196e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 3720f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3721f4f5df23SVikas Chaudhary flt_addr << 2, OPTROM_BURST_SIZE); 3722b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 37236e7b4292SVikas Chaudhary status = qla4_83xx_flash_read_u32(ha, flt_addr << 2, 37246e7b4292SVikas Chaudhary (uint8_t *)ha->request_ring, 37256e7b4292SVikas Chaudhary 0x400); 37266e7b4292SVikas Chaudhary if (status != QLA_SUCCESS) 37276e7b4292SVikas Chaudhary goto no_flash_data; 37286e7b4292SVikas Chaudhary } 37296e7b4292SVikas Chaudhary 3730f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le16(0xffff)) 3731f4f5df23SVikas Chaudhary goto no_flash_data; 3732f4f5df23SVikas Chaudhary if (flt->version != __constant_cpu_to_le16(1)) { 3733f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " 3734f4f5df23SVikas Chaudhary "version=0x%x length=0x%x checksum=0x%x.\n", 3735f4f5df23SVikas Chaudhary le16_to_cpu(flt->version), le16_to_cpu(flt->length), 3736f4f5df23SVikas Chaudhary le16_to_cpu(flt->checksum))); 3737f4f5df23SVikas Chaudhary goto no_flash_data; 3738f4f5df23SVikas Chaudhary } 3739f4f5df23SVikas Chaudhary 3740f4f5df23SVikas Chaudhary cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 3741f4f5df23SVikas Chaudhary for (chksum = 0; cnt; cnt--) 3742f4f5df23SVikas Chaudhary chksum += le16_to_cpu(*wptr++); 3743f4f5df23SVikas Chaudhary if (chksum) { 3744f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 3745f4f5df23SVikas Chaudhary "version=0x%x length=0x%x checksum=0x%x.\n", 3746f4f5df23SVikas Chaudhary le16_to_cpu(flt->version), le16_to_cpu(flt->length), 3747f4f5df23SVikas Chaudhary chksum)); 3748f4f5df23SVikas Chaudhary goto no_flash_data; 3749f4f5df23SVikas Chaudhary } 3750f4f5df23SVikas Chaudhary 3751f4f5df23SVikas Chaudhary loc = locations[1]; 3752f4f5df23SVikas Chaudhary cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 3753f4f5df23SVikas Chaudhary for ( ; cnt; cnt--, region++) { 3754f4f5df23SVikas Chaudhary /* Store addresses as DWORD offsets. */ 3755f4f5df23SVikas Chaudhary start = le32_to_cpu(region->start) >> 2; 3756f4f5df23SVikas Chaudhary 3757f4f5df23SVikas Chaudhary DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 3758f4f5df23SVikas Chaudhary "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 3759f4f5df23SVikas Chaudhary le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 3760f4f5df23SVikas Chaudhary 3761f4f5df23SVikas Chaudhary switch (le32_to_cpu(region->code) & 0xff) { 3762f4f5df23SVikas Chaudhary case FLT_REG_FDT: 3763f4f5df23SVikas Chaudhary hw->flt_region_fdt = start; 3764f4f5df23SVikas Chaudhary break; 3765f4f5df23SVikas Chaudhary case FLT_REG_BOOT_CODE_82: 3766f4f5df23SVikas Chaudhary hw->flt_region_boot = start; 3767f4f5df23SVikas Chaudhary break; 3768f4f5df23SVikas Chaudhary case FLT_REG_FW_82: 376993823956SNilesh Javali case FLT_REG_FW_82_1: 3770f4f5df23SVikas Chaudhary hw->flt_region_fw = start; 3771f4f5df23SVikas Chaudhary break; 3772f4f5df23SVikas Chaudhary case FLT_REG_BOOTLOAD_82: 3773f4f5df23SVikas Chaudhary hw->flt_region_bootload = start; 3774f4f5df23SVikas Chaudhary break; 37752a991c21SManish Rangankar case FLT_REG_ISCSI_PARAM: 37762a991c21SManish Rangankar hw->flt_iscsi_param = start; 37772a991c21SManish Rangankar break; 37784549415aSLalit Chandivade case FLT_REG_ISCSI_CHAP: 37794549415aSLalit Chandivade hw->flt_region_chap = start; 37804549415aSLalit Chandivade hw->flt_chap_size = le32_to_cpu(region->size); 37814549415aSLalit Chandivade break; 37821e9e2be3SAdheer Chandravanshi case FLT_REG_ISCSI_DDB: 37831e9e2be3SAdheer Chandravanshi hw->flt_region_ddb = start; 37841e9e2be3SAdheer Chandravanshi hw->flt_ddb_size = le32_to_cpu(region->size); 37851e9e2be3SAdheer Chandravanshi break; 3786f4f5df23SVikas Chaudhary } 3787f4f5df23SVikas Chaudhary } 3788f4f5df23SVikas Chaudhary goto done; 3789f4f5df23SVikas Chaudhary 3790f4f5df23SVikas Chaudhary no_flash_data: 3791f4f5df23SVikas Chaudhary /* Use hardcoded defaults. */ 3792f4f5df23SVikas Chaudhary loc = locations[0]; 3793f4f5df23SVikas Chaudhary 3794f4f5df23SVikas Chaudhary hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; 3795f4f5df23SVikas Chaudhary hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; 3796f4f5df23SVikas Chaudhary hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; 3797f4f5df23SVikas Chaudhary hw->flt_region_fw = FA_RISC_CODE_ADDR_82; 37989a16f65bSVikas Chaudhary hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2; 37994549415aSLalit Chandivade hw->flt_chap_size = FA_FLASH_CHAP_SIZE; 38001e9e2be3SAdheer Chandravanshi hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2; 38011e9e2be3SAdheer Chandravanshi hw->flt_ddb_size = FA_FLASH_DDB_SIZE; 38024549415aSLalit Chandivade 3803f4f5df23SVikas Chaudhary done: 38049a16f65bSVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 38051e9e2be3SAdheer Chandravanshi "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n", 38069a16f65bSVikas Chaudhary loc, hw->flt_region_flt, hw->flt_region_fdt, 38079a16f65bSVikas Chaudhary hw->flt_region_boot, hw->flt_region_bootload, 38081e9e2be3SAdheer Chandravanshi hw->flt_region_fw, hw->flt_region_chap, 38091e9e2be3SAdheer Chandravanshi hw->flt_chap_size, hw->flt_region_ddb, 38101e9e2be3SAdheer Chandravanshi hw->flt_ddb_size)); 3811f4f5df23SVikas Chaudhary } 3812f4f5df23SVikas Chaudhary 3813f4f5df23SVikas Chaudhary static void 3814f8086f4fSVikas Chaudhary qla4_82xx_get_fdt_info(struct scsi_qla_host *ha) 3815f4f5df23SVikas Chaudhary { 3816f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_4K 0x1000 3817f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_32K 0x8000 3818f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_64K 0x10000 3819f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "MID", "FDT" }; 3820f4f5df23SVikas Chaudhary uint16_t cnt, chksum; 3821f4f5df23SVikas Chaudhary uint16_t *wptr; 3822f4f5df23SVikas Chaudhary struct qla_fdt_layout *fdt; 38233c3e2108SVikas Chaudhary uint16_t mid = 0; 38243c3e2108SVikas Chaudhary uint16_t fid = 0; 3825f4f5df23SVikas Chaudhary struct ql82xx_hw_data *hw = &ha->hw; 3826f4f5df23SVikas Chaudhary 3827f4f5df23SVikas Chaudhary hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3828f4f5df23SVikas Chaudhary hw->flash_data_off = FARX_ACCESS_FLASH_DATA; 3829f4f5df23SVikas Chaudhary 3830f4f5df23SVikas Chaudhary wptr = (uint16_t *)ha->request_ring; 3831f4f5df23SVikas Chaudhary fdt = (struct qla_fdt_layout *)ha->request_ring; 3832f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3833f4f5df23SVikas Chaudhary hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); 3834f4f5df23SVikas Chaudhary 3835f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le16(0xffff)) 3836f4f5df23SVikas Chaudhary goto no_flash_data; 3837f4f5df23SVikas Chaudhary 3838f4f5df23SVikas Chaudhary if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 3839f4f5df23SVikas Chaudhary fdt->sig[3] != 'D') 3840f4f5df23SVikas Chaudhary goto no_flash_data; 3841f4f5df23SVikas Chaudhary 3842f4f5df23SVikas Chaudhary for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 3843f4f5df23SVikas Chaudhary cnt++) 3844f4f5df23SVikas Chaudhary chksum += le16_to_cpu(*wptr++); 3845f4f5df23SVikas Chaudhary 3846f4f5df23SVikas Chaudhary if (chksum) { 3847f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 3848f4f5df23SVikas Chaudhary "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 3849f4f5df23SVikas Chaudhary le16_to_cpu(fdt->version))); 3850f4f5df23SVikas Chaudhary goto no_flash_data; 3851f4f5df23SVikas Chaudhary } 3852f4f5df23SVikas Chaudhary 3853f4f5df23SVikas Chaudhary loc = locations[1]; 3854f4f5df23SVikas Chaudhary mid = le16_to_cpu(fdt->man_id); 3855f4f5df23SVikas Chaudhary fid = le16_to_cpu(fdt->id); 3856f4f5df23SVikas Chaudhary hw->fdt_wrt_disable = fdt->wrt_disable_bits; 3857f4f5df23SVikas Chaudhary hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); 3858f4f5df23SVikas Chaudhary hw->fdt_block_size = le32_to_cpu(fdt->block_size); 3859f4f5df23SVikas Chaudhary 3860f4f5df23SVikas Chaudhary if (fdt->unprotect_sec_cmd) { 3861f4f5df23SVikas Chaudhary hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | 3862f4f5df23SVikas Chaudhary fdt->unprotect_sec_cmd); 3863f4f5df23SVikas Chaudhary hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 3864f4f5df23SVikas Chaudhary flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : 3865f4f5df23SVikas Chaudhary flash_conf_addr(hw, 0x0336); 3866f4f5df23SVikas Chaudhary } 3867f4f5df23SVikas Chaudhary goto done; 3868f4f5df23SVikas Chaudhary 3869f4f5df23SVikas Chaudhary no_flash_data: 3870f4f5df23SVikas Chaudhary loc = locations[0]; 3871f4f5df23SVikas Chaudhary hw->fdt_block_size = FLASH_BLK_SIZE_64K; 3872f4f5df23SVikas Chaudhary done: 3873f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 3874f4f5df23SVikas Chaudhary "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 3875f4f5df23SVikas Chaudhary hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, 3876f4f5df23SVikas Chaudhary hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, 3877f4f5df23SVikas Chaudhary hw->fdt_block_size)); 3878f4f5df23SVikas Chaudhary } 3879f4f5df23SVikas Chaudhary 3880f4f5df23SVikas Chaudhary static void 3881f8086f4fSVikas Chaudhary qla4_82xx_get_idc_param(struct scsi_qla_host *ha) 3882f4f5df23SVikas Chaudhary { 3883f4f5df23SVikas Chaudhary #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 3884f4f5df23SVikas Chaudhary uint32_t *wptr; 3885f4f5df23SVikas Chaudhary 3886f4f5df23SVikas Chaudhary if (!is_qla8022(ha)) 3887f4f5df23SVikas Chaudhary return; 3888f4f5df23SVikas Chaudhary wptr = (uint32_t *)ha->request_ring; 3889f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3890f4f5df23SVikas Chaudhary QLA82XX_IDC_PARAM_ADDR , 8); 3891f4f5df23SVikas Chaudhary 3892f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 3893f4f5df23SVikas Chaudhary ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; 3894f4f5df23SVikas Chaudhary ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; 3895f4f5df23SVikas Chaudhary } else { 3896f4f5df23SVikas Chaudhary ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 3897f4f5df23SVikas Chaudhary ha->nx_reset_timeout = le32_to_cpu(*wptr); 3898f4f5df23SVikas Chaudhary } 3899f4f5df23SVikas Chaudhary 3900f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_DEBUG, ha, 3901f4f5df23SVikas Chaudhary "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); 3902f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_DEBUG, ha, 3903f4f5df23SVikas Chaudhary "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); 3904f4f5df23SVikas Chaudhary return; 3905f4f5df23SVikas Chaudhary } 3906f4f5df23SVikas Chaudhary 390733693c7aSVikas Chaudhary void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, 390833693c7aSVikas Chaudhary int in_count) 390933693c7aSVikas Chaudhary { 391033693c7aSVikas Chaudhary int i; 391133693c7aSVikas Chaudhary 391233693c7aSVikas Chaudhary /* Load all mailbox registers, except mailbox 0. */ 391333693c7aSVikas Chaudhary for (i = 1; i < in_count; i++) 391433693c7aSVikas Chaudhary writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]); 391533693c7aSVikas Chaudhary 391633693c7aSVikas Chaudhary /* Wakeup firmware */ 391733693c7aSVikas Chaudhary writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]); 391833693c7aSVikas Chaudhary readl(&ha->qla4_82xx_reg->mailbox_in[0]); 391933693c7aSVikas Chaudhary writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint); 392033693c7aSVikas Chaudhary readl(&ha->qla4_82xx_reg->hint); 392133693c7aSVikas Chaudhary } 392233693c7aSVikas Chaudhary 392333693c7aSVikas Chaudhary void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count) 392433693c7aSVikas Chaudhary { 392533693c7aSVikas Chaudhary int intr_status; 392633693c7aSVikas Chaudhary 392733693c7aSVikas Chaudhary intr_status = readl(&ha->qla4_82xx_reg->host_int); 392833693c7aSVikas Chaudhary if (intr_status & ISRX_82XX_RISC_INT) { 392933693c7aSVikas Chaudhary ha->mbox_status_count = out_count; 393033693c7aSVikas Chaudhary intr_status = readl(&ha->qla4_82xx_reg->host_status); 393133693c7aSVikas Chaudhary ha->isp_ops->interrupt_service_routine(ha, intr_status); 393233693c7aSVikas Chaudhary 393333693c7aSVikas Chaudhary if (test_bit(AF_INTERRUPTS_ON, &ha->flags) && 3934f5b893c9SChristoph Hellwig (!ha->pdev->msi_enabled && !ha->pdev->msix_enabled)) 393533693c7aSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 393633693c7aSVikas Chaudhary 0xfbff); 393733693c7aSVikas Chaudhary } 393833693c7aSVikas Chaudhary } 393933693c7aSVikas Chaudhary 3940f4f5df23SVikas Chaudhary int 3941f4f5df23SVikas Chaudhary qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 3942f4f5df23SVikas Chaudhary { 3943f4f5df23SVikas Chaudhary int ret; 3944f4f5df23SVikas Chaudhary uint32_t flt_addr; 3945f4f5df23SVikas Chaudhary 3946f4f5df23SVikas Chaudhary ret = qla4_8xxx_find_flt_start(ha, &flt_addr); 3947f4f5df23SVikas Chaudhary if (ret != QLA_SUCCESS) 3948f4f5df23SVikas Chaudhary return ret; 3949f4f5df23SVikas Chaudhary 3950f4f5df23SVikas Chaudhary qla4_8xxx_get_flt_info(ha, flt_addr); 39516e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 3952f8086f4fSVikas Chaudhary qla4_82xx_get_fdt_info(ha); 3953f8086f4fSVikas Chaudhary qla4_82xx_get_idc_param(ha); 3954b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 39556e7b4292SVikas Chaudhary qla4_83xx_get_idc_param(ha); 39566e7b4292SVikas Chaudhary } 3957f4f5df23SVikas Chaudhary 3958f4f5df23SVikas Chaudhary return QLA_SUCCESS; 3959f4f5df23SVikas Chaudhary } 3960f4f5df23SVikas Chaudhary 3961f4f5df23SVikas Chaudhary /** 3962f4f5df23SVikas Chaudhary * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance 3963f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 3964f4f5df23SVikas Chaudhary * 3965f4f5df23SVikas Chaudhary * Remarks: 3966f4f5df23SVikas Chaudhary * For iSCSI, throws away all I/O and AENs into bit bucket, so they will 3967f4f5df23SVikas Chaudhary * not be available after successful return. Driver must cleanup potential 3968f4f5df23SVikas Chaudhary * outstanding I/O's after calling this funcion. 3969f4f5df23SVikas Chaudhary **/ 3970f4f5df23SVikas Chaudhary int 3971f4f5df23SVikas Chaudhary qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) 3972f4f5df23SVikas Chaudhary { 3973f4f5df23SVikas Chaudhary int status; 3974f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 3975f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 3976f4f5df23SVikas Chaudhary 3977f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 3978f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 3979f4f5df23SVikas Chaudhary 3980f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_STOP_FW; 3981f4f5df23SVikas Chaudhary status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, 3982f4f5df23SVikas Chaudhary &mbox_cmd[0], &mbox_sts[0]); 3983f4f5df23SVikas Chaudhary 3984f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, 3985f4f5df23SVikas Chaudhary __func__, status)); 3986f4f5df23SVikas Chaudhary return status; 3987f4f5df23SVikas Chaudhary } 3988f4f5df23SVikas Chaudhary 3989f4f5df23SVikas Chaudhary /** 3990f8086f4fSVikas Chaudhary * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands. 3991f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 3992f4f5df23SVikas Chaudhary **/ 3993f4f5df23SVikas Chaudhary int 3994f8086f4fSVikas Chaudhary qla4_82xx_isp_reset(struct scsi_qla_host *ha) 3995f4f5df23SVikas Chaudhary { 3996f4f5df23SVikas Chaudhary int rval; 3997f4f5df23SVikas Chaudhary uint32_t dev_state; 3998f4f5df23SVikas Chaudhary 3999f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 4000f8086f4fSVikas Chaudhary dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 4001f4f5df23SVikas Chaudhary 4002de8c72daSVikas Chaudhary if (dev_state == QLA8XXX_DEV_READY) { 4003f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 4004f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4005de8c72daSVikas Chaudhary QLA8XXX_DEV_NEED_RESET); 4006de8c72daSVikas Chaudhary set_bit(AF_8XXX_RST_OWNER, &ha->flags); 4007f4f5df23SVikas Chaudhary } else 4008f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); 4009f4f5df23SVikas Chaudhary 4010f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 4011f4f5df23SVikas Chaudhary 4012f4f5df23SVikas Chaudhary rval = qla4_8xxx_device_state_handler(ha); 4013f4f5df23SVikas Chaudhary 4014f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 4015f4f5df23SVikas Chaudhary qla4_8xxx_clear_rst_ready(ha); 4016f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 4017f4f5df23SVikas Chaudhary 4018068237c8STej Parkash if (rval == QLA_SUCCESS) { 4019f8086f4fSVikas Chaudhary ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n"); 402021033639SNilesh Javali clear_bit(AF_FW_RECOVERY, &ha->flags); 4021068237c8STej Parkash } 402221033639SNilesh Javali 4023f4f5df23SVikas Chaudhary return rval; 4024f4f5df23SVikas Chaudhary } 4025f4f5df23SVikas Chaudhary 4026f4f5df23SVikas Chaudhary /** 4027f4f5df23SVikas Chaudhary * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number 4028f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 4029f4f5df23SVikas Chaudhary * 4030f4f5df23SVikas Chaudhary **/ 4031f4f5df23SVikas Chaudhary int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) 4032f4f5df23SVikas Chaudhary { 4033f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 4034f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 4035f4f5df23SVikas Chaudhary struct mbx_sys_info *sys_info; 4036f4f5df23SVikas Chaudhary dma_addr_t sys_info_dma; 4037f4f5df23SVikas Chaudhary int status = QLA_ERROR; 4038f4f5df23SVikas Chaudhary 4039750afb08SLuis Chamberlain sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), 4040f4f5df23SVikas Chaudhary &sys_info_dma, GFP_KERNEL); 4041f4f5df23SVikas Chaudhary if (sys_info == NULL) { 4042f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", 4043f4f5df23SVikas Chaudhary ha->host_no, __func__)); 4044f4f5df23SVikas Chaudhary return status; 4045f4f5df23SVikas Chaudhary } 4046f4f5df23SVikas Chaudhary 4047f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 4048f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 4049f4f5df23SVikas Chaudhary 4050f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; 4051f4f5df23SVikas Chaudhary mbox_cmd[1] = LSDW(sys_info_dma); 4052f4f5df23SVikas Chaudhary mbox_cmd[2] = MSDW(sys_info_dma); 4053f4f5df23SVikas Chaudhary mbox_cmd[4] = sizeof(*sys_info); 4054f4f5df23SVikas Chaudhary 4055f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], 4056f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 4057f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", 4058f4f5df23SVikas Chaudhary ha->host_no, __func__)); 4059f4f5df23SVikas Chaudhary goto exit_validate_mac82; 4060f4f5df23SVikas Chaudhary } 4061f4f5df23SVikas Chaudhary 40622ccdf0dcSVikas Chaudhary /* Make sure we receive the minimum required data to cache internally */ 4063b37ca418SVikas Chaudhary if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) < 4064e19dd66fSNilesh Javali offsetof(struct mbx_sys_info, reserved)) { 4065f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" 4066f4f5df23SVikas Chaudhary " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); 4067f4f5df23SVikas Chaudhary goto exit_validate_mac82; 4068f4f5df23SVikas Chaudhary } 4069f4f5df23SVikas Chaudhary 4070f4f5df23SVikas Chaudhary /* Save M.A.C. address & serial_number */ 40712a991c21SManish Rangankar ha->port_num = sys_info->port_num; 4072f4f5df23SVikas Chaudhary memcpy(ha->my_mac, &sys_info->mac_addr[0], 4073f4f5df23SVikas Chaudhary min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); 4074f4f5df23SVikas Chaudhary memcpy(ha->serial_number, &sys_info->serial_number, 4075f4f5df23SVikas Chaudhary min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); 407691ec7cecSVikas Chaudhary memcpy(ha->model_name, &sys_info->board_id_str, 407791ec7cecSVikas Chaudhary min(sizeof(ha->model_name), sizeof(sys_info->board_id_str))); 407891ec7cecSVikas Chaudhary ha->phy_port_cnt = sys_info->phys_port_cnt; 407991ec7cecSVikas Chaudhary ha->phy_port_num = sys_info->port_num; 408091ec7cecSVikas Chaudhary ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt; 4081f4f5df23SVikas Chaudhary 4082d1d81bd0SOleksandr Khoshaba DEBUG2(printk("scsi%ld: %s: mac %pM serial %s\n", 4083d1d81bd0SOleksandr Khoshaba ha->host_no, __func__, ha->my_mac, ha->serial_number)); 4084f4f5df23SVikas Chaudhary 4085f4f5df23SVikas Chaudhary status = QLA_SUCCESS; 4086f4f5df23SVikas Chaudhary 4087f4f5df23SVikas Chaudhary exit_validate_mac82: 4088f4f5df23SVikas Chaudhary dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, 4089f4f5df23SVikas Chaudhary sys_info_dma); 4090f4f5df23SVikas Chaudhary return status; 4091f4f5df23SVikas Chaudhary } 4092f4f5df23SVikas Chaudhary 4093f4f5df23SVikas Chaudhary /* Interrupt handling helpers. */ 4094f4f5df23SVikas Chaudhary 40955c19b92aSVikas Chaudhary int qla4_8xxx_intr_enable(struct scsi_qla_host *ha) 4096f4f5df23SVikas Chaudhary { 4097f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 4098f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 4099f4f5df23SVikas Chaudhary 4100f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 4101f4f5df23SVikas Chaudhary 4102f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 4103f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 4104f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 4105f4f5df23SVikas Chaudhary mbox_cmd[1] = INTR_ENABLE; 4106f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 4107f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 4108f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 4109f4f5df23SVikas Chaudhary "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 4110f4f5df23SVikas Chaudhary __func__, mbox_sts[0])); 4111f4f5df23SVikas Chaudhary return QLA_ERROR; 4112f4f5df23SVikas Chaudhary } 4113f4f5df23SVikas Chaudhary return QLA_SUCCESS; 4114f4f5df23SVikas Chaudhary } 4115f4f5df23SVikas Chaudhary 41165c19b92aSVikas Chaudhary int qla4_8xxx_intr_disable(struct scsi_qla_host *ha) 4117f4f5df23SVikas Chaudhary { 4118f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 4119f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 4120f4f5df23SVikas Chaudhary 4121f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 4122f4f5df23SVikas Chaudhary 4123f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 4124f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 4125f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 4126f4f5df23SVikas Chaudhary mbox_cmd[1] = INTR_DISABLE; 4127f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 4128f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 4129f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 4130f4f5df23SVikas Chaudhary "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 4131f4f5df23SVikas Chaudhary __func__, mbox_sts[0])); 4132f4f5df23SVikas Chaudhary return QLA_ERROR; 4133f4f5df23SVikas Chaudhary } 4134f4f5df23SVikas Chaudhary 4135f4f5df23SVikas Chaudhary return QLA_SUCCESS; 4136f4f5df23SVikas Chaudhary } 4137f4f5df23SVikas Chaudhary 4138f4f5df23SVikas Chaudhary void 4139f8086f4fSVikas Chaudhary qla4_82xx_enable_intrs(struct scsi_qla_host *ha) 4140f4f5df23SVikas Chaudhary { 41415c19b92aSVikas Chaudhary qla4_8xxx_intr_enable(ha); 4142f4f5df23SVikas Chaudhary 4143f4f5df23SVikas Chaudhary spin_lock_irq(&ha->hardware_lock); 4144f4f5df23SVikas Chaudhary /* BIT 10 - reset */ 4145f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 4146f4f5df23SVikas Chaudhary spin_unlock_irq(&ha->hardware_lock); 4147f4f5df23SVikas Chaudhary set_bit(AF_INTERRUPTS_ON, &ha->flags); 4148f4f5df23SVikas Chaudhary } 4149f4f5df23SVikas Chaudhary 4150f4f5df23SVikas Chaudhary void 4151f8086f4fSVikas Chaudhary qla4_82xx_disable_intrs(struct scsi_qla_host *ha) 4152f4f5df23SVikas Chaudhary { 41535fa8b573SSarang Radke if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) 41545c19b92aSVikas Chaudhary qla4_8xxx_intr_disable(ha); 4155f4f5df23SVikas Chaudhary 4156f4f5df23SVikas Chaudhary spin_lock_irq(&ha->hardware_lock); 4157f4f5df23SVikas Chaudhary /* BIT 10 - set */ 4158f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 4159f4f5df23SVikas Chaudhary spin_unlock_irq(&ha->hardware_lock); 4160f4f5df23SVikas Chaudhary } 4161f4f5df23SVikas Chaudhary 4162f4f5df23SVikas Chaudhary int 4163f4f5df23SVikas Chaudhary qla4_8xxx_enable_msix(struct scsi_qla_host *ha) 4164f4f5df23SVikas Chaudhary { 4165f5b893c9SChristoph Hellwig int ret; 4166f4f5df23SVikas Chaudhary 4167f5b893c9SChristoph Hellwig ret = pci_alloc_irq_vectors(ha->pdev, QLA_MSIX_ENTRIES, 4168f5b893c9SChristoph Hellwig QLA_MSIX_ENTRIES, PCI_IRQ_MSIX); 4169f5b893c9SChristoph Hellwig if (ret < 0) { 4170f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 4171f4f5df23SVikas Chaudhary "MSI-X: Failed to enable support -- %d/%d\n", 4172f4f5df23SVikas Chaudhary QLA_MSIX_ENTRIES, ret); 4173f5b893c9SChristoph Hellwig return ret; 4174f4f5df23SVikas Chaudhary } 4175f4f5df23SVikas Chaudhary 4176f5b893c9SChristoph Hellwig ret = request_irq(pci_irq_vector(ha->pdev, 0), 4177f5b893c9SChristoph Hellwig qla4_8xxx_default_intr_handler, 0, "qla4xxx (default)", 4178f5b893c9SChristoph Hellwig ha); 4179f5b893c9SChristoph Hellwig if (ret) 4180f5b893c9SChristoph Hellwig goto out_free_vectors; 4181f5b893c9SChristoph Hellwig 4182f5b893c9SChristoph Hellwig ret = request_irq(pci_irq_vector(ha->pdev, 1), 4183f5b893c9SChristoph Hellwig qla4_8xxx_msix_rsp_q, 0, "qla4xxx (rsp_q)", ha); 4184f5b893c9SChristoph Hellwig if (ret) 4185f5b893c9SChristoph Hellwig goto out_free_default_irq; 4186f5b893c9SChristoph Hellwig 4187f5b893c9SChristoph Hellwig return 0; 4188f5b893c9SChristoph Hellwig 4189f5b893c9SChristoph Hellwig out_free_default_irq: 4190f5b893c9SChristoph Hellwig free_irq(pci_irq_vector(ha->pdev, 0), ha); 4191f5b893c9SChristoph Hellwig out_free_vectors: 4192f5b893c9SChristoph Hellwig pci_free_irq_vectors(ha->pdev); 4193f4f5df23SVikas Chaudhary return ret; 4194f4f5df23SVikas Chaudhary } 419537418cc6SNilesh Javali 419637418cc6SNilesh Javali int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha) 419737418cc6SNilesh Javali { 419837418cc6SNilesh Javali int status = QLA_SUCCESS; 419937418cc6SNilesh Javali 420037418cc6SNilesh Javali /* Dont retry adapter initialization if IRQ allocation failed */ 420137418cc6SNilesh Javali if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) { 420237418cc6SNilesh Javali ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n", 420337418cc6SNilesh Javali __func__); 420437418cc6SNilesh Javali status = QLA_ERROR; 420537418cc6SNilesh Javali goto exit_init_adapter_failure; 420637418cc6SNilesh Javali } 420737418cc6SNilesh Javali 420837418cc6SNilesh Javali /* Since interrupts are registered in start_firmware for 420937418cc6SNilesh Javali * 8xxx, release them here if initialize_adapter fails 421037418cc6SNilesh Javali * and retry adapter initialization */ 421137418cc6SNilesh Javali qla4xxx_free_irqs(ha); 421237418cc6SNilesh Javali 421337418cc6SNilesh Javali exit_init_adapter_failure: 421437418cc6SNilesh Javali return status; 421537418cc6SNilesh Javali } 4216