1f4f5df23SVikas Chaudhary /* 2f4f5df23SVikas Chaudhary * QLogic iSCSI HBA Driver 34a4f51e9SVikas Chaudhary * Copyright (c) 2003-2013 QLogic Corporation 4f4f5df23SVikas Chaudhary * 5f4f5df23SVikas Chaudhary * See LICENSE.qla4xxx for copyright and licensing details. 6f4f5df23SVikas Chaudhary */ 7f4f5df23SVikas Chaudhary #include <linux/delay.h> 8a6751ccbSJiri Slaby #include <linux/io.h> 9f4f5df23SVikas Chaudhary #include <linux/pci.h> 10068237c8STej Parkash #include <linux/ratelimit.h> 11f4f5df23SVikas Chaudhary #include "ql4_def.h" 12f4f5df23SVikas Chaudhary #include "ql4_glbl.h" 136e7b4292SVikas Chaudhary #include "ql4_inline.h" 14f4f5df23SVikas Chaudhary 152f8e2c87SChristoph Hellwig #include <linux/io-64-nonatomic-lo-hi.h> 16797a796aSHitoshi Mitake 17b1829789STej Parkash #define TIMEOUT_100_MS 100 18f4f5df23SVikas Chaudhary #define MASK(n) DMA_BIT_MASK(n) 19f4f5df23SVikas Chaudhary #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 20f4f5df23SVikas Chaudhary #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 21f4f5df23SVikas Chaudhary #define MS_WIN(addr) (addr & 0x0ffc0000) 22f4f5df23SVikas Chaudhary #define QLA82XX_PCI_MN_2M (0) 23f4f5df23SVikas Chaudhary #define QLA82XX_PCI_MS_2M (0x80000) 24f4f5df23SVikas Chaudhary #define QLA82XX_PCI_OCM0_2M (0xc0000) 25f4f5df23SVikas Chaudhary #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 26f4f5df23SVikas Chaudhary #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 27f4f5df23SVikas Chaudhary 28f4f5df23SVikas Chaudhary /* CRB window related */ 29f4f5df23SVikas Chaudhary #define CRB_BLK(off) ((off >> 20) & 0x3f) 30f4f5df23SVikas Chaudhary #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 31f4f5df23SVikas Chaudhary #define CRB_WINDOW_2M (0x130060) 327664a1fdSVikas Chaudhary #define CRB_HI(off) ((qla4_82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 33f4f5df23SVikas Chaudhary ((off) & 0xf0000)) 34f4f5df23SVikas Chaudhary #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 35f4f5df23SVikas Chaudhary #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 36f4f5df23SVikas Chaudhary #define CRB_INDIRECT_2M (0x1e0000UL) 37f4f5df23SVikas Chaudhary 38f4f5df23SVikas Chaudhary static inline void __iomem * 39f4f5df23SVikas Chaudhary qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) 40f4f5df23SVikas Chaudhary { 41f4f5df23SVikas Chaudhary if ((off < ha->first_page_group_end) && 42f4f5df23SVikas Chaudhary (off >= ha->first_page_group_start)) 43f4f5df23SVikas Chaudhary return (void __iomem *)(ha->nx_pcibase + off); 44f4f5df23SVikas Chaudhary 45f4f5df23SVikas Chaudhary return NULL; 46f4f5df23SVikas Chaudhary } 47f4f5df23SVikas Chaudhary 48f4f5df23SVikas Chaudhary #define MAX_CRB_XFORM 60 49f4f5df23SVikas Chaudhary static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 50f4f5df23SVikas Chaudhary static int qla4_8xxx_crb_table_initialized; 51f4f5df23SVikas Chaudhary 52f4f5df23SVikas Chaudhary #define qla4_8xxx_crb_addr_transform(name) \ 53f4f5df23SVikas Chaudhary (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 54f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 55f4f5df23SVikas Chaudhary static void 56f8086f4fSVikas Chaudhary qla4_82xx_crb_addr_transform_setup(void) 57f4f5df23SVikas Chaudhary { 58f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(XDMA); 59f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(TIMR); 60f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SRE); 61f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN3); 62f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN2); 63f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN1); 64f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQN0); 65f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS3); 66f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS2); 67f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS1); 68f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SQS0); 69f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX7); 70f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX6); 71f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX5); 72f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX4); 73f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX3); 74f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX2); 75f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX1); 76f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(RPMX0); 77f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(ROMUSB); 78f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SN); 79f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(QMN); 80f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(QMS); 81f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGNI); 82f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGND); 83f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN3); 84f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN2); 85f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN1); 86f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGN0); 87f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGSI); 88f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGSD); 89f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS3); 90f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS2); 91f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS1); 92f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PGS0); 93f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PS); 94f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(PH); 95f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(NIU); 96f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(I2Q); 97f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(EG); 98f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(MN); 99f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(MS); 100f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS2); 101f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS1); 102f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAS0); 103f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(CAM); 104f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(C2C1); 105f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(C2C0); 106f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(SMB); 107f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(OCM0); 108f4f5df23SVikas Chaudhary qla4_8xxx_crb_addr_transform(I2C0); 109f4f5df23SVikas Chaudhary 110f4f5df23SVikas Chaudhary qla4_8xxx_crb_table_initialized = 1; 111f4f5df23SVikas Chaudhary } 112f4f5df23SVikas Chaudhary 113f4f5df23SVikas Chaudhary static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 114f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 0: PCI */ 115f4f5df23SVikas Chaudhary {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 116f4f5df23SVikas Chaudhary {1, 0x0110000, 0x0120000, 0x130000}, 117f4f5df23SVikas Chaudhary {1, 0x0120000, 0x0122000, 0x124000}, 118f4f5df23SVikas Chaudhary {1, 0x0130000, 0x0132000, 0x126000}, 119f4f5df23SVikas Chaudhary {1, 0x0140000, 0x0142000, 0x128000}, 120f4f5df23SVikas Chaudhary {1, 0x0150000, 0x0152000, 0x12a000}, 121f4f5df23SVikas Chaudhary {1, 0x0160000, 0x0170000, 0x110000}, 122f4f5df23SVikas Chaudhary {1, 0x0170000, 0x0172000, 0x12e000}, 123f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 124f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 125f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 126f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 127f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 128f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 129f4f5df23SVikas Chaudhary {1, 0x01e0000, 0x01e0800, 0x122000}, 130f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000} } }, 131f4f5df23SVikas Chaudhary {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 132f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 3: */ 133f4f5df23SVikas Chaudhary {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 134f4f5df23SVikas Chaudhary {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 135f4f5df23SVikas Chaudhary {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 136f4f5df23SVikas Chaudhary {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 137f4f5df23SVikas Chaudhary {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 138f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 139f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 140f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 141f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 142f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 143f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 144f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 145f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 146f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 147f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 148f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 149f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 150f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 151f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 152f4f5df23SVikas Chaudhary {1, 0x08f0000, 0x08f2000, 0x172000} } }, 153f4f5df23SVikas Chaudhary {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 154f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 155f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 156f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 157f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 158f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 159f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 160f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 161f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 162f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 163f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 164f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 165f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 166f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 167f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 168f4f5df23SVikas Chaudhary {1, 0x09f0000, 0x09f2000, 0x176000} } }, 169f4f5df23SVikas Chaudhary {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 170f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 171f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 172f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 173f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 174f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 175f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 176f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 177f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 178f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 179f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 180f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 181f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 182f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 183f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 184f4f5df23SVikas Chaudhary {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 185f4f5df23SVikas Chaudhary {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 186f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 187f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 188f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 189f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 190f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 191f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 192f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 193f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 194f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 195f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 196f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 197f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 198f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 199f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 200f4f5df23SVikas Chaudhary {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 201f4f5df23SVikas Chaudhary {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 202f4f5df23SVikas Chaudhary {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 203f4f5df23SVikas Chaudhary {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 204f4f5df23SVikas Chaudhary {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 205f4f5df23SVikas Chaudhary {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 206f4f5df23SVikas Chaudhary {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 207f4f5df23SVikas Chaudhary {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 208f4f5df23SVikas Chaudhary {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 209f4f5df23SVikas Chaudhary {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 210f4f5df23SVikas Chaudhary {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 211f4f5df23SVikas Chaudhary {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 212f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 23: */ 213f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 24: */ 214f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 25: */ 215f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 26: */ 216f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 27: */ 217f4f5df23SVikas Chaudhary {{{0, 0, 0, 0} } }, /* 28: */ 218f4f5df23SVikas Chaudhary {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 219f4f5df23SVikas Chaudhary {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 220f4f5df23SVikas Chaudhary {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 221f4f5df23SVikas Chaudhary {{{0} } }, /* 32: PCI */ 222f4f5df23SVikas Chaudhary {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 223f4f5df23SVikas Chaudhary {1, 0x2110000, 0x2120000, 0x130000}, 224f4f5df23SVikas Chaudhary {1, 0x2120000, 0x2122000, 0x124000}, 225f4f5df23SVikas Chaudhary {1, 0x2130000, 0x2132000, 0x126000}, 226f4f5df23SVikas Chaudhary {1, 0x2140000, 0x2142000, 0x128000}, 227f4f5df23SVikas Chaudhary {1, 0x2150000, 0x2152000, 0x12a000}, 228f4f5df23SVikas Chaudhary {1, 0x2160000, 0x2170000, 0x110000}, 229f4f5df23SVikas Chaudhary {1, 0x2170000, 0x2172000, 0x12e000}, 230f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 231f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 232f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 233f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 234f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 235f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 236f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000}, 237f4f5df23SVikas Chaudhary {0, 0x0000000, 0x0000000, 0x000000} } }, 238f4f5df23SVikas Chaudhary {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 239f4f5df23SVikas Chaudhary {{{0} } }, /* 35: */ 240f4f5df23SVikas Chaudhary {{{0} } }, /* 36: */ 241f4f5df23SVikas Chaudhary {{{0} } }, /* 37: */ 242f4f5df23SVikas Chaudhary {{{0} } }, /* 38: */ 243f4f5df23SVikas Chaudhary {{{0} } }, /* 39: */ 244f4f5df23SVikas Chaudhary {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 245f4f5df23SVikas Chaudhary {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 246f4f5df23SVikas Chaudhary {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 247f4f5df23SVikas Chaudhary {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 248f4f5df23SVikas Chaudhary {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 249f4f5df23SVikas Chaudhary {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 250f4f5df23SVikas Chaudhary {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 251f4f5df23SVikas Chaudhary {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 252f4f5df23SVikas Chaudhary {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 253f4f5df23SVikas Chaudhary {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 254f4f5df23SVikas Chaudhary {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 255f4f5df23SVikas Chaudhary {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 256f4f5df23SVikas Chaudhary {{{0} } }, /* 52: */ 257f4f5df23SVikas Chaudhary {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 258f4f5df23SVikas Chaudhary {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 259f4f5df23SVikas Chaudhary {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 260f4f5df23SVikas Chaudhary {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 261f4f5df23SVikas Chaudhary {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 262f4f5df23SVikas Chaudhary {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 263f4f5df23SVikas Chaudhary {{{0} } }, /* 59: I2C0 */ 264f4f5df23SVikas Chaudhary {{{0} } }, /* 60: I2C1 */ 265f4f5df23SVikas Chaudhary {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ 266f4f5df23SVikas Chaudhary {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 267f4f5df23SVikas Chaudhary {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 268f4f5df23SVikas Chaudhary }; 269f4f5df23SVikas Chaudhary 270f4f5df23SVikas Chaudhary /* 271f4f5df23SVikas Chaudhary * top 12 bits of crb internal address (hub, agent) 272f4f5df23SVikas Chaudhary */ 2737664a1fdSVikas Chaudhary static unsigned qla4_82xx_crb_hub_agt[64] = { 274f4f5df23SVikas Chaudhary 0, 275f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 276f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 277f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 278f4f5df23SVikas Chaudhary 0, 279f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 280f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 281f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 282f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 283f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 284f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 285f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 286f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 287f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 288f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 289f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 290f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 291f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 292f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 293f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 294f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 295f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 296f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 297f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 298f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 299f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 300f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 301f4f5df23SVikas Chaudhary 0, 302f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 303f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 304f4f5df23SVikas Chaudhary 0, 305f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 306f4f5df23SVikas Chaudhary 0, 307f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 308f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 309f4f5df23SVikas Chaudhary 0, 310f4f5df23SVikas Chaudhary 0, 311f4f5df23SVikas Chaudhary 0, 312f4f5df23SVikas Chaudhary 0, 313f4f5df23SVikas Chaudhary 0, 314f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 315f4f5df23SVikas Chaudhary 0, 316f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 317f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 318f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 319f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 320f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 321f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 322f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 323f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 324f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 325f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 326f4f5df23SVikas Chaudhary 0, 327f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 328f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 329f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 330f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 331f4f5df23SVikas Chaudhary 0, 332f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 333f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 334f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 335f4f5df23SVikas Chaudhary 0, 336f4f5df23SVikas Chaudhary QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 337f4f5df23SVikas Chaudhary 0, 338f4f5df23SVikas Chaudhary }; 339f4f5df23SVikas Chaudhary 340f4f5df23SVikas Chaudhary /* Device states */ 341f4f5df23SVikas Chaudhary static char *qdev_state[] = { 342f4f5df23SVikas Chaudhary "Unknown", 343f4f5df23SVikas Chaudhary "Cold", 344f4f5df23SVikas Chaudhary "Initializing", 345f4f5df23SVikas Chaudhary "Ready", 346f4f5df23SVikas Chaudhary "Need Reset", 347f4f5df23SVikas Chaudhary "Need Quiescent", 348f4f5df23SVikas Chaudhary "Failed", 349f4f5df23SVikas Chaudhary "Quiescent", 350f4f5df23SVikas Chaudhary }; 351f4f5df23SVikas Chaudhary 352f4f5df23SVikas Chaudhary /* 353f4f5df23SVikas Chaudhary * In: 'off' is offset from CRB space in 128M pci map 354f4f5df23SVikas Chaudhary * Out: 'off' is 2M pci map addr 355f4f5df23SVikas Chaudhary * side effect: lock crb window 356f4f5df23SVikas Chaudhary */ 357f4f5df23SVikas Chaudhary static void 358f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) 359f4f5df23SVikas Chaudhary { 360f4f5df23SVikas Chaudhary u32 win_read; 361f4f5df23SVikas Chaudhary 362f4f5df23SVikas Chaudhary ha->crb_win = CRB_HI(*off); 363f4f5df23SVikas Chaudhary writel(ha->crb_win, 364f4f5df23SVikas Chaudhary (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 365f4f5df23SVikas Chaudhary 366f4f5df23SVikas Chaudhary /* Read back value to make sure write has gone through before trying 367f4f5df23SVikas Chaudhary * to use it. */ 368f4f5df23SVikas Chaudhary win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 369f4f5df23SVikas Chaudhary if (win_read != ha->crb_win) { 370f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 371f4f5df23SVikas Chaudhary "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," 372f4f5df23SVikas Chaudhary " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 373f4f5df23SVikas Chaudhary } 374f4f5df23SVikas Chaudhary *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 375f4f5df23SVikas Chaudhary } 376f4f5df23SVikas Chaudhary 377f4f5df23SVikas Chaudhary void 378f8086f4fSVikas Chaudhary qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) 379f4f5df23SVikas Chaudhary { 380f4f5df23SVikas Chaudhary unsigned long flags = 0; 381f4f5df23SVikas Chaudhary int rv; 382f4f5df23SVikas Chaudhary 383f8086f4fSVikas Chaudhary rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); 384f4f5df23SVikas Chaudhary 385f4f5df23SVikas Chaudhary BUG_ON(rv == -1); 386f4f5df23SVikas Chaudhary 387f4f5df23SVikas Chaudhary if (rv == 1) { 388f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 389f8086f4fSVikas Chaudhary qla4_82xx_crb_win_lock(ha); 390f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(ha, &off); 391f4f5df23SVikas Chaudhary } 392f4f5df23SVikas Chaudhary 393f4f5df23SVikas Chaudhary writel(data, (void __iomem *)off); 394f4f5df23SVikas Chaudhary 395f4f5df23SVikas Chaudhary if (rv == 1) { 396f8086f4fSVikas Chaudhary qla4_82xx_crb_win_unlock(ha); 397f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 398f4f5df23SVikas Chaudhary } 399f4f5df23SVikas Chaudhary } 400f4f5df23SVikas Chaudhary 40133693c7aSVikas Chaudhary uint32_t qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off) 402f4f5df23SVikas Chaudhary { 403f4f5df23SVikas Chaudhary unsigned long flags = 0; 404f4f5df23SVikas Chaudhary int rv; 405f4f5df23SVikas Chaudhary u32 data; 406f4f5df23SVikas Chaudhary 407f8086f4fSVikas Chaudhary rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off); 408f4f5df23SVikas Chaudhary 409f4f5df23SVikas Chaudhary BUG_ON(rv == -1); 410f4f5df23SVikas Chaudhary 411f4f5df23SVikas Chaudhary if (rv == 1) { 412f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 413f8086f4fSVikas Chaudhary qla4_82xx_crb_win_lock(ha); 414f8086f4fSVikas Chaudhary qla4_82xx_pci_set_crbwindow_2M(ha, &off); 415f4f5df23SVikas Chaudhary } 416f4f5df23SVikas Chaudhary data = readl((void __iomem *)off); 417f4f5df23SVikas Chaudhary 418f4f5df23SVikas Chaudhary if (rv == 1) { 419f8086f4fSVikas Chaudhary qla4_82xx_crb_win_unlock(ha); 420f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 421f4f5df23SVikas Chaudhary } 422f4f5df23SVikas Chaudhary return data; 423f4f5df23SVikas Chaudhary } 424f4f5df23SVikas Chaudhary 425068237c8STej Parkash /* Minidump related functions */ 42633693c7aSVikas Chaudhary int qla4_82xx_md_rd_32(struct scsi_qla_host *ha, uint32_t off, uint32_t *data) 427068237c8STej Parkash { 42833693c7aSVikas Chaudhary uint32_t win_read, off_value; 42933693c7aSVikas Chaudhary int rval = QLA_SUCCESS; 43033693c7aSVikas Chaudhary 43133693c7aSVikas Chaudhary off_value = off & 0xFFFF0000; 43233693c7aSVikas Chaudhary writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 43333693c7aSVikas Chaudhary 43433693c7aSVikas Chaudhary /* 43533693c7aSVikas Chaudhary * Read back value to make sure write has gone through before trying 43633693c7aSVikas Chaudhary * to use it. 43733693c7aSVikas Chaudhary */ 43833693c7aSVikas Chaudhary win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 43933693c7aSVikas Chaudhary if (win_read != off_value) { 44033693c7aSVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 44133693c7aSVikas Chaudhary "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 44233693c7aSVikas Chaudhary __func__, off_value, win_read, off)); 44333693c7aSVikas Chaudhary rval = QLA_ERROR; 44433693c7aSVikas Chaudhary } else { 44533693c7aSVikas Chaudhary off_value = off & 0x0000FFFF; 44633693c7aSVikas Chaudhary *data = readl((void __iomem *)(off_value + CRB_INDIRECT_2M + 44733693c7aSVikas Chaudhary ha->nx_pcibase)); 44833693c7aSVikas Chaudhary } 44933693c7aSVikas Chaudhary return rval; 45033693c7aSVikas Chaudhary } 45133693c7aSVikas Chaudhary 45233693c7aSVikas Chaudhary int qla4_82xx_md_wr_32(struct scsi_qla_host *ha, uint32_t off, uint32_t data) 45333693c7aSVikas Chaudhary { 45433693c7aSVikas Chaudhary uint32_t win_read, off_value; 45533693c7aSVikas Chaudhary int rval = QLA_SUCCESS; 456068237c8STej Parkash 457068237c8STej Parkash off_value = off & 0xFFFF0000; 458068237c8STej Parkash writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 459068237c8STej Parkash 460068237c8STej Parkash /* Read back value to make sure write has gone through before trying 461068237c8STej Parkash * to use it. 462068237c8STej Parkash */ 463068237c8STej Parkash win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 464068237c8STej Parkash if (win_read != off_value) { 465068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 466068237c8STej Parkash "%s: Written (0x%x) != Read (0x%x), off=0x%x\n", 467068237c8STej Parkash __func__, off_value, win_read, off)); 46833693c7aSVikas Chaudhary rval = QLA_ERROR; 46933693c7aSVikas Chaudhary } else { 470068237c8STej Parkash off_value = off & 0x0000FFFF; 471068237c8STej Parkash writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M + 472068237c8STej Parkash ha->nx_pcibase)); 47333693c7aSVikas Chaudhary } 474068237c8STej Parkash return rval; 475068237c8STej Parkash } 476068237c8STej Parkash 477f4f5df23SVikas Chaudhary #define CRB_WIN_LOCK_TIMEOUT 100000000 478f4f5df23SVikas Chaudhary 479f8086f4fSVikas Chaudhary int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha) 480f4f5df23SVikas Chaudhary { 481f4f5df23SVikas Chaudhary int i; 482f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 483f4f5df23SVikas Chaudhary 484f4f5df23SVikas Chaudhary while (!done) { 485f4f5df23SVikas Chaudhary /* acquire semaphore3 from PCI HW block */ 486f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 487f4f5df23SVikas Chaudhary if (done == 1) 488f4f5df23SVikas Chaudhary break; 489f4f5df23SVikas Chaudhary if (timeout >= CRB_WIN_LOCK_TIMEOUT) 490f4f5df23SVikas Chaudhary return -1; 491f4f5df23SVikas Chaudhary 492f4f5df23SVikas Chaudhary timeout++; 493f4f5df23SVikas Chaudhary 494f4f5df23SVikas Chaudhary /* Yield CPU */ 495f4f5df23SVikas Chaudhary if (!in_interrupt()) 496f4f5df23SVikas Chaudhary schedule(); 497f4f5df23SVikas Chaudhary else { 498f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 499f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 500f4f5df23SVikas Chaudhary } 501f4f5df23SVikas Chaudhary } 502f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); 503f4f5df23SVikas Chaudhary return 0; 504f4f5df23SVikas Chaudhary } 505f4f5df23SVikas Chaudhary 506f8086f4fSVikas Chaudhary void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha) 507f4f5df23SVikas Chaudhary { 508f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 509f4f5df23SVikas Chaudhary } 510f4f5df23SVikas Chaudhary 511f4f5df23SVikas Chaudhary #define IDC_LOCK_TIMEOUT 100000000 512f4f5df23SVikas Chaudhary 513f4f5df23SVikas Chaudhary /** 514f8086f4fSVikas Chaudhary * qla4_82xx_idc_lock - hw_lock 515f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 516f4f5df23SVikas Chaudhary * 517f4f5df23SVikas Chaudhary * General purpose lock used to synchronize access to 518f4f5df23SVikas Chaudhary * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. 519f4f5df23SVikas Chaudhary **/ 520f8086f4fSVikas Chaudhary int qla4_82xx_idc_lock(struct scsi_qla_host *ha) 521f4f5df23SVikas Chaudhary { 522f4f5df23SVikas Chaudhary int i; 523f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 524f4f5df23SVikas Chaudhary 525f4f5df23SVikas Chaudhary while (!done) { 526f4f5df23SVikas Chaudhary /* acquire semaphore5 from PCI HW block */ 527f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 528f4f5df23SVikas Chaudhary if (done == 1) 529f4f5df23SVikas Chaudhary break; 530f4f5df23SVikas Chaudhary if (timeout >= IDC_LOCK_TIMEOUT) 531f4f5df23SVikas Chaudhary return -1; 532f4f5df23SVikas Chaudhary 533f4f5df23SVikas Chaudhary timeout++; 534f4f5df23SVikas Chaudhary 535f4f5df23SVikas Chaudhary /* Yield CPU */ 536f4f5df23SVikas Chaudhary if (!in_interrupt()) 537f4f5df23SVikas Chaudhary schedule(); 538f4f5df23SVikas Chaudhary else { 539f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 540f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 541f4f5df23SVikas Chaudhary } 542f4f5df23SVikas Chaudhary } 543f4f5df23SVikas Chaudhary return 0; 544f4f5df23SVikas Chaudhary } 545f4f5df23SVikas Chaudhary 546f8086f4fSVikas Chaudhary void qla4_82xx_idc_unlock(struct scsi_qla_host *ha) 547f4f5df23SVikas Chaudhary { 548f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 549f4f5df23SVikas Chaudhary } 550f4f5df23SVikas Chaudhary 551f4f5df23SVikas Chaudhary int 552f8086f4fSVikas Chaudhary qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) 553f4f5df23SVikas Chaudhary { 554f4f5df23SVikas Chaudhary struct crb_128M_2M_sub_block_map *m; 555f4f5df23SVikas Chaudhary 556f4f5df23SVikas Chaudhary if (*off >= QLA82XX_CRB_MAX) 557f4f5df23SVikas Chaudhary return -1; 558f4f5df23SVikas Chaudhary 559f4f5df23SVikas Chaudhary if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 560f4f5df23SVikas Chaudhary *off = (*off - QLA82XX_PCI_CAMQM) + 561f4f5df23SVikas Chaudhary QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 562f4f5df23SVikas Chaudhary return 0; 563f4f5df23SVikas Chaudhary } 564f4f5df23SVikas Chaudhary 565f4f5df23SVikas Chaudhary if (*off < QLA82XX_PCI_CRBSPACE) 566f4f5df23SVikas Chaudhary return -1; 567f4f5df23SVikas Chaudhary 568f4f5df23SVikas Chaudhary *off -= QLA82XX_PCI_CRBSPACE; 569f4f5df23SVikas Chaudhary /* 570f4f5df23SVikas Chaudhary * Try direct map 571f4f5df23SVikas Chaudhary */ 572f4f5df23SVikas Chaudhary 573f4f5df23SVikas Chaudhary m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 574f4f5df23SVikas Chaudhary 575f4f5df23SVikas Chaudhary if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 576f4f5df23SVikas Chaudhary *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 577f4f5df23SVikas Chaudhary return 0; 578f4f5df23SVikas Chaudhary } 579f4f5df23SVikas Chaudhary 580f4f5df23SVikas Chaudhary /* 581f4f5df23SVikas Chaudhary * Not in direct map, use crb window 582f4f5df23SVikas Chaudhary */ 583f4f5df23SVikas Chaudhary return 1; 584f4f5df23SVikas Chaudhary } 585f4f5df23SVikas Chaudhary 586f4f5df23SVikas Chaudhary /* 587f4f5df23SVikas Chaudhary * check memory access boundary. 588f4f5df23SVikas Chaudhary * used by test agent. support ddr access only for now 589f4f5df23SVikas Chaudhary */ 590f4f5df23SVikas Chaudhary static unsigned long 591f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha, 592f4f5df23SVikas Chaudhary unsigned long long addr, int size) 593f4f5df23SVikas Chaudhary { 594de8c72daSVikas Chaudhary if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 595de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX) || 596de8c72daSVikas Chaudhary !QLA8XXX_ADDR_IN_RANGE(addr + size - 1, 597de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) || 598f4f5df23SVikas Chaudhary ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { 599f4f5df23SVikas Chaudhary return 0; 600f4f5df23SVikas Chaudhary } 601f4f5df23SVikas Chaudhary return 1; 602f4f5df23SVikas Chaudhary } 603f4f5df23SVikas Chaudhary 6047664a1fdSVikas Chaudhary static int qla4_82xx_pci_set_window_warning_count; 605f4f5df23SVikas Chaudhary 606f4f5df23SVikas Chaudhary static unsigned long 607f8086f4fSVikas Chaudhary qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) 608f4f5df23SVikas Chaudhary { 609f4f5df23SVikas Chaudhary int window; 610f4f5df23SVikas Chaudhary u32 win_read; 611f4f5df23SVikas Chaudhary 612de8c72daSVikas Chaudhary if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 613de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX)) { 614f4f5df23SVikas Chaudhary /* DDR network side */ 615f4f5df23SVikas Chaudhary window = MN_WIN(addr); 616f4f5df23SVikas Chaudhary ha->ddr_mn_window = window; 617f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->mn_win_crb | 618f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 619f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | 620f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE); 621f4f5df23SVikas Chaudhary if ((win_read << 17) != window) { 622f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 623f4f5df23SVikas Chaudhary "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 624f4f5df23SVikas Chaudhary __func__, window, win_read); 625f4f5df23SVikas Chaudhary } 626f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 627de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, 628de8c72daSVikas Chaudhary QLA8XXX_ADDR_OCM0_MAX)) { 629f4f5df23SVikas Chaudhary unsigned int temp1; 630f4f5df23SVikas Chaudhary /* if bits 19:18&17:11 are on */ 631f4f5df23SVikas Chaudhary if ((addr & 0x00ff800) == 0xff800) { 632f4f5df23SVikas Chaudhary printk("%s: QM access not handled.\n", __func__); 633f4f5df23SVikas Chaudhary addr = -1UL; 634f4f5df23SVikas Chaudhary } 635f4f5df23SVikas Chaudhary 636f4f5df23SVikas Chaudhary window = OCM_WIN(addr); 637f4f5df23SVikas Chaudhary ha->ddr_mn_window = window; 638f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->mn_win_crb | 639f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 640f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb | 641f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE); 642f4f5df23SVikas Chaudhary temp1 = ((window & 0x1FF) << 7) | 643f4f5df23SVikas Chaudhary ((window & 0x0FFFE0000) >> 17); 644f4f5df23SVikas Chaudhary if (win_read != temp1) { 645f4f5df23SVikas Chaudhary printk("%s: Written OCMwin (0x%x) != Read" 646f4f5df23SVikas Chaudhary " OCMwin (0x%x)\n", __func__, temp1, win_read); 647f4f5df23SVikas Chaudhary } 648f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 649f4f5df23SVikas Chaudhary 650de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 651f4f5df23SVikas Chaudhary QLA82XX_P3_ADDR_QDR_NET_MAX)) { 652f4f5df23SVikas Chaudhary /* QDR network side */ 653f4f5df23SVikas Chaudhary window = MS_WIN(addr); 654f4f5df23SVikas Chaudhary ha->qdr_sn_window = window; 655f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->ms_win_crb | 656f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE, window); 657f8086f4fSVikas Chaudhary win_read = qla4_82xx_rd_32(ha, 658f4f5df23SVikas Chaudhary ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 659f4f5df23SVikas Chaudhary if (win_read != window) { 660f4f5df23SVikas Chaudhary printk("%s: Written MSwin (0x%x) != Read " 661f4f5df23SVikas Chaudhary "MSwin (0x%x)\n", __func__, window, win_read); 662f4f5df23SVikas Chaudhary } 663f4f5df23SVikas Chaudhary addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 664f4f5df23SVikas Chaudhary 665f4f5df23SVikas Chaudhary } else { 666f4f5df23SVikas Chaudhary /* 667f4f5df23SVikas Chaudhary * peg gdb frequently accesses memory that doesn't exist, 668f4f5df23SVikas Chaudhary * this limits the chit chat so debugging isn't slowed down. 669f4f5df23SVikas Chaudhary */ 6707664a1fdSVikas Chaudhary if ((qla4_82xx_pci_set_window_warning_count++ < 8) || 6717664a1fdSVikas Chaudhary (qla4_82xx_pci_set_window_warning_count%64 == 0)) { 672f4f5df23SVikas Chaudhary printk("%s: Warning:%s Unknown address range!\n", 673f4f5df23SVikas Chaudhary __func__, DRIVER_NAME); 674f4f5df23SVikas Chaudhary } 675f4f5df23SVikas Chaudhary addr = -1UL; 676f4f5df23SVikas Chaudhary } 677f4f5df23SVikas Chaudhary return addr; 678f4f5df23SVikas Chaudhary } 679f4f5df23SVikas Chaudhary 680f4f5df23SVikas Chaudhary /* check if address is in the same windows as the previous access */ 681f8086f4fSVikas Chaudhary static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha, 682f4f5df23SVikas Chaudhary unsigned long long addr) 683f4f5df23SVikas Chaudhary { 684f4f5df23SVikas Chaudhary int window; 685f4f5df23SVikas Chaudhary unsigned long long qdr_max; 686f4f5df23SVikas Chaudhary 687f4f5df23SVikas Chaudhary qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 688f4f5df23SVikas Chaudhary 689de8c72daSVikas Chaudhary if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 690de8c72daSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX)) { 691f4f5df23SVikas Chaudhary /* DDR network side */ 692f4f5df23SVikas Chaudhary BUG(); /* MN access can not come here */ 693de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0, 694de8c72daSVikas Chaudhary QLA8XXX_ADDR_OCM0_MAX)) { 695f4f5df23SVikas Chaudhary return 1; 696de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1, 697de8c72daSVikas Chaudhary QLA8XXX_ADDR_OCM1_MAX)) { 698f4f5df23SVikas Chaudhary return 1; 699de8c72daSVikas Chaudhary } else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 700f4f5df23SVikas Chaudhary qdr_max)) { 701f4f5df23SVikas Chaudhary /* QDR network side */ 702de8c72daSVikas Chaudhary window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f; 703f4f5df23SVikas Chaudhary if (ha->qdr_sn_window == window) 704f4f5df23SVikas Chaudhary return 1; 705f4f5df23SVikas Chaudhary } 706f4f5df23SVikas Chaudhary 707f4f5df23SVikas Chaudhary return 0; 708f4f5df23SVikas Chaudhary } 709f4f5df23SVikas Chaudhary 710f8086f4fSVikas Chaudhary static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha, 711f4f5df23SVikas Chaudhary u64 off, void *data, int size) 712f4f5df23SVikas Chaudhary { 713f4f5df23SVikas Chaudhary unsigned long flags; 714f4f5df23SVikas Chaudhary void __iomem *addr; 715f4f5df23SVikas Chaudhary int ret = 0; 716f4f5df23SVikas Chaudhary u64 start; 717f4f5df23SVikas Chaudhary void __iomem *mem_ptr = NULL; 718f4f5df23SVikas Chaudhary unsigned long mem_base; 719f4f5df23SVikas Chaudhary unsigned long mem_page; 720f4f5df23SVikas Chaudhary 721f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 722f4f5df23SVikas Chaudhary 723f4f5df23SVikas Chaudhary /* 724f4f5df23SVikas Chaudhary * If attempting to access unknown address or straddle hw windows, 725f4f5df23SVikas Chaudhary * do not access. 726f4f5df23SVikas Chaudhary */ 727f8086f4fSVikas Chaudhary start = qla4_82xx_pci_set_window(ha, off); 728f4f5df23SVikas Chaudhary if ((start == -1UL) || 729f8086f4fSVikas Chaudhary (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 730f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 731f4f5df23SVikas Chaudhary printk(KERN_ERR"%s out of bound pci memory access. " 732f4f5df23SVikas Chaudhary "offset is 0x%llx\n", DRIVER_NAME, off); 733f4f5df23SVikas Chaudhary return -1; 734f4f5df23SVikas Chaudhary } 735f4f5df23SVikas Chaudhary 736f4f5df23SVikas Chaudhary addr = qla4_8xxx_pci_base_offsetfset(ha, start); 737f4f5df23SVikas Chaudhary if (!addr) { 738f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 739f4f5df23SVikas Chaudhary mem_base = pci_resource_start(ha->pdev, 0); 740f4f5df23SVikas Chaudhary mem_page = start & PAGE_MASK; 741f4f5df23SVikas Chaudhary /* Map two pages whenever user tries to access addresses in two 742f4f5df23SVikas Chaudhary consecutive pages. 743f4f5df23SVikas Chaudhary */ 744f4f5df23SVikas Chaudhary if (mem_page != ((start + size - 1) & PAGE_MASK)) 745f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 746f4f5df23SVikas Chaudhary else 747f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 748f4f5df23SVikas Chaudhary 749f4f5df23SVikas Chaudhary if (mem_ptr == NULL) { 750f4f5df23SVikas Chaudhary *(u8 *)data = 0; 751f4f5df23SVikas Chaudhary return -1; 752f4f5df23SVikas Chaudhary } 753f4f5df23SVikas Chaudhary addr = mem_ptr; 754f4f5df23SVikas Chaudhary addr += start & (PAGE_SIZE - 1); 755f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 756f4f5df23SVikas Chaudhary } 757f4f5df23SVikas Chaudhary 758f4f5df23SVikas Chaudhary switch (size) { 759f4f5df23SVikas Chaudhary case 1: 760f4f5df23SVikas Chaudhary *(u8 *)data = readb(addr); 761f4f5df23SVikas Chaudhary break; 762f4f5df23SVikas Chaudhary case 2: 763f4f5df23SVikas Chaudhary *(u16 *)data = readw(addr); 764f4f5df23SVikas Chaudhary break; 765f4f5df23SVikas Chaudhary case 4: 766f4f5df23SVikas Chaudhary *(u32 *)data = readl(addr); 767f4f5df23SVikas Chaudhary break; 768f4f5df23SVikas Chaudhary case 8: 769f4f5df23SVikas Chaudhary *(u64 *)data = readq(addr); 770f4f5df23SVikas Chaudhary break; 771f4f5df23SVikas Chaudhary default: 772f4f5df23SVikas Chaudhary ret = -1; 773f4f5df23SVikas Chaudhary break; 774f4f5df23SVikas Chaudhary } 775f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 776f4f5df23SVikas Chaudhary 777f4f5df23SVikas Chaudhary if (mem_ptr) 778f4f5df23SVikas Chaudhary iounmap(mem_ptr); 779f4f5df23SVikas Chaudhary return ret; 780f4f5df23SVikas Chaudhary } 781f4f5df23SVikas Chaudhary 782f4f5df23SVikas Chaudhary static int 783f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, 784f4f5df23SVikas Chaudhary void *data, int size) 785f4f5df23SVikas Chaudhary { 786f4f5df23SVikas Chaudhary unsigned long flags; 787f4f5df23SVikas Chaudhary void __iomem *addr; 788f4f5df23SVikas Chaudhary int ret = 0; 789f4f5df23SVikas Chaudhary u64 start; 790f4f5df23SVikas Chaudhary void __iomem *mem_ptr = NULL; 791f4f5df23SVikas Chaudhary unsigned long mem_base; 792f4f5df23SVikas Chaudhary unsigned long mem_page; 793f4f5df23SVikas Chaudhary 794f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 795f4f5df23SVikas Chaudhary 796f4f5df23SVikas Chaudhary /* 797f4f5df23SVikas Chaudhary * If attempting to access unknown address or straddle hw windows, 798f4f5df23SVikas Chaudhary * do not access. 799f4f5df23SVikas Chaudhary */ 800f8086f4fSVikas Chaudhary start = qla4_82xx_pci_set_window(ha, off); 801f4f5df23SVikas Chaudhary if ((start == -1UL) || 802f8086f4fSVikas Chaudhary (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) { 803f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 804f4f5df23SVikas Chaudhary printk(KERN_ERR"%s out of bound pci memory access. " 805f4f5df23SVikas Chaudhary "offset is 0x%llx\n", DRIVER_NAME, off); 806f4f5df23SVikas Chaudhary return -1; 807f4f5df23SVikas Chaudhary } 808f4f5df23SVikas Chaudhary 809f4f5df23SVikas Chaudhary addr = qla4_8xxx_pci_base_offsetfset(ha, start); 810f4f5df23SVikas Chaudhary if (!addr) { 811f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 812f4f5df23SVikas Chaudhary mem_base = pci_resource_start(ha->pdev, 0); 813f4f5df23SVikas Chaudhary mem_page = start & PAGE_MASK; 814f4f5df23SVikas Chaudhary /* Map two pages whenever user tries to access addresses in two 815f4f5df23SVikas Chaudhary consecutive pages. 816f4f5df23SVikas Chaudhary */ 817f4f5df23SVikas Chaudhary if (mem_page != ((start + size - 1) & PAGE_MASK)) 818f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 819f4f5df23SVikas Chaudhary else 820f4f5df23SVikas Chaudhary mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 821f4f5df23SVikas Chaudhary if (mem_ptr == NULL) 822f4f5df23SVikas Chaudhary return -1; 823f4f5df23SVikas Chaudhary 824f4f5df23SVikas Chaudhary addr = mem_ptr; 825f4f5df23SVikas Chaudhary addr += start & (PAGE_SIZE - 1); 826f4f5df23SVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 827f4f5df23SVikas Chaudhary } 828f4f5df23SVikas Chaudhary 829f4f5df23SVikas Chaudhary switch (size) { 830f4f5df23SVikas Chaudhary case 1: 831f4f5df23SVikas Chaudhary writeb(*(u8 *)data, addr); 832f4f5df23SVikas Chaudhary break; 833f4f5df23SVikas Chaudhary case 2: 834f4f5df23SVikas Chaudhary writew(*(u16 *)data, addr); 835f4f5df23SVikas Chaudhary break; 836f4f5df23SVikas Chaudhary case 4: 837f4f5df23SVikas Chaudhary writel(*(u32 *)data, addr); 838f4f5df23SVikas Chaudhary break; 839f4f5df23SVikas Chaudhary case 8: 840f4f5df23SVikas Chaudhary writeq(*(u64 *)data, addr); 841f4f5df23SVikas Chaudhary break; 842f4f5df23SVikas Chaudhary default: 843f4f5df23SVikas Chaudhary ret = -1; 844f4f5df23SVikas Chaudhary break; 845f4f5df23SVikas Chaudhary } 846f4f5df23SVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 847f4f5df23SVikas Chaudhary if (mem_ptr) 848f4f5df23SVikas Chaudhary iounmap(mem_ptr); 849f4f5df23SVikas Chaudhary return ret; 850f4f5df23SVikas Chaudhary } 851f4f5df23SVikas Chaudhary 852f4f5df23SVikas Chaudhary #define MTU_FUDGE_FACTOR 100 853f4f5df23SVikas Chaudhary 854f4f5df23SVikas Chaudhary static unsigned long 855f8086f4fSVikas Chaudhary qla4_82xx_decode_crb_addr(unsigned long addr) 856f4f5df23SVikas Chaudhary { 857f4f5df23SVikas Chaudhary int i; 858f4f5df23SVikas Chaudhary unsigned long base_addr, offset, pci_base; 859f4f5df23SVikas Chaudhary 860f4f5df23SVikas Chaudhary if (!qla4_8xxx_crb_table_initialized) 861f8086f4fSVikas Chaudhary qla4_82xx_crb_addr_transform_setup(); 862f4f5df23SVikas Chaudhary 863f4f5df23SVikas Chaudhary pci_base = ADDR_ERROR; 864f4f5df23SVikas Chaudhary base_addr = addr & 0xfff00000; 865f4f5df23SVikas Chaudhary offset = addr & 0x000fffff; 866f4f5df23SVikas Chaudhary 867f4f5df23SVikas Chaudhary for (i = 0; i < MAX_CRB_XFORM; i++) { 868f4f5df23SVikas Chaudhary if (crb_addr_xform[i] == base_addr) { 869f4f5df23SVikas Chaudhary pci_base = i << 20; 870f4f5df23SVikas Chaudhary break; 871f4f5df23SVikas Chaudhary } 872f4f5df23SVikas Chaudhary } 873f4f5df23SVikas Chaudhary if (pci_base == ADDR_ERROR) 874f4f5df23SVikas Chaudhary return pci_base; 875f4f5df23SVikas Chaudhary else 876f4f5df23SVikas Chaudhary return pci_base + offset; 877f4f5df23SVikas Chaudhary } 878f4f5df23SVikas Chaudhary 879f4f5df23SVikas Chaudhary static long rom_max_timeout = 100; 8807664a1fdSVikas Chaudhary static long qla4_82xx_rom_lock_timeout = 100; 881f4f5df23SVikas Chaudhary 882f4f5df23SVikas Chaudhary static int 883f8086f4fSVikas Chaudhary qla4_82xx_rom_lock(struct scsi_qla_host *ha) 884f4f5df23SVikas Chaudhary { 885f4f5df23SVikas Chaudhary int i; 886f4f5df23SVikas Chaudhary int done = 0, timeout = 0; 887f4f5df23SVikas Chaudhary 888f4f5df23SVikas Chaudhary while (!done) { 889f4f5df23SVikas Chaudhary /* acquire semaphore2 from PCI HW block */ 890f4f5df23SVikas Chaudhary 891f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 892f4f5df23SVikas Chaudhary if (done == 1) 893f4f5df23SVikas Chaudhary break; 8947664a1fdSVikas Chaudhary if (timeout >= qla4_82xx_rom_lock_timeout) 895f4f5df23SVikas Chaudhary return -1; 896f4f5df23SVikas Chaudhary 897f4f5df23SVikas Chaudhary timeout++; 898f4f5df23SVikas Chaudhary 899f4f5df23SVikas Chaudhary /* Yield CPU */ 900f4f5df23SVikas Chaudhary if (!in_interrupt()) 901f4f5df23SVikas Chaudhary schedule(); 902f4f5df23SVikas Chaudhary else { 903f4f5df23SVikas Chaudhary for (i = 0; i < 20; i++) 904f4f5df23SVikas Chaudhary cpu_relax(); /*This a nop instr on i386*/ 905f4f5df23SVikas Chaudhary } 906f4f5df23SVikas Chaudhary } 907f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 908f4f5df23SVikas Chaudhary return 0; 909f4f5df23SVikas Chaudhary } 910f4f5df23SVikas Chaudhary 911f4f5df23SVikas Chaudhary static void 912f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(struct scsi_qla_host *ha) 913f4f5df23SVikas Chaudhary { 914f8086f4fSVikas Chaudhary qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 915f4f5df23SVikas Chaudhary } 916f4f5df23SVikas Chaudhary 917f4f5df23SVikas Chaudhary static int 918f8086f4fSVikas Chaudhary qla4_82xx_wait_rom_done(struct scsi_qla_host *ha) 919f4f5df23SVikas Chaudhary { 920f4f5df23SVikas Chaudhary long timeout = 0; 921f4f5df23SVikas Chaudhary long done = 0 ; 922f4f5df23SVikas Chaudhary 923f4f5df23SVikas Chaudhary while (done == 0) { 924f8086f4fSVikas Chaudhary done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 925f4f5df23SVikas Chaudhary done &= 2; 926f4f5df23SVikas Chaudhary timeout++; 927f4f5df23SVikas Chaudhary if (timeout >= rom_max_timeout) { 928f4f5df23SVikas Chaudhary printk("%s: Timeout reached waiting for rom done", 929f4f5df23SVikas Chaudhary DRIVER_NAME); 930f4f5df23SVikas Chaudhary return -1; 931f4f5df23SVikas Chaudhary } 932f4f5df23SVikas Chaudhary } 933f4f5df23SVikas Chaudhary return 0; 934f4f5df23SVikas Chaudhary } 935f4f5df23SVikas Chaudhary 936f4f5df23SVikas Chaudhary static int 937f8086f4fSVikas Chaudhary qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 938f4f5df23SVikas Chaudhary { 939f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 940f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 941f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 942f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 943f8086f4fSVikas Chaudhary if (qla4_82xx_wait_rom_done(ha)) { 944f4f5df23SVikas Chaudhary printk("%s: Error waiting for rom done\n", DRIVER_NAME); 945f4f5df23SVikas Chaudhary return -1; 946f4f5df23SVikas Chaudhary } 947f4f5df23SVikas Chaudhary /* reset abyte_cnt and dummy_byte_cnt */ 948f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 949f4f5df23SVikas Chaudhary udelay(10); 950f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 951f4f5df23SVikas Chaudhary 952f8086f4fSVikas Chaudhary *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 953f4f5df23SVikas Chaudhary return 0; 954f4f5df23SVikas Chaudhary } 955f4f5df23SVikas Chaudhary 956f4f5df23SVikas Chaudhary static int 957f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 958f4f5df23SVikas Chaudhary { 959f4f5df23SVikas Chaudhary int ret, loops = 0; 960f4f5df23SVikas Chaudhary 961f8086f4fSVikas Chaudhary while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { 962f4f5df23SVikas Chaudhary udelay(100); 963f4f5df23SVikas Chaudhary loops++; 964f4f5df23SVikas Chaudhary } 965f4f5df23SVikas Chaudhary if (loops >= 50000) { 966f8086f4fSVikas Chaudhary ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n", 967f8086f4fSVikas Chaudhary DRIVER_NAME); 968f4f5df23SVikas Chaudhary return -1; 969f4f5df23SVikas Chaudhary } 970f8086f4fSVikas Chaudhary ret = qla4_82xx_do_rom_fast_read(ha, addr, valp); 971f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 972f4f5df23SVikas Chaudhary return ret; 973f4f5df23SVikas Chaudhary } 974f4f5df23SVikas Chaudhary 975f4f5df23SVikas Chaudhary /** 976f4f5df23SVikas Chaudhary * This routine does CRB initialize sequence 977f4f5df23SVikas Chaudhary * to put the ISP into operational state 978f4f5df23SVikas Chaudhary **/ 979f4f5df23SVikas Chaudhary static int 980f8086f4fSVikas Chaudhary qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) 981f4f5df23SVikas Chaudhary { 982f4f5df23SVikas Chaudhary int addr, val; 983f4f5df23SVikas Chaudhary int i ; 984f4f5df23SVikas Chaudhary struct crb_addr_pair *buf; 985f4f5df23SVikas Chaudhary unsigned long off; 986f4f5df23SVikas Chaudhary unsigned offset, n; 987f4f5df23SVikas Chaudhary 988f4f5df23SVikas Chaudhary struct crb_addr_pair { 989f4f5df23SVikas Chaudhary long addr; 990f4f5df23SVikas Chaudhary long data; 991f4f5df23SVikas Chaudhary }; 992f4f5df23SVikas Chaudhary 993f4f5df23SVikas Chaudhary /* Halt all the indiviual PEGs and other blocks of the ISP */ 994f8086f4fSVikas Chaudhary qla4_82xx_rom_lock(ha); 995a1fc26baSSwapnil Nagle 996cb74428eSVikas Chaudhary /* disable all I2Q */ 997f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 998f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 999f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 1000f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 1001f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 1002f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 1003cb74428eSVikas Chaudhary 1004cb74428eSVikas Chaudhary /* disable all niu interrupts */ 1005f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 1006a1fc26baSSwapnil Nagle /* disable xge rx/tx */ 1007f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 1008a1fc26baSSwapnil Nagle /* disable xg1 rx/tx */ 1009f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 1010cb74428eSVikas Chaudhary /* disable sideband mac */ 1011f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 1012cb74428eSVikas Chaudhary /* disable ap0 mac */ 1013f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 1014cb74428eSVikas Chaudhary /* disable ap1 mac */ 1015f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 1016a1fc26baSSwapnil Nagle 1017a1fc26baSSwapnil Nagle /* halt sre */ 1018f8086f4fSVikas Chaudhary val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 1019f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 1020a1fc26baSSwapnil Nagle 1021a1fc26baSSwapnil Nagle /* halt epg */ 1022f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 1023a1fc26baSSwapnil Nagle 1024a1fc26baSSwapnil Nagle /* halt timers */ 1025f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 1026f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 1027f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 1028f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 1029f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 1030f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 1031a1fc26baSSwapnil Nagle 1032a1fc26baSSwapnil Nagle /* halt pegs */ 1033f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 1034f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 1035f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 1036f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 1037f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 1038cb74428eSVikas Chaudhary msleep(5); 1039a1fc26baSSwapnil Nagle 1040a1fc26baSSwapnil Nagle /* big hammer */ 1041f4f5df23SVikas Chaudhary if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 1042f4f5df23SVikas Chaudhary /* don't reset CAM block on reset */ 1043f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 1044f4f5df23SVikas Chaudhary else 1045f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 1046f4f5df23SVikas Chaudhary 1047f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 1048f4f5df23SVikas Chaudhary 1049f4f5df23SVikas Chaudhary /* Read the signature value from the flash. 1050f4f5df23SVikas Chaudhary * Offset 0: Contain signature (0xcafecafe) 1051f4f5df23SVikas Chaudhary * Offset 4: Offset and number of addr/value pairs 1052f4f5df23SVikas Chaudhary * that present in CRB initialize sequence 1053f4f5df23SVikas Chaudhary */ 1054f8086f4fSVikas Chaudhary if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1055f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(ha, 4, &n) != 0) { 1056f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1057f4f5df23SVikas Chaudhary "[ERROR] Reading crb_init area: n: %08x\n", n); 1058f4f5df23SVikas Chaudhary return -1; 1059f4f5df23SVikas Chaudhary } 1060f4f5df23SVikas Chaudhary 1061f4f5df23SVikas Chaudhary /* Offset in flash = lower 16 bits 1062f4f5df23SVikas Chaudhary * Number of enteries = upper 16 bits 1063f4f5df23SVikas Chaudhary */ 1064f4f5df23SVikas Chaudhary offset = n & 0xffffU; 1065f4f5df23SVikas Chaudhary n = (n >> 16) & 0xffffU; 1066f4f5df23SVikas Chaudhary 1067f4f5df23SVikas Chaudhary /* number of addr/value pair should not exceed 1024 enteries */ 1068f4f5df23SVikas Chaudhary if (n >= 1024) { 1069f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1070f4f5df23SVikas Chaudhary "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1071f4f5df23SVikas Chaudhary DRIVER_NAME, __func__, n); 1072f4f5df23SVikas Chaudhary return -1; 1073f4f5df23SVikas Chaudhary } 1074f4f5df23SVikas Chaudhary 1075f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1076f4f5df23SVikas Chaudhary "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); 1077f4f5df23SVikas Chaudhary 1078f4f5df23SVikas Chaudhary buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1079f4f5df23SVikas Chaudhary if (buf == NULL) { 1080f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1081f4f5df23SVikas Chaudhary "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); 1082f4f5df23SVikas Chaudhary return -1; 1083f4f5df23SVikas Chaudhary } 1084f4f5df23SVikas Chaudhary 1085f4f5df23SVikas Chaudhary for (i = 0; i < n; i++) { 1086f8086f4fSVikas Chaudhary if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1087f8086f4fSVikas Chaudhary qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 1088f4f5df23SVikas Chaudhary 0) { 1089f4f5df23SVikas Chaudhary kfree(buf); 1090f4f5df23SVikas Chaudhary return -1; 1091f4f5df23SVikas Chaudhary } 1092f4f5df23SVikas Chaudhary 1093f4f5df23SVikas Chaudhary buf[i].addr = addr; 1094f4f5df23SVikas Chaudhary buf[i].data = val; 1095f4f5df23SVikas Chaudhary } 1096f4f5df23SVikas Chaudhary 1097f4f5df23SVikas Chaudhary for (i = 0; i < n; i++) { 1098f4f5df23SVikas Chaudhary /* Translate internal CRB initialization 1099f4f5df23SVikas Chaudhary * address to PCI bus address 1100f4f5df23SVikas Chaudhary */ 1101f8086f4fSVikas Chaudhary off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) + 1102f4f5df23SVikas Chaudhary QLA82XX_PCI_CRBSPACE; 1103f4f5df23SVikas Chaudhary /* Not all CRB addr/value pair to be written, 1104f4f5df23SVikas Chaudhary * some of them are skipped 1105f4f5df23SVikas Chaudhary */ 1106f4f5df23SVikas Chaudhary 1107f4f5df23SVikas Chaudhary /* skip if LS bit is set*/ 1108f4f5df23SVikas Chaudhary if (off & 0x1) { 1109f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_WARNING, ha, 1110f4f5df23SVikas Chaudhary "Skip CRB init replay for offset = 0x%lx\n", off)); 1111f4f5df23SVikas Chaudhary continue; 1112f4f5df23SVikas Chaudhary } 1113f4f5df23SVikas Chaudhary 1114f4f5df23SVikas Chaudhary /* skipping cold reboot MAGIC */ 1115f4f5df23SVikas Chaudhary if (off == QLA82XX_CAM_RAM(0x1fc)) 1116f4f5df23SVikas Chaudhary continue; 1117f4f5df23SVikas Chaudhary 1118f4f5df23SVikas Chaudhary /* do not reset PCI */ 1119f4f5df23SVikas Chaudhary if (off == (ROMUSB_GLB + 0xbc)) 1120f4f5df23SVikas Chaudhary continue; 1121f4f5df23SVikas Chaudhary 1122f4f5df23SVikas Chaudhary /* skip core clock, so that firmware can increase the clock */ 1123f4f5df23SVikas Chaudhary if (off == (ROMUSB_GLB + 0xc8)) 1124f4f5df23SVikas Chaudhary continue; 1125f4f5df23SVikas Chaudhary 1126f4f5df23SVikas Chaudhary /* skip the function enable register */ 1127f4f5df23SVikas Chaudhary if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1128f4f5df23SVikas Chaudhary continue; 1129f4f5df23SVikas Chaudhary 1130f4f5df23SVikas Chaudhary if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1131f4f5df23SVikas Chaudhary continue; 1132f4f5df23SVikas Chaudhary 1133f4f5df23SVikas Chaudhary if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1134f4f5df23SVikas Chaudhary continue; 1135f4f5df23SVikas Chaudhary 1136f4f5df23SVikas Chaudhary if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1137f4f5df23SVikas Chaudhary continue; 1138f4f5df23SVikas Chaudhary 1139f4f5df23SVikas Chaudhary if (off == ADDR_ERROR) { 1140f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 1141f4f5df23SVikas Chaudhary "%s: [ERROR] Unknown addr: 0x%08lx\n", 1142f4f5df23SVikas Chaudhary DRIVER_NAME, buf[i].addr); 1143f4f5df23SVikas Chaudhary continue; 1144f4f5df23SVikas Chaudhary } 1145f4f5df23SVikas Chaudhary 1146f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, off, buf[i].data); 1147f4f5df23SVikas Chaudhary 1148f4f5df23SVikas Chaudhary /* ISP requires much bigger delay to settle down, 1149f4f5df23SVikas Chaudhary * else crb_window returns 0xffffffff 1150f4f5df23SVikas Chaudhary */ 1151f4f5df23SVikas Chaudhary if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1152f4f5df23SVikas Chaudhary msleep(1000); 1153f4f5df23SVikas Chaudhary 1154f4f5df23SVikas Chaudhary /* ISP requires millisec delay between 1155f4f5df23SVikas Chaudhary * successive CRB register updation 1156f4f5df23SVikas Chaudhary */ 1157f4f5df23SVikas Chaudhary msleep(1); 1158f4f5df23SVikas Chaudhary } 1159f4f5df23SVikas Chaudhary 1160f4f5df23SVikas Chaudhary kfree(buf); 1161f4f5df23SVikas Chaudhary 1162f4f5df23SVikas Chaudhary /* Resetting the data and instruction cache */ 1163f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1164f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1165f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1166f4f5df23SVikas Chaudhary 1167f4f5df23SVikas Chaudhary /* Clear all protocol processing engines */ 1168f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1169f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1170f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1171f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1172f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1173f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1174f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1175f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1176f4f5df23SVikas Chaudhary 1177f4f5df23SVikas Chaudhary return 0; 1178f4f5df23SVikas Chaudhary } 1179f4f5df23SVikas Chaudhary 1180dd3b854eSVikas Chaudhary /** 1181dd3b854eSVikas Chaudhary * qla4_8xxx_ms_mem_write_128b - Writes data to MS/off-chip memory 1182dd3b854eSVikas Chaudhary * @ha: Pointer to adapter structure 1183dd3b854eSVikas Chaudhary * @addr: Flash address to write to 1184dd3b854eSVikas Chaudhary * @data: Data to be written 1185dd3b854eSVikas Chaudhary * @count: word_count to be written 1186dd3b854eSVikas Chaudhary * 1187dd3b854eSVikas Chaudhary * Return: On success return QLA_SUCCESS 1188dd3b854eSVikas Chaudhary * On error return QLA_ERROR 1189dd3b854eSVikas Chaudhary **/ 1190dd3b854eSVikas Chaudhary int qla4_8xxx_ms_mem_write_128b(struct scsi_qla_host *ha, uint64_t addr, 1191dd3b854eSVikas Chaudhary uint32_t *data, uint32_t count) 1192dd3b854eSVikas Chaudhary { 1193dd3b854eSVikas Chaudhary int i, j; 1194dd3b854eSVikas Chaudhary uint32_t agt_ctrl; 1195dd3b854eSVikas Chaudhary unsigned long flags; 1196dd3b854eSVikas Chaudhary int ret_val = QLA_SUCCESS; 1197dd3b854eSVikas Chaudhary 1198dd3b854eSVikas Chaudhary /* Only 128-bit aligned access */ 1199dd3b854eSVikas Chaudhary if (addr & 0xF) { 1200dd3b854eSVikas Chaudhary ret_val = QLA_ERROR; 1201dd3b854eSVikas Chaudhary goto exit_ms_mem_write; 1202dd3b854eSVikas Chaudhary } 1203dd3b854eSVikas Chaudhary 1204dd3b854eSVikas Chaudhary write_lock_irqsave(&ha->hw_lock, flags); 1205dd3b854eSVikas Chaudhary 1206dd3b854eSVikas Chaudhary /* Write address */ 1207dd3b854eSVikas Chaudhary ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 0); 1208dd3b854eSVikas Chaudhary if (ret_val == QLA_ERROR) { 1209dd3b854eSVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: write to AGT_ADDR_HI failed\n", 1210dd3b854eSVikas Chaudhary __func__); 1211dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1212dd3b854eSVikas Chaudhary } 1213dd3b854eSVikas Chaudhary 1214dd3b854eSVikas Chaudhary for (i = 0; i < count; i++, addr += 16) { 1215dd3b854eSVikas Chaudhary if (!((QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET, 1216dd3b854eSVikas Chaudhary QLA8XXX_ADDR_QDR_NET_MAX)) || 1217dd3b854eSVikas Chaudhary (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET, 1218dd3b854eSVikas Chaudhary QLA8XXX_ADDR_DDR_NET_MAX)))) { 1219dd3b854eSVikas Chaudhary ret_val = QLA_ERROR; 1220dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1221dd3b854eSVikas Chaudhary } 1222dd3b854eSVikas Chaudhary 1223dd3b854eSVikas Chaudhary ret_val = ha->isp_ops->wr_reg_indirect(ha, 1224dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_ADDR_LO, 1225dd3b854eSVikas Chaudhary addr); 1226dd3b854eSVikas Chaudhary /* Write data */ 1227dd3b854eSVikas Chaudhary ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1228dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_WRDATA_LO, 1229dd3b854eSVikas Chaudhary *data++); 1230dd3b854eSVikas Chaudhary ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1231dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_WRDATA_HI, 1232dd3b854eSVikas Chaudhary *data++); 1233dd3b854eSVikas Chaudhary ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1234dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_WRDATA_ULO, 1235dd3b854eSVikas Chaudhary *data++); 1236dd3b854eSVikas Chaudhary ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1237dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_WRDATA_UHI, 1238dd3b854eSVikas Chaudhary *data++); 1239dd3b854eSVikas Chaudhary if (ret_val == QLA_ERROR) { 1240dd3b854eSVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: write to AGT_WRDATA failed\n", 1241dd3b854eSVikas Chaudhary __func__); 1242dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1243dd3b854eSVikas Chaudhary } 1244dd3b854eSVikas Chaudhary 1245dd3b854eSVikas Chaudhary /* Check write status */ 1246dd3b854eSVikas Chaudhary ret_val = ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, 1247dd3b854eSVikas Chaudhary MIU_TA_CTL_WRITE_ENABLE); 1248dd3b854eSVikas Chaudhary ret_val |= ha->isp_ops->wr_reg_indirect(ha, 1249dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_CTRL, 1250dd3b854eSVikas Chaudhary MIU_TA_CTL_WRITE_START); 1251dd3b854eSVikas Chaudhary if (ret_val == QLA_ERROR) { 1252dd3b854eSVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: write to AGT_CTRL failed\n", 1253dd3b854eSVikas Chaudhary __func__); 1254dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1255dd3b854eSVikas Chaudhary } 1256dd3b854eSVikas Chaudhary 1257dd3b854eSVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1258dd3b854eSVikas Chaudhary ret_val = ha->isp_ops->rd_reg_indirect(ha, 1259dd3b854eSVikas Chaudhary MD_MIU_TEST_AGT_CTRL, 1260dd3b854eSVikas Chaudhary &agt_ctrl); 1261dd3b854eSVikas Chaudhary if (ret_val == QLA_ERROR) { 1262dd3b854eSVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: failed to read MD_MIU_TEST_AGT_CTRL\n", 1263dd3b854eSVikas Chaudhary __func__); 1264dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1265dd3b854eSVikas Chaudhary } 1266dd3b854eSVikas Chaudhary if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0) 1267dd3b854eSVikas Chaudhary break; 1268dd3b854eSVikas Chaudhary } 1269dd3b854eSVikas Chaudhary 1270dd3b854eSVikas Chaudhary /* Status check failed */ 1271dd3b854eSVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1272dd3b854eSVikas Chaudhary printk_ratelimited(KERN_ERR "%s: MS memory write failed!\n", 1273dd3b854eSVikas Chaudhary __func__); 1274dd3b854eSVikas Chaudhary ret_val = QLA_ERROR; 1275dd3b854eSVikas Chaudhary goto exit_ms_mem_write_unlock; 1276dd3b854eSVikas Chaudhary } 1277dd3b854eSVikas Chaudhary } 1278dd3b854eSVikas Chaudhary 1279dd3b854eSVikas Chaudhary exit_ms_mem_write_unlock: 1280dd3b854eSVikas Chaudhary write_unlock_irqrestore(&ha->hw_lock, flags); 1281dd3b854eSVikas Chaudhary 1282dd3b854eSVikas Chaudhary exit_ms_mem_write: 1283dd3b854eSVikas Chaudhary return ret_val; 1284dd3b854eSVikas Chaudhary } 1285dd3b854eSVikas Chaudhary 1286f4f5df23SVikas Chaudhary static int 1287f8086f4fSVikas Chaudhary qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) 1288f4f5df23SVikas Chaudhary { 12894cd83cbeSLalit Chandivade int i, rval = 0; 1290f4f5df23SVikas Chaudhary long size = 0; 1291f4f5df23SVikas Chaudhary long flashaddr, memaddr; 1292f4f5df23SVikas Chaudhary u64 data; 1293f4f5df23SVikas Chaudhary u32 high, low; 1294f4f5df23SVikas Chaudhary 1295f4f5df23SVikas Chaudhary flashaddr = memaddr = ha->hw.flt_region_bootload; 1296f4f5df23SVikas Chaudhary size = (image_start - flashaddr) / 8; 1297f4f5df23SVikas Chaudhary 1298f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", 1299f4f5df23SVikas Chaudhary ha->host_no, __func__, flashaddr, image_start)); 1300f4f5df23SVikas Chaudhary 1301f4f5df23SVikas Chaudhary for (i = 0; i < size; i++) { 1302f8086f4fSVikas Chaudhary if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1303f8086f4fSVikas Chaudhary (qla4_82xx_rom_fast_read(ha, flashaddr + 4, 1304f4f5df23SVikas Chaudhary (int *)&high))) { 13054cd83cbeSLalit Chandivade rval = -1; 13064cd83cbeSLalit Chandivade goto exit_load_from_flash; 1307f4f5df23SVikas Chaudhary } 1308f4f5df23SVikas Chaudhary data = ((u64)high << 32) | low ; 1309f8086f4fSVikas Chaudhary rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8); 13104cd83cbeSLalit Chandivade if (rval) 13114cd83cbeSLalit Chandivade goto exit_load_from_flash; 13124cd83cbeSLalit Chandivade 1313f4f5df23SVikas Chaudhary flashaddr += 8; 1314f4f5df23SVikas Chaudhary memaddr += 8; 1315f4f5df23SVikas Chaudhary 1316f4f5df23SVikas Chaudhary if (i % 0x1000 == 0) 1317f4f5df23SVikas Chaudhary msleep(1); 1318f4f5df23SVikas Chaudhary 1319f4f5df23SVikas Chaudhary } 1320f4f5df23SVikas Chaudhary 1321f4f5df23SVikas Chaudhary udelay(100); 1322f4f5df23SVikas Chaudhary 1323f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1324f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1325f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1326f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1327f4f5df23SVikas Chaudhary 13284cd83cbeSLalit Chandivade exit_load_from_flash: 13294cd83cbeSLalit Chandivade return rval; 1330f4f5df23SVikas Chaudhary } 1331f4f5df23SVikas Chaudhary 1332f8086f4fSVikas Chaudhary static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) 1333f4f5df23SVikas Chaudhary { 1334f4f5df23SVikas Chaudhary u32 rst; 1335f4f5df23SVikas Chaudhary 1336f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1337f8086f4fSVikas Chaudhary if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { 1338f4f5df23SVikas Chaudhary printk(KERN_WARNING "%s: Error during CRB Initialization\n", 1339f4f5df23SVikas Chaudhary __func__); 1340f4f5df23SVikas Chaudhary return QLA_ERROR; 1341f4f5df23SVikas Chaudhary } 1342f4f5df23SVikas Chaudhary 1343f4f5df23SVikas Chaudhary udelay(500); 1344f4f5df23SVikas Chaudhary 1345f4f5df23SVikas Chaudhary /* at this point, QM is in reset. This could be a problem if there are 1346f4f5df23SVikas Chaudhary * incoming d* transition queue messages. QM/PCIE could wedge. 1347f4f5df23SVikas Chaudhary * To get around this, QM is brought out of reset. 1348f4f5df23SVikas Chaudhary */ 1349f4f5df23SVikas Chaudhary 1350f8086f4fSVikas Chaudhary rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 1351f4f5df23SVikas Chaudhary /* unreset qm */ 1352f4f5df23SVikas Chaudhary rst &= ~(1 << 28); 1353f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 1354f4f5df23SVikas Chaudhary 1355f8086f4fSVikas Chaudhary if (qla4_82xx_load_from_flash(ha, image_start)) { 1356f4f5df23SVikas Chaudhary printk("%s: Error trying to load fw from flash!\n", __func__); 1357f4f5df23SVikas Chaudhary return QLA_ERROR; 1358f4f5df23SVikas Chaudhary } 1359f4f5df23SVikas Chaudhary 1360f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1361f4f5df23SVikas Chaudhary } 1362f4f5df23SVikas Chaudhary 1363f4f5df23SVikas Chaudhary int 1364f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha, 1365f4f5df23SVikas Chaudhary u64 off, void *data, int size) 1366f4f5df23SVikas Chaudhary { 1367f4f5df23SVikas Chaudhary int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1368f4f5df23SVikas Chaudhary int shift_amount; 1369f4f5df23SVikas Chaudhary uint32_t temp; 1370f4f5df23SVikas Chaudhary uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1371f4f5df23SVikas Chaudhary 1372f4f5df23SVikas Chaudhary /* 1373f4f5df23SVikas Chaudhary * If not MN, go check for MS or invalid. 1374f4f5df23SVikas Chaudhary */ 1375f4f5df23SVikas Chaudhary 1376de8c72daSVikas Chaudhary if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1377f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_QDR_NET; 1378f4f5df23SVikas Chaudhary else { 1379f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_DDR_NET; 1380f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) 1381f8086f4fSVikas Chaudhary return qla4_82xx_pci_mem_read_direct(ha, 1382f4f5df23SVikas Chaudhary off, data, size); 1383f4f5df23SVikas Chaudhary } 1384f4f5df23SVikas Chaudhary 1385f4f5df23SVikas Chaudhary 1386f4f5df23SVikas Chaudhary off8 = off & 0xfffffff0; 1387f4f5df23SVikas Chaudhary off0[0] = off & 0xf; 1388f4f5df23SVikas Chaudhary sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1389f4f5df23SVikas Chaudhary shift_amount = 4; 1390f4f5df23SVikas Chaudhary 1391f4f5df23SVikas Chaudhary loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1392f4f5df23SVikas Chaudhary off0[1] = 0; 1393f4f5df23SVikas Chaudhary sz[1] = size - sz[0]; 1394f4f5df23SVikas Chaudhary 1395f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1396f4f5df23SVikas Chaudhary temp = off8 + (i << shift_amount); 1397f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1398f4f5df23SVikas Chaudhary temp = 0; 1399f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1400f4f5df23SVikas Chaudhary temp = MIU_TA_CTL_ENABLE; 1401f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1402c38fa3abSVikas Chaudhary temp = MIU_TA_CTL_START_ENABLE; 1403f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1404f4f5df23SVikas Chaudhary 1405f4f5df23SVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1406f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1407f4f5df23SVikas Chaudhary if ((temp & MIU_TA_CTL_BUSY) == 0) 1408f4f5df23SVikas Chaudhary break; 1409f4f5df23SVikas Chaudhary } 1410f4f5df23SVikas Chaudhary 1411f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1412068237c8STej Parkash printk_ratelimited(KERN_ERR 1413068237c8STej Parkash "%s: failed to read through agent\n", 1414068237c8STej Parkash __func__); 1415f4f5df23SVikas Chaudhary break; 1416f4f5df23SVikas Chaudhary } 1417f4f5df23SVikas Chaudhary 1418f4f5df23SVikas Chaudhary start = off0[i] >> 2; 1419f4f5df23SVikas Chaudhary end = (off0[i] + sz[i] - 1) >> 2; 1420f4f5df23SVikas Chaudhary for (k = start; k <= end; k++) { 1421f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, 1422f4f5df23SVikas Chaudhary mem_crb + MIU_TEST_AGT_RDDATA(k)); 1423f4f5df23SVikas Chaudhary word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1424f4f5df23SVikas Chaudhary } 1425f4f5df23SVikas Chaudhary } 1426f4f5df23SVikas Chaudhary 1427f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) 1428f4f5df23SVikas Chaudhary return -1; 1429f4f5df23SVikas Chaudhary 1430f4f5df23SVikas Chaudhary if ((off0[0] & 7) == 0) { 1431f4f5df23SVikas Chaudhary val = word[0]; 1432f4f5df23SVikas Chaudhary } else { 1433f4f5df23SVikas Chaudhary val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1434f4f5df23SVikas Chaudhary ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1435f4f5df23SVikas Chaudhary } 1436f4f5df23SVikas Chaudhary 1437f4f5df23SVikas Chaudhary switch (size) { 1438f4f5df23SVikas Chaudhary case 1: 1439f4f5df23SVikas Chaudhary *(uint8_t *)data = val; 1440f4f5df23SVikas Chaudhary break; 1441f4f5df23SVikas Chaudhary case 2: 1442f4f5df23SVikas Chaudhary *(uint16_t *)data = val; 1443f4f5df23SVikas Chaudhary break; 1444f4f5df23SVikas Chaudhary case 4: 1445f4f5df23SVikas Chaudhary *(uint32_t *)data = val; 1446f4f5df23SVikas Chaudhary break; 1447f4f5df23SVikas Chaudhary case 8: 1448f4f5df23SVikas Chaudhary *(uint64_t *)data = val; 1449f4f5df23SVikas Chaudhary break; 1450f4f5df23SVikas Chaudhary } 1451f4f5df23SVikas Chaudhary return 0; 1452f4f5df23SVikas Chaudhary } 1453f4f5df23SVikas Chaudhary 1454f4f5df23SVikas Chaudhary int 1455f8086f4fSVikas Chaudhary qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha, 1456f4f5df23SVikas Chaudhary u64 off, void *data, int size) 1457f4f5df23SVikas Chaudhary { 1458f4f5df23SVikas Chaudhary int i, j, ret = 0, loop, sz[2], off0; 1459f4f5df23SVikas Chaudhary int scale, shift_amount, startword; 1460f4f5df23SVikas Chaudhary uint32_t temp; 1461f4f5df23SVikas Chaudhary uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1462f4f5df23SVikas Chaudhary 1463f4f5df23SVikas Chaudhary /* 1464f4f5df23SVikas Chaudhary * If not MN, go check for MS or invalid. 1465f4f5df23SVikas Chaudhary */ 1466de8c72daSVikas Chaudhary if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1467f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_QDR_NET; 1468f4f5df23SVikas Chaudhary else { 1469f4f5df23SVikas Chaudhary mem_crb = QLA82XX_CRB_DDR_NET; 1470f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0) 1471f8086f4fSVikas Chaudhary return qla4_82xx_pci_mem_write_direct(ha, 1472f4f5df23SVikas Chaudhary off, data, size); 1473f4f5df23SVikas Chaudhary } 1474f4f5df23SVikas Chaudhary 1475f4f5df23SVikas Chaudhary off0 = off & 0x7; 1476f4f5df23SVikas Chaudhary sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1477f4f5df23SVikas Chaudhary sz[1] = size - sz[0]; 1478f4f5df23SVikas Chaudhary 1479f4f5df23SVikas Chaudhary off8 = off & 0xfffffff0; 1480f4f5df23SVikas Chaudhary loop = (((off & 0xf) + size - 1) >> 4) + 1; 1481f4f5df23SVikas Chaudhary shift_amount = 4; 1482f4f5df23SVikas Chaudhary scale = 2; 1483f4f5df23SVikas Chaudhary startword = (off & 0xf)/8; 1484f4f5df23SVikas Chaudhary 1485f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1486f8086f4fSVikas Chaudhary if (qla4_82xx_pci_mem_read_2M(ha, off8 + 1487f4f5df23SVikas Chaudhary (i << shift_amount), &word[i * scale], 8)) 1488f4f5df23SVikas Chaudhary return -1; 1489f4f5df23SVikas Chaudhary } 1490f4f5df23SVikas Chaudhary 1491f4f5df23SVikas Chaudhary switch (size) { 1492f4f5df23SVikas Chaudhary case 1: 1493f4f5df23SVikas Chaudhary tmpw = *((uint8_t *)data); 1494f4f5df23SVikas Chaudhary break; 1495f4f5df23SVikas Chaudhary case 2: 1496f4f5df23SVikas Chaudhary tmpw = *((uint16_t *)data); 1497f4f5df23SVikas Chaudhary break; 1498f4f5df23SVikas Chaudhary case 4: 1499f4f5df23SVikas Chaudhary tmpw = *((uint32_t *)data); 1500f4f5df23SVikas Chaudhary break; 1501f4f5df23SVikas Chaudhary case 8: 1502f4f5df23SVikas Chaudhary default: 1503f4f5df23SVikas Chaudhary tmpw = *((uint64_t *)data); 1504f4f5df23SVikas Chaudhary break; 1505f4f5df23SVikas Chaudhary } 1506f4f5df23SVikas Chaudhary 1507f4f5df23SVikas Chaudhary if (sz[0] == 8) 1508f4f5df23SVikas Chaudhary word[startword] = tmpw; 1509f4f5df23SVikas Chaudhary else { 1510f4f5df23SVikas Chaudhary word[startword] &= 1511f4f5df23SVikas Chaudhary ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1512f4f5df23SVikas Chaudhary word[startword] |= tmpw << (off0 * 8); 1513f4f5df23SVikas Chaudhary } 1514f4f5df23SVikas Chaudhary 1515f4f5df23SVikas Chaudhary if (sz[1] != 0) { 1516f4f5df23SVikas Chaudhary word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1517f4f5df23SVikas Chaudhary word[startword+1] |= tmpw >> (sz[0] * 8); 1518f4f5df23SVikas Chaudhary } 1519f4f5df23SVikas Chaudhary 1520f4f5df23SVikas Chaudhary for (i = 0; i < loop; i++) { 1521f4f5df23SVikas Chaudhary temp = off8 + (i << shift_amount); 1522f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1523f4f5df23SVikas Chaudhary temp = 0; 1524f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1525f4f5df23SVikas Chaudhary temp = word[i * scale] & 0xffffffff; 1526f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1527f4f5df23SVikas Chaudhary temp = (word[i * scale] >> 32) & 0xffffffff; 1528f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1529f4f5df23SVikas Chaudhary temp = word[i*scale + 1] & 0xffffffff; 1530f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, 1531f4f5df23SVikas Chaudhary temp); 1532f4f5df23SVikas Chaudhary temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1533f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, 1534f4f5df23SVikas Chaudhary temp); 1535f4f5df23SVikas Chaudhary 1536c38fa3abSVikas Chaudhary temp = MIU_TA_CTL_WRITE_ENABLE; 1537f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1538c38fa3abSVikas Chaudhary temp = MIU_TA_CTL_WRITE_START; 1539f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1540f4f5df23SVikas Chaudhary 1541f4f5df23SVikas Chaudhary for (j = 0; j < MAX_CTL_CHECK; j++) { 1542f8086f4fSVikas Chaudhary temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1543f4f5df23SVikas Chaudhary if ((temp & MIU_TA_CTL_BUSY) == 0) 1544f4f5df23SVikas Chaudhary break; 1545f4f5df23SVikas Chaudhary } 1546f4f5df23SVikas Chaudhary 1547f4f5df23SVikas Chaudhary if (j >= MAX_CTL_CHECK) { 1548f4f5df23SVikas Chaudhary if (printk_ratelimit()) 1549f4f5df23SVikas Chaudhary ql4_printk(KERN_ERR, ha, 1550068237c8STej Parkash "%s: failed to read through agent\n", 1551068237c8STej Parkash __func__); 1552f4f5df23SVikas Chaudhary ret = -1; 1553f4f5df23SVikas Chaudhary break; 1554f4f5df23SVikas Chaudhary } 1555f4f5df23SVikas Chaudhary } 1556f4f5df23SVikas Chaudhary 1557f4f5df23SVikas Chaudhary return ret; 1558f4f5df23SVikas Chaudhary } 1559f4f5df23SVikas Chaudhary 1560f8086f4fSVikas Chaudhary static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) 1561f4f5df23SVikas Chaudhary { 1562f4f5df23SVikas Chaudhary u32 val = 0; 1563f4f5df23SVikas Chaudhary int retries = 60; 1564f4f5df23SVikas Chaudhary 1565f4f5df23SVikas Chaudhary if (!pegtune_val) { 1566f4f5df23SVikas Chaudhary do { 1567f8086f4fSVikas Chaudhary val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE); 1568f4f5df23SVikas Chaudhary if ((val == PHAN_INITIALIZE_COMPLETE) || 1569f4f5df23SVikas Chaudhary (val == PHAN_INITIALIZE_ACK)) 1570f4f5df23SVikas Chaudhary return 0; 1571f4f5df23SVikas Chaudhary set_current_state(TASK_UNINTERRUPTIBLE); 1572f4f5df23SVikas Chaudhary schedule_timeout(500); 1573f4f5df23SVikas Chaudhary 1574f4f5df23SVikas Chaudhary } while (--retries); 1575f4f5df23SVikas Chaudhary 1576f4f5df23SVikas Chaudhary if (!retries) { 1577f8086f4fSVikas Chaudhary pegtune_val = qla4_82xx_rd_32(ha, 1578f4f5df23SVikas Chaudhary QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1579f4f5df23SVikas Chaudhary printk(KERN_WARNING "%s: init failed, " 1580f4f5df23SVikas Chaudhary "pegtune_val = %x\n", __func__, pegtune_val); 1581f4f5df23SVikas Chaudhary return -1; 1582f4f5df23SVikas Chaudhary } 1583f4f5df23SVikas Chaudhary } 1584f4f5df23SVikas Chaudhary return 0; 1585f4f5df23SVikas Chaudhary } 1586f4f5df23SVikas Chaudhary 1587f8086f4fSVikas Chaudhary static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha) 1588f4f5df23SVikas Chaudhary { 1589f4f5df23SVikas Chaudhary uint32_t state = 0; 1590f4f5df23SVikas Chaudhary int loops = 0; 1591f4f5df23SVikas Chaudhary 1592f4f5df23SVikas Chaudhary /* Window 1 call */ 1593f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1594f8086f4fSVikas Chaudhary state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); 1595f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1596f4f5df23SVikas Chaudhary 1597f4f5df23SVikas Chaudhary while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { 1598f4f5df23SVikas Chaudhary udelay(100); 1599f4f5df23SVikas Chaudhary /* Window 1 call */ 1600f4f5df23SVikas Chaudhary read_lock(&ha->hw_lock); 1601f8086f4fSVikas Chaudhary state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE); 1602f4f5df23SVikas Chaudhary read_unlock(&ha->hw_lock); 1603f4f5df23SVikas Chaudhary 1604f4f5df23SVikas Chaudhary loops++; 1605f4f5df23SVikas Chaudhary } 1606f4f5df23SVikas Chaudhary 1607f4f5df23SVikas Chaudhary if (loops >= 30000) { 1608f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 1609f4f5df23SVikas Chaudhary "Receive Peg initialization not complete: 0x%x.\n", state)); 1610f4f5df23SVikas Chaudhary return QLA_ERROR; 1611f4f5df23SVikas Chaudhary } 1612f4f5df23SVikas Chaudhary 1613f4f5df23SVikas Chaudhary return QLA_SUCCESS; 1614f4f5df23SVikas Chaudhary } 1615f4f5df23SVikas Chaudhary 1616626115cdSAndrew Morton void 1617f4f5df23SVikas Chaudhary qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) 1618f4f5df23SVikas Chaudhary { 1619f4f5df23SVikas Chaudhary uint32_t drv_active; 1620f4f5df23SVikas Chaudhary 162133693c7aSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 16226e7b4292SVikas Chaudhary 16236e7b4292SVikas Chaudhary /* 1624b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 16256e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 16266e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 16276e7b4292SVikas Chaudhary */ 1628b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 16296e7b4292SVikas Chaudhary drv_active |= (1 << ha->func_num); 16306e7b4292SVikas Chaudhary else 1631f4f5df23SVikas Chaudhary drv_active |= (1 << (ha->func_num * 4)); 16326e7b4292SVikas Chaudhary 1633068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1634068237c8STej Parkash __func__, ha->host_no, drv_active); 163533693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); 1636f4f5df23SVikas Chaudhary } 1637f4f5df23SVikas Chaudhary 1638f4f5df23SVikas Chaudhary void 1639f4f5df23SVikas Chaudhary qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) 1640f4f5df23SVikas Chaudhary { 1641f4f5df23SVikas Chaudhary uint32_t drv_active; 1642f4f5df23SVikas Chaudhary 164333693c7aSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 16446e7b4292SVikas Chaudhary 16456e7b4292SVikas Chaudhary /* 1646b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 16476e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 16486e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 16496e7b4292SVikas Chaudhary */ 1650b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 16516e7b4292SVikas Chaudhary drv_active &= ~(1 << (ha->func_num)); 16526e7b4292SVikas Chaudhary else 1653f4f5df23SVikas Chaudhary drv_active &= ~(1 << (ha->func_num * 4)); 16546e7b4292SVikas Chaudhary 1655068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n", 1656068237c8STej Parkash __func__, ha->host_no, drv_active); 165733693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, drv_active); 1658f4f5df23SVikas Chaudhary } 1659f4f5df23SVikas Chaudhary 166033693c7aSVikas Chaudhary inline int qla4_8xxx_need_reset(struct scsi_qla_host *ha) 1661f4f5df23SVikas Chaudhary { 16622232be0dSLalit Chandivade uint32_t drv_state, drv_active; 1663f4f5df23SVikas Chaudhary int rval; 1664f4f5df23SVikas Chaudhary 166533693c7aSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 166633693c7aSVikas Chaudhary drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 16676e7b4292SVikas Chaudhary 16686e7b4292SVikas Chaudhary /* 1669b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 16706e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 16716e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 16726e7b4292SVikas Chaudhary */ 1673b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 16746e7b4292SVikas Chaudhary rval = drv_state & (1 << ha->func_num); 16756e7b4292SVikas Chaudhary else 1676f4f5df23SVikas Chaudhary rval = drv_state & (1 << (ha->func_num * 4)); 16776e7b4292SVikas Chaudhary 16782232be0dSLalit Chandivade if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 16792232be0dSLalit Chandivade rval = 1; 16802232be0dSLalit Chandivade 1681f4f5df23SVikas Chaudhary return rval; 1682f4f5df23SVikas Chaudhary } 1683f4f5df23SVikas Chaudhary 16846e7b4292SVikas Chaudhary void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) 1685f4f5df23SVikas Chaudhary { 1686f4f5df23SVikas Chaudhary uint32_t drv_state; 1687f4f5df23SVikas Chaudhary 168833693c7aSVikas Chaudhary drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 16896e7b4292SVikas Chaudhary 16906e7b4292SVikas Chaudhary /* 1691b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 16926e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 16936e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 16946e7b4292SVikas Chaudhary */ 1695b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 16966e7b4292SVikas Chaudhary drv_state |= (1 << ha->func_num); 16976e7b4292SVikas Chaudhary else 1698f4f5df23SVikas Chaudhary drv_state |= (1 << (ha->func_num * 4)); 16996e7b4292SVikas Chaudhary 1700068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1701068237c8STej Parkash __func__, ha->host_no, drv_state); 170233693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); 1703f4f5df23SVikas Chaudhary } 1704f4f5df23SVikas Chaudhary 17056e7b4292SVikas Chaudhary void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) 1706f4f5df23SVikas Chaudhary { 1707f4f5df23SVikas Chaudhary uint32_t drv_state; 1708f4f5df23SVikas Chaudhary 170933693c7aSVikas Chaudhary drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 17106e7b4292SVikas Chaudhary 17116e7b4292SVikas Chaudhary /* 1712b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 17136e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 17146e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function 17156e7b4292SVikas Chaudhary */ 1716b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 17176e7b4292SVikas Chaudhary drv_state &= ~(1 << ha->func_num); 17186e7b4292SVikas Chaudhary else 1719f4f5df23SVikas Chaudhary drv_state &= ~(1 << (ha->func_num * 4)); 17206e7b4292SVikas Chaudhary 1721068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n", 1722068237c8STej Parkash __func__, ha->host_no, drv_state); 172333693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, drv_state); 1724f4f5df23SVikas Chaudhary } 1725f4f5df23SVikas Chaudhary 1726f4f5df23SVikas Chaudhary static inline void 1727f4f5df23SVikas Chaudhary qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) 1728f4f5df23SVikas Chaudhary { 1729f4f5df23SVikas Chaudhary uint32_t qsnt_state; 1730f4f5df23SVikas Chaudhary 173133693c7aSVikas Chaudhary qsnt_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); 17326e7b4292SVikas Chaudhary 17336e7b4292SVikas Chaudhary /* 1734b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, drv_active register has 1 bit per function, 17356e7b4292SVikas Chaudhary * shift 1 by func_num to set a bit for the function. 17366e7b4292SVikas Chaudhary * For ISP8022, drv_active has 4 bits per function. 17376e7b4292SVikas Chaudhary */ 1738b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 17396e7b4292SVikas Chaudhary qsnt_state |= (1 << ha->func_num); 17406e7b4292SVikas Chaudhary else 1741f4f5df23SVikas Chaudhary qsnt_state |= (2 << (ha->func_num * 4)); 17426e7b4292SVikas Chaudhary 174333693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_STATE, qsnt_state); 1744f4f5df23SVikas Chaudhary } 1745f4f5df23SVikas Chaudhary 1746f4f5df23SVikas Chaudhary 1747f4f5df23SVikas Chaudhary static int 1748f8086f4fSVikas Chaudhary qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) 1749f4f5df23SVikas Chaudhary { 1750f4f5df23SVikas Chaudhary uint16_t lnk; 1751f4f5df23SVikas Chaudhary 1752f4f5df23SVikas Chaudhary /* scrub dma mask expansion register */ 1753f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 1754f4f5df23SVikas Chaudhary 1755f4f5df23SVikas Chaudhary /* Overwrite stale initialization register values */ 1756f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1757f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); 1758f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 1759f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 1760f4f5df23SVikas Chaudhary 1761f8086f4fSVikas Chaudhary if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) { 1762f4f5df23SVikas Chaudhary printk("%s: Error trying to start fw!\n", __func__); 1763f4f5df23SVikas Chaudhary return QLA_ERROR; 1764f4f5df23SVikas Chaudhary } 1765f4f5df23SVikas Chaudhary 1766f4f5df23SVikas Chaudhary /* Handshake with the card before we register the devices. */ 1767f8086f4fSVikas Chaudhary if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { 1768f4f5df23SVikas Chaudhary printk("%s: Error during card handshake!\n", __func__); 1769f4f5df23SVikas Chaudhary return QLA_ERROR; 1770f4f5df23SVikas Chaudhary } 1771f4f5df23SVikas Chaudhary 1772f4f5df23SVikas Chaudhary /* Negotiated Link width */ 17735548bfd0SJiang Liu pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk); 1774f4f5df23SVikas Chaudhary ha->link_width = (lnk >> 4) & 0x3f; 1775f4f5df23SVikas Chaudhary 1776f4f5df23SVikas Chaudhary /* Synchronize with Receive peg */ 1777f8086f4fSVikas Chaudhary return qla4_82xx_rcvpeg_ready(ha); 1778f4f5df23SVikas Chaudhary } 1779f4f5df23SVikas Chaudhary 178033693c7aSVikas Chaudhary int qla4_82xx_try_start_fw(struct scsi_qla_host *ha) 1781f4f5df23SVikas Chaudhary { 1782f4f5df23SVikas Chaudhary int rval = QLA_ERROR; 1783f4f5df23SVikas Chaudhary 1784f4f5df23SVikas Chaudhary /* 1785f4f5df23SVikas Chaudhary * FW Load priority: 1786f4f5df23SVikas Chaudhary * 1) Operational firmware residing in flash. 1787f4f5df23SVikas Chaudhary * 2) Fail 1788f4f5df23SVikas Chaudhary */ 1789f4f5df23SVikas Chaudhary 1790f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1791f4f5df23SVikas Chaudhary "FW: Retrieving flash offsets from FLT/FDT ...\n"); 1792f4f5df23SVikas Chaudhary rval = qla4_8xxx_get_flash_info(ha); 1793f4f5df23SVikas Chaudhary if (rval != QLA_SUCCESS) 1794f4f5df23SVikas Chaudhary return rval; 1795f4f5df23SVikas Chaudhary 1796f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 1797f4f5df23SVikas Chaudhary "FW: Attempting to load firmware from flash...\n"); 1798f8086f4fSVikas Chaudhary rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw); 1799f4f5df23SVikas Chaudhary 1800f581a3f7SVikas Chaudhary if (rval != QLA_SUCCESS) { 1801f581a3f7SVikas Chaudhary ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" 1802f581a3f7SVikas Chaudhary " FAILED...\n"); 1803f581a3f7SVikas Chaudhary return rval; 1804f581a3f7SVikas Chaudhary } 1805f4f5df23SVikas Chaudhary 1806f4f5df23SVikas Chaudhary return rval; 1807f4f5df23SVikas Chaudhary } 1808f4f5df23SVikas Chaudhary 180933693c7aSVikas Chaudhary void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha) 1810b25ee66fSShyam Sundar { 1811f8086f4fSVikas Chaudhary if (qla4_82xx_rom_lock(ha)) { 1812b25ee66fSShyam Sundar /* Someone else is holding the lock. */ 1813b25ee66fSShyam Sundar dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); 1814b25ee66fSShyam Sundar } 1815b25ee66fSShyam Sundar 1816b25ee66fSShyam Sundar /* 1817b25ee66fSShyam Sundar * Either we got the lock, or someone 1818b25ee66fSShyam Sundar * else died while holding it. 1819b25ee66fSShyam Sundar * In either case, unlock. 1820b25ee66fSShyam Sundar */ 1821f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 1822b25ee66fSShyam Sundar } 1823b25ee66fSShyam Sundar 1824b1829789STej Parkash static uint32_t ql4_84xx_poll_wait_for_ready(struct scsi_qla_host *ha, 1825b1829789STej Parkash uint32_t addr1, uint32_t mask) 1826b1829789STej Parkash { 1827b1829789STej Parkash unsigned long timeout; 1828b1829789STej Parkash uint32_t rval = QLA_SUCCESS; 1829b1829789STej Parkash uint32_t temp; 1830b1829789STej Parkash 1831b1829789STej Parkash timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); 1832b1829789STej Parkash do { 1833b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 1834b1829789STej Parkash if ((temp & mask) != 0) 1835b1829789STej Parkash break; 1836b1829789STej Parkash 1837b1829789STej Parkash if (time_after_eq(jiffies, timeout)) { 1838b1829789STej Parkash ql4_printk(KERN_INFO, ha, "Error in processing rdmdio entry\n"); 1839b1829789STej Parkash return QLA_ERROR; 1840b1829789STej Parkash } 1841b1829789STej Parkash } while (1); 1842b1829789STej Parkash 1843b1829789STej Parkash return rval; 1844b1829789STej Parkash } 1845b1829789STej Parkash 1846b1829789STej Parkash uint32_t ql4_84xx_ipmdio_rd_reg(struct scsi_qla_host *ha, uint32_t addr1, 1847b1829789STej Parkash uint32_t addr3, uint32_t mask, uint32_t addr, 1848b1829789STej Parkash uint32_t *data_ptr) 1849b1829789STej Parkash { 1850b1829789STej Parkash int rval = QLA_SUCCESS; 1851b1829789STej Parkash uint32_t temp; 1852b1829789STej Parkash uint32_t data; 1853b1829789STej Parkash 1854b1829789STej Parkash rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1855b1829789STej Parkash if (rval) 1856b1829789STej Parkash goto exit_ipmdio_rd_reg; 1857b1829789STej Parkash 1858b1829789STej Parkash temp = (0x40000000 | addr); 1859b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, temp); 1860b1829789STej Parkash 1861b1829789STej Parkash rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1862b1829789STej Parkash if (rval) 1863b1829789STej Parkash goto exit_ipmdio_rd_reg; 1864b1829789STej Parkash 1865b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr3, &data); 1866b1829789STej Parkash *data_ptr = data; 1867b1829789STej Parkash 1868b1829789STej Parkash exit_ipmdio_rd_reg: 1869b1829789STej Parkash return rval; 1870b1829789STej Parkash } 1871b1829789STej Parkash 1872b1829789STej Parkash 1873b1829789STej Parkash static uint32_t ql4_84xx_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *ha, 1874b1829789STej Parkash uint32_t addr1, 1875b1829789STej Parkash uint32_t addr2, 1876b1829789STej Parkash uint32_t addr3, 1877b1829789STej Parkash uint32_t mask) 1878b1829789STej Parkash { 1879b1829789STej Parkash unsigned long timeout; 1880b1829789STej Parkash uint32_t temp; 1881b1829789STej Parkash uint32_t rval = QLA_SUCCESS; 1882b1829789STej Parkash 1883b1829789STej Parkash timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); 1884b1829789STej Parkash do { 1885b1829789STej Parkash ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp); 1886b1829789STej Parkash if ((temp & 0x1) != 1) 1887b1829789STej Parkash break; 1888b1829789STej Parkash if (time_after_eq(jiffies, timeout)) { 1889b1829789STej Parkash ql4_printk(KERN_INFO, ha, "Error in processing mdiobus idle\n"); 1890b1829789STej Parkash return QLA_ERROR; 1891b1829789STej Parkash } 1892b1829789STej Parkash } while (1); 1893b1829789STej Parkash 1894b1829789STej Parkash return rval; 1895b1829789STej Parkash } 1896b1829789STej Parkash 1897b1829789STej Parkash static int ql4_84xx_ipmdio_wr_reg(struct scsi_qla_host *ha, 1898b1829789STej Parkash uint32_t addr1, uint32_t addr3, 1899b1829789STej Parkash uint32_t mask, uint32_t addr, 1900b1829789STej Parkash uint32_t value) 1901b1829789STej Parkash { 1902b1829789STej Parkash int rval = QLA_SUCCESS; 1903b1829789STej Parkash 1904b1829789STej Parkash rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1905b1829789STej Parkash if (rval) 1906b1829789STej Parkash goto exit_ipmdio_wr_reg; 1907b1829789STej Parkash 1908b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr3, value); 1909b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, addr); 1910b1829789STej Parkash 1911b1829789STej Parkash rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); 1912b1829789STej Parkash if (rval) 1913b1829789STej Parkash goto exit_ipmdio_wr_reg; 1914b1829789STej Parkash 1915b1829789STej Parkash exit_ipmdio_wr_reg: 1916b1829789STej Parkash return rval; 1917b1829789STej Parkash } 1918b1829789STej Parkash 1919068237c8STej Parkash static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha, 19207664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 1921068237c8STej Parkash uint32_t **d_ptr) 1922068237c8STej Parkash { 1923068237c8STej Parkash uint32_t r_addr, r_stride, loop_cnt, i, r_value; 19247664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_crb *crb_hdr; 1925068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 1926068237c8STej Parkash 1927068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 19287664a1fdSVikas Chaudhary crb_hdr = (struct qla8xxx_minidump_entry_crb *)entry_hdr; 1929068237c8STej Parkash r_addr = crb_hdr->addr; 1930068237c8STej Parkash r_stride = crb_hdr->crb_strd.addr_stride; 1931068237c8STej Parkash loop_cnt = crb_hdr->op_count; 1932068237c8STej Parkash 1933068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 193433693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 1935068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_addr); 1936068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 1937068237c8STej Parkash r_addr += r_stride; 1938068237c8STej Parkash } 1939068237c8STej Parkash *d_ptr = data_ptr; 1940068237c8STej Parkash } 1941068237c8STej Parkash 194241f79bdeSSantosh Vernekar static int qla4_83xx_check_dma_engine_state(struct scsi_qla_host *ha) 194341f79bdeSSantosh Vernekar { 194441f79bdeSSantosh Vernekar int rval = QLA_SUCCESS; 194541f79bdeSSantosh Vernekar uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 194641f79bdeSSantosh Vernekar uint64_t dma_base_addr = 0; 194741f79bdeSSantosh Vernekar struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL; 194841f79bdeSSantosh Vernekar 194941f79bdeSSantosh Vernekar tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 195041f79bdeSSantosh Vernekar ha->fw_dump_tmplt_hdr; 195141f79bdeSSantosh Vernekar dma_eng_num = 195241f79bdeSSantosh Vernekar tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX]; 195341f79bdeSSantosh Vernekar dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS + 195441f79bdeSSantosh Vernekar (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET); 195541f79bdeSSantosh Vernekar 195641f79bdeSSantosh Vernekar /* Read the pex-dma's command-status-and-control register. */ 195741f79bdeSSantosh Vernekar rval = ha->isp_ops->rd_reg_indirect(ha, 195841f79bdeSSantosh Vernekar (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL), 195941f79bdeSSantosh Vernekar &cmd_sts_and_cntrl); 196041f79bdeSSantosh Vernekar 196141f79bdeSSantosh Vernekar if (rval) 196241f79bdeSSantosh Vernekar return QLA_ERROR; 196341f79bdeSSantosh Vernekar 196441f79bdeSSantosh Vernekar /* Check if requested pex-dma engine is available. */ 196541f79bdeSSantosh Vernekar if (cmd_sts_and_cntrl & BIT_31) 196641f79bdeSSantosh Vernekar return QLA_SUCCESS; 196741f79bdeSSantosh Vernekar else 196841f79bdeSSantosh Vernekar return QLA_ERROR; 196941f79bdeSSantosh Vernekar } 197041f79bdeSSantosh Vernekar 197141f79bdeSSantosh Vernekar static int qla4_83xx_start_pex_dma(struct scsi_qla_host *ha, 197241f79bdeSSantosh Vernekar struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr) 197341f79bdeSSantosh Vernekar { 197441f79bdeSSantosh Vernekar int rval = QLA_SUCCESS, wait = 0; 197541f79bdeSSantosh Vernekar uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 197641f79bdeSSantosh Vernekar uint64_t dma_base_addr = 0; 197741f79bdeSSantosh Vernekar struct qla4_8xxx_minidump_template_hdr *tmplt_hdr = NULL; 197841f79bdeSSantosh Vernekar 197941f79bdeSSantosh Vernekar tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 198041f79bdeSSantosh Vernekar ha->fw_dump_tmplt_hdr; 198141f79bdeSSantosh Vernekar dma_eng_num = 198241f79bdeSSantosh Vernekar tmplt_hdr->saved_state_array[QLA83XX_PEX_DMA_ENGINE_INDEX]; 198341f79bdeSSantosh Vernekar dma_base_addr = QLA83XX_PEX_DMA_BASE_ADDRESS + 198441f79bdeSSantosh Vernekar (dma_eng_num * QLA83XX_PEX_DMA_NUM_OFFSET); 198541f79bdeSSantosh Vernekar 198641f79bdeSSantosh Vernekar rval = ha->isp_ops->wr_reg_indirect(ha, 198741f79bdeSSantosh Vernekar dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_LOW, 198841f79bdeSSantosh Vernekar m_hdr->desc_card_addr); 198941f79bdeSSantosh Vernekar if (rval) 199041f79bdeSSantosh Vernekar goto error_exit; 199141f79bdeSSantosh Vernekar 199241f79bdeSSantosh Vernekar rval = ha->isp_ops->wr_reg_indirect(ha, 199341f79bdeSSantosh Vernekar dma_base_addr + QLA83XX_PEX_DMA_CMD_ADDR_HIGH, 0); 199441f79bdeSSantosh Vernekar if (rval) 199541f79bdeSSantosh Vernekar goto error_exit; 199641f79bdeSSantosh Vernekar 199741f79bdeSSantosh Vernekar rval = ha->isp_ops->wr_reg_indirect(ha, 199841f79bdeSSantosh Vernekar dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL, 199941f79bdeSSantosh Vernekar m_hdr->start_dma_cmd); 200041f79bdeSSantosh Vernekar if (rval) 200141f79bdeSSantosh Vernekar goto error_exit; 200241f79bdeSSantosh Vernekar 200341f79bdeSSantosh Vernekar /* Wait for dma operation to complete. */ 200441f79bdeSSantosh Vernekar for (wait = 0; wait < QLA83XX_PEX_DMA_MAX_WAIT; wait++) { 200541f79bdeSSantosh Vernekar rval = ha->isp_ops->rd_reg_indirect(ha, 200641f79bdeSSantosh Vernekar (dma_base_addr + QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL), 200741f79bdeSSantosh Vernekar &cmd_sts_and_cntrl); 200841f79bdeSSantosh Vernekar if (rval) 200941f79bdeSSantosh Vernekar goto error_exit; 201041f79bdeSSantosh Vernekar 201141f79bdeSSantosh Vernekar if ((cmd_sts_and_cntrl & BIT_1) == 0) 201241f79bdeSSantosh Vernekar break; 201341f79bdeSSantosh Vernekar else 201441f79bdeSSantosh Vernekar udelay(10); 201541f79bdeSSantosh Vernekar } 201641f79bdeSSantosh Vernekar 201741f79bdeSSantosh Vernekar /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */ 201841f79bdeSSantosh Vernekar if (wait >= QLA83XX_PEX_DMA_MAX_WAIT) { 201941f79bdeSSantosh Vernekar rval = QLA_ERROR; 202041f79bdeSSantosh Vernekar goto error_exit; 202141f79bdeSSantosh Vernekar } 202241f79bdeSSantosh Vernekar 202341f79bdeSSantosh Vernekar error_exit: 202441f79bdeSSantosh Vernekar return rval; 202541f79bdeSSantosh Vernekar } 202641f79bdeSSantosh Vernekar 20273c3cab17STej Parkash static int qla4_8xxx_minidump_pex_dma_read(struct scsi_qla_host *ha, 202841f79bdeSSantosh Vernekar struct qla8xxx_minidump_entry_hdr *entry_hdr, 202941f79bdeSSantosh Vernekar uint32_t **d_ptr) 203041f79bdeSSantosh Vernekar { 203141f79bdeSSantosh Vernekar int rval = QLA_SUCCESS; 203241f79bdeSSantosh Vernekar struct qla4_83xx_minidump_entry_rdmem_pex_dma *m_hdr = NULL; 203341f79bdeSSantosh Vernekar uint32_t size, read_size; 203441f79bdeSSantosh Vernekar uint8_t *data_ptr = (uint8_t *)*d_ptr; 203541f79bdeSSantosh Vernekar void *rdmem_buffer = NULL; 203641f79bdeSSantosh Vernekar dma_addr_t rdmem_dma; 203741f79bdeSSantosh Vernekar struct qla4_83xx_pex_dma_descriptor dma_desc; 203841f79bdeSSantosh Vernekar 203941f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 204041f79bdeSSantosh Vernekar 204141f79bdeSSantosh Vernekar rval = qla4_83xx_check_dma_engine_state(ha); 204241f79bdeSSantosh Vernekar if (rval != QLA_SUCCESS) { 204341f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 204441f79bdeSSantosh Vernekar "%s: DMA engine not available. Fallback to rdmem-read.\n", 204541f79bdeSSantosh Vernekar __func__)); 204641f79bdeSSantosh Vernekar return QLA_ERROR; 204741f79bdeSSantosh Vernekar } 204841f79bdeSSantosh Vernekar 204941f79bdeSSantosh Vernekar m_hdr = (struct qla4_83xx_minidump_entry_rdmem_pex_dma *)entry_hdr; 205041f79bdeSSantosh Vernekar rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, 205141f79bdeSSantosh Vernekar QLA83XX_PEX_DMA_READ_SIZE, 205241f79bdeSSantosh Vernekar &rdmem_dma, GFP_KERNEL); 205341f79bdeSSantosh Vernekar if (!rdmem_buffer) { 205441f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 205541f79bdeSSantosh Vernekar "%s: Unable to allocate rdmem dma buffer\n", 205641f79bdeSSantosh Vernekar __func__)); 205741f79bdeSSantosh Vernekar return QLA_ERROR; 205841f79bdeSSantosh Vernekar } 205941f79bdeSSantosh Vernekar 206041f79bdeSSantosh Vernekar /* Prepare pex-dma descriptor to be written to MS memory. */ 206141f79bdeSSantosh Vernekar /* dma-desc-cmd layout: 206241f79bdeSSantosh Vernekar * 0-3: dma-desc-cmd 0-3 206341f79bdeSSantosh Vernekar * 4-7: pcid function number 206441f79bdeSSantosh Vernekar * 8-15: dma-desc-cmd 8-15 206541f79bdeSSantosh Vernekar */ 206641f79bdeSSantosh Vernekar dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); 206741f79bdeSSantosh Vernekar dma_desc.cmd.dma_desc_cmd |= ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); 206841f79bdeSSantosh Vernekar dma_desc.dma_bus_addr = rdmem_dma; 206941f79bdeSSantosh Vernekar 207041f79bdeSSantosh Vernekar size = 0; 207141f79bdeSSantosh Vernekar read_size = 0; 207241f79bdeSSantosh Vernekar /* 207341f79bdeSSantosh Vernekar * Perform rdmem operation using pex-dma. 207441f79bdeSSantosh Vernekar * Prepare dma in chunks of QLA83XX_PEX_DMA_READ_SIZE. 207541f79bdeSSantosh Vernekar */ 207641f79bdeSSantosh Vernekar while (read_size < m_hdr->read_data_size) { 207741f79bdeSSantosh Vernekar if (m_hdr->read_data_size - read_size >= 207841f79bdeSSantosh Vernekar QLA83XX_PEX_DMA_READ_SIZE) 207941f79bdeSSantosh Vernekar size = QLA83XX_PEX_DMA_READ_SIZE; 208041f79bdeSSantosh Vernekar else { 208141f79bdeSSantosh Vernekar size = (m_hdr->read_data_size - read_size); 208241f79bdeSSantosh Vernekar 208341f79bdeSSantosh Vernekar if (rdmem_buffer) 208441f79bdeSSantosh Vernekar dma_free_coherent(&ha->pdev->dev, 208541f79bdeSSantosh Vernekar QLA83XX_PEX_DMA_READ_SIZE, 208641f79bdeSSantosh Vernekar rdmem_buffer, rdmem_dma); 208741f79bdeSSantosh Vernekar 208841f79bdeSSantosh Vernekar rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, size, 208941f79bdeSSantosh Vernekar &rdmem_dma, 209041f79bdeSSantosh Vernekar GFP_KERNEL); 209141f79bdeSSantosh Vernekar if (!rdmem_buffer) { 209241f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 209341f79bdeSSantosh Vernekar "%s: Unable to allocate rdmem dma buffer\n", 209441f79bdeSSantosh Vernekar __func__)); 209541f79bdeSSantosh Vernekar return QLA_ERROR; 209641f79bdeSSantosh Vernekar } 209741f79bdeSSantosh Vernekar dma_desc.dma_bus_addr = rdmem_dma; 209841f79bdeSSantosh Vernekar } 209941f79bdeSSantosh Vernekar 210041f79bdeSSantosh Vernekar dma_desc.src_addr = m_hdr->read_addr + read_size; 210141f79bdeSSantosh Vernekar dma_desc.cmd.read_data_size = size; 210241f79bdeSSantosh Vernekar 210341f79bdeSSantosh Vernekar /* Prepare: Write pex-dma descriptor to MS memory. */ 21043c3cab17STej Parkash rval = qla4_8xxx_ms_mem_write_128b(ha, 210541f79bdeSSantosh Vernekar (uint64_t)m_hdr->desc_card_addr, 210641f79bdeSSantosh Vernekar (uint32_t *)&dma_desc, 210741f79bdeSSantosh Vernekar (sizeof(struct qla4_83xx_pex_dma_descriptor)/16)); 21089c4f8d92SVikas Chaudhary if (rval != QLA_SUCCESS) { 210941f79bdeSSantosh Vernekar ql4_printk(KERN_INFO, ha, 211041f79bdeSSantosh Vernekar "%s: Error writing rdmem-dma-init to MS !!!\n", 211141f79bdeSSantosh Vernekar __func__); 211241f79bdeSSantosh Vernekar goto error_exit; 211341f79bdeSSantosh Vernekar } 211441f79bdeSSantosh Vernekar 211541f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 211641f79bdeSSantosh Vernekar "%s: Dma-desc: Instruct for rdmem dma (size 0x%x).\n", 211741f79bdeSSantosh Vernekar __func__, size)); 211841f79bdeSSantosh Vernekar /* Execute: Start pex-dma operation. */ 211941f79bdeSSantosh Vernekar rval = qla4_83xx_start_pex_dma(ha, m_hdr); 212041f79bdeSSantosh Vernekar if (rval != QLA_SUCCESS) { 212141f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, 212241f79bdeSSantosh Vernekar "scsi(%ld): start-pex-dma failed rval=0x%x\n", 212341f79bdeSSantosh Vernekar ha->host_no, rval)); 212441f79bdeSSantosh Vernekar goto error_exit; 212541f79bdeSSantosh Vernekar } 212641f79bdeSSantosh Vernekar 212741f79bdeSSantosh Vernekar memcpy(data_ptr, rdmem_buffer, size); 212841f79bdeSSantosh Vernekar data_ptr += size; 212941f79bdeSSantosh Vernekar read_size += size; 213041f79bdeSSantosh Vernekar } 213141f79bdeSSantosh Vernekar 213241f79bdeSSantosh Vernekar DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); 213341f79bdeSSantosh Vernekar 213441f79bdeSSantosh Vernekar *d_ptr = (uint32_t *)data_ptr; 213541f79bdeSSantosh Vernekar 213641f79bdeSSantosh Vernekar error_exit: 213741f79bdeSSantosh Vernekar if (rdmem_buffer) 213841f79bdeSSantosh Vernekar dma_free_coherent(&ha->pdev->dev, size, rdmem_buffer, 213941f79bdeSSantosh Vernekar rdmem_dma); 214041f79bdeSSantosh Vernekar 214141f79bdeSSantosh Vernekar return rval; 214241f79bdeSSantosh Vernekar } 214341f79bdeSSantosh Vernekar 2144068237c8STej Parkash static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha, 21457664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2146068237c8STej Parkash uint32_t **d_ptr) 2147068237c8STej Parkash { 2148068237c8STej Parkash uint32_t addr, r_addr, c_addr, t_r_addr; 2149068237c8STej Parkash uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2150068237c8STej Parkash unsigned long p_wait, w_time, p_mask; 2151068237c8STej Parkash uint32_t c_value_w, c_value_r; 21527664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_cache *cache_hdr; 2153068237c8STej Parkash int rval = QLA_ERROR; 2154068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2155068237c8STej Parkash 2156068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 21577664a1fdSVikas Chaudhary cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; 2158068237c8STej Parkash 2159068237c8STej Parkash loop_count = cache_hdr->op_count; 2160068237c8STej Parkash r_addr = cache_hdr->read_addr; 2161068237c8STej Parkash c_addr = cache_hdr->control_addr; 2162068237c8STej Parkash c_value_w = cache_hdr->cache_ctrl.write_value; 2163068237c8STej Parkash 2164068237c8STej Parkash t_r_addr = cache_hdr->tag_reg_addr; 2165068237c8STej Parkash t_value = cache_hdr->addr_ctrl.init_tag_value; 2166068237c8STej Parkash r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2167068237c8STej Parkash p_wait = cache_hdr->cache_ctrl.poll_wait; 2168068237c8STej Parkash p_mask = cache_hdr->cache_ctrl.poll_mask; 2169068237c8STej Parkash 2170068237c8STej Parkash for (i = 0; i < loop_count; i++) { 217133693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); 2172068237c8STej Parkash 2173068237c8STej Parkash if (c_value_w) 217433693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); 2175068237c8STej Parkash 2176068237c8STej Parkash if (p_mask) { 2177068237c8STej Parkash w_time = jiffies + p_wait; 2178068237c8STej Parkash do { 217933693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, c_addr, 218033693c7aSVikas Chaudhary &c_value_r); 2181068237c8STej Parkash if ((c_value_r & p_mask) == 0) { 2182068237c8STej Parkash break; 2183068237c8STej Parkash } else if (time_after_eq(jiffies, w_time)) { 2184068237c8STej Parkash /* capturing dump failed */ 2185068237c8STej Parkash return rval; 2186068237c8STej Parkash } 2187068237c8STej Parkash } while (1); 2188068237c8STej Parkash } 2189068237c8STej Parkash 2190068237c8STej Parkash addr = r_addr; 2191068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 219233693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); 2193068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2194068237c8STej Parkash addr += cache_hdr->read_ctrl.read_addr_stride; 2195068237c8STej Parkash } 2196068237c8STej Parkash 2197068237c8STej Parkash t_value += cache_hdr->addr_ctrl.tag_value_stride; 2198068237c8STej Parkash } 2199068237c8STej Parkash *d_ptr = data_ptr; 2200068237c8STej Parkash return QLA_SUCCESS; 2201068237c8STej Parkash } 2202068237c8STej Parkash 2203068237c8STej Parkash static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha, 22047664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr) 2205068237c8STej Parkash { 22067664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_crb *crb_entry; 2207068237c8STej Parkash uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS; 2208068237c8STej Parkash uint32_t crb_addr; 2209068237c8STej Parkash unsigned long wtime; 2210068237c8STej Parkash struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 2211068237c8STej Parkash int i; 2212068237c8STej Parkash 2213068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 2214068237c8STej Parkash tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 2215068237c8STej Parkash ha->fw_dump_tmplt_hdr; 22167664a1fdSVikas Chaudhary crb_entry = (struct qla8xxx_minidump_entry_crb *)entry_hdr; 2217068237c8STej Parkash 2218068237c8STej Parkash crb_addr = crb_entry->addr; 2219068237c8STej Parkash for (i = 0; i < crb_entry->op_count; i++) { 2220068237c8STej Parkash opcode = crb_entry->crb_ctrl.opcode; 2221de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_WR) { 222233693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, 222333693c7aSVikas Chaudhary crb_entry->value_1); 2224de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_WR; 2225068237c8STej Parkash } 2226de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_RW) { 222733693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 222833693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2229de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_RW; 2230068237c8STej Parkash } 2231de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_AND) { 223233693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2233068237c8STej Parkash read_value &= crb_entry->value_2; 2234de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_AND; 2235de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_OR) { 2236068237c8STej Parkash read_value |= crb_entry->value_3; 2237de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_OR; 2238068237c8STej Parkash } 223933693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2240068237c8STej Parkash } 2241de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_OR) { 224233693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2243068237c8STej Parkash read_value |= crb_entry->value_3; 224433693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, crb_addr, read_value); 2245de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_OR; 2246068237c8STej Parkash } 2247de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_POLL) { 2248068237c8STej Parkash poll_time = crb_entry->crb_strd.poll_timeout; 2249068237c8STej Parkash wtime = jiffies + poll_time; 225033693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, crb_addr, &read_value); 2251068237c8STej Parkash 2252068237c8STej Parkash do { 2253068237c8STej Parkash if ((read_value & crb_entry->value_2) == 225433693c7aSVikas Chaudhary crb_entry->value_1) { 2255068237c8STej Parkash break; 225633693c7aSVikas Chaudhary } else if (time_after_eq(jiffies, wtime)) { 2257068237c8STej Parkash /* capturing dump failed */ 2258068237c8STej Parkash rval = QLA_ERROR; 2259068237c8STej Parkash break; 226033693c7aSVikas Chaudhary } else { 226133693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, 226233693c7aSVikas Chaudhary crb_addr, &read_value); 226333693c7aSVikas Chaudhary } 2264068237c8STej Parkash } while (1); 2265de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_POLL; 2266068237c8STej Parkash } 2267068237c8STej Parkash 2268de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) { 2269068237c8STej Parkash if (crb_entry->crb_strd.state_index_a) { 2270068237c8STej Parkash index = crb_entry->crb_strd.state_index_a; 2271068237c8STej Parkash addr = tmplt_hdr->saved_state_array[index]; 2272068237c8STej Parkash } else { 2273068237c8STej Parkash addr = crb_addr; 2274068237c8STej Parkash } 2275068237c8STej Parkash 227633693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr, &read_value); 2277068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 2278068237c8STej Parkash tmplt_hdr->saved_state_array[index] = read_value; 2279de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE; 2280068237c8STej Parkash } 2281068237c8STej Parkash 2282de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) { 2283068237c8STej Parkash if (crb_entry->crb_strd.state_index_a) { 2284068237c8STej Parkash index = crb_entry->crb_strd.state_index_a; 2285068237c8STej Parkash addr = tmplt_hdr->saved_state_array[index]; 2286068237c8STej Parkash } else { 2287068237c8STej Parkash addr = crb_addr; 2288068237c8STej Parkash } 2289068237c8STej Parkash 2290068237c8STej Parkash if (crb_entry->crb_ctrl.state_index_v) { 2291068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 2292068237c8STej Parkash read_value = 2293068237c8STej Parkash tmplt_hdr->saved_state_array[index]; 2294068237c8STej Parkash } else { 2295068237c8STej Parkash read_value = crb_entry->value_1; 2296068237c8STej Parkash } 2297068237c8STej Parkash 229833693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr, read_value); 2299de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE; 2300068237c8STej Parkash } 2301068237c8STej Parkash 2302de8c72daSVikas Chaudhary if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) { 2303068237c8STej Parkash index = crb_entry->crb_ctrl.state_index_v; 2304068237c8STej Parkash read_value = tmplt_hdr->saved_state_array[index]; 2305068237c8STej Parkash read_value <<= crb_entry->crb_ctrl.shl; 2306068237c8STej Parkash read_value >>= crb_entry->crb_ctrl.shr; 2307068237c8STej Parkash if (crb_entry->value_2) 2308068237c8STej Parkash read_value &= crb_entry->value_2; 2309068237c8STej Parkash read_value |= crb_entry->value_3; 2310068237c8STej Parkash read_value += crb_entry->value_1; 2311068237c8STej Parkash tmplt_hdr->saved_state_array[index] = read_value; 2312de8c72daSVikas Chaudhary opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE; 2313068237c8STej Parkash } 2314068237c8STej Parkash crb_addr += crb_entry->crb_strd.addr_stride; 2315068237c8STej Parkash } 2316068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__)); 2317068237c8STej Parkash return rval; 2318068237c8STej Parkash } 2319068237c8STej Parkash 2320068237c8STej Parkash static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha, 23217664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2322068237c8STej Parkash uint32_t **d_ptr) 2323068237c8STej Parkash { 2324068237c8STej Parkash uint32_t r_addr, r_stride, loop_cnt, i, r_value; 23257664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdocm *ocm_hdr; 2326068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2327068237c8STej Parkash 2328068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 23297664a1fdSVikas Chaudhary ocm_hdr = (struct qla8xxx_minidump_entry_rdocm *)entry_hdr; 2330068237c8STej Parkash r_addr = ocm_hdr->read_addr; 2331068237c8STej Parkash r_stride = ocm_hdr->read_addr_stride; 2332068237c8STej Parkash loop_cnt = ocm_hdr->op_count; 2333068237c8STej Parkash 2334068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2335068237c8STej Parkash "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", 2336068237c8STej Parkash __func__, r_addr, r_stride, loop_cnt)); 2337068237c8STej Parkash 2338068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 2339068237c8STej Parkash r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); 2340068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2341068237c8STej Parkash r_addr += r_stride; 2342068237c8STej Parkash } 2343068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n", 234426fdf922SVikas Chaudhary __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)))); 2345068237c8STej Parkash *d_ptr = data_ptr; 2346068237c8STej Parkash } 2347068237c8STej Parkash 2348068237c8STej Parkash static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha, 23497664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2350068237c8STej Parkash uint32_t **d_ptr) 2351068237c8STej Parkash { 2352068237c8STej Parkash uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 23537664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_mux *mux_hdr; 2354068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2355068237c8STej Parkash 2356068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 23577664a1fdSVikas Chaudhary mux_hdr = (struct qla8xxx_minidump_entry_mux *)entry_hdr; 2358068237c8STej Parkash r_addr = mux_hdr->read_addr; 2359068237c8STej Parkash s_addr = mux_hdr->select_addr; 2360068237c8STej Parkash s_stride = mux_hdr->select_value_stride; 2361068237c8STej Parkash s_value = mux_hdr->select_value; 2362068237c8STej Parkash loop_cnt = mux_hdr->op_count; 2363068237c8STej Parkash 2364068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 236533693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); 236633693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 2367068237c8STej Parkash *data_ptr++ = cpu_to_le32(s_value); 2368068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2369068237c8STej Parkash s_value += s_stride; 2370068237c8STej Parkash } 2371068237c8STej Parkash *d_ptr = data_ptr; 2372068237c8STej Parkash } 2373068237c8STej Parkash 2374068237c8STej Parkash static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha, 23757664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2376068237c8STej Parkash uint32_t **d_ptr) 2377068237c8STej Parkash { 2378068237c8STej Parkash uint32_t addr, r_addr, c_addr, t_r_addr; 2379068237c8STej Parkash uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2380068237c8STej Parkash uint32_t c_value_w; 23817664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_cache *cache_hdr; 2382068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2383068237c8STej Parkash 23847664a1fdSVikas Chaudhary cache_hdr = (struct qla8xxx_minidump_entry_cache *)entry_hdr; 2385068237c8STej Parkash loop_count = cache_hdr->op_count; 2386068237c8STej Parkash r_addr = cache_hdr->read_addr; 2387068237c8STej Parkash c_addr = cache_hdr->control_addr; 2388068237c8STej Parkash c_value_w = cache_hdr->cache_ctrl.write_value; 2389068237c8STej Parkash 2390068237c8STej Parkash t_r_addr = cache_hdr->tag_reg_addr; 2391068237c8STej Parkash t_value = cache_hdr->addr_ctrl.init_tag_value; 2392068237c8STej Parkash r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2393068237c8STej Parkash 2394068237c8STej Parkash for (i = 0; i < loop_count; i++) { 239533693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, t_r_addr, t_value); 239633693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, c_addr, c_value_w); 2397068237c8STej Parkash addr = r_addr; 2398068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 239933693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr, &r_value); 2400068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2401068237c8STej Parkash addr += cache_hdr->read_ctrl.read_addr_stride; 2402068237c8STej Parkash } 2403068237c8STej Parkash t_value += cache_hdr->addr_ctrl.tag_value_stride; 2404068237c8STej Parkash } 2405068237c8STej Parkash *d_ptr = data_ptr; 2406068237c8STej Parkash } 2407068237c8STej Parkash 2408068237c8STej Parkash static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha, 24097664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2410068237c8STej Parkash uint32_t **d_ptr) 2411068237c8STej Parkash { 2412068237c8STej Parkash uint32_t s_addr, r_addr; 2413068237c8STej Parkash uint32_t r_stride, r_value, r_cnt, qid = 0; 2414068237c8STej Parkash uint32_t i, k, loop_cnt; 24157664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_queue *q_hdr; 2416068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2417068237c8STej Parkash 2418068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 24197664a1fdSVikas Chaudhary q_hdr = (struct qla8xxx_minidump_entry_queue *)entry_hdr; 2420068237c8STej Parkash s_addr = q_hdr->select_addr; 2421068237c8STej Parkash r_cnt = q_hdr->rd_strd.read_addr_cnt; 2422068237c8STej Parkash r_stride = q_hdr->rd_strd.read_addr_stride; 2423068237c8STej Parkash loop_cnt = q_hdr->op_count; 2424068237c8STej Parkash 2425068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 242633693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, s_addr, qid); 2427068237c8STej Parkash r_addr = q_hdr->read_addr; 2428068237c8STej Parkash for (k = 0; k < r_cnt; k++) { 242933693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 2430068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2431068237c8STej Parkash r_addr += r_stride; 2432068237c8STej Parkash } 2433068237c8STej Parkash qid += q_hdr->q_strd.queue_id_stride; 2434068237c8STej Parkash } 2435068237c8STej Parkash *d_ptr = data_ptr; 2436068237c8STej Parkash } 2437068237c8STej Parkash 2438068237c8STej Parkash #define MD_DIRECT_ROM_WINDOW 0x42110030 2439068237c8STej Parkash #define MD_DIRECT_ROM_READ_BASE 0x42150000 2440068237c8STej Parkash 2441f8086f4fSVikas Chaudhary static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha, 24427664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2443068237c8STej Parkash uint32_t **d_ptr) 2444068237c8STej Parkash { 2445068237c8STej Parkash uint32_t r_addr, r_value; 2446068237c8STej Parkash uint32_t i, loop_cnt; 24477664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdrom *rom_hdr; 2448068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2449068237c8STej Parkash 2450068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 24517664a1fdSVikas Chaudhary rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; 2452068237c8STej Parkash r_addr = rom_hdr->read_addr; 2453068237c8STej Parkash loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t); 2454068237c8STej Parkash 2455068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2456068237c8STej Parkash "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n", 2457068237c8STej Parkash __func__, r_addr, loop_cnt)); 2458068237c8STej Parkash 2459068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 246033693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_DIRECT_ROM_WINDOW, 246133693c7aSVikas Chaudhary (r_addr & 0xFFFF0000)); 246233693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, 246333693c7aSVikas Chaudhary MD_DIRECT_ROM_READ_BASE + (r_addr & 0x0000FFFF), 246433693c7aSVikas Chaudhary &r_value); 2465068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_value); 2466068237c8STej Parkash r_addr += sizeof(uint32_t); 2467068237c8STej Parkash } 2468068237c8STej Parkash *d_ptr = data_ptr; 2469068237c8STej Parkash } 2470068237c8STej Parkash 2471068237c8STej Parkash #define MD_MIU_TEST_AGT_CTRL 0x41000090 2472068237c8STej Parkash #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 2473068237c8STej Parkash #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 2474068237c8STej Parkash 247541f79bdeSSantosh Vernekar static int __qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 24767664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2477068237c8STej Parkash uint32_t **d_ptr) 2478068237c8STej Parkash { 2479068237c8STej Parkash uint32_t r_addr, r_value, r_data; 2480068237c8STej Parkash uint32_t i, j, loop_cnt; 24817664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_rdmem *m_hdr; 2482068237c8STej Parkash unsigned long flags; 2483068237c8STej Parkash uint32_t *data_ptr = *d_ptr; 2484068237c8STej Parkash 2485068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__)); 24867664a1fdSVikas Chaudhary m_hdr = (struct qla8xxx_minidump_entry_rdmem *)entry_hdr; 2487068237c8STej Parkash r_addr = m_hdr->read_addr; 2488068237c8STej Parkash loop_cnt = m_hdr->read_data_size/16; 2489068237c8STej Parkash 2490068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2491068237c8STej Parkash "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", 2492068237c8STej Parkash __func__, r_addr, m_hdr->read_data_size)); 2493068237c8STej Parkash 2494068237c8STej Parkash if (r_addr & 0xf) { 2495068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2496cf2fbdd2SMasanari Iida "[%s]: Read addr 0x%x not 16 bytes aligned\n", 2497068237c8STej Parkash __func__, r_addr)); 2498068237c8STej Parkash return QLA_ERROR; 2499068237c8STej Parkash } 2500068237c8STej Parkash 2501068237c8STej Parkash if (m_hdr->read_data_size % 16) { 2502068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2503068237c8STej Parkash "[%s]: Read data[0x%x] not multiple of 16 bytes\n", 2504068237c8STej Parkash __func__, m_hdr->read_data_size)); 2505068237c8STej Parkash return QLA_ERROR; 2506068237c8STej Parkash } 2507068237c8STej Parkash 2508068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2509068237c8STej Parkash "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 2510068237c8STej Parkash __func__, r_addr, m_hdr->read_data_size, loop_cnt)); 2511068237c8STej Parkash 2512068237c8STej Parkash write_lock_irqsave(&ha->hw_lock, flags); 2513068237c8STej Parkash for (i = 0; i < loop_cnt; i++) { 251433693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_LO, 251533693c7aSVikas Chaudhary r_addr); 2516068237c8STej Parkash r_value = 0; 251733693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_ADDR_HI, 251833693c7aSVikas Chaudhary r_value); 2519068237c8STej Parkash r_value = MIU_TA_CTL_ENABLE; 252033693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); 2521c38fa3abSVikas Chaudhary r_value = MIU_TA_CTL_START_ENABLE; 252233693c7aSVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, r_value); 2523068237c8STej Parkash 2524068237c8STej Parkash for (j = 0; j < MAX_CTL_CHECK; j++) { 252533693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, MD_MIU_TEST_AGT_CTRL, 252633693c7aSVikas Chaudhary &r_value); 2527068237c8STej Parkash if ((r_value & MIU_TA_CTL_BUSY) == 0) 2528068237c8STej Parkash break; 2529068237c8STej Parkash } 2530068237c8STej Parkash 2531068237c8STej Parkash if (j >= MAX_CTL_CHECK) { 2532068237c8STej Parkash printk_ratelimited(KERN_ERR 2533068237c8STej Parkash "%s: failed to read through agent\n", 2534068237c8STej Parkash __func__); 2535068237c8STej Parkash write_unlock_irqrestore(&ha->hw_lock, flags); 2536068237c8STej Parkash return QLA_SUCCESS; 2537068237c8STej Parkash } 2538068237c8STej Parkash 2539068237c8STej Parkash for (j = 0; j < 4; j++) { 254033693c7aSVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, 2541068237c8STej Parkash MD_MIU_TEST_AGT_RDDATA[j], 254233693c7aSVikas Chaudhary &r_data); 2543068237c8STej Parkash *data_ptr++ = cpu_to_le32(r_data); 2544068237c8STej Parkash } 2545068237c8STej Parkash 2546068237c8STej Parkash r_addr += 16; 2547068237c8STej Parkash } 2548068237c8STej Parkash write_unlock_irqrestore(&ha->hw_lock, flags); 2549068237c8STej Parkash 2550068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n", 2551068237c8STej Parkash __func__, (loop_cnt * 16))); 2552068237c8STej Parkash 2553068237c8STej Parkash *d_ptr = data_ptr; 2554068237c8STej Parkash return QLA_SUCCESS; 2555068237c8STej Parkash } 2556068237c8STej Parkash 255741f79bdeSSantosh Vernekar static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha, 255841f79bdeSSantosh Vernekar struct qla8xxx_minidump_entry_hdr *entry_hdr, 255941f79bdeSSantosh Vernekar uint32_t **d_ptr) 256041f79bdeSSantosh Vernekar { 256141f79bdeSSantosh Vernekar uint32_t *data_ptr = *d_ptr; 256241f79bdeSSantosh Vernekar int rval = QLA_SUCCESS; 256341f79bdeSSantosh Vernekar 25643c3cab17STej Parkash rval = qla4_8xxx_minidump_pex_dma_read(ha, entry_hdr, &data_ptr); 25653c3cab17STej Parkash if (rval != QLA_SUCCESS) 256641f79bdeSSantosh Vernekar rval = __qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 256741f79bdeSSantosh Vernekar &data_ptr); 256841f79bdeSSantosh Vernekar *d_ptr = data_ptr; 256941f79bdeSSantosh Vernekar return rval; 257041f79bdeSSantosh Vernekar } 257141f79bdeSSantosh Vernekar 25725e9bcec7SVikas Chaudhary static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha, 25737664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 2574068237c8STej Parkash int index) 2575068237c8STej Parkash { 2576de8c72daSVikas Chaudhary entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG; 2577068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 2578068237c8STej Parkash "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", 2579068237c8STej Parkash ha->host_no, index, entry_hdr->entry_type, 2580068237c8STej Parkash entry_hdr->d_ctrl.entry_capture_mask)); 258158e2bbe9STej Parkash /* If driver encounters a new entry type that it cannot process, 258258e2bbe9STej Parkash * it should just skip the entry and adjust the total buffer size by 258358e2bbe9STej Parkash * from subtracting the skipped bytes from it 258458e2bbe9STej Parkash */ 258558e2bbe9STej Parkash ha->fw_dump_skip_size += entry_hdr->entry_capture_size; 2586068237c8STej Parkash } 2587068237c8STej Parkash 25886e7b4292SVikas Chaudhary /* ISP83xx functions to process new minidump entries... */ 25896e7b4292SVikas Chaudhary static uint32_t qla83xx_minidump_process_pollrd(struct scsi_qla_host *ha, 25906e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 25916e7b4292SVikas Chaudhary uint32_t **d_ptr) 25926e7b4292SVikas Chaudhary { 25936e7b4292SVikas Chaudhary uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; 25946e7b4292SVikas Chaudhary uint16_t s_stride, i; 25956e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 25966e7b4292SVikas Chaudhary uint32_t rval = QLA_SUCCESS; 25976e7b4292SVikas Chaudhary struct qla83xx_minidump_entry_pollrd *pollrd_hdr; 25986e7b4292SVikas Chaudhary 25996e7b4292SVikas Chaudhary pollrd_hdr = (struct qla83xx_minidump_entry_pollrd *)entry_hdr; 26006e7b4292SVikas Chaudhary s_addr = le32_to_cpu(pollrd_hdr->select_addr); 26016e7b4292SVikas Chaudhary r_addr = le32_to_cpu(pollrd_hdr->read_addr); 26026e7b4292SVikas Chaudhary s_value = le32_to_cpu(pollrd_hdr->select_value); 26036e7b4292SVikas Chaudhary s_stride = le32_to_cpu(pollrd_hdr->select_value_stride); 26046e7b4292SVikas Chaudhary 26056e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); 26066e7b4292SVikas Chaudhary poll_mask = le32_to_cpu(pollrd_hdr->poll_mask); 26076e7b4292SVikas Chaudhary 26086e7b4292SVikas Chaudhary for (i = 0; i < le32_to_cpu(pollrd_hdr->op_count); i++) { 26096e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, s_addr, s_value); 26106e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(pollrd_hdr->poll_wait); 26116e7b4292SVikas Chaudhary while (1) { 26126e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, s_addr, &r_value); 26136e7b4292SVikas Chaudhary 26146e7b4292SVikas Chaudhary if ((r_value & poll_mask) != 0) { 26156e7b4292SVikas Chaudhary break; 26166e7b4292SVikas Chaudhary } else { 26176e7b4292SVikas Chaudhary msleep(1); 26186e7b4292SVikas Chaudhary if (--poll_wait == 0) { 26196e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", 26206e7b4292SVikas Chaudhary __func__); 26216e7b4292SVikas Chaudhary rval = QLA_ERROR; 26226e7b4292SVikas Chaudhary goto exit_process_pollrd; 26236e7b4292SVikas Chaudhary } 26246e7b4292SVikas Chaudhary } 26256e7b4292SVikas Chaudhary } 26266e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, r_addr, &r_value); 26276e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(s_value); 26286e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(r_value); 26296e7b4292SVikas Chaudhary s_value += s_stride; 26306e7b4292SVikas Chaudhary } 26316e7b4292SVikas Chaudhary 26326e7b4292SVikas Chaudhary *d_ptr = data_ptr; 26336e7b4292SVikas Chaudhary 26346e7b4292SVikas Chaudhary exit_process_pollrd: 26356e7b4292SVikas Chaudhary return rval; 26366e7b4292SVikas Chaudhary } 26376e7b4292SVikas Chaudhary 2638b1829789STej Parkash static uint32_t qla4_84xx_minidump_process_rddfe(struct scsi_qla_host *ha, 2639b1829789STej Parkash struct qla8xxx_minidump_entry_hdr *entry_hdr, 2640b1829789STej Parkash uint32_t **d_ptr) 2641b1829789STej Parkash { 2642b1829789STej Parkash int loop_cnt; 2643b1829789STej Parkash uint32_t addr1, addr2, value, data, temp, wrval; 2644b1829789STej Parkash uint8_t stride, stride2; 2645b1829789STej Parkash uint16_t count; 2646b1829789STej Parkash uint32_t poll, mask, data_size, modify_mask; 2647b1829789STej Parkash uint32_t wait_count = 0; 2648b1829789STej Parkash uint32_t *data_ptr = *d_ptr; 2649b1829789STej Parkash struct qla8044_minidump_entry_rddfe *rddfe; 2650b1829789STej Parkash uint32_t rval = QLA_SUCCESS; 2651b1829789STej Parkash 2652b1829789STej Parkash rddfe = (struct qla8044_minidump_entry_rddfe *)entry_hdr; 2653b1829789STej Parkash addr1 = le32_to_cpu(rddfe->addr_1); 2654b1829789STej Parkash value = le32_to_cpu(rddfe->value); 2655b1829789STej Parkash stride = le32_to_cpu(rddfe->stride); 2656b1829789STej Parkash stride2 = le32_to_cpu(rddfe->stride2); 2657b1829789STej Parkash count = le32_to_cpu(rddfe->count); 2658b1829789STej Parkash 2659b1829789STej Parkash poll = le32_to_cpu(rddfe->poll); 2660b1829789STej Parkash mask = le32_to_cpu(rddfe->mask); 2661b1829789STej Parkash modify_mask = le32_to_cpu(rddfe->modify_mask); 2662b1829789STej Parkash data_size = le32_to_cpu(rddfe->data_size); 2663b1829789STej Parkash 2664b1829789STej Parkash addr2 = addr1 + stride; 2665b1829789STej Parkash 2666b1829789STej Parkash for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) { 2667b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, (0x40000000 | value)); 2668b1829789STej Parkash 2669b1829789STej Parkash wait_count = 0; 2670b1829789STej Parkash while (wait_count < poll) { 2671b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 2672b1829789STej Parkash if ((temp & mask) != 0) 2673b1829789STej Parkash break; 2674b1829789STej Parkash wait_count++; 2675b1829789STej Parkash } 2676b1829789STej Parkash 2677b1829789STej Parkash if (wait_count == poll) { 2678b1829789STej Parkash ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__); 2679b1829789STej Parkash rval = QLA_ERROR; 2680b1829789STej Parkash goto exit_process_rddfe; 2681b1829789STej Parkash } else { 2682b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr2, &temp); 2683b1829789STej Parkash temp = temp & modify_mask; 2684b1829789STej Parkash temp = (temp | ((loop_cnt << 16) | loop_cnt)); 2685b1829789STej Parkash wrval = ((temp << 16) | temp); 2686b1829789STej Parkash 2687b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr2, wrval); 2688b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, value); 2689b1829789STej Parkash 2690b1829789STej Parkash wait_count = 0; 2691b1829789STej Parkash while (wait_count < poll) { 2692b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 2693b1829789STej Parkash if ((temp & mask) != 0) 2694b1829789STej Parkash break; 2695b1829789STej Parkash wait_count++; 2696b1829789STej Parkash } 2697b1829789STej Parkash if (wait_count == poll) { 2698b1829789STej Parkash ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", 2699b1829789STej Parkash __func__); 2700b1829789STej Parkash rval = QLA_ERROR; 2701b1829789STej Parkash goto exit_process_rddfe; 2702b1829789STej Parkash } 2703b1829789STej Parkash 2704b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, 2705b1829789STej Parkash ((0x40000000 | value) + 2706b1829789STej Parkash stride2)); 2707b1829789STej Parkash wait_count = 0; 2708b1829789STej Parkash while (wait_count < poll) { 2709b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &temp); 2710b1829789STej Parkash if ((temp & mask) != 0) 2711b1829789STej Parkash break; 2712b1829789STej Parkash wait_count++; 2713b1829789STej Parkash } 2714b1829789STej Parkash 2715b1829789STej Parkash if (wait_count == poll) { 2716b1829789STej Parkash ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", 2717b1829789STej Parkash __func__); 2718b1829789STej Parkash rval = QLA_ERROR; 2719b1829789STej Parkash goto exit_process_rddfe; 2720b1829789STej Parkash } 2721b1829789STej Parkash 2722b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr2, &data); 2723b1829789STej Parkash 2724b1829789STej Parkash *data_ptr++ = cpu_to_le32(wrval); 2725b1829789STej Parkash *data_ptr++ = cpu_to_le32(data); 2726b1829789STej Parkash } 2727b1829789STej Parkash } 2728b1829789STej Parkash 2729b1829789STej Parkash *d_ptr = data_ptr; 2730b1829789STej Parkash exit_process_rddfe: 2731b1829789STej Parkash return rval; 2732b1829789STej Parkash } 2733b1829789STej Parkash 2734b1829789STej Parkash static uint32_t qla4_84xx_minidump_process_rdmdio(struct scsi_qla_host *ha, 2735b1829789STej Parkash struct qla8xxx_minidump_entry_hdr *entry_hdr, 2736b1829789STej Parkash uint32_t **d_ptr) 2737b1829789STej Parkash { 2738b1829789STej Parkash int rval = QLA_SUCCESS; 2739b1829789STej Parkash uint32_t addr1, addr2, value1, value2, data, selval; 2740b1829789STej Parkash uint8_t stride1, stride2; 2741b1829789STej Parkash uint32_t addr3, addr4, addr5, addr6, addr7; 2742b1829789STej Parkash uint16_t count, loop_cnt; 2743b1829789STej Parkash uint32_t poll, mask; 2744b1829789STej Parkash uint32_t *data_ptr = *d_ptr; 2745b1829789STej Parkash struct qla8044_minidump_entry_rdmdio *rdmdio; 2746b1829789STej Parkash 2747b1829789STej Parkash rdmdio = (struct qla8044_minidump_entry_rdmdio *)entry_hdr; 2748b1829789STej Parkash addr1 = le32_to_cpu(rdmdio->addr_1); 2749b1829789STej Parkash addr2 = le32_to_cpu(rdmdio->addr_2); 2750b1829789STej Parkash value1 = le32_to_cpu(rdmdio->value_1); 2751b1829789STej Parkash stride1 = le32_to_cpu(rdmdio->stride_1); 2752b1829789STej Parkash stride2 = le32_to_cpu(rdmdio->stride_2); 2753b1829789STej Parkash count = le32_to_cpu(rdmdio->count); 2754b1829789STej Parkash 2755b1829789STej Parkash poll = le32_to_cpu(rdmdio->poll); 2756b1829789STej Parkash mask = le32_to_cpu(rdmdio->mask); 2757b1829789STej Parkash value2 = le32_to_cpu(rdmdio->value_2); 2758b1829789STej Parkash 2759b1829789STej Parkash addr3 = addr1 + stride1; 2760b1829789STej Parkash 2761b1829789STej Parkash for (loop_cnt = 0; loop_cnt < count; loop_cnt++) { 2762b1829789STej Parkash rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2, 2763b1829789STej Parkash addr3, mask); 2764b1829789STej Parkash if (rval) 2765b1829789STej Parkash goto exit_process_rdmdio; 2766b1829789STej Parkash 2767b1829789STej Parkash addr4 = addr2 - stride1; 2768b1829789STej Parkash rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4, 2769b1829789STej Parkash value2); 2770b1829789STej Parkash if (rval) 2771b1829789STej Parkash goto exit_process_rdmdio; 2772b1829789STej Parkash 2773b1829789STej Parkash addr5 = addr2 - (2 * stride1); 2774b1829789STej Parkash rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5, 2775b1829789STej Parkash value1); 2776b1829789STej Parkash if (rval) 2777b1829789STej Parkash goto exit_process_rdmdio; 2778b1829789STej Parkash 2779b1829789STej Parkash addr6 = addr2 - (3 * stride1); 2780b1829789STej Parkash rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, 2781b1829789STej Parkash addr6, 0x2); 2782b1829789STej Parkash if (rval) 2783b1829789STej Parkash goto exit_process_rdmdio; 2784b1829789STej Parkash 2785b1829789STej Parkash rval = ql4_84xx_poll_wait_ipmdio_bus_idle(ha, addr1, addr2, 2786b1829789STej Parkash addr3, mask); 2787b1829789STej Parkash if (rval) 2788b1829789STej Parkash goto exit_process_rdmdio; 2789b1829789STej Parkash 2790b1829789STej Parkash addr7 = addr2 - (4 * stride1); 2791b1829789STej Parkash rval = ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, 2792b1829789STej Parkash mask, addr7, &data); 2793b1829789STej Parkash if (rval) 2794b1829789STej Parkash goto exit_process_rdmdio; 2795b1829789STej Parkash 2796b1829789STej Parkash selval = (value2 << 18) | (value1 << 2) | 2; 2797b1829789STej Parkash 2798b1829789STej Parkash stride2 = le32_to_cpu(rdmdio->stride_2); 2799b1829789STej Parkash *data_ptr++ = cpu_to_le32(selval); 2800b1829789STej Parkash *data_ptr++ = cpu_to_le32(data); 2801b1829789STej Parkash 2802b1829789STej Parkash value1 = value1 + stride2; 2803b1829789STej Parkash *d_ptr = data_ptr; 2804b1829789STej Parkash } 2805b1829789STej Parkash 2806b1829789STej Parkash exit_process_rdmdio: 2807b1829789STej Parkash return rval; 2808b1829789STej Parkash } 2809b1829789STej Parkash 2810b1829789STej Parkash static uint32_t qla4_84xx_minidump_process_pollwr(struct scsi_qla_host *ha, 2811b1829789STej Parkash struct qla8xxx_minidump_entry_hdr *entry_hdr, 2812b1829789STej Parkash uint32_t **d_ptr) 2813b1829789STej Parkash { 2814b1829789STej Parkash uint32_t addr1, addr2, value1, value2, poll, mask, r_value; 2815b1829789STej Parkash struct qla8044_minidump_entry_pollwr *pollwr_hdr; 2816b1829789STej Parkash uint32_t wait_count = 0; 2817b1829789STej Parkash uint32_t rval = QLA_SUCCESS; 2818b1829789STej Parkash 2819b1829789STej Parkash pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr; 2820b1829789STej Parkash addr1 = le32_to_cpu(pollwr_hdr->addr_1); 2821b1829789STej Parkash addr2 = le32_to_cpu(pollwr_hdr->addr_2); 2822b1829789STej Parkash value1 = le32_to_cpu(pollwr_hdr->value_1); 2823b1829789STej Parkash value2 = le32_to_cpu(pollwr_hdr->value_2); 2824b1829789STej Parkash 2825b1829789STej Parkash poll = le32_to_cpu(pollwr_hdr->poll); 2826b1829789STej Parkash mask = le32_to_cpu(pollwr_hdr->mask); 2827b1829789STej Parkash 2828b1829789STej Parkash while (wait_count < poll) { 2829b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value); 2830b1829789STej Parkash 2831b1829789STej Parkash if ((r_value & poll) != 0) 2832b1829789STej Parkash break; 2833b1829789STej Parkash 2834b1829789STej Parkash wait_count++; 2835b1829789STej Parkash } 2836b1829789STej Parkash 2837b1829789STej Parkash if (wait_count == poll) { 2838b1829789STej Parkash ql4_printk(KERN_ERR, ha, "%s: TIMEOUT\n", __func__); 2839b1829789STej Parkash rval = QLA_ERROR; 2840b1829789STej Parkash goto exit_process_pollwr; 2841b1829789STej Parkash } 2842b1829789STej Parkash 2843b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr2, value2); 2844b1829789STej Parkash ha->isp_ops->wr_reg_indirect(ha, addr1, value1); 2845b1829789STej Parkash 2846b1829789STej Parkash wait_count = 0; 2847b1829789STej Parkash while (wait_count < poll) { 2848b1829789STej Parkash ha->isp_ops->rd_reg_indirect(ha, addr1, &r_value); 2849b1829789STej Parkash 2850b1829789STej Parkash if ((r_value & poll) != 0) 2851b1829789STej Parkash break; 2852b1829789STej Parkash wait_count++; 2853b1829789STej Parkash } 2854b1829789STej Parkash 2855b1829789STej Parkash exit_process_pollwr: 2856b1829789STej Parkash return rval; 2857b1829789STej Parkash } 2858b1829789STej Parkash 28596e7b4292SVikas Chaudhary static void qla83xx_minidump_process_rdmux2(struct scsi_qla_host *ha, 28606e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 28616e7b4292SVikas Chaudhary uint32_t **d_ptr) 28626e7b4292SVikas Chaudhary { 28636e7b4292SVikas Chaudhary uint32_t sel_val1, sel_val2, t_sel_val, data, i; 28646e7b4292SVikas Chaudhary uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; 28656e7b4292SVikas Chaudhary struct qla83xx_minidump_entry_rdmux2 *rdmux2_hdr; 28666e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 28676e7b4292SVikas Chaudhary 28686e7b4292SVikas Chaudhary rdmux2_hdr = (struct qla83xx_minidump_entry_rdmux2 *)entry_hdr; 28696e7b4292SVikas Chaudhary sel_val1 = le32_to_cpu(rdmux2_hdr->select_value_1); 28706e7b4292SVikas Chaudhary sel_val2 = le32_to_cpu(rdmux2_hdr->select_value_2); 28716e7b4292SVikas Chaudhary sel_addr1 = le32_to_cpu(rdmux2_hdr->select_addr_1); 28726e7b4292SVikas Chaudhary sel_addr2 = le32_to_cpu(rdmux2_hdr->select_addr_2); 28736e7b4292SVikas Chaudhary sel_val_mask = le32_to_cpu(rdmux2_hdr->select_value_mask); 28746e7b4292SVikas Chaudhary read_addr = le32_to_cpu(rdmux2_hdr->read_addr); 28756e7b4292SVikas Chaudhary 28766e7b4292SVikas Chaudhary for (i = 0; i < rdmux2_hdr->op_count; i++) { 28776e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val1); 28786e7b4292SVikas Chaudhary t_sel_val = sel_val1 & sel_val_mask; 28796e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(t_sel_val); 28806e7b4292SVikas Chaudhary 28816e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); 28826e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); 28836e7b4292SVikas Chaudhary 28846e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(data); 28856e7b4292SVikas Chaudhary 28866e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr1, sel_val2); 28876e7b4292SVikas Chaudhary t_sel_val = sel_val2 & sel_val_mask; 28886e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(t_sel_val); 28896e7b4292SVikas Chaudhary 28906e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, sel_addr2, t_sel_val); 28916e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, read_addr, &data); 28926e7b4292SVikas Chaudhary 28936e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(data); 28946e7b4292SVikas Chaudhary 28956e7b4292SVikas Chaudhary sel_val1 += rdmux2_hdr->select_value_stride; 28966e7b4292SVikas Chaudhary sel_val2 += rdmux2_hdr->select_value_stride; 28976e7b4292SVikas Chaudhary } 28986e7b4292SVikas Chaudhary 28996e7b4292SVikas Chaudhary *d_ptr = data_ptr; 29006e7b4292SVikas Chaudhary } 29016e7b4292SVikas Chaudhary 29026e7b4292SVikas Chaudhary static uint32_t qla83xx_minidump_process_pollrdmwr(struct scsi_qla_host *ha, 29036e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 29046e7b4292SVikas Chaudhary uint32_t **d_ptr) 29056e7b4292SVikas Chaudhary { 29066e7b4292SVikas Chaudhary uint32_t poll_wait, poll_mask, r_value, data; 29076e7b4292SVikas Chaudhary uint32_t addr_1, addr_2, value_1, value_2; 29086e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 29096e7b4292SVikas Chaudhary uint32_t rval = QLA_SUCCESS; 29106e7b4292SVikas Chaudhary struct qla83xx_minidump_entry_pollrdmwr *poll_hdr; 29116e7b4292SVikas Chaudhary 29126e7b4292SVikas Chaudhary poll_hdr = (struct qla83xx_minidump_entry_pollrdmwr *)entry_hdr; 29136e7b4292SVikas Chaudhary addr_1 = le32_to_cpu(poll_hdr->addr_1); 29146e7b4292SVikas Chaudhary addr_2 = le32_to_cpu(poll_hdr->addr_2); 29156e7b4292SVikas Chaudhary value_1 = le32_to_cpu(poll_hdr->value_1); 29166e7b4292SVikas Chaudhary value_2 = le32_to_cpu(poll_hdr->value_2); 29176e7b4292SVikas Chaudhary poll_mask = le32_to_cpu(poll_hdr->poll_mask); 29186e7b4292SVikas Chaudhary 29196e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr_1, value_1); 29206e7b4292SVikas Chaudhary 29216e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(poll_hdr->poll_wait); 29226e7b4292SVikas Chaudhary while (1) { 29236e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); 29246e7b4292SVikas Chaudhary 29256e7b4292SVikas Chaudhary if ((r_value & poll_mask) != 0) { 29266e7b4292SVikas Chaudhary break; 29276e7b4292SVikas Chaudhary } else { 29286e7b4292SVikas Chaudhary msleep(1); 29296e7b4292SVikas Chaudhary if (--poll_wait == 0) { 29306e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_1\n", 29316e7b4292SVikas Chaudhary __func__); 29326e7b4292SVikas Chaudhary rval = QLA_ERROR; 29336e7b4292SVikas Chaudhary goto exit_process_pollrdmwr; 29346e7b4292SVikas Chaudhary } 29356e7b4292SVikas Chaudhary } 29366e7b4292SVikas Chaudhary } 29376e7b4292SVikas Chaudhary 29386e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr_2, &data); 29396e7b4292SVikas Chaudhary data &= le32_to_cpu(poll_hdr->modify_mask); 29406e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr_2, data); 29416e7b4292SVikas Chaudhary ha->isp_ops->wr_reg_indirect(ha, addr_1, value_2); 29426e7b4292SVikas Chaudhary 29436e7b4292SVikas Chaudhary poll_wait = le32_to_cpu(poll_hdr->poll_wait); 29446e7b4292SVikas Chaudhary while (1) { 29456e7b4292SVikas Chaudhary ha->isp_ops->rd_reg_indirect(ha, addr_1, &r_value); 29466e7b4292SVikas Chaudhary 29476e7b4292SVikas Chaudhary if ((r_value & poll_mask) != 0) { 29486e7b4292SVikas Chaudhary break; 29496e7b4292SVikas Chaudhary } else { 29506e7b4292SVikas Chaudhary msleep(1); 29516e7b4292SVikas Chaudhary if (--poll_wait == 0) { 29526e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: TIMEOUT_2\n", 29536e7b4292SVikas Chaudhary __func__); 29546e7b4292SVikas Chaudhary rval = QLA_ERROR; 29556e7b4292SVikas Chaudhary goto exit_process_pollrdmwr; 29566e7b4292SVikas Chaudhary } 29576e7b4292SVikas Chaudhary } 29586e7b4292SVikas Chaudhary } 29596e7b4292SVikas Chaudhary 29606e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(addr_2); 29616e7b4292SVikas Chaudhary *data_ptr++ = cpu_to_le32(data); 29626e7b4292SVikas Chaudhary *d_ptr = data_ptr; 29636e7b4292SVikas Chaudhary 29646e7b4292SVikas Chaudhary exit_process_pollrdmwr: 29656e7b4292SVikas Chaudhary return rval; 29666e7b4292SVikas Chaudhary } 29676e7b4292SVikas Chaudhary 29686e7b4292SVikas Chaudhary static uint32_t qla4_83xx_minidump_process_rdrom(struct scsi_qla_host *ha, 29696e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr, 29706e7b4292SVikas Chaudhary uint32_t **d_ptr) 29716e7b4292SVikas Chaudhary { 29726e7b4292SVikas Chaudhary uint32_t fl_addr, u32_count, rval; 29736e7b4292SVikas Chaudhary struct qla8xxx_minidump_entry_rdrom *rom_hdr; 29746e7b4292SVikas Chaudhary uint32_t *data_ptr = *d_ptr; 29756e7b4292SVikas Chaudhary 29766e7b4292SVikas Chaudhary rom_hdr = (struct qla8xxx_minidump_entry_rdrom *)entry_hdr; 29776e7b4292SVikas Chaudhary fl_addr = le32_to_cpu(rom_hdr->read_addr); 29786e7b4292SVikas Chaudhary u32_count = le32_to_cpu(rom_hdr->read_data_size)/sizeof(uint32_t); 29796e7b4292SVikas Chaudhary 29806e7b4292SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "[%s]: fl_addr: 0x%x, count: 0x%x\n", 29816e7b4292SVikas Chaudhary __func__, fl_addr, u32_count)); 29826e7b4292SVikas Chaudhary 29836e7b4292SVikas Chaudhary rval = qla4_83xx_lockless_flash_read_u32(ha, fl_addr, 29846e7b4292SVikas Chaudhary (u8 *)(data_ptr), u32_count); 29856e7b4292SVikas Chaudhary 29866e7b4292SVikas Chaudhary if (rval == QLA_ERROR) { 29876e7b4292SVikas Chaudhary ql4_printk(KERN_ERR, ha, "%s: Flash Read Error,Count=%d\n", 29886e7b4292SVikas Chaudhary __func__, u32_count); 29896e7b4292SVikas Chaudhary goto exit_process_rdrom; 29906e7b4292SVikas Chaudhary } 29916e7b4292SVikas Chaudhary 29926e7b4292SVikas Chaudhary data_ptr += u32_count; 29936e7b4292SVikas Chaudhary *d_ptr = data_ptr; 29946e7b4292SVikas Chaudhary 29956e7b4292SVikas Chaudhary exit_process_rdrom: 29966e7b4292SVikas Chaudhary return rval; 29976e7b4292SVikas Chaudhary } 29986e7b4292SVikas Chaudhary 2999068237c8STej Parkash /** 3000f8086f4fSVikas Chaudhary * qla4_8xxx_collect_md_data - Retrieve firmware minidump data. 3001068237c8STej Parkash * @ha: pointer to adapter structure 3002068237c8STej Parkash **/ 3003068237c8STej Parkash static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha) 3004068237c8STej Parkash { 3005068237c8STej Parkash int num_entry_hdr = 0; 30067664a1fdSVikas Chaudhary struct qla8xxx_minidump_entry_hdr *entry_hdr; 3007068237c8STej Parkash struct qla4_8xxx_minidump_template_hdr *tmplt_hdr; 3008068237c8STej Parkash uint32_t *data_ptr; 3009068237c8STej Parkash uint32_t data_collected = 0; 3010068237c8STej Parkash int i, rval = QLA_ERROR; 3011068237c8STej Parkash uint64_t now; 3012068237c8STej Parkash uint32_t timestamp; 3013068237c8STej Parkash 301458e2bbe9STej Parkash ha->fw_dump_skip_size = 0; 3015068237c8STej Parkash if (!ha->fw_dump) { 3016068237c8STej Parkash ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n", 3017068237c8STej Parkash __func__, ha->host_no); 3018068237c8STej Parkash return rval; 3019068237c8STej Parkash } 3020068237c8STej Parkash 3021068237c8STej Parkash tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *) 3022068237c8STej Parkash ha->fw_dump_tmplt_hdr; 3023068237c8STej Parkash data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump + 3024068237c8STej Parkash ha->fw_dump_tmplt_size); 3025068237c8STej Parkash data_collected += ha->fw_dump_tmplt_size; 3026068237c8STej Parkash 3027068237c8STej Parkash num_entry_hdr = tmplt_hdr->num_of_entries; 3028068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n", 3029068237c8STej Parkash __func__, data_ptr); 3030068237c8STej Parkash ql4_printk(KERN_INFO, ha, 3031068237c8STej Parkash "[%s]: no of entry headers in Template: 0x%x\n", 3032068237c8STej Parkash __func__, num_entry_hdr); 3033068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n", 3034068237c8STej Parkash __func__, ha->fw_dump_capture_mask); 3035068237c8STej Parkash ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n", 3036068237c8STej Parkash __func__, ha->fw_dump_size, ha->fw_dump_size); 3037068237c8STej Parkash 3038068237c8STej Parkash /* Update current timestamp before taking dump */ 3039068237c8STej Parkash now = get_jiffies_64(); 3040068237c8STej Parkash timestamp = (u32)(jiffies_to_msecs(now) / 1000); 3041068237c8STej Parkash tmplt_hdr->driver_timestamp = timestamp; 3042068237c8STej Parkash 30437664a1fdSVikas Chaudhary entry_hdr = (struct qla8xxx_minidump_entry_hdr *) 3044068237c8STej Parkash (((uint8_t *)ha->fw_dump_tmplt_hdr) + 3045068237c8STej Parkash tmplt_hdr->first_entry_offset); 3046068237c8STej Parkash 3047b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) 30486e7b4292SVikas Chaudhary tmplt_hdr->saved_state_array[QLA83XX_SS_OCM_WNDREG_INDEX] = 30496e7b4292SVikas Chaudhary tmplt_hdr->ocm_window_reg[ha->func_num]; 30506e7b4292SVikas Chaudhary 3051068237c8STej Parkash /* Walk through the entry headers - validate/perform required action */ 3052068237c8STej Parkash for (i = 0; i < num_entry_hdr; i++) { 30534812d070SSantosh Vernekar if (data_collected > ha->fw_dump_size) { 3054068237c8STej Parkash ql4_printk(KERN_INFO, ha, 3055068237c8STej Parkash "Data collected: [0x%x], Total Dump size: [0x%x]\n", 3056068237c8STej Parkash data_collected, ha->fw_dump_size); 3057068237c8STej Parkash return rval; 3058068237c8STej Parkash } 3059068237c8STej Parkash 3060068237c8STej Parkash if (!(entry_hdr->d_ctrl.entry_capture_mask & 3061068237c8STej Parkash ha->fw_dump_capture_mask)) { 3062068237c8STej Parkash entry_hdr->d_ctrl.driver_flags |= 3063de8c72daSVikas Chaudhary QLA8XXX_DBG_SKIPPED_FLAG; 3064068237c8STej Parkash goto skip_nxt_entry; 3065068237c8STej Parkash } 3066068237c8STej Parkash 3067068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 3068068237c8STej Parkash "Data collected: [0x%x], Dump size left:[0x%x]\n", 3069068237c8STej Parkash data_collected, 3070068237c8STej Parkash (ha->fw_dump_size - data_collected))); 3071068237c8STej Parkash 3072068237c8STej Parkash /* Decode the entry type and take required action to capture 3073068237c8STej Parkash * debug data 3074068237c8STej Parkash */ 3075068237c8STej Parkash switch (entry_hdr->entry_type) { 3076de8c72daSVikas Chaudhary case QLA8XXX_RDEND: 30775e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3078068237c8STej Parkash break; 3079de8c72daSVikas Chaudhary case QLA8XXX_CNTRL: 3080068237c8STej Parkash rval = qla4_8xxx_minidump_process_control(ha, 3081068237c8STej Parkash entry_hdr); 3082068237c8STej Parkash if (rval != QLA_SUCCESS) { 30835e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3084068237c8STej Parkash goto md_failed; 3085068237c8STej Parkash } 3086068237c8STej Parkash break; 3087de8c72daSVikas Chaudhary case QLA8XXX_RDCRB: 3088068237c8STej Parkash qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr, 3089068237c8STej Parkash &data_ptr); 3090068237c8STej Parkash break; 3091de8c72daSVikas Chaudhary case QLA8XXX_RDMEM: 3092068237c8STej Parkash rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr, 3093068237c8STej Parkash &data_ptr); 3094068237c8STej Parkash if (rval != QLA_SUCCESS) { 30955e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3096068237c8STej Parkash goto md_failed; 3097068237c8STej Parkash } 3098068237c8STej Parkash break; 3099de8c72daSVikas Chaudhary case QLA8XXX_BOARD: 3100de8c72daSVikas Chaudhary case QLA8XXX_RDROM: 31016e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 3102f8086f4fSVikas Chaudhary qla4_82xx_minidump_process_rdrom(ha, entry_hdr, 3103068237c8STej Parkash &data_ptr); 3104b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 31056e7b4292SVikas Chaudhary rval = qla4_83xx_minidump_process_rdrom(ha, 31066e7b4292SVikas Chaudhary entry_hdr, 31076e7b4292SVikas Chaudhary &data_ptr); 31086e7b4292SVikas Chaudhary if (rval != QLA_SUCCESS) 31096e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, 31106e7b4292SVikas Chaudhary entry_hdr, 31116e7b4292SVikas Chaudhary i); 31126e7b4292SVikas Chaudhary } 3113068237c8STej Parkash break; 3114de8c72daSVikas Chaudhary case QLA8XXX_L2DTG: 3115de8c72daSVikas Chaudhary case QLA8XXX_L2ITG: 3116de8c72daSVikas Chaudhary case QLA8XXX_L2DAT: 3117de8c72daSVikas Chaudhary case QLA8XXX_L2INS: 3118068237c8STej Parkash rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr, 3119068237c8STej Parkash &data_ptr); 3120068237c8STej Parkash if (rval != QLA_SUCCESS) { 31215e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3122068237c8STej Parkash goto md_failed; 3123068237c8STej Parkash } 3124068237c8STej Parkash break; 31256e7b4292SVikas Chaudhary case QLA8XXX_L1DTG: 31266e7b4292SVikas Chaudhary case QLA8XXX_L1ITG: 3127de8c72daSVikas Chaudhary case QLA8XXX_L1DAT: 3128de8c72daSVikas Chaudhary case QLA8XXX_L1INS: 3129068237c8STej Parkash qla4_8xxx_minidump_process_l1cache(ha, entry_hdr, 3130068237c8STej Parkash &data_ptr); 3131068237c8STej Parkash break; 3132de8c72daSVikas Chaudhary case QLA8XXX_RDOCM: 3133068237c8STej Parkash qla4_8xxx_minidump_process_rdocm(ha, entry_hdr, 3134068237c8STej Parkash &data_ptr); 3135068237c8STej Parkash break; 3136de8c72daSVikas Chaudhary case QLA8XXX_RDMUX: 3137068237c8STej Parkash qla4_8xxx_minidump_process_rdmux(ha, entry_hdr, 3138068237c8STej Parkash &data_ptr); 3139068237c8STej Parkash break; 3140de8c72daSVikas Chaudhary case QLA8XXX_QUEUE: 3141068237c8STej Parkash qla4_8xxx_minidump_process_queue(ha, entry_hdr, 3142068237c8STej Parkash &data_ptr); 3143068237c8STej Parkash break; 31446e7b4292SVikas Chaudhary case QLA83XX_POLLRD: 3145b37ca418SVikas Chaudhary if (is_qla8022(ha)) { 31466e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 31476e7b4292SVikas Chaudhary break; 31486e7b4292SVikas Chaudhary } 31496e7b4292SVikas Chaudhary rval = qla83xx_minidump_process_pollrd(ha, entry_hdr, 31506e7b4292SVikas Chaudhary &data_ptr); 31516e7b4292SVikas Chaudhary if (rval != QLA_SUCCESS) 31526e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 31536e7b4292SVikas Chaudhary break; 31546e7b4292SVikas Chaudhary case QLA83XX_RDMUX2: 3155b37ca418SVikas Chaudhary if (is_qla8022(ha)) { 31566e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 31576e7b4292SVikas Chaudhary break; 31586e7b4292SVikas Chaudhary } 31596e7b4292SVikas Chaudhary qla83xx_minidump_process_rdmux2(ha, entry_hdr, 31606e7b4292SVikas Chaudhary &data_ptr); 31616e7b4292SVikas Chaudhary break; 31626e7b4292SVikas Chaudhary case QLA83XX_POLLRDMWR: 3163b37ca418SVikas Chaudhary if (is_qla8022(ha)) { 31646e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 31656e7b4292SVikas Chaudhary break; 31666e7b4292SVikas Chaudhary } 31676e7b4292SVikas Chaudhary rval = qla83xx_minidump_process_pollrdmwr(ha, entry_hdr, 31686e7b4292SVikas Chaudhary &data_ptr); 31696e7b4292SVikas Chaudhary if (rval != QLA_SUCCESS) 31706e7b4292SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 31716e7b4292SVikas Chaudhary break; 3172b1829789STej Parkash case QLA8044_RDDFE: 3173b1829789STej Parkash rval = qla4_84xx_minidump_process_rddfe(ha, entry_hdr, 3174b1829789STej Parkash &data_ptr); 3175b1829789STej Parkash if (rval != QLA_SUCCESS) 3176b1829789STej Parkash qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3177b1829789STej Parkash break; 3178b1829789STej Parkash case QLA8044_RDMDIO: 3179b1829789STej Parkash rval = qla4_84xx_minidump_process_rdmdio(ha, entry_hdr, 3180b1829789STej Parkash &data_ptr); 3181b1829789STej Parkash if (rval != QLA_SUCCESS) 3182b1829789STej Parkash qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3183b1829789STej Parkash break; 3184b1829789STej Parkash case QLA8044_POLLWR: 3185b1829789STej Parkash rval = qla4_84xx_minidump_process_pollwr(ha, entry_hdr, 3186b1829789STej Parkash &data_ptr); 3187b1829789STej Parkash if (rval != QLA_SUCCESS) 3188b1829789STej Parkash qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3189b1829789STej Parkash break; 3190de8c72daSVikas Chaudhary case QLA8XXX_RDNOP: 3191068237c8STej Parkash default: 31925e9bcec7SVikas Chaudhary qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i); 3193068237c8STej Parkash break; 3194068237c8STej Parkash } 3195068237c8STej Parkash 31964812d070SSantosh Vernekar data_collected = (uint8_t *)data_ptr - (uint8_t *)ha->fw_dump; 3197068237c8STej Parkash skip_nxt_entry: 3198068237c8STej Parkash /* next entry in the template */ 31997664a1fdSVikas Chaudhary entry_hdr = (struct qla8xxx_minidump_entry_hdr *) 3200068237c8STej Parkash (((uint8_t *)entry_hdr) + 3201068237c8STej Parkash entry_hdr->entry_size); 3202068237c8STej Parkash } 3203068237c8STej Parkash 320458e2bbe9STej Parkash if ((data_collected + ha->fw_dump_skip_size) != ha->fw_dump_size) { 3205068237c8STej Parkash ql4_printk(KERN_INFO, ha, 3206068237c8STej Parkash "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n", 3207068237c8STej Parkash data_collected, ha->fw_dump_size); 320835a9c2abSVikas Chaudhary rval = QLA_ERROR; 3209068237c8STej Parkash goto md_failed; 3210068237c8STej Parkash } 3211068237c8STej Parkash 3212068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n", 3213068237c8STej Parkash __func__, i)); 3214068237c8STej Parkash md_failed: 3215068237c8STej Parkash return rval; 3216068237c8STej Parkash } 3217068237c8STej Parkash 3218068237c8STej Parkash /** 3219068237c8STej Parkash * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready. 3220068237c8STej Parkash * @ha: pointer to adapter structure 3221068237c8STej Parkash **/ 3222068237c8STej Parkash static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code) 3223068237c8STej Parkash { 3224068237c8STej Parkash char event_string[40]; 3225068237c8STej Parkash char *envp[] = { event_string, NULL }; 3226068237c8STej Parkash 3227068237c8STej Parkash switch (code) { 3228068237c8STej Parkash case QL4_UEVENT_CODE_FW_DUMP: 3229068237c8STej Parkash snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 3230068237c8STej Parkash ha->host_no); 3231068237c8STej Parkash break; 3232068237c8STej Parkash default: 3233068237c8STej Parkash /*do nothing*/ 3234068237c8STej Parkash break; 3235068237c8STej Parkash } 3236068237c8STej Parkash 3237068237c8STej Parkash kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp); 3238068237c8STej Parkash } 3239068237c8STej Parkash 32406e7b4292SVikas Chaudhary void qla4_8xxx_get_minidump(struct scsi_qla_host *ha) 3241aec07caeSVikas Chaudhary { 3242aec07caeSVikas Chaudhary if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) && 3243aec07caeSVikas Chaudhary !test_bit(AF_82XX_FW_DUMPED, &ha->flags)) { 3244aec07caeSVikas Chaudhary if (!qla4_8xxx_collect_md_data(ha)) { 3245aec07caeSVikas Chaudhary qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP); 3246aec07caeSVikas Chaudhary set_bit(AF_82XX_FW_DUMPED, &ha->flags); 3247aec07caeSVikas Chaudhary } else { 3248aec07caeSVikas Chaudhary ql4_printk(KERN_INFO, ha, "%s: Unable to collect minidump\n", 3249aec07caeSVikas Chaudhary __func__); 3250aec07caeSVikas Chaudhary } 3251aec07caeSVikas Chaudhary } 3252aec07caeSVikas Chaudhary } 3253aec07caeSVikas Chaudhary 3254f4f5df23SVikas Chaudhary /** 3255f4f5df23SVikas Chaudhary * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw 3256f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 3257f4f5df23SVikas Chaudhary * 3258f4f5df23SVikas Chaudhary * Note: IDC lock must be held upon entry 3259f4f5df23SVikas Chaudhary **/ 32606e7b4292SVikas Chaudhary int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) 3261f4f5df23SVikas Chaudhary { 3262b25ee66fSShyam Sundar int rval = QLA_ERROR; 326332436aaaSVikas Chaudhary int i; 326480645dc0SVikas Chaudhary uint32_t old_count, count; 32654ebbb5cfSVikas Chaudhary int need_reset = 0; 3266f4f5df23SVikas Chaudhary 326733693c7aSVikas Chaudhary need_reset = ha->isp_ops->need_reset(ha); 3268b25ee66fSShyam Sundar 3269b25ee66fSShyam Sundar if (need_reset) { 3270b25ee66fSShyam Sundar /* We are trying to perform a recovery here. */ 32714ebbb5cfSVikas Chaudhary if (test_bit(AF_FW_RECOVERY, &ha->flags)) 327233693c7aSVikas Chaudhary ha->isp_ops->rom_lock_recovery(ha); 3273b25ee66fSShyam Sundar } else { 32744ebbb5cfSVikas Chaudhary old_count = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER); 32754ebbb5cfSVikas Chaudhary for (i = 0; i < 10; i++) { 32764ebbb5cfSVikas Chaudhary msleep(200); 32774ebbb5cfSVikas Chaudhary count = qla4_8xxx_rd_direct(ha, 32784ebbb5cfSVikas Chaudhary QLA8XXX_PEG_ALIVE_COUNTER); 32794ebbb5cfSVikas Chaudhary if (count != old_count) { 3280b25ee66fSShyam Sundar rval = QLA_SUCCESS; 3281f4f5df23SVikas Chaudhary goto dev_ready; 3282f4f5df23SVikas Chaudhary } 3283b25ee66fSShyam Sundar } 32844ebbb5cfSVikas Chaudhary ha->isp_ops->rom_lock_recovery(ha); 32854ebbb5cfSVikas Chaudhary } 3286f4f5df23SVikas Chaudhary 3287f4f5df23SVikas Chaudhary /* set to DEV_INITIALIZING */ 3288f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 328933693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 329033693c7aSVikas Chaudhary QLA8XXX_DEV_INITIALIZING); 3291f4f5df23SVikas Chaudhary 329233693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 32936e7b4292SVikas Chaudhary 32946e7b4292SVikas Chaudhary if (is_qla8022(ha)) 3295aec07caeSVikas Chaudhary qla4_8xxx_get_minidump(ha); 32966e7b4292SVikas Chaudhary 329733693c7aSVikas Chaudhary rval = ha->isp_ops->restart_firmware(ha); 329833693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3299f4f5df23SVikas Chaudhary 3300f4f5df23SVikas Chaudhary if (rval != QLA_SUCCESS) { 3301f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 3302f4f5df23SVikas Chaudhary qla4_8xxx_clear_drv_active(ha); 330333693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 330433693c7aSVikas Chaudhary QLA8XXX_DEV_FAILED); 3305f4f5df23SVikas Chaudhary return rval; 3306f4f5df23SVikas Chaudhary } 3307f4f5df23SVikas Chaudhary 3308f4f5df23SVikas Chaudhary dev_ready: 3309f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 331033693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, QLA8XXX_DEV_READY); 3311f4f5df23SVikas Chaudhary 3312b25ee66fSShyam Sundar return rval; 3313f4f5df23SVikas Chaudhary } 3314f4f5df23SVikas Chaudhary 3315f4f5df23SVikas Chaudhary /** 3316f8086f4fSVikas Chaudhary * qla4_82xx_need_reset_handler - Code to start reset sequence 3317f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 3318f4f5df23SVikas Chaudhary * 3319f4f5df23SVikas Chaudhary * Note: IDC lock must be held upon entry 3320f4f5df23SVikas Chaudhary **/ 3321f4f5df23SVikas Chaudhary static void 3322f8086f4fSVikas Chaudhary qla4_82xx_need_reset_handler(struct scsi_qla_host *ha) 3323f4f5df23SVikas Chaudhary { 3324f4f5df23SVikas Chaudhary uint32_t dev_state, drv_state, drv_active; 3325068237c8STej Parkash uint32_t active_mask = 0xFFFFFFFF; 3326f4f5df23SVikas Chaudhary unsigned long reset_timeout; 3327f4f5df23SVikas Chaudhary 3328f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 3329f4f5df23SVikas Chaudhary "Performing ISP error recovery\n"); 3330f4f5df23SVikas Chaudhary 3331f4f5df23SVikas Chaudhary if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { 3332f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 3333f4f5df23SVikas Chaudhary ha->isp_ops->disable_intrs(ha); 3334f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 3335f4f5df23SVikas Chaudhary } 3336f4f5df23SVikas Chaudhary 3337de8c72daSVikas Chaudhary if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { 3338068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, 3339068237c8STej Parkash "%s(%ld): reset acknowledged\n", 3340068237c8STej Parkash __func__, ha->host_no)); 3341f4f5df23SVikas Chaudhary qla4_8xxx_set_rst_ready(ha); 3342068237c8STej Parkash } else { 3343068237c8STej Parkash active_mask = (~(1 << (ha->func_num * 4))); 3344068237c8STej Parkash } 3345f4f5df23SVikas Chaudhary 3346f4f5df23SVikas Chaudhary /* wait for 10 seconds for reset ack from all functions */ 3347f4f5df23SVikas Chaudhary reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 3348f4f5df23SVikas Chaudhary 3349f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3350f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3351f4f5df23SVikas Chaudhary 3352f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, 3353f4f5df23SVikas Chaudhary "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 3354f4f5df23SVikas Chaudhary __func__, ha->host_no, drv_state, drv_active); 3355f4f5df23SVikas Chaudhary 3356068237c8STej Parkash while (drv_state != (drv_active & active_mask)) { 3357f4f5df23SVikas Chaudhary if (time_after_eq(jiffies, reset_timeout)) { 3358068237c8STej Parkash ql4_printk(KERN_INFO, ha, 3359068237c8STej Parkash "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", 3360068237c8STej Parkash DRIVER_NAME, drv_state, drv_active); 3361f4f5df23SVikas Chaudhary break; 3362f4f5df23SVikas Chaudhary } 3363f4f5df23SVikas Chaudhary 3364068237c8STej Parkash /* 3365068237c8STej Parkash * When reset_owner times out, check which functions 3366068237c8STej Parkash * acked/did not ack 3367068237c8STej Parkash */ 3368de8c72daSVikas Chaudhary if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { 3369068237c8STej Parkash ql4_printk(KERN_INFO, ha, 3370068237c8STej Parkash "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 3371068237c8STej Parkash __func__, ha->host_no, drv_state, 3372068237c8STej Parkash drv_active); 3373068237c8STej Parkash } 3374f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 3375f4f5df23SVikas Chaudhary msleep(1000); 3376f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 3377f4f5df23SVikas Chaudhary 3378f8086f4fSVikas Chaudhary drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 3379f8086f4fSVikas Chaudhary drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 3380f4f5df23SVikas Chaudhary } 3381f4f5df23SVikas Chaudhary 3382068237c8STej Parkash /* Clear RESET OWNER as we are not going to use it any further */ 3383de8c72daSVikas Chaudhary clear_bit(AF_8XXX_RST_OWNER, &ha->flags); 3384068237c8STej Parkash 3385f8086f4fSVikas Chaudhary dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 3386068237c8STej Parkash ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state, 3387f4f5df23SVikas Chaudhary dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 3388f4f5df23SVikas Chaudhary 3389f4f5df23SVikas Chaudhary /* Force to DEV_COLD unless someone else is starting a reset */ 3390de8c72daSVikas Chaudhary if (dev_state != QLA8XXX_DEV_INITIALIZING) { 3391f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 3392de8c72daSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD); 3393068237c8STej Parkash qla4_8xxx_set_rst_ready(ha); 3394f4f5df23SVikas Chaudhary } 3395f4f5df23SVikas Chaudhary } 3396f4f5df23SVikas Chaudhary 3397f4f5df23SVikas Chaudhary /** 3398f4f5df23SVikas Chaudhary * qla4_8xxx_need_qsnt_handler - Code to start qsnt 3399f4f5df23SVikas Chaudhary * @ha: pointer to adapter structure 3400f4f5df23SVikas Chaudhary **/ 3401f4f5df23SVikas Chaudhary void 3402f4f5df23SVikas Chaudhary qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 3403f4f5df23SVikas Chaudhary { 340433693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3405f4f5df23SVikas Chaudhary qla4_8xxx_set_qsnt_ready(ha); 340633693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3407f4f5df23SVikas Chaudhary } 3408f4f5df23SVikas Chaudhary 340983dbdf6fSVikas Chaudhary static void qla4_82xx_set_idc_ver(struct scsi_qla_host *ha) 341083dbdf6fSVikas Chaudhary { 341183dbdf6fSVikas Chaudhary int idc_ver; 341283dbdf6fSVikas Chaudhary uint32_t drv_active; 341383dbdf6fSVikas Chaudhary 341483dbdf6fSVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 341583dbdf6fSVikas Chaudhary if (drv_active == (1 << (ha->func_num * 4))) { 341683dbdf6fSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, 341783dbdf6fSVikas Chaudhary QLA82XX_IDC_VERSION); 341883dbdf6fSVikas Chaudhary ql4_printk(KERN_INFO, ha, 341983dbdf6fSVikas Chaudhary "%s: IDC version updated to %d\n", __func__, 342083dbdf6fSVikas Chaudhary QLA82XX_IDC_VERSION); 342183dbdf6fSVikas Chaudhary } else { 342283dbdf6fSVikas Chaudhary idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 342383dbdf6fSVikas Chaudhary if (QLA82XX_IDC_VERSION != idc_ver) { 342483dbdf6fSVikas Chaudhary ql4_printk(KERN_INFO, ha, 342583dbdf6fSVikas Chaudhary "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", 342683dbdf6fSVikas Chaudhary __func__, QLA82XX_IDC_VERSION, idc_ver); 342783dbdf6fSVikas Chaudhary } 342883dbdf6fSVikas Chaudhary } 342983dbdf6fSVikas Chaudhary } 343083dbdf6fSVikas Chaudhary 34316e7b4292SVikas Chaudhary static int qla4_83xx_set_idc_ver(struct scsi_qla_host *ha) 343283dbdf6fSVikas Chaudhary { 34336e7b4292SVikas Chaudhary int idc_ver; 34346e7b4292SVikas Chaudhary uint32_t drv_active; 34356e7b4292SVikas Chaudhary int rval = QLA_SUCCESS; 34366e7b4292SVikas Chaudhary 34376e7b4292SVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 34386e7b4292SVikas Chaudhary if (drv_active == (1 << ha->func_num)) { 34396e7b4292SVikas Chaudhary idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 34406e7b4292SVikas Chaudhary idc_ver &= (~0xFF); 34416e7b4292SVikas Chaudhary idc_ver |= QLA83XX_IDC_VER_MAJ_VALUE; 34426e7b4292SVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION, idc_ver); 34436e7b4292SVikas Chaudhary ql4_printk(KERN_INFO, ha, 34446e7b4292SVikas Chaudhary "%s: IDC version updated to %d\n", __func__, 3445ecca5120SVikas Chaudhary idc_ver); 34466e7b4292SVikas Chaudhary } else { 34476e7b4292SVikas Chaudhary idc_ver = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_IDC_VERSION); 34486e7b4292SVikas Chaudhary idc_ver &= 0xFF; 34496e7b4292SVikas Chaudhary if (QLA83XX_IDC_VER_MAJ_VALUE != idc_ver) { 34506e7b4292SVikas Chaudhary ql4_printk(KERN_INFO, ha, 34516e7b4292SVikas Chaudhary "%s: qla4xxx driver IDC version %d is not compatible with IDC version %d of other drivers!\n", 34526e7b4292SVikas Chaudhary __func__, QLA83XX_IDC_VER_MAJ_VALUE, 34536e7b4292SVikas Chaudhary idc_ver); 34546e7b4292SVikas Chaudhary rval = QLA_ERROR; 34556e7b4292SVikas Chaudhary goto exit_set_idc_ver; 34566e7b4292SVikas Chaudhary } 34576e7b4292SVikas Chaudhary } 34586e7b4292SVikas Chaudhary 34596e7b4292SVikas Chaudhary /* Update IDC_MINOR_VERSION */ 34606e7b4292SVikas Chaudhary idc_ver = qla4_83xx_rd_reg(ha, QLA83XX_CRB_IDC_VER_MINOR); 34616e7b4292SVikas Chaudhary idc_ver &= ~(0x03 << (ha->func_num * 2)); 34626e7b4292SVikas Chaudhary idc_ver |= (QLA83XX_IDC_VER_MIN_VALUE << (ha->func_num * 2)); 34636e7b4292SVikas Chaudhary qla4_83xx_wr_reg(ha, QLA83XX_CRB_IDC_VER_MINOR, idc_ver); 34646e7b4292SVikas Chaudhary 34656e7b4292SVikas Chaudhary exit_set_idc_ver: 34666e7b4292SVikas Chaudhary return rval; 34676e7b4292SVikas Chaudhary } 34686e7b4292SVikas Chaudhary 346939c95826SVikas Chaudhary int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha) 34706e7b4292SVikas Chaudhary { 34716e7b4292SVikas Chaudhary uint32_t drv_active; 34726e7b4292SVikas Chaudhary int rval = QLA_SUCCESS; 34736e7b4292SVikas Chaudhary 34746e7b4292SVikas Chaudhary if (test_bit(AF_INIT_DONE, &ha->flags)) 34756e7b4292SVikas Chaudhary goto exit_update_idc_reg; 34766e7b4292SVikas Chaudhary 347783dbdf6fSVikas Chaudhary ha->isp_ops->idc_lock(ha); 347883dbdf6fSVikas Chaudhary qla4_8xxx_set_drv_active(ha); 34796e7b4292SVikas Chaudhary 34806e7b4292SVikas Chaudhary /* 34816e7b4292SVikas Chaudhary * If we are the first driver to load and 34826e7b4292SVikas Chaudhary * ql4xdontresethba is not set, clear IDC_CTRL BIT0. 34836e7b4292SVikas Chaudhary */ 3484b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) { 34856e7b4292SVikas Chaudhary drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); 34866e7b4292SVikas Chaudhary if ((drv_active == (1 << ha->func_num)) && !ql4xdontresethba) 34876e7b4292SVikas Chaudhary qla4_83xx_clear_idc_dontreset(ha); 348883dbdf6fSVikas Chaudhary } 34896e7b4292SVikas Chaudhary 34906e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 34916e7b4292SVikas Chaudhary qla4_82xx_set_idc_ver(ha); 3492b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 34936e7b4292SVikas Chaudhary rval = qla4_83xx_set_idc_ver(ha); 34946e7b4292SVikas Chaudhary if (rval == QLA_ERROR) 34956e7b4292SVikas Chaudhary qla4_8xxx_clear_drv_active(ha); 34966e7b4292SVikas Chaudhary } 34976e7b4292SVikas Chaudhary 34986e7b4292SVikas Chaudhary ha->isp_ops->idc_unlock(ha); 34996e7b4292SVikas Chaudhary 35006e7b4292SVikas Chaudhary exit_update_idc_reg: 35016e7b4292SVikas Chaudhary return rval; 3502f4f5df23SVikas Chaudhary } 3503f4f5df23SVikas Chaudhary 3504f4f5df23SVikas Chaudhary /** 3505f4f5df23SVikas Chaudhary * qla4_8xxx_device_state_handler - Adapter state machine 3506f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 3507f4f5df23SVikas Chaudhary * 3508f4f5df23SVikas Chaudhary * Note: IDC lock must be UNLOCKED upon entry 3509f4f5df23SVikas Chaudhary **/ 3510f4f5df23SVikas Chaudhary int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) 3511f4f5df23SVikas Chaudhary { 3512f4f5df23SVikas Chaudhary uint32_t dev_state; 3513f4f5df23SVikas Chaudhary int rval = QLA_SUCCESS; 3514f4f5df23SVikas Chaudhary unsigned long dev_init_timeout; 3515f4f5df23SVikas Chaudhary 35166e7b4292SVikas Chaudhary rval = qla4_8xxx_update_idc_reg(ha); 35176e7b4292SVikas Chaudhary if (rval == QLA_ERROR) 35186e7b4292SVikas Chaudhary goto exit_state_handler; 3519f4f5df23SVikas Chaudhary 352033693c7aSVikas Chaudhary dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); 3521068237c8STej Parkash DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 3522068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 3523068237c8STej Parkash qdev_state[dev_state] : "Unknown")); 3524f4f5df23SVikas Chaudhary 3525f4f5df23SVikas Chaudhary /* wait for 30 seconds for device to go ready */ 3526f4f5df23SVikas Chaudhary dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 3527f4f5df23SVikas Chaudhary 352833693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3529e3f37d16SNilesh Javali while (1) { 3530f4f5df23SVikas Chaudhary 3531f4f5df23SVikas Chaudhary if (time_after_eq(jiffies, dev_init_timeout)) { 3532068237c8STej Parkash ql4_printk(KERN_WARNING, ha, 3533068237c8STej Parkash "%s: Device Init Failed 0x%x = %s\n", 3534068237c8STej Parkash DRIVER_NAME, 3535068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 3536068237c8STej Parkash qdev_state[dev_state] : "Unknown"); 353733693c7aSVikas Chaudhary qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, 3538de8c72daSVikas Chaudhary QLA8XXX_DEV_FAILED); 3539f4f5df23SVikas Chaudhary } 3540f4f5df23SVikas Chaudhary 354133693c7aSVikas Chaudhary dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); 3542068237c8STej Parkash ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", 3543068237c8STej Parkash dev_state, dev_state < MAX_STATES ? 3544068237c8STej Parkash qdev_state[dev_state] : "Unknown"); 3545f4f5df23SVikas Chaudhary 3546f4f5df23SVikas Chaudhary /* NOTE: Make sure idc unlocked upon exit of switch statement */ 3547f4f5df23SVikas Chaudhary switch (dev_state) { 3548de8c72daSVikas Chaudhary case QLA8XXX_DEV_READY: 3549f4f5df23SVikas Chaudhary goto exit; 3550de8c72daSVikas Chaudhary case QLA8XXX_DEV_COLD: 3551f4f5df23SVikas Chaudhary rval = qla4_8xxx_device_bootstrap(ha); 3552f4f5df23SVikas Chaudhary goto exit; 3553de8c72daSVikas Chaudhary case QLA8XXX_DEV_INITIALIZING: 355433693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3555f4f5df23SVikas Chaudhary msleep(1000); 355633693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3557f4f5df23SVikas Chaudhary break; 3558de8c72daSVikas Chaudhary case QLA8XXX_DEV_NEED_RESET: 35596e7b4292SVikas Chaudhary /* 3560b37ca418SVikas Chaudhary * For ISP8324 and ISP8042, if NEED_RESET is set by any 3561b37ca418SVikas Chaudhary * driver, it should be honored, irrespective of 3562b37ca418SVikas Chaudhary * IDC_CTRL DONTRESET_BIT0 35636e7b4292SVikas Chaudhary */ 3564b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) { 35656e7b4292SVikas Chaudhary qla4_83xx_need_reset_handler(ha); 35666e7b4292SVikas Chaudhary } else if (is_qla8022(ha)) { 3567f4f5df23SVikas Chaudhary if (!ql4xdontresethba) { 3568f8086f4fSVikas Chaudhary qla4_82xx_need_reset_handler(ha); 3569f4f5df23SVikas Chaudhary /* Update timeout value after need 3570f4f5df23SVikas Chaudhary * reset handler */ 3571f4f5df23SVikas Chaudhary dev_init_timeout = jiffies + 3572f4f5df23SVikas Chaudhary (ha->nx_dev_init_timeout * HZ); 35739acf7533SMike Hernandez } else { 357433693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 35759acf7533SMike Hernandez msleep(1000); 357633693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3577f4f5df23SVikas Chaudhary } 3578f4f5df23SVikas Chaudhary } 3579f4f5df23SVikas Chaudhary break; 3580de8c72daSVikas Chaudhary case QLA8XXX_DEV_NEED_QUIESCENT: 3581f4f5df23SVikas Chaudhary /* idc locked/unlocked in handler */ 3582f4f5df23SVikas Chaudhary qla4_8xxx_need_qsnt_handler(ha); 3583e3f37d16SNilesh Javali break; 3584de8c72daSVikas Chaudhary case QLA8XXX_DEV_QUIESCENT: 358533693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3586f4f5df23SVikas Chaudhary msleep(1000); 358733693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3588f4f5df23SVikas Chaudhary break; 3589de8c72daSVikas Chaudhary case QLA8XXX_DEV_FAILED: 359033693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3591f4f5df23SVikas Chaudhary qla4xxx_dead_adapter_cleanup(ha); 3592f4f5df23SVikas Chaudhary rval = QLA_ERROR; 359333693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3594f4f5df23SVikas Chaudhary goto exit; 3595f4f5df23SVikas Chaudhary default: 359633693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 3597f4f5df23SVikas Chaudhary qla4xxx_dead_adapter_cleanup(ha); 3598f4f5df23SVikas Chaudhary rval = QLA_ERROR; 359933693c7aSVikas Chaudhary ha->isp_ops->idc_lock(ha); 3600f4f5df23SVikas Chaudhary goto exit; 3601f4f5df23SVikas Chaudhary } 3602f4f5df23SVikas Chaudhary } 3603f4f5df23SVikas Chaudhary exit: 360433693c7aSVikas Chaudhary ha->isp_ops->idc_unlock(ha); 36056e7b4292SVikas Chaudhary exit_state_handler: 3606f4f5df23SVikas Chaudhary return rval; 3607f4f5df23SVikas Chaudhary } 3608f4f5df23SVikas Chaudhary 3609f4f5df23SVikas Chaudhary int qla4_8xxx_load_risc(struct scsi_qla_host *ha) 3610f4f5df23SVikas Chaudhary { 3611f4f5df23SVikas Chaudhary int retval; 361278764999SSarang Radke 361378764999SSarang Radke /* clear the interrupt */ 3614b37ca418SVikas Chaudhary if (is_qla8032(ha) || is_qla8042(ha)) { 36156e7b4292SVikas Chaudhary writel(0, &ha->qla4_83xx_reg->risc_intr); 36166e7b4292SVikas Chaudhary readl(&ha->qla4_83xx_reg->risc_intr); 36176e7b4292SVikas Chaudhary } else if (is_qla8022(ha)) { 36187664a1fdSVikas Chaudhary writel(0, &ha->qla4_82xx_reg->host_int); 36197664a1fdSVikas Chaudhary readl(&ha->qla4_82xx_reg->host_int); 36206e7b4292SVikas Chaudhary } 362178764999SSarang Radke 3622f4f5df23SVikas Chaudhary retval = qla4_8xxx_device_state_handler(ha); 3623f4f5df23SVikas Chaudhary 36241b3d399cSTej Parkash /* Initialize request and response queues. */ 36251b3d399cSTej Parkash if (retval == QLA_SUCCESS) 36261b3d399cSTej Parkash qla4xxx_init_rings(ha); 36271b3d399cSTej Parkash 3628137257daSPoornima Vonti if (retval == QLA_SUCCESS && !test_bit(AF_IRQ_ATTACHED, &ha->flags)) 3629f4f5df23SVikas Chaudhary retval = qla4xxx_request_irqs(ha); 3630f581a3f7SVikas Chaudhary 3631f4f5df23SVikas Chaudhary return retval; 3632f4f5df23SVikas Chaudhary } 3633f4f5df23SVikas Chaudhary 3634f4f5df23SVikas Chaudhary /*****************************************************************************/ 3635f4f5df23SVikas Chaudhary /* Flash Manipulation Routines */ 3636f4f5df23SVikas Chaudhary /*****************************************************************************/ 3637f4f5df23SVikas Chaudhary 3638f4f5df23SVikas Chaudhary #define OPTROM_BURST_SIZE 0x1000 3639f4f5df23SVikas Chaudhary #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3640f4f5df23SVikas Chaudhary 3641f4f5df23SVikas Chaudhary #define FARX_DATA_FLAG BIT_31 3642f4f5df23SVikas Chaudhary #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 3643f4f5df23SVikas Chaudhary #define FARX_ACCESS_FLASH_DATA 0x7FF00000 3644f4f5df23SVikas Chaudhary 3645f4f5df23SVikas Chaudhary static inline uint32_t 3646f4f5df23SVikas Chaudhary flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 3647f4f5df23SVikas Chaudhary { 3648f4f5df23SVikas Chaudhary return hw->flash_conf_off | faddr; 3649f4f5df23SVikas Chaudhary } 3650f4f5df23SVikas Chaudhary 3651f4f5df23SVikas Chaudhary static inline uint32_t 3652f4f5df23SVikas Chaudhary flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 3653f4f5df23SVikas Chaudhary { 3654f4f5df23SVikas Chaudhary return hw->flash_data_off | faddr; 3655f4f5df23SVikas Chaudhary } 3656f4f5df23SVikas Chaudhary 3657f4f5df23SVikas Chaudhary static uint32_t * 3658f8086f4fSVikas Chaudhary qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, 3659f4f5df23SVikas Chaudhary uint32_t faddr, uint32_t length) 3660f4f5df23SVikas Chaudhary { 3661f4f5df23SVikas Chaudhary uint32_t i; 3662f4f5df23SVikas Chaudhary uint32_t val; 3663f4f5df23SVikas Chaudhary int loops = 0; 3664f8086f4fSVikas Chaudhary while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) { 3665f4f5df23SVikas Chaudhary udelay(100); 3666f4f5df23SVikas Chaudhary cond_resched(); 3667f4f5df23SVikas Chaudhary loops++; 3668f4f5df23SVikas Chaudhary } 3669f4f5df23SVikas Chaudhary if (loops >= 50000) { 3670f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); 3671f4f5df23SVikas Chaudhary return dwptr; 3672f4f5df23SVikas Chaudhary } 3673f4f5df23SVikas Chaudhary 3674f4f5df23SVikas Chaudhary /* Dword reads to flash. */ 3675f4f5df23SVikas Chaudhary for (i = 0; i < length/4; i++, faddr += 4) { 3676f8086f4fSVikas Chaudhary if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) { 3677f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 3678f4f5df23SVikas Chaudhary "Do ROM fast read failed\n"); 3679f4f5df23SVikas Chaudhary goto done_read; 3680f4f5df23SVikas Chaudhary } 3681f4f5df23SVikas Chaudhary dwptr[i] = __constant_cpu_to_le32(val); 3682f4f5df23SVikas Chaudhary } 3683f4f5df23SVikas Chaudhary 3684f4f5df23SVikas Chaudhary done_read: 3685f8086f4fSVikas Chaudhary qla4_82xx_rom_unlock(ha); 3686f4f5df23SVikas Chaudhary return dwptr; 3687f4f5df23SVikas Chaudhary } 3688f4f5df23SVikas Chaudhary 3689f4f5df23SVikas Chaudhary /** 3690f4f5df23SVikas Chaudhary * Address and length are byte address 3691f4f5df23SVikas Chaudhary **/ 3692f4f5df23SVikas Chaudhary static uint8_t * 3693f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 3694f4f5df23SVikas Chaudhary uint32_t offset, uint32_t length) 3695f4f5df23SVikas Chaudhary { 3696f8086f4fSVikas Chaudhary qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length); 3697f4f5df23SVikas Chaudhary return buf; 3698f4f5df23SVikas Chaudhary } 3699f4f5df23SVikas Chaudhary 3700f4f5df23SVikas Chaudhary static int 3701f4f5df23SVikas Chaudhary qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) 3702f4f5df23SVikas Chaudhary { 3703f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "DEF", "PCI" }; 3704f4f5df23SVikas Chaudhary 3705f4f5df23SVikas Chaudhary /* 3706f4f5df23SVikas Chaudhary * FLT-location structure resides after the last PCI region. 3707f4f5df23SVikas Chaudhary */ 3708f4f5df23SVikas Chaudhary 3709f4f5df23SVikas Chaudhary /* Begin with sane defaults. */ 3710f4f5df23SVikas Chaudhary loc = locations[0]; 3711f4f5df23SVikas Chaudhary *start = FA_FLASH_LAYOUT_ADDR_82; 3712f4f5df23SVikas Chaudhary 3713f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 3714f4f5df23SVikas Chaudhary return QLA_SUCCESS; 3715f4f5df23SVikas Chaudhary } 3716f4f5df23SVikas Chaudhary 3717f4f5df23SVikas Chaudhary static void 3718f4f5df23SVikas Chaudhary qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) 3719f4f5df23SVikas Chaudhary { 3720f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "DEF", "FLT" }; 3721f4f5df23SVikas Chaudhary uint16_t *wptr; 3722f4f5df23SVikas Chaudhary uint16_t cnt, chksum; 37236e7b4292SVikas Chaudhary uint32_t start, status; 3724f4f5df23SVikas Chaudhary struct qla_flt_header *flt; 3725f4f5df23SVikas Chaudhary struct qla_flt_region *region; 3726f4f5df23SVikas Chaudhary struct ql82xx_hw_data *hw = &ha->hw; 3727f4f5df23SVikas Chaudhary 3728f4f5df23SVikas Chaudhary hw->flt_region_flt = flt_addr; 3729f4f5df23SVikas Chaudhary wptr = (uint16_t *)ha->request_ring; 3730f4f5df23SVikas Chaudhary flt = (struct qla_flt_header *)ha->request_ring; 3731f4f5df23SVikas Chaudhary region = (struct qla_flt_region *)&flt[1]; 37326e7b4292SVikas Chaudhary 37336e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 3734f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3735f4f5df23SVikas Chaudhary flt_addr << 2, OPTROM_BURST_SIZE); 3736b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 37376e7b4292SVikas Chaudhary status = qla4_83xx_flash_read_u32(ha, flt_addr << 2, 37386e7b4292SVikas Chaudhary (uint8_t *)ha->request_ring, 37396e7b4292SVikas Chaudhary 0x400); 37406e7b4292SVikas Chaudhary if (status != QLA_SUCCESS) 37416e7b4292SVikas Chaudhary goto no_flash_data; 37426e7b4292SVikas Chaudhary } 37436e7b4292SVikas Chaudhary 3744f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le16(0xffff)) 3745f4f5df23SVikas Chaudhary goto no_flash_data; 3746f4f5df23SVikas Chaudhary if (flt->version != __constant_cpu_to_le16(1)) { 3747f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " 3748f4f5df23SVikas Chaudhary "version=0x%x length=0x%x checksum=0x%x.\n", 3749f4f5df23SVikas Chaudhary le16_to_cpu(flt->version), le16_to_cpu(flt->length), 3750f4f5df23SVikas Chaudhary le16_to_cpu(flt->checksum))); 3751f4f5df23SVikas Chaudhary goto no_flash_data; 3752f4f5df23SVikas Chaudhary } 3753f4f5df23SVikas Chaudhary 3754f4f5df23SVikas Chaudhary cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 3755f4f5df23SVikas Chaudhary for (chksum = 0; cnt; cnt--) 3756f4f5df23SVikas Chaudhary chksum += le16_to_cpu(*wptr++); 3757f4f5df23SVikas Chaudhary if (chksum) { 3758f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 3759f4f5df23SVikas Chaudhary "version=0x%x length=0x%x checksum=0x%x.\n", 3760f4f5df23SVikas Chaudhary le16_to_cpu(flt->version), le16_to_cpu(flt->length), 3761f4f5df23SVikas Chaudhary chksum)); 3762f4f5df23SVikas Chaudhary goto no_flash_data; 3763f4f5df23SVikas Chaudhary } 3764f4f5df23SVikas Chaudhary 3765f4f5df23SVikas Chaudhary loc = locations[1]; 3766f4f5df23SVikas Chaudhary cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 3767f4f5df23SVikas Chaudhary for ( ; cnt; cnt--, region++) { 3768f4f5df23SVikas Chaudhary /* Store addresses as DWORD offsets. */ 3769f4f5df23SVikas Chaudhary start = le32_to_cpu(region->start) >> 2; 3770f4f5df23SVikas Chaudhary 3771f4f5df23SVikas Chaudhary DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 3772f4f5df23SVikas Chaudhary "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 3773f4f5df23SVikas Chaudhary le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 3774f4f5df23SVikas Chaudhary 3775f4f5df23SVikas Chaudhary switch (le32_to_cpu(region->code) & 0xff) { 3776f4f5df23SVikas Chaudhary case FLT_REG_FDT: 3777f4f5df23SVikas Chaudhary hw->flt_region_fdt = start; 3778f4f5df23SVikas Chaudhary break; 3779f4f5df23SVikas Chaudhary case FLT_REG_BOOT_CODE_82: 3780f4f5df23SVikas Chaudhary hw->flt_region_boot = start; 3781f4f5df23SVikas Chaudhary break; 3782f4f5df23SVikas Chaudhary case FLT_REG_FW_82: 378393823956SNilesh Javali case FLT_REG_FW_82_1: 3784f4f5df23SVikas Chaudhary hw->flt_region_fw = start; 3785f4f5df23SVikas Chaudhary break; 3786f4f5df23SVikas Chaudhary case FLT_REG_BOOTLOAD_82: 3787f4f5df23SVikas Chaudhary hw->flt_region_bootload = start; 3788f4f5df23SVikas Chaudhary break; 37892a991c21SManish Rangankar case FLT_REG_ISCSI_PARAM: 37902a991c21SManish Rangankar hw->flt_iscsi_param = start; 37912a991c21SManish Rangankar break; 37924549415aSLalit Chandivade case FLT_REG_ISCSI_CHAP: 37934549415aSLalit Chandivade hw->flt_region_chap = start; 37944549415aSLalit Chandivade hw->flt_chap_size = le32_to_cpu(region->size); 37954549415aSLalit Chandivade break; 37961e9e2be3SAdheer Chandravanshi case FLT_REG_ISCSI_DDB: 37971e9e2be3SAdheer Chandravanshi hw->flt_region_ddb = start; 37981e9e2be3SAdheer Chandravanshi hw->flt_ddb_size = le32_to_cpu(region->size); 37991e9e2be3SAdheer Chandravanshi break; 3800f4f5df23SVikas Chaudhary } 3801f4f5df23SVikas Chaudhary } 3802f4f5df23SVikas Chaudhary goto done; 3803f4f5df23SVikas Chaudhary 3804f4f5df23SVikas Chaudhary no_flash_data: 3805f4f5df23SVikas Chaudhary /* Use hardcoded defaults. */ 3806f4f5df23SVikas Chaudhary loc = locations[0]; 3807f4f5df23SVikas Chaudhary 3808f4f5df23SVikas Chaudhary hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; 3809f4f5df23SVikas Chaudhary hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; 3810f4f5df23SVikas Chaudhary hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; 3811f4f5df23SVikas Chaudhary hw->flt_region_fw = FA_RISC_CODE_ADDR_82; 38129a16f65bSVikas Chaudhary hw->flt_region_chap = FA_FLASH_ISCSI_CHAP >> 2; 38134549415aSLalit Chandivade hw->flt_chap_size = FA_FLASH_CHAP_SIZE; 38141e9e2be3SAdheer Chandravanshi hw->flt_region_ddb = FA_FLASH_ISCSI_DDB >> 2; 38151e9e2be3SAdheer Chandravanshi hw->flt_ddb_size = FA_FLASH_DDB_SIZE; 38164549415aSLalit Chandivade 3817f4f5df23SVikas Chaudhary done: 38189a16f65bSVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 38191e9e2be3SAdheer Chandravanshi "FLT[%s]: flt=0x%x fdt=0x%x boot=0x%x bootload=0x%x fw=0x%x chap=0x%x chap_size=0x%x ddb=0x%x ddb_size=0x%x\n", 38209a16f65bSVikas Chaudhary loc, hw->flt_region_flt, hw->flt_region_fdt, 38219a16f65bSVikas Chaudhary hw->flt_region_boot, hw->flt_region_bootload, 38221e9e2be3SAdheer Chandravanshi hw->flt_region_fw, hw->flt_region_chap, 38231e9e2be3SAdheer Chandravanshi hw->flt_chap_size, hw->flt_region_ddb, 38241e9e2be3SAdheer Chandravanshi hw->flt_ddb_size)); 3825f4f5df23SVikas Chaudhary } 3826f4f5df23SVikas Chaudhary 3827f4f5df23SVikas Chaudhary static void 3828f8086f4fSVikas Chaudhary qla4_82xx_get_fdt_info(struct scsi_qla_host *ha) 3829f4f5df23SVikas Chaudhary { 3830f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_4K 0x1000 3831f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_32K 0x8000 3832f4f5df23SVikas Chaudhary #define FLASH_BLK_SIZE_64K 0x10000 3833f4f5df23SVikas Chaudhary const char *loc, *locations[] = { "MID", "FDT" }; 3834f4f5df23SVikas Chaudhary uint16_t cnt, chksum; 3835f4f5df23SVikas Chaudhary uint16_t *wptr; 3836f4f5df23SVikas Chaudhary struct qla_fdt_layout *fdt; 38373c3e2108SVikas Chaudhary uint16_t mid = 0; 38383c3e2108SVikas Chaudhary uint16_t fid = 0; 3839f4f5df23SVikas Chaudhary struct ql82xx_hw_data *hw = &ha->hw; 3840f4f5df23SVikas Chaudhary 3841f4f5df23SVikas Chaudhary hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3842f4f5df23SVikas Chaudhary hw->flash_data_off = FARX_ACCESS_FLASH_DATA; 3843f4f5df23SVikas Chaudhary 3844f4f5df23SVikas Chaudhary wptr = (uint16_t *)ha->request_ring; 3845f4f5df23SVikas Chaudhary fdt = (struct qla_fdt_layout *)ha->request_ring; 3846f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3847f4f5df23SVikas Chaudhary hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); 3848f4f5df23SVikas Chaudhary 3849f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le16(0xffff)) 3850f4f5df23SVikas Chaudhary goto no_flash_data; 3851f4f5df23SVikas Chaudhary 3852f4f5df23SVikas Chaudhary if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 3853f4f5df23SVikas Chaudhary fdt->sig[3] != 'D') 3854f4f5df23SVikas Chaudhary goto no_flash_data; 3855f4f5df23SVikas Chaudhary 3856f4f5df23SVikas Chaudhary for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 3857f4f5df23SVikas Chaudhary cnt++) 3858f4f5df23SVikas Chaudhary chksum += le16_to_cpu(*wptr++); 3859f4f5df23SVikas Chaudhary 3860f4f5df23SVikas Chaudhary if (chksum) { 3861f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 3862f4f5df23SVikas Chaudhary "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 3863f4f5df23SVikas Chaudhary le16_to_cpu(fdt->version))); 3864f4f5df23SVikas Chaudhary goto no_flash_data; 3865f4f5df23SVikas Chaudhary } 3866f4f5df23SVikas Chaudhary 3867f4f5df23SVikas Chaudhary loc = locations[1]; 3868f4f5df23SVikas Chaudhary mid = le16_to_cpu(fdt->man_id); 3869f4f5df23SVikas Chaudhary fid = le16_to_cpu(fdt->id); 3870f4f5df23SVikas Chaudhary hw->fdt_wrt_disable = fdt->wrt_disable_bits; 3871f4f5df23SVikas Chaudhary hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); 3872f4f5df23SVikas Chaudhary hw->fdt_block_size = le32_to_cpu(fdt->block_size); 3873f4f5df23SVikas Chaudhary 3874f4f5df23SVikas Chaudhary if (fdt->unprotect_sec_cmd) { 3875f4f5df23SVikas Chaudhary hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | 3876f4f5df23SVikas Chaudhary fdt->unprotect_sec_cmd); 3877f4f5df23SVikas Chaudhary hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 3878f4f5df23SVikas Chaudhary flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : 3879f4f5df23SVikas Chaudhary flash_conf_addr(hw, 0x0336); 3880f4f5df23SVikas Chaudhary } 3881f4f5df23SVikas Chaudhary goto done; 3882f4f5df23SVikas Chaudhary 3883f4f5df23SVikas Chaudhary no_flash_data: 3884f4f5df23SVikas Chaudhary loc = locations[0]; 3885f4f5df23SVikas Chaudhary hw->fdt_block_size = FLASH_BLK_SIZE_64K; 3886f4f5df23SVikas Chaudhary done: 3887f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 3888f4f5df23SVikas Chaudhary "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 3889f4f5df23SVikas Chaudhary hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, 3890f4f5df23SVikas Chaudhary hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, 3891f4f5df23SVikas Chaudhary hw->fdt_block_size)); 3892f4f5df23SVikas Chaudhary } 3893f4f5df23SVikas Chaudhary 3894f4f5df23SVikas Chaudhary static void 3895f8086f4fSVikas Chaudhary qla4_82xx_get_idc_param(struct scsi_qla_host *ha) 3896f4f5df23SVikas Chaudhary { 3897f4f5df23SVikas Chaudhary #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 3898f4f5df23SVikas Chaudhary uint32_t *wptr; 3899f4f5df23SVikas Chaudhary 3900f4f5df23SVikas Chaudhary if (!is_qla8022(ha)) 3901f4f5df23SVikas Chaudhary return; 3902f4f5df23SVikas Chaudhary wptr = (uint32_t *)ha->request_ring; 3903f8086f4fSVikas Chaudhary qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 3904f4f5df23SVikas Chaudhary QLA82XX_IDC_PARAM_ADDR , 8); 3905f4f5df23SVikas Chaudhary 3906f4f5df23SVikas Chaudhary if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 3907f4f5df23SVikas Chaudhary ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; 3908f4f5df23SVikas Chaudhary ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; 3909f4f5df23SVikas Chaudhary } else { 3910f4f5df23SVikas Chaudhary ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 3911f4f5df23SVikas Chaudhary ha->nx_reset_timeout = le32_to_cpu(*wptr); 3912f4f5df23SVikas Chaudhary } 3913f4f5df23SVikas Chaudhary 3914f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_DEBUG, ha, 3915f4f5df23SVikas Chaudhary "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); 3916f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_DEBUG, ha, 3917f4f5df23SVikas Chaudhary "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); 3918f4f5df23SVikas Chaudhary return; 3919f4f5df23SVikas Chaudhary } 3920f4f5df23SVikas Chaudhary 392133693c7aSVikas Chaudhary void qla4_82xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, 392233693c7aSVikas Chaudhary int in_count) 392333693c7aSVikas Chaudhary { 392433693c7aSVikas Chaudhary int i; 392533693c7aSVikas Chaudhary 392633693c7aSVikas Chaudhary /* Load all mailbox registers, except mailbox 0. */ 392733693c7aSVikas Chaudhary for (i = 1; i < in_count; i++) 392833693c7aSVikas Chaudhary writel(mbx_cmd[i], &ha->qla4_82xx_reg->mailbox_in[i]); 392933693c7aSVikas Chaudhary 393033693c7aSVikas Chaudhary /* Wakeup firmware */ 393133693c7aSVikas Chaudhary writel(mbx_cmd[0], &ha->qla4_82xx_reg->mailbox_in[0]); 393233693c7aSVikas Chaudhary readl(&ha->qla4_82xx_reg->mailbox_in[0]); 393333693c7aSVikas Chaudhary writel(HINT_MBX_INT_PENDING, &ha->qla4_82xx_reg->hint); 393433693c7aSVikas Chaudhary readl(&ha->qla4_82xx_reg->hint); 393533693c7aSVikas Chaudhary } 393633693c7aSVikas Chaudhary 393733693c7aSVikas Chaudhary void qla4_82xx_process_mbox_intr(struct scsi_qla_host *ha, int out_count) 393833693c7aSVikas Chaudhary { 393933693c7aSVikas Chaudhary int intr_status; 394033693c7aSVikas Chaudhary 394133693c7aSVikas Chaudhary intr_status = readl(&ha->qla4_82xx_reg->host_int); 394233693c7aSVikas Chaudhary if (intr_status & ISRX_82XX_RISC_INT) { 394333693c7aSVikas Chaudhary ha->mbox_status_count = out_count; 394433693c7aSVikas Chaudhary intr_status = readl(&ha->qla4_82xx_reg->host_status); 394533693c7aSVikas Chaudhary ha->isp_ops->interrupt_service_routine(ha, intr_status); 394633693c7aSVikas Chaudhary 394733693c7aSVikas Chaudhary if (test_bit(AF_INTERRUPTS_ON, &ha->flags) && 394833693c7aSVikas Chaudhary test_bit(AF_INTx_ENABLED, &ha->flags)) 394933693c7aSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 395033693c7aSVikas Chaudhary 0xfbff); 395133693c7aSVikas Chaudhary } 395233693c7aSVikas Chaudhary } 395333693c7aSVikas Chaudhary 3954f4f5df23SVikas Chaudhary int 3955f4f5df23SVikas Chaudhary qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 3956f4f5df23SVikas Chaudhary { 3957f4f5df23SVikas Chaudhary int ret; 3958f4f5df23SVikas Chaudhary uint32_t flt_addr; 3959f4f5df23SVikas Chaudhary 3960f4f5df23SVikas Chaudhary ret = qla4_8xxx_find_flt_start(ha, &flt_addr); 3961f4f5df23SVikas Chaudhary if (ret != QLA_SUCCESS) 3962f4f5df23SVikas Chaudhary return ret; 3963f4f5df23SVikas Chaudhary 3964f4f5df23SVikas Chaudhary qla4_8xxx_get_flt_info(ha, flt_addr); 39656e7b4292SVikas Chaudhary if (is_qla8022(ha)) { 3966f8086f4fSVikas Chaudhary qla4_82xx_get_fdt_info(ha); 3967f8086f4fSVikas Chaudhary qla4_82xx_get_idc_param(ha); 3968b37ca418SVikas Chaudhary } else if (is_qla8032(ha) || is_qla8042(ha)) { 39696e7b4292SVikas Chaudhary qla4_83xx_get_idc_param(ha); 39706e7b4292SVikas Chaudhary } 3971f4f5df23SVikas Chaudhary 3972f4f5df23SVikas Chaudhary return QLA_SUCCESS; 3973f4f5df23SVikas Chaudhary } 3974f4f5df23SVikas Chaudhary 3975f4f5df23SVikas Chaudhary /** 3976f4f5df23SVikas Chaudhary * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance 3977f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 3978f4f5df23SVikas Chaudhary * 3979f4f5df23SVikas Chaudhary * Remarks: 3980f4f5df23SVikas Chaudhary * For iSCSI, throws away all I/O and AENs into bit bucket, so they will 3981f4f5df23SVikas Chaudhary * not be available after successful return. Driver must cleanup potential 3982f4f5df23SVikas Chaudhary * outstanding I/O's after calling this funcion. 3983f4f5df23SVikas Chaudhary **/ 3984f4f5df23SVikas Chaudhary int 3985f4f5df23SVikas Chaudhary qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) 3986f4f5df23SVikas Chaudhary { 3987f4f5df23SVikas Chaudhary int status; 3988f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 3989f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 3990f4f5df23SVikas Chaudhary 3991f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 3992f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 3993f4f5df23SVikas Chaudhary 3994f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_STOP_FW; 3995f4f5df23SVikas Chaudhary status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, 3996f4f5df23SVikas Chaudhary &mbox_cmd[0], &mbox_sts[0]); 3997f4f5df23SVikas Chaudhary 3998f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, 3999f4f5df23SVikas Chaudhary __func__, status)); 4000f4f5df23SVikas Chaudhary return status; 4001f4f5df23SVikas Chaudhary } 4002f4f5df23SVikas Chaudhary 4003f4f5df23SVikas Chaudhary /** 4004f8086f4fSVikas Chaudhary * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands. 4005f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 4006f4f5df23SVikas Chaudhary **/ 4007f4f5df23SVikas Chaudhary int 4008f8086f4fSVikas Chaudhary qla4_82xx_isp_reset(struct scsi_qla_host *ha) 4009f4f5df23SVikas Chaudhary { 4010f4f5df23SVikas Chaudhary int rval; 4011f4f5df23SVikas Chaudhary uint32_t dev_state; 4012f4f5df23SVikas Chaudhary 4013f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 4014f8086f4fSVikas Chaudhary dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 4015f4f5df23SVikas Chaudhary 4016de8c72daSVikas Chaudhary if (dev_state == QLA8XXX_DEV_READY) { 4017f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 4018f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 4019de8c72daSVikas Chaudhary QLA8XXX_DEV_NEED_RESET); 4020de8c72daSVikas Chaudhary set_bit(AF_8XXX_RST_OWNER, &ha->flags); 4021f4f5df23SVikas Chaudhary } else 4022f4f5df23SVikas Chaudhary ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); 4023f4f5df23SVikas Chaudhary 4024f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 4025f4f5df23SVikas Chaudhary 4026f4f5df23SVikas Chaudhary rval = qla4_8xxx_device_state_handler(ha); 4027f4f5df23SVikas Chaudhary 4028f8086f4fSVikas Chaudhary qla4_82xx_idc_lock(ha); 4029f4f5df23SVikas Chaudhary qla4_8xxx_clear_rst_ready(ha); 4030f8086f4fSVikas Chaudhary qla4_82xx_idc_unlock(ha); 4031f4f5df23SVikas Chaudhary 4032068237c8STej Parkash if (rval == QLA_SUCCESS) { 4033f8086f4fSVikas Chaudhary ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n"); 403421033639SNilesh Javali clear_bit(AF_FW_RECOVERY, &ha->flags); 4035068237c8STej Parkash } 403621033639SNilesh Javali 4037f4f5df23SVikas Chaudhary return rval; 4038f4f5df23SVikas Chaudhary } 4039f4f5df23SVikas Chaudhary 4040f4f5df23SVikas Chaudhary /** 4041f4f5df23SVikas Chaudhary * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number 4042f4f5df23SVikas Chaudhary * @ha: pointer to host adapter structure. 4043f4f5df23SVikas Chaudhary * 4044f4f5df23SVikas Chaudhary **/ 4045f4f5df23SVikas Chaudhary int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) 4046f4f5df23SVikas Chaudhary { 4047f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 4048f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 4049f4f5df23SVikas Chaudhary struct mbx_sys_info *sys_info; 4050f4f5df23SVikas Chaudhary dma_addr_t sys_info_dma; 4051f4f5df23SVikas Chaudhary int status = QLA_ERROR; 4052f4f5df23SVikas Chaudhary 4053f4f5df23SVikas Chaudhary sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), 4054f4f5df23SVikas Chaudhary &sys_info_dma, GFP_KERNEL); 4055f4f5df23SVikas Chaudhary if (sys_info == NULL) { 4056f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", 4057f4f5df23SVikas Chaudhary ha->host_no, __func__)); 4058f4f5df23SVikas Chaudhary return status; 4059f4f5df23SVikas Chaudhary } 4060f4f5df23SVikas Chaudhary 4061f4f5df23SVikas Chaudhary memset(sys_info, 0, sizeof(*sys_info)); 4062f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 4063f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 4064f4f5df23SVikas Chaudhary 4065f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; 4066f4f5df23SVikas Chaudhary mbox_cmd[1] = LSDW(sys_info_dma); 4067f4f5df23SVikas Chaudhary mbox_cmd[2] = MSDW(sys_info_dma); 4068f4f5df23SVikas Chaudhary mbox_cmd[4] = sizeof(*sys_info); 4069f4f5df23SVikas Chaudhary 4070f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], 4071f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 4072f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", 4073f4f5df23SVikas Chaudhary ha->host_no, __func__)); 4074f4f5df23SVikas Chaudhary goto exit_validate_mac82; 4075f4f5df23SVikas Chaudhary } 4076f4f5df23SVikas Chaudhary 40772ccdf0dcSVikas Chaudhary /* Make sure we receive the minimum required data to cache internally */ 4078b37ca418SVikas Chaudhary if (((is_qla8032(ha) || is_qla8042(ha)) ? mbox_sts[3] : mbox_sts[4]) < 4079e19dd66fSNilesh Javali offsetof(struct mbx_sys_info, reserved)) { 4080f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" 4081f4f5df23SVikas Chaudhary " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); 4082f4f5df23SVikas Chaudhary goto exit_validate_mac82; 4083f4f5df23SVikas Chaudhary } 4084f4f5df23SVikas Chaudhary 4085f4f5df23SVikas Chaudhary /* Save M.A.C. address & serial_number */ 40862a991c21SManish Rangankar ha->port_num = sys_info->port_num; 4087f4f5df23SVikas Chaudhary memcpy(ha->my_mac, &sys_info->mac_addr[0], 4088f4f5df23SVikas Chaudhary min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); 4089f4f5df23SVikas Chaudhary memcpy(ha->serial_number, &sys_info->serial_number, 4090f4f5df23SVikas Chaudhary min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); 409191ec7cecSVikas Chaudhary memcpy(ha->model_name, &sys_info->board_id_str, 409291ec7cecSVikas Chaudhary min(sizeof(ha->model_name), sizeof(sys_info->board_id_str))); 409391ec7cecSVikas Chaudhary ha->phy_port_cnt = sys_info->phys_port_cnt; 409491ec7cecSVikas Chaudhary ha->phy_port_num = sys_info->port_num; 409591ec7cecSVikas Chaudhary ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt; 4096f4f5df23SVikas Chaudhary 4097f4f5df23SVikas Chaudhary DEBUG2(printk("scsi%ld: %s: " 4098f4f5df23SVikas Chaudhary "mac %02x:%02x:%02x:%02x:%02x:%02x " 4099f4f5df23SVikas Chaudhary "serial %s\n", ha->host_no, __func__, 4100f4f5df23SVikas Chaudhary ha->my_mac[0], ha->my_mac[1], ha->my_mac[2], 4101f4f5df23SVikas Chaudhary ha->my_mac[3], ha->my_mac[4], ha->my_mac[5], 4102f4f5df23SVikas Chaudhary ha->serial_number)); 4103f4f5df23SVikas Chaudhary 4104f4f5df23SVikas Chaudhary status = QLA_SUCCESS; 4105f4f5df23SVikas Chaudhary 4106f4f5df23SVikas Chaudhary exit_validate_mac82: 4107f4f5df23SVikas Chaudhary dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, 4108f4f5df23SVikas Chaudhary sys_info_dma); 4109f4f5df23SVikas Chaudhary return status; 4110f4f5df23SVikas Chaudhary } 4111f4f5df23SVikas Chaudhary 4112f4f5df23SVikas Chaudhary /* Interrupt handling helpers. */ 4113f4f5df23SVikas Chaudhary 41145c19b92aSVikas Chaudhary int qla4_8xxx_intr_enable(struct scsi_qla_host *ha) 4115f4f5df23SVikas Chaudhary { 4116f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 4117f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 4118f4f5df23SVikas Chaudhary 4119f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 4120f4f5df23SVikas Chaudhary 4121f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 4122f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 4123f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 4124f4f5df23SVikas Chaudhary mbox_cmd[1] = INTR_ENABLE; 4125f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 4126f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 4127f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 4128f4f5df23SVikas Chaudhary "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 4129f4f5df23SVikas Chaudhary __func__, mbox_sts[0])); 4130f4f5df23SVikas Chaudhary return QLA_ERROR; 4131f4f5df23SVikas Chaudhary } 4132f4f5df23SVikas Chaudhary return QLA_SUCCESS; 4133f4f5df23SVikas Chaudhary } 4134f4f5df23SVikas Chaudhary 41355c19b92aSVikas Chaudhary int qla4_8xxx_intr_disable(struct scsi_qla_host *ha) 4136f4f5df23SVikas Chaudhary { 4137f4f5df23SVikas Chaudhary uint32_t mbox_cmd[MBOX_REG_COUNT]; 4138f4f5df23SVikas Chaudhary uint32_t mbox_sts[MBOX_REG_COUNT]; 4139f4f5df23SVikas Chaudhary 4140f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 4141f4f5df23SVikas Chaudhary 4142f4f5df23SVikas Chaudhary memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 4143f4f5df23SVikas Chaudhary memset(&mbox_sts, 0, sizeof(mbox_sts)); 4144f4f5df23SVikas Chaudhary mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 4145f4f5df23SVikas Chaudhary mbox_cmd[1] = INTR_DISABLE; 4146f4f5df23SVikas Chaudhary if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 4147f4f5df23SVikas Chaudhary &mbox_sts[0]) != QLA_SUCCESS) { 4148f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, 4149f4f5df23SVikas Chaudhary "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 4150f4f5df23SVikas Chaudhary __func__, mbox_sts[0])); 4151f4f5df23SVikas Chaudhary return QLA_ERROR; 4152f4f5df23SVikas Chaudhary } 4153f4f5df23SVikas Chaudhary 4154f4f5df23SVikas Chaudhary return QLA_SUCCESS; 4155f4f5df23SVikas Chaudhary } 4156f4f5df23SVikas Chaudhary 4157f4f5df23SVikas Chaudhary void 4158f8086f4fSVikas Chaudhary qla4_82xx_enable_intrs(struct scsi_qla_host *ha) 4159f4f5df23SVikas Chaudhary { 41605c19b92aSVikas Chaudhary qla4_8xxx_intr_enable(ha); 4161f4f5df23SVikas Chaudhary 4162f4f5df23SVikas Chaudhary spin_lock_irq(&ha->hardware_lock); 4163f4f5df23SVikas Chaudhary /* BIT 10 - reset */ 4164f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 4165f4f5df23SVikas Chaudhary spin_unlock_irq(&ha->hardware_lock); 4166f4f5df23SVikas Chaudhary set_bit(AF_INTERRUPTS_ON, &ha->flags); 4167f4f5df23SVikas Chaudhary } 4168f4f5df23SVikas Chaudhary 4169f4f5df23SVikas Chaudhary void 4170f8086f4fSVikas Chaudhary qla4_82xx_disable_intrs(struct scsi_qla_host *ha) 4171f4f5df23SVikas Chaudhary { 41725fa8b573SSarang Radke if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) 41735c19b92aSVikas Chaudhary qla4_8xxx_intr_disable(ha); 4174f4f5df23SVikas Chaudhary 4175f4f5df23SVikas Chaudhary spin_lock_irq(&ha->hardware_lock); 4176f4f5df23SVikas Chaudhary /* BIT 10 - set */ 4177f8086f4fSVikas Chaudhary qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 4178f4f5df23SVikas Chaudhary spin_unlock_irq(&ha->hardware_lock); 4179f4f5df23SVikas Chaudhary } 4180f4f5df23SVikas Chaudhary 4181f4f5df23SVikas Chaudhary struct ql4_init_msix_entry { 4182f4f5df23SVikas Chaudhary uint16_t entry; 4183f4f5df23SVikas Chaudhary uint16_t index; 4184f4f5df23SVikas Chaudhary const char *name; 4185f4f5df23SVikas Chaudhary irq_handler_t handler; 4186f4f5df23SVikas Chaudhary }; 4187f4f5df23SVikas Chaudhary 4188f4f5df23SVikas Chaudhary static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = { 4189f4f5df23SVikas Chaudhary { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT, 4190f4f5df23SVikas Chaudhary "qla4xxx (default)", 4191f4f5df23SVikas Chaudhary (irq_handler_t)qla4_8xxx_default_intr_handler }, 4192f4f5df23SVikas Chaudhary { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q, 4193f4f5df23SVikas Chaudhary "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q }, 4194f4f5df23SVikas Chaudhary }; 4195f4f5df23SVikas Chaudhary 4196f4f5df23SVikas Chaudhary void 4197f4f5df23SVikas Chaudhary qla4_8xxx_disable_msix(struct scsi_qla_host *ha) 4198f4f5df23SVikas Chaudhary { 4199f4f5df23SVikas Chaudhary int i; 4200f4f5df23SVikas Chaudhary struct ql4_msix_entry *qentry; 4201f4f5df23SVikas Chaudhary 4202f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 4203f4f5df23SVikas Chaudhary qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 4204f4f5df23SVikas Chaudhary if (qentry->have_irq) { 4205f4f5df23SVikas Chaudhary free_irq(qentry->msix_vector, ha); 4206f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 4207f4f5df23SVikas Chaudhary __func__, qla4_8xxx_msix_entries[i].name)); 4208f4f5df23SVikas Chaudhary } 4209f4f5df23SVikas Chaudhary } 4210f4f5df23SVikas Chaudhary pci_disable_msix(ha->pdev); 4211f4f5df23SVikas Chaudhary clear_bit(AF_MSIX_ENABLED, &ha->flags); 4212f4f5df23SVikas Chaudhary } 4213f4f5df23SVikas Chaudhary 4214f4f5df23SVikas Chaudhary int 4215f4f5df23SVikas Chaudhary qla4_8xxx_enable_msix(struct scsi_qla_host *ha) 4216f4f5df23SVikas Chaudhary { 4217f4f5df23SVikas Chaudhary int i, ret; 4218f4f5df23SVikas Chaudhary struct msix_entry entries[QLA_MSIX_ENTRIES]; 4219f4f5df23SVikas Chaudhary struct ql4_msix_entry *qentry; 4220f4f5df23SVikas Chaudhary 4221f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) 4222f4f5df23SVikas Chaudhary entries[i].entry = qla4_8xxx_msix_entries[i].entry; 4223f4f5df23SVikas Chaudhary 4224e88285d6SAlexander Gordeev ret = pci_enable_msix_exact(ha->pdev, entries, ARRAY_SIZE(entries)); 4225f4f5df23SVikas Chaudhary if (ret) { 4226f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 4227f4f5df23SVikas Chaudhary "MSI-X: Failed to enable support -- %d/%d\n", 4228f4f5df23SVikas Chaudhary QLA_MSIX_ENTRIES, ret); 4229f4f5df23SVikas Chaudhary goto msix_out; 4230f4f5df23SVikas Chaudhary } 4231f4f5df23SVikas Chaudhary set_bit(AF_MSIX_ENABLED, &ha->flags); 4232f4f5df23SVikas Chaudhary 4233f4f5df23SVikas Chaudhary for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 4234f4f5df23SVikas Chaudhary qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 4235f4f5df23SVikas Chaudhary qentry->msix_vector = entries[i].vector; 4236f4f5df23SVikas Chaudhary qentry->msix_entry = entries[i].entry; 4237f4f5df23SVikas Chaudhary qentry->have_irq = 0; 4238f4f5df23SVikas Chaudhary ret = request_irq(qentry->msix_vector, 4239f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].handler, 0, 4240f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].name, ha); 4241f4f5df23SVikas Chaudhary if (ret) { 4242f4f5df23SVikas Chaudhary ql4_printk(KERN_WARNING, ha, 4243f4f5df23SVikas Chaudhary "MSI-X: Unable to register handler -- %x/%d.\n", 4244f4f5df23SVikas Chaudhary qla4_8xxx_msix_entries[i].index, ret); 4245f4f5df23SVikas Chaudhary qla4_8xxx_disable_msix(ha); 4246f4f5df23SVikas Chaudhary goto msix_out; 4247f4f5df23SVikas Chaudhary } 4248f4f5df23SVikas Chaudhary qentry->have_irq = 1; 4249f4f5df23SVikas Chaudhary DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 4250f4f5df23SVikas Chaudhary __func__, qla4_8xxx_msix_entries[i].name)); 4251f4f5df23SVikas Chaudhary } 4252f4f5df23SVikas Chaudhary msix_out: 4253f4f5df23SVikas Chaudhary return ret; 4254f4f5df23SVikas Chaudhary } 425537418cc6SNilesh Javali 425637418cc6SNilesh Javali int qla4_8xxx_check_init_adapter_retry(struct scsi_qla_host *ha) 425737418cc6SNilesh Javali { 425837418cc6SNilesh Javali int status = QLA_SUCCESS; 425937418cc6SNilesh Javali 426037418cc6SNilesh Javali /* Dont retry adapter initialization if IRQ allocation failed */ 426137418cc6SNilesh Javali if (!test_bit(AF_IRQ_ATTACHED, &ha->flags)) { 426237418cc6SNilesh Javali ql4_printk(KERN_WARNING, ha, "%s: Skipping retry of adapter initialization as IRQs are not attached\n", 426337418cc6SNilesh Javali __func__); 426437418cc6SNilesh Javali status = QLA_ERROR; 426537418cc6SNilesh Javali goto exit_init_adapter_failure; 426637418cc6SNilesh Javali } 426737418cc6SNilesh Javali 426837418cc6SNilesh Javali /* Since interrupts are registered in start_firmware for 426937418cc6SNilesh Javali * 8xxx, release them here if initialize_adapter fails 427037418cc6SNilesh Javali * and retry adapter initialization */ 427137418cc6SNilesh Javali qla4xxx_free_irqs(ha); 427237418cc6SNilesh Javali 427337418cc6SNilesh Javali exit_init_adapter_failure: 427437418cc6SNilesh Javali return status; 427537418cc6SNilesh Javali } 4276