xref: /openbmc/linux/drivers/scsi/qla4xxx/ql4_fw.h (revision c4f7ac64)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * QLogic iSCSI HBA Driver
4  * Copyright (c)  2003-2013 QLogic Corporation
5  */
6 
7 #ifndef _QLA4X_FW_H
8 #define _QLA4X_FW_H
9 
10 
11 #define MAX_PRST_DEV_DB_ENTRIES		64
12 #define MIN_DISC_DEV_DB_ENTRY		MAX_PRST_DEV_DB_ENTRIES
13 #define MAX_DEV_DB_ENTRIES		512
14 #define MAX_DEV_DB_ENTRIES_40XX		256
15 
16 /*************************************************************************
17  *
18  *		ISP 4010 I/O Register Set Structure and Definitions
19  *
20  *************************************************************************/
21 
22 struct port_ctrl_stat_regs {
23 	__le32 ext_hw_conf;	/* 0x50  R/W */
24 	__le32 rsrvd0;		/* 0x54 */
25 	__le32 port_ctrl;	/* 0x58 */
26 	__le32 port_status;	/* 0x5c */
27 	__le32 rsrvd1[32];	/* 0x60-0xdf */
28 	__le32 gp_out;		/* 0xe0 */
29 	__le32 gp_in;		/* 0xe4 */
30 	__le32 rsrvd2[5];	/* 0xe8-0xfb */
31 	__le32 port_err_status; /* 0xfc */
32 };
33 
34 struct host_mem_cfg_regs {
35 	__le32 rsrvd0[12];	/* 0x50-0x79 */
36 	__le32 req_q_out;	/* 0x80 */
37 	__le32 rsrvd1[31];	/* 0x84-0xFF */
38 };
39 
40 /*
41  * ISP 82xx I/O Register Set structure definitions.
42  */
43 struct device_reg_82xx {
44 	__le32 req_q_out;	/* 0x0000 (R): Request Queue out-Pointer. */
45 	__le32 reserve1[63];	/* Request Queue out-Pointer. (64 * 4) */
46 	__le32 rsp_q_in;	/* 0x0100 (R/W): Response Queue In-Pointer. */
47 	__le32 reserve2[63];	/* Response Queue In-Pointer. */
48 	__le32 rsp_q_out;	/* 0x0200 (R/W): Response Queue Out-Pointer. */
49 	__le32 reserve3[63];	/* Response Queue Out-Pointer. */
50 
51 	__le32 mailbox_in[8];	/* 0x0300 (R/W): Mail box In registers */
52 	__le32 reserve4[24];
53 	__le32 hint;		/* 0x0380 (R/W): Host interrupt register */
54 #define HINT_MBX_INT_PENDING	BIT_0
55 	__le32 reserve5[31];
56 	__le32 mailbox_out[8];	/* 0x0400 (R): Mail box Out registers */
57 	__le32 reserve6[56];
58 
59 	__le32 host_status;	/* Offset 0x500 (R): host status */
60 #define HSRX_RISC_MB_INT	BIT_0  /* RISC to Host Mailbox interrupt */
61 #define HSRX_RISC_IOCB_INT	BIT_1  /* RISC to Host IOCB interrupt */
62 
63 	__le32 host_int;	/* Offset 0x0504 (R/W): Interrupt status. */
64 #define ISRX_82XX_RISC_INT	BIT_0 /* RISC interrupt. */
65 };
66 
67 /* ISP 83xx I/O Register Set structure */
68 struct device_reg_83xx {
69 	__le32 mailbox_in[16];	/* 0x0000 */
70 	__le32 reserve1[496];	/* 0x0040 */
71 	__le32 mailbox_out[16];	/* 0x0800 */
72 	__le32 reserve2[496];
73 	__le32 mbox_int;	/* 0x1000 */
74 	__le32 reserve3[63];
75 	__le32 req_q_out;	/* 0x1100 */
76 	__le32 reserve4[63];
77 
78 	__le32 rsp_q_in;	/* 0x1200 */
79 	__le32 reserve5[1919];
80 
81 	__le32 req_q_in;	/* 0x3000 */
82 	__le32 reserve6[3];
83 	__le32 iocb_int_mask;	/* 0x3010 */
84 	__le32 reserve7[3];
85 	__le32 rsp_q_out;	/* 0x3020 */
86 	__le32 reserve8[3];
87 	__le32 anonymousbuff;	/* 0x3030 */
88 	__le32 mb_int_mask;	/* 0x3034 */
89 
90 	__le32 host_intr;	/* 0x3038 - Host Interrupt Register */
91 	__le32 risc_intr;	/* 0x303C - RISC Interrupt Register */
92 	__le32 reserve9[544];
93 	__le32 leg_int_ptr;	/* 0x38C0 - Legacy Interrupt Pointer Register */
94 	__le32 leg_int_trig;	/* 0x38C4 - Legacy Interrupt Trigger Control */
95 	__le32 leg_int_mask;	/* 0x38C8 - Legacy Interrupt Mask Register */
96 };
97 
98 #define INT_ENABLE_FW_MB	(1 << 2)
99 #define INT_MASK_FW_MB		(1 << 2)
100 
101 /*  remote register set (access via PCI memory read/write) */
102 struct isp_reg {
103 #define MBOX_REG_COUNT 8
104 	__le32 mailbox[MBOX_REG_COUNT];
105 
106 	__le32 flash_address;	/* 0x20 */
107 	__le32 flash_data;
108 	__le32 ctrl_status;
109 
110 	union {
111 		struct {
112 			__le32 nvram;
113 			__le32 reserved1[2]; /* 0x30 */
114 		} __attribute__ ((packed)) isp4010;
115 		struct {
116 			__le32 intr_mask;
117 			__le32 nvram; /* 0x30 */
118 			__le32 semaphore;
119 		} __attribute__ ((packed)) isp4022;
120 	} u1;
121 
122 	__le32 req_q_in;    /* SCSI Request Queue Producer Index */
123 	__le32 rsp_q_out;   /* SCSI Completion Queue Consumer Index */
124 
125 	__le32 reserved2[4];	/* 0x40 */
126 
127 	union {
128 		struct {
129 			__le32 ext_hw_conf; /* 0x50 */
130 			__le32 flow_ctrl;
131 			__le32 port_ctrl;
132 			__le32 port_status;
133 
134 			__le32 reserved3[8]; /* 0x60 */
135 
136 			__le32 req_q_out; /* 0x80 */
137 
138 			__le32 reserved4[23]; /* 0x84 */
139 
140 			__le32 gp_out; /* 0xe0 */
141 			__le32 gp_in;
142 
143 			__le32 reserved5[5];
144 
145 			__le32 port_err_status; /* 0xfc */
146 		} __attribute__ ((packed)) isp4010;
147 		struct {
148 			union {
149 				struct port_ctrl_stat_regs p0;
150 				struct host_mem_cfg_regs p1;
151 			};
152 		} __attribute__ ((packed)) isp4022;
153 	} u2;
154 };				/* 256 x100 */
155 
156 
157 /* Semaphore Defines for 4010 */
158 #define QL4010_DRVR_SEM_BITS	0x00000030
159 #define QL4010_GPIO_SEM_BITS	0x000000c0
160 #define QL4010_SDRAM_SEM_BITS	0x00000300
161 #define QL4010_PHY_SEM_BITS	0x00000c00
162 #define QL4010_NVRAM_SEM_BITS	0x00003000
163 #define QL4010_FLASH_SEM_BITS	0x0000c000
164 
165 #define QL4010_DRVR_SEM_MASK	0x00300000
166 #define QL4010_GPIO_SEM_MASK	0x00c00000
167 #define QL4010_SDRAM_SEM_MASK	0x03000000
168 #define QL4010_PHY_SEM_MASK	0x0c000000
169 #define QL4010_NVRAM_SEM_MASK	0x30000000
170 #define QL4010_FLASH_SEM_MASK	0xc0000000
171 
172 /* Semaphore Defines for 4022 */
173 #define QL4022_RESOURCE_MASK_BASE_CODE 0x7
174 #define QL4022_RESOURCE_BITS_BASE_CODE 0x4
175 
176 
177 #define QL4022_DRVR_SEM_MASK	(QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
178 #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
179 #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
180 #define QL4022_NVRAM_SEM_MASK	(QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
181 #define QL4022_FLASH_SEM_MASK	(QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
182 
183 /* nvram address for 4032 */
184 #define NVRAM_PORT0_BOOT_MODE		0x03b1
185 #define NVRAM_PORT0_BOOT_PRI_TGT	0x03b2
186 #define NVRAM_PORT0_BOOT_SEC_TGT	0x03bb
187 #define NVRAM_PORT1_BOOT_MODE		0x07b1
188 #define NVRAM_PORT1_BOOT_PRI_TGT	0x07b2
189 #define NVRAM_PORT1_BOOT_SEC_TGT	0x07bb
190 
191 
192 /* Page # defines for 4022 */
193 #define PORT_CTRL_STAT_PAGE			0	/* 4022 */
194 #define HOST_MEM_CFG_PAGE			1	/* 4022 */
195 #define LOCAL_RAM_CFG_PAGE			2	/* 4022 */
196 #define PROT_STAT_PAGE				3	/* 4022 */
197 
198 /* Register Mask - sets corresponding mask bits in the upper word */
199 static inline uint32_t set_rmask(uint32_t val)
200 {
201 	return (val & 0xffff) | (val << 16);
202 }
203 
204 
205 static inline uint32_t clr_rmask(uint32_t val)
206 {
207 	return 0 | (val << 16);
208 }
209 
210 /*  ctrl_status definitions */
211 #define CSR_SCSI_PAGE_SELECT			0x00000003
212 #define CSR_SCSI_INTR_ENABLE			0x00000004	/* 4010 */
213 #define CSR_SCSI_RESET_INTR			0x00000008
214 #define CSR_SCSI_COMPLETION_INTR		0x00000010
215 #define CSR_SCSI_PROCESSOR_INTR			0x00000020
216 #define CSR_INTR_RISC				0x00000040
217 #define CSR_BOOT_ENABLE				0x00000080
218 #define CSR_NET_PAGE_SELECT			0x00000300	/* 4010 */
219 #define CSR_FUNC_NUM				0x00000700	/* 4022 */
220 #define CSR_NET_RESET_INTR			0x00000800	/* 4010 */
221 #define CSR_FORCE_SOFT_RESET			0x00002000	/* 4022 */
222 #define CSR_FATAL_ERROR				0x00004000
223 #define CSR_SOFT_RESET				0x00008000
224 #define ISP_CONTROL_FN_MASK			CSR_FUNC_NUM
225 #define ISP_CONTROL_FN0_SCSI			0x0500
226 #define ISP_CONTROL_FN1_SCSI			0x0700
227 
228 #define INTR_PENDING				(CSR_SCSI_COMPLETION_INTR |\
229 						 CSR_SCSI_PROCESSOR_INTR |\
230 						 CSR_SCSI_RESET_INTR)
231 
232 /* ISP InterruptMask definitions */
233 #define IMR_SCSI_INTR_ENABLE			0x00000004	/* 4022 */
234 
235 /* ISP 4022 nvram definitions */
236 #define NVR_WRITE_ENABLE			0x00000010	/* 4022 */
237 
238 #define QL4010_NVRAM_SIZE			0x200
239 #define QL40X2_NVRAM_SIZE			0x800
240 
241 /*  ISP port_status definitions */
242 
243 /*  ISP Semaphore definitions */
244 
245 /*  ISP General Purpose Output definitions */
246 #define GPOR_TOPCAT_RESET			0x00000004
247 
248 /*  shadow registers (DMA'd from HA to system memory.  read only) */
249 struct shadow_regs {
250 	/* SCSI Request Queue Consumer Index */
251 	__le32 req_q_out;	/*  0 x0   R */
252 
253 	/* SCSI Completion Queue Producer Index */
254 	__le32 rsp_q_in;	/*  4 x4   R */
255 };		  /*  8 x8 */
256 
257 
258 /*  External hardware configuration register */
259 union external_hw_config_reg {
260 	struct {
261 		/* FIXME: Do we even need this?	 All values are
262 		 * referred to by 16 bit quantities.  Platform and
263 		 * endianess issues. */
264 		__le32 bReserved0:1;
265 		__le32 bSDRAMProtectionMethod:2;
266 		__le32 bSDRAMBanks:1;
267 		__le32 bSDRAMChipWidth:1;
268 		__le32 bSDRAMChipSize:2;
269 		__le32 bParityDisable:1;
270 		__le32 bExternalMemoryType:1;
271 		__le32 bFlashBIOSWriteEnable:1;
272 		__le32 bFlashUpperBankSelect:1;
273 		__le32 bWriteBurst:2;
274 		__le32 bReserved1:3;
275 		__le32 bMask:16;
276 	};
277 	uint32_t Asuint32_t;
278 };
279 
280 /* 82XX Support  start */
281 /* 82xx Default FLT Addresses */
282 #define FA_FLASH_LAYOUT_ADDR_82		0xFC400
283 #define FA_FLASH_DESCR_ADDR_82		0xFC000
284 #define FA_BOOT_LOAD_ADDR_82		0x04000
285 #define FA_BOOT_CODE_ADDR_82		0x20000
286 #define FA_RISC_CODE_ADDR_82		0x40000
287 #define FA_GOLD_RISC_CODE_ADDR_82	0x80000
288 #define FA_FLASH_ISCSI_CHAP		0x540000
289 #define FA_FLASH_CHAP_SIZE		0xC0000
290 #define FA_FLASH_ISCSI_DDB		0x420000
291 #define FA_FLASH_DDB_SIZE		0x080000
292 
293 /* Flash Description Table */
294 struct qla_fdt_layout {
295 	uint8_t sig[4];
296 	uint16_t version;
297 	uint16_t len;
298 	uint16_t checksum;
299 	uint8_t unused1[2];
300 	uint8_t model[16];
301 	uint16_t man_id;
302 	uint16_t id;
303 	uint8_t flags;
304 	uint8_t erase_cmd;
305 	uint8_t alt_erase_cmd;
306 	uint8_t wrt_enable_cmd;
307 	uint8_t wrt_enable_bits;
308 	uint8_t wrt_sts_reg_cmd;
309 	uint8_t unprotect_sec_cmd;
310 	uint8_t read_man_id_cmd;
311 	uint32_t block_size;
312 	uint32_t alt_block_size;
313 	uint32_t flash_size;
314 	uint32_t wrt_enable_data;
315 	uint8_t read_id_addr_len;
316 	uint8_t wrt_disable_bits;
317 	uint8_t read_dev_id_len;
318 	uint8_t chip_erase_cmd;
319 	uint16_t read_timeout;
320 	uint8_t protect_sec_cmd;
321 	uint8_t unused2[65];
322 };
323 
324 /* Flash Layout Table */
325 
326 struct qla_flt_location {
327 	uint8_t sig[4];
328 	uint16_t start_lo;
329 	uint16_t start_hi;
330 	uint8_t version;
331 	uint8_t unused[5];
332 	uint16_t checksum;
333 };
334 
335 struct qla_flt_header {
336 	uint16_t version;
337 	uint16_t length;
338 	uint16_t checksum;
339 	uint16_t unused;
340 };
341 
342 /* 82xx FLT Regions */
343 #define FLT_REG_FDT		0x1a
344 #define FLT_REG_FLT		0x1c
345 #define FLT_REG_BOOTLOAD_82	0x72
346 #define FLT_REG_FW_82		0x74
347 #define FLT_REG_FW_82_1		0x97
348 #define FLT_REG_GOLD_FW_82	0x75
349 #define FLT_REG_BOOT_CODE_82	0x78
350 #define FLT_REG_ISCSI_PARAM	0x65
351 #define FLT_REG_ISCSI_CHAP	0x63
352 #define FLT_REG_ISCSI_DDB	0x6A
353 
354 struct qla_flt_region {
355 	uint32_t code;
356 	uint32_t size;
357 	uint32_t start;
358 	uint32_t end;
359 };
360 
361 /*************************************************************************
362  *
363  *		Mailbox Commands Structures and Definitions
364  *
365  *************************************************************************/
366 
367 /*  Mailbox command definitions */
368 #define MBOX_CMD_ABOUT_FW			0x0009
369 #define MBOX_CMD_PING				0x000B
370 #define PING_IPV6_PROTOCOL_ENABLE		0x1
371 #define PING_IPV6_LINKLOCAL_ADDR		0x4
372 #define PING_IPV6_ADDR0				0x8
373 #define PING_IPV6_ADDR1				0xC
374 #define MBOX_CMD_ENABLE_INTRS			0x0010
375 #define INTR_DISABLE				0
376 #define INTR_ENABLE				1
377 #define MBOX_CMD_STOP_FW			0x0014
378 #define MBOX_CMD_ABORT_TASK			0x0015
379 #define MBOX_CMD_LUN_RESET			0x0016
380 #define MBOX_CMD_TARGET_WARM_RESET		0x0017
381 #define MBOX_CMD_GET_MANAGEMENT_DATA		0x001E
382 #define MBOX_CMD_GET_FW_STATUS			0x001F
383 #define MBOX_CMD_SET_ISNS_SERVICE		0x0021
384 #define ISNS_DISABLE				0
385 #define ISNS_ENABLE				1
386 #define MBOX_CMD_COPY_FLASH			0x0024
387 #define MBOX_CMD_WRITE_FLASH			0x0025
388 #define MBOX_CMD_READ_FLASH			0x0026
389 #define MBOX_CMD_CLEAR_DATABASE_ENTRY		0x0031
390 #define MBOX_CMD_CONN_OPEN			0x0074
391 #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT		0x0056
392 #define DDB_NOT_LOGGED_IN			0x09
393 #define LOGOUT_OPTION_CLOSE_SESSION		0x0002
394 #define LOGOUT_OPTION_RELOGIN			0x0004
395 #define LOGOUT_OPTION_FREE_DDB			0x0008
396 #define MBOX_CMD_SET_PARAM			0x0059
397 #define SET_DRVR_VERSION			0x200
398 #define MAX_DRVR_VER_LEN			24
399 #define MBOX_CMD_EXECUTE_IOCB_A64		0x005A
400 #define MBOX_CMD_INITIALIZE_FIRMWARE		0x0060
401 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK		0x0061
402 #define MBOX_CMD_REQUEST_DATABASE_ENTRY		0x0062
403 #define MBOX_CMD_SET_DATABASE_ENTRY		0x0063
404 #define MBOX_CMD_GET_DATABASE_ENTRY		0x0064
405 #define DDB_DS_UNASSIGNED			0x00
406 #define DDB_DS_NO_CONNECTION_ACTIVE		0x01
407 #define DDB_DS_DISCOVERY			0x02
408 #define DDB_DS_SESSION_ACTIVE			0x04
409 #define DDB_DS_SESSION_FAILED			0x06
410 #define DDB_DS_LOGIN_IN_PROCESS			0x07
411 #define MBOX_CMD_GET_FW_STATE			0x0069
412 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A
413 #define MBOX_CMD_DIAG_TEST			0x0075
414 #define MBOX_CMD_GET_SYS_INFO			0x0078
415 #define MBOX_CMD_GET_NVRAM			0x0078	/* For 40xx */
416 #define MBOX_CMD_SET_NVRAM			0x0079	/* For 40xx */
417 #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS	0x0087
418 #define MBOX_CMD_SET_ACB			0x0088
419 #define MBOX_CMD_GET_ACB			0x0089
420 #define MBOX_CMD_DISABLE_ACB			0x008A
421 #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE	0x008B
422 #define MBOX_CMD_GET_IPV6_DEST_CACHE		0x008C
423 #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST	0x008D
424 #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST	0x008E
425 #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE	0x0090
426 #define MBOX_CMD_GET_IP_ADDR_STATE		0x0091
427 #define MBOX_CMD_SEND_IPV6_ROUTER_SOL		0x0092
428 #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR	0x0093
429 #define MBOX_CMD_SET_PORT_CONFIG		0x0122
430 #define MBOX_CMD_GET_PORT_CONFIG		0x0123
431 #define MBOX_CMD_SET_LED_CONFIG			0x0125
432 #define MBOX_CMD_GET_LED_CONFIG			0x0126
433 #define MBOX_CMD_MINIDUMP			0x0129
434 
435 /* Port Config */
436 #define ENABLE_INTERNAL_LOOPBACK		0x04
437 #define ENABLE_EXTERNAL_LOOPBACK		0x08
438 #define ENABLE_DCBX				0x10
439 
440 /* Minidump subcommand */
441 #define MINIDUMP_GET_SIZE_SUBCOMMAND		0x00
442 #define MINIDUMP_GET_TMPLT_SUBCOMMAND		0x01
443 
444 /* Mailbox 1 */
445 #define FW_STATE_READY				0x0000
446 #define FW_STATE_CONFIG_WAIT			0x0001
447 #define FW_STATE_WAIT_AUTOCONNECT		0x0002
448 #define FW_STATE_ERROR				0x0004
449 #define FW_STATE_CONFIGURING_IP			0x0008
450 
451 /* Mailbox 3 */
452 #define FW_ADDSTATE_OPTICAL_MEDIA		0x0001
453 #define FW_ADDSTATE_DHCPv4_ENABLED		0x0002
454 #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED	0x0004
455 #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED	0x0008
456 #define FW_ADDSTATE_LINK_UP			0x0010
457 #define FW_ADDSTATE_ISNS_SVC_ENABLED		0x0020
458 #define FW_ADDSTATE_LINK_SPEED_10MBPS		0x0100
459 #define FW_ADDSTATE_LINK_SPEED_100MBPS		0x0200
460 #define FW_ADDSTATE_LINK_SPEED_1GBPS		0x0400
461 #define FW_ADDSTATE_LINK_SPEED_10GBPS		0x0800
462 
463 #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS	0x006B
464 #define IPV6_DEFAULT_DDB_ENTRY			0x0001
465 
466 #define MBOX_CMD_CONN_OPEN_SESS_LOGIN		0x0074
467 #define MBOX_CMD_GET_CRASH_RECORD		0x0076	/* 4010 only */
468 #define MBOX_CMD_GET_CONN_EVENT_LOG		0x0077
469 
470 #define MBOX_CMD_IDC_ACK			0x0101
471 #define MBOX_CMD_IDC_TIME_EXTEND		0x0102
472 #define MBOX_CMD_PORT_RESET			0x0120
473 #define MBOX_CMD_SET_PORT_CONFIG		0x0122
474 
475 /*  Mailbox status definitions */
476 #define MBOX_COMPLETION_STATUS			4
477 #define MBOX_STS_BUSY				0x0007
478 #define MBOX_STS_INTERMEDIATE_COMPLETION	0x1000
479 #define MBOX_STS_COMMAND_COMPLETE		0x4000
480 #define MBOX_STS_COMMAND_ERROR			0x4005
481 
482 #define MBOX_ASYNC_EVENT_STATUS			8
483 #define MBOX_ASTS_SYSTEM_ERROR			0x8002
484 #define MBOX_ASTS_REQUEST_TRANSFER_ERROR	0x8003
485 #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR	0x8004
486 #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM	0x8005
487 #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED	0x8006
488 #define MBOX_ASTS_LINK_UP			0x8010
489 #define MBOX_ASTS_LINK_DOWN			0x8011
490 #define MBOX_ASTS_DATABASE_CHANGED		0x8014
491 #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED	0x8015
492 #define MBOX_ASTS_SELF_TEST_FAILED		0x8016
493 #define MBOX_ASTS_LOGIN_FAILED			0x8017
494 #define MBOX_ASTS_DNS				0x8018
495 #define MBOX_ASTS_HEARTBEAT			0x8019
496 #define MBOX_ASTS_NVRAM_INVALID			0x801A
497 #define MBOX_ASTS_MAC_ADDRESS_CHANGED		0x801B
498 #define MBOX_ASTS_IP_ADDRESS_CHANGED		0x801C
499 #define MBOX_ASTS_DHCP_LEASE_EXPIRED		0x801D
500 #define MBOX_ASTS_DHCP_LEASE_ACQUIRED		0x801F
501 #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
502 #define MBOX_ASTS_DUPLICATE_IP			0x8025
503 #define MBOX_ASTS_ARP_COMPLETE			0x8026
504 #define MBOX_ASTS_SUBNET_STATE_CHANGE		0x8027
505 #define MBOX_ASTS_RESPONSE_QUEUE_FULL		0x8028
506 #define MBOX_ASTS_IP_ADDR_STATE_CHANGED		0x8029
507 #define MBOX_ASTS_IPV6_DEFAULT_ROUTER_CHANGED	0x802A
508 #define MBOX_ASTS_IPV6_LINK_MTU_CHANGE		0x802B
509 #define MBOX_ASTS_IPV6_AUTO_PREFIX_IGNORED	0x802C
510 #define MBOX_ASTS_IPV6_ND_LOCAL_PREFIX_IGNORED	0x802D
511 #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD		0x802E
512 #define MBOX_ASTS_INITIALIZATION_FAILED		0x8031
513 #define MBOX_ASTS_SYSTEM_WARNING_EVENT		0x8036
514 #define MBOX_ASTS_IDC_COMPLETE			0x8100
515 #define MBOX_ASTS_IDC_REQUEST_NOTIFICATION	0x8101
516 #define MBOX_ASTS_IDC_TIME_EXTEND_NOTIFICATION	0x8102
517 #define MBOX_ASTS_DCBX_CONF_CHANGE		0x8110
518 #define MBOX_ASTS_TXSCVR_INSERTED		0x8130
519 #define MBOX_ASTS_TXSCVR_REMOVED		0x8131
520 
521 #define ISNS_EVENT_DATA_RECEIVED		0x0000
522 #define ISNS_EVENT_CONNECTION_OPENED		0x0001
523 #define ISNS_EVENT_CONNECTION_FAILED		0x0002
524 #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR	0x8022
525 #define MBOX_ASTS_SUBNET_STATE_CHANGE		0x8027
526 
527 /* ACB Configuration Defines */
528 #define ACB_CONFIG_DISABLE		0x00
529 #define ACB_CONFIG_SET			0x01
530 
531 /* ACB/IP Address State Defines */
532 #define IP_ADDRSTATE_UNCONFIGURED	0
533 #define IP_ADDRSTATE_INVALID		1
534 #define IP_ADDRSTATE_ACQUIRING		2
535 #define IP_ADDRSTATE_TENTATIVE		3
536 #define IP_ADDRSTATE_DEPRICATED		4
537 #define IP_ADDRSTATE_PREFERRED		5
538 #define IP_ADDRSTATE_DISABLING		6
539 
540 /* FLASH offsets */
541 #define FLASH_SEGMENT_IFCB	0x04000000
542 
543 #define FLASH_OPT_RMW_HOLD	0
544 #define FLASH_OPT_RMW_INIT	1
545 #define FLASH_OPT_COMMIT	2
546 #define FLASH_OPT_RMW_COMMIT	3
547 
548 /* generic defines to enable/disable params */
549 #define QL4_PARAM_DISABLE	0
550 #define QL4_PARAM_ENABLE	1
551 
552 /*************************************************************************/
553 
554 /* Host Adapter Initialization Control Block (from host) */
555 struct addr_ctrl_blk {
556 	uint8_t version;	/* 00 */
557 #define  IFCB_VER_MIN			0x01
558 #define  IFCB_VER_MAX			0x02
559 	uint8_t control;	/* 01 */
560 #define	 CTRLOPT_NEW_CONN_DISABLE	0x0002
561 
562 	uint16_t fw_options;	/* 02-03 */
563 #define	 FWOPT_HEARTBEAT_ENABLE		  0x1000
564 #define	 FWOPT_SESSION_MODE		  0x0040
565 #define	 FWOPT_INITIATOR_MODE		  0x0020
566 #define	 FWOPT_TARGET_MODE		  0x0010
567 #define	 FWOPT_ENABLE_CRBDB		  0x8000
568 
569 	uint16_t exec_throttle;	/* 04-05 */
570 	uint8_t zio_count;	/* 06 */
571 	uint8_t res0;	/* 07 */
572 	uint16_t eth_mtu_size;	/* 08-09 */
573 	uint16_t add_fw_options;	/* 0A-0B */
574 #define ADFWOPT_SERIALIZE_TASK_MGMT	0x0400
575 #define ADFWOPT_AUTOCONN_DISABLE	0x0002
576 
577 	uint8_t hb_interval;	/* 0C */
578 	uint8_t inst_num; /* 0D */
579 	uint16_t res1;		/* 0E-0F */
580 	uint16_t rqq_consumer_idx;	/* 10-11 */
581 	uint16_t compq_producer_idx;	/* 12-13 */
582 	uint16_t rqq_len;	/* 14-15 */
583 	uint16_t compq_len;	/* 16-17 */
584 	uint32_t rqq_addr_lo;	/* 18-1B */
585 	uint32_t rqq_addr_hi;	/* 1C-1F */
586 	uint32_t compq_addr_lo;	/* 20-23 */
587 	uint32_t compq_addr_hi;	/* 24-27 */
588 	uint32_t shdwreg_addr_lo;	/* 28-2B */
589 	uint32_t shdwreg_addr_hi;	/* 2C-2F */
590 
591 	uint16_t iscsi_opts;	/* 30-31 */
592 #define ISCSIOPTS_HEADER_DIGEST_EN		0x2000
593 #define ISCSIOPTS_DATA_DIGEST_EN		0x1000
594 #define ISCSIOPTS_IMMEDIATE_DATA_EN		0x0800
595 #define ISCSIOPTS_INITIAL_R2T_EN		0x0400
596 #define ISCSIOPTS_DATA_SEQ_INORDER_EN		0x0200
597 #define ISCSIOPTS_DATA_PDU_INORDER_EN		0x0100
598 #define ISCSIOPTS_CHAP_AUTH_EN			0x0080
599 #define ISCSIOPTS_SNACK_EN			0x0040
600 #define ISCSIOPTS_DISCOVERY_LOGOUT_EN		0x0020
601 #define ISCSIOPTS_BIDI_CHAP_EN			0x0010
602 #define ISCSIOPTS_DISCOVERY_AUTH_EN		0x0008
603 #define ISCSIOPTS_STRICT_LOGIN_COMP_EN		0x0004
604 #define ISCSIOPTS_ERL				0x0003
605 	uint16_t ipv4_tcp_opts;	/* 32-33 */
606 #define TCPOPT_DELAYED_ACK_DISABLE	0x8000
607 #define TCPOPT_DHCP_ENABLE		0x0200
608 #define TCPOPT_DNS_SERVER_IP_EN		0x0100
609 #define TCPOPT_SLP_DA_INFO_EN		0x0080
610 #define TCPOPT_NAGLE_ALGO_DISABLE	0x0020
611 #define TCPOPT_WINDOW_SCALE_DISABLE	0x0010
612 #define TCPOPT_TIMER_SCALE		0x000E
613 #define TCPOPT_TIMESTAMP_ENABLE		0x0001
614 	uint16_t ipv4_ip_opts;	/* 34-35 */
615 #define IPOPT_IPV4_PROTOCOL_ENABLE	0x8000
616 #define IPOPT_IPV4_TOS_EN		0x4000
617 #define IPOPT_VLAN_TAGGING_ENABLE	0x2000
618 #define IPOPT_GRAT_ARP_EN		0x1000
619 #define IPOPT_ALT_CID_EN		0x0800
620 #define IPOPT_REQ_VID_EN		0x0400
621 #define IPOPT_USE_VID_EN		0x0200
622 #define IPOPT_LEARN_IQN_EN		0x0100
623 #define IPOPT_FRAGMENTATION_DISABLE	0x0010
624 #define IPOPT_IN_FORWARD_EN		0x0008
625 #define IPOPT_ARP_REDIRECT_EN		0x0004
626 
627 	uint16_t iscsi_max_pdu_size;	/* 36-37 */
628 	uint8_t ipv4_tos;	/* 38 */
629 	uint8_t ipv4_ttl;	/* 39 */
630 	uint8_t acb_version;	/* 3A */
631 #define ACB_NOT_SUPPORTED		0x00
632 #define ACB_SUPPORTED			0x02 /* Capable of ACB Version 2
633 						Features */
634 
635 	uint8_t res2;	/* 3B */
636 	uint16_t def_timeout;	/* 3C-3D */
637 	uint16_t iscsi_fburst_len;	/* 3E-3F */
638 	uint16_t iscsi_def_time2wait;	/* 40-41 */
639 	uint16_t iscsi_def_time2retain;	/* 42-43 */
640 	uint16_t iscsi_max_outstnd_r2t;	/* 44-45 */
641 	uint16_t conn_ka_timeout;	/* 46-47 */
642 	uint16_t ipv4_port;	/* 48-49 */
643 	uint16_t iscsi_max_burst_len;	/* 4A-4B */
644 	uint32_t res5;		/* 4C-4F */
645 	uint8_t ipv4_addr[4];	/* 50-53 */
646 	uint16_t ipv4_vlan_tag;	/* 54-55 */
647 	uint8_t ipv4_addr_state;	/* 56 */
648 	uint8_t ipv4_cacheid;	/* 57 */
649 	uint8_t res6[8];	/* 58-5F */
650 	uint8_t ipv4_subnet[4];	/* 60-63 */
651 	uint8_t res7[12];	/* 64-6F */
652 	uint8_t ipv4_gw_addr[4];	/* 70-73 */
653 	uint8_t res8[0xc];	/* 74-7F */
654 	uint8_t pri_dns_srvr_ip[4];/* 80-83 */
655 	uint8_t sec_dns_srvr_ip[4];/* 84-87 */
656 	uint16_t min_eph_port;	/* 88-89 */
657 	uint16_t max_eph_port;	/* 8A-8B */
658 	uint8_t res9[4];	/* 8C-8F */
659 	uint8_t iscsi_alias[32];/* 90-AF */
660 	uint8_t res9_1[0x16];	/* B0-C5 */
661 	uint16_t tgt_portal_grp;/* C6-C7 */
662 	uint8_t abort_timer;	/* C8	 */
663 	uint8_t ipv4_tcp_wsf;	/* C9	 */
664 	uint8_t res10[6];	/* CA-CF */
665 	uint8_t ipv4_sec_ip_addr[4];	/* D0-D3 */
666 	uint8_t ipv4_dhcp_vid_len;	/* D4 */
667 	uint8_t ipv4_dhcp_vid[11];	/* D5-DF */
668 	uint8_t res11[20];	/* E0-F3 */
669 	uint8_t ipv4_dhcp_alt_cid_len;	/* F4 */
670 	uint8_t ipv4_dhcp_alt_cid[11];	/* F5-FF */
671 	uint8_t iscsi_name[224];	/* 100-1DF */
672 	uint8_t res12[32];	/* 1E0-1FF */
673 	uint32_t cookie;	/* 200-203 */
674 	uint16_t ipv6_port;	/* 204-205 */
675 	uint16_t ipv6_opts;	/* 206-207 */
676 #define IPV6_OPT_IPV6_PROTOCOL_ENABLE		0x8000
677 #define IPV6_OPT_VLAN_TAGGING_ENABLE		0x2000
678 #define IPV6_OPT_GRAT_NEIGHBOR_ADV_EN		0x1000
679 #define IPV6_OPT_REDIRECT_EN			0x0004
680 
681 	uint16_t ipv6_addtl_opts;	/* 208-209 */
682 #define IPV6_ADDOPT_IGNORE_ICMP_ECHO_REQ		0x0040
683 #define IPV6_ADDOPT_MLD_EN				0x0004
684 #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE	0x0002 /* Pri ACB
685 								  Only */
686 #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR		0x0001
687 
688 	uint16_t ipv6_tcp_opts;	/* 20A-20B */
689 #define IPV6_TCPOPT_DELAYED_ACK_DISABLE		0x8000
690 #define IPV6_TCPOPT_NAGLE_ALGO_DISABLE		0x0020
691 #define IPV6_TCPOPT_WINDOW_SCALE_DISABLE	0x0010
692 #define IPV6_TCPOPT_TIMER_SCALE			0x000E
693 #define IPV6_TCPOPT_TIMESTAMP_EN		0x0001
694 	uint8_t ipv6_tcp_wsf;	/* 20C */
695 	uint16_t ipv6_flow_lbl;	/* 20D-20F */
696 	uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */
697 	uint16_t ipv6_vlan_tag;	/* 220-221 */
698 	uint8_t ipv6_lnk_lcl_addr_state;/* 222 */
699 	uint8_t ipv6_addr0_state;	/* 223 */
700 	uint8_t ipv6_addr1_state;	/* 224 */
701 	uint8_t ipv6_dflt_rtr_state;    /* 225 */
702 #define IPV6_RTRSTATE_UNKNOWN                   0
703 #define IPV6_RTRSTATE_MANUAL                    1
704 #define IPV6_RTRSTATE_ADVERTISED                3
705 #define IPV6_RTRSTATE_STALE                     4
706 
707 	uint8_t ipv6_traffic_class;	/* 226 */
708 	uint8_t ipv6_hop_limit;	/* 227 */
709 	uint8_t ipv6_if_id[8];	/* 228-22F */
710 	uint8_t ipv6_addr0[16];	/* 230-23F */
711 	uint8_t ipv6_addr1[16];	/* 240-24F */
712 	uint32_t ipv6_nd_reach_time;	/* 250-253 */
713 	uint32_t ipv6_nd_rexmit_timer;	/* 254-257 */
714 	uint32_t ipv6_nd_stale_timeout;	/* 258-25B */
715 	uint8_t ipv6_dup_addr_detect_count;	/* 25C */
716 	uint8_t ipv6_cache_id;	/* 25D */
717 	uint8_t res13[18];	/* 25E-26F */
718 	uint32_t ipv6_gw_advrt_mtu;	/* 270-273 */
719 	uint8_t res14[140];	/* 274-2FF */
720 };
721 
722 #define IP_ADDR_COUNT	4 /* Total 4 IP address supported in one interface
723 			   * One IPv4, one IPv6 link local and 2 IPv6
724 			   */
725 
726 #define IP_STATE_MASK	0x0F000000
727 #define IP_STATE_SHIFT	24
728 
729 struct init_fw_ctrl_blk {
730 	struct addr_ctrl_blk pri;
731 /*	struct addr_ctrl_blk sec;*/
732 };
733 
734 #define PRIMARI_ACB		0
735 #define SECONDARY_ACB		1
736 
737 struct addr_ctrl_blk_def {
738 	uint8_t reserved1[1];	/* 00 */
739 	uint8_t control;	/* 01 */
740 	uint8_t reserved2[11];	/* 02-0C */
741 	uint8_t inst_num;	/* 0D */
742 	uint8_t reserved3[34];	/* 0E-2F */
743 	uint16_t iscsi_opts;	/* 30-31 */
744 	uint16_t ipv4_tcp_opts;	/* 32-33 */
745 	uint16_t ipv4_ip_opts;	/* 34-35 */
746 	uint16_t iscsi_max_pdu_size;	/* 36-37 */
747 	uint8_t ipv4_tos;	/* 38 */
748 	uint8_t ipv4_ttl;	/* 39 */
749 	uint8_t reserved4[2];	/* 3A-3B */
750 	uint16_t def_timeout;	/* 3C-3D */
751 	uint16_t iscsi_fburst_len;	/* 3E-3F */
752 	uint8_t reserved5[4];	/* 40-43 */
753 	uint16_t iscsi_max_outstnd_r2t;	/* 44-45 */
754 	uint8_t reserved6[2];	/* 46-47 */
755 	uint16_t ipv4_port;	/* 48-49 */
756 	uint16_t iscsi_max_burst_len;	/* 4A-4B */
757 	uint8_t reserved7[4];	/* 4C-4F */
758 	uint8_t ipv4_addr[4];	/* 50-53 */
759 	uint16_t ipv4_vlan_tag;	/* 54-55 */
760 	uint8_t ipv4_addr_state;	/* 56 */
761 	uint8_t ipv4_cacheid;	/* 57 */
762 	uint8_t reserved8[8];	/* 58-5F */
763 	uint8_t ipv4_subnet[4];	/* 60-63 */
764 	uint8_t reserved9[12];	/* 64-6F */
765 	uint8_t ipv4_gw_addr[4];	/* 70-73 */
766 	uint8_t reserved10[84];	/* 74-C7 */
767 	uint8_t abort_timer;	/* C8    */
768 	uint8_t ipv4_tcp_wsf;	/* C9    */
769 	uint8_t reserved11[10];	/* CA-D3 */
770 	uint8_t ipv4_dhcp_vid_len;	/* D4 */
771 	uint8_t ipv4_dhcp_vid[11];	/* D5-DF */
772 	uint8_t reserved12[20];	/* E0-F3 */
773 	uint8_t ipv4_dhcp_alt_cid_len;	/* F4 */
774 	uint8_t ipv4_dhcp_alt_cid[11];	/* F5-FF */
775 	uint8_t iscsi_name[224];	/* 100-1DF */
776 	uint8_t reserved13[32];	/* 1E0-1FF */
777 	uint32_t cookie;	/* 200-203 */
778 	uint16_t ipv6_port;	/* 204-205 */
779 	uint16_t ipv6_opts;	/* 206-207 */
780 	uint16_t ipv6_addtl_opts;	/* 208-209 */
781 	uint16_t ipv6_tcp_opts;		/* 20A-20B */
782 	uint8_t ipv6_tcp_wsf;		/* 20C */
783 	uint16_t ipv6_flow_lbl;		/* 20D-20F */
784 	uint8_t ipv6_dflt_rtr_addr[16];	/* 210-21F */
785 	uint16_t ipv6_vlan_tag;		/* 220-221 */
786 	uint8_t ipv6_lnk_lcl_addr_state;	/* 222 */
787 	uint8_t ipv6_addr0_state;	/* 223 */
788 	uint8_t ipv6_addr1_state;	/* 224 */
789 	uint8_t ipv6_dflt_rtr_state;	/* 225 */
790 	uint8_t ipv6_traffic_class;	/* 226 */
791 	uint8_t ipv6_hop_limit;		/* 227 */
792 	uint8_t ipv6_if_id[8];		/* 228-22F */
793 	uint8_t ipv6_addr0[16];		/* 230-23F */
794 	uint8_t ipv6_addr1[16];		/* 240-24F */
795 	uint32_t ipv6_nd_reach_time;	/* 250-253 */
796 	uint32_t ipv6_nd_rexmit_timer;	/* 254-257 */
797 	uint32_t ipv6_nd_stale_timeout;	/* 258-25B */
798 	uint8_t ipv6_dup_addr_detect_count;	/* 25C */
799 	uint8_t ipv6_cache_id;		/* 25D */
800 	uint8_t reserved14[18];		/* 25E-26F */
801 	uint32_t ipv6_gw_advrt_mtu;	/* 270-273 */
802 	uint8_t reserved15[140];	/* 274-2FF */
803 };
804 
805 /*************************************************************************/
806 
807 #define MAX_CHAP_ENTRIES_40XX	128
808 #define MAX_CHAP_ENTRIES_82XX	1024
809 #define MAX_RESRV_CHAP_IDX	3
810 #define FLASH_CHAP_OFFSET	0x06000000
811 
812 struct ql4_chap_table {
813 	uint16_t link;
814 	uint8_t flags;
815 	uint8_t secret_len;
816 #define MIN_CHAP_SECRET_LEN	12
817 #define MAX_CHAP_SECRET_LEN	100
818 	uint8_t secret[MAX_CHAP_SECRET_LEN];
819 #define MAX_CHAP_NAME_LEN	256
820 	uint8_t name[MAX_CHAP_NAME_LEN];
821 	uint16_t reserved;
822 #define CHAP_VALID_COOKIE	0x4092
823 #define CHAP_INVALID_COOKIE	0xFFEE
824 	uint16_t cookie;
825 };
826 
827 struct dev_db_entry {
828 	uint16_t options;	/* 00-01 */
829 #define DDB_OPT_DISC_SESSION  0x10
830 #define DDB_OPT_TARGET	      0x02 /* device is a target */
831 #define DDB_OPT_IPV6_DEVICE	0x100
832 #define DDB_OPT_AUTO_SENDTGTS_DISABLE		0x40
833 #define DDB_OPT_IPV6_NULL_LINK_LOCAL		0x800 /* post connection */
834 #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL	0x800 /* pre connection */
835 
836 #define OPT_IS_FW_ASSIGNED_IPV6		11
837 #define OPT_IPV6_DEVICE			8
838 #define OPT_AUTO_SENDTGTS_DISABLE	6
839 #define OPT_DISC_SESSION		4
840 #define OPT_ENTRY_STATE			3
841 	uint16_t exec_throttle;	/* 02-03 */
842 	uint16_t exec_count;	/* 04-05 */
843 	uint16_t res0;	/* 06-07 */
844 	uint16_t iscsi_options;	/* 08-09 */
845 #define ISCSIOPT_HEADER_DIGEST_EN		13
846 #define ISCSIOPT_DATA_DIGEST_EN			12
847 #define ISCSIOPT_IMMEDIATE_DATA_EN		11
848 #define ISCSIOPT_INITIAL_R2T_EN			10
849 #define ISCSIOPT_DATA_SEQ_IN_ORDER		9
850 #define ISCSIOPT_DATA_PDU_IN_ORDER		8
851 #define ISCSIOPT_CHAP_AUTH_EN			7
852 #define ISCSIOPT_SNACK_REQ_EN			6
853 #define ISCSIOPT_DISCOVERY_LOGOUT_EN		5
854 #define ISCSIOPT_BIDI_CHAP_EN			4
855 #define ISCSIOPT_DISCOVERY_AUTH_OPTIONAL	3
856 #define ISCSIOPT_ERL1				1
857 #define ISCSIOPT_ERL0				0
858 
859 	uint16_t tcp_options;	/* 0A-0B */
860 #define TCPOPT_TIMESTAMP_STAT	6
861 #define TCPOPT_NAGLE_DISABLE	5
862 #define TCPOPT_WSF_DISABLE	4
863 #define TCPOPT_TIMER_SCALE3	3
864 #define TCPOPT_TIMER_SCALE2	2
865 #define TCPOPT_TIMER_SCALE1	1
866 #define TCPOPT_TIMESTAMP_EN	0
867 
868 	uint16_t ip_options;	/* 0C-0D */
869 #define IPOPT_FRAGMENT_DISABLE	4
870 
871 	uint16_t iscsi_max_rcv_data_seg_len;	/* 0E-0F */
872 #define BYTE_UNITS	512
873 	uint32_t res1;	/* 10-13 */
874 	uint16_t iscsi_max_snd_data_seg_len;	/* 14-15 */
875 	uint16_t iscsi_first_burst_len;	/* 16-17 */
876 	uint16_t iscsi_def_time2wait;	/* 18-19 */
877 	uint16_t iscsi_def_time2retain;	/* 1A-1B */
878 	uint16_t iscsi_max_outsnd_r2t;	/* 1C-1D */
879 	uint16_t ka_timeout;	/* 1E-1F */
880 	uint8_t isid[6];	/* 20-25 big-endian, must be converted
881 				 * to little-endian */
882 	uint16_t tsid;		/* 26-27 */
883 	uint16_t port;	/* 28-29 */
884 	uint16_t iscsi_max_burst_len;	/* 2A-2B */
885 	uint16_t def_timeout;	/* 2C-2D */
886 	uint16_t res2;	/* 2E-2F */
887 	uint8_t ip_addr[0x10];	/* 30-3F */
888 	uint8_t iscsi_alias[0x20];	/* 40-5F */
889 	uint8_t tgt_addr[0x20];	/* 60-7F */
890 	uint16_t mss;	/* 80-81 */
891 	uint16_t res3;	/* 82-83 */
892 	uint16_t lcl_port;	/* 84-85 */
893 	uint8_t ipv4_tos;	/* 86 */
894 	uint16_t ipv6_flow_lbl;	/* 87-89 */
895 	uint8_t res4[0x36];	/* 8A-BF */
896 	uint8_t iscsi_name[0xE0];	/* C0-19F : xxzzy Make this a
897 					 * pointer to a string so we
898 					 * don't have to reserve so
899 					 * much RAM */
900 	uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */
901 	uint8_t res5[0x10];	/* 1B0-1BF */
902 #define DDB_NO_LINK	0xFFFF
903 #define DDB_ISNS	0xFFFD
904 	uint16_t ddb_link;	/* 1C0-1C1 */
905 	uint16_t chap_tbl_idx;	/* 1C2-1C3 */
906 	uint16_t tgt_portal_grp; /* 1C4-1C5 */
907 	uint8_t tcp_xmt_wsf;	/* 1C6 */
908 	uint8_t tcp_rcv_wsf;	/* 1C7 */
909 	uint32_t stat_sn;	/* 1C8-1CB */
910 	uint32_t exp_stat_sn;	/* 1CC-1CF */
911 	uint8_t res6[0x2b];	/* 1D0-1FB */
912 #define DDB_VALID_COOKIE	0x9034
913 	uint16_t cookie;	/* 1FC-1FD */
914 	uint16_t len;		/* 1FE-1FF */
915 };
916 
917 /*************************************************************************/
918 
919 /* Flash definitions */
920 
921 #define FLASH_OFFSET_SYS_INFO	0x02000000
922 #define FLASH_DEFAULTBLOCKSIZE	0x20000
923 #define FLASH_EOF_OFFSET	(FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
924 							    * for EOF
925 							    * signature */
926 #define FLASH_RAW_ACCESS_ADDR	0x8e000000
927 
928 #define BOOT_PARAM_OFFSET_PORT0 0x3b0
929 #define BOOT_PARAM_OFFSET_PORT1 0x7b0
930 
931 #define FLASH_OFFSET_DB_INFO	0x05000000
932 #define FLASH_OFFSET_DB_END	(FLASH_OFFSET_DB_INFO + 0x7fff)
933 
934 
935 struct sys_info_phys_addr {
936 	uint8_t address[6];	/* 00-05 */
937 	uint8_t filler[2];	/* 06-07 */
938 };
939 
940 struct flash_sys_info {
941 	uint32_t cookie;	/* 00-03 */
942 	uint32_t physAddrCount; /* 04-07 */
943 	struct sys_info_phys_addr physAddr[4]; /* 08-27 */
944 	uint8_t vendorId[128];	/* 28-A7 */
945 	uint8_t productId[128]; /* A8-127 */
946 	uint32_t serialNumber;	/* 128-12B */
947 
948 	/*  PCI Configuration values */
949 	uint32_t pciDeviceVendor;	/* 12C-12F */
950 	uint32_t pciDeviceId;	/* 130-133 */
951 	uint32_t pciSubsysVendor;	/* 134-137 */
952 	uint32_t pciSubsysId;	/* 138-13B */
953 
954 	/*  This validates version 1. */
955 	uint32_t crumbs;	/* 13C-13F */
956 
957 	uint32_t enterpriseNumber;	/* 140-143 */
958 
959 	uint32_t mtu;		/* 144-147 */
960 	uint32_t reserved0;	/* 148-14b */
961 	uint32_t crumbs2;	/* 14c-14f */
962 	uint8_t acSerialNumber[16];	/* 150-15f */
963 	uint32_t crumbs3;	/* 160-16f */
964 
965 	/* Leave this last in the struct so it is declared invalid if
966 	 * any new items are added.
967 	 */
968 	uint32_t reserved1[39]; /* 170-1ff */
969 };	/* 200 */
970 
971 struct mbx_sys_info {
972 	uint8_t board_id_str[16];   /*  0-f  Keep board ID string first */
973 				/* in this structure for GUI. */
974 	uint16_t board_id;	/* 10-11 board ID code */
975 	uint16_t phys_port_cnt;	/* 12-13 number of physical network ports */
976 	uint16_t port_num;	/* 14-15 network port for this PCI function */
977 				/* (port 0 is first port) */
978 	uint8_t mac_addr[6];	/* 16-1b MAC address for this PCI function */
979 	uint32_t iscsi_pci_func_cnt;  /* 1c-1f number of iSCSI PCI functions */
980 	uint32_t pci_func;	      /* 20-23 this PCI function */
981 	unsigned char serial_number[16];  /* 24-33 serial number string */
982 	uint8_t reserved[12];		  /* 34-3f */
983 };
984 
985 struct about_fw_info {
986 	uint16_t fw_major;		/* 00 - 01 */
987 	uint16_t fw_minor;		/* 02 - 03 */
988 	uint16_t fw_patch;		/* 04 - 05 */
989 	uint16_t fw_build;		/* 06 - 07 */
990 	uint8_t fw_build_date[16];	/* 08 - 17 ASCII String */
991 	uint8_t fw_build_time[16];	/* 18 - 27 ASCII String */
992 	uint8_t fw_build_user[16];	/* 28 - 37 ASCII String */
993 	uint16_t fw_load_source;	/* 38 - 39 */
994 					/* 1 = Flash Primary,
995 					   2 = Flash Secondary,
996 					   3 = Host Download
997 					*/
998 	uint8_t reserved1[6];		/* 3A - 3F */
999 	uint16_t iscsi_major;		/* 40 - 41 */
1000 	uint16_t iscsi_minor;		/* 42 - 43 */
1001 	uint16_t bootload_major;	/* 44 - 45 */
1002 	uint16_t bootload_minor;	/* 46 - 47 */
1003 	uint16_t bootload_patch;	/* 48 - 49 */
1004 	uint16_t bootload_build;	/* 4A - 4B */
1005 	uint8_t extended_timestamp[180];/* 4C - FF */
1006 };
1007 
1008 struct crash_record {
1009 	uint16_t fw_major_version;	/* 00 - 01 */
1010 	uint16_t fw_minor_version;	/* 02 - 03 */
1011 	uint16_t fw_patch_version;	/* 04 - 05 */
1012 	uint16_t fw_build_version;	/* 06 - 07 */
1013 
1014 	uint8_t build_date[16]; /* 08 - 17 */
1015 	uint8_t build_time[16]; /* 18 - 27 */
1016 	uint8_t build_user[16]; /* 28 - 37 */
1017 	uint8_t card_serial_num[16];	/* 38 - 47 */
1018 
1019 	uint32_t time_of_crash_in_secs; /* 48 - 4B */
1020 	uint32_t time_of_crash_in_ms;	/* 4C - 4F */
1021 
1022 	uint16_t out_RISC_sd_num_frames;	/* 50 - 51 */
1023 	uint16_t OAP_sd_num_words;	/* 52 - 53 */
1024 	uint16_t IAP_sd_num_frames;	/* 54 - 55 */
1025 	uint16_t in_RISC_sd_num_words;	/* 56 - 57 */
1026 
1027 	uint8_t reserved1[28];	/* 58 - 7F */
1028 
1029 	uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
1030 	uint8_t in_RISC_reg_dump[256];	/*180 -27F */
1031 	uint8_t in_out_RISC_stack_dump[0];	/*280 - ??? */
1032 };
1033 
1034 struct conn_event_log_entry {
1035 #define MAX_CONN_EVENT_LOG_ENTRIES	100
1036 	uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
1037 	uint32_t timestamp_ms;	/* 04 - 07 milliseconds since boot */
1038 	uint16_t device_index;	/* 08 - 09  */
1039 	uint16_t fw_conn_state; /* 0A - 0B  */
1040 	uint8_t event_type;	/* 0C - 0C  */
1041 	uint8_t error_code;	/* 0D - 0D  */
1042 	uint16_t error_code_detail;	/* 0E - 0F  */
1043 	uint8_t num_consecutive_events; /* 10 - 10  */
1044 	uint8_t rsvd[3];	/* 11 - 13  */
1045 };
1046 
1047 /*************************************************************************
1048  *
1049  *				IOCB Commands Structures and Definitions
1050  *
1051  *************************************************************************/
1052 #define IOCB_MAX_CDB_LEN	    16	/* Bytes in a CBD */
1053 #define IOCB_MAX_SENSEDATA_LEN	    32	/* Bytes of sense data */
1054 #define IOCB_MAX_EXT_SENSEDATA_LEN  60  /* Bytes of extended sense data */
1055 
1056 /* IOCB header structure */
1057 struct qla4_header {
1058 	uint8_t entryType;
1059 #define ET_STATUS		 0x03
1060 #define ET_MARKER		 0x04
1061 #define ET_CONT_T1		 0x0A
1062 #define ET_STATUS_CONTINUATION	 0x10
1063 #define ET_CMND_T3		 0x19
1064 #define ET_PASSTHRU0		 0x3A
1065 #define ET_PASSTHRU_STATUS	 0x3C
1066 #define ET_MBOX_CMD		0x38
1067 #define ET_MBOX_STATUS		0x39
1068 
1069 	uint8_t entryStatus;
1070 	uint8_t systemDefined;
1071 #define SD_ISCSI_PDU	0x01
1072 	uint8_t entryCount;
1073 
1074 	/* SyetemDefined definition */
1075 };
1076 
1077 /* Generic queue entry structure*/
1078 struct queue_entry {
1079 	uint8_t data[60];
1080 	uint32_t signature;
1081 
1082 };
1083 
1084 /* 64 bit addressing segment counts*/
1085 
1086 #define COMMAND_SEG_A64	  1
1087 #define CONTINUE_SEG_A64  5
1088 
1089 /* 64 bit addressing segment definition*/
1090 
1091 struct data_seg_a64 {
1092 	struct {
1093 		uint32_t addrLow;
1094 		uint32_t addrHigh;
1095 
1096 	} base;
1097 
1098 	uint32_t count;
1099 
1100 };
1101 
1102 /* Command Type 3 entry structure*/
1103 
1104 struct command_t3_entry {
1105 	struct qla4_header hdr;	/* 00-03 */
1106 
1107 	uint32_t handle;	/* 04-07 */
1108 	uint16_t target;	/* 08-09 */
1109 	uint16_t connection_id; /* 0A-0B */
1110 
1111 	uint8_t control_flags;	/* 0C */
1112 
1113 	/* data direction  (bits 5-6) */
1114 #define CF_WRITE		0x20
1115 #define CF_READ			0x40
1116 #define CF_NO_DATA		0x00
1117 
1118 	/* task attributes (bits 2-0) */
1119 #define CF_HEAD_TAG		0x03
1120 #define CF_ORDERED_TAG		0x02
1121 #define CF_SIMPLE_TAG		0x01
1122 
1123 	/* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
1124 	 * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
1125 	 * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
1126 	 * PROPERLY.
1127 	 */
1128 	uint8_t state_flags;	/* 0D */
1129 	uint8_t cmdRefNum;	/* 0E */
1130 	uint8_t reserved1;	/* 0F */
1131 	uint8_t cdb[IOCB_MAX_CDB_LEN];	/* 10-1F */
1132 	struct scsi_lun lun;	/* FCP LUN (BE). */
1133 	uint32_t cmdSeqNum;	/* 28-2B */
1134 	uint16_t timeout;	/* 2C-2D */
1135 	uint16_t dataSegCnt;	/* 2E-2F */
1136 	uint32_t ttlByteCnt;	/* 30-33 */
1137 	struct data_seg_a64 dataseg[COMMAND_SEG_A64];	/* 34-3F */
1138 
1139 };
1140 
1141 
1142 /* Continuation Type 1 entry structure*/
1143 struct continuation_t1_entry {
1144 	struct qla4_header hdr;
1145 
1146 	struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
1147 
1148 };
1149 
1150 /* Parameterize for 64 or 32 bits */
1151 #define COMMAND_SEG	COMMAND_SEG_A64
1152 #define CONTINUE_SEG	CONTINUE_SEG_A64
1153 
1154 #define ET_COMMAND	ET_CMND_T3
1155 #define ET_CONTINUE	ET_CONT_T1
1156 
1157 /* Marker entry structure*/
1158 struct qla4_marker_entry {
1159 	struct qla4_header hdr;	/* 00-03 */
1160 
1161 	uint32_t system_defined; /* 04-07 */
1162 	uint16_t target;	/* 08-09 */
1163 	uint16_t modifier;	/* 0A-0B */
1164 #define MM_LUN_RESET		0
1165 #define MM_TGT_WARM_RESET	1
1166 
1167 	uint16_t flags;		/* 0C-0D */
1168 	uint16_t reserved1;	/* 0E-0F */
1169 	struct scsi_lun lun;	/* FCP LUN (BE). */
1170 	uint64_t reserved2;	/* 18-1F */
1171 	uint64_t reserved3;	/* 20-27 */
1172 	uint64_t reserved4;	/* 28-2F */
1173 	uint64_t reserved5;	/* 30-37 */
1174 	uint64_t reserved6;	/* 38-3F */
1175 };
1176 
1177 /* Status entry structure*/
1178 struct status_entry {
1179 	struct qla4_header hdr;	/* 00-03 */
1180 
1181 	uint32_t handle;	/* 04-07 */
1182 
1183 	uint8_t scsiStatus;	/* 08 */
1184 
1185 	uint8_t iscsiFlags;	/* 09 */
1186 #define ISCSI_FLAG_RESIDUAL_UNDER	  0x02
1187 #define ISCSI_FLAG_RESIDUAL_OVER	  0x04
1188 
1189 	uint8_t iscsiResponse;	/* 0A */
1190 
1191 	uint8_t completionStatus;	/* 0B */
1192 #define SCS_COMPLETE			  0x00
1193 #define SCS_INCOMPLETE			  0x01
1194 #define SCS_RESET_OCCURRED		  0x04
1195 #define SCS_ABORTED			  0x05
1196 #define SCS_TIMEOUT			  0x06
1197 #define SCS_DATA_OVERRUN		  0x07
1198 #define SCS_DATA_UNDERRUN		  0x15
1199 #define SCS_QUEUE_FULL			  0x1C
1200 #define SCS_DEVICE_UNAVAILABLE		  0x28
1201 #define SCS_DEVICE_LOGGED_OUT		  0x29
1202 
1203 	uint8_t reserved1;	/* 0C */
1204 
1205 	/* state_flags MUST be at the same location as state_flags in
1206 	 * the Command_T3/4_Entry */
1207 	uint8_t state_flags;	/* 0D */
1208 
1209 	uint16_t senseDataByteCnt;	/* 0E-0F */
1210 	uint32_t residualByteCnt;	/* 10-13 */
1211 	uint32_t bidiResidualByteCnt;	/* 14-17 */
1212 	uint32_t expSeqNum;	/* 18-1B */
1213 	uint32_t maxCmdSeqNum;	/* 1C-1F */
1214 	uint8_t senseData[IOCB_MAX_SENSEDATA_LEN];	/* 20-3F */
1215 
1216 };
1217 
1218 /* Status Continuation entry */
1219 struct status_cont_entry {
1220        struct qla4_header hdr; /* 00-03 */
1221        uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */
1222 };
1223 
1224 struct passthru0 {
1225 	struct qla4_header hdr;		       /* 00-03 */
1226 	uint32_t handle;	/* 04-07 */
1227 	uint16_t target;	/* 08-09 */
1228 	uint16_t connection_id;	/* 0A-0B */
1229 #define ISNS_DEFAULT_SERVER_CONN_ID	((uint16_t)0x8000)
1230 
1231 	uint16_t control_flags;	/* 0C-0D */
1232 #define PT_FLAG_ETHERNET_FRAME		0x8000
1233 #define PT_FLAG_ISNS_PDU		0x8000
1234 #define PT_FLAG_SEND_BUFFER		0x0200
1235 #define PT_FLAG_WAIT_4_RESPONSE		0x0100
1236 #define PT_FLAG_ISCSI_PDU		0x1000
1237 
1238 	uint16_t timeout;	/* 0E-0F */
1239 #define PT_DEFAULT_TIMEOUT		30 /* seconds */
1240 
1241 	struct data_seg_a64 out_dsd;    /* 10-1B */
1242 	uint32_t res1;		/* 1C-1F */
1243 	struct data_seg_a64 in_dsd;     /* 20-2B */
1244 	uint8_t res2[20];	/* 2C-3F */
1245 };
1246 
1247 struct passthru_status {
1248 	struct qla4_header hdr;		       /* 00-03 */
1249 	uint32_t handle;	/* 04-07 */
1250 	uint16_t target;	/* 08-09 */
1251 	uint16_t connectionID;	/* 0A-0B */
1252 
1253 	uint8_t completionStatus;	/* 0C */
1254 #define PASSTHRU_STATUS_COMPLETE		0x01
1255 
1256 	uint8_t residualFlags;	/* 0D */
1257 
1258 	uint16_t timeout;	/* 0E-0F */
1259 	uint16_t portNumber;	/* 10-11 */
1260 	uint8_t res1[10];	/* 12-1B */
1261 	uint32_t outResidual;	/* 1C-1F */
1262 	uint8_t res2[12];	/* 20-2B */
1263 	uint32_t inResidual;	/* 2C-2F */
1264 	uint8_t res4[16];	/* 30-3F */
1265 };
1266 
1267 struct mbox_cmd_iocb {
1268 	struct qla4_header hdr;	/* 00-03 */
1269 	uint32_t handle;	/* 04-07 */
1270 	uint32_t in_mbox[8];	/* 08-25 */
1271 	uint32_t res1[6];	/* 26-3F */
1272 };
1273 
1274 struct mbox_status_iocb {
1275 	struct qla4_header hdr;	/* 00-03 */
1276 	uint32_t handle;	/* 04-07 */
1277 	uint32_t out_mbox[8];	/* 08-25 */
1278 	uint32_t res1[6];	/* 26-3F */
1279 };
1280 
1281 /*
1282  * ISP queue - response queue entry definition.
1283  */
1284 struct response {
1285 	uint8_t data[60];
1286 	uint32_t signature;
1287 #define RESPONSE_PROCESSED	0xDEADDEAD	/* Signature */
1288 };
1289 
1290 struct ql_iscsi_stats {
1291 	uint64_t mac_tx_frames; /* 0000–0007 */
1292 	uint64_t mac_tx_bytes; /* 0008–000F */
1293 	uint64_t mac_tx_multicast_frames; /* 0010–0017 */
1294 	uint64_t mac_tx_broadcast_frames; /* 0018–001F */
1295 	uint64_t mac_tx_pause_frames; /* 0020–0027 */
1296 	uint64_t mac_tx_control_frames; /* 0028–002F */
1297 	uint64_t mac_tx_deferral; /* 0030–0037 */
1298 	uint64_t mac_tx_excess_deferral; /* 0038–003F */
1299 	uint64_t mac_tx_late_collision; /* 0040–0047 */
1300 	uint64_t mac_tx_abort; /* 0048–004F */
1301 	uint64_t mac_tx_single_collision; /* 0050–0057 */
1302 	uint64_t mac_tx_multiple_collision; /* 0058–005F */
1303 	uint64_t mac_tx_collision; /* 0060–0067 */
1304 	uint64_t mac_tx_frames_dropped; /* 0068–006F */
1305 	uint64_t mac_tx_jumbo_frames; /* 0070–0077 */
1306 	uint64_t mac_rx_frames; /* 0078–007F */
1307 	uint64_t mac_rx_bytes; /* 0080–0087 */
1308 	uint64_t mac_rx_unknown_control_frames; /* 0088–008F */
1309 	uint64_t mac_rx_pause_frames; /* 0090–0097 */
1310 	uint64_t mac_rx_control_frames; /* 0098–009F */
1311 	uint64_t mac_rx_dribble; /* 00A0–00A7 */
1312 	uint64_t mac_rx_frame_length_error; /* 00A8–00AF */
1313 	uint64_t mac_rx_jabber; /* 00B0–00B7 */
1314 	uint64_t mac_rx_carrier_sense_error; /* 00B8–00BF */
1315 	uint64_t mac_rx_frame_discarded; /* 00C0–00C7 */
1316 	uint64_t mac_rx_frames_dropped; /* 00C8–00CF */
1317 	uint64_t mac_crc_error; /* 00D0–00D7 */
1318 	uint64_t mac_encoding_error; /* 00D8–00DF */
1319 	uint64_t mac_rx_length_error_large; /* 00E0–00E7 */
1320 	uint64_t mac_rx_length_error_small; /* 00E8–00EF */
1321 	uint64_t mac_rx_multicast_frames; /* 00F0–00F7 */
1322 	uint64_t mac_rx_broadcast_frames; /* 00F8–00FF */
1323 	uint64_t ip_tx_packets; /* 0100–0107 */
1324 	uint64_t ip_tx_bytes; /* 0108–010F */
1325 	uint64_t ip_tx_fragments; /* 0110–0117 */
1326 	uint64_t ip_rx_packets; /* 0118–011F */
1327 	uint64_t ip_rx_bytes; /* 0120–0127 */
1328 	uint64_t ip_rx_fragments; /* 0128–012F */
1329 	uint64_t ip_datagram_reassembly; /* 0130–0137 */
1330 	uint64_t ip_invalid_address_error; /* 0138–013F */
1331 	uint64_t ip_error_packets; /* 0140–0147 */
1332 	uint64_t ip_fragrx_overlap; /* 0148–014F */
1333 	uint64_t ip_fragrx_outoforder; /* 0150–0157 */
1334 	uint64_t ip_datagram_reassembly_timeout; /* 0158–015F */
1335 	uint64_t ipv6_tx_packets; /* 0160–0167 */
1336 	uint64_t ipv6_tx_bytes; /* 0168–016F */
1337 	uint64_t ipv6_tx_fragments; /* 0170–0177 */
1338 	uint64_t ipv6_rx_packets; /* 0178–017F */
1339 	uint64_t ipv6_rx_bytes; /* 0180–0187 */
1340 	uint64_t ipv6_rx_fragments; /* 0188–018F */
1341 	uint64_t ipv6_datagram_reassembly; /* 0190–0197 */
1342 	uint64_t ipv6_invalid_address_error; /* 0198–019F */
1343 	uint64_t ipv6_error_packets; /* 01A0–01A7 */
1344 	uint64_t ipv6_fragrx_overlap; /* 01A8–01AF */
1345 	uint64_t ipv6_fragrx_outoforder; /* 01B0–01B7 */
1346 	uint64_t ipv6_datagram_reassembly_timeout; /* 01B8–01BF */
1347 	uint64_t tcp_tx_segments; /* 01C0–01C7 */
1348 	uint64_t tcp_tx_bytes; /* 01C8–01CF */
1349 	uint64_t tcp_rx_segments; /* 01D0–01D7 */
1350 	uint64_t tcp_rx_byte; /* 01D8–01DF */
1351 	uint64_t tcp_duplicate_ack_retx; /* 01E0–01E7 */
1352 	uint64_t tcp_retx_timer_expired; /* 01E8–01EF */
1353 	uint64_t tcp_rx_duplicate_ack; /* 01F0–01F7 */
1354 	uint64_t tcp_rx_pure_ackr; /* 01F8–01FF */
1355 	uint64_t tcp_tx_delayed_ack; /* 0200–0207 */
1356 	uint64_t tcp_tx_pure_ack; /* 0208–020F */
1357 	uint64_t tcp_rx_segment_error; /* 0210–0217 */
1358 	uint64_t tcp_rx_segment_outoforder; /* 0218–021F */
1359 	uint64_t tcp_rx_window_probe; /* 0220–0227 */
1360 	uint64_t tcp_rx_window_update; /* 0228–022F */
1361 	uint64_t tcp_tx_window_probe_persist; /* 0230–0237 */
1362 	uint64_t ecc_error_correction; /* 0238–023F */
1363 	uint64_t iscsi_pdu_tx; /* 0240-0247 */
1364 	uint64_t iscsi_data_bytes_tx; /* 0248-024F */
1365 	uint64_t iscsi_pdu_rx; /* 0250-0257 */
1366 	uint64_t iscsi_data_bytes_rx; /* 0258-025F */
1367 	uint64_t iscsi_io_completed; /* 0260-0267 */
1368 	uint64_t iscsi_unexpected_io_rx; /* 0268-026F */
1369 	uint64_t iscsi_format_error; /* 0270-0277 */
1370 	uint64_t iscsi_hdr_digest_error; /* 0278-027F */
1371 	uint64_t iscsi_data_digest_error; /* 0280-0287 */
1372 	uint64_t iscsi_sequence_error; /* 0288-028F */
1373 	uint32_t tx_cmd_pdu; /* 0290-0293 */
1374 	uint32_t tx_resp_pdu; /* 0294-0297 */
1375 	uint32_t rx_cmd_pdu; /* 0298-029B */
1376 	uint32_t rx_resp_pdu; /* 029C-029F */
1377 
1378 	uint64_t tx_data_octets; /* 02A0-02A7 */
1379 	uint64_t rx_data_octets; /* 02A8-02AF */
1380 
1381 	uint32_t hdr_digest_err; /* 02B0–02B3 */
1382 	uint32_t data_digest_err; /* 02B4–02B7 */
1383 	uint32_t conn_timeout_err; /* 02B8–02BB */
1384 	uint32_t framing_err; /* 02BC–02BF */
1385 
1386 	uint32_t tx_nopout_pdus; /* 02C0–02C3 */
1387 	uint32_t tx_scsi_cmd_pdus;  /* 02C4–02C7 */
1388 	uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */
1389 	uint32_t tx_login_cmd_pdus; /* 02CC–02CF */
1390 	uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */
1391 	uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */
1392 	uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */
1393 	uint32_t tx_snack_req_pdus; /* 02DC–02DF */
1394 
1395 	uint32_t rx_nopin_pdus; /* 02E0–02E3 */
1396 	uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */
1397 	uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */
1398 	uint32_t rx_login_resp_pdus; /* 02EC–02EF */
1399 	uint32_t rx_text_resp_pdus; /* 02F0–02F3 */
1400 	uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */
1401 	uint32_t rx_logout_resp_pdus; /* 02F8–02FB */
1402 
1403 	uint32_t rx_r2t_pdus; /* 02FC–02FF */
1404 	uint32_t rx_async_pdus; /* 0300–0303 */
1405 	uint32_t rx_reject_pdus; /* 0304–0307 */
1406 
1407 	uint8_t reserved2[264]; /* 0x0308 - 0x040F */
1408 };
1409 
1410 #define QLA8XXX_DBG_STATE_ARRAY_LEN		16
1411 #define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN		8
1412 #define QLA8XXX_DBG_RSVD_ARRAY_LEN		8
1413 #define QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN	16
1414 #define QLA83XX_SS_OCM_WNDREG_INDEX		3
1415 #define QLA83XX_SS_PCI_INDEX			0
1416 #define QLA8022_TEMPLATE_CAP_OFFSET		172
1417 #define QLA83XX_TEMPLATE_CAP_OFFSET		268
1418 #define QLA80XX_TEMPLATE_RESERVED_BITS		16
1419 
1420 struct qla4_8xxx_minidump_template_hdr {
1421 	uint32_t entry_type;
1422 	uint32_t first_entry_offset;
1423 	uint32_t size_of_template;
1424 	uint32_t capture_debug_level;
1425 	uint32_t num_of_entries;
1426 	uint32_t version;
1427 	uint32_t driver_timestamp;
1428 	uint32_t checksum;
1429 
1430 	uint32_t driver_capture_mask;
1431 	uint32_t driver_info_word2;
1432 	uint32_t driver_info_word3;
1433 	uint32_t driver_info_word4;
1434 
1435 	uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN];
1436 	uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN];
1437 	uint32_t ocm_window_reg[QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN];
1438 	uint32_t capabilities[QLA80XX_TEMPLATE_RESERVED_BITS];
1439 };
1440 
1441 #endif /*  _QLA4X_FW_H */
1442