1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8 #ifndef _QLA4X_FW_H 9 #define _QLA4X_FW_H 10 11 12 #define MAX_PRST_DEV_DB_ENTRIES 64 13 #define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES 14 #define MAX_DEV_DB_ENTRIES 512 15 16 /************************************************************************* 17 * 18 * ISP 4010 I/O Register Set Structure and Definitions 19 * 20 *************************************************************************/ 21 22 struct port_ctrl_stat_regs { 23 __le32 ext_hw_conf; /* 0x50 R/W */ 24 __le32 rsrvd0; /* 0x54 */ 25 __le32 port_ctrl; /* 0x58 */ 26 __le32 port_status; /* 0x5c */ 27 __le32 rsrvd1[32]; /* 0x60-0xdf */ 28 __le32 gp_out; /* 0xe0 */ 29 __le32 gp_in; /* 0xe4 */ 30 __le32 rsrvd2[5]; /* 0xe8-0xfb */ 31 __le32 port_err_status; /* 0xfc */ 32 }; 33 34 struct host_mem_cfg_regs { 35 __le32 rsrvd0[12]; /* 0x50-0x79 */ 36 __le32 req_q_out; /* 0x80 */ 37 __le32 rsrvd1[31]; /* 0x84-0xFF */ 38 }; 39 40 /* 41 * ISP 82xx I/O Register Set structure definitions. 42 */ 43 struct device_reg_82xx { 44 __le32 req_q_out; /* 0x0000 (R): Request Queue out-Pointer. */ 45 __le32 reserve1[63]; /* Request Queue out-Pointer. (64 * 4) */ 46 __le32 rsp_q_in; /* 0x0100 (R/W): Response Queue In-Pointer. */ 47 __le32 reserve2[63]; /* Response Queue In-Pointer. */ 48 __le32 rsp_q_out; /* 0x0200 (R/W): Response Queue Out-Pointer. */ 49 __le32 reserve3[63]; /* Response Queue Out-Pointer. */ 50 51 __le32 mailbox_in[8]; /* 0x0300 (R/W): Mail box In registers */ 52 __le32 reserve4[24]; 53 __le32 hint; /* 0x0380 (R/W): Host interrupt register */ 54 #define HINT_MBX_INT_PENDING BIT_0 55 __le32 reserve5[31]; 56 __le32 mailbox_out[8]; /* 0x0400 (R): Mail box Out registers */ 57 __le32 reserve6[56]; 58 59 __le32 host_status; /* Offset 0x500 (R): host status */ 60 #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */ 61 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */ 62 63 __le32 host_int; /* Offset 0x0504 (R/W): Interrupt status. */ 64 #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */ 65 }; 66 67 /* remote register set (access via PCI memory read/write) */ 68 struct isp_reg { 69 #define MBOX_REG_COUNT 8 70 __le32 mailbox[MBOX_REG_COUNT]; 71 72 __le32 flash_address; /* 0x20 */ 73 __le32 flash_data; 74 __le32 ctrl_status; 75 76 union { 77 struct { 78 __le32 nvram; 79 __le32 reserved1[2]; /* 0x30 */ 80 } __attribute__ ((packed)) isp4010; 81 struct { 82 __le32 intr_mask; 83 __le32 nvram; /* 0x30 */ 84 __le32 semaphore; 85 } __attribute__ ((packed)) isp4022; 86 } u1; 87 88 __le32 req_q_in; /* SCSI Request Queue Producer Index */ 89 __le32 rsp_q_out; /* SCSI Completion Queue Consumer Index */ 90 91 __le32 reserved2[4]; /* 0x40 */ 92 93 union { 94 struct { 95 __le32 ext_hw_conf; /* 0x50 */ 96 __le32 flow_ctrl; 97 __le32 port_ctrl; 98 __le32 port_status; 99 100 __le32 reserved3[8]; /* 0x60 */ 101 102 __le32 req_q_out; /* 0x80 */ 103 104 __le32 reserved4[23]; /* 0x84 */ 105 106 __le32 gp_out; /* 0xe0 */ 107 __le32 gp_in; 108 109 __le32 reserved5[5]; 110 111 __le32 port_err_status; /* 0xfc */ 112 } __attribute__ ((packed)) isp4010; 113 struct { 114 union { 115 struct port_ctrl_stat_regs p0; 116 struct host_mem_cfg_regs p1; 117 }; 118 } __attribute__ ((packed)) isp4022; 119 } u2; 120 }; /* 256 x100 */ 121 122 123 /* Semaphore Defines for 4010 */ 124 #define QL4010_DRVR_SEM_BITS 0x00000030 125 #define QL4010_GPIO_SEM_BITS 0x000000c0 126 #define QL4010_SDRAM_SEM_BITS 0x00000300 127 #define QL4010_PHY_SEM_BITS 0x00000c00 128 #define QL4010_NVRAM_SEM_BITS 0x00003000 129 #define QL4010_FLASH_SEM_BITS 0x0000c000 130 131 #define QL4010_DRVR_SEM_MASK 0x00300000 132 #define QL4010_GPIO_SEM_MASK 0x00c00000 133 #define QL4010_SDRAM_SEM_MASK 0x03000000 134 #define QL4010_PHY_SEM_MASK 0x0c000000 135 #define QL4010_NVRAM_SEM_MASK 0x30000000 136 #define QL4010_FLASH_SEM_MASK 0xc0000000 137 138 /* Semaphore Defines for 4022 */ 139 #define QL4022_RESOURCE_MASK_BASE_CODE 0x7 140 #define QL4022_RESOURCE_BITS_BASE_CODE 0x4 141 142 143 #define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16)) 144 #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16)) 145 #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16)) 146 #define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16)) 147 #define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16)) 148 149 150 151 /* Page # defines for 4022 */ 152 #define PORT_CTRL_STAT_PAGE 0 /* 4022 */ 153 #define HOST_MEM_CFG_PAGE 1 /* 4022 */ 154 #define LOCAL_RAM_CFG_PAGE 2 /* 4022 */ 155 #define PROT_STAT_PAGE 3 /* 4022 */ 156 157 /* Register Mask - sets corresponding mask bits in the upper word */ 158 static inline uint32_t set_rmask(uint32_t val) 159 { 160 return (val & 0xffff) | (val << 16); 161 } 162 163 164 static inline uint32_t clr_rmask(uint32_t val) 165 { 166 return 0 | (val << 16); 167 } 168 169 /* ctrl_status definitions */ 170 #define CSR_SCSI_PAGE_SELECT 0x00000003 171 #define CSR_SCSI_INTR_ENABLE 0x00000004 /* 4010 */ 172 #define CSR_SCSI_RESET_INTR 0x00000008 173 #define CSR_SCSI_COMPLETION_INTR 0x00000010 174 #define CSR_SCSI_PROCESSOR_INTR 0x00000020 175 #define CSR_INTR_RISC 0x00000040 176 #define CSR_BOOT_ENABLE 0x00000080 177 #define CSR_NET_PAGE_SELECT 0x00000300 /* 4010 */ 178 #define CSR_FUNC_NUM 0x00000700 /* 4022 */ 179 #define CSR_NET_RESET_INTR 0x00000800 /* 4010 */ 180 #define CSR_FORCE_SOFT_RESET 0x00002000 /* 4022 */ 181 #define CSR_FATAL_ERROR 0x00004000 182 #define CSR_SOFT_RESET 0x00008000 183 #define ISP_CONTROL_FN_MASK CSR_FUNC_NUM 184 #define ISP_CONTROL_FN0_SCSI 0x0500 185 #define ISP_CONTROL_FN1_SCSI 0x0700 186 187 #define INTR_PENDING (CSR_SCSI_COMPLETION_INTR |\ 188 CSR_SCSI_PROCESSOR_INTR |\ 189 CSR_SCSI_RESET_INTR) 190 191 /* ISP InterruptMask definitions */ 192 #define IMR_SCSI_INTR_ENABLE 0x00000004 /* 4022 */ 193 194 /* ISP 4022 nvram definitions */ 195 #define NVR_WRITE_ENABLE 0x00000010 /* 4022 */ 196 197 /* ISP port_status definitions */ 198 199 /* ISP Semaphore definitions */ 200 201 /* ISP General Purpose Output definitions */ 202 #define GPOR_TOPCAT_RESET 0x00000004 203 204 /* shadow registers (DMA'd from HA to system memory. read only) */ 205 struct shadow_regs { 206 /* SCSI Request Queue Consumer Index */ 207 __le32 req_q_out; /* 0 x0 R */ 208 209 /* SCSI Completion Queue Producer Index */ 210 __le32 rsp_q_in; /* 4 x4 R */ 211 }; /* 8 x8 */ 212 213 214 /* External hardware configuration register */ 215 union external_hw_config_reg { 216 struct { 217 /* FIXME: Do we even need this? All values are 218 * referred to by 16 bit quantities. Platform and 219 * endianess issues. */ 220 __le32 bReserved0:1; 221 __le32 bSDRAMProtectionMethod:2; 222 __le32 bSDRAMBanks:1; 223 __le32 bSDRAMChipWidth:1; 224 __le32 bSDRAMChipSize:2; 225 __le32 bParityDisable:1; 226 __le32 bExternalMemoryType:1; 227 __le32 bFlashBIOSWriteEnable:1; 228 __le32 bFlashUpperBankSelect:1; 229 __le32 bWriteBurst:2; 230 __le32 bReserved1:3; 231 __le32 bMask:16; 232 }; 233 uint32_t Asuint32_t; 234 }; 235 236 /* 82XX Support start */ 237 /* 82xx Default FLT Addresses */ 238 #define FA_FLASH_LAYOUT_ADDR_82 0xFC400 239 #define FA_FLASH_DESCR_ADDR_82 0xFC000 240 #define FA_BOOT_LOAD_ADDR_82 0x04000 241 #define FA_BOOT_CODE_ADDR_82 0x20000 242 #define FA_RISC_CODE_ADDR_82 0x40000 243 #define FA_GOLD_RISC_CODE_ADDR_82 0x80000 244 245 /* Flash Description Table */ 246 struct qla_fdt_layout { 247 uint8_t sig[4]; 248 uint16_t version; 249 uint16_t len; 250 uint16_t checksum; 251 uint8_t unused1[2]; 252 uint8_t model[16]; 253 uint16_t man_id; 254 uint16_t id; 255 uint8_t flags; 256 uint8_t erase_cmd; 257 uint8_t alt_erase_cmd; 258 uint8_t wrt_enable_cmd; 259 uint8_t wrt_enable_bits; 260 uint8_t wrt_sts_reg_cmd; 261 uint8_t unprotect_sec_cmd; 262 uint8_t read_man_id_cmd; 263 uint32_t block_size; 264 uint32_t alt_block_size; 265 uint32_t flash_size; 266 uint32_t wrt_enable_data; 267 uint8_t read_id_addr_len; 268 uint8_t wrt_disable_bits; 269 uint8_t read_dev_id_len; 270 uint8_t chip_erase_cmd; 271 uint16_t read_timeout; 272 uint8_t protect_sec_cmd; 273 uint8_t unused2[65]; 274 }; 275 276 /* Flash Layout Table */ 277 278 struct qla_flt_location { 279 uint8_t sig[4]; 280 uint16_t start_lo; 281 uint16_t start_hi; 282 uint8_t version; 283 uint8_t unused[5]; 284 uint16_t checksum; 285 }; 286 287 struct qla_flt_header { 288 uint16_t version; 289 uint16_t length; 290 uint16_t checksum; 291 uint16_t unused; 292 }; 293 294 /* 82xx FLT Regions */ 295 #define FLT_REG_FDT 0x1a 296 #define FLT_REG_FLT 0x1c 297 #define FLT_REG_BOOTLOAD_82 0x72 298 #define FLT_REG_FW_82 0x74 299 #define FLT_REG_GOLD_FW_82 0x75 300 #define FLT_REG_BOOT_CODE_82 0x78 301 302 struct qla_flt_region { 303 uint32_t code; 304 uint32_t size; 305 uint32_t start; 306 uint32_t end; 307 }; 308 309 /************************************************************************* 310 * 311 * Mailbox Commands Structures and Definitions 312 * 313 *************************************************************************/ 314 315 /* Mailbox command definitions */ 316 #define MBOX_CMD_ABOUT_FW 0x0009 317 #define MBOX_CMD_PING 0x000B 318 #define MBOX_CMD_ENABLE_INTRS 0x0010 319 #define INTR_DISABLE 0 320 #define INTR_ENABLE 1 321 #define MBOX_CMD_STOP_FW 0x0014 322 #define MBOX_CMD_ABORT_TASK 0x0015 323 #define MBOX_CMD_LUN_RESET 0x0016 324 #define MBOX_CMD_TARGET_WARM_RESET 0x0017 325 #define MBOX_CMD_GET_MANAGEMENT_DATA 0x001E 326 #define MBOX_CMD_GET_FW_STATUS 0x001F 327 #define MBOX_CMD_SET_ISNS_SERVICE 0x0021 328 #define ISNS_DISABLE 0 329 #define ISNS_ENABLE 1 330 #define MBOX_CMD_COPY_FLASH 0x0024 331 #define MBOX_CMD_WRITE_FLASH 0x0025 332 #define MBOX_CMD_READ_FLASH 0x0026 333 #define MBOX_CMD_CLEAR_DATABASE_ENTRY 0x0031 334 #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT 0x0056 335 #define LOGOUT_OPTION_CLOSE_SESSION 0x01 336 #define LOGOUT_OPTION_RELOGIN 0x02 337 #define MBOX_CMD_EXECUTE_IOCB_A64 0x005A 338 #define MBOX_CMD_INITIALIZE_FIRMWARE 0x0060 339 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK 0x0061 340 #define MBOX_CMD_REQUEST_DATABASE_ENTRY 0x0062 341 #define MBOX_CMD_SET_DATABASE_ENTRY 0x0063 342 #define MBOX_CMD_GET_DATABASE_ENTRY 0x0064 343 #define DDB_DS_UNASSIGNED 0x00 344 #define DDB_DS_NO_CONNECTION_ACTIVE 0x01 345 #define DDB_DS_SESSION_ACTIVE 0x04 346 #define DDB_DS_SESSION_FAILED 0x06 347 #define DDB_DS_LOGIN_IN_PROCESS 0x07 348 #define MBOX_CMD_GET_FW_STATE 0x0069 349 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A 350 #define MBOX_CMD_GET_SYS_INFO 0x0078 351 #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS 0x0087 352 #define MBOX_CMD_SET_ACB 0x0088 353 #define MBOX_CMD_GET_ACB 0x0089 354 #define MBOX_CMD_DISABLE_ACB 0x008A 355 #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE 0x008B 356 #define MBOX_CMD_GET_IPV6_DEST_CACHE 0x008C 357 #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST 0x008D 358 #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST 0x008E 359 #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE 0x0090 360 #define MBOX_CMD_GET_IP_ADDR_STATE 0x0091 361 #define MBOX_CMD_SEND_IPV6_ROUTER_SOL 0x0092 362 #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR 0x0093 363 364 /* Mailbox 1 */ 365 #define FW_STATE_READY 0x0000 366 #define FW_STATE_CONFIG_WAIT 0x0001 367 #define FW_STATE_WAIT_AUTOCONNECT 0x0002 368 #define FW_STATE_ERROR 0x0004 369 #define FW_STATE_CONFIGURING_IP 0x0008 370 371 /* Mailbox 3 */ 372 #define FW_ADDSTATE_OPTICAL_MEDIA 0x0001 373 #define FW_ADDSTATE_DHCPv4_ENABLED 0x0002 374 #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED 0x0004 375 #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED 0x0008 376 #define FW_ADDSTATE_LINK_UP 0x0010 377 #define FW_ADDSTATE_ISNS_SVC_ENABLED 0x0020 378 #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS 0x006B 379 #define MBOX_CMD_CONN_OPEN_SESS_LOGIN 0x0074 380 #define MBOX_CMD_GET_CRASH_RECORD 0x0076 /* 4010 only */ 381 #define MBOX_CMD_GET_CONN_EVENT_LOG 0x0077 382 383 /* Mailbox status definitions */ 384 #define MBOX_COMPLETION_STATUS 4 385 #define MBOX_STS_BUSY 0x0007 386 #define MBOX_STS_INTERMEDIATE_COMPLETION 0x1000 387 #define MBOX_STS_COMMAND_COMPLETE 0x4000 388 #define MBOX_STS_COMMAND_ERROR 0x4005 389 390 #define MBOX_ASYNC_EVENT_STATUS 8 391 #define MBOX_ASTS_SYSTEM_ERROR 0x8002 392 #define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003 393 #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004 394 #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM 0x8005 395 #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED 0x8006 396 #define MBOX_ASTS_LINK_UP 0x8010 397 #define MBOX_ASTS_LINK_DOWN 0x8011 398 #define MBOX_ASTS_DATABASE_CHANGED 0x8014 399 #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED 0x8015 400 #define MBOX_ASTS_SELF_TEST_FAILED 0x8016 401 #define MBOX_ASTS_LOGIN_FAILED 0x8017 402 #define MBOX_ASTS_DNS 0x8018 403 #define MBOX_ASTS_HEARTBEAT 0x8019 404 #define MBOX_ASTS_NVRAM_INVALID 0x801A 405 #define MBOX_ASTS_MAC_ADDRESS_CHANGED 0x801B 406 #define MBOX_ASTS_IP_ADDRESS_CHANGED 0x801C 407 #define MBOX_ASTS_DHCP_LEASE_EXPIRED 0x801D 408 #define MBOX_ASTS_DHCP_LEASE_ACQUIRED 0x801F 409 #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021 410 #define MBOX_ASTS_DUPLICATE_IP 0x8025 411 #define MBOX_ASTS_ARP_COMPLETE 0x8026 412 #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 413 #define MBOX_ASTS_RESPONSE_QUEUE_FULL 0x8028 414 #define MBOX_ASTS_IP_ADDR_STATE_CHANGED 0x8029 415 #define MBOX_ASTS_IPV6_PREFIX_EXPIRED 0x802B 416 #define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED 0x802C 417 #define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED 0x802D 418 #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD 0x802E 419 #define MBOX_ASTS_TXSCVR_INSERTED 0x8130 420 #define MBOX_ASTS_TXSCVR_REMOVED 0x8131 421 422 #define ISNS_EVENT_DATA_RECEIVED 0x0000 423 #define ISNS_EVENT_CONNECTION_OPENED 0x0001 424 #define ISNS_EVENT_CONNECTION_FAILED 0x0002 425 #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR 0x8022 426 #define MBOX_ASTS_SUBNET_STATE_CHANGE 0x8027 427 428 /* ACB State Defines */ 429 #define ACB_STATE_UNCONFIGURED 0x00 430 #define ACB_STATE_INVALID 0x01 431 #define ACB_STATE_ACQUIRING 0x02 432 #define ACB_STATE_TENTATIVE 0x03 433 #define ACB_STATE_DEPRICATED 0x04 434 #define ACB_STATE_VALID 0x05 435 #define ACB_STATE_DISABLING 0x06 436 437 /*************************************************************************/ 438 439 /* Host Adapter Initialization Control Block (from host) */ 440 struct addr_ctrl_blk { 441 uint8_t version; /* 00 */ 442 #define IFCB_VER_MIN 0x01 443 #define IFCB_VER_MAX 0x02 444 uint8_t control; /* 01 */ 445 446 uint16_t fw_options; /* 02-03 */ 447 #define FWOPT_HEARTBEAT_ENABLE 0x1000 448 #define FWOPT_SESSION_MODE 0x0040 449 #define FWOPT_INITIATOR_MODE 0x0020 450 #define FWOPT_TARGET_MODE 0x0010 451 #define FWOPT_ENABLE_CRBDB 0x8000 452 453 uint16_t exec_throttle; /* 04-05 */ 454 uint8_t zio_count; /* 06 */ 455 uint8_t res0; /* 07 */ 456 uint16_t eth_mtu_size; /* 08-09 */ 457 uint16_t add_fw_options; /* 0A-0B */ 458 #define SERIALIZE_TASK_MGMT 0x0400 459 460 uint8_t hb_interval; /* 0C */ 461 uint8_t inst_num; /* 0D */ 462 uint16_t res1; /* 0E-0F */ 463 uint16_t rqq_consumer_idx; /* 10-11 */ 464 uint16_t compq_producer_idx; /* 12-13 */ 465 uint16_t rqq_len; /* 14-15 */ 466 uint16_t compq_len; /* 16-17 */ 467 uint32_t rqq_addr_lo; /* 18-1B */ 468 uint32_t rqq_addr_hi; /* 1C-1F */ 469 uint32_t compq_addr_lo; /* 20-23 */ 470 uint32_t compq_addr_hi; /* 24-27 */ 471 uint32_t shdwreg_addr_lo; /* 28-2B */ 472 uint32_t shdwreg_addr_hi; /* 2C-2F */ 473 474 uint16_t iscsi_opts; /* 30-31 */ 475 uint16_t ipv4_tcp_opts; /* 32-33 */ 476 uint16_t ipv4_ip_opts; /* 34-35 */ 477 #define IPOPT_IPv4_PROTOCOL_ENABLE 0x8000 478 479 uint16_t iscsi_max_pdu_size; /* 36-37 */ 480 uint8_t ipv4_tos; /* 38 */ 481 uint8_t ipv4_ttl; /* 39 */ 482 uint8_t acb_version; /* 3A */ 483 #define ACB_NOT_SUPPORTED 0x00 484 #define ACB_SUPPORTED 0x02 /* Capable of ACB Version 2 485 Features */ 486 487 uint8_t res2; /* 3B */ 488 uint16_t def_timeout; /* 3C-3D */ 489 uint16_t iscsi_fburst_len; /* 3E-3F */ 490 uint16_t iscsi_def_time2wait; /* 40-41 */ 491 uint16_t iscsi_def_time2retain; /* 42-43 */ 492 uint16_t iscsi_max_outstnd_r2t; /* 44-45 */ 493 uint16_t conn_ka_timeout; /* 46-47 */ 494 uint16_t ipv4_port; /* 48-49 */ 495 uint16_t iscsi_max_burst_len; /* 4A-4B */ 496 uint32_t res5; /* 4C-4F */ 497 uint8_t ipv4_addr[4]; /* 50-53 */ 498 uint16_t ipv4_vlan_tag; /* 54-55 */ 499 uint8_t ipv4_addr_state; /* 56 */ 500 uint8_t ipv4_cacheid; /* 57 */ 501 uint8_t res6[8]; /* 58-5F */ 502 uint8_t ipv4_subnet[4]; /* 60-63 */ 503 uint8_t res7[12]; /* 64-6F */ 504 uint8_t ipv4_gw_addr[4]; /* 70-73 */ 505 uint8_t res8[0xc]; /* 74-7F */ 506 uint8_t pri_dns_srvr_ip[4];/* 80-83 */ 507 uint8_t sec_dns_srvr_ip[4];/* 84-87 */ 508 uint16_t min_eph_port; /* 88-89 */ 509 uint16_t max_eph_port; /* 8A-8B */ 510 uint8_t res9[4]; /* 8C-8F */ 511 uint8_t iscsi_alias[32];/* 90-AF */ 512 uint8_t res9_1[0x16]; /* B0-C5 */ 513 uint16_t tgt_portal_grp;/* C6-C7 */ 514 uint8_t abort_timer; /* C8 */ 515 uint8_t ipv4_tcp_wsf; /* C9 */ 516 uint8_t res10[6]; /* CA-CF */ 517 uint8_t ipv4_sec_ip_addr[4]; /* D0-D3 */ 518 uint8_t ipv4_dhcp_vid_len; /* D4 */ 519 uint8_t ipv4_dhcp_vid[11]; /* D5-DF */ 520 uint8_t res11[20]; /* E0-F3 */ 521 uint8_t ipv4_dhcp_alt_cid_len; /* F4 */ 522 uint8_t ipv4_dhcp_alt_cid[11]; /* F5-FF */ 523 uint8_t iscsi_name[224]; /* 100-1DF */ 524 uint8_t res12[32]; /* 1E0-1FF */ 525 uint32_t cookie; /* 200-203 */ 526 uint16_t ipv6_port; /* 204-205 */ 527 uint16_t ipv6_opts; /* 206-207 */ 528 #define IPV6_OPT_IPV6_PROTOCOL_ENABLE 0x8000 529 530 uint16_t ipv6_addtl_opts; /* 208-209 */ 531 #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE 0x0002 /* Pri ACB 532 Only */ 533 #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR 0x0001 534 535 uint16_t ipv6_tcp_opts; /* 20A-20B */ 536 uint8_t ipv6_tcp_wsf; /* 20C */ 537 uint16_t ipv6_flow_lbl; /* 20D-20F */ 538 uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */ 539 uint16_t ipv6_vlan_tag; /* 220-221 */ 540 uint8_t ipv6_lnk_lcl_addr_state;/* 222 */ 541 uint8_t ipv6_addr0_state; /* 223 */ 542 uint8_t ipv6_addr1_state; /* 224 */ 543 #define IP_ADDRSTATE_UNCONFIGURED 0 544 #define IP_ADDRSTATE_INVALID 1 545 #define IP_ADDRSTATE_ACQUIRING 2 546 #define IP_ADDRSTATE_TENTATIVE 3 547 #define IP_ADDRSTATE_DEPRICATED 4 548 #define IP_ADDRSTATE_PREFERRED 5 549 #define IP_ADDRSTATE_DISABLING 6 550 551 uint8_t ipv6_dflt_rtr_state; /* 225 */ 552 #define IPV6_RTRSTATE_UNKNOWN 0 553 #define IPV6_RTRSTATE_MANUAL 1 554 #define IPV6_RTRSTATE_ADVERTISED 3 555 #define IPV6_RTRSTATE_STALE 4 556 557 uint8_t ipv6_traffic_class; /* 226 */ 558 uint8_t ipv6_hop_limit; /* 227 */ 559 uint8_t ipv6_if_id[8]; /* 228-22F */ 560 uint8_t ipv6_addr0[16]; /* 230-23F */ 561 uint8_t ipv6_addr1[16]; /* 240-24F */ 562 uint32_t ipv6_nd_reach_time; /* 250-253 */ 563 uint32_t ipv6_nd_rexmit_timer; /* 254-257 */ 564 uint32_t ipv6_nd_stale_timeout; /* 258-25B */ 565 uint8_t ipv6_dup_addr_detect_count; /* 25C */ 566 uint8_t ipv6_cache_id; /* 25D */ 567 uint8_t res13[18]; /* 25E-26F */ 568 uint32_t ipv6_gw_advrt_mtu; /* 270-273 */ 569 uint8_t res14[140]; /* 274-2FF */ 570 }; 571 572 struct init_fw_ctrl_blk { 573 struct addr_ctrl_blk pri; 574 /* struct addr_ctrl_blk sec;*/ 575 }; 576 577 /*************************************************************************/ 578 579 struct dev_db_entry { 580 uint16_t options; /* 00-01 */ 581 #define DDB_OPT_DISC_SESSION 0x10 582 #define DDB_OPT_TARGET 0x02 /* device is a target */ 583 #define DDB_OPT_IPV6_DEVICE 0x100 584 #define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */ 585 #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */ 586 587 uint16_t exec_throttle; /* 02-03 */ 588 uint16_t exec_count; /* 04-05 */ 589 uint16_t res0; /* 06-07 */ 590 uint16_t iscsi_options; /* 08-09 */ 591 uint16_t tcp_options; /* 0A-0B */ 592 uint16_t ip_options; /* 0C-0D */ 593 uint16_t iscsi_max_rcv_data_seg_len; /* 0E-0F */ 594 uint32_t res1; /* 10-13 */ 595 uint16_t iscsi_max_snd_data_seg_len; /* 14-15 */ 596 uint16_t iscsi_first_burst_len; /* 16-17 */ 597 uint16_t iscsi_def_time2wait; /* 18-19 */ 598 uint16_t iscsi_def_time2retain; /* 1A-1B */ 599 uint16_t iscsi_max_outsnd_r2t; /* 1C-1D */ 600 uint16_t ka_timeout; /* 1E-1F */ 601 uint8_t isid[6]; /* 20-25 big-endian, must be converted 602 * to little-endian */ 603 uint16_t tsid; /* 26-27 */ 604 uint16_t port; /* 28-29 */ 605 uint16_t iscsi_max_burst_len; /* 2A-2B */ 606 uint16_t def_timeout; /* 2C-2D */ 607 uint16_t res2; /* 2E-2F */ 608 uint8_t ip_addr[0x10]; /* 30-3F */ 609 uint8_t iscsi_alias[0x20]; /* 40-5F */ 610 uint8_t tgt_addr[0x20]; /* 60-7F */ 611 uint16_t mss; /* 80-81 */ 612 uint16_t res3; /* 82-83 */ 613 uint16_t lcl_port; /* 84-85 */ 614 uint8_t ipv4_tos; /* 86 */ 615 uint16_t ipv6_flow_lbl; /* 87-89 */ 616 uint8_t res4[0x36]; /* 8A-BF */ 617 uint8_t iscsi_name[0xE0]; /* C0-19F : xxzzy Make this a 618 * pointer to a string so we 619 * don't have to reserve soooo 620 * much RAM */ 621 uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */ 622 uint8_t res5[0x10]; /* 1B0-1BF */ 623 uint16_t ddb_link; /* 1C0-1C1 */ 624 uint16_t chap_tbl_idx; /* 1C2-1C3 */ 625 uint16_t tgt_portal_grp; /* 1C4-1C5 */ 626 uint8_t tcp_xmt_wsf; /* 1C6 */ 627 uint8_t tcp_rcv_wsf; /* 1C7 */ 628 uint32_t stat_sn; /* 1C8-1CB */ 629 uint32_t exp_stat_sn; /* 1CC-1CF */ 630 uint8_t res6[0x30]; /* 1D0-1FF */ 631 }; 632 633 /*************************************************************************/ 634 635 /* Flash definitions */ 636 637 #define FLASH_OFFSET_SYS_INFO 0x02000000 638 #define FLASH_DEFAULTBLOCKSIZE 0x20000 639 #define FLASH_EOF_OFFSET (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes 640 * for EOF 641 * signature */ 642 643 struct sys_info_phys_addr { 644 uint8_t address[6]; /* 00-05 */ 645 uint8_t filler[2]; /* 06-07 */ 646 }; 647 648 struct flash_sys_info { 649 uint32_t cookie; /* 00-03 */ 650 uint32_t physAddrCount; /* 04-07 */ 651 struct sys_info_phys_addr physAddr[4]; /* 08-27 */ 652 uint8_t vendorId[128]; /* 28-A7 */ 653 uint8_t productId[128]; /* A8-127 */ 654 uint32_t serialNumber; /* 128-12B */ 655 656 /* PCI Configuration values */ 657 uint32_t pciDeviceVendor; /* 12C-12F */ 658 uint32_t pciDeviceId; /* 130-133 */ 659 uint32_t pciSubsysVendor; /* 134-137 */ 660 uint32_t pciSubsysId; /* 138-13B */ 661 662 /* This validates version 1. */ 663 uint32_t crumbs; /* 13C-13F */ 664 665 uint32_t enterpriseNumber; /* 140-143 */ 666 667 uint32_t mtu; /* 144-147 */ 668 uint32_t reserved0; /* 148-14b */ 669 uint32_t crumbs2; /* 14c-14f */ 670 uint8_t acSerialNumber[16]; /* 150-15f */ 671 uint32_t crumbs3; /* 160-16f */ 672 673 /* Leave this last in the struct so it is declared invalid if 674 * any new items are added. 675 */ 676 uint32_t reserved1[39]; /* 170-1ff */ 677 }; /* 200 */ 678 679 struct mbx_sys_info { 680 uint8_t board_id_str[16]; /* 0-f Keep board ID string first */ 681 /* in this structure for GUI. */ 682 uint16_t board_id; /* 10-11 board ID code */ 683 uint16_t phys_port_cnt; /* 12-13 number of physical network ports */ 684 uint16_t port_num; /* 14-15 network port for this PCI function */ 685 /* (port 0 is first port) */ 686 uint8_t mac_addr[6]; /* 16-1b MAC address for this PCI function */ 687 uint32_t iscsi_pci_func_cnt; /* 1c-1f number of iSCSI PCI functions */ 688 uint32_t pci_func; /* 20-23 this PCI function */ 689 unsigned char serial_number[16]; /* 24-33 serial number string */ 690 uint8_t reserved[12]; /* 34-3f */ 691 }; 692 693 struct about_fw_info { 694 uint16_t fw_major; /* 00 - 01 */ 695 uint16_t fw_minor; /* 02 - 03 */ 696 uint16_t fw_patch; /* 04 - 05 */ 697 uint16_t fw_build; /* 06 - 07 */ 698 uint8_t fw_build_date[16]; /* 08 - 17 ASCII String */ 699 uint8_t fw_build_time[16]; /* 18 - 27 ASCII String */ 700 uint8_t fw_build_user[16]; /* 28 - 37 ASCII String */ 701 uint16_t fw_load_source; /* 38 - 39 */ 702 /* 1 = Flash Primary, 703 2 = Flash Secondary, 704 3 = Host Download 705 */ 706 uint8_t reserved1[6]; /* 3A - 3F */ 707 uint16_t iscsi_major; /* 40 - 41 */ 708 uint16_t iscsi_minor; /* 42 - 43 */ 709 uint16_t bootload_major; /* 44 - 45 */ 710 uint16_t bootload_minor; /* 46 - 47 */ 711 uint16_t bootload_patch; /* 48 - 49 */ 712 uint16_t bootload_build; /* 4A - 4B */ 713 uint8_t reserved2[180]; /* 4C - FF */ 714 }; 715 716 struct crash_record { 717 uint16_t fw_major_version; /* 00 - 01 */ 718 uint16_t fw_minor_version; /* 02 - 03 */ 719 uint16_t fw_patch_version; /* 04 - 05 */ 720 uint16_t fw_build_version; /* 06 - 07 */ 721 722 uint8_t build_date[16]; /* 08 - 17 */ 723 uint8_t build_time[16]; /* 18 - 27 */ 724 uint8_t build_user[16]; /* 28 - 37 */ 725 uint8_t card_serial_num[16]; /* 38 - 47 */ 726 727 uint32_t time_of_crash_in_secs; /* 48 - 4B */ 728 uint32_t time_of_crash_in_ms; /* 4C - 4F */ 729 730 uint16_t out_RISC_sd_num_frames; /* 50 - 51 */ 731 uint16_t OAP_sd_num_words; /* 52 - 53 */ 732 uint16_t IAP_sd_num_frames; /* 54 - 55 */ 733 uint16_t in_RISC_sd_num_words; /* 56 - 57 */ 734 735 uint8_t reserved1[28]; /* 58 - 7F */ 736 737 uint8_t out_RISC_reg_dump[256]; /* 80 -17F */ 738 uint8_t in_RISC_reg_dump[256]; /*180 -27F */ 739 uint8_t in_out_RISC_stack_dump[0]; /*280 - ??? */ 740 }; 741 742 struct conn_event_log_entry { 743 #define MAX_CONN_EVENT_LOG_ENTRIES 100 744 uint32_t timestamp_sec; /* 00 - 03 seconds since boot */ 745 uint32_t timestamp_ms; /* 04 - 07 milliseconds since boot */ 746 uint16_t device_index; /* 08 - 09 */ 747 uint16_t fw_conn_state; /* 0A - 0B */ 748 uint8_t event_type; /* 0C - 0C */ 749 uint8_t error_code; /* 0D - 0D */ 750 uint16_t error_code_detail; /* 0E - 0F */ 751 uint8_t num_consecutive_events; /* 10 - 10 */ 752 uint8_t rsvd[3]; /* 11 - 13 */ 753 }; 754 755 /************************************************************************* 756 * 757 * IOCB Commands Structures and Definitions 758 * 759 *************************************************************************/ 760 #define IOCB_MAX_CDB_LEN 16 /* Bytes in a CBD */ 761 #define IOCB_MAX_SENSEDATA_LEN 32 /* Bytes of sense data */ 762 #define IOCB_MAX_EXT_SENSEDATA_LEN 60 /* Bytes of extended sense data */ 763 764 /* IOCB header structure */ 765 struct qla4_header { 766 uint8_t entryType; 767 #define ET_STATUS 0x03 768 #define ET_MARKER 0x04 769 #define ET_CONT_T1 0x0A 770 #define ET_STATUS_CONTINUATION 0x10 771 #define ET_CMND_T3 0x19 772 #define ET_PASSTHRU0 0x3A 773 #define ET_PASSTHRU_STATUS 0x3C 774 775 uint8_t entryStatus; 776 uint8_t systemDefined; 777 uint8_t entryCount; 778 779 /* SyetemDefined definition */ 780 }; 781 782 /* Generic queue entry structure*/ 783 struct queue_entry { 784 uint8_t data[60]; 785 uint32_t signature; 786 787 }; 788 789 /* 64 bit addressing segment counts*/ 790 791 #define COMMAND_SEG_A64 1 792 #define CONTINUE_SEG_A64 5 793 794 /* 64 bit addressing segment definition*/ 795 796 struct data_seg_a64 { 797 struct { 798 uint32_t addrLow; 799 uint32_t addrHigh; 800 801 } base; 802 803 uint32_t count; 804 805 }; 806 807 /* Command Type 3 entry structure*/ 808 809 struct command_t3_entry { 810 struct qla4_header hdr; /* 00-03 */ 811 812 uint32_t handle; /* 04-07 */ 813 uint16_t target; /* 08-09 */ 814 uint16_t connection_id; /* 0A-0B */ 815 816 uint8_t control_flags; /* 0C */ 817 818 /* data direction (bits 5-6) */ 819 #define CF_WRITE 0x20 820 #define CF_READ 0x40 821 #define CF_NO_DATA 0x00 822 823 /* task attributes (bits 2-0) */ 824 #define CF_HEAD_TAG 0x03 825 #define CF_ORDERED_TAG 0x02 826 #define CF_SIMPLE_TAG 0x01 827 828 /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS 829 * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS 830 * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET 831 * PROPERLY. 832 */ 833 uint8_t state_flags; /* 0D */ 834 uint8_t cmdRefNum; /* 0E */ 835 uint8_t reserved1; /* 0F */ 836 uint8_t cdb[IOCB_MAX_CDB_LEN]; /* 10-1F */ 837 struct scsi_lun lun; /* FCP LUN (BE). */ 838 uint32_t cmdSeqNum; /* 28-2B */ 839 uint16_t timeout; /* 2C-2D */ 840 uint16_t dataSegCnt; /* 2E-2F */ 841 uint32_t ttlByteCnt; /* 30-33 */ 842 struct data_seg_a64 dataseg[COMMAND_SEG_A64]; /* 34-3F */ 843 844 }; 845 846 847 /* Continuation Type 1 entry structure*/ 848 struct continuation_t1_entry { 849 struct qla4_header hdr; 850 851 struct data_seg_a64 dataseg[CONTINUE_SEG_A64]; 852 853 }; 854 855 /* Parameterize for 64 or 32 bits */ 856 #define COMMAND_SEG COMMAND_SEG_A64 857 #define CONTINUE_SEG CONTINUE_SEG_A64 858 859 #define ET_COMMAND ET_CMND_T3 860 #define ET_CONTINUE ET_CONT_T1 861 862 /* Marker entry structure*/ 863 struct qla4_marker_entry { 864 struct qla4_header hdr; /* 00-03 */ 865 866 uint32_t system_defined; /* 04-07 */ 867 uint16_t target; /* 08-09 */ 868 uint16_t modifier; /* 0A-0B */ 869 #define MM_LUN_RESET 0 870 #define MM_TGT_WARM_RESET 1 871 872 uint16_t flags; /* 0C-0D */ 873 uint16_t reserved1; /* 0E-0F */ 874 struct scsi_lun lun; /* FCP LUN (BE). */ 875 uint64_t reserved2; /* 18-1F */ 876 uint64_t reserved3; /* 20-27 */ 877 uint64_t reserved4; /* 28-2F */ 878 uint64_t reserved5; /* 30-37 */ 879 uint64_t reserved6; /* 38-3F */ 880 }; 881 882 /* Status entry structure*/ 883 struct status_entry { 884 struct qla4_header hdr; /* 00-03 */ 885 886 uint32_t handle; /* 04-07 */ 887 888 uint8_t scsiStatus; /* 08 */ 889 #define SCSI_CHECK_CONDITION 0x02 890 891 uint8_t iscsiFlags; /* 09 */ 892 #define ISCSI_FLAG_RESIDUAL_UNDER 0x02 893 #define ISCSI_FLAG_RESIDUAL_OVER 0x04 894 895 uint8_t iscsiResponse; /* 0A */ 896 897 uint8_t completionStatus; /* 0B */ 898 #define SCS_COMPLETE 0x00 899 #define SCS_INCOMPLETE 0x01 900 #define SCS_RESET_OCCURRED 0x04 901 #define SCS_ABORTED 0x05 902 #define SCS_TIMEOUT 0x06 903 #define SCS_DATA_OVERRUN 0x07 904 #define SCS_DATA_UNDERRUN 0x15 905 #define SCS_QUEUE_FULL 0x1C 906 #define SCS_DEVICE_UNAVAILABLE 0x28 907 #define SCS_DEVICE_LOGGED_OUT 0x29 908 909 uint8_t reserved1; /* 0C */ 910 911 /* state_flags MUST be at the same location as state_flags in 912 * the Command_T3/4_Entry */ 913 uint8_t state_flags; /* 0D */ 914 915 uint16_t senseDataByteCnt; /* 0E-0F */ 916 uint32_t residualByteCnt; /* 10-13 */ 917 uint32_t bidiResidualByteCnt; /* 14-17 */ 918 uint32_t expSeqNum; /* 18-1B */ 919 uint32_t maxCmdSeqNum; /* 1C-1F */ 920 uint8_t senseData[IOCB_MAX_SENSEDATA_LEN]; /* 20-3F */ 921 922 }; 923 924 /* Status Continuation entry */ 925 struct status_cont_entry { 926 struct qla4_header hdr; /* 00-03 */ 927 uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */ 928 }; 929 930 struct passthru0 { 931 struct qla4_header hdr; /* 00-03 */ 932 uint32_t handle; /* 04-07 */ 933 uint16_t target; /* 08-09 */ 934 uint16_t connectionID; /* 0A-0B */ 935 #define ISNS_DEFAULT_SERVER_CONN_ID ((uint16_t)0x8000) 936 937 uint16_t controlFlags; /* 0C-0D */ 938 #define PT_FLAG_ETHERNET_FRAME 0x8000 939 #define PT_FLAG_ISNS_PDU 0x8000 940 #define PT_FLAG_SEND_BUFFER 0x0200 941 #define PT_FLAG_WAIT_4_RESPONSE 0x0100 942 943 uint16_t timeout; /* 0E-0F */ 944 #define PT_DEFAULT_TIMEOUT 30 /* seconds */ 945 946 struct data_seg_a64 outDataSeg64; /* 10-1B */ 947 uint32_t res1; /* 1C-1F */ 948 struct data_seg_a64 inDataSeg64; /* 20-2B */ 949 uint8_t res2[20]; /* 2C-3F */ 950 }; 951 952 struct passthru_status { 953 struct qla4_header hdr; /* 00-03 */ 954 uint32_t handle; /* 04-07 */ 955 uint16_t target; /* 08-09 */ 956 uint16_t connectionID; /* 0A-0B */ 957 958 uint8_t completionStatus; /* 0C */ 959 #define PASSTHRU_STATUS_COMPLETE 0x01 960 961 uint8_t residualFlags; /* 0D */ 962 963 uint16_t timeout; /* 0E-0F */ 964 uint16_t portNumber; /* 10-11 */ 965 uint8_t res1[10]; /* 12-1B */ 966 uint32_t outResidual; /* 1C-1F */ 967 uint8_t res2[12]; /* 20-2B */ 968 uint32_t inResidual; /* 2C-2F */ 969 uint8_t res4[16]; /* 30-3F */ 970 }; 971 972 /* 973 * ISP queue - response queue entry definition. 974 */ 975 struct response { 976 uint8_t data[60]; 977 uint32_t signature; 978 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 979 }; 980 981 #endif /* _QLA4X_FW_H */ 982