1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2006 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8 #ifndef __QL4_DEF_H 9 #define __QL4_DEF_H 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/module.h> 15 #include <linux/list.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/sched.h> 19 #include <linux/slab.h> 20 #include <linux/dmapool.h> 21 #include <linux/mempool.h> 22 #include <linux/spinlock.h> 23 #include <linux/workqueue.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/mutex.h> 27 28 #include <net/tcp.h> 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport.h> 34 #include <scsi/scsi_transport_iscsi.h> 35 36 37 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010 38 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010 39 #endif 40 41 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 42 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 43 #endif 44 45 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032 46 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032 47 #endif 48 49 #define QLA_SUCCESS 0 50 #define QLA_ERROR 1 51 52 /* 53 * Data bit definitions 54 */ 55 #define BIT_0 0x1 56 #define BIT_1 0x2 57 #define BIT_2 0x4 58 #define BIT_3 0x8 59 #define BIT_4 0x10 60 #define BIT_5 0x20 61 #define BIT_6 0x40 62 #define BIT_7 0x80 63 #define BIT_8 0x100 64 #define BIT_9 0x200 65 #define BIT_10 0x400 66 #define BIT_11 0x800 67 #define BIT_12 0x1000 68 #define BIT_13 0x2000 69 #define BIT_14 0x4000 70 #define BIT_15 0x8000 71 #define BIT_16 0x10000 72 #define BIT_17 0x20000 73 #define BIT_18 0x40000 74 #define BIT_19 0x80000 75 #define BIT_20 0x100000 76 #define BIT_21 0x200000 77 #define BIT_22 0x400000 78 #define BIT_23 0x800000 79 #define BIT_24 0x1000000 80 #define BIT_25 0x2000000 81 #define BIT_26 0x4000000 82 #define BIT_27 0x8000000 83 #define BIT_28 0x10000000 84 #define BIT_29 0x20000000 85 #define BIT_30 0x40000000 86 #define BIT_31 0x80000000 87 88 /* 89 * Host adapter default definitions 90 ***********************************/ 91 #define MAX_HBAS 16 92 #define MAX_BUSES 1 93 #define MAX_TARGETS (MAX_PRST_DEV_DB_ENTRIES + MAX_DEV_DB_ENTRIES) 94 #define MAX_LUNS 0xffff 95 #define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */ 96 #define MAX_DDB_ENTRIES (MAX_PRST_DEV_DB_ENTRIES + MAX_DEV_DB_ENTRIES) 97 #define MAX_PDU_ENTRIES 32 98 #define INVALID_ENTRY 0xFFFF 99 #define MAX_CMDS_TO_RISC 1024 100 #define MAX_SRBS MAX_CMDS_TO_RISC 101 #define MBOX_AEN_REG_COUNT 5 102 #define MAX_INIT_RETRIES 5 103 104 /* 105 * Buffer sizes 106 */ 107 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC 108 #define RESPONSE_QUEUE_DEPTH 64 109 #define QUEUE_SIZE 64 110 #define DMA_BUFFER_SIZE 512 111 112 /* 113 * Misc 114 */ 115 #define MAC_ADDR_LEN 6 /* in bytes */ 116 #define IP_ADDR_LEN 4 /* in bytes */ 117 #define DRIVER_NAME "qla4xxx" 118 119 #define MAX_LINKED_CMDS_PER_LUN 3 120 #define MAX_REQS_SERVICED_PER_INTR 16 121 122 #define ISCSI_IPADDR_SIZE 4 /* IP address size */ 123 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */ 124 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */ 125 126 #define LSDW(x) ((u32)((u64)(x))) 127 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16)) 128 129 /* 130 * Retry & Timeout Values 131 */ 132 #define MBOX_TOV 60 133 #define SOFT_RESET_TOV 30 134 #define RESET_INTR_TOV 3 135 #define SEMAPHORE_TOV 10 136 #define ADAPTER_INIT_TOV 120 137 #define ADAPTER_RESET_TOV 180 138 #define EXTEND_CMD_TOV 60 139 #define WAIT_CMD_TOV 30 140 #define EH_WAIT_CMD_TOV 120 141 #define FIRMWARE_UP_TOV 60 142 #define RESET_FIRMWARE_TOV 30 143 #define LOGOUT_TOV 10 144 #define IOCB_TOV_MARGIN 10 145 #define RELOGIN_TOV 18 146 #define ISNS_DEREG_TOV 5 147 148 #define MAX_RESET_HA_RETRIES 2 149 150 /* 151 * SCSI Request Block structure (srb) that is placed 152 * on cmd->SCp location of every I/O [We have 22 bytes available] 153 */ 154 struct srb { 155 struct list_head list; /* (8) */ 156 struct scsi_qla_host *ha; /* HA the SP is queued on */ 157 struct ddb_entry *ddb; 158 uint16_t flags; /* (1) Status flags. */ 159 160 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */ 161 #define SRB_GOT_SENSE BIT_4 /* sense data recieved. */ 162 uint8_t state; /* (1) Status flags. */ 163 164 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */ 165 #define SRB_FREE_STATE 1 166 #define SRB_ACTIVE_STATE 3 167 #define SRB_ACTIVE_TIMEOUT_STATE 4 168 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */ 169 170 struct scsi_cmnd *cmd; /* (4) SCSI command block */ 171 dma_addr_t dma_handle; /* (4) for unmap of single transfers */ 172 atomic_t ref_count; /* reference count for this srb */ 173 uint32_t fw_ddb_index; 174 uint8_t err_id; /* error id */ 175 #define SRB_ERR_PORT 1 /* Request failed because "port down" */ 176 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */ 177 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */ 178 #define SRB_ERR_OTHER 4 179 180 uint16_t reserved; 181 uint16_t iocb_tov; 182 uint16_t iocb_cnt; /* Number of used iocbs */ 183 uint16_t cc_stat; 184 u_long r_start; /* Time we recieve a cmd from OS */ 185 u_long u_start; /* Time when we handed the cmd to F/W */ 186 187 /* Used for extended sense / status continuation */ 188 uint8_t *req_sense_ptr; 189 uint16_t req_sense_len; 190 uint16_t reserved2; 191 }; 192 193 /* 194 * Asynchronous Event Queue structure 195 */ 196 struct aen { 197 uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; 198 }; 199 200 struct ql4_aen_log { 201 int count; 202 struct aen entry[MAX_AEN_ENTRIES]; 203 }; 204 205 /* 206 * Device Database (DDB) structure 207 */ 208 struct ddb_entry { 209 struct list_head list; /* ddb list */ 210 struct scsi_qla_host *ha; 211 struct iscsi_cls_session *sess; 212 struct iscsi_cls_conn *conn; 213 214 atomic_t state; /* DDB State */ 215 216 unsigned long flags; /* DDB Flags */ 217 218 unsigned long dev_scan_wait_to_start_relogin; 219 unsigned long dev_scan_wait_to_complete_relogin; 220 221 uint16_t os_target_id; /* Target ID */ 222 uint16_t fw_ddb_index; /* DDB firmware index */ 223 uint8_t reserved[2]; 224 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */ 225 226 uint32_t CmdSn; 227 uint16_t target_session_id; 228 uint16_t connection_id; 229 uint16_t exe_throttle; /* Max mumber of cmds outstanding 230 * simultaneously */ 231 uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to 232 * complete */ 233 uint16_t default_relogin_timeout; /* Max time to wait for 234 * relogin to complete */ 235 uint16_t tcp_source_port_num; 236 uint32_t default_time2wait; /* Default Min time between 237 * relogins (+aens) */ 238 239 atomic_t port_down_timer; /* Device connection timer */ 240 atomic_t retry_relogin_timer; /* Min Time between relogins 241 * (4000 only) */ 242 atomic_t relogin_timer; /* Max Time to wait for relogin to complete */ 243 atomic_t relogin_retry_count; /* Num of times relogin has been 244 * retried */ 245 246 uint16_t port; 247 uint32_t tpgt; 248 uint8_t ip_addr[ISCSI_IPADDR_SIZE]; 249 uint8_t iscsi_name[ISCSI_NAME_SIZE]; /* 72 x48 */ 250 uint8_t iscsi_alias[0x20]; 251 uint8_t isid[6]; 252 }; 253 254 /* 255 * DDB states. 256 */ 257 #define DDB_STATE_DEAD 0 /* We can no longer talk to 258 * this device */ 259 #define DDB_STATE_ONLINE 1 /* Device ready to accept 260 * commands */ 261 #define DDB_STATE_MISSING 2 /* Device logged off, trying 262 * to re-login */ 263 264 /* 265 * DDB flags. 266 */ 267 #define DF_RELOGIN 0 /* Relogin to device */ 268 #define DF_NO_RELOGIN 1 /* Do not relogin if IOCTL 269 * logged it out */ 270 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */ 271 #define DF_FO_MASKED 3 272 273 274 #include "ql4_fw.h" 275 #include "ql4_nvram.h" 276 277 /* 278 * Linux Host Adapter structure 279 */ 280 struct scsi_qla_host { 281 /* Linux adapter configuration data */ 282 unsigned long flags; 283 284 #define AF_ONLINE 0 /* 0x00000001 */ 285 #define AF_INIT_DONE 1 /* 0x00000002 */ 286 #define AF_MBOX_COMMAND 2 /* 0x00000004 */ 287 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */ 288 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */ 289 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ 290 #define AF_LINK_UP 8 /* 0x00000100 */ 291 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */ 292 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */ 293 294 unsigned long dpc_flags; 295 296 #define DPC_RESET_HA 1 /* 0x00000002 */ 297 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */ 298 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */ 299 #define DPC_RESET_HA_DESTROY_DDB_LIST 4 /* 0x00000010 */ 300 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */ 301 #define DPC_ISNS_RESTART 7 /* 0x00000080 */ 302 #define DPC_AEN 9 /* 0x00000200 */ 303 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */ 304 305 struct Scsi_Host *host; /* pointer to host data */ 306 uint32_t tot_ddbs; 307 308 uint16_t iocb_cnt; 309 310 /* SRB cache. */ 311 #define SRB_MIN_REQ 128 312 mempool_t *srb_mempool; 313 314 /* pci information */ 315 struct pci_dev *pdev; 316 317 struct isp_reg __iomem *reg; /* Base I/O address */ 318 unsigned long pio_address; 319 unsigned long pio_length; 320 #define MIN_IOBASE_LEN 0x100 321 322 uint16_t req_q_count; 323 uint8_t marker_needed; 324 uint8_t rsvd1; 325 326 unsigned long host_no; 327 328 /* NVRAM registers */ 329 struct eeprom_data *nvram; 330 spinlock_t hardware_lock ____cacheline_aligned; 331 uint32_t eeprom_cmd_data; 332 333 /* Counters for general statistics */ 334 uint64_t isr_count; 335 uint64_t adapter_error_count; 336 uint64_t device_error_count; 337 uint64_t total_io_count; 338 uint64_t total_mbytes_xferred; 339 uint64_t link_failure_count; 340 uint64_t invalid_crc_count; 341 uint32_t bytes_xfered; 342 uint32_t spurious_int_count; 343 uint32_t aborted_io_count; 344 uint32_t io_timeout_count; 345 uint32_t mailbox_timeout_count; 346 uint32_t seconds_since_last_intr; 347 uint32_t seconds_since_last_heartbeat; 348 uint32_t mac_index; 349 350 /* Info Needed for Management App */ 351 /* --- From GetFwVersion --- */ 352 uint32_t firmware_version[2]; 353 uint32_t patch_number; 354 uint32_t build_number; 355 uint32_t board_id; 356 357 /* --- From Init_FW --- */ 358 /* init_cb_t *init_cb; */ 359 uint16_t firmware_options; 360 uint16_t tcp_options; 361 uint8_t ip_address[IP_ADDR_LEN]; 362 uint8_t subnet_mask[IP_ADDR_LEN]; 363 uint8_t gateway[IP_ADDR_LEN]; 364 uint8_t alias[32]; 365 uint8_t name_string[256]; 366 uint8_t heartbeat_interval; 367 uint8_t rsvd; 368 369 /* --- From FlashSysInfo --- */ 370 uint8_t my_mac[MAC_ADDR_LEN]; 371 uint8_t serial_number[16]; 372 373 /* --- From GetFwState --- */ 374 uint32_t firmware_state; 375 uint32_t addl_fw_state; 376 377 /* Linux kernel thread */ 378 struct workqueue_struct *dpc_thread; 379 struct work_struct dpc_work; 380 381 /* Linux timer thread */ 382 struct timer_list timer; 383 uint32_t timer_active; 384 385 /* Recovery Timers */ 386 uint32_t port_down_retry_count; 387 uint32_t discovery_wait; 388 atomic_t check_relogin_timeouts; 389 uint32_t retry_reset_ha_cnt; 390 uint32_t isp_reset_timer; /* reset test timer */ 391 uint32_t nic_reset_timer; /* simulated nic reset test timer */ 392 int eh_start; 393 struct list_head free_srb_q; 394 uint16_t free_srb_q_count; 395 uint16_t num_srbs_allocated; 396 397 /* DMA Memory Block */ 398 void *queues; 399 dma_addr_t queues_dma; 400 unsigned long queues_len; 401 402 #define MEM_ALIGN_VALUE \ 403 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \ 404 sizeof(struct queue_entry)) 405 /* request and response queue variables */ 406 dma_addr_t request_dma; 407 struct queue_entry *request_ring; 408 struct queue_entry *request_ptr; 409 dma_addr_t response_dma; 410 struct queue_entry *response_ring; 411 struct queue_entry *response_ptr; 412 dma_addr_t shadow_regs_dma; 413 struct shadow_regs *shadow_regs; 414 uint16_t request_in; /* Current indexes. */ 415 uint16_t request_out; 416 uint16_t response_in; 417 uint16_t response_out; 418 419 /* aen queue variables */ 420 uint16_t aen_q_count; /* Number of available aen_q entries */ 421 uint16_t aen_in; /* Current indexes */ 422 uint16_t aen_out; 423 struct aen aen_q[MAX_AEN_ENTRIES]; 424 425 struct ql4_aen_log aen_log;/* tracks all aens */ 426 427 /* This mutex protects several threads to do mailbox commands 428 * concurrently. 429 */ 430 struct mutex mbox_sem; 431 432 /* temporary mailbox status registers */ 433 volatile uint8_t mbox_status_count; 434 volatile uint32_t mbox_status[MBOX_REG_COUNT]; 435 436 /* local device database list (contains internal ddb entries) */ 437 struct list_head ddb_list; 438 439 /* Map ddb_list entry by FW ddb index */ 440 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES]; 441 442 /* Saved srb for status continuation entry processing */ 443 struct srb *status_srb; 444 }; 445 446 static inline int is_qla4010(struct scsi_qla_host *ha) 447 { 448 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010; 449 } 450 451 static inline int is_qla4022(struct scsi_qla_host *ha) 452 { 453 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; 454 } 455 456 static inline int is_qla4032(struct scsi_qla_host *ha) 457 { 458 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032; 459 } 460 461 static inline int adapter_up(struct scsi_qla_host *ha) 462 { 463 return (test_bit(AF_ONLINE, &ha->flags) != 0) && 464 (test_bit(AF_LINK_UP, &ha->flags) != 0); 465 } 466 467 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost) 468 { 469 return (struct scsi_qla_host *)shost->hostdata; 470 } 471 472 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) 473 { 474 return (is_qla4010(ha) ? 475 &ha->reg->u1.isp4010.nvram : 476 &ha->reg->u1.isp4022.semaphore); 477 } 478 479 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) 480 { 481 return (is_qla4010(ha) ? 482 &ha->reg->u1.isp4010.nvram : 483 &ha->reg->u1.isp4022.nvram); 484 } 485 486 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) 487 { 488 return (is_qla4010(ha) ? 489 &ha->reg->u2.isp4010.ext_hw_conf : 490 &ha->reg->u2.isp4022.p0.ext_hw_conf); 491 } 492 493 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) 494 { 495 return (is_qla4010(ha) ? 496 &ha->reg->u2.isp4010.port_status : 497 &ha->reg->u2.isp4022.p0.port_status); 498 } 499 500 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) 501 { 502 return (is_qla4010(ha) ? 503 &ha->reg->u2.isp4010.port_ctrl : 504 &ha->reg->u2.isp4022.p0.port_ctrl); 505 } 506 507 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) 508 { 509 return (is_qla4010(ha) ? 510 &ha->reg->u2.isp4010.port_err_status : 511 &ha->reg->u2.isp4022.p0.port_err_status); 512 } 513 514 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) 515 { 516 return (is_qla4010(ha) ? 517 &ha->reg->u2.isp4010.gp_out : 518 &ha->reg->u2.isp4022.p0.gp_out); 519 } 520 521 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) 522 { 523 return (is_qla4010(ha) ? 524 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 : 525 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2); 526 } 527 528 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 529 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask); 530 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 531 532 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) 533 { 534 if (is_qla4010(a)) 535 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, 536 QL4010_FLASH_SEM_BITS); 537 else 538 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, 539 (QL4022_RESOURCE_BITS_BASE_CODE | 540 (a->mac_index)) << 13); 541 } 542 543 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) 544 { 545 if (is_qla4010(a)) 546 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); 547 else 548 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); 549 } 550 551 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) 552 { 553 if (is_qla4010(a)) 554 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, 555 QL4010_NVRAM_SEM_BITS); 556 else 557 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, 558 (QL4022_RESOURCE_BITS_BASE_CODE | 559 (a->mac_index)) << 10); 560 } 561 562 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) 563 { 564 if (is_qla4010(a)) 565 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); 566 else 567 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); 568 } 569 570 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) 571 { 572 if (is_qla4010(a)) 573 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, 574 QL4010_DRVR_SEM_BITS); 575 else 576 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, 577 (QL4022_RESOURCE_BITS_BASE_CODE | 578 (a->mac_index)) << 1); 579 } 580 581 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) 582 { 583 if (is_qla4010(a)) 584 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); 585 else 586 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); 587 } 588 589 /*---------------------------------------------------------------------------*/ 590 591 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */ 592 #define PRESERVE_DDB_LIST 0 593 #define REBUILD_DDB_LIST 1 594 595 /* Defines for process_aen() */ 596 #define PROCESS_ALL_AENS 0 597 #define FLUSH_DDB_CHANGED_AENS 1 598 #define RELOGIN_DDB_CHANGED_AENS 2 599 600 #endif /*_QLA4XXX_H */ 601