1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8 #ifndef __QL4_DEF_H 9 #define __QL4_DEF_H 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/module.h> 15 #include <linux/list.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/sched.h> 19 #include <linux/slab.h> 20 #include <linux/dmapool.h> 21 #include <linux/mempool.h> 22 #include <linux/spinlock.h> 23 #include <linux/workqueue.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/mutex.h> 27 #include <linux/aer.h> 28 #include <linux/bsg-lib.h> 29 #include <linux/vmalloc.h> 30 31 #include <net/tcp.h> 32 #include <scsi/scsi.h> 33 #include <scsi/scsi_host.h> 34 #include <scsi/scsi_device.h> 35 #include <scsi/scsi_cmnd.h> 36 #include <scsi/scsi_transport.h> 37 #include <scsi/scsi_transport_iscsi.h> 38 #include <scsi/scsi_bsg_iscsi.h> 39 #include <scsi/scsi_netlink.h> 40 #include <scsi/libiscsi.h> 41 42 #include "ql4_dbg.h" 43 #include "ql4_nx.h" 44 #include "ql4_fw.h" 45 #include "ql4_nvram.h" 46 #include "ql4_83xx.h" 47 48 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010 49 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010 50 #endif 51 52 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 53 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 54 #endif 55 56 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032 57 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032 58 #endif 59 60 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022 61 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022 62 #endif 63 64 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324 65 #define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032 66 #endif 67 68 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8042 69 #define PCI_DEVICE_ID_QLOGIC_ISP8042 0x8042 70 #endif 71 72 #define ISP4XXX_PCI_FN_1 0x1 73 #define ISP4XXX_PCI_FN_2 0x3 74 75 #define QLA_SUCCESS 0 76 #define QLA_ERROR 1 77 #define STATUS(status) status == QLA_ERROR ? "FAILED" : "SUCCEEDED" 78 79 /* 80 * Data bit definitions 81 */ 82 #define BIT_0 0x1 83 #define BIT_1 0x2 84 #define BIT_2 0x4 85 #define BIT_3 0x8 86 #define BIT_4 0x10 87 #define BIT_5 0x20 88 #define BIT_6 0x40 89 #define BIT_7 0x80 90 #define BIT_8 0x100 91 #define BIT_9 0x200 92 #define BIT_10 0x400 93 #define BIT_11 0x800 94 #define BIT_12 0x1000 95 #define BIT_13 0x2000 96 #define BIT_14 0x4000 97 #define BIT_15 0x8000 98 #define BIT_16 0x10000 99 #define BIT_17 0x20000 100 #define BIT_18 0x40000 101 #define BIT_19 0x80000 102 #define BIT_20 0x100000 103 #define BIT_21 0x200000 104 #define BIT_22 0x400000 105 #define BIT_23 0x800000 106 #define BIT_24 0x1000000 107 #define BIT_25 0x2000000 108 #define BIT_26 0x4000000 109 #define BIT_27 0x8000000 110 #define BIT_28 0x10000000 111 #define BIT_29 0x20000000 112 #define BIT_30 0x40000000 113 #define BIT_31 0x80000000 114 115 /** 116 * Macros to help code, maintain, etc. 117 **/ 118 #define ql4_printk(level, ha, format, arg...) \ 119 dev_printk(level , &((ha)->pdev->dev) , format , ## arg) 120 121 122 /* 123 * Host adapter default definitions 124 ***********************************/ 125 #define MAX_HBAS 16 126 #define MAX_BUSES 1 127 #define MAX_TARGETS MAX_DEV_DB_ENTRIES 128 #define MAX_LUNS 0xffff 129 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES 130 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES 131 #define MAX_PDU_ENTRIES 32 132 #define INVALID_ENTRY 0xFFFF 133 #define MAX_CMDS_TO_RISC 1024 134 #define MAX_SRBS MAX_CMDS_TO_RISC 135 #define MBOX_AEN_REG_COUNT 8 136 #define MAX_INIT_RETRIES 5 137 138 /* 139 * Buffer sizes 140 */ 141 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC 142 #define RESPONSE_QUEUE_DEPTH 64 143 #define QUEUE_SIZE 64 144 #define DMA_BUFFER_SIZE 512 145 #define IOCB_HIWAT_CUSHION 4 146 147 /* 148 * Misc 149 */ 150 #define MAC_ADDR_LEN 6 /* in bytes */ 151 #define IP_ADDR_LEN 4 /* in bytes */ 152 #define IPv6_ADDR_LEN 16 /* IPv6 address size */ 153 #define DRIVER_NAME "qla4xxx" 154 155 #define MAX_LINKED_CMDS_PER_LUN 3 156 #define MAX_REQS_SERVICED_PER_INTR 1 157 158 #define ISCSI_IPADDR_SIZE 4 /* IP address size */ 159 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */ 160 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */ 161 162 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */ 163 /* recovery timeout */ 164 165 #define LSDW(x) ((u32)((u64)(x))) 166 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16)) 167 168 #define DEV_DB_NON_PERSISTENT 0 169 #define DEV_DB_PERSISTENT 1 170 171 #define QL4_ISP_REG_DISCONNECT 0xffffffffU 172 173 #define COPY_ISID(dst_isid, src_isid) { \ 174 int i, j; \ 175 for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \ 176 dst_isid[i++] = src_isid[j--]; \ 177 } 178 179 #define SET_BITVAL(o, n, v) { \ 180 if (o) \ 181 n |= v; \ 182 else \ 183 n &= ~v; \ 184 } 185 186 #define OP_STATE(o, f, p) { \ 187 p = (o & f) ? "enable" : "disable"; \ 188 } 189 190 /* 191 * Retry & Timeout Values 192 */ 193 #define MBOX_TOV 60 194 #define SOFT_RESET_TOV 30 195 #define RESET_INTR_TOV 3 196 #define SEMAPHORE_TOV 10 197 #define ADAPTER_INIT_TOV 30 198 #define ADAPTER_RESET_TOV 180 199 #define EXTEND_CMD_TOV 60 200 #define WAIT_CMD_TOV 5 201 #define EH_WAIT_CMD_TOV 120 202 #define FIRMWARE_UP_TOV 60 203 #define RESET_FIRMWARE_TOV 30 204 #define LOGOUT_TOV 10 205 #define IOCB_TOV_MARGIN 10 206 #define RELOGIN_TOV 18 207 #define ISNS_DEREG_TOV 5 208 #define HBA_ONLINE_TOV 30 209 #define DISABLE_ACB_TOV 30 210 #define IP_CONFIG_TOV 30 211 #define LOGIN_TOV 12 212 #define BOOT_LOGIN_RESP_TOV 60 213 214 #define MAX_RESET_HA_RETRIES 2 215 #define FW_ALIVE_WAIT_TOV 3 216 #define IDC_EXTEND_TOV 8 217 #define IDC_COMP_TOV 5 218 #define LINK_UP_COMP_TOV 30 219 220 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 221 222 /* 223 * SCSI Request Block structure (srb) that is placed 224 * on cmd->SCp location of every I/O [We have 22 bytes available] 225 */ 226 struct srb { 227 struct list_head list; /* (8) */ 228 struct scsi_qla_host *ha; /* HA the SP is queued on */ 229 struct ddb_entry *ddb; 230 uint16_t flags; /* (1) Status flags. */ 231 232 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */ 233 #define SRB_GOT_SENSE BIT_4 /* sense data received. */ 234 uint8_t state; /* (1) Status flags. */ 235 236 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */ 237 #define SRB_FREE_STATE 1 238 #define SRB_ACTIVE_STATE 3 239 #define SRB_ACTIVE_TIMEOUT_STATE 4 240 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */ 241 242 struct scsi_cmnd *cmd; /* (4) SCSI command block */ 243 dma_addr_t dma_handle; /* (4) for unmap of single transfers */ 244 struct kref srb_ref; /* reference count for this srb */ 245 uint8_t err_id; /* error id */ 246 #define SRB_ERR_PORT 1 /* Request failed because "port down" */ 247 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */ 248 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */ 249 #define SRB_ERR_OTHER 4 250 251 uint16_t reserved; 252 uint16_t iocb_tov; 253 uint16_t iocb_cnt; /* Number of used iocbs */ 254 uint16_t cc_stat; 255 256 /* Used for extended sense / status continuation */ 257 uint8_t *req_sense_ptr; 258 uint16_t req_sense_len; 259 uint16_t reserved2; 260 }; 261 262 /* Mailbox request block structure */ 263 struct mrb { 264 struct scsi_qla_host *ha; 265 struct mbox_cmd_iocb *mbox; 266 uint32_t mbox_cmd; 267 uint16_t iocb_cnt; /* Number of used iocbs */ 268 uint32_t pid; 269 }; 270 271 /* 272 * Asynchronous Event Queue structure 273 */ 274 struct aen { 275 uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; 276 }; 277 278 struct ql4_aen_log { 279 int count; 280 struct aen entry[MAX_AEN_ENTRIES]; 281 }; 282 283 /* 284 * Device Database (DDB) structure 285 */ 286 struct ddb_entry { 287 struct scsi_qla_host *ha; 288 struct iscsi_cls_session *sess; 289 struct iscsi_cls_conn *conn; 290 291 uint16_t fw_ddb_index; /* DDB firmware index */ 292 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */ 293 uint16_t ddb_type; 294 #define FLASH_DDB 0x01 295 296 struct dev_db_entry fw_ddb_entry; 297 int (*unblock_sess)(struct iscsi_cls_session *cls_session); 298 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index, 299 struct ddb_entry *ddb_entry, uint32_t state); 300 301 /* Driver Re-login */ 302 unsigned long flags; /* DDB Flags */ 303 #define DDB_CONN_CLOSE_FAILURE 0 /* 0x00000001 */ 304 305 uint16_t default_relogin_timeout; /* Max time to wait for 306 * relogin to complete */ 307 atomic_t retry_relogin_timer; /* Min Time between relogins 308 * (4000 only) */ 309 atomic_t relogin_timer; /* Max Time to wait for 310 * relogin to complete */ 311 atomic_t relogin_retry_count; /* Num of times relogin has been 312 * retried */ 313 uint32_t default_time2wait; /* Default Min time between 314 * relogins (+aens) */ 315 uint16_t chap_tbl_idx; 316 }; 317 318 struct qla_ddb_index { 319 struct list_head list; 320 uint16_t fw_ddb_idx; 321 uint16_t flash_ddb_idx; 322 struct dev_db_entry fw_ddb; 323 uint8_t flash_isid[6]; 324 }; 325 326 #define DDB_IPADDR_LEN 64 327 328 struct ql4_tuple_ddb { 329 int port; 330 int tpgt; 331 char ip_addr[DDB_IPADDR_LEN]; 332 char iscsi_name[ISCSI_NAME_SIZE]; 333 uint16_t options; 334 #define DDB_OPT_IPV6 0x0e0e 335 #define DDB_OPT_IPV4 0x0f0f 336 uint8_t isid[6]; 337 }; 338 339 /* 340 * DDB states. 341 */ 342 #define DDB_STATE_DEAD 0 /* We can no longer talk to 343 * this device */ 344 #define DDB_STATE_ONLINE 1 /* Device ready to accept 345 * commands */ 346 #define DDB_STATE_MISSING 2 /* Device logged off, trying 347 * to re-login */ 348 349 /* 350 * DDB flags. 351 */ 352 #define DF_RELOGIN 0 /* Relogin to device */ 353 #define DF_BOOT_TGT 1 /* Boot target entry */ 354 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */ 355 #define DF_FO_MASKED 3 356 #define DF_DISABLE_RELOGIN 4 /* Disable relogin to device */ 357 358 enum qla4_work_type { 359 QLA4_EVENT_AEN, 360 QLA4_EVENT_PING_STATUS, 361 }; 362 363 struct qla4_work_evt { 364 struct list_head list; 365 enum qla4_work_type type; 366 union { 367 struct { 368 enum iscsi_host_event_code code; 369 uint32_t data_size; 370 uint8_t data[0]; 371 } aen; 372 struct { 373 uint32_t status; 374 uint32_t pid; 375 uint32_t data_size; 376 uint8_t data[0]; 377 } ping; 378 } u; 379 }; 380 381 struct ql82xx_hw_data { 382 /* Offsets for flash/nvram access (set to ~0 if not used). */ 383 uint32_t flash_conf_off; 384 uint32_t flash_data_off; 385 386 uint32_t fdt_wrt_disable; 387 uint32_t fdt_erase_cmd; 388 uint32_t fdt_block_size; 389 uint32_t fdt_unprotect_sec_cmd; 390 uint32_t fdt_protect_sec_cmd; 391 392 uint32_t flt_region_flt; 393 uint32_t flt_region_fdt; 394 uint32_t flt_region_boot; 395 uint32_t flt_region_bootload; 396 uint32_t flt_region_fw; 397 398 uint32_t flt_iscsi_param; 399 uint32_t flt_region_chap; 400 uint32_t flt_chap_size; 401 uint32_t flt_region_ddb; 402 uint32_t flt_ddb_size; 403 }; 404 405 struct qla4_8xxx_legacy_intr_set { 406 uint32_t int_vec_bit; 407 uint32_t tgt_status_reg; 408 uint32_t tgt_mask_reg; 409 uint32_t pci_int_reg; 410 }; 411 412 /* MSI-X Support */ 413 #define QLA_MSIX_ENTRIES 2 414 415 /* 416 * ISP Operations 417 */ 418 struct isp_operations { 419 int (*iospace_config) (struct scsi_qla_host *ha); 420 void (*pci_config) (struct scsi_qla_host *); 421 void (*disable_intrs) (struct scsi_qla_host *); 422 void (*enable_intrs) (struct scsi_qla_host *); 423 int (*start_firmware) (struct scsi_qla_host *); 424 int (*restart_firmware) (struct scsi_qla_host *); 425 irqreturn_t (*intr_handler) (int , void *); 426 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t); 427 int (*need_reset) (struct scsi_qla_host *); 428 int (*reset_chip) (struct scsi_qla_host *); 429 int (*reset_firmware) (struct scsi_qla_host *); 430 void (*queue_iocb) (struct scsi_qla_host *); 431 void (*complete_iocb) (struct scsi_qla_host *); 432 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *); 433 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *); 434 int (*get_sys_info) (struct scsi_qla_host *); 435 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong); 436 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t); 437 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *); 438 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t); 439 int (*idc_lock) (struct scsi_qla_host *); 440 void (*idc_unlock) (struct scsi_qla_host *); 441 void (*rom_lock_recovery) (struct scsi_qla_host *); 442 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int); 443 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int); 444 }; 445 446 struct ql4_mdump_size_table { 447 uint32_t size; 448 uint32_t size_cmask_02; 449 uint32_t size_cmask_04; 450 uint32_t size_cmask_08; 451 uint32_t size_cmask_10; 452 uint32_t size_cmask_FF; 453 uint32_t version; 454 }; 455 456 /*qla4xxx ipaddress configuration details */ 457 struct ipaddress_config { 458 uint16_t ipv4_options; 459 uint16_t tcp_options; 460 uint16_t ipv4_vlan_tag; 461 uint8_t ipv4_addr_state; 462 uint8_t ip_address[IP_ADDR_LEN]; 463 uint8_t subnet_mask[IP_ADDR_LEN]; 464 uint8_t gateway[IP_ADDR_LEN]; 465 uint32_t ipv6_options; 466 uint32_t ipv6_addl_options; 467 uint8_t ipv6_link_local_state; 468 uint8_t ipv6_addr0_state; 469 uint8_t ipv6_addr1_state; 470 uint8_t ipv6_default_router_state; 471 uint16_t ipv6_vlan_tag; 472 struct in6_addr ipv6_link_local_addr; 473 struct in6_addr ipv6_addr0; 474 struct in6_addr ipv6_addr1; 475 struct in6_addr ipv6_default_router_addr; 476 uint16_t eth_mtu_size; 477 uint16_t ipv4_port; 478 uint16_t ipv6_port; 479 uint8_t control; 480 uint16_t ipv6_tcp_options; 481 uint8_t tcp_wsf; 482 uint8_t ipv6_tcp_wsf; 483 uint8_t ipv4_tos; 484 uint8_t ipv4_cache_id; 485 uint8_t ipv6_cache_id; 486 uint8_t ipv4_alt_cid_len; 487 uint8_t ipv4_alt_cid[11]; 488 uint8_t ipv4_vid_len; 489 uint8_t ipv4_vid[11]; 490 uint8_t ipv4_ttl; 491 uint16_t ipv6_flow_lbl; 492 uint8_t ipv6_traffic_class; 493 uint8_t ipv6_hop_limit; 494 uint32_t ipv6_nd_reach_time; 495 uint32_t ipv6_nd_rexmit_timer; 496 uint32_t ipv6_nd_stale_timeout; 497 uint8_t ipv6_dup_addr_detect_count; 498 uint32_t ipv6_gw_advrt_mtu; 499 uint16_t def_timeout; 500 uint8_t abort_timer; 501 uint16_t iscsi_options; 502 uint16_t iscsi_max_pdu_size; 503 uint16_t iscsi_first_burst_len; 504 uint16_t iscsi_max_outstnd_r2t; 505 uint16_t iscsi_max_burst_len; 506 uint8_t iscsi_name[224]; 507 }; 508 509 #define QL4_CHAP_MAX_NAME_LEN 256 510 #define QL4_CHAP_MAX_SECRET_LEN 100 511 #define LOCAL_CHAP 0 512 #define BIDI_CHAP 1 513 514 struct ql4_chap_format { 515 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN]; 516 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN]; 517 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN]; 518 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN]; 519 u16 intr_chap_name_length; 520 u16 intr_secret_length; 521 u16 target_chap_name_length; 522 u16 target_secret_length; 523 }; 524 525 struct ip_address_format { 526 u8 ip_type; 527 u8 ip_address[16]; 528 }; 529 530 struct ql4_conn_info { 531 u16 dest_port; 532 struct ip_address_format dest_ipaddr; 533 struct ql4_chap_format chap; 534 }; 535 536 struct ql4_boot_session_info { 537 u8 target_name[224]; 538 struct ql4_conn_info conn_list[1]; 539 }; 540 541 struct ql4_boot_tgt_info { 542 struct ql4_boot_session_info boot_pri_sess; 543 struct ql4_boot_session_info boot_sec_sess; 544 }; 545 546 /* 547 * Linux Host Adapter structure 548 */ 549 struct scsi_qla_host { 550 /* Linux adapter configuration data */ 551 unsigned long flags; 552 553 #define AF_ONLINE 0 /* 0x00000001 */ 554 #define AF_INIT_DONE 1 /* 0x00000002 */ 555 #define AF_MBOX_COMMAND 2 /* 0x00000004 */ 556 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */ 557 #define AF_ST_DISCOVERY_IN_PROGRESS 4 /* 0x00000010 */ 558 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */ 559 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ 560 #define AF_LINK_UP 8 /* 0x00000100 */ 561 #define AF_LOOPBACK 9 /* 0x00000200 */ 562 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */ 563 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */ 564 #define AF_HA_REMOVAL 12 /* 0x00001000 */ 565 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */ 566 #define AF_FW_RECOVERY 19 /* 0x00080000 */ 567 #define AF_EEH_BUSY 20 /* 0x00100000 */ 568 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */ 569 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */ 570 #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */ 571 #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */ 572 #define AF_82XX_DUMP_READING 26 /* 0x04000000 */ 573 #define AF_83XX_IOCB_INTR_ON 28 /* 0x10000000 */ 574 #define AF_83XX_MBOX_INTR_ON 29 /* 0x20000000 */ 575 576 unsigned long dpc_flags; 577 578 #define DPC_RESET_HA 1 /* 0x00000002 */ 579 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */ 580 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */ 581 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */ 582 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */ 583 #define DPC_ISNS_RESTART 7 /* 0x00000080 */ 584 #define DPC_AEN 9 /* 0x00000200 */ 585 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */ 586 #define DPC_LINK_CHANGED 18 /* 0x00040000 */ 587 #define DPC_RESET_ACTIVE 20 /* 0x00100000 */ 588 #define DPC_HA_UNRECOVERABLE 21 /* 0x00200000 ISP-82xx only*/ 589 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00400000 ISP-82xx only*/ 590 #define DPC_POST_IDC_ACK 23 /* 0x00800000 */ 591 #define DPC_RESTORE_ACB 24 /* 0x01000000 */ 592 #define DPC_SYSFS_DDB_EXPORT 25 /* 0x02000000 */ 593 594 struct Scsi_Host *host; /* pointer to host data */ 595 uint32_t tot_ddbs; 596 597 uint16_t iocb_cnt; 598 uint16_t iocb_hiwat; 599 600 /* SRB cache. */ 601 #define SRB_MIN_REQ 128 602 mempool_t *srb_mempool; 603 604 /* pci information */ 605 struct pci_dev *pdev; 606 607 struct isp_reg __iomem *reg; /* Base I/O address */ 608 unsigned long pio_address; 609 unsigned long pio_length; 610 #define MIN_IOBASE_LEN 0x100 611 612 uint16_t req_q_count; 613 614 unsigned long host_no; 615 616 /* NVRAM registers */ 617 struct eeprom_data *nvram; 618 spinlock_t hardware_lock ____cacheline_aligned; 619 uint32_t eeprom_cmd_data; 620 621 /* Counters for general statistics */ 622 uint64_t isr_count; 623 uint64_t adapter_error_count; 624 uint64_t device_error_count; 625 uint64_t total_io_count; 626 uint64_t total_mbytes_xferred; 627 uint64_t link_failure_count; 628 uint64_t invalid_crc_count; 629 uint32_t bytes_xfered; 630 uint32_t spurious_int_count; 631 uint32_t aborted_io_count; 632 uint32_t io_timeout_count; 633 uint32_t mailbox_timeout_count; 634 uint32_t seconds_since_last_intr; 635 uint32_t seconds_since_last_heartbeat; 636 uint32_t mac_index; 637 638 /* Info Needed for Management App */ 639 /* --- From GetFwVersion --- */ 640 uint32_t firmware_version[2]; 641 uint32_t patch_number; 642 uint32_t build_number; 643 uint32_t board_id; 644 645 /* --- From Init_FW --- */ 646 /* init_cb_t *init_cb; */ 647 uint16_t firmware_options; 648 uint8_t alias[32]; 649 uint8_t name_string[256]; 650 uint8_t heartbeat_interval; 651 652 /* --- From FlashSysInfo --- */ 653 uint8_t my_mac[MAC_ADDR_LEN]; 654 uint8_t serial_number[16]; 655 uint16_t port_num; 656 /* --- From GetFwState --- */ 657 uint32_t firmware_state; 658 uint32_t addl_fw_state; 659 660 /* Linux kernel thread */ 661 struct workqueue_struct *dpc_thread; 662 struct work_struct dpc_work; 663 664 /* Linux timer thread */ 665 struct timer_list timer; 666 uint32_t timer_active; 667 668 /* Recovery Timers */ 669 atomic_t check_relogin_timeouts; 670 uint32_t retry_reset_ha_cnt; 671 uint32_t isp_reset_timer; /* reset test timer */ 672 uint32_t nic_reset_timer; /* simulated nic reset test timer */ 673 int eh_start; 674 struct list_head free_srb_q; 675 uint16_t free_srb_q_count; 676 uint16_t num_srbs_allocated; 677 678 /* DMA Memory Block */ 679 void *queues; 680 dma_addr_t queues_dma; 681 unsigned long queues_len; 682 683 #define MEM_ALIGN_VALUE \ 684 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \ 685 sizeof(struct queue_entry)) 686 /* request and response queue variables */ 687 dma_addr_t request_dma; 688 struct queue_entry *request_ring; 689 struct queue_entry *request_ptr; 690 dma_addr_t response_dma; 691 struct queue_entry *response_ring; 692 struct queue_entry *response_ptr; 693 dma_addr_t shadow_regs_dma; 694 struct shadow_regs *shadow_regs; 695 uint16_t request_in; /* Current indexes. */ 696 uint16_t request_out; 697 uint16_t response_in; 698 uint16_t response_out; 699 700 /* aen queue variables */ 701 uint16_t aen_q_count; /* Number of available aen_q entries */ 702 uint16_t aen_in; /* Current indexes */ 703 uint16_t aen_out; 704 struct aen aen_q[MAX_AEN_ENTRIES]; 705 706 struct ql4_aen_log aen_log;/* tracks all aens */ 707 708 /* This mutex protects several threads to do mailbox commands 709 * concurrently. 710 */ 711 struct mutex mbox_sem; 712 713 /* temporary mailbox status registers */ 714 volatile uint8_t mbox_status_count; 715 volatile uint32_t mbox_status[MBOX_REG_COUNT]; 716 717 /* FW ddb index map */ 718 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES]; 719 720 /* Saved srb for status continuation entry processing */ 721 struct srb *status_srb; 722 723 uint8_t acb_version; 724 725 /* qla82xx specific fields */ 726 struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */ 727 unsigned long nx_pcibase; /* Base I/O address */ 728 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */ 729 unsigned long nx_db_wr_ptr; /* Door bell write pointer */ 730 unsigned long first_page_group_start; 731 unsigned long first_page_group_end; 732 733 uint32_t crb_win; 734 uint32_t curr_window; 735 uint32_t ddr_mn_window; 736 unsigned long mn_win_crb; 737 unsigned long ms_win_crb; 738 int qdr_sn_window; 739 rwlock_t hw_lock; 740 uint16_t func_num; 741 int link_width; 742 743 struct qla4_8xxx_legacy_intr_set nx_legacy_intr; 744 u32 nx_crb_mask; 745 746 uint8_t revision_id; 747 uint32_t fw_heartbeat_counter; 748 749 struct isp_operations *isp_ops; 750 struct ql82xx_hw_data hw; 751 752 uint32_t nx_dev_init_timeout; 753 uint32_t nx_reset_timeout; 754 void *fw_dump; 755 uint32_t fw_dump_size; 756 uint32_t fw_dump_capture_mask; 757 void *fw_dump_tmplt_hdr; 758 uint32_t fw_dump_tmplt_size; 759 uint32_t fw_dump_skip_size; 760 761 struct completion mbx_intr_comp; 762 763 struct ipaddress_config ip_config; 764 struct iscsi_iface *iface_ipv4; 765 struct iscsi_iface *iface_ipv6_0; 766 struct iscsi_iface *iface_ipv6_1; 767 768 /* --- From About Firmware --- */ 769 struct about_fw_info fw_info; 770 uint32_t fw_uptime_secs; /* seconds elapsed since fw bootup */ 771 uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */ 772 uint16_t def_timeout; /* Default login timeout */ 773 774 uint32_t flash_state; 775 #define QLFLASH_WAITING 0 776 #define QLFLASH_READING 1 777 #define QLFLASH_WRITING 2 778 struct dma_pool *chap_dma_pool; 779 uint8_t *chap_list; /* CHAP table cache */ 780 struct mutex chap_sem; 781 782 #define CHAP_DMA_BLOCK_SIZE 512 783 struct workqueue_struct *task_wq; 784 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG]; 785 #define SYSFS_FLAG_FW_SEL_BOOT 2 786 struct iscsi_boot_kset *boot_kset; 787 struct ql4_boot_tgt_info boot_tgt; 788 uint16_t phy_port_num; 789 uint16_t phy_port_cnt; 790 uint16_t iscsi_pci_func_cnt; 791 uint8_t model_name[16]; 792 struct completion disable_acb_comp; 793 struct dma_pool *fw_ddb_dma_pool; 794 #define DDB_DMA_BLOCK_SIZE 512 795 uint16_t pri_ddb_idx; 796 uint16_t sec_ddb_idx; 797 int is_reset; 798 uint16_t temperature; 799 800 /* event work list */ 801 struct list_head work_list; 802 spinlock_t work_lock; 803 804 /* mbox iocb */ 805 #define MAX_MRB 128 806 struct mrb *active_mrb_array[MAX_MRB]; 807 uint32_t mrb_index; 808 809 uint32_t *reg_tbl; 810 struct qla4_83xx_reset_template reset_tmplt; 811 struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address 812 for ISP8324 and 813 and ISP8042 */ 814 uint32_t pf_bit; 815 struct qla4_83xx_idc_information idc_info; 816 struct addr_ctrl_blk *saved_acb; 817 int notify_idc_comp; 818 int notify_link_up_comp; 819 int idc_extend_tmo; 820 struct completion idc_comp; 821 struct completion link_up_comp; 822 }; 823 824 struct ql4_task_data { 825 struct scsi_qla_host *ha; 826 uint8_t iocb_req_cnt; 827 dma_addr_t data_dma; 828 void *req_buffer; 829 dma_addr_t req_dma; 830 uint32_t req_len; 831 void *resp_buffer; 832 dma_addr_t resp_dma; 833 uint32_t resp_len; 834 struct iscsi_task *task; 835 struct passthru_status sts; 836 struct work_struct task_work; 837 }; 838 839 struct qla_endpoint { 840 struct Scsi_Host *host; 841 struct sockaddr_storage dst_addr; 842 }; 843 844 struct qla_conn { 845 struct qla_endpoint *qla_ep; 846 }; 847 848 static inline int is_ipv4_enabled(struct scsi_qla_host *ha) 849 { 850 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0); 851 } 852 853 static inline int is_ipv6_enabled(struct scsi_qla_host *ha) 854 { 855 return ((ha->ip_config.ipv6_options & 856 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0); 857 } 858 859 static inline int is_qla4010(struct scsi_qla_host *ha) 860 { 861 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010; 862 } 863 864 static inline int is_qla4022(struct scsi_qla_host *ha) 865 { 866 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; 867 } 868 869 static inline int is_qla4032(struct scsi_qla_host *ha) 870 { 871 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032; 872 } 873 874 static inline int is_qla40XX(struct scsi_qla_host *ha) 875 { 876 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha); 877 } 878 879 static inline int is_qla8022(struct scsi_qla_host *ha) 880 { 881 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 882 } 883 884 static inline int is_qla8032(struct scsi_qla_host *ha) 885 { 886 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324; 887 } 888 889 static inline int is_qla8042(struct scsi_qla_host *ha) 890 { 891 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042; 892 } 893 894 static inline int is_qla80XX(struct scsi_qla_host *ha) 895 { 896 return is_qla8022(ha) || is_qla8032(ha) || is_qla8042(ha); 897 } 898 899 static inline int is_aer_supported(struct scsi_qla_host *ha) 900 { 901 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) || 902 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324) || 903 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042)); 904 } 905 906 static inline int adapter_up(struct scsi_qla_host *ha) 907 { 908 return (test_bit(AF_ONLINE, &ha->flags) != 0) && 909 (test_bit(AF_LINK_UP, &ha->flags) != 0) && 910 (!test_bit(AF_LOOPBACK, &ha->flags)); 911 } 912 913 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost) 914 { 915 return (struct scsi_qla_host *)iscsi_host_priv(shost); 916 } 917 918 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) 919 { 920 return (is_qla4010(ha) ? 921 &ha->reg->u1.isp4010.nvram : 922 &ha->reg->u1.isp4022.semaphore); 923 } 924 925 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) 926 { 927 return (is_qla4010(ha) ? 928 &ha->reg->u1.isp4010.nvram : 929 &ha->reg->u1.isp4022.nvram); 930 } 931 932 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) 933 { 934 return (is_qla4010(ha) ? 935 &ha->reg->u2.isp4010.ext_hw_conf : 936 &ha->reg->u2.isp4022.p0.ext_hw_conf); 937 } 938 939 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) 940 { 941 return (is_qla4010(ha) ? 942 &ha->reg->u2.isp4010.port_status : 943 &ha->reg->u2.isp4022.p0.port_status); 944 } 945 946 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) 947 { 948 return (is_qla4010(ha) ? 949 &ha->reg->u2.isp4010.port_ctrl : 950 &ha->reg->u2.isp4022.p0.port_ctrl); 951 } 952 953 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) 954 { 955 return (is_qla4010(ha) ? 956 &ha->reg->u2.isp4010.port_err_status : 957 &ha->reg->u2.isp4022.p0.port_err_status); 958 } 959 960 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) 961 { 962 return (is_qla4010(ha) ? 963 &ha->reg->u2.isp4010.gp_out : 964 &ha->reg->u2.isp4022.p0.gp_out); 965 } 966 967 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) 968 { 969 return (is_qla4010(ha) ? 970 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 : 971 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2); 972 } 973 974 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 975 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask); 976 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 977 978 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) 979 { 980 if (is_qla4010(a)) 981 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, 982 QL4010_FLASH_SEM_BITS); 983 else 984 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, 985 (QL4022_RESOURCE_BITS_BASE_CODE | 986 (a->mac_index)) << 13); 987 } 988 989 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) 990 { 991 if (is_qla4010(a)) 992 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); 993 else 994 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); 995 } 996 997 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) 998 { 999 if (is_qla4010(a)) 1000 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, 1001 QL4010_NVRAM_SEM_BITS); 1002 else 1003 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, 1004 (QL4022_RESOURCE_BITS_BASE_CODE | 1005 (a->mac_index)) << 10); 1006 } 1007 1008 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) 1009 { 1010 if (is_qla4010(a)) 1011 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); 1012 else 1013 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); 1014 } 1015 1016 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) 1017 { 1018 if (is_qla4010(a)) 1019 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, 1020 QL4010_DRVR_SEM_BITS); 1021 else 1022 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, 1023 (QL4022_RESOURCE_BITS_BASE_CODE | 1024 (a->mac_index)) << 1); 1025 } 1026 1027 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) 1028 { 1029 if (is_qla4010(a)) 1030 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); 1031 else 1032 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); 1033 } 1034 1035 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha) 1036 { 1037 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) || 1038 test_bit(DPC_RESET_HA, &ha->dpc_flags) || 1039 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) || 1040 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) || 1041 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) || 1042 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags); 1043 1044 } 1045 1046 static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha, 1047 const uint32_t crb_reg) 1048 { 1049 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]); 1050 } 1051 1052 static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha, 1053 const uint32_t crb_reg, 1054 const uint32_t value) 1055 { 1056 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value); 1057 } 1058 1059 /*---------------------------------------------------------------------------*/ 1060 1061 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */ 1062 1063 #define INIT_ADAPTER 0 1064 #define RESET_ADAPTER 1 1065 1066 #define PRESERVE_DDB_LIST 0 1067 #define REBUILD_DDB_LIST 1 1068 1069 /* Defines for process_aen() */ 1070 #define PROCESS_ALL_AENS 0 1071 #define FLUSH_DDB_CHANGED_AENS 1 1072 1073 /* Defines for udev events */ 1074 #define QL4_UEVENT_CODE_FW_DUMP 0 1075 1076 #endif /*_QLA4XXX_H */ 1077