1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * QLogic iSCSI HBA Driver 4 * Copyright (c) 2003-2013 QLogic Corporation 5 */ 6 7 #ifndef __QL4_DEF_H 8 #define __QL4_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/workqueue.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/mutex.h> 26 #include <linux/aer.h> 27 #include <linux/bsg-lib.h> 28 #include <linux/vmalloc.h> 29 30 #include <net/tcp.h> 31 #include <scsi/scsi.h> 32 #include <scsi/scsi_host.h> 33 #include <scsi/scsi_device.h> 34 #include <scsi/scsi_cmnd.h> 35 #include <scsi/scsi_transport.h> 36 #include <scsi/scsi_transport_iscsi.h> 37 #include <scsi/scsi_bsg_iscsi.h> 38 #include <scsi/scsi_netlink.h> 39 #include <scsi/libiscsi.h> 40 41 #include "ql4_dbg.h" 42 #include "ql4_nx.h" 43 #include "ql4_fw.h" 44 #include "ql4_nvram.h" 45 #include "ql4_83xx.h" 46 47 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010 48 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010 49 #endif 50 51 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 52 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 53 #endif 54 55 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032 56 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032 57 #endif 58 59 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022 60 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022 61 #endif 62 63 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324 64 #define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032 65 #endif 66 67 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8042 68 #define PCI_DEVICE_ID_QLOGIC_ISP8042 0x8042 69 #endif 70 71 #define ISP4XXX_PCI_FN_1 0x1 72 #define ISP4XXX_PCI_FN_2 0x3 73 74 #define QLA_SUCCESS 0 75 #define QLA_ERROR 1 76 #define STATUS(status) status == QLA_ERROR ? "FAILED" : "SUCCEEDED" 77 78 /* 79 * Data bit definitions 80 */ 81 #define BIT_0 0x1 82 #define BIT_1 0x2 83 #define BIT_2 0x4 84 #define BIT_3 0x8 85 #define BIT_4 0x10 86 #define BIT_5 0x20 87 #define BIT_6 0x40 88 #define BIT_7 0x80 89 #define BIT_8 0x100 90 #define BIT_9 0x200 91 #define BIT_10 0x400 92 #define BIT_11 0x800 93 #define BIT_12 0x1000 94 #define BIT_13 0x2000 95 #define BIT_14 0x4000 96 #define BIT_15 0x8000 97 #define BIT_16 0x10000 98 #define BIT_17 0x20000 99 #define BIT_18 0x40000 100 #define BIT_19 0x80000 101 #define BIT_20 0x100000 102 #define BIT_21 0x200000 103 #define BIT_22 0x400000 104 #define BIT_23 0x800000 105 #define BIT_24 0x1000000 106 #define BIT_25 0x2000000 107 #define BIT_26 0x4000000 108 #define BIT_27 0x8000000 109 #define BIT_28 0x10000000 110 #define BIT_29 0x20000000 111 #define BIT_30 0x40000000 112 #define BIT_31 0x80000000 113 114 /** 115 * Macros to help code, maintain, etc. 116 **/ 117 #define ql4_printk(level, ha, format, arg...) \ 118 dev_printk(level , &((ha)->pdev->dev) , format , ## arg) 119 120 121 /* 122 * Host adapter default definitions 123 ***********************************/ 124 #define MAX_HBAS 16 125 #define MAX_BUSES 1 126 #define MAX_TARGETS MAX_DEV_DB_ENTRIES 127 #define MAX_LUNS 0xffff 128 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES 129 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES 130 #define MAX_PDU_ENTRIES 32 131 #define INVALID_ENTRY 0xFFFF 132 #define MAX_CMDS_TO_RISC 1024 133 #define MAX_SRBS MAX_CMDS_TO_RISC 134 #define MBOX_AEN_REG_COUNT 8 135 #define MAX_INIT_RETRIES 5 136 137 /* 138 * Buffer sizes 139 */ 140 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC 141 #define RESPONSE_QUEUE_DEPTH 64 142 #define QUEUE_SIZE 64 143 #define DMA_BUFFER_SIZE 512 144 #define IOCB_HIWAT_CUSHION 4 145 146 /* 147 * Misc 148 */ 149 #define MAC_ADDR_LEN 6 /* in bytes */ 150 #define IP_ADDR_LEN 4 /* in bytes */ 151 #define IPv6_ADDR_LEN 16 /* IPv6 address size */ 152 #define DRIVER_NAME "qla4xxx" 153 154 #define MAX_LINKED_CMDS_PER_LUN 3 155 #define MAX_REQS_SERVICED_PER_INTR 1 156 157 #define ISCSI_IPADDR_SIZE 4 /* IP address size */ 158 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */ 159 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */ 160 161 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */ 162 /* recovery timeout */ 163 164 #define LSDW(x) ((u32)((u64)(x))) 165 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16)) 166 167 #define DEV_DB_NON_PERSISTENT 0 168 #define DEV_DB_PERSISTENT 1 169 170 #define QL4_ISP_REG_DISCONNECT 0xffffffffU 171 172 #define COPY_ISID(dst_isid, src_isid) { \ 173 int i, j; \ 174 for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \ 175 dst_isid[i++] = src_isid[j--]; \ 176 } 177 178 #define SET_BITVAL(o, n, v) { \ 179 if (o) \ 180 n |= v; \ 181 else \ 182 n &= ~v; \ 183 } 184 185 #define OP_STATE(o, f, p) { \ 186 p = (o & f) ? "enable" : "disable"; \ 187 } 188 189 /* 190 * Retry & Timeout Values 191 */ 192 #define MBOX_TOV 60 193 #define SOFT_RESET_TOV 30 194 #define RESET_INTR_TOV 3 195 #define SEMAPHORE_TOV 10 196 #define ADAPTER_INIT_TOV 30 197 #define ADAPTER_RESET_TOV 180 198 #define EXTEND_CMD_TOV 60 199 #define WAIT_CMD_TOV 5 200 #define EH_WAIT_CMD_TOV 120 201 #define FIRMWARE_UP_TOV 60 202 #define RESET_FIRMWARE_TOV 30 203 #define LOGOUT_TOV 10 204 #define IOCB_TOV_MARGIN 10 205 #define RELOGIN_TOV 18 206 #define ISNS_DEREG_TOV 5 207 #define HBA_ONLINE_TOV 30 208 #define DISABLE_ACB_TOV 30 209 #define IP_CONFIG_TOV 30 210 #define LOGIN_TOV 12 211 #define BOOT_LOGIN_RESP_TOV 60 212 213 #define MAX_RESET_HA_RETRIES 2 214 #define FW_ALIVE_WAIT_TOV 3 215 #define IDC_EXTEND_TOV 8 216 #define IDC_COMP_TOV 5 217 #define LINK_UP_COMP_TOV 30 218 219 /* 220 * Note: the data structure below does not have a struct iscsi_cmd member since 221 * the qla4xxx driver does not use libiscsi for SCSI I/O. 222 */ 223 struct qla4xxx_cmd_priv { 224 struct srb *srb; 225 }; 226 227 static inline struct qla4xxx_cmd_priv *qla4xxx_cmd_priv(struct scsi_cmnd *cmd) 228 { 229 return scsi_cmd_priv(cmd); 230 } 231 232 /* 233 * SCSI Request Block structure (srb) that is associated with each scsi_cmnd. 234 */ 235 struct srb { 236 struct list_head list; /* (8) */ 237 struct scsi_qla_host *ha; /* HA the SP is queued on */ 238 struct ddb_entry *ddb; 239 uint16_t flags; /* (1) Status flags. */ 240 241 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */ 242 #define SRB_GOT_SENSE BIT_4 /* sense data received. */ 243 uint8_t state; /* (1) Status flags. */ 244 245 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */ 246 #define SRB_FREE_STATE 1 247 #define SRB_ACTIVE_STATE 3 248 #define SRB_ACTIVE_TIMEOUT_STATE 4 249 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */ 250 251 struct scsi_cmnd *cmd; /* (4) SCSI command block */ 252 dma_addr_t dma_handle; /* (4) for unmap of single transfers */ 253 struct kref srb_ref; /* reference count for this srb */ 254 uint8_t err_id; /* error id */ 255 #define SRB_ERR_PORT 1 /* Request failed because "port down" */ 256 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */ 257 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */ 258 #define SRB_ERR_OTHER 4 259 260 uint16_t reserved; 261 uint16_t iocb_tov; 262 uint16_t iocb_cnt; /* Number of used iocbs */ 263 uint16_t cc_stat; 264 265 /* Used for extended sense / status continuation */ 266 uint8_t *req_sense_ptr; 267 uint16_t req_sense_len; 268 uint16_t reserved2; 269 }; 270 271 /* Mailbox request block structure */ 272 struct mrb { 273 struct scsi_qla_host *ha; 274 struct mbox_cmd_iocb *mbox; 275 uint32_t mbox_cmd; 276 uint16_t iocb_cnt; /* Number of used iocbs */ 277 uint32_t pid; 278 }; 279 280 /* 281 * Asynchronous Event Queue structure 282 */ 283 struct aen { 284 uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; 285 }; 286 287 struct ql4_aen_log { 288 int count; 289 struct aen entry[MAX_AEN_ENTRIES]; 290 }; 291 292 /* 293 * Device Database (DDB) structure 294 */ 295 struct ddb_entry { 296 struct scsi_qla_host *ha; 297 struct iscsi_cls_session *sess; 298 struct iscsi_cls_conn *conn; 299 300 uint16_t fw_ddb_index; /* DDB firmware index */ 301 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */ 302 uint16_t ddb_type; 303 #define FLASH_DDB 0x01 304 305 struct dev_db_entry fw_ddb_entry; 306 int (*unblock_sess)(struct iscsi_cls_session *cls_session); 307 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index, 308 struct ddb_entry *ddb_entry, uint32_t state); 309 310 /* Driver Re-login */ 311 unsigned long flags; /* DDB Flags */ 312 #define DDB_CONN_CLOSE_FAILURE 0 /* 0x00000001 */ 313 314 uint16_t default_relogin_timeout; /* Max time to wait for 315 * relogin to complete */ 316 atomic_t retry_relogin_timer; /* Min Time between relogins 317 * (4000 only) */ 318 atomic_t relogin_timer; /* Max Time to wait for 319 * relogin to complete */ 320 atomic_t relogin_retry_count; /* Num of times relogin has been 321 * retried */ 322 uint32_t default_time2wait; /* Default Min time between 323 * relogins (+aens) */ 324 uint16_t chap_tbl_idx; 325 }; 326 327 struct qla_ddb_index { 328 struct list_head list; 329 uint16_t fw_ddb_idx; 330 uint16_t flash_ddb_idx; 331 struct dev_db_entry fw_ddb; 332 uint8_t flash_isid[6]; 333 }; 334 335 #define DDB_IPADDR_LEN 64 336 337 struct ql4_tuple_ddb { 338 int port; 339 int tpgt; 340 char ip_addr[DDB_IPADDR_LEN]; 341 char iscsi_name[ISCSI_NAME_SIZE]; 342 uint16_t options; 343 #define DDB_OPT_IPV6 0x0e0e 344 #define DDB_OPT_IPV4 0x0f0f 345 uint8_t isid[6]; 346 }; 347 348 /* 349 * DDB states. 350 */ 351 #define DDB_STATE_DEAD 0 /* We can no longer talk to 352 * this device */ 353 #define DDB_STATE_ONLINE 1 /* Device ready to accept 354 * commands */ 355 #define DDB_STATE_MISSING 2 /* Device logged off, trying 356 * to re-login */ 357 358 /* 359 * DDB flags. 360 */ 361 #define DF_RELOGIN 0 /* Relogin to device */ 362 #define DF_BOOT_TGT 1 /* Boot target entry */ 363 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */ 364 #define DF_FO_MASKED 3 365 #define DF_DISABLE_RELOGIN 4 /* Disable relogin to device */ 366 367 enum qla4_work_type { 368 QLA4_EVENT_AEN, 369 QLA4_EVENT_PING_STATUS, 370 }; 371 372 struct qla4_work_evt { 373 struct list_head list; 374 enum qla4_work_type type; 375 union { 376 struct { 377 enum iscsi_host_event_code code; 378 uint32_t data_size; 379 uint8_t data[]; 380 } aen; 381 struct { 382 uint32_t status; 383 uint32_t pid; 384 uint32_t data_size; 385 uint8_t data[]; 386 } ping; 387 } u; 388 }; 389 390 struct ql82xx_hw_data { 391 /* Offsets for flash/nvram access (set to ~0 if not used). */ 392 uint32_t flash_conf_off; 393 uint32_t flash_data_off; 394 395 uint32_t fdt_wrt_disable; 396 uint32_t fdt_erase_cmd; 397 uint32_t fdt_block_size; 398 uint32_t fdt_unprotect_sec_cmd; 399 uint32_t fdt_protect_sec_cmd; 400 401 uint32_t flt_region_flt; 402 uint32_t flt_region_fdt; 403 uint32_t flt_region_boot; 404 uint32_t flt_region_bootload; 405 uint32_t flt_region_fw; 406 407 uint32_t flt_iscsi_param; 408 uint32_t flt_region_chap; 409 uint32_t flt_chap_size; 410 uint32_t flt_region_ddb; 411 uint32_t flt_ddb_size; 412 }; 413 414 struct qla4_8xxx_legacy_intr_set { 415 uint32_t int_vec_bit; 416 uint32_t tgt_status_reg; 417 uint32_t tgt_mask_reg; 418 uint32_t pci_int_reg; 419 }; 420 421 /* MSI-X Support */ 422 #define QLA_MSIX_ENTRIES 2 423 424 /* 425 * ISP Operations 426 */ 427 struct isp_operations { 428 int (*iospace_config) (struct scsi_qla_host *ha); 429 void (*pci_config) (struct scsi_qla_host *); 430 void (*disable_intrs) (struct scsi_qla_host *); 431 void (*enable_intrs) (struct scsi_qla_host *); 432 int (*start_firmware) (struct scsi_qla_host *); 433 int (*restart_firmware) (struct scsi_qla_host *); 434 irqreturn_t (*intr_handler) (int , void *); 435 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t); 436 int (*need_reset) (struct scsi_qla_host *); 437 int (*reset_chip) (struct scsi_qla_host *); 438 int (*reset_firmware) (struct scsi_qla_host *); 439 void (*queue_iocb) (struct scsi_qla_host *); 440 void (*complete_iocb) (struct scsi_qla_host *); 441 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *); 442 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *); 443 int (*get_sys_info) (struct scsi_qla_host *); 444 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong); 445 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t); 446 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *); 447 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t); 448 int (*idc_lock) (struct scsi_qla_host *); /* Context: task, can sleep */ 449 void (*idc_unlock) (struct scsi_qla_host *); 450 void (*rom_lock_recovery) (struct scsi_qla_host *); /* Context: task, can sleep */ 451 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int); 452 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int); 453 }; 454 455 struct ql4_mdump_size_table { 456 uint32_t size; 457 uint32_t size_cmask_02; 458 uint32_t size_cmask_04; 459 uint32_t size_cmask_08; 460 uint32_t size_cmask_10; 461 uint32_t size_cmask_FF; 462 uint32_t version; 463 }; 464 465 /*qla4xxx ipaddress configuration details */ 466 struct ipaddress_config { 467 uint16_t ipv4_options; 468 uint16_t tcp_options; 469 uint16_t ipv4_vlan_tag; 470 uint8_t ipv4_addr_state; 471 uint8_t ip_address[IP_ADDR_LEN]; 472 uint8_t subnet_mask[IP_ADDR_LEN]; 473 uint8_t gateway[IP_ADDR_LEN]; 474 uint32_t ipv6_options; 475 uint32_t ipv6_addl_options; 476 uint8_t ipv6_link_local_state; 477 uint8_t ipv6_addr0_state; 478 uint8_t ipv6_addr1_state; 479 uint8_t ipv6_default_router_state; 480 uint16_t ipv6_vlan_tag; 481 struct in6_addr ipv6_link_local_addr; 482 struct in6_addr ipv6_addr0; 483 struct in6_addr ipv6_addr1; 484 struct in6_addr ipv6_default_router_addr; 485 uint16_t eth_mtu_size; 486 uint16_t ipv4_port; 487 uint16_t ipv6_port; 488 uint8_t control; 489 uint16_t ipv6_tcp_options; 490 uint8_t tcp_wsf; 491 uint8_t ipv6_tcp_wsf; 492 uint8_t ipv4_tos; 493 uint8_t ipv4_cache_id; 494 uint8_t ipv6_cache_id; 495 uint8_t ipv4_alt_cid_len; 496 uint8_t ipv4_alt_cid[11]; 497 uint8_t ipv4_vid_len; 498 uint8_t ipv4_vid[11]; 499 uint8_t ipv4_ttl; 500 uint16_t ipv6_flow_lbl; 501 uint8_t ipv6_traffic_class; 502 uint8_t ipv6_hop_limit; 503 uint32_t ipv6_nd_reach_time; 504 uint32_t ipv6_nd_rexmit_timer; 505 uint32_t ipv6_nd_stale_timeout; 506 uint8_t ipv6_dup_addr_detect_count; 507 uint32_t ipv6_gw_advrt_mtu; 508 uint16_t def_timeout; 509 uint8_t abort_timer; 510 uint16_t iscsi_options; 511 uint16_t iscsi_max_pdu_size; 512 uint16_t iscsi_first_burst_len; 513 uint16_t iscsi_max_outstnd_r2t; 514 uint16_t iscsi_max_burst_len; 515 uint8_t iscsi_name[224]; 516 }; 517 518 #define QL4_CHAP_MAX_NAME_LEN 256 519 #define QL4_CHAP_MAX_SECRET_LEN 100 520 #define LOCAL_CHAP 0 521 #define BIDI_CHAP 1 522 523 struct ql4_chap_format { 524 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN]; 525 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN]; 526 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN]; 527 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN]; 528 u16 intr_chap_name_length; 529 u16 intr_secret_length; 530 u16 target_chap_name_length; 531 u16 target_secret_length; 532 }; 533 534 struct ip_address_format { 535 u8 ip_type; 536 u8 ip_address[16]; 537 }; 538 539 struct ql4_conn_info { 540 u16 dest_port; 541 struct ip_address_format dest_ipaddr; 542 struct ql4_chap_format chap; 543 }; 544 545 struct ql4_boot_session_info { 546 u8 target_name[224]; 547 struct ql4_conn_info conn_list[1]; 548 }; 549 550 struct ql4_boot_tgt_info { 551 struct ql4_boot_session_info boot_pri_sess; 552 struct ql4_boot_session_info boot_sec_sess; 553 }; 554 555 /* 556 * Linux Host Adapter structure 557 */ 558 struct scsi_qla_host { 559 /* Linux adapter configuration data */ 560 unsigned long flags; 561 562 #define AF_ONLINE 0 /* 0x00000001 */ 563 #define AF_INIT_DONE 1 /* 0x00000002 */ 564 #define AF_MBOX_COMMAND 2 /* 0x00000004 */ 565 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */ 566 #define AF_ST_DISCOVERY_IN_PROGRESS 4 /* 0x00000010 */ 567 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */ 568 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ 569 #define AF_LINK_UP 8 /* 0x00000100 */ 570 #define AF_LOOPBACK 9 /* 0x00000200 */ 571 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */ 572 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */ 573 #define AF_HA_REMOVAL 12 /* 0x00001000 */ 574 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */ 575 #define AF_FW_RECOVERY 19 /* 0x00080000 */ 576 #define AF_EEH_BUSY 20 /* 0x00100000 */ 577 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */ 578 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */ 579 #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */ 580 #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */ 581 #define AF_82XX_DUMP_READING 26 /* 0x04000000 */ 582 #define AF_83XX_IOCB_INTR_ON 28 /* 0x10000000 */ 583 #define AF_83XX_MBOX_INTR_ON 29 /* 0x20000000 */ 584 585 unsigned long dpc_flags; 586 587 #define DPC_RESET_HA 1 /* 0x00000002 */ 588 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */ 589 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */ 590 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */ 591 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */ 592 #define DPC_ISNS_RESTART 7 /* 0x00000080 */ 593 #define DPC_AEN 9 /* 0x00000200 */ 594 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */ 595 #define DPC_LINK_CHANGED 18 /* 0x00040000 */ 596 #define DPC_RESET_ACTIVE 20 /* 0x00100000 */ 597 #define DPC_HA_UNRECOVERABLE 21 /* 0x00200000 ISP-82xx only*/ 598 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00400000 ISP-82xx only*/ 599 #define DPC_POST_IDC_ACK 23 /* 0x00800000 */ 600 #define DPC_RESTORE_ACB 24 /* 0x01000000 */ 601 #define DPC_SYSFS_DDB_EXPORT 25 /* 0x02000000 */ 602 603 struct Scsi_Host *host; /* pointer to host data */ 604 uint32_t tot_ddbs; 605 606 uint16_t iocb_cnt; 607 uint16_t iocb_hiwat; 608 609 /* SRB cache. */ 610 #define SRB_MIN_REQ 128 611 mempool_t *srb_mempool; 612 613 /* pci information */ 614 struct pci_dev *pdev; 615 616 struct isp_reg __iomem *reg; /* Base I/O address */ 617 unsigned long pio_address; 618 unsigned long pio_length; 619 #define MIN_IOBASE_LEN 0x100 620 621 uint16_t req_q_count; 622 623 unsigned long host_no; 624 625 /* NVRAM registers */ 626 struct eeprom_data *nvram; 627 spinlock_t hardware_lock ____cacheline_aligned; 628 uint32_t eeprom_cmd_data; 629 630 /* Counters for general statistics */ 631 uint64_t isr_count; 632 uint64_t adapter_error_count; 633 uint64_t device_error_count; 634 uint64_t total_io_count; 635 uint64_t total_mbytes_xferred; 636 uint64_t link_failure_count; 637 uint64_t invalid_crc_count; 638 uint32_t bytes_xfered; 639 uint32_t spurious_int_count; 640 uint32_t aborted_io_count; 641 uint32_t io_timeout_count; 642 uint32_t mailbox_timeout_count; 643 uint32_t seconds_since_last_intr; 644 uint32_t seconds_since_last_heartbeat; 645 uint32_t mac_index; 646 647 /* Info Needed for Management App */ 648 /* --- From GetFwVersion --- */ 649 uint32_t firmware_version[2]; 650 uint32_t patch_number; 651 uint32_t build_number; 652 uint32_t board_id; 653 654 /* --- From Init_FW --- */ 655 /* init_cb_t *init_cb; */ 656 uint16_t firmware_options; 657 uint8_t alias[32]; 658 uint8_t name_string[256]; 659 uint8_t heartbeat_interval; 660 661 /* --- From FlashSysInfo --- */ 662 uint8_t my_mac[MAC_ADDR_LEN]; 663 uint8_t serial_number[16]; 664 uint16_t port_num; 665 /* --- From GetFwState --- */ 666 uint32_t firmware_state; 667 uint32_t addl_fw_state; 668 669 /* Linux kernel thread */ 670 struct workqueue_struct *dpc_thread; 671 struct work_struct dpc_work; 672 673 /* Linux timer thread */ 674 struct timer_list timer; 675 uint32_t timer_active; 676 677 /* Recovery Timers */ 678 atomic_t check_relogin_timeouts; 679 uint32_t retry_reset_ha_cnt; 680 uint32_t isp_reset_timer; /* reset test timer */ 681 uint32_t nic_reset_timer; /* simulated nic reset test timer */ 682 int eh_start; 683 struct list_head free_srb_q; 684 uint16_t free_srb_q_count; 685 uint16_t num_srbs_allocated; 686 687 /* DMA Memory Block */ 688 void *queues; 689 dma_addr_t queues_dma; 690 unsigned long queues_len; 691 692 #define MEM_ALIGN_VALUE \ 693 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \ 694 sizeof(struct queue_entry)) 695 /* request and response queue variables */ 696 dma_addr_t request_dma; 697 struct queue_entry *request_ring; 698 struct queue_entry *request_ptr; 699 dma_addr_t response_dma; 700 struct queue_entry *response_ring; 701 struct queue_entry *response_ptr; 702 dma_addr_t shadow_regs_dma; 703 struct shadow_regs *shadow_regs; 704 uint16_t request_in; /* Current indexes. */ 705 uint16_t request_out; 706 uint16_t response_in; 707 uint16_t response_out; 708 709 /* aen queue variables */ 710 uint16_t aen_q_count; /* Number of available aen_q entries */ 711 uint16_t aen_in; /* Current indexes */ 712 uint16_t aen_out; 713 struct aen aen_q[MAX_AEN_ENTRIES]; 714 715 struct ql4_aen_log aen_log;/* tracks all aens */ 716 717 /* This mutex protects several threads to do mailbox commands 718 * concurrently. 719 */ 720 struct mutex mbox_sem; 721 722 /* temporary mailbox status registers */ 723 volatile uint8_t mbox_status_count; 724 volatile uint32_t mbox_status[MBOX_REG_COUNT]; 725 726 /* FW ddb index map */ 727 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES]; 728 729 /* Saved srb for status continuation entry processing */ 730 struct srb *status_srb; 731 732 uint8_t acb_version; 733 734 /* qla82xx specific fields */ 735 struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */ 736 unsigned long nx_pcibase; /* Base I/O address */ 737 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */ 738 unsigned long nx_db_wr_ptr; /* Door bell write pointer */ 739 unsigned long first_page_group_start; 740 unsigned long first_page_group_end; 741 742 uint32_t crb_win; 743 uint32_t curr_window; 744 uint32_t ddr_mn_window; 745 unsigned long mn_win_crb; 746 unsigned long ms_win_crb; 747 int qdr_sn_window; 748 rwlock_t hw_lock; 749 uint16_t func_num; 750 int link_width; 751 752 struct qla4_8xxx_legacy_intr_set nx_legacy_intr; 753 u32 nx_crb_mask; 754 755 uint8_t revision_id; 756 uint32_t fw_heartbeat_counter; 757 758 struct isp_operations *isp_ops; 759 struct ql82xx_hw_data hw; 760 761 uint32_t nx_dev_init_timeout; 762 uint32_t nx_reset_timeout; 763 void *fw_dump; 764 uint32_t fw_dump_size; 765 uint32_t fw_dump_capture_mask; 766 void *fw_dump_tmplt_hdr; 767 uint32_t fw_dump_tmplt_size; 768 uint32_t fw_dump_skip_size; 769 770 struct completion mbx_intr_comp; 771 772 struct ipaddress_config ip_config; 773 struct iscsi_iface *iface_ipv4; 774 struct iscsi_iface *iface_ipv6_0; 775 struct iscsi_iface *iface_ipv6_1; 776 777 /* --- From About Firmware --- */ 778 struct about_fw_info fw_info; 779 uint32_t fw_uptime_secs; /* seconds elapsed since fw bootup */ 780 uint32_t fw_uptime_msecs; /* milliseconds beyond elapsed seconds */ 781 uint16_t def_timeout; /* Default login timeout */ 782 783 uint32_t flash_state; 784 #define QLFLASH_WAITING 0 785 #define QLFLASH_READING 1 786 #define QLFLASH_WRITING 2 787 struct dma_pool *chap_dma_pool; 788 uint8_t *chap_list; /* CHAP table cache */ 789 struct mutex chap_sem; 790 791 #define CHAP_DMA_BLOCK_SIZE 512 792 struct workqueue_struct *task_wq; 793 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG]; 794 #define SYSFS_FLAG_FW_SEL_BOOT 2 795 struct iscsi_boot_kset *boot_kset; 796 struct ql4_boot_tgt_info boot_tgt; 797 uint16_t phy_port_num; 798 uint16_t phy_port_cnt; 799 uint16_t iscsi_pci_func_cnt; 800 uint8_t model_name[16]; 801 struct completion disable_acb_comp; 802 struct dma_pool *fw_ddb_dma_pool; 803 #define DDB_DMA_BLOCK_SIZE 512 804 uint16_t pri_ddb_idx; 805 uint16_t sec_ddb_idx; 806 int is_reset; 807 uint16_t temperature; 808 809 /* event work list */ 810 struct list_head work_list; 811 spinlock_t work_lock; 812 813 /* mbox iocb */ 814 #define MAX_MRB 128 815 struct mrb *active_mrb_array[MAX_MRB]; 816 uint32_t mrb_index; 817 818 uint32_t *reg_tbl; 819 struct qla4_83xx_reset_template reset_tmplt; 820 struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address 821 for ISP8324 and 822 and ISP8042 */ 823 uint32_t pf_bit; 824 struct qla4_83xx_idc_information idc_info; 825 struct addr_ctrl_blk *saved_acb; 826 int notify_idc_comp; 827 int notify_link_up_comp; 828 int idc_extend_tmo; 829 struct completion idc_comp; 830 struct completion link_up_comp; 831 }; 832 833 struct ql4_task_data { 834 struct scsi_qla_host *ha; 835 uint8_t iocb_req_cnt; 836 dma_addr_t data_dma; 837 void *req_buffer; 838 dma_addr_t req_dma; 839 uint32_t req_len; 840 void *resp_buffer; 841 dma_addr_t resp_dma; 842 uint32_t resp_len; 843 struct iscsi_task *task; 844 struct passthru_status sts; 845 struct work_struct task_work; 846 }; 847 848 struct qla_endpoint { 849 struct Scsi_Host *host; 850 struct sockaddr_storage dst_addr; 851 }; 852 853 struct qla_conn { 854 struct qla_endpoint *qla_ep; 855 }; 856 857 static inline int is_ipv4_enabled(struct scsi_qla_host *ha) 858 { 859 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0); 860 } 861 862 static inline int is_ipv6_enabled(struct scsi_qla_host *ha) 863 { 864 return ((ha->ip_config.ipv6_options & 865 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0); 866 } 867 868 static inline int is_qla4010(struct scsi_qla_host *ha) 869 { 870 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010; 871 } 872 873 static inline int is_qla4022(struct scsi_qla_host *ha) 874 { 875 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; 876 } 877 878 static inline int is_qla4032(struct scsi_qla_host *ha) 879 { 880 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032; 881 } 882 883 static inline int is_qla40XX(struct scsi_qla_host *ha) 884 { 885 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha); 886 } 887 888 static inline int is_qla8022(struct scsi_qla_host *ha) 889 { 890 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 891 } 892 893 static inline int is_qla8032(struct scsi_qla_host *ha) 894 { 895 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324; 896 } 897 898 static inline int is_qla8042(struct scsi_qla_host *ha) 899 { 900 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042; 901 } 902 903 static inline int is_qla80XX(struct scsi_qla_host *ha) 904 { 905 return is_qla8022(ha) || is_qla8032(ha) || is_qla8042(ha); 906 } 907 908 static inline int is_aer_supported(struct scsi_qla_host *ha) 909 { 910 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) || 911 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324) || 912 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042)); 913 } 914 915 static inline int adapter_up(struct scsi_qla_host *ha) 916 { 917 return (test_bit(AF_ONLINE, &ha->flags) != 0) && 918 (test_bit(AF_LINK_UP, &ha->flags) != 0) && 919 (!test_bit(AF_LOOPBACK, &ha->flags)); 920 } 921 922 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost) 923 { 924 return (struct scsi_qla_host *)iscsi_host_priv(shost); 925 } 926 927 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) 928 { 929 return (is_qla4010(ha) ? 930 &ha->reg->u1.isp4010.nvram : 931 &ha->reg->u1.isp4022.semaphore); 932 } 933 934 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) 935 { 936 return (is_qla4010(ha) ? 937 &ha->reg->u1.isp4010.nvram : 938 &ha->reg->u1.isp4022.nvram); 939 } 940 941 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) 942 { 943 return (is_qla4010(ha) ? 944 &ha->reg->u2.isp4010.ext_hw_conf : 945 &ha->reg->u2.isp4022.p0.ext_hw_conf); 946 } 947 948 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) 949 { 950 return (is_qla4010(ha) ? 951 &ha->reg->u2.isp4010.port_status : 952 &ha->reg->u2.isp4022.p0.port_status); 953 } 954 955 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) 956 { 957 return (is_qla4010(ha) ? 958 &ha->reg->u2.isp4010.port_ctrl : 959 &ha->reg->u2.isp4022.p0.port_ctrl); 960 } 961 962 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) 963 { 964 return (is_qla4010(ha) ? 965 &ha->reg->u2.isp4010.port_err_status : 966 &ha->reg->u2.isp4022.p0.port_err_status); 967 } 968 969 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) 970 { 971 return (is_qla4010(ha) ? 972 &ha->reg->u2.isp4010.gp_out : 973 &ha->reg->u2.isp4022.p0.gp_out); 974 } 975 976 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) 977 { 978 return (is_qla4010(ha) ? 979 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 : 980 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2); 981 } 982 983 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 984 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask); 985 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 986 987 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) 988 { 989 if (is_qla4010(a)) 990 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, 991 QL4010_FLASH_SEM_BITS); 992 else 993 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, 994 (QL4022_RESOURCE_BITS_BASE_CODE | 995 (a->mac_index)) << 13); 996 } 997 998 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) 999 { 1000 if (is_qla4010(a)) 1001 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); 1002 else 1003 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); 1004 } 1005 1006 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) 1007 { 1008 if (is_qla4010(a)) 1009 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, 1010 QL4010_NVRAM_SEM_BITS); 1011 else 1012 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, 1013 (QL4022_RESOURCE_BITS_BASE_CODE | 1014 (a->mac_index)) << 10); 1015 } 1016 1017 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) 1018 { 1019 if (is_qla4010(a)) 1020 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); 1021 else 1022 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); 1023 } 1024 1025 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) 1026 { 1027 if (is_qla4010(a)) 1028 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, 1029 QL4010_DRVR_SEM_BITS); 1030 else 1031 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, 1032 (QL4022_RESOURCE_BITS_BASE_CODE | 1033 (a->mac_index)) << 1); 1034 } 1035 1036 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) 1037 { 1038 if (is_qla4010(a)) 1039 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); 1040 else 1041 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); 1042 } 1043 1044 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha) 1045 { 1046 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) || 1047 test_bit(DPC_RESET_HA, &ha->dpc_flags) || 1048 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) || 1049 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) || 1050 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) || 1051 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags); 1052 1053 } 1054 1055 static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha, 1056 const uint32_t crb_reg) 1057 { 1058 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]); 1059 } 1060 1061 static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha, 1062 const uint32_t crb_reg, 1063 const uint32_t value) 1064 { 1065 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value); 1066 } 1067 1068 /*---------------------------------------------------------------------------*/ 1069 1070 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */ 1071 1072 #define INIT_ADAPTER 0 1073 #define RESET_ADAPTER 1 1074 1075 #define PRESERVE_DDB_LIST 0 1076 #define REBUILD_DDB_LIST 1 1077 1078 /* Defines for process_aen() */ 1079 #define PROCESS_ALL_AENS 0 1080 #define FLUSH_DDB_CHANGED_AENS 1 1081 1082 /* Defines for udev events */ 1083 #define QL4_UEVENT_CODE_FW_DUMP 0 1084 1085 #endif /*_QLA4XXX_H */ 1086