1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2012 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8 #ifndef __QL4_DEF_H 9 #define __QL4_DEF_H 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/module.h> 15 #include <linux/list.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/sched.h> 19 #include <linux/slab.h> 20 #include <linux/dmapool.h> 21 #include <linux/mempool.h> 22 #include <linux/spinlock.h> 23 #include <linux/workqueue.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/mutex.h> 27 #include <linux/aer.h> 28 #include <linux/bsg-lib.h> 29 30 #include <net/tcp.h> 31 #include <scsi/scsi.h> 32 #include <scsi/scsi_host.h> 33 #include <scsi/scsi_device.h> 34 #include <scsi/scsi_cmnd.h> 35 #include <scsi/scsi_transport.h> 36 #include <scsi/scsi_transport_iscsi.h> 37 #include <scsi/scsi_bsg_iscsi.h> 38 #include <scsi/scsi_netlink.h> 39 #include <scsi/libiscsi.h> 40 41 #include "ql4_dbg.h" 42 #include "ql4_nx.h" 43 #include "ql4_fw.h" 44 #include "ql4_nvram.h" 45 #include "ql4_83xx.h" 46 47 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010 48 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010 49 #endif 50 51 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 52 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 53 #endif 54 55 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032 56 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032 57 #endif 58 59 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022 60 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022 61 #endif 62 63 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324 64 #define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032 65 #endif 66 67 #define ISP4XXX_PCI_FN_1 0x1 68 #define ISP4XXX_PCI_FN_2 0x3 69 70 #define QLA_SUCCESS 0 71 #define QLA_ERROR 1 72 73 /* 74 * Data bit definitions 75 */ 76 #define BIT_0 0x1 77 #define BIT_1 0x2 78 #define BIT_2 0x4 79 #define BIT_3 0x8 80 #define BIT_4 0x10 81 #define BIT_5 0x20 82 #define BIT_6 0x40 83 #define BIT_7 0x80 84 #define BIT_8 0x100 85 #define BIT_9 0x200 86 #define BIT_10 0x400 87 #define BIT_11 0x800 88 #define BIT_12 0x1000 89 #define BIT_13 0x2000 90 #define BIT_14 0x4000 91 #define BIT_15 0x8000 92 #define BIT_16 0x10000 93 #define BIT_17 0x20000 94 #define BIT_18 0x40000 95 #define BIT_19 0x80000 96 #define BIT_20 0x100000 97 #define BIT_21 0x200000 98 #define BIT_22 0x400000 99 #define BIT_23 0x800000 100 #define BIT_24 0x1000000 101 #define BIT_25 0x2000000 102 #define BIT_26 0x4000000 103 #define BIT_27 0x8000000 104 #define BIT_28 0x10000000 105 #define BIT_29 0x20000000 106 #define BIT_30 0x40000000 107 #define BIT_31 0x80000000 108 109 /** 110 * Macros to help code, maintain, etc. 111 **/ 112 #define ql4_printk(level, ha, format, arg...) \ 113 dev_printk(level , &((ha)->pdev->dev) , format , ## arg) 114 115 116 /* 117 * Host adapter default definitions 118 ***********************************/ 119 #define MAX_HBAS 16 120 #define MAX_BUSES 1 121 #define MAX_TARGETS MAX_DEV_DB_ENTRIES 122 #define MAX_LUNS 0xffff 123 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES 124 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES 125 #define MAX_PDU_ENTRIES 32 126 #define INVALID_ENTRY 0xFFFF 127 #define MAX_CMDS_TO_RISC 1024 128 #define MAX_SRBS MAX_CMDS_TO_RISC 129 #define MBOX_AEN_REG_COUNT 8 130 #define MAX_INIT_RETRIES 5 131 132 /* 133 * Buffer sizes 134 */ 135 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC 136 #define RESPONSE_QUEUE_DEPTH 64 137 #define QUEUE_SIZE 64 138 #define DMA_BUFFER_SIZE 512 139 140 /* 141 * Misc 142 */ 143 #define MAC_ADDR_LEN 6 /* in bytes */ 144 #define IP_ADDR_LEN 4 /* in bytes */ 145 #define IPv6_ADDR_LEN 16 /* IPv6 address size */ 146 #define DRIVER_NAME "qla4xxx" 147 148 #define MAX_LINKED_CMDS_PER_LUN 3 149 #define MAX_REQS_SERVICED_PER_INTR 1 150 151 #define ISCSI_IPADDR_SIZE 4 /* IP address size */ 152 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */ 153 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */ 154 155 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */ 156 /* recovery timeout */ 157 158 #define LSDW(x) ((u32)((u64)(x))) 159 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16)) 160 161 /* 162 * Retry & Timeout Values 163 */ 164 #define MBOX_TOV 60 165 #define SOFT_RESET_TOV 30 166 #define RESET_INTR_TOV 3 167 #define SEMAPHORE_TOV 10 168 #define ADAPTER_INIT_TOV 30 169 #define ADAPTER_RESET_TOV 180 170 #define EXTEND_CMD_TOV 60 171 #define WAIT_CMD_TOV 30 172 #define EH_WAIT_CMD_TOV 120 173 #define FIRMWARE_UP_TOV 60 174 #define RESET_FIRMWARE_TOV 30 175 #define LOGOUT_TOV 10 176 #define IOCB_TOV_MARGIN 10 177 #define RELOGIN_TOV 18 178 #define ISNS_DEREG_TOV 5 179 #define HBA_ONLINE_TOV 30 180 #define DISABLE_ACB_TOV 30 181 #define IP_CONFIG_TOV 30 182 #define LOGIN_TOV 12 183 184 #define MAX_RESET_HA_RETRIES 2 185 #define FW_ALIVE_WAIT_TOV 3 186 187 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 188 189 /* 190 * SCSI Request Block structure (srb) that is placed 191 * on cmd->SCp location of every I/O [We have 22 bytes available] 192 */ 193 struct srb { 194 struct list_head list; /* (8) */ 195 struct scsi_qla_host *ha; /* HA the SP is queued on */ 196 struct ddb_entry *ddb; 197 uint16_t flags; /* (1) Status flags. */ 198 199 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */ 200 #define SRB_GOT_SENSE BIT_4 /* sense data received. */ 201 uint8_t state; /* (1) Status flags. */ 202 203 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */ 204 #define SRB_FREE_STATE 1 205 #define SRB_ACTIVE_STATE 3 206 #define SRB_ACTIVE_TIMEOUT_STATE 4 207 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */ 208 209 struct scsi_cmnd *cmd; /* (4) SCSI command block */ 210 dma_addr_t dma_handle; /* (4) for unmap of single transfers */ 211 struct kref srb_ref; /* reference count for this srb */ 212 uint8_t err_id; /* error id */ 213 #define SRB_ERR_PORT 1 /* Request failed because "port down" */ 214 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */ 215 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */ 216 #define SRB_ERR_OTHER 4 217 218 uint16_t reserved; 219 uint16_t iocb_tov; 220 uint16_t iocb_cnt; /* Number of used iocbs */ 221 uint16_t cc_stat; 222 223 /* Used for extended sense / status continuation */ 224 uint8_t *req_sense_ptr; 225 uint16_t req_sense_len; 226 uint16_t reserved2; 227 }; 228 229 /* Mailbox request block structure */ 230 struct mrb { 231 struct scsi_qla_host *ha; 232 struct mbox_cmd_iocb *mbox; 233 uint32_t mbox_cmd; 234 uint16_t iocb_cnt; /* Number of used iocbs */ 235 uint32_t pid; 236 }; 237 238 /* 239 * Asynchronous Event Queue structure 240 */ 241 struct aen { 242 uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; 243 }; 244 245 struct ql4_aen_log { 246 int count; 247 struct aen entry[MAX_AEN_ENTRIES]; 248 }; 249 250 /* 251 * Device Database (DDB) structure 252 */ 253 struct ddb_entry { 254 struct scsi_qla_host *ha; 255 struct iscsi_cls_session *sess; 256 struct iscsi_cls_conn *conn; 257 258 uint16_t fw_ddb_index; /* DDB firmware index */ 259 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */ 260 uint16_t ddb_type; 261 #define FLASH_DDB 0x01 262 263 struct dev_db_entry fw_ddb_entry; 264 int (*unblock_sess)(struct iscsi_cls_session *cls_session); 265 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index, 266 struct ddb_entry *ddb_entry, uint32_t state); 267 268 /* Driver Re-login */ 269 unsigned long flags; /* DDB Flags */ 270 uint16_t default_relogin_timeout; /* Max time to wait for 271 * relogin to complete */ 272 atomic_t retry_relogin_timer; /* Min Time between relogins 273 * (4000 only) */ 274 atomic_t relogin_timer; /* Max Time to wait for 275 * relogin to complete */ 276 atomic_t relogin_retry_count; /* Num of times relogin has been 277 * retried */ 278 uint32_t default_time2wait; /* Default Min time between 279 * relogins (+aens) */ 280 uint16_t chap_tbl_idx; 281 }; 282 283 struct qla_ddb_index { 284 struct list_head list; 285 uint16_t fw_ddb_idx; 286 struct dev_db_entry fw_ddb; 287 uint8_t flash_isid[6]; 288 }; 289 290 #define DDB_IPADDR_LEN 64 291 292 struct ql4_tuple_ddb { 293 int port; 294 int tpgt; 295 char ip_addr[DDB_IPADDR_LEN]; 296 char iscsi_name[ISCSI_NAME_SIZE]; 297 uint16_t options; 298 #define DDB_OPT_IPV6 0x0e0e 299 #define DDB_OPT_IPV4 0x0f0f 300 uint8_t isid[6]; 301 }; 302 303 /* 304 * DDB states. 305 */ 306 #define DDB_STATE_DEAD 0 /* We can no longer talk to 307 * this device */ 308 #define DDB_STATE_ONLINE 1 /* Device ready to accept 309 * commands */ 310 #define DDB_STATE_MISSING 2 /* Device logged off, trying 311 * to re-login */ 312 313 /* 314 * DDB flags. 315 */ 316 #define DF_RELOGIN 0 /* Relogin to device */ 317 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */ 318 #define DF_FO_MASKED 3 319 320 enum qla4_work_type { 321 QLA4_EVENT_AEN, 322 QLA4_EVENT_PING_STATUS, 323 }; 324 325 struct qla4_work_evt { 326 struct list_head list; 327 enum qla4_work_type type; 328 union { 329 struct { 330 enum iscsi_host_event_code code; 331 uint32_t data_size; 332 uint8_t data[0]; 333 } aen; 334 struct { 335 uint32_t status; 336 uint32_t pid; 337 uint32_t data_size; 338 uint8_t data[0]; 339 } ping; 340 } u; 341 }; 342 343 struct ql82xx_hw_data { 344 /* Offsets for flash/nvram access (set to ~0 if not used). */ 345 uint32_t flash_conf_off; 346 uint32_t flash_data_off; 347 348 uint32_t fdt_wrt_disable; 349 uint32_t fdt_erase_cmd; 350 uint32_t fdt_block_size; 351 uint32_t fdt_unprotect_sec_cmd; 352 uint32_t fdt_protect_sec_cmd; 353 354 uint32_t flt_region_flt; 355 uint32_t flt_region_fdt; 356 uint32_t flt_region_boot; 357 uint32_t flt_region_bootload; 358 uint32_t flt_region_fw; 359 360 uint32_t flt_iscsi_param; 361 uint32_t flt_region_chap; 362 uint32_t flt_chap_size; 363 }; 364 365 struct qla4_8xxx_legacy_intr_set { 366 uint32_t int_vec_bit; 367 uint32_t tgt_status_reg; 368 uint32_t tgt_mask_reg; 369 uint32_t pci_int_reg; 370 }; 371 372 /* MSI-X Support */ 373 374 #define QLA_MSIX_DEFAULT 0x00 375 #define QLA_MSIX_RSP_Q 0x01 376 377 #define QLA_MSIX_ENTRIES 2 378 #define QLA_MIDX_DEFAULT 0 379 #define QLA_MIDX_RSP_Q 1 380 381 struct ql4_msix_entry { 382 int have_irq; 383 uint16_t msix_vector; 384 uint16_t msix_entry; 385 }; 386 387 /* 388 * ISP Operations 389 */ 390 struct isp_operations { 391 int (*iospace_config) (struct scsi_qla_host *ha); 392 void (*pci_config) (struct scsi_qla_host *); 393 void (*disable_intrs) (struct scsi_qla_host *); 394 void (*enable_intrs) (struct scsi_qla_host *); 395 int (*start_firmware) (struct scsi_qla_host *); 396 int (*restart_firmware) (struct scsi_qla_host *); 397 irqreturn_t (*intr_handler) (int , void *); 398 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t); 399 int (*need_reset) (struct scsi_qla_host *); 400 int (*reset_chip) (struct scsi_qla_host *); 401 int (*reset_firmware) (struct scsi_qla_host *); 402 void (*queue_iocb) (struct scsi_qla_host *); 403 void (*complete_iocb) (struct scsi_qla_host *); 404 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *); 405 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *); 406 int (*get_sys_info) (struct scsi_qla_host *); 407 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong); 408 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t); 409 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *); 410 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t); 411 int (*idc_lock) (struct scsi_qla_host *); 412 void (*idc_unlock) (struct scsi_qla_host *); 413 void (*rom_lock_recovery) (struct scsi_qla_host *); 414 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int); 415 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int); 416 }; 417 418 struct ql4_mdump_size_table { 419 uint32_t size; 420 uint32_t size_cmask_02; 421 uint32_t size_cmask_04; 422 uint32_t size_cmask_08; 423 uint32_t size_cmask_10; 424 uint32_t size_cmask_FF; 425 uint32_t version; 426 }; 427 428 /*qla4xxx ipaddress configuration details */ 429 struct ipaddress_config { 430 uint16_t ipv4_options; 431 uint16_t tcp_options; 432 uint16_t ipv4_vlan_tag; 433 uint8_t ipv4_addr_state; 434 uint8_t ip_address[IP_ADDR_LEN]; 435 uint8_t subnet_mask[IP_ADDR_LEN]; 436 uint8_t gateway[IP_ADDR_LEN]; 437 uint32_t ipv6_options; 438 uint32_t ipv6_addl_options; 439 uint8_t ipv6_link_local_state; 440 uint8_t ipv6_addr0_state; 441 uint8_t ipv6_addr1_state; 442 uint8_t ipv6_default_router_state; 443 uint16_t ipv6_vlan_tag; 444 struct in6_addr ipv6_link_local_addr; 445 struct in6_addr ipv6_addr0; 446 struct in6_addr ipv6_addr1; 447 struct in6_addr ipv6_default_router_addr; 448 uint16_t eth_mtu_size; 449 uint16_t ipv4_port; 450 uint16_t ipv6_port; 451 }; 452 453 #define QL4_CHAP_MAX_NAME_LEN 256 454 #define QL4_CHAP_MAX_SECRET_LEN 100 455 #define LOCAL_CHAP 0 456 #define BIDI_CHAP 1 457 458 struct ql4_chap_format { 459 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN]; 460 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN]; 461 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN]; 462 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN]; 463 u16 intr_chap_name_length; 464 u16 intr_secret_length; 465 u16 target_chap_name_length; 466 u16 target_secret_length; 467 }; 468 469 struct ip_address_format { 470 u8 ip_type; 471 u8 ip_address[16]; 472 }; 473 474 struct ql4_conn_info { 475 u16 dest_port; 476 struct ip_address_format dest_ipaddr; 477 struct ql4_chap_format chap; 478 }; 479 480 struct ql4_boot_session_info { 481 u8 target_name[224]; 482 struct ql4_conn_info conn_list[1]; 483 }; 484 485 struct ql4_boot_tgt_info { 486 struct ql4_boot_session_info boot_pri_sess; 487 struct ql4_boot_session_info boot_sec_sess; 488 }; 489 490 /* 491 * Linux Host Adapter structure 492 */ 493 struct scsi_qla_host { 494 /* Linux adapter configuration data */ 495 unsigned long flags; 496 497 #define AF_ONLINE 0 /* 0x00000001 */ 498 #define AF_INIT_DONE 1 /* 0x00000002 */ 499 #define AF_MBOX_COMMAND 2 /* 0x00000004 */ 500 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */ 501 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */ 502 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ 503 #define AF_LINK_UP 8 /* 0x00000100 */ 504 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */ 505 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */ 506 #define AF_HA_REMOVAL 12 /* 0x00001000 */ 507 #define AF_INTx_ENABLED 15 /* 0x00008000 */ 508 #define AF_MSI_ENABLED 16 /* 0x00010000 */ 509 #define AF_MSIX_ENABLED 17 /* 0x00020000 */ 510 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */ 511 #define AF_FW_RECOVERY 19 /* 0x00080000 */ 512 #define AF_EEH_BUSY 20 /* 0x00100000 */ 513 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */ 514 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */ 515 #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */ 516 #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */ 517 #define AF_82XX_DUMP_READING 26 /* 0x04000000 */ 518 #define AF_83XX_NO_FW_DUMP 27 /* 0x08000000 */ 519 520 unsigned long dpc_flags; 521 522 #define DPC_RESET_HA 1 /* 0x00000002 */ 523 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */ 524 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */ 525 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */ 526 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */ 527 #define DPC_ISNS_RESTART 7 /* 0x00000080 */ 528 #define DPC_AEN 9 /* 0x00000200 */ 529 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */ 530 #define DPC_LINK_CHANGED 18 /* 0x00040000 */ 531 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */ 532 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/ 533 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/ 534 #define DPC_POST_IDC_ACK 23 /* 0x00200000 */ 535 536 struct Scsi_Host *host; /* pointer to host data */ 537 uint32_t tot_ddbs; 538 539 uint16_t iocb_cnt; 540 541 /* SRB cache. */ 542 #define SRB_MIN_REQ 128 543 mempool_t *srb_mempool; 544 545 /* pci information */ 546 struct pci_dev *pdev; 547 548 struct isp_reg __iomem *reg; /* Base I/O address */ 549 unsigned long pio_address; 550 unsigned long pio_length; 551 #define MIN_IOBASE_LEN 0x100 552 553 uint16_t req_q_count; 554 555 unsigned long host_no; 556 557 /* NVRAM registers */ 558 struct eeprom_data *nvram; 559 spinlock_t hardware_lock ____cacheline_aligned; 560 uint32_t eeprom_cmd_data; 561 562 /* Counters for general statistics */ 563 uint64_t isr_count; 564 uint64_t adapter_error_count; 565 uint64_t device_error_count; 566 uint64_t total_io_count; 567 uint64_t total_mbytes_xferred; 568 uint64_t link_failure_count; 569 uint64_t invalid_crc_count; 570 uint32_t bytes_xfered; 571 uint32_t spurious_int_count; 572 uint32_t aborted_io_count; 573 uint32_t io_timeout_count; 574 uint32_t mailbox_timeout_count; 575 uint32_t seconds_since_last_intr; 576 uint32_t seconds_since_last_heartbeat; 577 uint32_t mac_index; 578 579 /* Info Needed for Management App */ 580 /* --- From GetFwVersion --- */ 581 uint32_t firmware_version[2]; 582 uint32_t patch_number; 583 uint32_t build_number; 584 uint32_t board_id; 585 586 /* --- From Init_FW --- */ 587 /* init_cb_t *init_cb; */ 588 uint16_t firmware_options; 589 uint8_t alias[32]; 590 uint8_t name_string[256]; 591 uint8_t heartbeat_interval; 592 593 /* --- From FlashSysInfo --- */ 594 uint8_t my_mac[MAC_ADDR_LEN]; 595 uint8_t serial_number[16]; 596 uint16_t port_num; 597 /* --- From GetFwState --- */ 598 uint32_t firmware_state; 599 uint32_t addl_fw_state; 600 601 /* Linux kernel thread */ 602 struct workqueue_struct *dpc_thread; 603 struct work_struct dpc_work; 604 605 /* Linux timer thread */ 606 struct timer_list timer; 607 uint32_t timer_active; 608 609 /* Recovery Timers */ 610 atomic_t check_relogin_timeouts; 611 uint32_t retry_reset_ha_cnt; 612 uint32_t isp_reset_timer; /* reset test timer */ 613 uint32_t nic_reset_timer; /* simulated nic reset test timer */ 614 int eh_start; 615 struct list_head free_srb_q; 616 uint16_t free_srb_q_count; 617 uint16_t num_srbs_allocated; 618 619 /* DMA Memory Block */ 620 void *queues; 621 dma_addr_t queues_dma; 622 unsigned long queues_len; 623 624 #define MEM_ALIGN_VALUE \ 625 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \ 626 sizeof(struct queue_entry)) 627 /* request and response queue variables */ 628 dma_addr_t request_dma; 629 struct queue_entry *request_ring; 630 struct queue_entry *request_ptr; 631 dma_addr_t response_dma; 632 struct queue_entry *response_ring; 633 struct queue_entry *response_ptr; 634 dma_addr_t shadow_regs_dma; 635 struct shadow_regs *shadow_regs; 636 uint16_t request_in; /* Current indexes. */ 637 uint16_t request_out; 638 uint16_t response_in; 639 uint16_t response_out; 640 641 /* aen queue variables */ 642 uint16_t aen_q_count; /* Number of available aen_q entries */ 643 uint16_t aen_in; /* Current indexes */ 644 uint16_t aen_out; 645 struct aen aen_q[MAX_AEN_ENTRIES]; 646 647 struct ql4_aen_log aen_log;/* tracks all aens */ 648 649 /* This mutex protects several threads to do mailbox commands 650 * concurrently. 651 */ 652 struct mutex mbox_sem; 653 654 /* temporary mailbox status registers */ 655 volatile uint8_t mbox_status_count; 656 volatile uint32_t mbox_status[MBOX_REG_COUNT]; 657 658 /* FW ddb index map */ 659 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES]; 660 661 /* Saved srb for status continuation entry processing */ 662 struct srb *status_srb; 663 664 uint8_t acb_version; 665 666 /* qla82xx specific fields */ 667 struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */ 668 unsigned long nx_pcibase; /* Base I/O address */ 669 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */ 670 unsigned long nx_db_wr_ptr; /* Door bell write pointer */ 671 unsigned long first_page_group_start; 672 unsigned long first_page_group_end; 673 674 uint32_t crb_win; 675 uint32_t curr_window; 676 uint32_t ddr_mn_window; 677 unsigned long mn_win_crb; 678 unsigned long ms_win_crb; 679 int qdr_sn_window; 680 rwlock_t hw_lock; 681 uint16_t func_num; 682 int link_width; 683 684 struct qla4_8xxx_legacy_intr_set nx_legacy_intr; 685 u32 nx_crb_mask; 686 687 uint8_t revision_id; 688 uint32_t fw_heartbeat_counter; 689 690 struct isp_operations *isp_ops; 691 struct ql82xx_hw_data hw; 692 693 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES]; 694 695 uint32_t nx_dev_init_timeout; 696 uint32_t nx_reset_timeout; 697 void *fw_dump; 698 uint32_t fw_dump_size; 699 uint32_t fw_dump_capture_mask; 700 void *fw_dump_tmplt_hdr; 701 uint32_t fw_dump_tmplt_size; 702 703 struct completion mbx_intr_comp; 704 705 struct ipaddress_config ip_config; 706 struct iscsi_iface *iface_ipv4; 707 struct iscsi_iface *iface_ipv6_0; 708 struct iscsi_iface *iface_ipv6_1; 709 710 /* --- From About Firmware --- */ 711 uint16_t iscsi_major; 712 uint16_t iscsi_minor; 713 uint16_t bootload_major; 714 uint16_t bootload_minor; 715 uint16_t bootload_patch; 716 uint16_t bootload_build; 717 uint16_t def_timeout; /* Default login timeout */ 718 719 uint32_t flash_state; 720 #define QLFLASH_WAITING 0 721 #define QLFLASH_READING 1 722 #define QLFLASH_WRITING 2 723 struct dma_pool *chap_dma_pool; 724 uint8_t *chap_list; /* CHAP table cache */ 725 struct mutex chap_sem; 726 727 #define CHAP_DMA_BLOCK_SIZE 512 728 struct workqueue_struct *task_wq; 729 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG]; 730 #define SYSFS_FLAG_FW_SEL_BOOT 2 731 struct iscsi_boot_kset *boot_kset; 732 struct ql4_boot_tgt_info boot_tgt; 733 uint16_t phy_port_num; 734 uint16_t phy_port_cnt; 735 uint16_t iscsi_pci_func_cnt; 736 uint8_t model_name[16]; 737 struct completion disable_acb_comp; 738 struct dma_pool *fw_ddb_dma_pool; 739 #define DDB_DMA_BLOCK_SIZE 512 740 uint16_t pri_ddb_idx; 741 uint16_t sec_ddb_idx; 742 int is_reset; 743 uint16_t temperature; 744 745 /* event work list */ 746 struct list_head work_list; 747 spinlock_t work_lock; 748 749 /* mbox iocb */ 750 #define MAX_MRB 128 751 struct mrb *active_mrb_array[MAX_MRB]; 752 uint32_t mrb_index; 753 754 uint32_t *reg_tbl; 755 struct qla4_83xx_reset_template reset_tmplt; 756 struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address 757 for ISP8324 */ 758 uint32_t pf_bit; 759 struct qla4_83xx_idc_information idc_info; 760 }; 761 762 struct ql4_task_data { 763 struct scsi_qla_host *ha; 764 uint8_t iocb_req_cnt; 765 dma_addr_t data_dma; 766 void *req_buffer; 767 dma_addr_t req_dma; 768 uint32_t req_len; 769 void *resp_buffer; 770 dma_addr_t resp_dma; 771 uint32_t resp_len; 772 struct iscsi_task *task; 773 struct passthru_status sts; 774 struct work_struct task_work; 775 }; 776 777 struct qla_endpoint { 778 struct Scsi_Host *host; 779 struct sockaddr_storage dst_addr; 780 }; 781 782 struct qla_conn { 783 struct qla_endpoint *qla_ep; 784 }; 785 786 static inline int is_ipv4_enabled(struct scsi_qla_host *ha) 787 { 788 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0); 789 } 790 791 static inline int is_ipv6_enabled(struct scsi_qla_host *ha) 792 { 793 return ((ha->ip_config.ipv6_options & 794 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0); 795 } 796 797 static inline int is_qla4010(struct scsi_qla_host *ha) 798 { 799 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010; 800 } 801 802 static inline int is_qla4022(struct scsi_qla_host *ha) 803 { 804 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; 805 } 806 807 static inline int is_qla4032(struct scsi_qla_host *ha) 808 { 809 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032; 810 } 811 812 static inline int is_qla40XX(struct scsi_qla_host *ha) 813 { 814 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha); 815 } 816 817 static inline int is_qla8022(struct scsi_qla_host *ha) 818 { 819 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 820 } 821 822 static inline int is_qla8032(struct scsi_qla_host *ha) 823 { 824 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324; 825 } 826 827 static inline int is_qla80XX(struct scsi_qla_host *ha) 828 { 829 return is_qla8022(ha) || is_qla8032(ha); 830 } 831 832 static inline int is_aer_supported(struct scsi_qla_host *ha) 833 { 834 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) || 835 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324)); 836 } 837 838 static inline int adapter_up(struct scsi_qla_host *ha) 839 { 840 return (test_bit(AF_ONLINE, &ha->flags) != 0) && 841 (test_bit(AF_LINK_UP, &ha->flags) != 0); 842 } 843 844 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost) 845 { 846 return (struct scsi_qla_host *)iscsi_host_priv(shost); 847 } 848 849 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) 850 { 851 return (is_qla4010(ha) ? 852 &ha->reg->u1.isp4010.nvram : 853 &ha->reg->u1.isp4022.semaphore); 854 } 855 856 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) 857 { 858 return (is_qla4010(ha) ? 859 &ha->reg->u1.isp4010.nvram : 860 &ha->reg->u1.isp4022.nvram); 861 } 862 863 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) 864 { 865 return (is_qla4010(ha) ? 866 &ha->reg->u2.isp4010.ext_hw_conf : 867 &ha->reg->u2.isp4022.p0.ext_hw_conf); 868 } 869 870 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) 871 { 872 return (is_qla4010(ha) ? 873 &ha->reg->u2.isp4010.port_status : 874 &ha->reg->u2.isp4022.p0.port_status); 875 } 876 877 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) 878 { 879 return (is_qla4010(ha) ? 880 &ha->reg->u2.isp4010.port_ctrl : 881 &ha->reg->u2.isp4022.p0.port_ctrl); 882 } 883 884 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) 885 { 886 return (is_qla4010(ha) ? 887 &ha->reg->u2.isp4010.port_err_status : 888 &ha->reg->u2.isp4022.p0.port_err_status); 889 } 890 891 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) 892 { 893 return (is_qla4010(ha) ? 894 &ha->reg->u2.isp4010.gp_out : 895 &ha->reg->u2.isp4022.p0.gp_out); 896 } 897 898 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) 899 { 900 return (is_qla4010(ha) ? 901 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 : 902 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2); 903 } 904 905 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 906 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask); 907 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 908 909 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) 910 { 911 if (is_qla4010(a)) 912 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, 913 QL4010_FLASH_SEM_BITS); 914 else 915 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, 916 (QL4022_RESOURCE_BITS_BASE_CODE | 917 (a->mac_index)) << 13); 918 } 919 920 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) 921 { 922 if (is_qla4010(a)) 923 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); 924 else 925 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); 926 } 927 928 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) 929 { 930 if (is_qla4010(a)) 931 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, 932 QL4010_NVRAM_SEM_BITS); 933 else 934 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, 935 (QL4022_RESOURCE_BITS_BASE_CODE | 936 (a->mac_index)) << 10); 937 } 938 939 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) 940 { 941 if (is_qla4010(a)) 942 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); 943 else 944 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); 945 } 946 947 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) 948 { 949 if (is_qla4010(a)) 950 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, 951 QL4010_DRVR_SEM_BITS); 952 else 953 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, 954 (QL4022_RESOURCE_BITS_BASE_CODE | 955 (a->mac_index)) << 1); 956 } 957 958 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) 959 { 960 if (is_qla4010(a)) 961 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); 962 else 963 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); 964 } 965 966 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha) 967 { 968 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) || 969 test_bit(DPC_RESET_HA, &ha->dpc_flags) || 970 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) || 971 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) || 972 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) || 973 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags); 974 975 } 976 977 static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha, 978 const uint32_t crb_reg) 979 { 980 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]); 981 } 982 983 static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha, 984 const uint32_t crb_reg, 985 const uint32_t value) 986 { 987 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value); 988 } 989 990 /*---------------------------------------------------------------------------*/ 991 992 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */ 993 994 #define INIT_ADAPTER 0 995 #define RESET_ADAPTER 1 996 997 #define PRESERVE_DDB_LIST 0 998 #define REBUILD_DDB_LIST 1 999 1000 /* Defines for process_aen() */ 1001 #define PROCESS_ALL_AENS 0 1002 #define FLUSH_DDB_CHANGED_AENS 1 1003 1004 /* Defines for udev events */ 1005 #define QL4_UEVENT_CODE_FW_DUMP 0 1006 1007 #endif /*_QLA4XXX_H */ 1008