1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8 #ifndef __QL4_DEF_H 9 #define __QL4_DEF_H 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/module.h> 15 #include <linux/list.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/sched.h> 19 #include <linux/slab.h> 20 #include <linux/dmapool.h> 21 #include <linux/mempool.h> 22 #include <linux/spinlock.h> 23 #include <linux/workqueue.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/mutex.h> 27 #include <linux/aer.h> 28 29 #include <net/tcp.h> 30 #include <scsi/scsi.h> 31 #include <scsi/scsi_host.h> 32 #include <scsi/scsi_device.h> 33 #include <scsi/scsi_cmnd.h> 34 #include <scsi/scsi_transport.h> 35 #include <scsi/scsi_transport_iscsi.h> 36 37 #include "ql4_dbg.h" 38 #include "ql4_nx.h" 39 40 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010 41 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010 42 #endif 43 44 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 45 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 46 #endif 47 48 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032 49 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032 50 #endif 51 52 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022 53 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022 54 #endif 55 56 #define ISP4XXX_PCI_FN_1 0x1 57 #define ISP4XXX_PCI_FN_2 0x3 58 59 #define QLA_SUCCESS 0 60 #define QLA_ERROR 1 61 62 /* 63 * Data bit definitions 64 */ 65 #define BIT_0 0x1 66 #define BIT_1 0x2 67 #define BIT_2 0x4 68 #define BIT_3 0x8 69 #define BIT_4 0x10 70 #define BIT_5 0x20 71 #define BIT_6 0x40 72 #define BIT_7 0x80 73 #define BIT_8 0x100 74 #define BIT_9 0x200 75 #define BIT_10 0x400 76 #define BIT_11 0x800 77 #define BIT_12 0x1000 78 #define BIT_13 0x2000 79 #define BIT_14 0x4000 80 #define BIT_15 0x8000 81 #define BIT_16 0x10000 82 #define BIT_17 0x20000 83 #define BIT_18 0x40000 84 #define BIT_19 0x80000 85 #define BIT_20 0x100000 86 #define BIT_21 0x200000 87 #define BIT_22 0x400000 88 #define BIT_23 0x800000 89 #define BIT_24 0x1000000 90 #define BIT_25 0x2000000 91 #define BIT_26 0x4000000 92 #define BIT_27 0x8000000 93 #define BIT_28 0x10000000 94 #define BIT_29 0x20000000 95 #define BIT_30 0x40000000 96 #define BIT_31 0x80000000 97 98 /** 99 * Macros to help code, maintain, etc. 100 **/ 101 #define ql4_printk(level, ha, format, arg...) \ 102 dev_printk(level , &((ha)->pdev->dev) , format , ## arg) 103 104 105 /* 106 * Host adapter default definitions 107 ***********************************/ 108 #define MAX_HBAS 16 109 #define MAX_BUSES 1 110 #define MAX_TARGETS MAX_DEV_DB_ENTRIES 111 #define MAX_LUNS 0xffff 112 #define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */ 113 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES 114 #define MAX_PDU_ENTRIES 32 115 #define INVALID_ENTRY 0xFFFF 116 #define MAX_CMDS_TO_RISC 1024 117 #define MAX_SRBS MAX_CMDS_TO_RISC 118 #define MBOX_AEN_REG_COUNT 8 119 #define MAX_INIT_RETRIES 5 120 121 /* 122 * Buffer sizes 123 */ 124 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC 125 #define RESPONSE_QUEUE_DEPTH 64 126 #define QUEUE_SIZE 64 127 #define DMA_BUFFER_SIZE 512 128 129 /* 130 * Misc 131 */ 132 #define MAC_ADDR_LEN 6 /* in bytes */ 133 #define IP_ADDR_LEN 4 /* in bytes */ 134 #define IPv6_ADDR_LEN 16 /* IPv6 address size */ 135 #define DRIVER_NAME "qla4xxx" 136 137 #define MAX_LINKED_CMDS_PER_LUN 3 138 #define MAX_REQS_SERVICED_PER_INTR 1 139 140 #define ISCSI_IPADDR_SIZE 4 /* IP address size */ 141 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */ 142 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */ 143 144 #define QL4_SESS_RECOVERY_TMO 30 /* iSCSI session */ 145 /* recovery timeout */ 146 147 #define LSDW(x) ((u32)((u64)(x))) 148 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16)) 149 150 /* 151 * Retry & Timeout Values 152 */ 153 #define MBOX_TOV 60 154 #define SOFT_RESET_TOV 30 155 #define RESET_INTR_TOV 3 156 #define SEMAPHORE_TOV 10 157 #define ADAPTER_INIT_TOV 30 158 #define ADAPTER_RESET_TOV 180 159 #define EXTEND_CMD_TOV 60 160 #define WAIT_CMD_TOV 30 161 #define EH_WAIT_CMD_TOV 120 162 #define FIRMWARE_UP_TOV 60 163 #define RESET_FIRMWARE_TOV 30 164 #define LOGOUT_TOV 10 165 #define IOCB_TOV_MARGIN 10 166 #define RELOGIN_TOV 18 167 #define ISNS_DEREG_TOV 5 168 #define HBA_ONLINE_TOV 30 169 170 #define MAX_RESET_HA_RETRIES 2 171 172 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 173 174 /* 175 * SCSI Request Block structure (srb) that is placed 176 * on cmd->SCp location of every I/O [We have 22 bytes available] 177 */ 178 struct srb { 179 struct list_head list; /* (8) */ 180 struct scsi_qla_host *ha; /* HA the SP is queued on */ 181 struct ddb_entry *ddb; 182 uint16_t flags; /* (1) Status flags. */ 183 184 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */ 185 #define SRB_GOT_SENSE BIT_4 /* sense data received. */ 186 uint8_t state; /* (1) Status flags. */ 187 188 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */ 189 #define SRB_FREE_STATE 1 190 #define SRB_ACTIVE_STATE 3 191 #define SRB_ACTIVE_TIMEOUT_STATE 4 192 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */ 193 194 struct scsi_cmnd *cmd; /* (4) SCSI command block */ 195 dma_addr_t dma_handle; /* (4) for unmap of single transfers */ 196 struct kref srb_ref; /* reference count for this srb */ 197 uint8_t err_id; /* error id */ 198 #define SRB_ERR_PORT 1 /* Request failed because "port down" */ 199 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */ 200 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */ 201 #define SRB_ERR_OTHER 4 202 203 uint16_t reserved; 204 uint16_t iocb_tov; 205 uint16_t iocb_cnt; /* Number of used iocbs */ 206 uint16_t cc_stat; 207 208 /* Used for extended sense / status continuation */ 209 uint8_t *req_sense_ptr; 210 uint16_t req_sense_len; 211 uint16_t reserved2; 212 }; 213 214 /* 215 * Asynchronous Event Queue structure 216 */ 217 struct aen { 218 uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; 219 }; 220 221 struct ql4_aen_log { 222 int count; 223 struct aen entry[MAX_AEN_ENTRIES]; 224 }; 225 226 /* 227 * Device Database (DDB) structure 228 */ 229 struct ddb_entry { 230 struct list_head list; /* ddb list */ 231 struct scsi_qla_host *ha; 232 struct iscsi_cls_session *sess; 233 struct iscsi_cls_conn *conn; 234 235 atomic_t state; /* DDB State */ 236 237 unsigned long flags; /* DDB Flags */ 238 239 uint16_t fw_ddb_index; /* DDB firmware index */ 240 uint16_t options; 241 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */ 242 243 uint32_t CmdSn; 244 uint16_t target_session_id; 245 uint16_t connection_id; 246 uint16_t exe_throttle; /* Max mumber of cmds outstanding 247 * simultaneously */ 248 uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to 249 * complete */ 250 uint16_t default_relogin_timeout; /* Max time to wait for 251 * relogin to complete */ 252 uint16_t tcp_source_port_num; 253 uint32_t default_time2wait; /* Default Min time between 254 * relogins (+aens) */ 255 256 atomic_t retry_relogin_timer; /* Min Time between relogins 257 * (4000 only) */ 258 atomic_t relogin_timer; /* Max Time to wait for relogin to complete */ 259 atomic_t relogin_retry_count; /* Num of times relogin has been 260 * retried */ 261 262 uint16_t port; 263 uint32_t tpgt; 264 uint8_t ip_addr[IP_ADDR_LEN]; 265 uint8_t iscsi_name[ISCSI_NAME_SIZE]; /* 72 x48 */ 266 uint8_t iscsi_alias[0x20]; 267 uint8_t isid[6]; 268 uint16_t iscsi_max_burst_len; 269 uint16_t iscsi_max_outsnd_r2t; 270 uint16_t iscsi_first_burst_len; 271 uint16_t iscsi_max_rcv_data_seg_len; 272 uint16_t iscsi_max_snd_data_seg_len; 273 274 struct in6_addr remote_ipv6_addr; 275 struct in6_addr link_local_ipv6_addr; 276 }; 277 278 /* 279 * DDB states. 280 */ 281 #define DDB_STATE_DEAD 0 /* We can no longer talk to 282 * this device */ 283 #define DDB_STATE_ONLINE 1 /* Device ready to accept 284 * commands */ 285 #define DDB_STATE_MISSING 2 /* Device logged off, trying 286 * to re-login */ 287 288 /* 289 * DDB flags. 290 */ 291 #define DF_RELOGIN 0 /* Relogin to device */ 292 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */ 293 #define DF_FO_MASKED 3 294 295 296 #include "ql4_fw.h" 297 #include "ql4_nvram.h" 298 299 struct ql82xx_hw_data { 300 /* Offsets for flash/nvram access (set to ~0 if not used). */ 301 uint32_t flash_conf_off; 302 uint32_t flash_data_off; 303 304 uint32_t fdt_wrt_disable; 305 uint32_t fdt_erase_cmd; 306 uint32_t fdt_block_size; 307 uint32_t fdt_unprotect_sec_cmd; 308 uint32_t fdt_protect_sec_cmd; 309 310 uint32_t flt_region_flt; 311 uint32_t flt_region_fdt; 312 uint32_t flt_region_boot; 313 uint32_t flt_region_bootload; 314 uint32_t flt_region_fw; 315 uint32_t reserved; 316 }; 317 318 struct qla4_8xxx_legacy_intr_set { 319 uint32_t int_vec_bit; 320 uint32_t tgt_status_reg; 321 uint32_t tgt_mask_reg; 322 uint32_t pci_int_reg; 323 }; 324 325 /* MSI-X Support */ 326 327 #define QLA_MSIX_DEFAULT 0x00 328 #define QLA_MSIX_RSP_Q 0x01 329 330 #define QLA_MSIX_ENTRIES 2 331 #define QLA_MIDX_DEFAULT 0 332 #define QLA_MIDX_RSP_Q 1 333 334 struct ql4_msix_entry { 335 int have_irq; 336 uint16_t msix_vector; 337 uint16_t msix_entry; 338 }; 339 340 /* 341 * ISP Operations 342 */ 343 struct isp_operations { 344 int (*iospace_config) (struct scsi_qla_host *ha); 345 void (*pci_config) (struct scsi_qla_host *); 346 void (*disable_intrs) (struct scsi_qla_host *); 347 void (*enable_intrs) (struct scsi_qla_host *); 348 int (*start_firmware) (struct scsi_qla_host *); 349 irqreturn_t (*intr_handler) (int , void *); 350 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t); 351 int (*reset_chip) (struct scsi_qla_host *); 352 int (*reset_firmware) (struct scsi_qla_host *); 353 void (*queue_iocb) (struct scsi_qla_host *); 354 void (*complete_iocb) (struct scsi_qla_host *); 355 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *); 356 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *); 357 int (*get_sys_info) (struct scsi_qla_host *); 358 }; 359 360 /* 361 * Linux Host Adapter structure 362 */ 363 struct scsi_qla_host { 364 /* Linux adapter configuration data */ 365 unsigned long flags; 366 367 #define AF_ONLINE 0 /* 0x00000001 */ 368 #define AF_INIT_DONE 1 /* 0x00000002 */ 369 #define AF_MBOX_COMMAND 2 /* 0x00000004 */ 370 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */ 371 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */ 372 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ 373 #define AF_LINK_UP 8 /* 0x00000100 */ 374 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */ 375 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */ 376 #define AF_HA_REMOVAL 12 /* 0x00001000 */ 377 #define AF_INTx_ENABLED 15 /* 0x00008000 */ 378 #define AF_MSI_ENABLED 16 /* 0x00010000 */ 379 #define AF_MSIX_ENABLED 17 /* 0x00020000 */ 380 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */ 381 #define AF_FW_RECOVERY 19 /* 0x00080000 */ 382 #define AF_EEH_BUSY 20 /* 0x00100000 */ 383 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */ 384 385 unsigned long dpc_flags; 386 387 #define DPC_RESET_HA 1 /* 0x00000002 */ 388 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */ 389 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */ 390 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */ 391 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */ 392 #define DPC_ISNS_RESTART 7 /* 0x00000080 */ 393 #define DPC_AEN 9 /* 0x00000200 */ 394 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */ 395 #define DPC_LINK_CHANGED 18 /* 0x00040000 */ 396 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */ 397 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/ 398 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/ 399 400 401 struct Scsi_Host *host; /* pointer to host data */ 402 uint32_t tot_ddbs; 403 404 uint16_t iocb_cnt; 405 406 /* SRB cache. */ 407 #define SRB_MIN_REQ 128 408 mempool_t *srb_mempool; 409 410 /* pci information */ 411 struct pci_dev *pdev; 412 413 struct isp_reg __iomem *reg; /* Base I/O address */ 414 unsigned long pio_address; 415 unsigned long pio_length; 416 #define MIN_IOBASE_LEN 0x100 417 418 uint16_t req_q_count; 419 420 unsigned long host_no; 421 422 /* NVRAM registers */ 423 struct eeprom_data *nvram; 424 spinlock_t hardware_lock ____cacheline_aligned; 425 uint32_t eeprom_cmd_data; 426 427 /* Counters for general statistics */ 428 uint64_t isr_count; 429 uint64_t adapter_error_count; 430 uint64_t device_error_count; 431 uint64_t total_io_count; 432 uint64_t total_mbytes_xferred; 433 uint64_t link_failure_count; 434 uint64_t invalid_crc_count; 435 uint32_t bytes_xfered; 436 uint32_t spurious_int_count; 437 uint32_t aborted_io_count; 438 uint32_t io_timeout_count; 439 uint32_t mailbox_timeout_count; 440 uint32_t seconds_since_last_intr; 441 uint32_t seconds_since_last_heartbeat; 442 uint32_t mac_index; 443 444 /* Info Needed for Management App */ 445 /* --- From GetFwVersion --- */ 446 uint32_t firmware_version[2]; 447 uint32_t patch_number; 448 uint32_t build_number; 449 uint32_t board_id; 450 451 /* --- From Init_FW --- */ 452 /* init_cb_t *init_cb; */ 453 uint16_t firmware_options; 454 uint16_t tcp_options; 455 uint8_t ip_address[IP_ADDR_LEN]; 456 uint8_t subnet_mask[IP_ADDR_LEN]; 457 uint8_t gateway[IP_ADDR_LEN]; 458 uint8_t alias[32]; 459 uint8_t name_string[256]; 460 uint8_t heartbeat_interval; 461 462 /* --- From FlashSysInfo --- */ 463 uint8_t my_mac[MAC_ADDR_LEN]; 464 uint8_t serial_number[16]; 465 466 /* --- From GetFwState --- */ 467 uint32_t firmware_state; 468 uint32_t addl_fw_state; 469 470 /* Linux kernel thread */ 471 struct workqueue_struct *dpc_thread; 472 struct work_struct dpc_work; 473 474 /* Linux timer thread */ 475 struct timer_list timer; 476 uint32_t timer_active; 477 478 /* Recovery Timers */ 479 atomic_t check_relogin_timeouts; 480 uint32_t retry_reset_ha_cnt; 481 uint32_t isp_reset_timer; /* reset test timer */ 482 uint32_t nic_reset_timer; /* simulated nic reset test timer */ 483 int eh_start; 484 struct list_head free_srb_q; 485 uint16_t free_srb_q_count; 486 uint16_t num_srbs_allocated; 487 488 /* DMA Memory Block */ 489 void *queues; 490 dma_addr_t queues_dma; 491 unsigned long queues_len; 492 493 #define MEM_ALIGN_VALUE \ 494 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \ 495 sizeof(struct queue_entry)) 496 /* request and response queue variables */ 497 dma_addr_t request_dma; 498 struct queue_entry *request_ring; 499 struct queue_entry *request_ptr; 500 dma_addr_t response_dma; 501 struct queue_entry *response_ring; 502 struct queue_entry *response_ptr; 503 dma_addr_t shadow_regs_dma; 504 struct shadow_regs *shadow_regs; 505 uint16_t request_in; /* Current indexes. */ 506 uint16_t request_out; 507 uint16_t response_in; 508 uint16_t response_out; 509 510 /* aen queue variables */ 511 uint16_t aen_q_count; /* Number of available aen_q entries */ 512 uint16_t aen_in; /* Current indexes */ 513 uint16_t aen_out; 514 struct aen aen_q[MAX_AEN_ENTRIES]; 515 516 struct ql4_aen_log aen_log;/* tracks all aens */ 517 518 /* This mutex protects several threads to do mailbox commands 519 * concurrently. 520 */ 521 struct mutex mbox_sem; 522 523 /* temporary mailbox status registers */ 524 volatile uint8_t mbox_status_count; 525 volatile uint32_t mbox_status[MBOX_REG_COUNT]; 526 527 /* local device database list (contains internal ddb entries) */ 528 struct list_head ddb_list; 529 530 /* Map ddb_list entry by FW ddb index */ 531 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES]; 532 533 /* Saved srb for status continuation entry processing */ 534 struct srb *status_srb; 535 536 /* IPv6 support info from InitFW */ 537 uint8_t acb_version; 538 uint8_t ipv4_addr_state; 539 uint16_t ipv4_options; 540 541 uint32_t resvd2; 542 uint32_t ipv6_options; 543 uint32_t ipv6_addl_options; 544 uint8_t ipv6_link_local_state; 545 uint8_t ipv6_addr0_state; 546 uint8_t ipv6_addr1_state; 547 uint8_t ipv6_default_router_state; 548 struct in6_addr ipv6_link_local_addr; 549 struct in6_addr ipv6_addr0; 550 struct in6_addr ipv6_addr1; 551 struct in6_addr ipv6_default_router_addr; 552 553 /* qla82xx specific fields */ 554 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */ 555 unsigned long nx_pcibase; /* Base I/O address */ 556 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */ 557 unsigned long nx_db_wr_ptr; /* Door bell write pointer */ 558 unsigned long first_page_group_start; 559 unsigned long first_page_group_end; 560 561 uint32_t crb_win; 562 uint32_t curr_window; 563 uint32_t ddr_mn_window; 564 unsigned long mn_win_crb; 565 unsigned long ms_win_crb; 566 int qdr_sn_window; 567 rwlock_t hw_lock; 568 uint16_t func_num; 569 int link_width; 570 571 struct qla4_8xxx_legacy_intr_set nx_legacy_intr; 572 u32 nx_crb_mask; 573 574 uint8_t revision_id; 575 uint32_t fw_heartbeat_counter; 576 577 struct isp_operations *isp_ops; 578 struct ql82xx_hw_data hw; 579 580 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES]; 581 582 uint32_t nx_dev_init_timeout; 583 uint32_t nx_reset_timeout; 584 585 struct completion mbx_intr_comp; 586 587 /* --- From About Firmware --- */ 588 uint16_t iscsi_major; 589 uint16_t iscsi_minor; 590 uint16_t bootload_major; 591 uint16_t bootload_minor; 592 uint16_t bootload_patch; 593 uint16_t bootload_build; 594 }; 595 596 static inline int is_ipv4_enabled(struct scsi_qla_host *ha) 597 { 598 return ((ha->ipv4_options & IPOPT_IPv4_PROTOCOL_ENABLE) != 0); 599 } 600 601 static inline int is_ipv6_enabled(struct scsi_qla_host *ha) 602 { 603 return ((ha->ipv6_options & IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0); 604 } 605 606 static inline int is_qla4010(struct scsi_qla_host *ha) 607 { 608 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010; 609 } 610 611 static inline int is_qla4022(struct scsi_qla_host *ha) 612 { 613 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; 614 } 615 616 static inline int is_qla4032(struct scsi_qla_host *ha) 617 { 618 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032; 619 } 620 621 static inline int is_qla8022(struct scsi_qla_host *ha) 622 { 623 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 624 } 625 626 /* Note: Currently AER/EEH is now supported only for 8022 cards 627 * This function needs to be updated when AER/EEH is enabled 628 * for other cards. 629 */ 630 static inline int is_aer_supported(struct scsi_qla_host *ha) 631 { 632 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 633 } 634 635 static inline int adapter_up(struct scsi_qla_host *ha) 636 { 637 return (test_bit(AF_ONLINE, &ha->flags) != 0) && 638 (test_bit(AF_LINK_UP, &ha->flags) != 0); 639 } 640 641 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost) 642 { 643 return (struct scsi_qla_host *)shost->hostdata; 644 } 645 646 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) 647 { 648 return (is_qla4010(ha) ? 649 &ha->reg->u1.isp4010.nvram : 650 &ha->reg->u1.isp4022.semaphore); 651 } 652 653 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) 654 { 655 return (is_qla4010(ha) ? 656 &ha->reg->u1.isp4010.nvram : 657 &ha->reg->u1.isp4022.nvram); 658 } 659 660 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) 661 { 662 return (is_qla4010(ha) ? 663 &ha->reg->u2.isp4010.ext_hw_conf : 664 &ha->reg->u2.isp4022.p0.ext_hw_conf); 665 } 666 667 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) 668 { 669 return (is_qla4010(ha) ? 670 &ha->reg->u2.isp4010.port_status : 671 &ha->reg->u2.isp4022.p0.port_status); 672 } 673 674 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) 675 { 676 return (is_qla4010(ha) ? 677 &ha->reg->u2.isp4010.port_ctrl : 678 &ha->reg->u2.isp4022.p0.port_ctrl); 679 } 680 681 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) 682 { 683 return (is_qla4010(ha) ? 684 &ha->reg->u2.isp4010.port_err_status : 685 &ha->reg->u2.isp4022.p0.port_err_status); 686 } 687 688 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) 689 { 690 return (is_qla4010(ha) ? 691 &ha->reg->u2.isp4010.gp_out : 692 &ha->reg->u2.isp4022.p0.gp_out); 693 } 694 695 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) 696 { 697 return (is_qla4010(ha) ? 698 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 : 699 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2); 700 } 701 702 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 703 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask); 704 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 705 706 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) 707 { 708 if (is_qla4010(a)) 709 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, 710 QL4010_FLASH_SEM_BITS); 711 else 712 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, 713 (QL4022_RESOURCE_BITS_BASE_CODE | 714 (a->mac_index)) << 13); 715 } 716 717 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) 718 { 719 if (is_qla4010(a)) 720 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); 721 else 722 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); 723 } 724 725 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) 726 { 727 if (is_qla4010(a)) 728 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, 729 QL4010_NVRAM_SEM_BITS); 730 else 731 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, 732 (QL4022_RESOURCE_BITS_BASE_CODE | 733 (a->mac_index)) << 10); 734 } 735 736 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) 737 { 738 if (is_qla4010(a)) 739 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); 740 else 741 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); 742 } 743 744 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) 745 { 746 if (is_qla4010(a)) 747 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, 748 QL4010_DRVR_SEM_BITS); 749 else 750 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, 751 (QL4022_RESOURCE_BITS_BASE_CODE | 752 (a->mac_index)) << 1); 753 } 754 755 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) 756 { 757 if (is_qla4010(a)) 758 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); 759 else 760 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); 761 } 762 763 /*---------------------------------------------------------------------------*/ 764 765 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */ 766 #define PRESERVE_DDB_LIST 0 767 #define REBUILD_DDB_LIST 1 768 769 /* Defines for process_aen() */ 770 #define PROCESS_ALL_AENS 0 771 #define FLUSH_DDB_CHANGED_AENS 1 772 773 #endif /*_QLA4XXX_H */ 774