1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 8 #ifndef __QL4_DEF_H 9 #define __QL4_DEF_H 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/module.h> 15 #include <linux/list.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/sched.h> 19 #include <linux/slab.h> 20 #include <linux/dmapool.h> 21 #include <linux/mempool.h> 22 #include <linux/spinlock.h> 23 #include <linux/workqueue.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/mutex.h> 27 #include <linux/aer.h> 28 #include <linux/bsg-lib.h> 29 30 #include <net/tcp.h> 31 #include <scsi/scsi.h> 32 #include <scsi/scsi_host.h> 33 #include <scsi/scsi_device.h> 34 #include <scsi/scsi_cmnd.h> 35 #include <scsi/scsi_transport.h> 36 #include <scsi/scsi_transport_iscsi.h> 37 #include <scsi/scsi_bsg_iscsi.h> 38 #include <scsi/scsi_netlink.h> 39 #include <scsi/libiscsi.h> 40 41 #include "ql4_dbg.h" 42 #include "ql4_nx.h" 43 #include "ql4_fw.h" 44 #include "ql4_nvram.h" 45 46 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010 47 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010 48 #endif 49 50 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022 51 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022 52 #endif 53 54 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032 55 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032 56 #endif 57 58 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022 59 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022 60 #endif 61 62 #define ISP4XXX_PCI_FN_1 0x1 63 #define ISP4XXX_PCI_FN_2 0x3 64 65 #define QLA_SUCCESS 0 66 #define QLA_ERROR 1 67 68 /* 69 * Data bit definitions 70 */ 71 #define BIT_0 0x1 72 #define BIT_1 0x2 73 #define BIT_2 0x4 74 #define BIT_3 0x8 75 #define BIT_4 0x10 76 #define BIT_5 0x20 77 #define BIT_6 0x40 78 #define BIT_7 0x80 79 #define BIT_8 0x100 80 #define BIT_9 0x200 81 #define BIT_10 0x400 82 #define BIT_11 0x800 83 #define BIT_12 0x1000 84 #define BIT_13 0x2000 85 #define BIT_14 0x4000 86 #define BIT_15 0x8000 87 #define BIT_16 0x10000 88 #define BIT_17 0x20000 89 #define BIT_18 0x40000 90 #define BIT_19 0x80000 91 #define BIT_20 0x100000 92 #define BIT_21 0x200000 93 #define BIT_22 0x400000 94 #define BIT_23 0x800000 95 #define BIT_24 0x1000000 96 #define BIT_25 0x2000000 97 #define BIT_26 0x4000000 98 #define BIT_27 0x8000000 99 #define BIT_28 0x10000000 100 #define BIT_29 0x20000000 101 #define BIT_30 0x40000000 102 #define BIT_31 0x80000000 103 104 /** 105 * Macros to help code, maintain, etc. 106 **/ 107 #define ql4_printk(level, ha, format, arg...) \ 108 dev_printk(level , &((ha)->pdev->dev) , format , ## arg) 109 110 111 /* 112 * Host adapter default definitions 113 ***********************************/ 114 #define MAX_HBAS 16 115 #define MAX_BUSES 1 116 #define MAX_TARGETS MAX_DEV_DB_ENTRIES 117 #define MAX_LUNS 0xffff 118 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES 119 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES 120 #define MAX_PDU_ENTRIES 32 121 #define INVALID_ENTRY 0xFFFF 122 #define MAX_CMDS_TO_RISC 1024 123 #define MAX_SRBS MAX_CMDS_TO_RISC 124 #define MBOX_AEN_REG_COUNT 8 125 #define MAX_INIT_RETRIES 5 126 127 /* 128 * Buffer sizes 129 */ 130 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC 131 #define RESPONSE_QUEUE_DEPTH 64 132 #define QUEUE_SIZE 64 133 #define DMA_BUFFER_SIZE 512 134 135 /* 136 * Misc 137 */ 138 #define MAC_ADDR_LEN 6 /* in bytes */ 139 #define IP_ADDR_LEN 4 /* in bytes */ 140 #define IPv6_ADDR_LEN 16 /* IPv6 address size */ 141 #define DRIVER_NAME "qla4xxx" 142 143 #define MAX_LINKED_CMDS_PER_LUN 3 144 #define MAX_REQS_SERVICED_PER_INTR 1 145 146 #define ISCSI_IPADDR_SIZE 4 /* IP address size */ 147 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */ 148 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */ 149 150 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */ 151 /* recovery timeout */ 152 153 #define LSDW(x) ((u32)((u64)(x))) 154 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16)) 155 156 /* 157 * Retry & Timeout Values 158 */ 159 #define MBOX_TOV 60 160 #define SOFT_RESET_TOV 30 161 #define RESET_INTR_TOV 3 162 #define SEMAPHORE_TOV 10 163 #define ADAPTER_INIT_TOV 30 164 #define ADAPTER_RESET_TOV 180 165 #define EXTEND_CMD_TOV 60 166 #define WAIT_CMD_TOV 30 167 #define EH_WAIT_CMD_TOV 120 168 #define FIRMWARE_UP_TOV 60 169 #define RESET_FIRMWARE_TOV 30 170 #define LOGOUT_TOV 10 171 #define IOCB_TOV_MARGIN 10 172 #define RELOGIN_TOV 18 173 #define ISNS_DEREG_TOV 5 174 #define HBA_ONLINE_TOV 30 175 #define DISABLE_ACB_TOV 30 176 #define IP_CONFIG_TOV 30 177 #define LOGIN_TOV 12 178 179 #define MAX_RESET_HA_RETRIES 2 180 #define FW_ALIVE_WAIT_TOV 3 181 182 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 183 184 /* 185 * SCSI Request Block structure (srb) that is placed 186 * on cmd->SCp location of every I/O [We have 22 bytes available] 187 */ 188 struct srb { 189 struct list_head list; /* (8) */ 190 struct scsi_qla_host *ha; /* HA the SP is queued on */ 191 struct ddb_entry *ddb; 192 uint16_t flags; /* (1) Status flags. */ 193 194 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */ 195 #define SRB_GOT_SENSE BIT_4 /* sense data received. */ 196 uint8_t state; /* (1) Status flags. */ 197 198 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */ 199 #define SRB_FREE_STATE 1 200 #define SRB_ACTIVE_STATE 3 201 #define SRB_ACTIVE_TIMEOUT_STATE 4 202 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */ 203 204 struct scsi_cmnd *cmd; /* (4) SCSI command block */ 205 dma_addr_t dma_handle; /* (4) for unmap of single transfers */ 206 struct kref srb_ref; /* reference count for this srb */ 207 uint8_t err_id; /* error id */ 208 #define SRB_ERR_PORT 1 /* Request failed because "port down" */ 209 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */ 210 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */ 211 #define SRB_ERR_OTHER 4 212 213 uint16_t reserved; 214 uint16_t iocb_tov; 215 uint16_t iocb_cnt; /* Number of used iocbs */ 216 uint16_t cc_stat; 217 218 /* Used for extended sense / status continuation */ 219 uint8_t *req_sense_ptr; 220 uint16_t req_sense_len; 221 uint16_t reserved2; 222 }; 223 224 /* Mailbox request block structure */ 225 struct mrb { 226 struct scsi_qla_host *ha; 227 struct mbox_cmd_iocb *mbox; 228 uint32_t mbox_cmd; 229 uint16_t iocb_cnt; /* Number of used iocbs */ 230 uint32_t pid; 231 }; 232 233 /* 234 * Asynchronous Event Queue structure 235 */ 236 struct aen { 237 uint32_t mbox_sts[MBOX_AEN_REG_COUNT]; 238 }; 239 240 struct ql4_aen_log { 241 int count; 242 struct aen entry[MAX_AEN_ENTRIES]; 243 }; 244 245 /* 246 * Device Database (DDB) structure 247 */ 248 struct ddb_entry { 249 struct scsi_qla_host *ha; 250 struct iscsi_cls_session *sess; 251 struct iscsi_cls_conn *conn; 252 253 uint16_t fw_ddb_index; /* DDB firmware index */ 254 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */ 255 uint16_t ddb_type; 256 #define FLASH_DDB 0x01 257 258 struct dev_db_entry fw_ddb_entry; 259 int (*unblock_sess)(struct iscsi_cls_session *cls_session); 260 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index, 261 struct ddb_entry *ddb_entry, uint32_t state); 262 263 /* Driver Re-login */ 264 unsigned long flags; /* DDB Flags */ 265 uint16_t default_relogin_timeout; /* Max time to wait for 266 * relogin to complete */ 267 atomic_t retry_relogin_timer; /* Min Time between relogins 268 * (4000 only) */ 269 atomic_t relogin_timer; /* Max Time to wait for 270 * relogin to complete */ 271 atomic_t relogin_retry_count; /* Num of times relogin has been 272 * retried */ 273 uint32_t default_time2wait; /* Default Min time between 274 * relogins (+aens) */ 275 uint16_t chap_tbl_idx; 276 }; 277 278 struct qla_ddb_index { 279 struct list_head list; 280 uint16_t fw_ddb_idx; 281 struct dev_db_entry fw_ddb; 282 }; 283 284 #define DDB_IPADDR_LEN 64 285 286 struct ql4_tuple_ddb { 287 int port; 288 int tpgt; 289 char ip_addr[DDB_IPADDR_LEN]; 290 char iscsi_name[ISCSI_NAME_SIZE]; 291 uint16_t options; 292 #define DDB_OPT_IPV6 0x0e0e 293 #define DDB_OPT_IPV4 0x0f0f 294 uint8_t isid[6]; 295 }; 296 297 /* 298 * DDB states. 299 */ 300 #define DDB_STATE_DEAD 0 /* We can no longer talk to 301 * this device */ 302 #define DDB_STATE_ONLINE 1 /* Device ready to accept 303 * commands */ 304 #define DDB_STATE_MISSING 2 /* Device logged off, trying 305 * to re-login */ 306 307 /* 308 * DDB flags. 309 */ 310 #define DF_RELOGIN 0 /* Relogin to device */ 311 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */ 312 #define DF_FO_MASKED 3 313 314 enum qla4_work_type { 315 QLA4_EVENT_AEN, 316 QLA4_EVENT_PING_STATUS, 317 }; 318 319 struct qla4_work_evt { 320 struct list_head list; 321 enum qla4_work_type type; 322 union { 323 struct { 324 enum iscsi_host_event_code code; 325 uint32_t data_size; 326 uint8_t data[0]; 327 } aen; 328 struct { 329 uint32_t status; 330 uint32_t pid; 331 uint32_t data_size; 332 uint8_t data[0]; 333 } ping; 334 } u; 335 }; 336 337 struct ql82xx_hw_data { 338 /* Offsets for flash/nvram access (set to ~0 if not used). */ 339 uint32_t flash_conf_off; 340 uint32_t flash_data_off; 341 342 uint32_t fdt_wrt_disable; 343 uint32_t fdt_erase_cmd; 344 uint32_t fdt_block_size; 345 uint32_t fdt_unprotect_sec_cmd; 346 uint32_t fdt_protect_sec_cmd; 347 348 uint32_t flt_region_flt; 349 uint32_t flt_region_fdt; 350 uint32_t flt_region_boot; 351 uint32_t flt_region_bootload; 352 uint32_t flt_region_fw; 353 354 uint32_t flt_iscsi_param; 355 uint32_t flt_region_chap; 356 uint32_t flt_chap_size; 357 }; 358 359 struct qla4_8xxx_legacy_intr_set { 360 uint32_t int_vec_bit; 361 uint32_t tgt_status_reg; 362 uint32_t tgt_mask_reg; 363 uint32_t pci_int_reg; 364 }; 365 366 /* MSI-X Support */ 367 368 #define QLA_MSIX_DEFAULT 0x00 369 #define QLA_MSIX_RSP_Q 0x01 370 371 #define QLA_MSIX_ENTRIES 2 372 #define QLA_MIDX_DEFAULT 0 373 #define QLA_MIDX_RSP_Q 1 374 375 struct ql4_msix_entry { 376 int have_irq; 377 uint16_t msix_vector; 378 uint16_t msix_entry; 379 }; 380 381 /* 382 * ISP Operations 383 */ 384 struct isp_operations { 385 int (*iospace_config) (struct scsi_qla_host *ha); 386 void (*pci_config) (struct scsi_qla_host *); 387 void (*disable_intrs) (struct scsi_qla_host *); 388 void (*enable_intrs) (struct scsi_qla_host *); 389 int (*start_firmware) (struct scsi_qla_host *); 390 irqreturn_t (*intr_handler) (int , void *); 391 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t); 392 int (*reset_chip) (struct scsi_qla_host *); 393 int (*reset_firmware) (struct scsi_qla_host *); 394 void (*queue_iocb) (struct scsi_qla_host *); 395 void (*complete_iocb) (struct scsi_qla_host *); 396 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *); 397 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *); 398 int (*get_sys_info) (struct scsi_qla_host *); 399 }; 400 401 /*qla4xxx ipaddress configuration details */ 402 struct ipaddress_config { 403 uint16_t ipv4_options; 404 uint16_t tcp_options; 405 uint16_t ipv4_vlan_tag; 406 uint8_t ipv4_addr_state; 407 uint8_t ip_address[IP_ADDR_LEN]; 408 uint8_t subnet_mask[IP_ADDR_LEN]; 409 uint8_t gateway[IP_ADDR_LEN]; 410 uint32_t ipv6_options; 411 uint32_t ipv6_addl_options; 412 uint8_t ipv6_link_local_state; 413 uint8_t ipv6_addr0_state; 414 uint8_t ipv6_addr1_state; 415 uint8_t ipv6_default_router_state; 416 uint16_t ipv6_vlan_tag; 417 struct in6_addr ipv6_link_local_addr; 418 struct in6_addr ipv6_addr0; 419 struct in6_addr ipv6_addr1; 420 struct in6_addr ipv6_default_router_addr; 421 uint16_t eth_mtu_size; 422 uint16_t ipv4_port; 423 uint16_t ipv6_port; 424 }; 425 426 #define QL4_CHAP_MAX_NAME_LEN 256 427 #define QL4_CHAP_MAX_SECRET_LEN 100 428 #define LOCAL_CHAP 0 429 #define BIDI_CHAP 1 430 431 struct ql4_chap_format { 432 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN]; 433 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN]; 434 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN]; 435 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN]; 436 u16 intr_chap_name_length; 437 u16 intr_secret_length; 438 u16 target_chap_name_length; 439 u16 target_secret_length; 440 }; 441 442 struct ip_address_format { 443 u8 ip_type; 444 u8 ip_address[16]; 445 }; 446 447 struct ql4_conn_info { 448 u16 dest_port; 449 struct ip_address_format dest_ipaddr; 450 struct ql4_chap_format chap; 451 }; 452 453 struct ql4_boot_session_info { 454 u8 target_name[224]; 455 struct ql4_conn_info conn_list[1]; 456 }; 457 458 struct ql4_boot_tgt_info { 459 struct ql4_boot_session_info boot_pri_sess; 460 struct ql4_boot_session_info boot_sec_sess; 461 }; 462 463 /* 464 * Linux Host Adapter structure 465 */ 466 struct scsi_qla_host { 467 /* Linux adapter configuration data */ 468 unsigned long flags; 469 470 #define AF_ONLINE 0 /* 0x00000001 */ 471 #define AF_INIT_DONE 1 /* 0x00000002 */ 472 #define AF_MBOX_COMMAND 2 /* 0x00000004 */ 473 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */ 474 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */ 475 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */ 476 #define AF_LINK_UP 8 /* 0x00000100 */ 477 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */ 478 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */ 479 #define AF_HA_REMOVAL 12 /* 0x00001000 */ 480 #define AF_INTx_ENABLED 15 /* 0x00008000 */ 481 #define AF_MSI_ENABLED 16 /* 0x00010000 */ 482 #define AF_MSIX_ENABLED 17 /* 0x00020000 */ 483 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */ 484 #define AF_FW_RECOVERY 19 /* 0x00080000 */ 485 #define AF_EEH_BUSY 20 /* 0x00100000 */ 486 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */ 487 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */ 488 unsigned long dpc_flags; 489 490 #define DPC_RESET_HA 1 /* 0x00000002 */ 491 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */ 492 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */ 493 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */ 494 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */ 495 #define DPC_ISNS_RESTART 7 /* 0x00000080 */ 496 #define DPC_AEN 9 /* 0x00000200 */ 497 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */ 498 #define DPC_LINK_CHANGED 18 /* 0x00040000 */ 499 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */ 500 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/ 501 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/ 502 503 504 struct Scsi_Host *host; /* pointer to host data */ 505 uint32_t tot_ddbs; 506 507 uint16_t iocb_cnt; 508 509 /* SRB cache. */ 510 #define SRB_MIN_REQ 128 511 mempool_t *srb_mempool; 512 513 /* pci information */ 514 struct pci_dev *pdev; 515 516 struct isp_reg __iomem *reg; /* Base I/O address */ 517 unsigned long pio_address; 518 unsigned long pio_length; 519 #define MIN_IOBASE_LEN 0x100 520 521 uint16_t req_q_count; 522 523 unsigned long host_no; 524 525 /* NVRAM registers */ 526 struct eeprom_data *nvram; 527 spinlock_t hardware_lock ____cacheline_aligned; 528 uint32_t eeprom_cmd_data; 529 530 /* Counters for general statistics */ 531 uint64_t isr_count; 532 uint64_t adapter_error_count; 533 uint64_t device_error_count; 534 uint64_t total_io_count; 535 uint64_t total_mbytes_xferred; 536 uint64_t link_failure_count; 537 uint64_t invalid_crc_count; 538 uint32_t bytes_xfered; 539 uint32_t spurious_int_count; 540 uint32_t aborted_io_count; 541 uint32_t io_timeout_count; 542 uint32_t mailbox_timeout_count; 543 uint32_t seconds_since_last_intr; 544 uint32_t seconds_since_last_heartbeat; 545 uint32_t mac_index; 546 547 /* Info Needed for Management App */ 548 /* --- From GetFwVersion --- */ 549 uint32_t firmware_version[2]; 550 uint32_t patch_number; 551 uint32_t build_number; 552 uint32_t board_id; 553 554 /* --- From Init_FW --- */ 555 /* init_cb_t *init_cb; */ 556 uint16_t firmware_options; 557 uint8_t alias[32]; 558 uint8_t name_string[256]; 559 uint8_t heartbeat_interval; 560 561 /* --- From FlashSysInfo --- */ 562 uint8_t my_mac[MAC_ADDR_LEN]; 563 uint8_t serial_number[16]; 564 uint16_t port_num; 565 /* --- From GetFwState --- */ 566 uint32_t firmware_state; 567 uint32_t addl_fw_state; 568 569 /* Linux kernel thread */ 570 struct workqueue_struct *dpc_thread; 571 struct work_struct dpc_work; 572 573 /* Linux timer thread */ 574 struct timer_list timer; 575 uint32_t timer_active; 576 577 /* Recovery Timers */ 578 atomic_t check_relogin_timeouts; 579 uint32_t retry_reset_ha_cnt; 580 uint32_t isp_reset_timer; /* reset test timer */ 581 uint32_t nic_reset_timer; /* simulated nic reset test timer */ 582 int eh_start; 583 struct list_head free_srb_q; 584 uint16_t free_srb_q_count; 585 uint16_t num_srbs_allocated; 586 587 /* DMA Memory Block */ 588 void *queues; 589 dma_addr_t queues_dma; 590 unsigned long queues_len; 591 592 #define MEM_ALIGN_VALUE \ 593 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \ 594 sizeof(struct queue_entry)) 595 /* request and response queue variables */ 596 dma_addr_t request_dma; 597 struct queue_entry *request_ring; 598 struct queue_entry *request_ptr; 599 dma_addr_t response_dma; 600 struct queue_entry *response_ring; 601 struct queue_entry *response_ptr; 602 dma_addr_t shadow_regs_dma; 603 struct shadow_regs *shadow_regs; 604 uint16_t request_in; /* Current indexes. */ 605 uint16_t request_out; 606 uint16_t response_in; 607 uint16_t response_out; 608 609 /* aen queue variables */ 610 uint16_t aen_q_count; /* Number of available aen_q entries */ 611 uint16_t aen_in; /* Current indexes */ 612 uint16_t aen_out; 613 struct aen aen_q[MAX_AEN_ENTRIES]; 614 615 struct ql4_aen_log aen_log;/* tracks all aens */ 616 617 /* This mutex protects several threads to do mailbox commands 618 * concurrently. 619 */ 620 struct mutex mbox_sem; 621 622 /* temporary mailbox status registers */ 623 volatile uint8_t mbox_status_count; 624 volatile uint32_t mbox_status[MBOX_REG_COUNT]; 625 626 /* FW ddb index map */ 627 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES]; 628 629 /* Saved srb for status continuation entry processing */ 630 struct srb *status_srb; 631 632 uint8_t acb_version; 633 634 /* qla82xx specific fields */ 635 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */ 636 unsigned long nx_pcibase; /* Base I/O address */ 637 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */ 638 unsigned long nx_db_wr_ptr; /* Door bell write pointer */ 639 unsigned long first_page_group_start; 640 unsigned long first_page_group_end; 641 642 uint32_t crb_win; 643 uint32_t curr_window; 644 uint32_t ddr_mn_window; 645 unsigned long mn_win_crb; 646 unsigned long ms_win_crb; 647 int qdr_sn_window; 648 rwlock_t hw_lock; 649 uint16_t func_num; 650 int link_width; 651 652 struct qla4_8xxx_legacy_intr_set nx_legacy_intr; 653 u32 nx_crb_mask; 654 655 uint8_t revision_id; 656 uint32_t fw_heartbeat_counter; 657 658 struct isp_operations *isp_ops; 659 struct ql82xx_hw_data hw; 660 661 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES]; 662 663 uint32_t nx_dev_init_timeout; 664 uint32_t nx_reset_timeout; 665 666 struct completion mbx_intr_comp; 667 668 struct ipaddress_config ip_config; 669 struct iscsi_iface *iface_ipv4; 670 struct iscsi_iface *iface_ipv6_0; 671 struct iscsi_iface *iface_ipv6_1; 672 673 /* --- From About Firmware --- */ 674 uint16_t iscsi_major; 675 uint16_t iscsi_minor; 676 uint16_t bootload_major; 677 uint16_t bootload_minor; 678 uint16_t bootload_patch; 679 uint16_t bootload_build; 680 uint16_t def_timeout; /* Default login timeout */ 681 682 uint32_t flash_state; 683 #define QLFLASH_WAITING 0 684 #define QLFLASH_READING 1 685 #define QLFLASH_WRITING 2 686 struct dma_pool *chap_dma_pool; 687 uint8_t *chap_list; /* CHAP table cache */ 688 struct mutex chap_sem; 689 690 #define CHAP_DMA_BLOCK_SIZE 512 691 struct workqueue_struct *task_wq; 692 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG]; 693 #define SYSFS_FLAG_FW_SEL_BOOT 2 694 struct iscsi_boot_kset *boot_kset; 695 struct ql4_boot_tgt_info boot_tgt; 696 uint16_t phy_port_num; 697 uint16_t phy_port_cnt; 698 uint16_t iscsi_pci_func_cnt; 699 uint8_t model_name[16]; 700 struct completion disable_acb_comp; 701 struct dma_pool *fw_ddb_dma_pool; 702 #define DDB_DMA_BLOCK_SIZE 512 703 uint16_t pri_ddb_idx; 704 uint16_t sec_ddb_idx; 705 int is_reset; 706 uint16_t temperature; 707 708 /* event work list */ 709 struct list_head work_list; 710 spinlock_t work_lock; 711 712 /* mbox iocb */ 713 #define MAX_MRB 128 714 struct mrb *active_mrb_array[MAX_MRB]; 715 uint32_t mrb_index; 716 }; 717 718 struct ql4_task_data { 719 struct scsi_qla_host *ha; 720 uint8_t iocb_req_cnt; 721 dma_addr_t data_dma; 722 void *req_buffer; 723 dma_addr_t req_dma; 724 uint32_t req_len; 725 void *resp_buffer; 726 dma_addr_t resp_dma; 727 uint32_t resp_len; 728 struct iscsi_task *task; 729 struct passthru_status sts; 730 struct work_struct task_work; 731 }; 732 733 struct qla_endpoint { 734 struct Scsi_Host *host; 735 struct sockaddr dst_addr; 736 }; 737 738 struct qla_conn { 739 struct qla_endpoint *qla_ep; 740 }; 741 742 static inline int is_ipv4_enabled(struct scsi_qla_host *ha) 743 { 744 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0); 745 } 746 747 static inline int is_ipv6_enabled(struct scsi_qla_host *ha) 748 { 749 return ((ha->ip_config.ipv6_options & 750 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0); 751 } 752 753 static inline int is_qla4010(struct scsi_qla_host *ha) 754 { 755 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010; 756 } 757 758 static inline int is_qla4022(struct scsi_qla_host *ha) 759 { 760 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022; 761 } 762 763 static inline int is_qla4032(struct scsi_qla_host *ha) 764 { 765 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032; 766 } 767 768 static inline int is_qla40XX(struct scsi_qla_host *ha) 769 { 770 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha); 771 } 772 773 static inline int is_qla8022(struct scsi_qla_host *ha) 774 { 775 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 776 } 777 778 /* Note: Currently AER/EEH is now supported only for 8022 cards 779 * This function needs to be updated when AER/EEH is enabled 780 * for other cards. 781 */ 782 static inline int is_aer_supported(struct scsi_qla_host *ha) 783 { 784 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022; 785 } 786 787 static inline int adapter_up(struct scsi_qla_host *ha) 788 { 789 return (test_bit(AF_ONLINE, &ha->flags) != 0) && 790 (test_bit(AF_LINK_UP, &ha->flags) != 0); 791 } 792 793 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost) 794 { 795 return (struct scsi_qla_host *)iscsi_host_priv(shost); 796 } 797 798 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha) 799 { 800 return (is_qla4010(ha) ? 801 &ha->reg->u1.isp4010.nvram : 802 &ha->reg->u1.isp4022.semaphore); 803 } 804 805 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha) 806 { 807 return (is_qla4010(ha) ? 808 &ha->reg->u1.isp4010.nvram : 809 &ha->reg->u1.isp4022.nvram); 810 } 811 812 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha) 813 { 814 return (is_qla4010(ha) ? 815 &ha->reg->u2.isp4010.ext_hw_conf : 816 &ha->reg->u2.isp4022.p0.ext_hw_conf); 817 } 818 819 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha) 820 { 821 return (is_qla4010(ha) ? 822 &ha->reg->u2.isp4010.port_status : 823 &ha->reg->u2.isp4022.p0.port_status); 824 } 825 826 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha) 827 { 828 return (is_qla4010(ha) ? 829 &ha->reg->u2.isp4010.port_ctrl : 830 &ha->reg->u2.isp4022.p0.port_ctrl); 831 } 832 833 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha) 834 { 835 return (is_qla4010(ha) ? 836 &ha->reg->u2.isp4010.port_err_status : 837 &ha->reg->u2.isp4022.p0.port_err_status); 838 } 839 840 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha) 841 { 842 return (is_qla4010(ha) ? 843 &ha->reg->u2.isp4010.gp_out : 844 &ha->reg->u2.isp4022.p0.gp_out); 845 } 846 847 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha) 848 { 849 return (is_qla4010(ha) ? 850 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 : 851 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2); 852 } 853 854 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 855 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask); 856 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits); 857 858 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a) 859 { 860 if (is_qla4010(a)) 861 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK, 862 QL4010_FLASH_SEM_BITS); 863 else 864 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK, 865 (QL4022_RESOURCE_BITS_BASE_CODE | 866 (a->mac_index)) << 13); 867 } 868 869 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a) 870 { 871 if (is_qla4010(a)) 872 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK); 873 else 874 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK); 875 } 876 877 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a) 878 { 879 if (is_qla4010(a)) 880 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK, 881 QL4010_NVRAM_SEM_BITS); 882 else 883 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK, 884 (QL4022_RESOURCE_BITS_BASE_CODE | 885 (a->mac_index)) << 10); 886 } 887 888 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a) 889 { 890 if (is_qla4010(a)) 891 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK); 892 else 893 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK); 894 } 895 896 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a) 897 { 898 if (is_qla4010(a)) 899 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK, 900 QL4010_DRVR_SEM_BITS); 901 else 902 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK, 903 (QL4022_RESOURCE_BITS_BASE_CODE | 904 (a->mac_index)) << 1); 905 } 906 907 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a) 908 { 909 if (is_qla4010(a)) 910 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK); 911 else 912 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK); 913 } 914 915 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha) 916 { 917 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) || 918 test_bit(DPC_RESET_HA, &ha->dpc_flags) || 919 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) || 920 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) || 921 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) || 922 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags); 923 924 } 925 /*---------------------------------------------------------------------------*/ 926 927 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */ 928 929 #define INIT_ADAPTER 0 930 #define RESET_ADAPTER 1 931 932 #define PRESERVE_DDB_LIST 0 933 #define REBUILD_DDB_LIST 1 934 935 /* Defines for process_aen() */ 936 #define PROCESS_ALL_AENS 0 937 #define FLUSH_DDB_CHANGED_AENS 1 938 939 #endif /*_QLA4XXX_H */ 940