xref: /openbmc/linux/drivers/scsi/qla2xxx/qla_tmpl.h (revision d2999e1b)
1 /*
2  * QLogic Fibre Channel HBA Driver
3  * Copyright (c)  2003-2014 QLogic Corporation
4  *
5  * See LICENSE.qla2xxx for copyright and licensing details.
6  */
7 
8 #ifndef __QLA_DMP27_H__
9 #define	__QLA_DMP27_H__
10 
11 #define IOBASE_ADDR	offsetof(struct device_reg_24xx, iobase_addr)
12 
13 struct __packed qla27xx_fwdt_template {
14 	uint32_t template_type;
15 	uint32_t entry_offset;
16 	uint32_t template_size;
17 	uint32_t reserved_1;
18 
19 	uint32_t entry_count;
20 	uint32_t template_version;
21 	uint32_t capture_timestamp;
22 	uint32_t template_checksum;
23 
24 	uint32_t reserved_2;
25 	uint32_t driver_info[3];
26 
27 	uint32_t saved_state[16];
28 
29 	uint32_t reserved_3[8];
30 	uint32_t firmware_version[5];
31 };
32 
33 #define TEMPLATE_TYPE_FWDUMP		99
34 
35 #define ENTRY_TYPE_NOP			0
36 #define ENTRY_TYPE_TMP_END		255
37 #define ENTRY_TYPE_RD_IOB_T1		256
38 #define ENTRY_TYPE_WR_IOB_T1		257
39 #define ENTRY_TYPE_RD_IOB_T2		258
40 #define ENTRY_TYPE_WR_IOB_T2		259
41 #define ENTRY_TYPE_RD_PCI		260
42 #define ENTRY_TYPE_WR_PCI		261
43 #define ENTRY_TYPE_RD_RAM		262
44 #define ENTRY_TYPE_GET_QUEUE		263
45 #define ENTRY_TYPE_GET_FCE		264
46 #define ENTRY_TYPE_PSE_RISC		265
47 #define ENTRY_TYPE_RST_RISC		266
48 #define ENTRY_TYPE_DIS_INTR		267
49 #define ENTRY_TYPE_GET_HBUF		268
50 #define ENTRY_TYPE_SCRATCH		269
51 #define ENTRY_TYPE_RDREMREG		270
52 #define ENTRY_TYPE_WRREMREG		271
53 #define ENTRY_TYPE_RDREMRAM		272
54 #define ENTRY_TYPE_PCICFG		273
55 #define ENTRY_TYPE_GET_SHADOW		274
56 
57 #define CAPTURE_FLAG_PHYS_ONLY		BIT_0
58 #define CAPTURE_FLAG_PHYS_VIRT		BIT_1
59 
60 #define DRIVER_FLAG_SKIP_ENTRY		BIT_7
61 
62 struct __packed qla27xx_fwdt_entry {
63 	struct __packed {
64 		uint32_t entry_type;
65 		uint32_t entry_size;
66 		uint32_t reserved_1;
67 
68 		uint8_t  capture_flags;
69 		uint8_t  reserved_2[2];
70 		uint8_t  driver_flags;
71 	} hdr;
72 	union __packed {
73 		struct __packed {
74 		} t0;
75 
76 		struct __packed {
77 		} t255;
78 
79 		struct __packed {
80 			uint32_t base_addr;
81 			uint8_t  reg_width;
82 			uint16_t reg_count;
83 			uint8_t  pci_offset;
84 		} t256;
85 
86 		struct __packed {
87 			uint32_t base_addr;
88 			uint32_t write_data;
89 			uint8_t  pci_offset;
90 			uint8_t  reserved[3];
91 		} t257;
92 
93 		struct __packed {
94 			uint32_t base_addr;
95 			uint8_t  reg_width;
96 			uint16_t reg_count;
97 			uint8_t  pci_offset;
98 			uint8_t  banksel_offset;
99 			uint8_t  reserved[3];
100 			uint32_t bank;
101 		} t258;
102 
103 		struct __packed {
104 			uint32_t base_addr;
105 			uint32_t write_data;
106 			uint8_t  reserved[2];
107 			uint8_t  pci_offset;
108 			uint8_t  banksel_offset;
109 			uint32_t bank;
110 		} t259;
111 
112 		struct __packed {
113 			uint8_t pci_offset;
114 			uint8_t reserved[3];
115 		} t260;
116 
117 		struct __packed {
118 			uint8_t pci_offset;
119 			uint8_t reserved[3];
120 			uint32_t write_data;
121 		} t261;
122 
123 		struct __packed {
124 			uint8_t  ram_area;
125 			uint8_t  reserved[3];
126 			uint32_t start_addr;
127 			uint32_t end_addr;
128 		} t262;
129 
130 		struct __packed {
131 			uint32_t num_queues;
132 			uint8_t  queue_type;
133 			uint8_t  reserved[3];
134 		} t263;
135 
136 		struct __packed {
137 			uint32_t fce_trace_size;
138 			uint64_t write_pointer;
139 			uint64_t base_pointer;
140 			uint32_t fce_enable_mb0;
141 			uint32_t fce_enable_mb2;
142 			uint32_t fce_enable_mb3;
143 			uint32_t fce_enable_mb4;
144 			uint32_t fce_enable_mb5;
145 			uint32_t fce_enable_mb6;
146 		} t264;
147 
148 		struct __packed {
149 		} t265;
150 
151 		struct __packed {
152 		} t266;
153 
154 		struct __packed {
155 			uint8_t  pci_offset;
156 			uint8_t  reserved[3];
157 			uint32_t data;
158 		} t267;
159 
160 		struct __packed {
161 			uint8_t  buf_type;
162 			uint8_t  reserved[3];
163 			uint32_t buf_size;
164 			uint64_t start_addr;
165 		} t268;
166 
167 		struct __packed {
168 			uint32_t scratch_size;
169 		} t269;
170 
171 		struct __packed {
172 			uint32_t addr;
173 			uint32_t count;
174 		} t270;
175 
176 		struct __packed {
177 			uint32_t addr;
178 			uint32_t data;
179 		} t271;
180 
181 		struct __packed {
182 			uint32_t addr;
183 			uint32_t count;
184 		} t272;
185 
186 		struct __packed {
187 			uint32_t addr;
188 			uint32_t count;
189 		} t273;
190 
191 		struct __packed {
192 			uint32_t num_queues;
193 			uint8_t  queue_type;
194 			uint8_t  reserved[3];
195 		} t274;
196 	};
197 };
198 
199 #define T262_RAM_AREA_CRITICAL_RAM	1
200 #define T262_RAM_AREA_EXTERNAL_RAM	2
201 #define T262_RAM_AREA_SHARED_RAM	3
202 #define T262_RAM_AREA_DDR_RAM		4
203 
204 #define T263_QUEUE_TYPE_REQ		1
205 #define T263_QUEUE_TYPE_RSP		2
206 #define T263_QUEUE_TYPE_ATIO		3
207 
208 #define T268_BUF_TYPE_EXTD_TRACE	1
209 #define T268_BUF_TYPE_EXCH_BUFOFF	2
210 #define T268_BUF_TYPE_EXTD_LOGIN	3
211 
212 #define T274_QUEUE_TYPE_REQ_SHAD	1
213 #define T274_QUEUE_TYPE_RSP_SHAD	2
214 #define T274_QUEUE_TYPE_ATIO_SHAD	3
215 
216 #endif
217