1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 #ifndef __QLA_DMP27_H__ 9 #define __QLA_DMP27_H__ 10 11 #define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr) 12 13 struct __packed qla27xx_fwdt_template { 14 uint32_t template_type; 15 uint32_t entry_offset; 16 uint32_t template_size; 17 uint32_t reserved_1; 18 19 uint32_t entry_count; 20 uint32_t template_version; 21 uint32_t capture_timestamp; 22 uint32_t template_checksum; 23 24 uint32_t reserved_2; 25 uint32_t driver_info[3]; 26 27 uint32_t saved_state[16]; 28 29 uint32_t reserved_3[8]; 30 uint32_t firmware_version[5]; 31 }; 32 33 #define TEMPLATE_TYPE_FWDUMP 99 34 35 #define ENTRY_TYPE_NOP 0 36 #define ENTRY_TYPE_TMP_END 255 37 #define ENTRY_TYPE_RD_IOB_T1 256 38 #define ENTRY_TYPE_WR_IOB_T1 257 39 #define ENTRY_TYPE_RD_IOB_T2 258 40 #define ENTRY_TYPE_WR_IOB_T2 259 41 #define ENTRY_TYPE_RD_PCI 260 42 #define ENTRY_TYPE_WR_PCI 261 43 #define ENTRY_TYPE_RD_RAM 262 44 #define ENTRY_TYPE_GET_QUEUE 263 45 #define ENTRY_TYPE_GET_FCE 264 46 #define ENTRY_TYPE_PSE_RISC 265 47 #define ENTRY_TYPE_RST_RISC 266 48 #define ENTRY_TYPE_DIS_INTR 267 49 #define ENTRY_TYPE_GET_HBUF 268 50 #define ENTRY_TYPE_SCRATCH 269 51 #define ENTRY_TYPE_RDREMREG 270 52 #define ENTRY_TYPE_WRREMREG 271 53 #define ENTRY_TYPE_RDREMRAM 272 54 #define ENTRY_TYPE_PCICFG 273 55 56 #define CAPTURE_FLAG_PHYS_ONLY BIT_0 57 #define CAPTURE_FLAG_PHYS_VIRT BIT_1 58 59 #define DRIVER_FLAG_SKIP_ENTRY BIT_7 60 61 struct __packed qla27xx_fwdt_entry { 62 struct __packed { 63 uint32_t entry_type; 64 uint32_t entry_size; 65 uint32_t reserved_1; 66 67 uint8_t capture_flags; 68 uint8_t reserved_2[2]; 69 uint8_t driver_flags; 70 } hdr; 71 union __packed { 72 struct __packed { 73 } t0; 74 75 struct __packed { 76 } t255; 77 78 struct __packed { 79 uint32_t base_addr; 80 uint8_t reg_width; 81 uint16_t reg_count; 82 uint8_t pci_offset; 83 } t256; 84 85 struct __packed { 86 uint32_t base_addr; 87 uint32_t write_data; 88 uint8_t pci_offset; 89 uint8_t reserved[3]; 90 } t257; 91 92 struct __packed { 93 uint32_t base_addr; 94 uint8_t reg_width; 95 uint16_t reg_count; 96 uint8_t pci_offset; 97 uint8_t banksel_offset; 98 uint8_t reserved[3]; 99 uint32_t bank; 100 } t258; 101 102 struct __packed { 103 uint32_t base_addr; 104 uint32_t write_data; 105 uint8_t reserved[2]; 106 uint8_t pci_offset; 107 uint8_t banksel_offset; 108 uint32_t bank; 109 } t259; 110 111 struct __packed { 112 uint8_t pci_addr; 113 uint8_t reserved[3]; 114 } t260; 115 116 struct __packed { 117 uint8_t pci_addr; 118 uint8_t reserved[3]; 119 uint32_t write_data; 120 } t261; 121 122 struct __packed { 123 uint8_t ram_area; 124 uint8_t reserved[3]; 125 uint32_t start_addr; 126 uint32_t end_addr; 127 } t262; 128 129 struct __packed { 130 uint32_t num_queues; 131 uint8_t queue_type; 132 uint8_t reserved[3]; 133 } t263; 134 135 struct __packed { 136 uint32_t fce_trace_size; 137 uint64_t write_pointer; 138 uint64_t base_pointer; 139 uint32_t fce_enable_mb0; 140 uint32_t fce_enable_mb2; 141 uint32_t fce_enable_mb3; 142 uint32_t fce_enable_mb4; 143 uint32_t fce_enable_mb5; 144 uint32_t fce_enable_mb6; 145 } t264; 146 147 struct __packed { 148 } t265; 149 150 struct __packed { 151 } t266; 152 153 struct __packed { 154 uint8_t pci_offset; 155 uint8_t reserved[3]; 156 uint32_t data; 157 } t267; 158 159 struct __packed { 160 uint8_t buf_type; 161 uint8_t reserved[3]; 162 uint32_t buf_size; 163 uint64_t start_addr; 164 } t268; 165 166 struct __packed { 167 uint32_t scratch_size; 168 } t269; 169 170 struct __packed { 171 uint32_t addr; 172 uint32_t count; 173 } t270; 174 175 struct __packed { 176 uint32_t addr; 177 uint32_t data; 178 } t271; 179 180 struct __packed { 181 uint32_t addr; 182 uint32_t count; 183 } t272; 184 185 struct __packed { 186 uint32_t addr; 187 uint32_t count; 188 } t273; 189 }; 190 }; 191 192 #define T262_RAM_AREA_CRITICAL_RAM 1 193 #define T262_RAM_AREA_EXTERNAL_RAM 2 194 #define T262_RAM_AREA_SHARED_RAM 3 195 #define T262_RAM_AREA_DDR_RAM 4 196 197 #define T263_QUEUE_TYPE_REQ 1 198 #define T263_QUEUE_TYPE_RSP 2 199 #define T263_QUEUE_TYPE_ATIO 3 200 201 #define T268_BUF_TYPE_EXTD_TRACE 1 202 #define T268_BUF_TYPE_EXCH_BUFOFF 2 203 #define T268_BUF_TYPE_EXTD_LOGIN 3 204 205 #endif 206