1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 #include "qla_tmpl.h" 9 10 /* note default template is in big endian */ 11 static const uint32_t ql27xx_fwdt_default_template[] = { 12 0x63000000, 0xa4000000, 0x7c050000, 0x00000000, 13 0x30000000, 0x01000000, 0x00000000, 0xc0406eb4, 14 0x00000000, 0x00000000, 0x00000000, 0x00000000, 15 0x00000000, 0x00000000, 0x00000000, 0x00000000, 16 0x00000000, 0x00000000, 0x00000000, 0x00000000, 17 0x00000000, 0x00000000, 0x00000000, 0x00000000, 18 0x00000000, 0x00000000, 0x00000000, 0x00000000, 19 0x00000000, 0x00000000, 0x00000000, 0x00000000, 20 0x00000000, 0x00000000, 0x00000000, 0x00000000, 21 0x00000000, 0x00000000, 0x00000000, 0x00000000, 22 0x00000000, 0x04010000, 0x14000000, 0x00000000, 23 0x02000000, 0x44000000, 0x09010000, 0x10000000, 24 0x00000000, 0x02000000, 0x01010000, 0x1c000000, 25 0x00000000, 0x02000000, 0x00600000, 0x00000000, 26 0xc0000000, 0x01010000, 0x1c000000, 0x00000000, 27 0x02000000, 0x00600000, 0x00000000, 0xcc000000, 28 0x01010000, 0x1c000000, 0x00000000, 0x02000000, 29 0x10600000, 0x00000000, 0xd4000000, 0x01010000, 30 0x1c000000, 0x00000000, 0x02000000, 0x700f0000, 31 0x00000060, 0xf0000000, 0x00010000, 0x18000000, 32 0x00000000, 0x02000000, 0x00700000, 0x041000c0, 33 0x00010000, 0x18000000, 0x00000000, 0x02000000, 34 0x10700000, 0x041000c0, 0x00010000, 0x18000000, 35 0x00000000, 0x02000000, 0x40700000, 0x041000c0, 36 0x01010000, 0x1c000000, 0x00000000, 0x02000000, 37 0x007c0000, 0x01000000, 0xc0000000, 0x00010000, 38 0x18000000, 0x00000000, 0x02000000, 0x007c0000, 39 0x040300c4, 0x00010000, 0x18000000, 0x00000000, 40 0x02000000, 0x007c0000, 0x040100c0, 0x01010000, 41 0x1c000000, 0x00000000, 0x02000000, 0x007c0000, 42 0x00000000, 0xc0000000, 0x00010000, 0x18000000, 43 0x00000000, 0x02000000, 0x007c0000, 0x04200000, 44 0x0b010000, 0x18000000, 0x00000000, 0x02000000, 45 0x0c000000, 0x00000000, 0x02010000, 0x20000000, 46 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 47 0xf0000000, 0x000000b0, 0x02010000, 0x20000000, 48 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 49 0xf0000000, 0x000010b0, 0x02010000, 0x20000000, 50 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 51 0xf0000000, 0x000020b0, 0x02010000, 0x20000000, 52 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 53 0xf0000000, 0x000030b0, 0x02010000, 0x20000000, 54 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 55 0xf0000000, 0x000040b0, 0x02010000, 0x20000000, 56 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 57 0xf0000000, 0x000050b0, 0x02010000, 0x20000000, 58 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 59 0xf0000000, 0x000060b0, 0x02010000, 0x20000000, 60 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 61 0xf0000000, 0x000070b0, 0x02010000, 0x20000000, 62 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 63 0xf0000000, 0x000080b0, 0x02010000, 0x20000000, 64 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 65 0xf0000000, 0x000090b0, 0x02010000, 0x20000000, 66 0x00000000, 0x02000000, 0x700f0000, 0x040100fc, 67 0xf0000000, 0x0000a0b0, 0x00010000, 0x18000000, 68 0x00000000, 0x02000000, 0x0a000000, 0x040100c0, 69 0x00010000, 0x18000000, 0x00000000, 0x02000000, 70 0x0a000000, 0x04200080, 0x00010000, 0x18000000, 71 0x00000000, 0x02000000, 0x00be0000, 0x041000c0, 72 0x00010000, 0x18000000, 0x00000000, 0x02000000, 73 0x10be0000, 0x041000c0, 0x00010000, 0x18000000, 74 0x00000000, 0x02000000, 0x20be0000, 0x041000c0, 75 0x00010000, 0x18000000, 0x00000000, 0x02000000, 76 0x30be0000, 0x041000c0, 0x00010000, 0x18000000, 77 0x00000000, 0x02000000, 0x00b00000, 0x041000c0, 78 0x00010000, 0x18000000, 0x00000000, 0x02000000, 79 0x10b00000, 0x041000c0, 0x00010000, 0x18000000, 80 0x00000000, 0x02000000, 0x20b00000, 0x041000c0, 81 0x00010000, 0x18000000, 0x00000000, 0x02000000, 82 0x30b00000, 0x041000c0, 0x00010000, 0x18000000, 83 0x00000000, 0x02000000, 0x00300000, 0x041000c0, 84 0x00010000, 0x18000000, 0x00000000, 0x02000000, 85 0x10300000, 0x041000c0, 0x00010000, 0x18000000, 86 0x00000000, 0x02000000, 0x20300000, 0x041000c0, 87 0x00010000, 0x18000000, 0x00000000, 0x02000000, 88 0x30300000, 0x041000c0, 0x0a010000, 0x10000000, 89 0x00000000, 0x02000000, 0x06010000, 0x1c000000, 90 0x00000000, 0x02000000, 0x01000000, 0x00000200, 91 0xff230200, 0x06010000, 0x1c000000, 0x00000000, 92 0x02000000, 0x02000000, 0x00001000, 0x00000000, 93 0x07010000, 0x18000000, 0x00000000, 0x02000000, 94 0x00000000, 0x01000000, 0x07010000, 0x18000000, 95 0x00000000, 0x02000000, 0x00000000, 0x02000000, 96 0x07010000, 0x18000000, 0x00000000, 0x02000000, 97 0x00000000, 0x03000000, 0x0d010000, 0x14000000, 98 0x00000000, 0x02000000, 0x00000000, 0xff000000, 99 0x10000000, 0x00000000, 0x00000080, 100 }; 101 102 static inline void __iomem * 103 qla27xx_isp_reg(struct scsi_qla_host *vha) 104 { 105 return &vha->hw->iobase->isp24; 106 } 107 108 static inline void 109 qla27xx_insert16(uint16_t value, void *buf, ulong *len) 110 { 111 if (buf) { 112 buf += *len; 113 *(__le16 *)buf = cpu_to_le16(value); 114 } 115 *len += sizeof(value); 116 } 117 118 static inline void 119 qla27xx_insert32(uint32_t value, void *buf, ulong *len) 120 { 121 if (buf) { 122 buf += *len; 123 *(__le32 *)buf = cpu_to_le32(value); 124 } 125 *len += sizeof(value); 126 } 127 128 static inline void 129 qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len) 130 { 131 132 if (buf && mem && size) { 133 buf += *len; 134 memcpy(buf, mem, size); 135 } 136 *len += size; 137 } 138 139 static inline void 140 qla27xx_read8(void __iomem *window, void *buf, ulong *len) 141 { 142 uint8_t value = ~0; 143 144 if (buf) { 145 value = RD_REG_BYTE(window); 146 } 147 qla27xx_insert32(value, buf, len); 148 } 149 150 static inline void 151 qla27xx_read16(void __iomem *window, void *buf, ulong *len) 152 { 153 uint16_t value = ~0; 154 155 if (buf) { 156 value = RD_REG_WORD(window); 157 } 158 qla27xx_insert32(value, buf, len); 159 } 160 161 static inline void 162 qla27xx_read32(void __iomem *window, void *buf, ulong *len) 163 { 164 uint32_t value = ~0; 165 166 if (buf) { 167 value = RD_REG_DWORD(window); 168 } 169 qla27xx_insert32(value, buf, len); 170 } 171 172 static inline void (*qla27xx_read_vector(uint width))(void __iomem*, void *, ulong *) 173 { 174 return 175 (width == 1) ? qla27xx_read8 : 176 (width == 2) ? qla27xx_read16 : 177 qla27xx_read32; 178 } 179 180 static inline void 181 qla27xx_read_reg(__iomem struct device_reg_24xx *reg, 182 uint offset, void *buf, ulong *len) 183 { 184 void __iomem *window = (void __iomem *)reg + offset; 185 186 qla27xx_read32(window, buf, len); 187 } 188 189 static inline void 190 qla27xx_write_reg(__iomem struct device_reg_24xx *reg, 191 uint offset, uint32_t data, void *buf) 192 { 193 __iomem void *window = (void __iomem *)reg + offset; 194 195 if (buf) { 196 WRT_REG_DWORD(window, data); 197 } 198 } 199 200 static inline void 201 qla27xx_read_window(__iomem struct device_reg_24xx *reg, 202 uint32_t addr, uint offset, uint count, uint width, void *buf, 203 ulong *len) 204 { 205 void __iomem *window = (void __iomem *)reg + offset; 206 void (*readn)(void __iomem*, void *, ulong *) = qla27xx_read_vector(width); 207 208 qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf); 209 while (count--) { 210 qla27xx_insert32(addr, buf, len); 211 readn(window, buf, len); 212 window += width; 213 addr++; 214 } 215 } 216 217 static inline void 218 qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf) 219 { 220 if (buf) 221 ent->hdr.driver_flags |= DRIVER_FLAG_SKIP_ENTRY; 222 ql_dbg(ql_dbg_misc + ql_dbg_verbose, NULL, 0xd011, 223 "Skipping entry %d\n", ent->hdr.entry_type); 224 } 225 226 static int 227 qla27xx_fwdt_entry_t0(struct scsi_qla_host *vha, 228 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 229 { 230 ql_dbg(ql_dbg_misc, vha, 0xd100, 231 "%s: nop [%lx]\n", __func__, *len); 232 qla27xx_skip_entry(ent, buf); 233 234 return false; 235 } 236 237 static int 238 qla27xx_fwdt_entry_t255(struct scsi_qla_host *vha, 239 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 240 { 241 ql_dbg(ql_dbg_misc, vha, 0xd1ff, 242 "%s: end [%lx]\n", __func__, *len); 243 qla27xx_skip_entry(ent, buf); 244 245 /* terminate */ 246 return true; 247 } 248 249 static int 250 qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha, 251 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 252 { 253 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha); 254 255 ql_dbg(ql_dbg_misc, vha, 0xd200, 256 "%s: rdio t1 [%lx]\n", __func__, *len); 257 qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset, 258 ent->t256.reg_count, ent->t256.reg_width, buf, len); 259 260 return false; 261 } 262 263 static int 264 qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha, 265 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 266 { 267 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha); 268 269 ql_dbg(ql_dbg_misc, vha, 0xd201, 270 "%s: wrio t1 [%lx]\n", __func__, *len); 271 qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf); 272 qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf); 273 274 return false; 275 } 276 277 static int 278 qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha, 279 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 280 { 281 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha); 282 283 ql_dbg(ql_dbg_misc, vha, 0xd202, 284 "%s: rdio t2 [%lx]\n", __func__, *len); 285 qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf); 286 qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset, 287 ent->t258.reg_count, ent->t258.reg_width, buf, len); 288 289 return false; 290 } 291 292 static int 293 qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha, 294 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 295 { 296 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha); 297 298 ql_dbg(ql_dbg_misc, vha, 0xd203, 299 "%s: wrio t2 [%lx]\n", __func__, *len); 300 qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf); 301 qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf); 302 qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf); 303 304 return false; 305 } 306 307 static int 308 qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha, 309 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 310 { 311 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha); 312 313 ql_dbg(ql_dbg_misc, vha, 0xd204, 314 "%s: rdpci [%lx]\n", __func__, *len); 315 qla27xx_insert32(ent->t260.pci_offset, buf, len); 316 qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len); 317 318 return false; 319 } 320 321 static int 322 qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha, 323 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 324 { 325 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha); 326 327 ql_dbg(ql_dbg_misc, vha, 0xd205, 328 "%s: wrpci [%lx]\n", __func__, *len); 329 qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf); 330 331 return false; 332 } 333 334 static int 335 qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha, 336 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 337 { 338 ulong dwords; 339 ulong start; 340 ulong end; 341 342 ql_dbg(ql_dbg_misc, vha, 0xd206, 343 "%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len); 344 start = ent->t262.start_addr; 345 end = ent->t262.end_addr; 346 347 if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) { 348 ; 349 } else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) { 350 end = vha->hw->fw_memory_size; 351 if (buf) 352 ent->t262.end_addr = end; 353 } else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) { 354 start = vha->hw->fw_shared_ram_start; 355 end = vha->hw->fw_shared_ram_end; 356 if (buf) { 357 ent->t262.start_addr = start; 358 ent->t262.end_addr = end; 359 } 360 } else if (ent->t262.ram_area == T262_RAM_AREA_DDR_RAM) { 361 start = vha->hw->fw_ddr_ram_start; 362 end = vha->hw->fw_ddr_ram_end; 363 if (buf) { 364 ent->t262.start_addr = start; 365 ent->t262.end_addr = end; 366 } 367 } else { 368 ql_dbg(ql_dbg_misc, vha, 0xd022, 369 "%s: unknown area %x\n", __func__, ent->t262.ram_area); 370 qla27xx_skip_entry(ent, buf); 371 goto done; 372 } 373 374 if (end <= start || start == 0 || end == 0) { 375 ql_dbg(ql_dbg_misc, vha, 0xd023, 376 "%s: unusable range (start=%x end=%x)\n", __func__, 377 ent->t262.end_addr, ent->t262.start_addr); 378 qla27xx_skip_entry(ent, buf); 379 goto done; 380 } 381 382 dwords = end - start + 1; 383 if (buf) { 384 buf += *len; 385 qla24xx_dump_ram(vha->hw, start, buf, dwords, &buf); 386 } 387 *len += dwords * sizeof(uint32_t); 388 done: 389 return false; 390 } 391 392 static int 393 qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha, 394 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 395 { 396 uint count = 0; 397 uint i; 398 uint length; 399 400 ql_dbg(ql_dbg_misc, vha, 0xd207, 401 "%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len); 402 if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) { 403 for (i = 0; i < vha->hw->max_req_queues; i++) { 404 struct req_que *req = vha->hw->req_q_map[i]; 405 406 if (!test_bit(i, vha->hw->req_qid_map)) 407 continue; 408 409 if (req || !buf) { 410 length = req ? 411 req->length : REQUEST_ENTRY_CNT_24XX; 412 qla27xx_insert16(i, buf, len); 413 qla27xx_insert16(length, buf, len); 414 qla27xx_insertbuf(req ? req->ring : NULL, 415 length * sizeof(*req->ring), buf, len); 416 count++; 417 } 418 } 419 } else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) { 420 for (i = 0; i < vha->hw->max_rsp_queues; i++) { 421 struct rsp_que *rsp = vha->hw->rsp_q_map[i]; 422 423 if (!test_bit(i, vha->hw->rsp_qid_map)) 424 continue; 425 426 if (rsp || !buf) { 427 length = rsp ? 428 rsp->length : RESPONSE_ENTRY_CNT_MQ; 429 qla27xx_insert16(i, buf, len); 430 qla27xx_insert16(length, buf, len); 431 qla27xx_insertbuf(rsp ? rsp->ring : NULL, 432 length * sizeof(*rsp->ring), buf, len); 433 count++; 434 } 435 } 436 } else { 437 ql_dbg(ql_dbg_misc, vha, 0xd026, 438 "%s: unknown queue %x\n", __func__, ent->t263.queue_type); 439 qla27xx_skip_entry(ent, buf); 440 } 441 442 if (buf) 443 ent->t263.num_queues = count; 444 445 return false; 446 } 447 448 static int 449 qla27xx_fwdt_entry_t264(struct scsi_qla_host *vha, 450 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 451 { 452 ql_dbg(ql_dbg_misc, vha, 0xd208, 453 "%s: getfce [%lx]\n", __func__, *len); 454 if (vha->hw->fce) { 455 if (buf) { 456 ent->t264.fce_trace_size = FCE_SIZE; 457 ent->t264.write_pointer = vha->hw->fce_wr; 458 ent->t264.base_pointer = vha->hw->fce_dma; 459 ent->t264.fce_enable_mb0 = vha->hw->fce_mb[0]; 460 ent->t264.fce_enable_mb2 = vha->hw->fce_mb[2]; 461 ent->t264.fce_enable_mb3 = vha->hw->fce_mb[3]; 462 ent->t264.fce_enable_mb4 = vha->hw->fce_mb[4]; 463 ent->t264.fce_enable_mb5 = vha->hw->fce_mb[5]; 464 ent->t264.fce_enable_mb6 = vha->hw->fce_mb[6]; 465 } 466 qla27xx_insertbuf(vha->hw->fce, FCE_SIZE, buf, len); 467 } else { 468 ql_dbg(ql_dbg_misc, vha, 0xd027, 469 "%s: missing fce\n", __func__); 470 qla27xx_skip_entry(ent, buf); 471 } 472 473 return false; 474 } 475 476 static int 477 qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha, 478 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 479 { 480 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha); 481 482 ql_dbg(ql_dbg_misc, vha, 0xd209, 483 "%s: pause risc [%lx]\n", __func__, *len); 484 if (buf) 485 qla24xx_pause_risc(reg, vha->hw); 486 487 return false; 488 } 489 490 static int 491 qla27xx_fwdt_entry_t266(struct scsi_qla_host *vha, 492 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 493 { 494 ql_dbg(ql_dbg_misc, vha, 0xd20a, 495 "%s: reset risc [%lx]\n", __func__, *len); 496 if (buf) 497 qla24xx_soft_reset(vha->hw); 498 499 return false; 500 } 501 502 static int 503 qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha, 504 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 505 { 506 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha); 507 508 ql_dbg(ql_dbg_misc, vha, 0xd20b, 509 "%s: dis intr [%lx]\n", __func__, *len); 510 qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf); 511 512 return false; 513 } 514 515 static int 516 qla27xx_fwdt_entry_t268(struct scsi_qla_host *vha, 517 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 518 { 519 ql_dbg(ql_dbg_misc, vha, 0xd20c, 520 "%s: gethb(%x) [%lx]\n", __func__, ent->t268.buf_type, *len); 521 if (ent->t268.buf_type == T268_BUF_TYPE_EXTD_TRACE) { 522 if (vha->hw->eft) { 523 if (buf) { 524 ent->t268.buf_size = EFT_SIZE; 525 ent->t268.start_addr = vha->hw->eft_dma; 526 } 527 qla27xx_insertbuf(vha->hw->eft, EFT_SIZE, buf, len); 528 } else { 529 ql_dbg(ql_dbg_misc, vha, 0xd028, 530 "%s: missing eft\n", __func__); 531 qla27xx_skip_entry(ent, buf); 532 } 533 } else { 534 ql_dbg(ql_dbg_misc, vha, 0xd02b, 535 "%s: unknown buffer %x\n", __func__, ent->t268.buf_type); 536 qla27xx_skip_entry(ent, buf); 537 } 538 539 return false; 540 } 541 542 static int 543 qla27xx_fwdt_entry_t269(struct scsi_qla_host *vha, 544 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 545 { 546 ql_dbg(ql_dbg_misc, vha, 0xd20d, 547 "%s: scratch [%lx]\n", __func__, *len); 548 qla27xx_insert32(0xaaaaaaaa, buf, len); 549 qla27xx_insert32(0xbbbbbbbb, buf, len); 550 qla27xx_insert32(0xcccccccc, buf, len); 551 qla27xx_insert32(0xdddddddd, buf, len); 552 qla27xx_insert32(*len + sizeof(uint32_t), buf, len); 553 if (buf) 554 ent->t269.scratch_size = 5 * sizeof(uint32_t); 555 556 return false; 557 } 558 559 static int 560 qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha, 561 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 562 { 563 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha); 564 ulong dwords = ent->t270.count; 565 ulong addr = ent->t270.addr; 566 567 ql_dbg(ql_dbg_misc, vha, 0xd20e, 568 "%s: rdremreg [%lx]\n", __func__, *len); 569 qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf); 570 while (dwords--) { 571 qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf); 572 qla27xx_insert32(addr, buf, len); 573 qla27xx_read_reg(reg, 0xc4, buf, len); 574 addr += sizeof(uint32_t); 575 } 576 577 return false; 578 } 579 580 static int 581 qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha, 582 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 583 { 584 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha); 585 ulong addr = ent->t271.addr; 586 ulong data = ent->t271.data; 587 588 ql_dbg(ql_dbg_misc, vha, 0xd20f, 589 "%s: wrremreg [%lx]\n", __func__, *len); 590 qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf); 591 qla27xx_write_reg(reg, 0xc4, data, buf); 592 qla27xx_write_reg(reg, 0xc0, addr, buf); 593 594 return false; 595 } 596 597 static int 598 qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha, 599 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 600 { 601 ulong dwords = ent->t272.count; 602 ulong start = ent->t272.addr; 603 604 ql_dbg(ql_dbg_misc, vha, 0xd210, 605 "%s: rdremram [%lx]\n", __func__, *len); 606 if (buf) { 607 ql_dbg(ql_dbg_misc, vha, 0xd02c, 608 "%s: @%lx -> (%lx dwords)\n", __func__, start, dwords); 609 buf += *len; 610 qla27xx_dump_mpi_ram(vha->hw, start, buf, dwords, &buf); 611 } 612 *len += dwords * sizeof(uint32_t); 613 614 return false; 615 } 616 617 static int 618 qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha, 619 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 620 { 621 ulong dwords = ent->t273.count; 622 ulong addr = ent->t273.addr; 623 uint32_t value; 624 625 ql_dbg(ql_dbg_misc, vha, 0xd211, 626 "%s: pcicfg [%lx]\n", __func__, *len); 627 while (dwords--) { 628 value = ~0; 629 if (pci_read_config_dword(vha->hw->pdev, addr, &value)) 630 ql_dbg(ql_dbg_misc, vha, 0xd02d, 631 "%s: failed pcicfg read at %lx\n", __func__, addr); 632 qla27xx_insert32(addr, buf, len); 633 qla27xx_insert32(value, buf, len); 634 addr += sizeof(uint32_t); 635 } 636 637 return false; 638 } 639 640 static int 641 qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha, 642 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 643 { 644 uint count = 0; 645 uint i; 646 647 ql_dbg(ql_dbg_misc, vha, 0xd212, 648 "%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len); 649 if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) { 650 for (i = 0; i < vha->hw->max_req_queues; i++) { 651 struct req_que *req = vha->hw->req_q_map[i]; 652 653 if (!test_bit(i, vha->hw->req_qid_map)) 654 continue; 655 656 if (req || !buf) { 657 qla27xx_insert16(i, buf, len); 658 qla27xx_insert16(1, buf, len); 659 qla27xx_insert32(req && req->out_ptr ? 660 *req->out_ptr : 0, buf, len); 661 count++; 662 } 663 } 664 } else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) { 665 for (i = 0; i < vha->hw->max_rsp_queues; i++) { 666 struct rsp_que *rsp = vha->hw->rsp_q_map[i]; 667 668 if (!test_bit(i, vha->hw->rsp_qid_map)) 669 continue; 670 671 if (rsp || !buf) { 672 qla27xx_insert16(i, buf, len); 673 qla27xx_insert16(1, buf, len); 674 qla27xx_insert32(rsp && rsp->in_ptr ? 675 *rsp->in_ptr : 0, buf, len); 676 count++; 677 } 678 } 679 } else { 680 ql_dbg(ql_dbg_misc, vha, 0xd02f, 681 "%s: unknown queue %x\n", __func__, ent->t274.queue_type); 682 qla27xx_skip_entry(ent, buf); 683 } 684 685 if (buf) 686 ent->t274.num_queues = count; 687 688 if (!count) 689 qla27xx_skip_entry(ent, buf); 690 691 return false; 692 } 693 694 static int 695 qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha, 696 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 697 { 698 ulong offset = offsetof(typeof(*ent), t275.buffer); 699 700 ql_dbg(ql_dbg_misc, vha, 0xd213, 701 "%s: buffer(%x) [%lx]\n", __func__, ent->t275.length, *len); 702 if (!ent->t275.length) { 703 ql_dbg(ql_dbg_misc, vha, 0xd020, 704 "%s: buffer zero length\n", __func__); 705 qla27xx_skip_entry(ent, buf); 706 goto done; 707 } 708 if (offset + ent->t275.length > ent->hdr.entry_size) { 709 ql_dbg(ql_dbg_misc, vha, 0xd030, 710 "%s: buffer overflow\n", __func__); 711 qla27xx_skip_entry(ent, buf); 712 goto done; 713 } 714 715 qla27xx_insertbuf(ent->t275.buffer, ent->t275.length, buf, len); 716 done: 717 return false; 718 } 719 720 static int 721 qla27xx_fwdt_entry_other(struct scsi_qla_host *vha, 722 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len) 723 { 724 ql_dbg(ql_dbg_misc, vha, 0xd2ff, 725 "%s: type %x [%lx]\n", __func__, ent->hdr.entry_type, *len); 726 qla27xx_skip_entry(ent, buf); 727 728 return false; 729 } 730 731 struct qla27xx_fwdt_entry_call { 732 uint type; 733 int (*call)( 734 struct scsi_qla_host *, 735 struct qla27xx_fwdt_entry *, 736 void *, 737 ulong *); 738 }; 739 740 static struct qla27xx_fwdt_entry_call ql27xx_fwdt_entry_call_list[] = { 741 { ENTRY_TYPE_NOP , qla27xx_fwdt_entry_t0 } , 742 { ENTRY_TYPE_TMP_END , qla27xx_fwdt_entry_t255 } , 743 { ENTRY_TYPE_RD_IOB_T1 , qla27xx_fwdt_entry_t256 } , 744 { ENTRY_TYPE_WR_IOB_T1 , qla27xx_fwdt_entry_t257 } , 745 { ENTRY_TYPE_RD_IOB_T2 , qla27xx_fwdt_entry_t258 } , 746 { ENTRY_TYPE_WR_IOB_T2 , qla27xx_fwdt_entry_t259 } , 747 { ENTRY_TYPE_RD_PCI , qla27xx_fwdt_entry_t260 } , 748 { ENTRY_TYPE_WR_PCI , qla27xx_fwdt_entry_t261 } , 749 { ENTRY_TYPE_RD_RAM , qla27xx_fwdt_entry_t262 } , 750 { ENTRY_TYPE_GET_QUEUE , qla27xx_fwdt_entry_t263 } , 751 { ENTRY_TYPE_GET_FCE , qla27xx_fwdt_entry_t264 } , 752 { ENTRY_TYPE_PSE_RISC , qla27xx_fwdt_entry_t265 } , 753 { ENTRY_TYPE_RST_RISC , qla27xx_fwdt_entry_t266 } , 754 { ENTRY_TYPE_DIS_INTR , qla27xx_fwdt_entry_t267 } , 755 { ENTRY_TYPE_GET_HBUF , qla27xx_fwdt_entry_t268 } , 756 { ENTRY_TYPE_SCRATCH , qla27xx_fwdt_entry_t269 } , 757 { ENTRY_TYPE_RDREMREG , qla27xx_fwdt_entry_t270 } , 758 { ENTRY_TYPE_WRREMREG , qla27xx_fwdt_entry_t271 } , 759 { ENTRY_TYPE_RDREMRAM , qla27xx_fwdt_entry_t272 } , 760 { ENTRY_TYPE_PCICFG , qla27xx_fwdt_entry_t273 } , 761 { ENTRY_TYPE_GET_SHADOW , qla27xx_fwdt_entry_t274 } , 762 { ENTRY_TYPE_WRITE_BUF , qla27xx_fwdt_entry_t275 } , 763 { -1 , qla27xx_fwdt_entry_other } 764 }; 765 766 static inline int (*qla27xx_find_entry(uint type)) 767 (struct scsi_qla_host *, struct qla27xx_fwdt_entry *, void *, ulong *) 768 { 769 struct qla27xx_fwdt_entry_call *list = ql27xx_fwdt_entry_call_list; 770 771 while (list->type < type) 772 list++; 773 774 if (list->type == type) 775 return list->call; 776 return qla27xx_fwdt_entry_other; 777 } 778 779 static inline void * 780 qla27xx_next_entry(void *p) 781 { 782 struct qla27xx_fwdt_entry *ent = p; 783 784 return p + ent->hdr.entry_size; 785 } 786 787 static void 788 qla27xx_walk_template(struct scsi_qla_host *vha, 789 struct qla27xx_fwdt_template *tmp, void *buf, ulong *len) 790 { 791 struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset; 792 ulong count = tmp->entry_count; 793 794 ql_dbg(ql_dbg_misc, vha, 0xd01a, 795 "%s: entry count %lx\n", __func__, count); 796 while (count--) { 797 if (qla27xx_find_entry(ent->hdr.entry_type)(vha, ent, buf, len)) 798 break; 799 ent = qla27xx_next_entry(ent); 800 } 801 802 if (count) 803 ql_dbg(ql_dbg_misc, vha, 0xd018, 804 "%s: residual count (%lx)\n", __func__, count); 805 806 if (ent->hdr.entry_type != ENTRY_TYPE_TMP_END) 807 ql_dbg(ql_dbg_misc, vha, 0xd019, 808 "%s: missing end (%lx)\n", __func__, count); 809 810 ql_dbg(ql_dbg_misc, vha, 0xd01b, 811 "%s: len=%lx\n", __func__, *len); 812 813 if (buf) { 814 ql_log(ql_log_warn, vha, 0xd015, 815 "Firmware dump saved to temp buffer (%ld/%p)\n", 816 vha->host_no, vha->hw->fw_dump); 817 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 818 } 819 } 820 821 static void 822 qla27xx_time_stamp(struct qla27xx_fwdt_template *tmp) 823 { 824 tmp->capture_timestamp = jiffies; 825 } 826 827 static void 828 qla27xx_driver_info(struct qla27xx_fwdt_template *tmp) 829 { 830 uint8_t v[] = { 0, 0, 0, 0, 0, 0 }; 831 832 sscanf(qla2x00_version_str, "%hhu.%hhu.%hhu.%hhu.%hhu.%hhu", 833 v+0, v+1, v+2, v+3, v+4, v+5); 834 835 tmp->driver_info[0] = v[3] << 24 | v[2] << 16 | v[1] << 8 | v[0]; 836 tmp->driver_info[1] = v[5] << 8 | v[4]; 837 tmp->driver_info[2] = 0x12345678; 838 } 839 840 static void 841 qla27xx_firmware_info(struct qla27xx_fwdt_template *tmp, 842 struct scsi_qla_host *vha) 843 { 844 tmp->firmware_version[0] = vha->hw->fw_major_version; 845 tmp->firmware_version[1] = vha->hw->fw_minor_version; 846 tmp->firmware_version[2] = vha->hw->fw_subminor_version; 847 tmp->firmware_version[3] = 848 vha->hw->fw_attributes_h << 16 | vha->hw->fw_attributes; 849 tmp->firmware_version[4] = 850 vha->hw->fw_attributes_ext[1] << 16 | vha->hw->fw_attributes_ext[0]; 851 } 852 853 static void 854 ql27xx_edit_template(struct scsi_qla_host *vha, 855 struct qla27xx_fwdt_template *tmp) 856 { 857 qla27xx_time_stamp(tmp); 858 qla27xx_driver_info(tmp); 859 qla27xx_firmware_info(tmp, vha); 860 } 861 862 static inline uint32_t 863 qla27xx_template_checksum(void *p, ulong size) 864 { 865 uint32_t *buf = p; 866 uint64_t sum = 0; 867 868 size /= sizeof(*buf); 869 870 while (size--) 871 sum += *buf++; 872 873 sum = (sum & 0xffffffff) + (sum >> 32); 874 875 return ~sum; 876 } 877 878 static inline int 879 qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp) 880 { 881 return qla27xx_template_checksum(tmp, tmp->template_size) == 0; 882 } 883 884 static inline int 885 qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp) 886 { 887 return tmp->template_type == TEMPLATE_TYPE_FWDUMP; 888 } 889 890 static void 891 qla27xx_execute_fwdt_template(struct scsi_qla_host *vha) 892 { 893 struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template; 894 ulong len; 895 896 if (qla27xx_fwdt_template_valid(tmp)) { 897 len = tmp->template_size; 898 tmp = memcpy(vha->hw->fw_dump, tmp, len); 899 ql27xx_edit_template(vha, tmp); 900 qla27xx_walk_template(vha, tmp, tmp, &len); 901 vha->hw->fw_dump_len = len; 902 vha->hw->fw_dumped = 1; 903 } 904 } 905 906 ulong 907 qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha) 908 { 909 struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template; 910 ulong len = 0; 911 912 if (qla27xx_fwdt_template_valid(tmp)) { 913 len = tmp->template_size; 914 qla27xx_walk_template(vha, tmp, NULL, &len); 915 } 916 917 return len; 918 } 919 920 ulong 921 qla27xx_fwdt_template_size(void *p) 922 { 923 struct qla27xx_fwdt_template *tmp = p; 924 925 return tmp->template_size; 926 } 927 928 ulong 929 qla27xx_fwdt_template_default_size(void) 930 { 931 return sizeof(ql27xx_fwdt_default_template); 932 } 933 934 const void * 935 qla27xx_fwdt_template_default(void) 936 { 937 return ql27xx_fwdt_default_template; 938 } 939 940 int 941 qla27xx_fwdt_template_valid(void *p) 942 { 943 struct qla27xx_fwdt_template *tmp = p; 944 945 if (!qla27xx_verify_template_header(tmp)) { 946 ql_log(ql_log_warn, NULL, 0xd01c, 947 "%s: template type %x\n", __func__, tmp->template_type); 948 return false; 949 } 950 951 if (!qla27xx_verify_template_checksum(tmp)) { 952 ql_log(ql_log_warn, NULL, 0xd01d, 953 "%s: failed template checksum\n", __func__); 954 return false; 955 } 956 957 return true; 958 } 959 960 void 961 qla27xx_fwdump(scsi_qla_host_t *vha, int hardware_locked) 962 { 963 ulong flags = 0; 964 965 #ifndef __CHECKER__ 966 if (!hardware_locked) 967 spin_lock_irqsave(&vha->hw->hardware_lock, flags); 968 #endif 969 970 if (!vha->hw->fw_dump) 971 ql_log(ql_log_warn, vha, 0xd01e, "fwdump buffer missing.\n"); 972 else if (!vha->hw->fw_dump_template) 973 ql_log(ql_log_warn, vha, 0xd01f, "fwdump template missing.\n"); 974 else if (vha->hw->fw_dumped) 975 ql_log(ql_log_warn, vha, 0xd300, 976 "Firmware has been previously dumped (%p)," 977 " -- ignoring request\n", vha->hw->fw_dump); 978 else 979 qla27xx_execute_fwdt_template(vha); 980 981 #ifndef __CHECKER__ 982 if (!hardware_locked) 983 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags); 984 #endif 985 } 986