1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2005 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 #include <asm/uaccess.h> 11 12 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t); 13 static void qla2x00_nv_deselect(scsi_qla_host_t *); 14 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t); 15 16 /* 17 * NVRAM support routines 18 */ 19 20 /** 21 * qla2x00_lock_nvram_access() - 22 * @ha: HA context 23 */ 24 void 25 qla2x00_lock_nvram_access(scsi_qla_host_t *ha) 26 { 27 uint16_t data; 28 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 29 30 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 31 data = RD_REG_WORD(®->nvram); 32 while (data & NVR_BUSY) { 33 udelay(100); 34 data = RD_REG_WORD(®->nvram); 35 } 36 37 /* Lock resource */ 38 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 39 RD_REG_WORD(®->u.isp2300.host_semaphore); 40 udelay(5); 41 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 42 while ((data & BIT_0) == 0) { 43 /* Lock failed */ 44 udelay(100); 45 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 46 RD_REG_WORD(®->u.isp2300.host_semaphore); 47 udelay(5); 48 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 49 } 50 } 51 } 52 53 /** 54 * qla2x00_unlock_nvram_access() - 55 * @ha: HA context 56 */ 57 void 58 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha) 59 { 60 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 61 62 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 63 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); 64 RD_REG_WORD(®->u.isp2300.host_semaphore); 65 } 66 } 67 68 /** 69 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 70 * request routine to get the word from NVRAM. 71 * @ha: HA context 72 * @addr: Address in NVRAM to read 73 * 74 * Returns the word read from nvram @addr. 75 */ 76 uint16_t 77 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr) 78 { 79 uint16_t data; 80 uint32_t nv_cmd; 81 82 nv_cmd = addr << 16; 83 nv_cmd |= NV_READ_OP; 84 data = qla2x00_nvram_request(ha, nv_cmd); 85 86 return (data); 87 } 88 89 /** 90 * qla2x00_write_nvram_word() - Write NVRAM data. 91 * @ha: HA context 92 * @addr: Address in NVRAM to write 93 * @data: word to program 94 */ 95 void 96 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data) 97 { 98 int count; 99 uint16_t word; 100 uint32_t nv_cmd, wait_cnt; 101 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 102 103 qla2x00_nv_write(ha, NVR_DATA_OUT); 104 qla2x00_nv_write(ha, 0); 105 qla2x00_nv_write(ha, 0); 106 107 for (word = 0; word < 8; word++) 108 qla2x00_nv_write(ha, NVR_DATA_OUT); 109 110 qla2x00_nv_deselect(ha); 111 112 /* Write data */ 113 nv_cmd = (addr << 16) | NV_WRITE_OP; 114 nv_cmd |= data; 115 nv_cmd <<= 5; 116 for (count = 0; count < 27; count++) { 117 if (nv_cmd & BIT_31) 118 qla2x00_nv_write(ha, NVR_DATA_OUT); 119 else 120 qla2x00_nv_write(ha, 0); 121 122 nv_cmd <<= 1; 123 } 124 125 qla2x00_nv_deselect(ha); 126 127 /* Wait for NVRAM to become ready */ 128 WRT_REG_WORD(®->nvram, NVR_SELECT); 129 RD_REG_WORD(®->nvram); /* PCI Posting. */ 130 wait_cnt = NVR_WAIT_CNT; 131 do { 132 if (!--wait_cnt) { 133 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n", 134 __func__, ha->host_no)); 135 break; 136 } 137 NVRAM_DELAY(); 138 word = RD_REG_WORD(®->nvram); 139 } while ((word & NVR_DATA_IN) == 0); 140 141 qla2x00_nv_deselect(ha); 142 143 /* Disable writes */ 144 qla2x00_nv_write(ha, NVR_DATA_OUT); 145 for (count = 0; count < 10; count++) 146 qla2x00_nv_write(ha, 0); 147 148 qla2x00_nv_deselect(ha); 149 } 150 151 static int 152 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data, 153 uint32_t tmo) 154 { 155 int ret, count; 156 uint16_t word; 157 uint32_t nv_cmd; 158 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 159 160 ret = QLA_SUCCESS; 161 162 qla2x00_nv_write(ha, NVR_DATA_OUT); 163 qla2x00_nv_write(ha, 0); 164 qla2x00_nv_write(ha, 0); 165 166 for (word = 0; word < 8; word++) 167 qla2x00_nv_write(ha, NVR_DATA_OUT); 168 169 qla2x00_nv_deselect(ha); 170 171 /* Write data */ 172 nv_cmd = (addr << 16) | NV_WRITE_OP; 173 nv_cmd |= data; 174 nv_cmd <<= 5; 175 for (count = 0; count < 27; count++) { 176 if (nv_cmd & BIT_31) 177 qla2x00_nv_write(ha, NVR_DATA_OUT); 178 else 179 qla2x00_nv_write(ha, 0); 180 181 nv_cmd <<= 1; 182 } 183 184 qla2x00_nv_deselect(ha); 185 186 /* Wait for NVRAM to become ready */ 187 WRT_REG_WORD(®->nvram, NVR_SELECT); 188 RD_REG_WORD(®->nvram); /* PCI Posting. */ 189 do { 190 NVRAM_DELAY(); 191 word = RD_REG_WORD(®->nvram); 192 if (!--tmo) { 193 ret = QLA_FUNCTION_FAILED; 194 break; 195 } 196 } while ((word & NVR_DATA_IN) == 0); 197 198 qla2x00_nv_deselect(ha); 199 200 /* Disable writes */ 201 qla2x00_nv_write(ha, NVR_DATA_OUT); 202 for (count = 0; count < 10; count++) 203 qla2x00_nv_write(ha, 0); 204 205 qla2x00_nv_deselect(ha); 206 207 return ret; 208 } 209 210 /** 211 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 212 * NVRAM. 213 * @ha: HA context 214 * @nv_cmd: NVRAM command 215 * 216 * Bit definitions for NVRAM command: 217 * 218 * Bit 26 = start bit 219 * Bit 25, 24 = opcode 220 * Bit 23-16 = address 221 * Bit 15-0 = write data 222 * 223 * Returns the word read from nvram @addr. 224 */ 225 static uint16_t 226 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd) 227 { 228 uint8_t cnt; 229 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 230 uint16_t data = 0; 231 uint16_t reg_data; 232 233 /* Send command to NVRAM. */ 234 nv_cmd <<= 5; 235 for (cnt = 0; cnt < 11; cnt++) { 236 if (nv_cmd & BIT_31) 237 qla2x00_nv_write(ha, NVR_DATA_OUT); 238 else 239 qla2x00_nv_write(ha, 0); 240 nv_cmd <<= 1; 241 } 242 243 /* Read data from NVRAM. */ 244 for (cnt = 0; cnt < 16; cnt++) { 245 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); 246 RD_REG_WORD(®->nvram); /* PCI Posting. */ 247 NVRAM_DELAY(); 248 data <<= 1; 249 reg_data = RD_REG_WORD(®->nvram); 250 if (reg_data & NVR_DATA_IN) 251 data |= BIT_0; 252 WRT_REG_WORD(®->nvram, NVR_SELECT); 253 RD_REG_WORD(®->nvram); /* PCI Posting. */ 254 NVRAM_DELAY(); 255 } 256 257 /* Deselect chip. */ 258 WRT_REG_WORD(®->nvram, NVR_DESELECT); 259 RD_REG_WORD(®->nvram); /* PCI Posting. */ 260 NVRAM_DELAY(); 261 262 return (data); 263 } 264 265 /** 266 * qla2x00_nv_write() - Clean NVRAM operations. 267 * @ha: HA context 268 */ 269 static void 270 qla2x00_nv_deselect(scsi_qla_host_t *ha) 271 { 272 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 273 274 WRT_REG_WORD(®->nvram, NVR_DESELECT); 275 RD_REG_WORD(®->nvram); /* PCI Posting. */ 276 NVRAM_DELAY(); 277 } 278 279 /** 280 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 281 * @ha: HA context 282 * @data: Serial interface selector 283 */ 284 static void 285 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data) 286 { 287 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 288 289 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 290 RD_REG_WORD(®->nvram); /* PCI Posting. */ 291 NVRAM_DELAY(); 292 WRT_REG_WORD(®->nvram, data | NVR_SELECT| NVR_CLOCK | 293 NVR_WRT_ENABLE); 294 RD_REG_WORD(®->nvram); /* PCI Posting. */ 295 NVRAM_DELAY(); 296 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 297 RD_REG_WORD(®->nvram); /* PCI Posting. */ 298 NVRAM_DELAY(); 299 } 300 301 /** 302 * qla2x00_clear_nvram_protection() - 303 * @ha: HA context 304 */ 305 static int 306 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha) 307 { 308 int ret, stat; 309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 310 uint32_t word, wait_cnt; 311 uint16_t wprot, wprot_old; 312 313 /* Clear NVRAM write protection. */ 314 ret = QLA_FUNCTION_FAILED; 315 316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 318 __constant_cpu_to_le16(0x1234), 100000); 319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 320 if (stat != QLA_SUCCESS || wprot != 0x1234) { 321 /* Write enable. */ 322 qla2x00_nv_write(ha, NVR_DATA_OUT); 323 qla2x00_nv_write(ha, 0); 324 qla2x00_nv_write(ha, 0); 325 for (word = 0; word < 8; word++) 326 qla2x00_nv_write(ha, NVR_DATA_OUT); 327 328 qla2x00_nv_deselect(ha); 329 330 /* Enable protection register. */ 331 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 332 qla2x00_nv_write(ha, NVR_PR_ENABLE); 333 qla2x00_nv_write(ha, NVR_PR_ENABLE); 334 for (word = 0; word < 8; word++) 335 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 336 337 qla2x00_nv_deselect(ha); 338 339 /* Clear protection register (ffff is cleared). */ 340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 343 for (word = 0; word < 8; word++) 344 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 345 346 qla2x00_nv_deselect(ha); 347 348 /* Wait for NVRAM to become ready. */ 349 WRT_REG_WORD(®->nvram, NVR_SELECT); 350 RD_REG_WORD(®->nvram); /* PCI Posting. */ 351 wait_cnt = NVR_WAIT_CNT; 352 do { 353 if (!--wait_cnt) { 354 DEBUG9_10(printk("%s(%ld): NVRAM didn't go " 355 "ready...\n", __func__, 356 ha->host_no)); 357 break; 358 } 359 NVRAM_DELAY(); 360 word = RD_REG_WORD(®->nvram); 361 } while ((word & NVR_DATA_IN) == 0); 362 363 if (wait_cnt) 364 ret = QLA_SUCCESS; 365 } else 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 367 368 return ret; 369 } 370 371 static void 372 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat) 373 { 374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 375 uint32_t word, wait_cnt; 376 377 if (stat != QLA_SUCCESS) 378 return; 379 380 /* Set NVRAM write protection. */ 381 /* Write enable. */ 382 qla2x00_nv_write(ha, NVR_DATA_OUT); 383 qla2x00_nv_write(ha, 0); 384 qla2x00_nv_write(ha, 0); 385 for (word = 0; word < 8; word++) 386 qla2x00_nv_write(ha, NVR_DATA_OUT); 387 388 qla2x00_nv_deselect(ha); 389 390 /* Enable protection register. */ 391 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 392 qla2x00_nv_write(ha, NVR_PR_ENABLE); 393 qla2x00_nv_write(ha, NVR_PR_ENABLE); 394 for (word = 0; word < 8; word++) 395 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 396 397 qla2x00_nv_deselect(ha); 398 399 /* Enable protection register. */ 400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 401 qla2x00_nv_write(ha, NVR_PR_ENABLE); 402 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 403 for (word = 0; word < 8; word++) 404 qla2x00_nv_write(ha, NVR_PR_ENABLE); 405 406 qla2x00_nv_deselect(ha); 407 408 /* Wait for NVRAM to become ready. */ 409 WRT_REG_WORD(®->nvram, NVR_SELECT); 410 RD_REG_WORD(®->nvram); /* PCI Posting. */ 411 wait_cnt = NVR_WAIT_CNT; 412 do { 413 if (!--wait_cnt) { 414 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n", 415 __func__, ha->host_no)); 416 break; 417 } 418 NVRAM_DELAY(); 419 word = RD_REG_WORD(®->nvram); 420 } while ((word & NVR_DATA_IN) == 0); 421 } 422 423 424 /*****************************************************************************/ 425 /* Flash Manipulation Routines */ 426 /*****************************************************************************/ 427 428 static inline uint32_t 429 flash_conf_to_access_addr(uint32_t faddr) 430 { 431 return FARX_ACCESS_FLASH_CONF | faddr; 432 } 433 434 static inline uint32_t 435 flash_data_to_access_addr(uint32_t faddr) 436 { 437 return FARX_ACCESS_FLASH_DATA | faddr; 438 } 439 440 static inline uint32_t 441 nvram_conf_to_access_addr(uint32_t naddr) 442 { 443 return FARX_ACCESS_NVRAM_CONF | naddr; 444 } 445 446 static inline uint32_t 447 nvram_data_to_access_addr(uint32_t naddr) 448 { 449 return FARX_ACCESS_NVRAM_DATA | naddr; 450 } 451 452 static uint32_t 453 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr) 454 { 455 int rval; 456 uint32_t cnt, data; 457 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 458 459 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); 460 /* Wait for READ cycle to complete. */ 461 rval = QLA_SUCCESS; 462 for (cnt = 3000; 463 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && 464 rval == QLA_SUCCESS; cnt--) { 465 if (cnt) 466 udelay(10); 467 else 468 rval = QLA_FUNCTION_TIMEOUT; 469 cond_resched(); 470 } 471 472 /* TODO: What happens if we time out? */ 473 data = 0xDEADDEAD; 474 if (rval == QLA_SUCCESS) 475 data = RD_REG_DWORD(®->flash_data); 476 477 return data; 478 } 479 480 uint32_t * 481 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, 482 uint32_t dwords) 483 { 484 uint32_t i; 485 486 /* Dword reads to flash. */ 487 for (i = 0; i < dwords; i++, faddr++) 488 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 489 flash_data_to_access_addr(faddr))); 490 491 return dwptr; 492 } 493 494 static int 495 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data) 496 { 497 int rval; 498 uint32_t cnt; 499 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 500 501 WRT_REG_DWORD(®->flash_data, data); 502 RD_REG_DWORD(®->flash_data); /* PCI Posting. */ 503 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); 504 /* Wait for Write cycle to complete. */ 505 rval = QLA_SUCCESS; 506 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && 507 rval == QLA_SUCCESS; cnt--) { 508 if (cnt) 509 udelay(10); 510 else 511 rval = QLA_FUNCTION_TIMEOUT; 512 cond_resched(); 513 } 514 return rval; 515 } 516 517 static void 518 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id, 519 uint8_t *flash_id) 520 { 521 uint32_t ids; 522 523 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab)); 524 *man_id = LSB(ids); 525 *flash_id = MSB(ids); 526 527 /* Check if man_id and flash_id are valid. */ 528 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 529 /* Read information using 0x9f opcode 530 * Device ID, Mfg ID would be read in the format: 531 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 532 * Example: ATMEL 0x00 01 45 1F 533 * Extract MFG and Dev ID from last two bytes. 534 */ 535 ids = qla24xx_read_flash_dword(ha, 536 flash_data_to_access_addr(0xd009f)); 537 *man_id = LSB(ids); 538 *flash_id = MSB(ids); 539 } 540 } 541 542 static int 543 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, 544 uint32_t dwords) 545 { 546 int ret; 547 uint32_t liter; 548 uint32_t sec_mask, rest_addr, conf_addr, sec_end_mask; 549 uint32_t fdata, findex ; 550 uint8_t man_id, flash_id; 551 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 552 553 ret = QLA_SUCCESS; 554 555 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 556 DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__, 557 ha->host_no, man_id, flash_id)); 558 559 sec_end_mask = 0; 560 conf_addr = flash_conf_to_access_addr(0x03d8); 561 switch (man_id) { 562 case 0xbf: /* STT flash. */ 563 rest_addr = 0x1fff; 564 sec_mask = 0x3e000; 565 if (flash_id == 0x80) 566 conf_addr = flash_conf_to_access_addr(0x0352); 567 break; 568 case 0x13: /* ST M25P80. */ 569 rest_addr = 0x3fff; 570 sec_mask = 0x3c000; 571 break; 572 case 0x1f: // Atmel 26DF081A 573 rest_addr = 0x0fff; 574 sec_mask = 0xff000; 575 sec_end_mask = 0x003ff; 576 conf_addr = flash_conf_to_access_addr(0x0320); 577 break; 578 default: 579 /* Default to 64 kb sector size. */ 580 rest_addr = 0x3fff; 581 sec_mask = 0x3c000; 582 break; 583 } 584 585 /* Enable flash write. */ 586 WRT_REG_DWORD(®->ctrl_status, 587 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 588 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 589 590 /* Disable flash write-protection. */ 591 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); 592 /* Some flash parts need an additional zero-write to clear bits.*/ 593 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); 594 595 do { /* Loop once to provide quick error exit. */ 596 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 597 if (man_id == 0x1f) { 598 findex = faddr << 2; 599 fdata = findex & sec_mask; 600 } else { 601 findex = faddr; 602 fdata = (findex & sec_mask) << 2; 603 } 604 605 /* Are we at the beginning of a sector? */ 606 if ((findex & rest_addr) == 0) { 607 /* 608 * Do sector unprotect at 4K boundry for Atmel 609 * part. 610 */ 611 if (man_id == 0x1f) 612 qla24xx_write_flash_dword(ha, 613 flash_conf_to_access_addr(0x0339), 614 (fdata & 0xff00) | ((fdata << 16) & 615 0xff0000) | ((fdata >> 16) & 0xff)); 616 ret = qla24xx_write_flash_dword(ha, conf_addr, 617 (fdata & 0xff00) |((fdata << 16) & 618 0xff0000) | ((fdata >> 16) & 0xff)); 619 if (ret != QLA_SUCCESS) { 620 DEBUG9(printk("%s(%ld) Unable to flash " 621 "sector: address=%x.\n", __func__, 622 ha->host_no, faddr)); 623 break; 624 } 625 } 626 ret = qla24xx_write_flash_dword(ha, 627 flash_data_to_access_addr(faddr), 628 cpu_to_le32(*dwptr)); 629 if (ret != QLA_SUCCESS) { 630 DEBUG9(printk("%s(%ld) Unable to program flash " 631 "address=%x data=%x.\n", __func__, 632 ha->host_no, faddr, *dwptr)); 633 break; 634 } 635 636 /* Do sector protect at 4K boundry for Atmel part. */ 637 if (man_id == 0x1f && 638 ((faddr & sec_end_mask) == 0x3ff)) 639 qla24xx_write_flash_dword(ha, 640 flash_conf_to_access_addr(0x0336), 641 (fdata & 0xff00) | ((fdata << 16) & 642 0xff0000) | ((fdata >> 16) & 0xff)); 643 } 644 } while (0); 645 646 /* Enable flash write-protection. */ 647 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c); 648 649 /* Disable flash write. */ 650 WRT_REG_DWORD(®->ctrl_status, 651 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 652 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 653 654 return ret; 655 } 656 657 uint8_t * 658 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 659 uint32_t bytes) 660 { 661 uint32_t i; 662 uint16_t *wptr; 663 664 /* Word reads to NVRAM via registers. */ 665 wptr = (uint16_t *)buf; 666 qla2x00_lock_nvram_access(ha); 667 for (i = 0; i < bytes >> 1; i++, naddr++) 668 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 669 naddr)); 670 qla2x00_unlock_nvram_access(ha); 671 672 return buf; 673 } 674 675 uint8_t * 676 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 677 uint32_t bytes) 678 { 679 uint32_t i; 680 uint32_t *dwptr; 681 682 /* Dword reads to flash. */ 683 dwptr = (uint32_t *)buf; 684 for (i = 0; i < bytes >> 2; i++, naddr++) 685 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 686 nvram_data_to_access_addr(naddr))); 687 688 return buf; 689 } 690 691 int 692 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 693 uint32_t bytes) 694 { 695 int ret, stat; 696 uint32_t i; 697 uint16_t *wptr; 698 699 ret = QLA_SUCCESS; 700 701 qla2x00_lock_nvram_access(ha); 702 703 /* Disable NVRAM write-protection. */ 704 stat = qla2x00_clear_nvram_protection(ha); 705 706 wptr = (uint16_t *)buf; 707 for (i = 0; i < bytes >> 1; i++, naddr++) { 708 qla2x00_write_nvram_word(ha, naddr, 709 cpu_to_le16(*wptr)); 710 wptr++; 711 } 712 713 /* Enable NVRAM write-protection. */ 714 qla2x00_set_nvram_protection(ha, stat); 715 716 qla2x00_unlock_nvram_access(ha); 717 718 return ret; 719 } 720 721 int 722 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 723 uint32_t bytes) 724 { 725 int ret; 726 uint32_t i; 727 uint32_t *dwptr; 728 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 729 730 ret = QLA_SUCCESS; 731 732 /* Enable flash write. */ 733 WRT_REG_DWORD(®->ctrl_status, 734 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 735 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 736 737 /* Disable NVRAM write-protection. */ 738 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 739 0); 740 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 741 0); 742 743 /* Dword writes to flash. */ 744 dwptr = (uint32_t *)buf; 745 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) { 746 ret = qla24xx_write_flash_dword(ha, 747 nvram_data_to_access_addr(naddr), 748 cpu_to_le32(*dwptr)); 749 if (ret != QLA_SUCCESS) { 750 DEBUG9(printk("%s(%ld) Unable to program " 751 "nvram address=%x data=%x.\n", __func__, 752 ha->host_no, naddr, *dwptr)); 753 break; 754 } 755 } 756 757 /* Enable NVRAM write-protection. */ 758 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 759 0x8c); 760 761 /* Disable flash write. */ 762 WRT_REG_DWORD(®->ctrl_status, 763 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 764 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 765 766 return ret; 767 } 768 769 uint8_t * 770 qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 771 uint32_t bytes) 772 { 773 uint32_t i; 774 uint32_t *dwptr; 775 776 /* Dword reads to flash. */ 777 dwptr = (uint32_t *)buf; 778 for (i = 0; i < bytes >> 2; i++, naddr++) 779 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 780 flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr))); 781 782 return buf; 783 } 784 785 int 786 qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 787 uint32_t bytes) 788 { 789 return qla24xx_write_flash_data(ha, (uint32_t *)buf, 790 FA_VPD_NVRAM_ADDR | naddr, bytes >> 2); 791 } 792 793 static inline void 794 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) 795 { 796 if (IS_QLA2322(ha)) { 797 /* Flip all colors. */ 798 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 799 /* Turn off. */ 800 ha->beacon_color_state = 0; 801 *pflags = GPIO_LED_ALL_OFF; 802 } else { 803 /* Turn on. */ 804 ha->beacon_color_state = QLA_LED_ALL_ON; 805 *pflags = GPIO_LED_RGA_ON; 806 } 807 } else { 808 /* Flip green led only. */ 809 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 810 /* Turn off. */ 811 ha->beacon_color_state = 0; 812 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 813 } else { 814 /* Turn on. */ 815 ha->beacon_color_state = QLA_LED_GRN_ON; 816 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 817 } 818 } 819 } 820 821 void 822 qla2x00_beacon_blink(struct scsi_qla_host *ha) 823 { 824 uint16_t gpio_enable; 825 uint16_t gpio_data; 826 uint16_t led_color = 0; 827 unsigned long flags; 828 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 829 830 if (ha->pio_address) 831 reg = (struct device_reg_2xxx __iomem *)ha->pio_address; 832 833 spin_lock_irqsave(&ha->hardware_lock, flags); 834 835 /* Save the Original GPIOE. */ 836 if (ha->pio_address) { 837 gpio_enable = RD_REG_WORD_PIO(®->gpioe); 838 gpio_data = RD_REG_WORD_PIO(®->gpiod); 839 } else { 840 gpio_enable = RD_REG_WORD(®->gpioe); 841 gpio_data = RD_REG_WORD(®->gpiod); 842 } 843 844 /* Set the modified gpio_enable values */ 845 gpio_enable |= GPIO_LED_MASK; 846 847 if (ha->pio_address) { 848 WRT_REG_WORD_PIO(®->gpioe, gpio_enable); 849 } else { 850 WRT_REG_WORD(®->gpioe, gpio_enable); 851 RD_REG_WORD(®->gpioe); 852 } 853 854 qla2x00_flip_colors(ha, &led_color); 855 856 /* Clear out any previously set LED color. */ 857 gpio_data &= ~GPIO_LED_MASK; 858 859 /* Set the new input LED color to GPIOD. */ 860 gpio_data |= led_color; 861 862 /* Set the modified gpio_data values */ 863 if (ha->pio_address) { 864 WRT_REG_WORD_PIO(®->gpiod, gpio_data); 865 } else { 866 WRT_REG_WORD(®->gpiod, gpio_data); 867 RD_REG_WORD(®->gpiod); 868 } 869 870 spin_unlock_irqrestore(&ha->hardware_lock, flags); 871 } 872 873 int 874 qla2x00_beacon_on(struct scsi_qla_host *ha) 875 { 876 uint16_t gpio_enable; 877 uint16_t gpio_data; 878 unsigned long flags; 879 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 880 881 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 882 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 883 884 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { 885 qla_printk(KERN_WARNING, ha, 886 "Unable to update fw options (beacon on).\n"); 887 return QLA_FUNCTION_FAILED; 888 } 889 890 if (ha->pio_address) 891 reg = (struct device_reg_2xxx __iomem *)ha->pio_address; 892 893 /* Turn off LEDs. */ 894 spin_lock_irqsave(&ha->hardware_lock, flags); 895 if (ha->pio_address) { 896 gpio_enable = RD_REG_WORD_PIO(®->gpioe); 897 gpio_data = RD_REG_WORD_PIO(®->gpiod); 898 } else { 899 gpio_enable = RD_REG_WORD(®->gpioe); 900 gpio_data = RD_REG_WORD(®->gpiod); 901 } 902 gpio_enable |= GPIO_LED_MASK; 903 904 /* Set the modified gpio_enable values. */ 905 if (ha->pio_address) { 906 WRT_REG_WORD_PIO(®->gpioe, gpio_enable); 907 } else { 908 WRT_REG_WORD(®->gpioe, gpio_enable); 909 RD_REG_WORD(®->gpioe); 910 } 911 912 /* Clear out previously set LED colour. */ 913 gpio_data &= ~GPIO_LED_MASK; 914 if (ha->pio_address) { 915 WRT_REG_WORD_PIO(®->gpiod, gpio_data); 916 } else { 917 WRT_REG_WORD(®->gpiod, gpio_data); 918 RD_REG_WORD(®->gpiod); 919 } 920 spin_unlock_irqrestore(&ha->hardware_lock, flags); 921 922 /* 923 * Let the per HBA timer kick off the blinking process based on 924 * the following flags. No need to do anything else now. 925 */ 926 ha->beacon_blink_led = 1; 927 ha->beacon_color_state = 0; 928 929 return QLA_SUCCESS; 930 } 931 932 int 933 qla2x00_beacon_off(struct scsi_qla_host *ha) 934 { 935 int rval = QLA_SUCCESS; 936 937 ha->beacon_blink_led = 0; 938 939 /* Set the on flag so when it gets flipped it will be off. */ 940 if (IS_QLA2322(ha)) 941 ha->beacon_color_state = QLA_LED_ALL_ON; 942 else 943 ha->beacon_color_state = QLA_LED_GRN_ON; 944 945 ha->isp_ops->beacon_blink(ha); /* This turns green LED off */ 946 947 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 948 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 949 950 rval = qla2x00_set_fw_options(ha, ha->fw_options); 951 if (rval != QLA_SUCCESS) 952 qla_printk(KERN_WARNING, ha, 953 "Unable to update fw options (beacon off).\n"); 954 return rval; 955 } 956 957 958 static inline void 959 qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) 960 { 961 /* Flip all colors. */ 962 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 963 /* Turn off. */ 964 ha->beacon_color_state = 0; 965 *pflags = 0; 966 } else { 967 /* Turn on. */ 968 ha->beacon_color_state = QLA_LED_ALL_ON; 969 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 970 } 971 } 972 973 void 974 qla24xx_beacon_blink(struct scsi_qla_host *ha) 975 { 976 uint16_t led_color = 0; 977 uint32_t gpio_data; 978 unsigned long flags; 979 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 980 981 /* Save the Original GPIOD. */ 982 spin_lock_irqsave(&ha->hardware_lock, flags); 983 gpio_data = RD_REG_DWORD(®->gpiod); 984 985 /* Enable the gpio_data reg for update. */ 986 gpio_data |= GPDX_LED_UPDATE_MASK; 987 988 WRT_REG_DWORD(®->gpiod, gpio_data); 989 gpio_data = RD_REG_DWORD(®->gpiod); 990 991 /* Set the color bits. */ 992 qla24xx_flip_colors(ha, &led_color); 993 994 /* Clear out any previously set LED color. */ 995 gpio_data &= ~GPDX_LED_COLOR_MASK; 996 997 /* Set the new input LED color to GPIOD. */ 998 gpio_data |= led_color; 999 1000 /* Set the modified gpio_data values. */ 1001 WRT_REG_DWORD(®->gpiod, gpio_data); 1002 gpio_data = RD_REG_DWORD(®->gpiod); 1003 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1004 } 1005 1006 int 1007 qla24xx_beacon_on(struct scsi_qla_host *ha) 1008 { 1009 uint32_t gpio_data; 1010 unsigned long flags; 1011 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1012 1013 if (ha->beacon_blink_led == 0) { 1014 /* Enable firmware for update */ 1015 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1016 1017 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) 1018 return QLA_FUNCTION_FAILED; 1019 1020 if (qla2x00_get_fw_options(ha, ha->fw_options) != 1021 QLA_SUCCESS) { 1022 qla_printk(KERN_WARNING, ha, 1023 "Unable to update fw options (beacon on).\n"); 1024 return QLA_FUNCTION_FAILED; 1025 } 1026 1027 spin_lock_irqsave(&ha->hardware_lock, flags); 1028 gpio_data = RD_REG_DWORD(®->gpiod); 1029 1030 /* Enable the gpio_data reg for update. */ 1031 gpio_data |= GPDX_LED_UPDATE_MASK; 1032 WRT_REG_DWORD(®->gpiod, gpio_data); 1033 RD_REG_DWORD(®->gpiod); 1034 1035 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1036 } 1037 1038 /* So all colors blink together. */ 1039 ha->beacon_color_state = 0; 1040 1041 /* Let the per HBA timer kick off the blinking process. */ 1042 ha->beacon_blink_led = 1; 1043 1044 return QLA_SUCCESS; 1045 } 1046 1047 int 1048 qla24xx_beacon_off(struct scsi_qla_host *ha) 1049 { 1050 uint32_t gpio_data; 1051 unsigned long flags; 1052 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1053 1054 ha->beacon_blink_led = 0; 1055 ha->beacon_color_state = QLA_LED_ALL_ON; 1056 1057 ha->isp_ops->beacon_blink(ha); /* Will flip to all off. */ 1058 1059 /* Give control back to firmware. */ 1060 spin_lock_irqsave(&ha->hardware_lock, flags); 1061 gpio_data = RD_REG_DWORD(®->gpiod); 1062 1063 /* Disable the gpio_data reg for update. */ 1064 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1065 WRT_REG_DWORD(®->gpiod, gpio_data); 1066 RD_REG_DWORD(®->gpiod); 1067 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1068 1069 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1070 1071 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { 1072 qla_printk(KERN_WARNING, ha, 1073 "Unable to update fw options (beacon off).\n"); 1074 return QLA_FUNCTION_FAILED; 1075 } 1076 1077 if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { 1078 qla_printk(KERN_WARNING, ha, 1079 "Unable to get fw options (beacon off).\n"); 1080 return QLA_FUNCTION_FAILED; 1081 } 1082 1083 return QLA_SUCCESS; 1084 } 1085 1086 1087 /* 1088 * Flash support routines 1089 */ 1090 1091 /** 1092 * qla2x00_flash_enable() - Setup flash for reading and writing. 1093 * @ha: HA context 1094 */ 1095 static void 1096 qla2x00_flash_enable(scsi_qla_host_t *ha) 1097 { 1098 uint16_t data; 1099 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1100 1101 data = RD_REG_WORD(®->ctrl_status); 1102 data |= CSR_FLASH_ENABLE; 1103 WRT_REG_WORD(®->ctrl_status, data); 1104 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1105 } 1106 1107 /** 1108 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1109 * @ha: HA context 1110 */ 1111 static void 1112 qla2x00_flash_disable(scsi_qla_host_t *ha) 1113 { 1114 uint16_t data; 1115 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1116 1117 data = RD_REG_WORD(®->ctrl_status); 1118 data &= ~(CSR_FLASH_ENABLE); 1119 WRT_REG_WORD(®->ctrl_status, data); 1120 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1121 } 1122 1123 /** 1124 * qla2x00_read_flash_byte() - Reads a byte from flash 1125 * @ha: HA context 1126 * @addr: Address in flash to read 1127 * 1128 * A word is read from the chip, but, only the lower byte is valid. 1129 * 1130 * Returns the byte read from flash @addr. 1131 */ 1132 static uint8_t 1133 qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr) 1134 { 1135 uint16_t data; 1136 uint16_t bank_select; 1137 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1138 1139 bank_select = RD_REG_WORD(®->ctrl_status); 1140 1141 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1142 /* Specify 64K address range: */ 1143 /* clear out Module Select and Flash Address bits [19:16]. */ 1144 bank_select &= ~0xf8; 1145 bank_select |= addr >> 12 & 0xf0; 1146 bank_select |= CSR_FLASH_64K_BANK; 1147 WRT_REG_WORD(®->ctrl_status, bank_select); 1148 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1149 1150 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1151 data = RD_REG_WORD(®->flash_data); 1152 1153 return (uint8_t)data; 1154 } 1155 1156 /* Setup bit 16 of flash address. */ 1157 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 1158 bank_select |= CSR_FLASH_64K_BANK; 1159 WRT_REG_WORD(®->ctrl_status, bank_select); 1160 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1161 } else if (((addr & BIT_16) == 0) && 1162 (bank_select & CSR_FLASH_64K_BANK)) { 1163 bank_select &= ~(CSR_FLASH_64K_BANK); 1164 WRT_REG_WORD(®->ctrl_status, bank_select); 1165 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1166 } 1167 1168 /* Always perform IO mapped accesses to the FLASH registers. */ 1169 if (ha->pio_address) { 1170 uint16_t data2; 1171 1172 reg = (struct device_reg_2xxx __iomem *)ha->pio_address; 1173 WRT_REG_WORD_PIO(®->flash_address, (uint16_t)addr); 1174 do { 1175 data = RD_REG_WORD_PIO(®->flash_data); 1176 barrier(); 1177 cpu_relax(); 1178 data2 = RD_REG_WORD_PIO(®->flash_data); 1179 } while (data != data2); 1180 } else { 1181 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1182 data = qla2x00_debounce_register(®->flash_data); 1183 } 1184 1185 return (uint8_t)data; 1186 } 1187 1188 /** 1189 * qla2x00_write_flash_byte() - Write a byte to flash 1190 * @ha: HA context 1191 * @addr: Address in flash to write 1192 * @data: Data to write 1193 */ 1194 static void 1195 qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data) 1196 { 1197 uint16_t bank_select; 1198 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1199 1200 bank_select = RD_REG_WORD(®->ctrl_status); 1201 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1202 /* Specify 64K address range: */ 1203 /* clear out Module Select and Flash Address bits [19:16]. */ 1204 bank_select &= ~0xf8; 1205 bank_select |= addr >> 12 & 0xf0; 1206 bank_select |= CSR_FLASH_64K_BANK; 1207 WRT_REG_WORD(®->ctrl_status, bank_select); 1208 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1209 1210 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1211 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1212 WRT_REG_WORD(®->flash_data, (uint16_t)data); 1213 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1214 1215 return; 1216 } 1217 1218 /* Setup bit 16 of flash address. */ 1219 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 1220 bank_select |= CSR_FLASH_64K_BANK; 1221 WRT_REG_WORD(®->ctrl_status, bank_select); 1222 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1223 } else if (((addr & BIT_16) == 0) && 1224 (bank_select & CSR_FLASH_64K_BANK)) { 1225 bank_select &= ~(CSR_FLASH_64K_BANK); 1226 WRT_REG_WORD(®->ctrl_status, bank_select); 1227 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1228 } 1229 1230 /* Always perform IO mapped accesses to the FLASH registers. */ 1231 if (ha->pio_address) { 1232 reg = (struct device_reg_2xxx __iomem *)ha->pio_address; 1233 WRT_REG_WORD_PIO(®->flash_address, (uint16_t)addr); 1234 WRT_REG_WORD_PIO(®->flash_data, (uint16_t)data); 1235 } else { 1236 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1237 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1238 WRT_REG_WORD(®->flash_data, (uint16_t)data); 1239 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1240 } 1241 } 1242 1243 /** 1244 * qla2x00_poll_flash() - Polls flash for completion. 1245 * @ha: HA context 1246 * @addr: Address in flash to poll 1247 * @poll_data: Data to be polled 1248 * @man_id: Flash manufacturer ID 1249 * @flash_id: Flash ID 1250 * 1251 * This function polls the device until bit 7 of what is read matches data 1252 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed 1253 * out (a fatal error). The flash book recommeds reading bit 7 again after 1254 * reading bit 5 as a 1. 1255 * 1256 * Returns 0 on success, else non-zero. 1257 */ 1258 static int 1259 qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data, 1260 uint8_t man_id, uint8_t flash_id) 1261 { 1262 int status; 1263 uint8_t flash_data; 1264 uint32_t cnt; 1265 1266 status = 1; 1267 1268 /* Wait for 30 seconds for command to finish. */ 1269 poll_data &= BIT_7; 1270 for (cnt = 3000000; cnt; cnt--) { 1271 flash_data = qla2x00_read_flash_byte(ha, addr); 1272 if ((flash_data & BIT_7) == poll_data) { 1273 status = 0; 1274 break; 1275 } 1276 1277 if (man_id != 0x40 && man_id != 0xda) { 1278 if ((flash_data & BIT_5) && cnt > 2) 1279 cnt = 2; 1280 } 1281 udelay(10); 1282 barrier(); 1283 cond_resched(); 1284 } 1285 return status; 1286 } 1287 1288 /** 1289 * qla2x00_program_flash_address() - Programs a flash address 1290 * @ha: HA context 1291 * @addr: Address in flash to program 1292 * @data: Data to be written in flash 1293 * @man_id: Flash manufacturer ID 1294 * @flash_id: Flash ID 1295 * 1296 * Returns 0 on success, else non-zero. 1297 */ 1298 static int 1299 qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data, 1300 uint8_t man_id, uint8_t flash_id) 1301 { 1302 /* Write Program Command Sequence. */ 1303 if (IS_OEM_001(ha)) { 1304 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1305 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1306 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 1307 qla2x00_write_flash_byte(ha, addr, data); 1308 } else { 1309 if (man_id == 0xda && flash_id == 0xc1) { 1310 qla2x00_write_flash_byte(ha, addr, data); 1311 if (addr & 0x7e) 1312 return 0; 1313 } else { 1314 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1315 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1316 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 1317 qla2x00_write_flash_byte(ha, addr, data); 1318 } 1319 } 1320 1321 udelay(150); 1322 1323 /* Wait for write to complete. */ 1324 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 1325 } 1326 1327 /** 1328 * qla2x00_erase_flash() - Erase the flash. 1329 * @ha: HA context 1330 * @man_id: Flash manufacturer ID 1331 * @flash_id: Flash ID 1332 * 1333 * Returns 0 on success, else non-zero. 1334 */ 1335 static int 1336 qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id) 1337 { 1338 /* Individual Sector Erase Command Sequence */ 1339 if (IS_OEM_001(ha)) { 1340 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1341 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1342 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 1343 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1344 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1345 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 1346 } else { 1347 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1348 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1349 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 1350 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1351 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1352 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 1353 } 1354 1355 udelay(150); 1356 1357 /* Wait for erase to complete. */ 1358 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 1359 } 1360 1361 /** 1362 * qla2x00_erase_flash_sector() - Erase a flash sector. 1363 * @ha: HA context 1364 * @addr: Flash sector to erase 1365 * @sec_mask: Sector address mask 1366 * @man_id: Flash manufacturer ID 1367 * @flash_id: Flash ID 1368 * 1369 * Returns 0 on success, else non-zero. 1370 */ 1371 static int 1372 qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr, 1373 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 1374 { 1375 /* Individual Sector Erase Command Sequence */ 1376 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1377 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1378 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 1379 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1380 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1381 if (man_id == 0x1f && flash_id == 0x13) 1382 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 1383 else 1384 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 1385 1386 udelay(150); 1387 1388 /* Wait for erase to complete. */ 1389 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 1390 } 1391 1392 /** 1393 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 1394 * @man_id: Flash manufacturer ID 1395 * @flash_id: Flash ID 1396 */ 1397 static void 1398 qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id, 1399 uint8_t *flash_id) 1400 { 1401 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1402 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1403 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 1404 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 1405 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 1406 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1407 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1408 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 1409 } 1410 1411 static void 1412 qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr, 1413 uint32_t length) 1414 { 1415 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1416 uint32_t midpoint, ilength; 1417 uint8_t data; 1418 1419 midpoint = length / 2; 1420 1421 WRT_REG_WORD(®->nvram, 0); 1422 RD_REG_WORD(®->nvram); 1423 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 1424 if (ilength == midpoint) { 1425 WRT_REG_WORD(®->nvram, NVR_SELECT); 1426 RD_REG_WORD(®->nvram); 1427 } 1428 data = qla2x00_read_flash_byte(ha, saddr); 1429 if (saddr % 100) 1430 udelay(10); 1431 *tmp_buf = data; 1432 cond_resched(); 1433 } 1434 } 1435 1436 static inline void 1437 qla2x00_suspend_hba(struct scsi_qla_host *ha) 1438 { 1439 int cnt; 1440 unsigned long flags; 1441 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1442 1443 /* Suspend HBA. */ 1444 scsi_block_requests(ha->host); 1445 ha->isp_ops->disable_intrs(ha); 1446 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1447 1448 /* Pause RISC. */ 1449 spin_lock_irqsave(&ha->hardware_lock, flags); 1450 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 1451 RD_REG_WORD(®->hccr); 1452 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 1453 for (cnt = 0; cnt < 30000; cnt++) { 1454 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 1455 break; 1456 udelay(100); 1457 } 1458 } else { 1459 udelay(10); 1460 } 1461 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1462 } 1463 1464 static inline void 1465 qla2x00_resume_hba(struct scsi_qla_host *ha) 1466 { 1467 /* Resume HBA. */ 1468 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1469 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); 1470 qla2xxx_wake_dpc(ha); 1471 qla2x00_wait_for_hba_online(ha); 1472 scsi_unblock_requests(ha->host); 1473 } 1474 1475 uint8_t * 1476 qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1477 uint32_t offset, uint32_t length) 1478 { 1479 uint32_t addr, midpoint; 1480 uint8_t *data; 1481 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1482 1483 /* Suspend HBA. */ 1484 qla2x00_suspend_hba(ha); 1485 1486 /* Go with read. */ 1487 midpoint = ha->optrom_size / 2; 1488 1489 qla2x00_flash_enable(ha); 1490 WRT_REG_WORD(®->nvram, 0); 1491 RD_REG_WORD(®->nvram); /* PCI Posting. */ 1492 for (addr = offset, data = buf; addr < length; addr++, data++) { 1493 if (addr == midpoint) { 1494 WRT_REG_WORD(®->nvram, NVR_SELECT); 1495 RD_REG_WORD(®->nvram); /* PCI Posting. */ 1496 } 1497 1498 *data = qla2x00_read_flash_byte(ha, addr); 1499 } 1500 qla2x00_flash_disable(ha); 1501 1502 /* Resume HBA. */ 1503 qla2x00_resume_hba(ha); 1504 1505 return buf; 1506 } 1507 1508 int 1509 qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1510 uint32_t offset, uint32_t length) 1511 { 1512 1513 int rval; 1514 uint8_t man_id, flash_id, sec_number, data; 1515 uint16_t wd; 1516 uint32_t addr, liter, sec_mask, rest_addr; 1517 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1518 1519 /* Suspend HBA. */ 1520 qla2x00_suspend_hba(ha); 1521 1522 rval = QLA_SUCCESS; 1523 sec_number = 0; 1524 1525 /* Reset ISP chip. */ 1526 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 1527 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 1528 1529 /* Go with write. */ 1530 qla2x00_flash_enable(ha); 1531 do { /* Loop once to provide quick error exit */ 1532 /* Structure of flash memory based on manufacturer */ 1533 if (IS_OEM_001(ha)) { 1534 /* OEM variant with special flash part. */ 1535 man_id = flash_id = 0; 1536 rest_addr = 0xffff; 1537 sec_mask = 0x10000; 1538 goto update_flash; 1539 } 1540 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 1541 switch (man_id) { 1542 case 0x20: /* ST flash. */ 1543 if (flash_id == 0xd2 || flash_id == 0xe3) { 1544 /* 1545 * ST m29w008at part - 64kb sector size with 1546 * 32kb,8kb,8kb,16kb sectors at memory address 1547 * 0xf0000. 1548 */ 1549 rest_addr = 0xffff; 1550 sec_mask = 0x10000; 1551 break; 1552 } 1553 /* 1554 * ST m29w010b part - 16kb sector size 1555 * Default to 16kb sectors 1556 */ 1557 rest_addr = 0x3fff; 1558 sec_mask = 0x1c000; 1559 break; 1560 case 0x40: /* Mostel flash. */ 1561 /* Mostel v29c51001 part - 512 byte sector size. */ 1562 rest_addr = 0x1ff; 1563 sec_mask = 0x1fe00; 1564 break; 1565 case 0xbf: /* SST flash. */ 1566 /* SST39sf10 part - 4kb sector size. */ 1567 rest_addr = 0xfff; 1568 sec_mask = 0x1f000; 1569 break; 1570 case 0xda: /* Winbond flash. */ 1571 /* Winbond W29EE011 part - 256 byte sector size. */ 1572 rest_addr = 0x7f; 1573 sec_mask = 0x1ff80; 1574 break; 1575 case 0xc2: /* Macronix flash. */ 1576 /* 64k sector size. */ 1577 if (flash_id == 0x38 || flash_id == 0x4f) { 1578 rest_addr = 0xffff; 1579 sec_mask = 0x10000; 1580 break; 1581 } 1582 /* Fall through... */ 1583 1584 case 0x1f: /* Atmel flash. */ 1585 /* 512k sector size. */ 1586 if (flash_id == 0x13) { 1587 rest_addr = 0x7fffffff; 1588 sec_mask = 0x80000000; 1589 break; 1590 } 1591 /* Fall through... */ 1592 1593 case 0x01: /* AMD flash. */ 1594 if (flash_id == 0x38 || flash_id == 0x40 || 1595 flash_id == 0x4f) { 1596 /* Am29LV081 part - 64kb sector size. */ 1597 /* Am29LV002BT part - 64kb sector size. */ 1598 rest_addr = 0xffff; 1599 sec_mask = 0x10000; 1600 break; 1601 } else if (flash_id == 0x3e) { 1602 /* 1603 * Am29LV008b part - 64kb sector size with 1604 * 32kb,8kb,8kb,16kb sector at memory address 1605 * h0xf0000. 1606 */ 1607 rest_addr = 0xffff; 1608 sec_mask = 0x10000; 1609 break; 1610 } else if (flash_id == 0x20 || flash_id == 0x6e) { 1611 /* 1612 * Am29LV010 part or AM29f010 - 16kb sector 1613 * size. 1614 */ 1615 rest_addr = 0x3fff; 1616 sec_mask = 0x1c000; 1617 break; 1618 } else if (flash_id == 0x6d) { 1619 /* Am29LV001 part - 8kb sector size. */ 1620 rest_addr = 0x1fff; 1621 sec_mask = 0x1e000; 1622 break; 1623 } 1624 default: 1625 /* Default to 16 kb sector size. */ 1626 rest_addr = 0x3fff; 1627 sec_mask = 0x1c000; 1628 break; 1629 } 1630 1631 update_flash: 1632 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1633 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 1634 rval = QLA_FUNCTION_FAILED; 1635 break; 1636 } 1637 } 1638 1639 for (addr = offset, liter = 0; liter < length; liter++, 1640 addr++) { 1641 data = buf[liter]; 1642 /* Are we at the beginning of a sector? */ 1643 if ((addr & rest_addr) == 0) { 1644 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1645 if (addr >= 0x10000UL) { 1646 if (((addr >> 12) & 0xf0) && 1647 ((man_id == 0x01 && 1648 flash_id == 0x3e) || 1649 (man_id == 0x20 && 1650 flash_id == 0xd2))) { 1651 sec_number++; 1652 if (sec_number == 1) { 1653 rest_addr = 1654 0x7fff; 1655 sec_mask = 1656 0x18000; 1657 } else if ( 1658 sec_number == 2 || 1659 sec_number == 3) { 1660 rest_addr = 1661 0x1fff; 1662 sec_mask = 1663 0x1e000; 1664 } else if ( 1665 sec_number == 4) { 1666 rest_addr = 1667 0x3fff; 1668 sec_mask = 1669 0x1c000; 1670 } 1671 } 1672 } 1673 } else if (addr == ha->optrom_size / 2) { 1674 WRT_REG_WORD(®->nvram, NVR_SELECT); 1675 RD_REG_WORD(®->nvram); 1676 } 1677 1678 if (flash_id == 0xda && man_id == 0xc1) { 1679 qla2x00_write_flash_byte(ha, 0x5555, 1680 0xaa); 1681 qla2x00_write_flash_byte(ha, 0x2aaa, 1682 0x55); 1683 qla2x00_write_flash_byte(ha, 0x5555, 1684 0xa0); 1685 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 1686 /* Then erase it */ 1687 if (qla2x00_erase_flash_sector(ha, 1688 addr, sec_mask, man_id, 1689 flash_id)) { 1690 rval = QLA_FUNCTION_FAILED; 1691 break; 1692 } 1693 if (man_id == 0x01 && flash_id == 0x6d) 1694 sec_number++; 1695 } 1696 } 1697 1698 if (man_id == 0x01 && flash_id == 0x6d) { 1699 if (sec_number == 1 && 1700 addr == (rest_addr - 1)) { 1701 rest_addr = 0x0fff; 1702 sec_mask = 0x1f000; 1703 } else if (sec_number == 3 && (addr & 0x7ffe)) { 1704 rest_addr = 0x3fff; 1705 sec_mask = 0x1c000; 1706 } 1707 } 1708 1709 if (qla2x00_program_flash_address(ha, addr, data, 1710 man_id, flash_id)) { 1711 rval = QLA_FUNCTION_FAILED; 1712 break; 1713 } 1714 cond_resched(); 1715 } 1716 } while (0); 1717 qla2x00_flash_disable(ha); 1718 1719 /* Resume HBA. */ 1720 qla2x00_resume_hba(ha); 1721 1722 return rval; 1723 } 1724 1725 uint8_t * 1726 qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1727 uint32_t offset, uint32_t length) 1728 { 1729 /* Suspend HBA. */ 1730 scsi_block_requests(ha->host); 1731 ha->isp_ops->disable_intrs(ha); 1732 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1733 1734 /* Go with read. */ 1735 qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2); 1736 1737 /* Resume HBA. */ 1738 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1739 ha->isp_ops->enable_intrs(ha); 1740 scsi_unblock_requests(ha->host); 1741 1742 return buf; 1743 } 1744 1745 int 1746 qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1747 uint32_t offset, uint32_t length) 1748 { 1749 int rval; 1750 1751 /* Suspend HBA. */ 1752 scsi_block_requests(ha->host); 1753 ha->isp_ops->disable_intrs(ha); 1754 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1755 1756 /* Go with write. */ 1757 rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2, 1758 length >> 2); 1759 1760 /* Resume HBA -- RISC reset needed. */ 1761 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1762 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); 1763 qla2xxx_wake_dpc(ha); 1764 qla2x00_wait_for_hba_online(ha); 1765 scsi_unblock_requests(ha->host); 1766 1767 return rval; 1768 } 1769 1770 /** 1771 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 1772 * @ha: HA context 1773 * @pcids: Pointer to the FCODE PCI data structure 1774 * 1775 * The process of retrieving the FCODE version information is at best 1776 * described as interesting. 1777 * 1778 * Within the first 100h bytes of the image an ASCII string is present 1779 * which contains several pieces of information including the FCODE 1780 * version. Unfortunately it seems the only reliable way to retrieve 1781 * the version is by scanning for another sentinel within the string, 1782 * the FCODE build date: 1783 * 1784 * ... 2.00.02 10/17/02 ... 1785 * 1786 * Returns QLA_SUCCESS on successful retrieval of version. 1787 */ 1788 static void 1789 qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids) 1790 { 1791 int ret = QLA_FUNCTION_FAILED; 1792 uint32_t istart, iend, iter, vend; 1793 uint8_t do_next, rbyte, *vbyte; 1794 1795 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 1796 1797 /* Skip the PCI data structure. */ 1798 istart = pcids + 1799 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 1800 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 1801 iend = istart + 0x100; 1802 do { 1803 /* Scan for the sentinel date string...eeewww. */ 1804 do_next = 0; 1805 iter = istart; 1806 while ((iter < iend) && !do_next) { 1807 iter++; 1808 if (qla2x00_read_flash_byte(ha, iter) == '/') { 1809 if (qla2x00_read_flash_byte(ha, iter + 2) == 1810 '/') 1811 do_next++; 1812 else if (qla2x00_read_flash_byte(ha, 1813 iter + 3) == '/') 1814 do_next++; 1815 } 1816 } 1817 if (!do_next) 1818 break; 1819 1820 /* Backtrack to previous ' ' (space). */ 1821 do_next = 0; 1822 while ((iter > istart) && !do_next) { 1823 iter--; 1824 if (qla2x00_read_flash_byte(ha, iter) == ' ') 1825 do_next++; 1826 } 1827 if (!do_next) 1828 break; 1829 1830 /* 1831 * Mark end of version tag, and find previous ' ' (space) or 1832 * string length (recent FCODE images -- major hack ahead!!!). 1833 */ 1834 vend = iter - 1; 1835 do_next = 0; 1836 while ((iter > istart) && !do_next) { 1837 iter--; 1838 rbyte = qla2x00_read_flash_byte(ha, iter); 1839 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 1840 do_next++; 1841 } 1842 if (!do_next) 1843 break; 1844 1845 /* Mark beginning of version tag, and copy data. */ 1846 iter++; 1847 if ((vend - iter) && 1848 ((vend - iter) < sizeof(ha->fcode_revision))) { 1849 vbyte = ha->fcode_revision; 1850 while (iter <= vend) { 1851 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 1852 iter++; 1853 } 1854 ret = QLA_SUCCESS; 1855 } 1856 } while (0); 1857 1858 if (ret != QLA_SUCCESS) 1859 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 1860 } 1861 1862 int 1863 qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf) 1864 { 1865 int ret = QLA_SUCCESS; 1866 uint8_t code_type, last_image; 1867 uint32_t pcihdr, pcids; 1868 uint8_t *dbyte; 1869 uint16_t *dcode; 1870 1871 if (!ha->pio_address || !mbuf) 1872 return QLA_FUNCTION_FAILED; 1873 1874 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 1875 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 1876 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 1877 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 1878 1879 qla2x00_flash_enable(ha); 1880 1881 /* Begin with first PCI expansion ROM header. */ 1882 pcihdr = 0; 1883 last_image = 1; 1884 do { 1885 /* Verify PCI expansion ROM header. */ 1886 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 1887 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 1888 /* No signature */ 1889 DEBUG2(printk("scsi(%ld): No matching ROM " 1890 "signature.\n", ha->host_no)); 1891 ret = QLA_FUNCTION_FAILED; 1892 break; 1893 } 1894 1895 /* Locate PCI data structure. */ 1896 pcids = pcihdr + 1897 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 1898 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 1899 1900 /* Validate signature of PCI data structure. */ 1901 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 1902 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 1903 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 1904 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 1905 /* Incorrect header. */ 1906 DEBUG2(printk("%s(): PCI data struct not found " 1907 "pcir_adr=%x.\n", __func__, pcids)); 1908 ret = QLA_FUNCTION_FAILED; 1909 break; 1910 } 1911 1912 /* Read version */ 1913 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 1914 switch (code_type) { 1915 case ROM_CODE_TYPE_BIOS: 1916 /* Intel x86, PC-AT compatible. */ 1917 ha->bios_revision[0] = 1918 qla2x00_read_flash_byte(ha, pcids + 0x12); 1919 ha->bios_revision[1] = 1920 qla2x00_read_flash_byte(ha, pcids + 0x13); 1921 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__, 1922 ha->bios_revision[1], ha->bios_revision[0])); 1923 break; 1924 case ROM_CODE_TYPE_FCODE: 1925 /* Open Firmware standard for PCI (FCode). */ 1926 /* Eeeewww... */ 1927 qla2x00_get_fcode_version(ha, pcids); 1928 break; 1929 case ROM_CODE_TYPE_EFI: 1930 /* Extensible Firmware Interface (EFI). */ 1931 ha->efi_revision[0] = 1932 qla2x00_read_flash_byte(ha, pcids + 0x12); 1933 ha->efi_revision[1] = 1934 qla2x00_read_flash_byte(ha, pcids + 0x13); 1935 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__, 1936 ha->efi_revision[1], ha->efi_revision[0])); 1937 break; 1938 default: 1939 DEBUG2(printk("%s(): Unrecognized code type %x at " 1940 "pcids %x.\n", __func__, code_type, pcids)); 1941 break; 1942 } 1943 1944 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 1945 1946 /* Locate next PCI expansion ROM. */ 1947 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 1948 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 1949 } while (!last_image); 1950 1951 if (IS_QLA2322(ha)) { 1952 /* Read firmware image information. */ 1953 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 1954 dbyte = mbuf; 1955 memset(dbyte, 0, 8); 1956 dcode = (uint16_t *)dbyte; 1957 1958 qla2x00_read_flash_data(ha, dbyte, FA_RISC_CODE_ADDR * 4 + 10, 1959 8); 1960 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n", 1961 __func__, ha->host_no)); 1962 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8)); 1963 1964 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 1965 dcode[2] == 0xffff && dcode[3] == 0xffff) || 1966 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 1967 dcode[3] == 0)) { 1968 DEBUG2(printk("%s(): Unrecognized fw revision at " 1969 "%x.\n", __func__, FA_RISC_CODE_ADDR * 4)); 1970 } else { 1971 /* values are in big endian */ 1972 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 1973 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 1974 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 1975 } 1976 } 1977 1978 qla2x00_flash_disable(ha); 1979 1980 return ret; 1981 } 1982 1983 int 1984 qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf) 1985 { 1986 int ret = QLA_SUCCESS; 1987 uint32_t pcihdr, pcids; 1988 uint32_t *dcode; 1989 uint8_t *bcode; 1990 uint8_t code_type, last_image; 1991 int i; 1992 1993 if (!mbuf) 1994 return QLA_FUNCTION_FAILED; 1995 1996 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 1997 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 1998 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 1999 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2000 2001 dcode = mbuf; 2002 2003 /* Begin with first PCI expansion ROM header. */ 2004 pcihdr = 0; 2005 last_image = 1; 2006 do { 2007 /* Verify PCI expansion ROM header. */ 2008 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20); 2009 bcode = mbuf + (pcihdr % 4); 2010 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) { 2011 /* No signature */ 2012 DEBUG2(printk("scsi(%ld): No matching ROM " 2013 "signature.\n", ha->host_no)); 2014 ret = QLA_FUNCTION_FAILED; 2015 break; 2016 } 2017 2018 /* Locate PCI data structure. */ 2019 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 2020 2021 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20); 2022 bcode = mbuf + (pcihdr % 4); 2023 2024 /* Validate signature of PCI data structure. */ 2025 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 2026 bcode[0x2] != 'I' || bcode[0x3] != 'R') { 2027 /* Incorrect header. */ 2028 DEBUG2(printk("%s(): PCI data struct not found " 2029 "pcir_adr=%x.\n", __func__, pcids)); 2030 ret = QLA_FUNCTION_FAILED; 2031 break; 2032 } 2033 2034 /* Read version */ 2035 code_type = bcode[0x14]; 2036 switch (code_type) { 2037 case ROM_CODE_TYPE_BIOS: 2038 /* Intel x86, PC-AT compatible. */ 2039 ha->bios_revision[0] = bcode[0x12]; 2040 ha->bios_revision[1] = bcode[0x13]; 2041 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__, 2042 ha->bios_revision[1], ha->bios_revision[0])); 2043 break; 2044 case ROM_CODE_TYPE_FCODE: 2045 /* Open Firmware standard for PCI (FCode). */ 2046 ha->fcode_revision[0] = bcode[0x12]; 2047 ha->fcode_revision[1] = bcode[0x13]; 2048 DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__, 2049 ha->fcode_revision[1], ha->fcode_revision[0])); 2050 break; 2051 case ROM_CODE_TYPE_EFI: 2052 /* Extensible Firmware Interface (EFI). */ 2053 ha->efi_revision[0] = bcode[0x12]; 2054 ha->efi_revision[1] = bcode[0x13]; 2055 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__, 2056 ha->efi_revision[1], ha->efi_revision[0])); 2057 break; 2058 default: 2059 DEBUG2(printk("%s(): Unrecognized code type %x at " 2060 "pcids %x.\n", __func__, code_type, pcids)); 2061 break; 2062 } 2063 2064 last_image = bcode[0x15] & BIT_7; 2065 2066 /* Locate next PCI expansion ROM. */ 2067 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 2068 } while (!last_image); 2069 2070 /* Read firmware image information. */ 2071 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2072 dcode = mbuf; 2073 2074 qla24xx_read_flash_data(ha, dcode, FA_RISC_CODE_ADDR + 4, 4); 2075 for (i = 0; i < 4; i++) 2076 dcode[i] = be32_to_cpu(dcode[i]); 2077 2078 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 2079 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 2080 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 2081 dcode[3] == 0)) { 2082 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n", 2083 __func__, FA_RISC_CODE_ADDR)); 2084 } else { 2085 ha->fw_revision[0] = dcode[0]; 2086 ha->fw_revision[1] = dcode[1]; 2087 ha->fw_revision[2] = dcode[2]; 2088 ha->fw_revision[3] = dcode[3]; 2089 } 2090 2091 return ret; 2092 } 2093