1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/delay.h> 9 #include <linux/slab.h> 10 #include <linux/vmalloc.h> 11 #include <linux/uaccess.h> 12 13 /* 14 * NVRAM support routines 15 */ 16 17 /** 18 * qla2x00_lock_nvram_access() - 19 * @ha: HA context 20 */ 21 static void 22 qla2x00_lock_nvram_access(struct qla_hw_data *ha) 23 { 24 uint16_t data; 25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 26 27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 28 data = rd_reg_word(®->nvram); 29 while (data & NVR_BUSY) { 30 udelay(100); 31 data = rd_reg_word(®->nvram); 32 } 33 34 /* Lock resource */ 35 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); 36 rd_reg_word(®->u.isp2300.host_semaphore); 37 udelay(5); 38 data = rd_reg_word(®->u.isp2300.host_semaphore); 39 while ((data & BIT_0) == 0) { 40 /* Lock failed */ 41 udelay(100); 42 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); 43 rd_reg_word(®->u.isp2300.host_semaphore); 44 udelay(5); 45 data = rd_reg_word(®->u.isp2300.host_semaphore); 46 } 47 } 48 } 49 50 /** 51 * qla2x00_unlock_nvram_access() - 52 * @ha: HA context 53 */ 54 static void 55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha) 56 { 57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 58 59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 60 wrt_reg_word(®->u.isp2300.host_semaphore, 0); 61 rd_reg_word(®->u.isp2300.host_semaphore); 62 } 63 } 64 65 /** 66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 67 * @ha: HA context 68 * @data: Serial interface selector 69 */ 70 static void 71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data) 72 { 73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 74 75 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 76 rd_reg_word(®->nvram); /* PCI Posting. */ 77 NVRAM_DELAY(); 78 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_CLOCK | 79 NVR_WRT_ENABLE); 80 rd_reg_word(®->nvram); /* PCI Posting. */ 81 NVRAM_DELAY(); 82 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 83 rd_reg_word(®->nvram); /* PCI Posting. */ 84 NVRAM_DELAY(); 85 } 86 87 /** 88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 89 * NVRAM. 90 * @ha: HA context 91 * @nv_cmd: NVRAM command 92 * 93 * Bit definitions for NVRAM command: 94 * 95 * Bit 26 = start bit 96 * Bit 25, 24 = opcode 97 * Bit 23-16 = address 98 * Bit 15-0 = write data 99 * 100 * Returns the word read from nvram @addr. 101 */ 102 static uint16_t 103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) 104 { 105 uint8_t cnt; 106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 107 uint16_t data = 0; 108 uint16_t reg_data; 109 110 /* Send command to NVRAM. */ 111 nv_cmd <<= 5; 112 for (cnt = 0; cnt < 11; cnt++) { 113 if (nv_cmd & BIT_31) 114 qla2x00_nv_write(ha, NVR_DATA_OUT); 115 else 116 qla2x00_nv_write(ha, 0); 117 nv_cmd <<= 1; 118 } 119 120 /* Read data from NVRAM. */ 121 for (cnt = 0; cnt < 16; cnt++) { 122 wrt_reg_word(®->nvram, NVR_SELECT | NVR_CLOCK); 123 rd_reg_word(®->nvram); /* PCI Posting. */ 124 NVRAM_DELAY(); 125 data <<= 1; 126 reg_data = rd_reg_word(®->nvram); 127 if (reg_data & NVR_DATA_IN) 128 data |= BIT_0; 129 wrt_reg_word(®->nvram, NVR_SELECT); 130 rd_reg_word(®->nvram); /* PCI Posting. */ 131 NVRAM_DELAY(); 132 } 133 134 /* Deselect chip. */ 135 wrt_reg_word(®->nvram, NVR_DESELECT); 136 rd_reg_word(®->nvram); /* PCI Posting. */ 137 NVRAM_DELAY(); 138 139 return data; 140 } 141 142 143 /** 144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 145 * request routine to get the word from NVRAM. 146 * @ha: HA context 147 * @addr: Address in NVRAM to read 148 * 149 * Returns the word read from nvram @addr. 150 */ 151 static uint16_t 152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) 153 { 154 uint16_t data; 155 uint32_t nv_cmd; 156 157 nv_cmd = addr << 16; 158 nv_cmd |= NV_READ_OP; 159 data = qla2x00_nvram_request(ha, nv_cmd); 160 161 return (data); 162 } 163 164 /** 165 * qla2x00_nv_deselect() - Deselect NVRAM operations. 166 * @ha: HA context 167 */ 168 static void 169 qla2x00_nv_deselect(struct qla_hw_data *ha) 170 { 171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 172 173 wrt_reg_word(®->nvram, NVR_DESELECT); 174 rd_reg_word(®->nvram); /* PCI Posting. */ 175 NVRAM_DELAY(); 176 } 177 178 /** 179 * qla2x00_write_nvram_word() - Write NVRAM data. 180 * @ha: HA context 181 * @addr: Address in NVRAM to write 182 * @data: word to program 183 */ 184 static void 185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, __le16 data) 186 { 187 int count; 188 uint16_t word; 189 uint32_t nv_cmd, wait_cnt; 190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 191 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 192 193 qla2x00_nv_write(ha, NVR_DATA_OUT); 194 qla2x00_nv_write(ha, 0); 195 qla2x00_nv_write(ha, 0); 196 197 for (word = 0; word < 8; word++) 198 qla2x00_nv_write(ha, NVR_DATA_OUT); 199 200 qla2x00_nv_deselect(ha); 201 202 /* Write data */ 203 nv_cmd = (addr << 16) | NV_WRITE_OP; 204 nv_cmd |= (__force u16)data; 205 nv_cmd <<= 5; 206 for (count = 0; count < 27; count++) { 207 if (nv_cmd & BIT_31) 208 qla2x00_nv_write(ha, NVR_DATA_OUT); 209 else 210 qla2x00_nv_write(ha, 0); 211 212 nv_cmd <<= 1; 213 } 214 215 qla2x00_nv_deselect(ha); 216 217 /* Wait for NVRAM to become ready */ 218 wrt_reg_word(®->nvram, NVR_SELECT); 219 rd_reg_word(®->nvram); /* PCI Posting. */ 220 wait_cnt = NVR_WAIT_CNT; 221 do { 222 if (!--wait_cnt) { 223 ql_dbg(ql_dbg_user, vha, 0x708d, 224 "NVRAM didn't go ready...\n"); 225 break; 226 } 227 NVRAM_DELAY(); 228 word = rd_reg_word(®->nvram); 229 } while ((word & NVR_DATA_IN) == 0); 230 231 qla2x00_nv_deselect(ha); 232 233 /* Disable writes */ 234 qla2x00_nv_write(ha, NVR_DATA_OUT); 235 for (count = 0; count < 10; count++) 236 qla2x00_nv_write(ha, 0); 237 238 qla2x00_nv_deselect(ha); 239 } 240 241 static int 242 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, 243 __le16 data, uint32_t tmo) 244 { 245 int ret, count; 246 uint16_t word; 247 uint32_t nv_cmd; 248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 249 250 ret = QLA_SUCCESS; 251 252 qla2x00_nv_write(ha, NVR_DATA_OUT); 253 qla2x00_nv_write(ha, 0); 254 qla2x00_nv_write(ha, 0); 255 256 for (word = 0; word < 8; word++) 257 qla2x00_nv_write(ha, NVR_DATA_OUT); 258 259 qla2x00_nv_deselect(ha); 260 261 /* Write data */ 262 nv_cmd = (addr << 16) | NV_WRITE_OP; 263 nv_cmd |= (__force u16)data; 264 nv_cmd <<= 5; 265 for (count = 0; count < 27; count++) { 266 if (nv_cmd & BIT_31) 267 qla2x00_nv_write(ha, NVR_DATA_OUT); 268 else 269 qla2x00_nv_write(ha, 0); 270 271 nv_cmd <<= 1; 272 } 273 274 qla2x00_nv_deselect(ha); 275 276 /* Wait for NVRAM to become ready */ 277 wrt_reg_word(®->nvram, NVR_SELECT); 278 rd_reg_word(®->nvram); /* PCI Posting. */ 279 do { 280 NVRAM_DELAY(); 281 word = rd_reg_word(®->nvram); 282 if (!--tmo) { 283 ret = QLA_FUNCTION_FAILED; 284 break; 285 } 286 } while ((word & NVR_DATA_IN) == 0); 287 288 qla2x00_nv_deselect(ha); 289 290 /* Disable writes */ 291 qla2x00_nv_write(ha, NVR_DATA_OUT); 292 for (count = 0; count < 10; count++) 293 qla2x00_nv_write(ha, 0); 294 295 qla2x00_nv_deselect(ha); 296 297 return ret; 298 } 299 300 /** 301 * qla2x00_clear_nvram_protection() - 302 * @ha: HA context 303 */ 304 static int 305 qla2x00_clear_nvram_protection(struct qla_hw_data *ha) 306 { 307 int ret, stat; 308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 309 uint32_t word, wait_cnt; 310 __le16 wprot, wprot_old; 311 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 312 313 /* Clear NVRAM write protection. */ 314 ret = QLA_FUNCTION_FAILED; 315 316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 318 cpu_to_le16(0x1234), 100000); 319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 320 if (stat != QLA_SUCCESS || wprot != cpu_to_le16(0x1234)) { 321 /* Write enable. */ 322 qla2x00_nv_write(ha, NVR_DATA_OUT); 323 qla2x00_nv_write(ha, 0); 324 qla2x00_nv_write(ha, 0); 325 for (word = 0; word < 8; word++) 326 qla2x00_nv_write(ha, NVR_DATA_OUT); 327 328 qla2x00_nv_deselect(ha); 329 330 /* Enable protection register. */ 331 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 332 qla2x00_nv_write(ha, NVR_PR_ENABLE); 333 qla2x00_nv_write(ha, NVR_PR_ENABLE); 334 for (word = 0; word < 8; word++) 335 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 336 337 qla2x00_nv_deselect(ha); 338 339 /* Clear protection register (ffff is cleared). */ 340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 343 for (word = 0; word < 8; word++) 344 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 345 346 qla2x00_nv_deselect(ha); 347 348 /* Wait for NVRAM to become ready. */ 349 wrt_reg_word(®->nvram, NVR_SELECT); 350 rd_reg_word(®->nvram); /* PCI Posting. */ 351 wait_cnt = NVR_WAIT_CNT; 352 do { 353 if (!--wait_cnt) { 354 ql_dbg(ql_dbg_user, vha, 0x708e, 355 "NVRAM didn't go ready...\n"); 356 break; 357 } 358 NVRAM_DELAY(); 359 word = rd_reg_word(®->nvram); 360 } while ((word & NVR_DATA_IN) == 0); 361 362 if (wait_cnt) 363 ret = QLA_SUCCESS; 364 } else 365 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 366 367 return ret; 368 } 369 370 static void 371 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) 372 { 373 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 374 uint32_t word, wait_cnt; 375 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 376 377 if (stat != QLA_SUCCESS) 378 return; 379 380 /* Set NVRAM write protection. */ 381 /* Write enable. */ 382 qla2x00_nv_write(ha, NVR_DATA_OUT); 383 qla2x00_nv_write(ha, 0); 384 qla2x00_nv_write(ha, 0); 385 for (word = 0; word < 8; word++) 386 qla2x00_nv_write(ha, NVR_DATA_OUT); 387 388 qla2x00_nv_deselect(ha); 389 390 /* Enable protection register. */ 391 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 392 qla2x00_nv_write(ha, NVR_PR_ENABLE); 393 qla2x00_nv_write(ha, NVR_PR_ENABLE); 394 for (word = 0; word < 8; word++) 395 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 396 397 qla2x00_nv_deselect(ha); 398 399 /* Enable protection register. */ 400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 401 qla2x00_nv_write(ha, NVR_PR_ENABLE); 402 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 403 for (word = 0; word < 8; word++) 404 qla2x00_nv_write(ha, NVR_PR_ENABLE); 405 406 qla2x00_nv_deselect(ha); 407 408 /* Wait for NVRAM to become ready. */ 409 wrt_reg_word(®->nvram, NVR_SELECT); 410 rd_reg_word(®->nvram); /* PCI Posting. */ 411 wait_cnt = NVR_WAIT_CNT; 412 do { 413 if (!--wait_cnt) { 414 ql_dbg(ql_dbg_user, vha, 0x708f, 415 "NVRAM didn't go ready...\n"); 416 break; 417 } 418 NVRAM_DELAY(); 419 word = rd_reg_word(®->nvram); 420 } while ((word & NVR_DATA_IN) == 0); 421 } 422 423 424 /*****************************************************************************/ 425 /* Flash Manipulation Routines */ 426 /*****************************************************************************/ 427 428 static inline uint32_t 429 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) 430 { 431 return ha->flash_conf_off + faddr; 432 } 433 434 static inline uint32_t 435 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) 436 { 437 return ha->flash_data_off + faddr; 438 } 439 440 static inline uint32_t 441 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) 442 { 443 return ha->nvram_conf_off + naddr; 444 } 445 446 static inline uint32_t 447 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) 448 { 449 return ha->nvram_data_off + naddr; 450 } 451 452 static int 453 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t *data) 454 { 455 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 456 ulong cnt = 30000; 457 458 wrt_reg_dword(®->flash_addr, addr & ~FARX_DATA_FLAG); 459 460 while (cnt--) { 461 if (rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG) { 462 *data = rd_reg_dword(®->flash_data); 463 return QLA_SUCCESS; 464 } 465 udelay(10); 466 cond_resched(); 467 } 468 469 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 470 "Flash read dword at %x timeout.\n", addr); 471 *data = 0xDEADDEAD; 472 return QLA_FUNCTION_TIMEOUT; 473 } 474 475 int 476 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 477 uint32_t dwords) 478 { 479 ulong i; 480 int ret = QLA_SUCCESS; 481 struct qla_hw_data *ha = vha->hw; 482 483 /* Dword reads to flash. */ 484 faddr = flash_data_addr(ha, faddr); 485 for (i = 0; i < dwords; i++, faddr++, dwptr++) { 486 ret = qla24xx_read_flash_dword(ha, faddr, dwptr); 487 if (ret != QLA_SUCCESS) 488 break; 489 cpu_to_le32s(dwptr); 490 } 491 492 return ret; 493 } 494 495 static int 496 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) 497 { 498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 499 ulong cnt = 500000; 500 501 wrt_reg_dword(®->flash_data, data); 502 wrt_reg_dword(®->flash_addr, addr | FARX_DATA_FLAG); 503 504 while (cnt--) { 505 if (!(rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG)) 506 return QLA_SUCCESS; 507 udelay(10); 508 cond_resched(); 509 } 510 511 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 512 "Flash write dword at %x timeout.\n", addr); 513 return QLA_FUNCTION_TIMEOUT; 514 } 515 516 static void 517 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 518 uint8_t *flash_id) 519 { 520 uint32_t faddr, ids = 0; 521 522 *man_id = *flash_id = 0; 523 524 faddr = flash_conf_addr(ha, 0x03ab); 525 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 526 *man_id = LSB(ids); 527 *flash_id = MSB(ids); 528 } 529 530 /* Check if man_id and flash_id are valid. */ 531 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 532 /* Read information using 0x9f opcode 533 * Device ID, Mfg ID would be read in the format: 534 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 535 * Example: ATMEL 0x00 01 45 1F 536 * Extract MFG and Dev ID from last two bytes. 537 */ 538 faddr = flash_conf_addr(ha, 0x009f); 539 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 540 *man_id = LSB(ids); 541 *flash_id = MSB(ids); 542 } 543 } 544 } 545 546 static int 547 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) 548 { 549 const char *loc, *locations[] = { "DEF", "PCI" }; 550 uint32_t pcihdr, pcids; 551 uint16_t cnt, chksum; 552 __le16 *wptr; 553 struct qla_hw_data *ha = vha->hw; 554 struct req_que *req = ha->req_q_map[0]; 555 struct qla_flt_location *fltl = (void *)req->ring; 556 uint32_t *dcode = (uint32_t *)req->ring; 557 uint8_t *buf = (void *)req->ring, *bcode, last_image; 558 559 /* 560 * FLT-location structure resides after the last PCI region. 561 */ 562 563 /* Begin with sane defaults. */ 564 loc = locations[0]; 565 *start = 0; 566 if (IS_QLA24XX_TYPE(ha)) 567 *start = FA_FLASH_LAYOUT_ADDR_24; 568 else if (IS_QLA25XX(ha)) 569 *start = FA_FLASH_LAYOUT_ADDR; 570 else if (IS_QLA81XX(ha)) 571 *start = FA_FLASH_LAYOUT_ADDR_81; 572 else if (IS_P3P_TYPE(ha)) { 573 *start = FA_FLASH_LAYOUT_ADDR_82; 574 goto end; 575 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 576 *start = FA_FLASH_LAYOUT_ADDR_83; 577 goto end; 578 } else if (IS_QLA28XX(ha)) { 579 *start = FA_FLASH_LAYOUT_ADDR_28; 580 goto end; 581 } 582 583 /* Begin with first PCI expansion ROM header. */ 584 pcihdr = 0; 585 do { 586 /* Verify PCI expansion ROM header. */ 587 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 588 bcode = buf + (pcihdr % 4); 589 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) 590 goto end; 591 592 /* Locate PCI data structure. */ 593 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 594 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 595 bcode = buf + (pcihdr % 4); 596 597 /* Validate signature of PCI data structure. */ 598 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 599 bcode[0x2] != 'I' || bcode[0x3] != 'R') 600 goto end; 601 602 last_image = bcode[0x15] & BIT_7; 603 604 /* Locate next PCI expansion ROM. */ 605 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 606 } while (!last_image); 607 608 /* Now verify FLT-location structure. */ 609 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, sizeof(*fltl) >> 2); 610 if (memcmp(fltl->sig, "QFLT", 4)) 611 goto end; 612 613 wptr = (__force __le16 *)req->ring; 614 cnt = sizeof(*fltl) / sizeof(*wptr); 615 for (chksum = 0; cnt--; wptr++) 616 chksum += le16_to_cpu(*wptr); 617 if (chksum) { 618 ql_log(ql_log_fatal, vha, 0x0045, 619 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); 620 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e, 621 fltl, sizeof(*fltl)); 622 return QLA_FUNCTION_FAILED; 623 } 624 625 /* Good data. Use specified location. */ 626 loc = locations[1]; 627 *start = (le16_to_cpu(fltl->start_hi) << 16 | 628 le16_to_cpu(fltl->start_lo)) >> 2; 629 end: 630 ql_dbg(ql_dbg_init, vha, 0x0046, 631 "FLTL[%s] = 0x%x.\n", 632 loc, *start); 633 return QLA_SUCCESS; 634 } 635 636 static void 637 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) 638 { 639 const char *locations[] = { "DEF", "FLT" }, *loc = locations[1]; 640 const uint32_t def_fw[] = 641 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 }; 642 const uint32_t def_boot[] = 643 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 }; 644 const uint32_t def_vpd_nvram[] = 645 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 }; 646 const uint32_t def_vpd0[] = 647 { 0, 0, FA_VPD0_ADDR_81 }; 648 const uint32_t def_vpd1[] = 649 { 0, 0, FA_VPD1_ADDR_81 }; 650 const uint32_t def_nvram0[] = 651 { 0, 0, FA_NVRAM0_ADDR_81 }; 652 const uint32_t def_nvram1[] = 653 { 0, 0, FA_NVRAM1_ADDR_81 }; 654 const uint32_t def_fdt[] = 655 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR, 656 FA_FLASH_DESCR_ADDR_81 }; 657 const uint32_t def_npiv_conf0[] = 658 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR, 659 FA_NPIV_CONF0_ADDR_81 }; 660 const uint32_t def_npiv_conf1[] = 661 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR, 662 FA_NPIV_CONF1_ADDR_81 }; 663 const uint32_t fcp_prio_cfg0[] = 664 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25, 665 0 }; 666 const uint32_t fcp_prio_cfg1[] = 667 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25, 668 0 }; 669 670 struct qla_hw_data *ha = vha->hw; 671 uint32_t def = IS_QLA81XX(ha) ? 2 : IS_QLA25XX(ha) ? 1 : 0; 672 struct qla_flt_header *flt = ha->flt; 673 struct qla_flt_region *region = &flt->region[0]; 674 __le16 *wptr; 675 uint16_t cnt, chksum; 676 uint32_t start; 677 678 /* Assign FCP prio region since older adapters may not have FLT, or 679 FCP prio region in it's FLT. 680 */ 681 ha->flt_region_fcp_prio = (ha->port_no == 0) ? 682 fcp_prio_cfg0[def] : fcp_prio_cfg1[def]; 683 684 ha->flt_region_flt = flt_addr; 685 wptr = (__force __le16 *)ha->flt; 686 ha->isp_ops->read_optrom(vha, flt, flt_addr << 2, 687 (sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE)); 688 689 if (le16_to_cpu(*wptr) == 0xffff) 690 goto no_flash_data; 691 if (flt->version != cpu_to_le16(1)) { 692 ql_log(ql_log_warn, vha, 0x0047, 693 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 694 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 695 le16_to_cpu(flt->checksum)); 696 goto no_flash_data; 697 } 698 699 cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr); 700 for (chksum = 0; cnt--; wptr++) 701 chksum += le16_to_cpu(*wptr); 702 if (chksum) { 703 ql_log(ql_log_fatal, vha, 0x0048, 704 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 705 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 706 le16_to_cpu(flt->checksum)); 707 goto no_flash_data; 708 } 709 710 cnt = le16_to_cpu(flt->length) / sizeof(*region); 711 for ( ; cnt; cnt--, region++) { 712 /* Store addresses as DWORD offsets. */ 713 start = le32_to_cpu(region->start) >> 2; 714 ql_dbg(ql_dbg_init, vha, 0x0049, 715 "FLT[%#x]: start=%#x end=%#x size=%#x.\n", 716 le16_to_cpu(region->code), start, 717 le32_to_cpu(region->end) >> 2, 718 le32_to_cpu(region->size) >> 2); 719 if (region->attribute) 720 ql_log(ql_dbg_init, vha, 0xffff, 721 "Region %x is secure\n", region->code); 722 723 switch (le16_to_cpu(region->code)) { 724 case FLT_REG_FCOE_FW: 725 if (!IS_QLA8031(ha)) 726 break; 727 ha->flt_region_fw = start; 728 break; 729 case FLT_REG_FW: 730 if (IS_QLA8031(ha)) 731 break; 732 ha->flt_region_fw = start; 733 break; 734 case FLT_REG_BOOT_CODE: 735 ha->flt_region_boot = start; 736 break; 737 case FLT_REG_VPD_0: 738 if (IS_QLA8031(ha)) 739 break; 740 ha->flt_region_vpd_nvram = start; 741 if (IS_P3P_TYPE(ha)) 742 break; 743 if (ha->port_no == 0) 744 ha->flt_region_vpd = start; 745 break; 746 case FLT_REG_VPD_1: 747 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 748 break; 749 if (ha->port_no == 1) 750 ha->flt_region_vpd = start; 751 break; 752 case FLT_REG_VPD_2: 753 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 754 break; 755 if (ha->port_no == 2) 756 ha->flt_region_vpd = start; 757 break; 758 case FLT_REG_VPD_3: 759 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 760 break; 761 if (ha->port_no == 3) 762 ha->flt_region_vpd = start; 763 break; 764 case FLT_REG_NVRAM_0: 765 if (IS_QLA8031(ha)) 766 break; 767 if (ha->port_no == 0) 768 ha->flt_region_nvram = start; 769 break; 770 case FLT_REG_NVRAM_1: 771 if (IS_QLA8031(ha)) 772 break; 773 if (ha->port_no == 1) 774 ha->flt_region_nvram = start; 775 break; 776 case FLT_REG_NVRAM_2: 777 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 778 break; 779 if (ha->port_no == 2) 780 ha->flt_region_nvram = start; 781 break; 782 case FLT_REG_NVRAM_3: 783 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 784 break; 785 if (ha->port_no == 3) 786 ha->flt_region_nvram = start; 787 break; 788 case FLT_REG_FDT: 789 ha->flt_region_fdt = start; 790 break; 791 case FLT_REG_NPIV_CONF_0: 792 if (ha->port_no == 0) 793 ha->flt_region_npiv_conf = start; 794 break; 795 case FLT_REG_NPIV_CONF_1: 796 if (ha->port_no == 1) 797 ha->flt_region_npiv_conf = start; 798 break; 799 case FLT_REG_GOLD_FW: 800 ha->flt_region_gold_fw = start; 801 break; 802 case FLT_REG_FCP_PRIO_0: 803 if (ha->port_no == 0) 804 ha->flt_region_fcp_prio = start; 805 break; 806 case FLT_REG_FCP_PRIO_1: 807 if (ha->port_no == 1) 808 ha->flt_region_fcp_prio = start; 809 break; 810 case FLT_REG_BOOT_CODE_82XX: 811 ha->flt_region_boot = start; 812 break; 813 case FLT_REG_BOOT_CODE_8044: 814 if (IS_QLA8044(ha)) 815 ha->flt_region_boot = start; 816 break; 817 case FLT_REG_FW_82XX: 818 ha->flt_region_fw = start; 819 break; 820 case FLT_REG_CNA_FW: 821 if (IS_CNA_CAPABLE(ha)) 822 ha->flt_region_fw = start; 823 break; 824 case FLT_REG_GOLD_FW_82XX: 825 ha->flt_region_gold_fw = start; 826 break; 827 case FLT_REG_BOOTLOAD_82XX: 828 ha->flt_region_bootload = start; 829 break; 830 case FLT_REG_VPD_8XXX: 831 if (IS_CNA_CAPABLE(ha)) 832 ha->flt_region_vpd = start; 833 break; 834 case FLT_REG_FCOE_NVRAM_0: 835 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 836 break; 837 if (ha->port_no == 0) 838 ha->flt_region_nvram = start; 839 break; 840 case FLT_REG_FCOE_NVRAM_1: 841 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 842 break; 843 if (ha->port_no == 1) 844 ha->flt_region_nvram = start; 845 break; 846 case FLT_REG_IMG_PRI_27XX: 847 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 848 ha->flt_region_img_status_pri = start; 849 break; 850 case FLT_REG_IMG_SEC_27XX: 851 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 852 ha->flt_region_img_status_sec = start; 853 break; 854 case FLT_REG_FW_SEC_27XX: 855 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 856 ha->flt_region_fw_sec = start; 857 break; 858 case FLT_REG_BOOTLOAD_SEC_27XX: 859 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 860 ha->flt_region_boot_sec = start; 861 break; 862 case FLT_REG_AUX_IMG_PRI_28XX: 863 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 864 ha->flt_region_aux_img_status_pri = start; 865 break; 866 case FLT_REG_AUX_IMG_SEC_28XX: 867 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 868 ha->flt_region_aux_img_status_sec = start; 869 break; 870 case FLT_REG_NVRAM_SEC_28XX_0: 871 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 872 if (ha->port_no == 0) 873 ha->flt_region_nvram_sec = start; 874 break; 875 case FLT_REG_NVRAM_SEC_28XX_1: 876 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 877 if (ha->port_no == 1) 878 ha->flt_region_nvram_sec = start; 879 break; 880 case FLT_REG_NVRAM_SEC_28XX_2: 881 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 882 if (ha->port_no == 2) 883 ha->flt_region_nvram_sec = start; 884 break; 885 case FLT_REG_NVRAM_SEC_28XX_3: 886 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 887 if (ha->port_no == 3) 888 ha->flt_region_nvram_sec = start; 889 break; 890 case FLT_REG_VPD_SEC_27XX_0: 891 case FLT_REG_VPD_SEC_28XX_0: 892 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 893 ha->flt_region_vpd_nvram_sec = start; 894 if (ha->port_no == 0) 895 ha->flt_region_vpd_sec = start; 896 } 897 break; 898 case FLT_REG_VPD_SEC_27XX_1: 899 case FLT_REG_VPD_SEC_28XX_1: 900 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 901 if (ha->port_no == 1) 902 ha->flt_region_vpd_sec = start; 903 break; 904 case FLT_REG_VPD_SEC_27XX_2: 905 case FLT_REG_VPD_SEC_28XX_2: 906 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 907 if (ha->port_no == 2) 908 ha->flt_region_vpd_sec = start; 909 break; 910 case FLT_REG_VPD_SEC_27XX_3: 911 case FLT_REG_VPD_SEC_28XX_3: 912 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 913 if (ha->port_no == 3) 914 ha->flt_region_vpd_sec = start; 915 break; 916 } 917 } 918 goto done; 919 920 no_flash_data: 921 /* Use hardcoded defaults. */ 922 loc = locations[0]; 923 ha->flt_region_fw = def_fw[def]; 924 ha->flt_region_boot = def_boot[def]; 925 ha->flt_region_vpd_nvram = def_vpd_nvram[def]; 926 ha->flt_region_vpd = (ha->port_no == 0) ? 927 def_vpd0[def] : def_vpd1[def]; 928 ha->flt_region_nvram = (ha->port_no == 0) ? 929 def_nvram0[def] : def_nvram1[def]; 930 ha->flt_region_fdt = def_fdt[def]; 931 ha->flt_region_npiv_conf = (ha->port_no == 0) ? 932 def_npiv_conf0[def] : def_npiv_conf1[def]; 933 done: 934 ql_dbg(ql_dbg_init, vha, 0x004a, 935 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x " 936 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n", 937 loc, ha->flt_region_boot, ha->flt_region_fw, 938 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram, 939 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf, 940 ha->flt_region_fcp_prio); 941 } 942 943 static void 944 qla2xxx_get_fdt_info(scsi_qla_host_t *vha) 945 { 946 #define FLASH_BLK_SIZE_4K 0x1000 947 #define FLASH_BLK_SIZE_32K 0x8000 948 #define FLASH_BLK_SIZE_64K 0x10000 949 const char *loc, *locations[] = { "MID", "FDT" }; 950 struct qla_hw_data *ha = vha->hw; 951 struct req_que *req = ha->req_q_map[0]; 952 uint16_t cnt, chksum; 953 __le16 *wptr = (__force __le16 *)req->ring; 954 struct qla_fdt_layout *fdt = (struct qla_fdt_layout *)req->ring; 955 uint8_t man_id, flash_id; 956 uint16_t mid = 0, fid = 0; 957 958 ha->isp_ops->read_optrom(vha, fdt, ha->flt_region_fdt << 2, 959 OPTROM_BURST_DWORDS); 960 if (le16_to_cpu(*wptr) == 0xffff) 961 goto no_flash_data; 962 if (memcmp(fdt->sig, "QLID", 4)) 963 goto no_flash_data; 964 965 for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++) 966 chksum += le16_to_cpu(*wptr); 967 if (chksum) { 968 ql_dbg(ql_dbg_init, vha, 0x004c, 969 "Inconsistent FDT detected:" 970 " checksum=0x%x id=%c version0x%x.\n", chksum, 971 fdt->sig[0], le16_to_cpu(fdt->version)); 972 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113, 973 fdt, sizeof(*fdt)); 974 goto no_flash_data; 975 } 976 977 loc = locations[1]; 978 mid = le16_to_cpu(fdt->man_id); 979 fid = le16_to_cpu(fdt->id); 980 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 981 ha->fdt_wrt_enable = fdt->wrt_enable_bits; 982 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd; 983 if (IS_QLA8044(ha)) 984 ha->fdt_erase_cmd = fdt->erase_cmd; 985 else 986 ha->fdt_erase_cmd = 987 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); 988 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 989 if (fdt->unprotect_sec_cmd) { 990 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | 991 fdt->unprotect_sec_cmd); 992 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 993 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd) : 994 flash_conf_addr(ha, 0x0336); 995 } 996 goto done; 997 no_flash_data: 998 loc = locations[0]; 999 if (IS_P3P_TYPE(ha)) { 1000 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1001 goto done; 1002 } 1003 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 1004 mid = man_id; 1005 fid = flash_id; 1006 ha->fdt_wrt_disable = 0x9c; 1007 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); 1008 switch (man_id) { 1009 case 0xbf: /* STT flash. */ 1010 if (flash_id == 0x8e) 1011 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1012 else 1013 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 1014 1015 if (flash_id == 0x80) 1016 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); 1017 break; 1018 case 0x13: /* ST M25P80. */ 1019 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1020 break; 1021 case 0x1f: /* Atmel 26DF081A. */ 1022 ha->fdt_block_size = FLASH_BLK_SIZE_4K; 1023 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); 1024 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); 1025 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); 1026 break; 1027 default: 1028 /* Default to 64 kb sector size. */ 1029 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1030 break; 1031 } 1032 done: 1033 ql_dbg(ql_dbg_init, vha, 0x004d, 1034 "FDT[%s]: (0x%x/0x%x) erase=0x%x " 1035 "pr=%x wrtd=0x%x blk=0x%x.\n", 1036 loc, mid, fid, 1037 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, 1038 ha->fdt_wrt_disable, ha->fdt_block_size); 1039 1040 } 1041 1042 static void 1043 qla2xxx_get_idc_param(scsi_qla_host_t *vha) 1044 { 1045 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 1046 __le32 *wptr; 1047 struct qla_hw_data *ha = vha->hw; 1048 struct req_que *req = ha->req_q_map[0]; 1049 1050 if (!(IS_P3P_TYPE(ha))) 1051 return; 1052 1053 wptr = (__force __le32 *)req->ring; 1054 ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8); 1055 1056 if (*wptr == cpu_to_le32(0xffffffff)) { 1057 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; 1058 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; 1059 } else { 1060 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr); 1061 wptr++; 1062 ha->fcoe_reset_timeout = le32_to_cpu(*wptr); 1063 } 1064 ql_dbg(ql_dbg_init, vha, 0x004e, 1065 "fcoe_dev_init_timeout=%d " 1066 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout, 1067 ha->fcoe_reset_timeout); 1068 return; 1069 } 1070 1071 int 1072 qla2xxx_get_flash_info(scsi_qla_host_t *vha) 1073 { 1074 int ret; 1075 uint32_t flt_addr; 1076 struct qla_hw_data *ha = vha->hw; 1077 1078 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1079 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && 1080 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1081 return QLA_SUCCESS; 1082 1083 ret = qla2xxx_find_flt_start(vha, &flt_addr); 1084 if (ret != QLA_SUCCESS) 1085 return ret; 1086 1087 qla2xxx_get_flt_info(vha, flt_addr); 1088 qla2xxx_get_fdt_info(vha); 1089 qla2xxx_get_idc_param(vha); 1090 1091 return QLA_SUCCESS; 1092 } 1093 1094 void 1095 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) 1096 { 1097 #define NPIV_CONFIG_SIZE (16*1024) 1098 void *data; 1099 __le16 *wptr; 1100 uint16_t cnt, chksum; 1101 int i; 1102 struct qla_npiv_header hdr; 1103 struct qla_npiv_entry *entry; 1104 struct qla_hw_data *ha = vha->hw; 1105 1106 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1107 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha)) 1108 return; 1109 1110 if (ha->flags.nic_core_reset_hdlr_active) 1111 return; 1112 1113 if (IS_QLA8044(ha)) 1114 return; 1115 1116 ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2, 1117 sizeof(struct qla_npiv_header)); 1118 if (hdr.version == cpu_to_le16(0xffff)) 1119 return; 1120 if (hdr.version != cpu_to_le16(1)) { 1121 ql_dbg(ql_dbg_user, vha, 0x7090, 1122 "Unsupported NPIV-Config " 1123 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1124 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1125 le16_to_cpu(hdr.checksum)); 1126 return; 1127 } 1128 1129 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); 1130 if (!data) { 1131 ql_log(ql_log_warn, vha, 0x7091, 1132 "Unable to allocate memory for data.\n"); 1133 return; 1134 } 1135 1136 ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2, 1137 NPIV_CONFIG_SIZE); 1138 1139 cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1; 1140 for (wptr = data, chksum = 0; cnt--; wptr++) 1141 chksum += le16_to_cpu(*wptr); 1142 if (chksum) { 1143 ql_dbg(ql_dbg_user, vha, 0x7092, 1144 "Inconsistent NPIV-Config " 1145 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1146 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1147 le16_to_cpu(hdr.checksum)); 1148 goto done; 1149 } 1150 1151 entry = data + sizeof(struct qla_npiv_header); 1152 cnt = le16_to_cpu(hdr.entries); 1153 for (i = 0; cnt; cnt--, entry++, i++) { 1154 uint16_t flags; 1155 struct fc_vport_identifiers vid; 1156 struct fc_vport *vport; 1157 1158 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); 1159 1160 flags = le16_to_cpu(entry->flags); 1161 if (flags == 0xffff) 1162 continue; 1163 if ((flags & BIT_0) == 0) 1164 continue; 1165 1166 memset(&vid, 0, sizeof(vid)); 1167 vid.roles = FC_PORT_ROLE_FCP_INITIATOR; 1168 vid.vport_type = FC_PORTTYPE_NPIV; 1169 vid.disable = false; 1170 vid.port_name = wwn_to_u64(entry->port_name); 1171 vid.node_name = wwn_to_u64(entry->node_name); 1172 1173 ql_dbg(ql_dbg_user, vha, 0x7093, 1174 "NPIV[%02x]: wwpn=%llx wwnn=%llx vf_id=%#x Q_qos=%#x F_qos=%#x.\n", 1175 cnt, vid.port_name, vid.node_name, 1176 le16_to_cpu(entry->vf_id), 1177 entry->q_qos, entry->f_qos); 1178 1179 if (i < QLA_PRECONFIG_VPORTS) { 1180 vport = fc_vport_create(vha->host, 0, &vid); 1181 if (!vport) 1182 ql_log(ql_log_warn, vha, 0x7094, 1183 "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n", 1184 cnt, vid.port_name, vid.node_name); 1185 } 1186 } 1187 done: 1188 kfree(data); 1189 } 1190 1191 static int 1192 qla24xx_unprotect_flash(scsi_qla_host_t *vha) 1193 { 1194 struct qla_hw_data *ha = vha->hw; 1195 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1196 1197 if (ha->flags.fac_supported) 1198 return qla81xx_fac_do_write_enable(vha, 1); 1199 1200 /* Enable flash write. */ 1201 wrt_reg_dword(®->ctrl_status, 1202 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); 1203 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1204 1205 if (!ha->fdt_wrt_disable) 1206 goto done; 1207 1208 /* Disable flash write-protection, first clear SR protection bit */ 1209 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1210 /* Then write zero again to clear remaining SR bits.*/ 1211 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1212 done: 1213 return QLA_SUCCESS; 1214 } 1215 1216 static int 1217 qla24xx_protect_flash(scsi_qla_host_t *vha) 1218 { 1219 struct qla_hw_data *ha = vha->hw; 1220 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1221 ulong cnt = 300; 1222 uint32_t faddr, dword; 1223 1224 if (ha->flags.fac_supported) 1225 return qla81xx_fac_do_write_enable(vha, 0); 1226 1227 if (!ha->fdt_wrt_disable) 1228 goto skip_wrt_protect; 1229 1230 /* Enable flash write-protection and wait for completion. */ 1231 faddr = flash_conf_addr(ha, 0x101); 1232 qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable); 1233 faddr = flash_conf_addr(ha, 0x5); 1234 while (cnt--) { 1235 if (!qla24xx_read_flash_dword(ha, faddr, &dword)) { 1236 if (!(dword & BIT_0)) 1237 break; 1238 } 1239 udelay(10); 1240 } 1241 1242 skip_wrt_protect: 1243 /* Disable flash write. */ 1244 wrt_reg_dword(®->ctrl_status, 1245 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1246 1247 return QLA_SUCCESS; 1248 } 1249 1250 static int 1251 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) 1252 { 1253 struct qla_hw_data *ha = vha->hw; 1254 uint32_t start, finish; 1255 1256 if (ha->flags.fac_supported) { 1257 start = fdata >> 2; 1258 finish = start + (ha->fdt_block_size >> 2) - 1; 1259 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha, 1260 start), flash_data_addr(ha, finish)); 1261 } 1262 1263 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, 1264 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) | 1265 ((fdata >> 16) & 0xff)); 1266 } 1267 1268 static int 1269 qla24xx_write_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr, 1270 uint32_t dwords) 1271 { 1272 int ret; 1273 ulong liter; 1274 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 1275 uint32_t sec_mask, rest_addr, fdata; 1276 dma_addr_t optrom_dma; 1277 void *optrom = NULL; 1278 struct qla_hw_data *ha = vha->hw; 1279 1280 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 1281 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1282 goto next; 1283 1284 /* Allocate dma buffer for burst write */ 1285 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 1286 &optrom_dma, GFP_KERNEL); 1287 if (!optrom) { 1288 ql_log(ql_log_warn, vha, 0x7095, 1289 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 1290 } 1291 1292 next: 1293 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1294 "Unprotect flash...\n"); 1295 ret = qla24xx_unprotect_flash(vha); 1296 if (ret) { 1297 ql_log(ql_log_warn, vha, 0x7096, 1298 "Failed to unprotect flash.\n"); 1299 goto done; 1300 } 1301 1302 rest_addr = (ha->fdt_block_size >> 2) - 1; 1303 sec_mask = ~rest_addr; 1304 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 1305 fdata = (faddr & sec_mask) << 2; 1306 1307 /* Are we at the beginning of a sector? */ 1308 if (!(faddr & rest_addr)) { 1309 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1310 "Erase sector %#x...\n", faddr); 1311 1312 ret = qla24xx_erase_sector(vha, fdata); 1313 if (ret) { 1314 ql_dbg(ql_dbg_user, vha, 0x7007, 1315 "Failed to erase sector %x.\n", faddr); 1316 break; 1317 } 1318 } 1319 1320 if (optrom) { 1321 /* If smaller than a burst remaining */ 1322 if (dwords - liter < dburst) 1323 dburst = dwords - liter; 1324 1325 /* Copy to dma buffer */ 1326 memcpy(optrom, dwptr, dburst << 2); 1327 1328 /* Burst write */ 1329 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1330 "Write burst (%#lx dwords)...\n", dburst); 1331 ret = qla2x00_load_ram(vha, optrom_dma, 1332 flash_data_addr(ha, faddr), dburst); 1333 if (!ret) { 1334 liter += dburst - 1; 1335 faddr += dburst - 1; 1336 dwptr += dburst - 1; 1337 continue; 1338 } 1339 1340 ql_log(ql_log_warn, vha, 0x7097, 1341 "Failed burst-write at %x (%p/%#llx)....\n", 1342 flash_data_addr(ha, faddr), optrom, 1343 (u64)optrom_dma); 1344 1345 dma_free_coherent(&ha->pdev->dev, 1346 OPTROM_BURST_SIZE, optrom, optrom_dma); 1347 optrom = NULL; 1348 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1349 break; 1350 ql_log(ql_log_warn, vha, 0x7098, 1351 "Reverting to slow write...\n"); 1352 } 1353 1354 /* Slow write */ 1355 ret = qla24xx_write_flash_dword(ha, 1356 flash_data_addr(ha, faddr), le32_to_cpu(*dwptr)); 1357 if (ret) { 1358 ql_dbg(ql_dbg_user, vha, 0x7006, 1359 "Failed slopw write %x (%x)\n", faddr, *dwptr); 1360 break; 1361 } 1362 } 1363 1364 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1365 "Protect flash...\n"); 1366 ret = qla24xx_protect_flash(vha); 1367 if (ret) 1368 ql_log(ql_log_warn, vha, 0x7099, 1369 "Failed to protect flash\n"); 1370 done: 1371 if (optrom) 1372 dma_free_coherent(&ha->pdev->dev, 1373 OPTROM_BURST_SIZE, optrom, optrom_dma); 1374 1375 return ret; 1376 } 1377 1378 uint8_t * 1379 qla2x00_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1380 uint32_t bytes) 1381 { 1382 uint32_t i; 1383 __le16 *wptr; 1384 struct qla_hw_data *ha = vha->hw; 1385 1386 /* Word reads to NVRAM via registers. */ 1387 wptr = buf; 1388 qla2x00_lock_nvram_access(ha); 1389 for (i = 0; i < bytes >> 1; i++, naddr++) 1390 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 1391 naddr)); 1392 qla2x00_unlock_nvram_access(ha); 1393 1394 return buf; 1395 } 1396 1397 uint8_t * 1398 qla24xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1399 uint32_t bytes) 1400 { 1401 struct qla_hw_data *ha = vha->hw; 1402 uint32_t *dwptr = buf; 1403 uint32_t i; 1404 1405 if (IS_P3P_TYPE(ha)) 1406 return buf; 1407 1408 /* Dword reads to flash. */ 1409 naddr = nvram_data_addr(ha, naddr); 1410 bytes >>= 2; 1411 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1412 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1413 break; 1414 cpu_to_le32s(dwptr); 1415 } 1416 1417 return buf; 1418 } 1419 1420 int 1421 qla2x00_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1422 uint32_t bytes) 1423 { 1424 int ret, stat; 1425 uint32_t i; 1426 uint16_t *wptr; 1427 unsigned long flags; 1428 struct qla_hw_data *ha = vha->hw; 1429 1430 ret = QLA_SUCCESS; 1431 1432 spin_lock_irqsave(&ha->hardware_lock, flags); 1433 qla2x00_lock_nvram_access(ha); 1434 1435 /* Disable NVRAM write-protection. */ 1436 stat = qla2x00_clear_nvram_protection(ha); 1437 1438 wptr = (uint16_t *)buf; 1439 for (i = 0; i < bytes >> 1; i++, naddr++) { 1440 qla2x00_write_nvram_word(ha, naddr, 1441 cpu_to_le16(*wptr)); 1442 wptr++; 1443 } 1444 1445 /* Enable NVRAM write-protection. */ 1446 qla2x00_set_nvram_protection(ha, stat); 1447 1448 qla2x00_unlock_nvram_access(ha); 1449 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1450 1451 return ret; 1452 } 1453 1454 int 1455 qla24xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1456 uint32_t bytes) 1457 { 1458 struct qla_hw_data *ha = vha->hw; 1459 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1460 __le32 *dwptr = buf; 1461 uint32_t i; 1462 int ret; 1463 1464 ret = QLA_SUCCESS; 1465 1466 if (IS_P3P_TYPE(ha)) 1467 return ret; 1468 1469 /* Enable flash write. */ 1470 wrt_reg_dword(®->ctrl_status, 1471 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); 1472 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1473 1474 /* Disable NVRAM write-protection. */ 1475 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1476 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1477 1478 /* Dword writes to flash. */ 1479 naddr = nvram_data_addr(ha, naddr); 1480 bytes >>= 2; 1481 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1482 if (qla24xx_write_flash_dword(ha, naddr, le32_to_cpu(*dwptr))) { 1483 ql_dbg(ql_dbg_user, vha, 0x709a, 1484 "Unable to program nvram address=%x data=%x.\n", 1485 naddr, *dwptr); 1486 break; 1487 } 1488 } 1489 1490 /* Enable NVRAM write-protection. */ 1491 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c); 1492 1493 /* Disable flash write. */ 1494 wrt_reg_dword(®->ctrl_status, 1495 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1496 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1497 1498 return ret; 1499 } 1500 1501 uint8_t * 1502 qla25xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1503 uint32_t bytes) 1504 { 1505 struct qla_hw_data *ha = vha->hw; 1506 uint32_t *dwptr = buf; 1507 uint32_t i; 1508 1509 /* Dword reads to flash. */ 1510 naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr); 1511 bytes >>= 2; 1512 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1513 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1514 break; 1515 1516 cpu_to_le32s(dwptr); 1517 } 1518 1519 return buf; 1520 } 1521 1522 #define RMW_BUFFER_SIZE (64 * 1024) 1523 int 1524 qla25xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1525 uint32_t bytes) 1526 { 1527 struct qla_hw_data *ha = vha->hw; 1528 uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE); 1529 1530 if (!dbuf) 1531 return QLA_MEMORY_ALLOC_FAILED; 1532 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1533 RMW_BUFFER_SIZE); 1534 memcpy(dbuf + (naddr << 2), buf, bytes); 1535 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1536 RMW_BUFFER_SIZE); 1537 vfree(dbuf); 1538 1539 return QLA_SUCCESS; 1540 } 1541 1542 static inline void 1543 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1544 { 1545 if (IS_QLA2322(ha)) { 1546 /* Flip all colors. */ 1547 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1548 /* Turn off. */ 1549 ha->beacon_color_state = 0; 1550 *pflags = GPIO_LED_ALL_OFF; 1551 } else { 1552 /* Turn on. */ 1553 ha->beacon_color_state = QLA_LED_ALL_ON; 1554 *pflags = GPIO_LED_RGA_ON; 1555 } 1556 } else { 1557 /* Flip green led only. */ 1558 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 1559 /* Turn off. */ 1560 ha->beacon_color_state = 0; 1561 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 1562 } else { 1563 /* Turn on. */ 1564 ha->beacon_color_state = QLA_LED_GRN_ON; 1565 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 1566 } 1567 } 1568 } 1569 1570 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) 1571 1572 void 1573 qla2x00_beacon_blink(struct scsi_qla_host *vha) 1574 { 1575 uint16_t gpio_enable; 1576 uint16_t gpio_data; 1577 uint16_t led_color = 0; 1578 unsigned long flags; 1579 struct qla_hw_data *ha = vha->hw; 1580 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1581 1582 if (IS_P3P_TYPE(ha)) 1583 return; 1584 1585 spin_lock_irqsave(&ha->hardware_lock, flags); 1586 1587 /* Save the Original GPIOE. */ 1588 if (ha->pio_address) { 1589 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1590 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1591 } else { 1592 gpio_enable = rd_reg_word(®->gpioe); 1593 gpio_data = rd_reg_word(®->gpiod); 1594 } 1595 1596 /* Set the modified gpio_enable values */ 1597 gpio_enable |= GPIO_LED_MASK; 1598 1599 if (ha->pio_address) { 1600 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1601 } else { 1602 wrt_reg_word(®->gpioe, gpio_enable); 1603 rd_reg_word(®->gpioe); 1604 } 1605 1606 qla2x00_flip_colors(ha, &led_color); 1607 1608 /* Clear out any previously set LED color. */ 1609 gpio_data &= ~GPIO_LED_MASK; 1610 1611 /* Set the new input LED color to GPIOD. */ 1612 gpio_data |= led_color; 1613 1614 /* Set the modified gpio_data values */ 1615 if (ha->pio_address) { 1616 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1617 } else { 1618 wrt_reg_word(®->gpiod, gpio_data); 1619 rd_reg_word(®->gpiod); 1620 } 1621 1622 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1623 } 1624 1625 int 1626 qla2x00_beacon_on(struct scsi_qla_host *vha) 1627 { 1628 uint16_t gpio_enable; 1629 uint16_t gpio_data; 1630 unsigned long flags; 1631 struct qla_hw_data *ha = vha->hw; 1632 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1633 1634 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1635 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 1636 1637 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1638 ql_log(ql_log_warn, vha, 0x709b, 1639 "Unable to update fw options (beacon on).\n"); 1640 return QLA_FUNCTION_FAILED; 1641 } 1642 1643 /* Turn off LEDs. */ 1644 spin_lock_irqsave(&ha->hardware_lock, flags); 1645 if (ha->pio_address) { 1646 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1647 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1648 } else { 1649 gpio_enable = rd_reg_word(®->gpioe); 1650 gpio_data = rd_reg_word(®->gpiod); 1651 } 1652 gpio_enable |= GPIO_LED_MASK; 1653 1654 /* Set the modified gpio_enable values. */ 1655 if (ha->pio_address) { 1656 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1657 } else { 1658 wrt_reg_word(®->gpioe, gpio_enable); 1659 rd_reg_word(®->gpioe); 1660 } 1661 1662 /* Clear out previously set LED colour. */ 1663 gpio_data &= ~GPIO_LED_MASK; 1664 if (ha->pio_address) { 1665 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1666 } else { 1667 wrt_reg_word(®->gpiod, gpio_data); 1668 rd_reg_word(®->gpiod); 1669 } 1670 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1671 1672 /* 1673 * Let the per HBA timer kick off the blinking process based on 1674 * the following flags. No need to do anything else now. 1675 */ 1676 ha->beacon_blink_led = 1; 1677 ha->beacon_color_state = 0; 1678 1679 return QLA_SUCCESS; 1680 } 1681 1682 int 1683 qla2x00_beacon_off(struct scsi_qla_host *vha) 1684 { 1685 int rval = QLA_SUCCESS; 1686 struct qla_hw_data *ha = vha->hw; 1687 1688 ha->beacon_blink_led = 0; 1689 1690 /* Set the on flag so when it gets flipped it will be off. */ 1691 if (IS_QLA2322(ha)) 1692 ha->beacon_color_state = QLA_LED_ALL_ON; 1693 else 1694 ha->beacon_color_state = QLA_LED_GRN_ON; 1695 1696 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ 1697 1698 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1699 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 1700 1701 rval = qla2x00_set_fw_options(vha, ha->fw_options); 1702 if (rval != QLA_SUCCESS) 1703 ql_log(ql_log_warn, vha, 0x709c, 1704 "Unable to update fw options (beacon off).\n"); 1705 return rval; 1706 } 1707 1708 1709 static inline void 1710 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1711 { 1712 /* Flip all colors. */ 1713 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1714 /* Turn off. */ 1715 ha->beacon_color_state = 0; 1716 *pflags = 0; 1717 } else { 1718 /* Turn on. */ 1719 ha->beacon_color_state = QLA_LED_ALL_ON; 1720 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 1721 } 1722 } 1723 1724 void 1725 qla24xx_beacon_blink(struct scsi_qla_host *vha) 1726 { 1727 uint16_t led_color = 0; 1728 uint32_t gpio_data; 1729 unsigned long flags; 1730 struct qla_hw_data *ha = vha->hw; 1731 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1732 1733 /* Save the Original GPIOD. */ 1734 spin_lock_irqsave(&ha->hardware_lock, flags); 1735 gpio_data = rd_reg_dword(®->gpiod); 1736 1737 /* Enable the gpio_data reg for update. */ 1738 gpio_data |= GPDX_LED_UPDATE_MASK; 1739 1740 wrt_reg_dword(®->gpiod, gpio_data); 1741 gpio_data = rd_reg_dword(®->gpiod); 1742 1743 /* Set the color bits. */ 1744 qla24xx_flip_colors(ha, &led_color); 1745 1746 /* Clear out any previously set LED color. */ 1747 gpio_data &= ~GPDX_LED_COLOR_MASK; 1748 1749 /* Set the new input LED color to GPIOD. */ 1750 gpio_data |= led_color; 1751 1752 /* Set the modified gpio_data values. */ 1753 wrt_reg_dword(®->gpiod, gpio_data); 1754 gpio_data = rd_reg_dword(®->gpiod); 1755 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1756 } 1757 1758 static uint32_t 1759 qla83xx_select_led_port(struct qla_hw_data *ha) 1760 { 1761 uint32_t led_select_value = 0; 1762 1763 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1764 goto out; 1765 1766 if (ha->port_no == 0) 1767 led_select_value = QLA83XX_LED_PORT0; 1768 else 1769 led_select_value = QLA83XX_LED_PORT1; 1770 1771 out: 1772 return led_select_value; 1773 } 1774 1775 void 1776 qla83xx_beacon_blink(struct scsi_qla_host *vha) 1777 { 1778 uint32_t led_select_value; 1779 struct qla_hw_data *ha = vha->hw; 1780 uint16_t led_cfg[6]; 1781 uint16_t orig_led_cfg[6]; 1782 uint32_t led_10_value, led_43_value; 1783 1784 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha) && 1785 !IS_QLA28XX(ha)) 1786 return; 1787 1788 if (!ha->beacon_blink_led) 1789 return; 1790 1791 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 1792 qla2x00_write_ram_word(vha, 0x1003, 0x40000230); 1793 qla2x00_write_ram_word(vha, 0x1004, 0x40000230); 1794 } else if (IS_QLA2031(ha)) { 1795 led_select_value = qla83xx_select_led_port(ha); 1796 1797 qla83xx_wr_reg(vha, led_select_value, 0x40000230); 1798 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230); 1799 } else if (IS_QLA8031(ha)) { 1800 led_select_value = qla83xx_select_led_port(ha); 1801 1802 qla83xx_rd_reg(vha, led_select_value, &led_10_value); 1803 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value); 1804 qla83xx_wr_reg(vha, led_select_value, 0x01f44000); 1805 msleep(500); 1806 qla83xx_wr_reg(vha, led_select_value, 0x400001f4); 1807 msleep(1000); 1808 qla83xx_wr_reg(vha, led_select_value, led_10_value); 1809 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value); 1810 } else if (IS_QLA81XX(ha)) { 1811 int rval; 1812 1813 /* Save Current */ 1814 rval = qla81xx_get_led_config(vha, orig_led_cfg); 1815 /* Do the blink */ 1816 if (rval == QLA_SUCCESS) { 1817 if (IS_QLA81XX(ha)) { 1818 led_cfg[0] = 0x4000; 1819 led_cfg[1] = 0x2000; 1820 led_cfg[2] = 0; 1821 led_cfg[3] = 0; 1822 led_cfg[4] = 0; 1823 led_cfg[5] = 0; 1824 } else { 1825 led_cfg[0] = 0x4000; 1826 led_cfg[1] = 0x4000; 1827 led_cfg[2] = 0x4000; 1828 led_cfg[3] = 0x2000; 1829 led_cfg[4] = 0; 1830 led_cfg[5] = 0x2000; 1831 } 1832 rval = qla81xx_set_led_config(vha, led_cfg); 1833 msleep(1000); 1834 if (IS_QLA81XX(ha)) { 1835 led_cfg[0] = 0x4000; 1836 led_cfg[1] = 0x2000; 1837 led_cfg[2] = 0; 1838 } else { 1839 led_cfg[0] = 0x4000; 1840 led_cfg[1] = 0x2000; 1841 led_cfg[2] = 0x4000; 1842 led_cfg[3] = 0x4000; 1843 led_cfg[4] = 0; 1844 led_cfg[5] = 0x2000; 1845 } 1846 rval = qla81xx_set_led_config(vha, led_cfg); 1847 } 1848 /* On exit, restore original (presumes no status change) */ 1849 qla81xx_set_led_config(vha, orig_led_cfg); 1850 } 1851 } 1852 1853 int 1854 qla24xx_beacon_on(struct scsi_qla_host *vha) 1855 { 1856 uint32_t gpio_data; 1857 unsigned long flags; 1858 struct qla_hw_data *ha = vha->hw; 1859 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1860 1861 if (IS_P3P_TYPE(ha)) 1862 return QLA_SUCCESS; 1863 1864 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1865 goto skip_gpio; /* let blink handle it */ 1866 1867 if (ha->beacon_blink_led == 0) { 1868 /* Enable firmware for update */ 1869 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1870 1871 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) 1872 return QLA_FUNCTION_FAILED; 1873 1874 if (qla2x00_get_fw_options(vha, ha->fw_options) != 1875 QLA_SUCCESS) { 1876 ql_log(ql_log_warn, vha, 0x7009, 1877 "Unable to update fw options (beacon on).\n"); 1878 return QLA_FUNCTION_FAILED; 1879 } 1880 1881 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1882 goto skip_gpio; 1883 1884 spin_lock_irqsave(&ha->hardware_lock, flags); 1885 gpio_data = rd_reg_dword(®->gpiod); 1886 1887 /* Enable the gpio_data reg for update. */ 1888 gpio_data |= GPDX_LED_UPDATE_MASK; 1889 wrt_reg_dword(®->gpiod, gpio_data); 1890 rd_reg_dword(®->gpiod); 1891 1892 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1893 } 1894 1895 /* So all colors blink together. */ 1896 ha->beacon_color_state = 0; 1897 1898 skip_gpio: 1899 /* Let the per HBA timer kick off the blinking process. */ 1900 ha->beacon_blink_led = 1; 1901 1902 return QLA_SUCCESS; 1903 } 1904 1905 int 1906 qla24xx_beacon_off(struct scsi_qla_host *vha) 1907 { 1908 uint32_t gpio_data; 1909 unsigned long flags; 1910 struct qla_hw_data *ha = vha->hw; 1911 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1912 1913 if (IS_P3P_TYPE(ha)) 1914 return QLA_SUCCESS; 1915 1916 if (!ha->flags.fw_started) 1917 return QLA_SUCCESS; 1918 1919 ha->beacon_blink_led = 0; 1920 1921 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1922 goto set_fw_options; 1923 1924 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1925 return QLA_SUCCESS; 1926 1927 ha->beacon_color_state = QLA_LED_ALL_ON; 1928 1929 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ 1930 1931 /* Give control back to firmware. */ 1932 spin_lock_irqsave(&ha->hardware_lock, flags); 1933 gpio_data = rd_reg_dword(®->gpiod); 1934 1935 /* Disable the gpio_data reg for update. */ 1936 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1937 wrt_reg_dword(®->gpiod, gpio_data); 1938 rd_reg_dword(®->gpiod); 1939 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1940 1941 set_fw_options: 1942 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1943 1944 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1945 ql_log(ql_log_warn, vha, 0x704d, 1946 "Unable to update fw options (beacon on).\n"); 1947 return QLA_FUNCTION_FAILED; 1948 } 1949 1950 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1951 ql_log(ql_log_warn, vha, 0x704e, 1952 "Unable to update fw options (beacon on).\n"); 1953 return QLA_FUNCTION_FAILED; 1954 } 1955 1956 return QLA_SUCCESS; 1957 } 1958 1959 1960 /* 1961 * Flash support routines 1962 */ 1963 1964 /** 1965 * qla2x00_flash_enable() - Setup flash for reading and writing. 1966 * @ha: HA context 1967 */ 1968 static void 1969 qla2x00_flash_enable(struct qla_hw_data *ha) 1970 { 1971 uint16_t data; 1972 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1973 1974 data = rd_reg_word(®->ctrl_status); 1975 data |= CSR_FLASH_ENABLE; 1976 wrt_reg_word(®->ctrl_status, data); 1977 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 1978 } 1979 1980 /** 1981 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1982 * @ha: HA context 1983 */ 1984 static void 1985 qla2x00_flash_disable(struct qla_hw_data *ha) 1986 { 1987 uint16_t data; 1988 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1989 1990 data = rd_reg_word(®->ctrl_status); 1991 data &= ~(CSR_FLASH_ENABLE); 1992 wrt_reg_word(®->ctrl_status, data); 1993 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 1994 } 1995 1996 /** 1997 * qla2x00_read_flash_byte() - Reads a byte from flash 1998 * @ha: HA context 1999 * @addr: Address in flash to read 2000 * 2001 * A word is read from the chip, but, only the lower byte is valid. 2002 * 2003 * Returns the byte read from flash @addr. 2004 */ 2005 static uint8_t 2006 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) 2007 { 2008 uint16_t data; 2009 uint16_t bank_select; 2010 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2011 2012 bank_select = rd_reg_word(®->ctrl_status); 2013 2014 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2015 /* Specify 64K address range: */ 2016 /* clear out Module Select and Flash Address bits [19:16]. */ 2017 bank_select &= ~0xf8; 2018 bank_select |= addr >> 12 & 0xf0; 2019 bank_select |= CSR_FLASH_64K_BANK; 2020 wrt_reg_word(®->ctrl_status, bank_select); 2021 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2022 2023 wrt_reg_word(®->flash_address, (uint16_t)addr); 2024 data = rd_reg_word(®->flash_data); 2025 2026 return (uint8_t)data; 2027 } 2028 2029 /* Setup bit 16 of flash address. */ 2030 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2031 bank_select |= CSR_FLASH_64K_BANK; 2032 wrt_reg_word(®->ctrl_status, bank_select); 2033 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2034 } else if (((addr & BIT_16) == 0) && 2035 (bank_select & CSR_FLASH_64K_BANK)) { 2036 bank_select &= ~(CSR_FLASH_64K_BANK); 2037 wrt_reg_word(®->ctrl_status, bank_select); 2038 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2039 } 2040 2041 /* Always perform IO mapped accesses to the FLASH registers. */ 2042 if (ha->pio_address) { 2043 uint16_t data2; 2044 2045 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2046 do { 2047 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2048 barrier(); 2049 cpu_relax(); 2050 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2051 } while (data != data2); 2052 } else { 2053 wrt_reg_word(®->flash_address, (uint16_t)addr); 2054 data = qla2x00_debounce_register(®->flash_data); 2055 } 2056 2057 return (uint8_t)data; 2058 } 2059 2060 /** 2061 * qla2x00_write_flash_byte() - Write a byte to flash 2062 * @ha: HA context 2063 * @addr: Address in flash to write 2064 * @data: Data to write 2065 */ 2066 static void 2067 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) 2068 { 2069 uint16_t bank_select; 2070 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2071 2072 bank_select = rd_reg_word(®->ctrl_status); 2073 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2074 /* Specify 64K address range: */ 2075 /* clear out Module Select and Flash Address bits [19:16]. */ 2076 bank_select &= ~0xf8; 2077 bank_select |= addr >> 12 & 0xf0; 2078 bank_select |= CSR_FLASH_64K_BANK; 2079 wrt_reg_word(®->ctrl_status, bank_select); 2080 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2081 2082 wrt_reg_word(®->flash_address, (uint16_t)addr); 2083 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2084 wrt_reg_word(®->flash_data, (uint16_t)data); 2085 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2086 2087 return; 2088 } 2089 2090 /* Setup bit 16 of flash address. */ 2091 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2092 bank_select |= CSR_FLASH_64K_BANK; 2093 wrt_reg_word(®->ctrl_status, bank_select); 2094 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2095 } else if (((addr & BIT_16) == 0) && 2096 (bank_select & CSR_FLASH_64K_BANK)) { 2097 bank_select &= ~(CSR_FLASH_64K_BANK); 2098 wrt_reg_word(®->ctrl_status, bank_select); 2099 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2100 } 2101 2102 /* Always perform IO mapped accesses to the FLASH registers. */ 2103 if (ha->pio_address) { 2104 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2105 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); 2106 } else { 2107 wrt_reg_word(®->flash_address, (uint16_t)addr); 2108 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2109 wrt_reg_word(®->flash_data, (uint16_t)data); 2110 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2111 } 2112 } 2113 2114 /** 2115 * qla2x00_poll_flash() - Polls flash for completion. 2116 * @ha: HA context 2117 * @addr: Address in flash to poll 2118 * @poll_data: Data to be polled 2119 * @man_id: Flash manufacturer ID 2120 * @flash_id: Flash ID 2121 * 2122 * This function polls the device until bit 7 of what is read matches data 2123 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed 2124 * out (a fatal error). The flash book recommeds reading bit 7 again after 2125 * reading bit 5 as a 1. 2126 * 2127 * Returns 0 on success, else non-zero. 2128 */ 2129 static int 2130 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, 2131 uint8_t man_id, uint8_t flash_id) 2132 { 2133 int status; 2134 uint8_t flash_data; 2135 uint32_t cnt; 2136 2137 status = 1; 2138 2139 /* Wait for 30 seconds for command to finish. */ 2140 poll_data &= BIT_7; 2141 for (cnt = 3000000; cnt; cnt--) { 2142 flash_data = qla2x00_read_flash_byte(ha, addr); 2143 if ((flash_data & BIT_7) == poll_data) { 2144 status = 0; 2145 break; 2146 } 2147 2148 if (man_id != 0x40 && man_id != 0xda) { 2149 if ((flash_data & BIT_5) && cnt > 2) 2150 cnt = 2; 2151 } 2152 udelay(10); 2153 barrier(); 2154 cond_resched(); 2155 } 2156 return status; 2157 } 2158 2159 /** 2160 * qla2x00_program_flash_address() - Programs a flash address 2161 * @ha: HA context 2162 * @addr: Address in flash to program 2163 * @data: Data to be written in flash 2164 * @man_id: Flash manufacturer ID 2165 * @flash_id: Flash ID 2166 * 2167 * Returns 0 on success, else non-zero. 2168 */ 2169 static int 2170 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, 2171 uint8_t data, uint8_t man_id, uint8_t flash_id) 2172 { 2173 /* Write Program Command Sequence. */ 2174 if (IS_OEM_001(ha)) { 2175 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2176 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2177 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 2178 qla2x00_write_flash_byte(ha, addr, data); 2179 } else { 2180 if (man_id == 0xda && flash_id == 0xc1) { 2181 qla2x00_write_flash_byte(ha, addr, data); 2182 if (addr & 0x7e) 2183 return 0; 2184 } else { 2185 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2186 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2187 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 2188 qla2x00_write_flash_byte(ha, addr, data); 2189 } 2190 } 2191 2192 udelay(150); 2193 2194 /* Wait for write to complete. */ 2195 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 2196 } 2197 2198 /** 2199 * qla2x00_erase_flash() - Erase the flash. 2200 * @ha: HA context 2201 * @man_id: Flash manufacturer ID 2202 * @flash_id: Flash ID 2203 * 2204 * Returns 0 on success, else non-zero. 2205 */ 2206 static int 2207 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id) 2208 { 2209 /* Individual Sector Erase Command Sequence */ 2210 if (IS_OEM_001(ha)) { 2211 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2212 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2213 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 2214 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2215 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2216 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 2217 } else { 2218 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2219 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2220 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2221 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2222 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2223 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 2224 } 2225 2226 udelay(150); 2227 2228 /* Wait for erase to complete. */ 2229 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 2230 } 2231 2232 /** 2233 * qla2x00_erase_flash_sector() - Erase a flash sector. 2234 * @ha: HA context 2235 * @addr: Flash sector to erase 2236 * @sec_mask: Sector address mask 2237 * @man_id: Flash manufacturer ID 2238 * @flash_id: Flash ID 2239 * 2240 * Returns 0 on success, else non-zero. 2241 */ 2242 static int 2243 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, 2244 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 2245 { 2246 /* Individual Sector Erase Command Sequence */ 2247 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2248 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2249 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2250 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2251 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2252 if (man_id == 0x1f && flash_id == 0x13) 2253 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 2254 else 2255 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 2256 2257 udelay(150); 2258 2259 /* Wait for erase to complete. */ 2260 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 2261 } 2262 2263 /** 2264 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 2265 * @ha: host adapter 2266 * @man_id: Flash manufacturer ID 2267 * @flash_id: Flash ID 2268 */ 2269 static void 2270 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 2271 uint8_t *flash_id) 2272 { 2273 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2274 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2275 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 2276 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 2277 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 2278 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2279 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2280 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 2281 } 2282 2283 static void 2284 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf, 2285 uint32_t saddr, uint32_t length) 2286 { 2287 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2288 uint32_t midpoint, ilength; 2289 uint8_t data; 2290 2291 midpoint = length / 2; 2292 2293 wrt_reg_word(®->nvram, 0); 2294 rd_reg_word(®->nvram); 2295 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 2296 if (ilength == midpoint) { 2297 wrt_reg_word(®->nvram, NVR_SELECT); 2298 rd_reg_word(®->nvram); 2299 } 2300 data = qla2x00_read_flash_byte(ha, saddr); 2301 if (saddr % 100) 2302 udelay(10); 2303 *tmp_buf = data; 2304 cond_resched(); 2305 } 2306 } 2307 2308 static inline void 2309 qla2x00_suspend_hba(struct scsi_qla_host *vha) 2310 { 2311 int cnt; 2312 unsigned long flags; 2313 struct qla_hw_data *ha = vha->hw; 2314 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2315 2316 /* Suspend HBA. */ 2317 scsi_block_requests(vha->host); 2318 ha->isp_ops->disable_intrs(ha); 2319 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2320 2321 /* Pause RISC. */ 2322 spin_lock_irqsave(&ha->hardware_lock, flags); 2323 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2324 rd_reg_word(®->hccr); 2325 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2326 for (cnt = 0; cnt < 30000; cnt++) { 2327 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) 2328 break; 2329 udelay(100); 2330 } 2331 } else { 2332 udelay(10); 2333 } 2334 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2335 } 2336 2337 static inline void 2338 qla2x00_resume_hba(struct scsi_qla_host *vha) 2339 { 2340 struct qla_hw_data *ha = vha->hw; 2341 2342 /* Resume HBA. */ 2343 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2344 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2345 qla2xxx_wake_dpc(vha); 2346 qla2x00_wait_for_chip_reset(vha); 2347 scsi_unblock_requests(vha->host); 2348 } 2349 2350 void * 2351 qla2x00_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2352 uint32_t offset, uint32_t length) 2353 { 2354 uint32_t addr, midpoint; 2355 uint8_t *data; 2356 struct qla_hw_data *ha = vha->hw; 2357 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2358 2359 /* Suspend HBA. */ 2360 qla2x00_suspend_hba(vha); 2361 2362 /* Go with read. */ 2363 midpoint = ha->optrom_size / 2; 2364 2365 qla2x00_flash_enable(ha); 2366 wrt_reg_word(®->nvram, 0); 2367 rd_reg_word(®->nvram); /* PCI Posting. */ 2368 for (addr = offset, data = buf; addr < length; addr++, data++) { 2369 if (addr == midpoint) { 2370 wrt_reg_word(®->nvram, NVR_SELECT); 2371 rd_reg_word(®->nvram); /* PCI Posting. */ 2372 } 2373 2374 *data = qla2x00_read_flash_byte(ha, addr); 2375 } 2376 qla2x00_flash_disable(ha); 2377 2378 /* Resume HBA. */ 2379 qla2x00_resume_hba(vha); 2380 2381 return buf; 2382 } 2383 2384 int 2385 qla2x00_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2386 uint32_t offset, uint32_t length) 2387 { 2388 2389 int rval; 2390 uint8_t man_id, flash_id, sec_number, *data; 2391 uint16_t wd; 2392 uint32_t addr, liter, sec_mask, rest_addr; 2393 struct qla_hw_data *ha = vha->hw; 2394 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2395 2396 /* Suspend HBA. */ 2397 qla2x00_suspend_hba(vha); 2398 2399 rval = QLA_SUCCESS; 2400 sec_number = 0; 2401 2402 /* Reset ISP chip. */ 2403 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 2404 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2405 2406 /* Go with write. */ 2407 qla2x00_flash_enable(ha); 2408 do { /* Loop once to provide quick error exit */ 2409 /* Structure of flash memory based on manufacturer */ 2410 if (IS_OEM_001(ha)) { 2411 /* OEM variant with special flash part. */ 2412 man_id = flash_id = 0; 2413 rest_addr = 0xffff; 2414 sec_mask = 0x10000; 2415 goto update_flash; 2416 } 2417 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 2418 switch (man_id) { 2419 case 0x20: /* ST flash. */ 2420 if (flash_id == 0xd2 || flash_id == 0xe3) { 2421 /* 2422 * ST m29w008at part - 64kb sector size with 2423 * 32kb,8kb,8kb,16kb sectors at memory address 2424 * 0xf0000. 2425 */ 2426 rest_addr = 0xffff; 2427 sec_mask = 0x10000; 2428 break; 2429 } 2430 /* 2431 * ST m29w010b part - 16kb sector size 2432 * Default to 16kb sectors 2433 */ 2434 rest_addr = 0x3fff; 2435 sec_mask = 0x1c000; 2436 break; 2437 case 0x40: /* Mostel flash. */ 2438 /* Mostel v29c51001 part - 512 byte sector size. */ 2439 rest_addr = 0x1ff; 2440 sec_mask = 0x1fe00; 2441 break; 2442 case 0xbf: /* SST flash. */ 2443 /* SST39sf10 part - 4kb sector size. */ 2444 rest_addr = 0xfff; 2445 sec_mask = 0x1f000; 2446 break; 2447 case 0xda: /* Winbond flash. */ 2448 /* Winbond W29EE011 part - 256 byte sector size. */ 2449 rest_addr = 0x7f; 2450 sec_mask = 0x1ff80; 2451 break; 2452 case 0xc2: /* Macronix flash. */ 2453 /* 64k sector size. */ 2454 if (flash_id == 0x38 || flash_id == 0x4f) { 2455 rest_addr = 0xffff; 2456 sec_mask = 0x10000; 2457 break; 2458 } 2459 fallthrough; 2460 2461 case 0x1f: /* Atmel flash. */ 2462 /* 512k sector size. */ 2463 if (flash_id == 0x13) { 2464 rest_addr = 0x7fffffff; 2465 sec_mask = 0x80000000; 2466 break; 2467 } 2468 fallthrough; 2469 2470 case 0x01: /* AMD flash. */ 2471 if (flash_id == 0x38 || flash_id == 0x40 || 2472 flash_id == 0x4f) { 2473 /* Am29LV081 part - 64kb sector size. */ 2474 /* Am29LV002BT part - 64kb sector size. */ 2475 rest_addr = 0xffff; 2476 sec_mask = 0x10000; 2477 break; 2478 } else if (flash_id == 0x3e) { 2479 /* 2480 * Am29LV008b part - 64kb sector size with 2481 * 32kb,8kb,8kb,16kb sector at memory address 2482 * h0xf0000. 2483 */ 2484 rest_addr = 0xffff; 2485 sec_mask = 0x10000; 2486 break; 2487 } else if (flash_id == 0x20 || flash_id == 0x6e) { 2488 /* 2489 * Am29LV010 part or AM29f010 - 16kb sector 2490 * size. 2491 */ 2492 rest_addr = 0x3fff; 2493 sec_mask = 0x1c000; 2494 break; 2495 } else if (flash_id == 0x6d) { 2496 /* Am29LV001 part - 8kb sector size. */ 2497 rest_addr = 0x1fff; 2498 sec_mask = 0x1e000; 2499 break; 2500 } 2501 fallthrough; 2502 default: 2503 /* Default to 16 kb sector size. */ 2504 rest_addr = 0x3fff; 2505 sec_mask = 0x1c000; 2506 break; 2507 } 2508 2509 update_flash: 2510 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2511 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 2512 rval = QLA_FUNCTION_FAILED; 2513 break; 2514 } 2515 } 2516 2517 for (addr = offset, liter = 0; liter < length; liter++, 2518 addr++) { 2519 data = buf + liter; 2520 /* Are we at the beginning of a sector? */ 2521 if ((addr & rest_addr) == 0) { 2522 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2523 if (addr >= 0x10000UL) { 2524 if (((addr >> 12) & 0xf0) && 2525 ((man_id == 0x01 && 2526 flash_id == 0x3e) || 2527 (man_id == 0x20 && 2528 flash_id == 0xd2))) { 2529 sec_number++; 2530 if (sec_number == 1) { 2531 rest_addr = 2532 0x7fff; 2533 sec_mask = 2534 0x18000; 2535 } else if ( 2536 sec_number == 2 || 2537 sec_number == 3) { 2538 rest_addr = 2539 0x1fff; 2540 sec_mask = 2541 0x1e000; 2542 } else if ( 2543 sec_number == 4) { 2544 rest_addr = 2545 0x3fff; 2546 sec_mask = 2547 0x1c000; 2548 } 2549 } 2550 } 2551 } else if (addr == ha->optrom_size / 2) { 2552 wrt_reg_word(®->nvram, NVR_SELECT); 2553 rd_reg_word(®->nvram); 2554 } 2555 2556 if (flash_id == 0xda && man_id == 0xc1) { 2557 qla2x00_write_flash_byte(ha, 0x5555, 2558 0xaa); 2559 qla2x00_write_flash_byte(ha, 0x2aaa, 2560 0x55); 2561 qla2x00_write_flash_byte(ha, 0x5555, 2562 0xa0); 2563 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 2564 /* Then erase it */ 2565 if (qla2x00_erase_flash_sector(ha, 2566 addr, sec_mask, man_id, 2567 flash_id)) { 2568 rval = QLA_FUNCTION_FAILED; 2569 break; 2570 } 2571 if (man_id == 0x01 && flash_id == 0x6d) 2572 sec_number++; 2573 } 2574 } 2575 2576 if (man_id == 0x01 && flash_id == 0x6d) { 2577 if (sec_number == 1 && 2578 addr == (rest_addr - 1)) { 2579 rest_addr = 0x0fff; 2580 sec_mask = 0x1f000; 2581 } else if (sec_number == 3 && (addr & 0x7ffe)) { 2582 rest_addr = 0x3fff; 2583 sec_mask = 0x1c000; 2584 } 2585 } 2586 2587 if (qla2x00_program_flash_address(ha, addr, *data, 2588 man_id, flash_id)) { 2589 rval = QLA_FUNCTION_FAILED; 2590 break; 2591 } 2592 cond_resched(); 2593 } 2594 } while (0); 2595 qla2x00_flash_disable(ha); 2596 2597 /* Resume HBA. */ 2598 qla2x00_resume_hba(vha); 2599 2600 return rval; 2601 } 2602 2603 void * 2604 qla24xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2605 uint32_t offset, uint32_t length) 2606 { 2607 struct qla_hw_data *ha = vha->hw; 2608 2609 /* Suspend HBA. */ 2610 scsi_block_requests(vha->host); 2611 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2612 2613 /* Go with read. */ 2614 qla24xx_read_flash_data(vha, buf, offset >> 2, length >> 2); 2615 2616 /* Resume HBA. */ 2617 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2618 scsi_unblock_requests(vha->host); 2619 2620 return buf; 2621 } 2622 2623 static int 2624 qla28xx_extract_sfub_and_verify(struct scsi_qla_host *vha, __le32 *buf, 2625 uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf) 2626 { 2627 uint32_t check_sum = 0; 2628 __le32 *p; 2629 int i; 2630 2631 p = buf + buf_size_without_sfub; 2632 2633 /* Extract SFUB from end of file */ 2634 memcpy(sfub_buf, (uint8_t *)p, 2635 sizeof(struct secure_flash_update_block)); 2636 2637 for (i = 0; i < (sizeof(struct secure_flash_update_block) >> 2); i++) 2638 check_sum += le32_to_cpu(p[i]); 2639 2640 check_sum = (~check_sum) + 1; 2641 2642 if (check_sum != le32_to_cpu(p[i])) { 2643 ql_log(ql_log_warn, vha, 0x7097, 2644 "SFUB checksum failed, 0x%x, 0x%x\n", 2645 check_sum, le32_to_cpu(p[i])); 2646 return QLA_COMMAND_ERROR; 2647 } 2648 2649 return QLA_SUCCESS; 2650 } 2651 2652 static int 2653 qla28xx_get_flash_region(struct scsi_qla_host *vha, uint32_t start, 2654 struct qla_flt_region *region) 2655 { 2656 struct qla_hw_data *ha = vha->hw; 2657 struct qla_flt_header *flt = ha->flt; 2658 struct qla_flt_region *flt_reg = &flt->region[0]; 2659 uint16_t cnt; 2660 int rval = QLA_FUNCTION_FAILED; 2661 2662 if (!ha->flt) 2663 return QLA_FUNCTION_FAILED; 2664 2665 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 2666 for (; cnt; cnt--, flt_reg++) { 2667 if (le32_to_cpu(flt_reg->start) == start) { 2668 memcpy((uint8_t *)region, flt_reg, 2669 sizeof(struct qla_flt_region)); 2670 rval = QLA_SUCCESS; 2671 break; 2672 } 2673 } 2674 2675 return rval; 2676 } 2677 2678 static int 2679 qla28xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2680 uint32_t dwords) 2681 { 2682 struct qla_hw_data *ha = vha->hw; 2683 ulong liter; 2684 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 2685 uint32_t sec_mask, rest_addr, fdata; 2686 void *optrom = NULL; 2687 dma_addr_t optrom_dma; 2688 int rval, ret; 2689 struct secure_flash_update_block *sfub; 2690 dma_addr_t sfub_dma; 2691 uint32_t offset = faddr << 2; 2692 uint32_t buf_size_without_sfub = 0; 2693 struct qla_flt_region region; 2694 bool reset_to_rom = false; 2695 uint32_t risc_size, risc_attr = 0; 2696 __be32 *fw_array = NULL; 2697 2698 /* Retrieve region info - must be a start address passed in */ 2699 rval = qla28xx_get_flash_region(vha, offset, ®ion); 2700 2701 if (rval != QLA_SUCCESS) { 2702 ql_log(ql_log_warn, vha, 0xffff, 2703 "Invalid address %x - not a region start address\n", 2704 offset); 2705 goto done; 2706 } 2707 2708 /* Allocate dma buffer for burst write */ 2709 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2710 &optrom_dma, GFP_KERNEL); 2711 if (!optrom) { 2712 ql_log(ql_log_warn, vha, 0x7095, 2713 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 2714 rval = QLA_COMMAND_ERROR; 2715 goto done; 2716 } 2717 2718 /* 2719 * If adapter supports secure flash and region is secure 2720 * extract secure flash update block (SFUB) and verify 2721 */ 2722 if (ha->flags.secure_adapter && region.attribute) { 2723 2724 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2725 "Region %x is secure\n", le16_to_cpu(region.code)); 2726 2727 switch (le16_to_cpu(region.code)) { 2728 case FLT_REG_FW: 2729 case FLT_REG_FW_SEC_27XX: 2730 case FLT_REG_MPI_PRI_28XX: 2731 case FLT_REG_MPI_SEC_28XX: 2732 fw_array = (__force __be32 *)dwptr; 2733 2734 /* 1st fw array */ 2735 risc_size = be32_to_cpu(fw_array[3]); 2736 risc_attr = be32_to_cpu(fw_array[9]); 2737 2738 buf_size_without_sfub = risc_size; 2739 fw_array += risc_size; 2740 2741 /* 2nd fw array */ 2742 risc_size = be32_to_cpu(fw_array[3]); 2743 2744 buf_size_without_sfub += risc_size; 2745 fw_array += risc_size; 2746 2747 /* 1st dump template */ 2748 risc_size = be32_to_cpu(fw_array[2]); 2749 2750 /* skip header and ignore checksum */ 2751 buf_size_without_sfub += risc_size; 2752 fw_array += risc_size; 2753 2754 if (risc_attr & BIT_9) { 2755 /* 2nd dump template */ 2756 risc_size = be32_to_cpu(fw_array[2]); 2757 2758 /* skip header and ignore checksum */ 2759 buf_size_without_sfub += risc_size; 2760 fw_array += risc_size; 2761 } 2762 break; 2763 2764 case FLT_REG_PEP_PRI_28XX: 2765 case FLT_REG_PEP_SEC_28XX: 2766 fw_array = (__force __be32 *)dwptr; 2767 2768 /* 1st fw array */ 2769 risc_size = be32_to_cpu(fw_array[3]); 2770 risc_attr = be32_to_cpu(fw_array[9]); 2771 2772 buf_size_without_sfub = risc_size; 2773 fw_array += risc_size; 2774 break; 2775 2776 default: 2777 ql_log(ql_log_warn + ql_dbg_verbose, vha, 2778 0xffff, "Secure region %x not supported\n", 2779 le16_to_cpu(region.code)); 2780 rval = QLA_COMMAND_ERROR; 2781 goto done; 2782 } 2783 2784 sfub = dma_alloc_coherent(&ha->pdev->dev, 2785 sizeof(struct secure_flash_update_block), &sfub_dma, 2786 GFP_KERNEL); 2787 if (!sfub) { 2788 ql_log(ql_log_warn, vha, 0xffff, 2789 "Unable to allocate memory for SFUB\n"); 2790 rval = QLA_COMMAND_ERROR; 2791 goto done; 2792 } 2793 2794 rval = qla28xx_extract_sfub_and_verify(vha, (__le32 *)dwptr, 2795 dwords, buf_size_without_sfub, (uint8_t *)sfub); 2796 2797 if (rval != QLA_SUCCESS) 2798 goto done; 2799 2800 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2801 "SFUB extract and verify successful\n"); 2802 } 2803 2804 rest_addr = (ha->fdt_block_size >> 2) - 1; 2805 sec_mask = ~rest_addr; 2806 2807 /* Lock semaphore */ 2808 rval = qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_LOCK); 2809 if (rval != QLA_SUCCESS) { 2810 ql_log(ql_log_warn, vha, 0xffff, 2811 "Unable to lock flash semaphore."); 2812 goto done; 2813 } 2814 2815 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2816 "Unprotect flash...\n"); 2817 rval = qla24xx_unprotect_flash(vha); 2818 if (rval) { 2819 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2820 ql_log(ql_log_warn, vha, 0x7096, "Failed unprotect flash\n"); 2821 goto done; 2822 } 2823 2824 for (liter = 0; liter < dwords; liter++, faddr++) { 2825 fdata = (faddr & sec_mask) << 2; 2826 2827 /* If start of sector */ 2828 if (!(faddr & rest_addr)) { 2829 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2830 "Erase sector %#x...\n", faddr); 2831 rval = qla24xx_erase_sector(vha, fdata); 2832 if (rval) { 2833 ql_dbg(ql_dbg_user, vha, 0x7007, 2834 "Failed erase sector %#x\n", faddr); 2835 goto write_protect; 2836 } 2837 } 2838 } 2839 2840 if (ha->flags.secure_adapter) { 2841 /* 2842 * If adapter supports secure flash but FW doesn't, 2843 * disable write protect, release semaphore and reset 2844 * chip to execute ROM code in order to update region securely 2845 */ 2846 if (!ha->flags.secure_fw) { 2847 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2848 "Disable Write and Release Semaphore."); 2849 rval = qla24xx_protect_flash(vha); 2850 if (rval != QLA_SUCCESS) { 2851 qla81xx_fac_semaphore_access(vha, 2852 FAC_SEMAPHORE_UNLOCK); 2853 ql_log(ql_log_warn, vha, 0xffff, 2854 "Unable to protect flash."); 2855 goto done; 2856 } 2857 2858 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2859 "Reset chip to ROM."); 2860 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2861 set_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags); 2862 qla2xxx_wake_dpc(vha); 2863 rval = qla2x00_wait_for_chip_reset(vha); 2864 if (rval != QLA_SUCCESS) { 2865 ql_log(ql_log_warn, vha, 0xffff, 2866 "Unable to reset to ROM code."); 2867 goto done; 2868 } 2869 reset_to_rom = true; 2870 ha->flags.fac_supported = 0; 2871 2872 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2873 "Lock Semaphore"); 2874 rval = qla2xxx_write_remote_register(vha, 2875 FLASH_SEMAPHORE_REGISTER_ADDR, 0x00020002); 2876 if (rval != QLA_SUCCESS) { 2877 ql_log(ql_log_warn, vha, 0xffff, 2878 "Unable to lock flash semaphore."); 2879 goto done; 2880 } 2881 2882 /* Unprotect flash */ 2883 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2884 "Enable Write."); 2885 rval = qla2x00_write_ram_word(vha, 0x7ffd0101, 0); 2886 if (rval) { 2887 ql_log(ql_log_warn, vha, 0x7096, 2888 "Failed unprotect flash\n"); 2889 goto done; 2890 } 2891 } 2892 2893 /* If region is secure, send Secure Flash MB Cmd */ 2894 if (region.attribute && buf_size_without_sfub) { 2895 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2896 "Sending Secure Flash MB Cmd\n"); 2897 rval = qla28xx_secure_flash_update(vha, 0, 2898 le16_to_cpu(region.code), 2899 buf_size_without_sfub, sfub_dma, 2900 sizeof(struct secure_flash_update_block) >> 2); 2901 if (rval != QLA_SUCCESS) { 2902 ql_log(ql_log_warn, vha, 0xffff, 2903 "Secure Flash MB Cmd failed %x.", rval); 2904 goto write_protect; 2905 } 2906 } 2907 2908 } 2909 2910 /* re-init flash offset */ 2911 faddr = offset >> 2; 2912 2913 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 2914 fdata = (faddr & sec_mask) << 2; 2915 2916 /* If smaller than a burst remaining */ 2917 if (dwords - liter < dburst) 2918 dburst = dwords - liter; 2919 2920 /* Copy to dma buffer */ 2921 memcpy(optrom, dwptr, dburst << 2); 2922 2923 /* Burst write */ 2924 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2925 "Write burst (%#lx dwords)...\n", dburst); 2926 rval = qla2x00_load_ram(vha, optrom_dma, 2927 flash_data_addr(ha, faddr), dburst); 2928 if (rval != QLA_SUCCESS) { 2929 ql_log(ql_log_warn, vha, 0x7097, 2930 "Failed burst write at %x (%p/%#llx)...\n", 2931 flash_data_addr(ha, faddr), optrom, 2932 (u64)optrom_dma); 2933 break; 2934 } 2935 2936 liter += dburst - 1; 2937 faddr += dburst - 1; 2938 dwptr += dburst - 1; 2939 } 2940 2941 write_protect: 2942 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2943 "Protect flash...\n"); 2944 ret = qla24xx_protect_flash(vha); 2945 if (ret) { 2946 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2947 ql_log(ql_log_warn, vha, 0x7099, 2948 "Failed protect flash\n"); 2949 rval = QLA_COMMAND_ERROR; 2950 } 2951 2952 if (reset_to_rom == true) { 2953 /* Schedule DPC to restart the RISC */ 2954 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2955 qla2xxx_wake_dpc(vha); 2956 2957 ret = qla2x00_wait_for_hba_online(vha); 2958 if (ret != QLA_SUCCESS) { 2959 ql_log(ql_log_warn, vha, 0xffff, 2960 "Adapter did not come out of reset\n"); 2961 rval = QLA_COMMAND_ERROR; 2962 } 2963 } 2964 2965 done: 2966 if (optrom) 2967 dma_free_coherent(&ha->pdev->dev, 2968 OPTROM_BURST_SIZE, optrom, optrom_dma); 2969 2970 return rval; 2971 } 2972 2973 int 2974 qla24xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2975 uint32_t offset, uint32_t length) 2976 { 2977 int rval; 2978 struct qla_hw_data *ha = vha->hw; 2979 2980 /* Suspend HBA. */ 2981 scsi_block_requests(vha->host); 2982 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2983 2984 /* Go with write. */ 2985 if (IS_QLA28XX(ha)) 2986 rval = qla28xx_write_flash_data(vha, buf, offset >> 2, 2987 length >> 2); 2988 else 2989 rval = qla24xx_write_flash_data(vha, buf, offset >> 2, 2990 length >> 2); 2991 2992 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2993 scsi_unblock_requests(vha->host); 2994 2995 return rval; 2996 } 2997 2998 void * 2999 qla25xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 3000 uint32_t offset, uint32_t length) 3001 { 3002 int rval; 3003 dma_addr_t optrom_dma; 3004 void *optrom; 3005 uint8_t *pbuf; 3006 uint32_t faddr, left, burst; 3007 struct qla_hw_data *ha = vha->hw; 3008 3009 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 3010 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3011 goto try_fast; 3012 if (offset & 0xfff) 3013 goto slow_read; 3014 if (length < OPTROM_BURST_SIZE) 3015 goto slow_read; 3016 3017 try_fast: 3018 if (offset & 0xff) 3019 goto slow_read; 3020 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3021 &optrom_dma, GFP_KERNEL); 3022 if (!optrom) { 3023 ql_log(ql_log_warn, vha, 0x00cc, 3024 "Unable to allocate memory for optrom burst read (%x KB).\n", 3025 OPTROM_BURST_SIZE / 1024); 3026 goto slow_read; 3027 } 3028 3029 pbuf = buf; 3030 faddr = offset >> 2; 3031 left = length >> 2; 3032 burst = OPTROM_BURST_DWORDS; 3033 while (left != 0) { 3034 if (burst > left) 3035 burst = left; 3036 3037 rval = qla2x00_dump_ram(vha, optrom_dma, 3038 flash_data_addr(ha, faddr), burst); 3039 if (rval) { 3040 ql_log(ql_log_warn, vha, 0x00f5, 3041 "Unable to burst-read optrom segment (%x/%x/%llx).\n", 3042 rval, flash_data_addr(ha, faddr), 3043 (unsigned long long)optrom_dma); 3044 ql_log(ql_log_warn, vha, 0x00f6, 3045 "Reverting to slow-read.\n"); 3046 3047 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3048 optrom, optrom_dma); 3049 goto slow_read; 3050 } 3051 3052 memcpy(pbuf, optrom, burst * 4); 3053 3054 left -= burst; 3055 faddr += burst; 3056 pbuf += burst * 4; 3057 } 3058 3059 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, 3060 optrom_dma); 3061 3062 return buf; 3063 3064 slow_read: 3065 return qla24xx_read_optrom_data(vha, buf, offset, length); 3066 } 3067 3068 /** 3069 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 3070 * @ha: HA context 3071 * @pcids: Pointer to the FCODE PCI data structure 3072 * 3073 * The process of retrieving the FCODE version information is at best 3074 * described as interesting. 3075 * 3076 * Within the first 100h bytes of the image an ASCII string is present 3077 * which contains several pieces of information including the FCODE 3078 * version. Unfortunately it seems the only reliable way to retrieve 3079 * the version is by scanning for another sentinel within the string, 3080 * the FCODE build date: 3081 * 3082 * ... 2.00.02 10/17/02 ... 3083 * 3084 * Returns QLA_SUCCESS on successful retrieval of version. 3085 */ 3086 static void 3087 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) 3088 { 3089 int ret = QLA_FUNCTION_FAILED; 3090 uint32_t istart, iend, iter, vend; 3091 uint8_t do_next, rbyte, *vbyte; 3092 3093 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3094 3095 /* Skip the PCI data structure. */ 3096 istart = pcids + 3097 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 3098 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 3099 iend = istart + 0x100; 3100 do { 3101 /* Scan for the sentinel date string...eeewww. */ 3102 do_next = 0; 3103 iter = istart; 3104 while ((iter < iend) && !do_next) { 3105 iter++; 3106 if (qla2x00_read_flash_byte(ha, iter) == '/') { 3107 if (qla2x00_read_flash_byte(ha, iter + 2) == 3108 '/') 3109 do_next++; 3110 else if (qla2x00_read_flash_byte(ha, 3111 iter + 3) == '/') 3112 do_next++; 3113 } 3114 } 3115 if (!do_next) 3116 break; 3117 3118 /* Backtrack to previous ' ' (space). */ 3119 do_next = 0; 3120 while ((iter > istart) && !do_next) { 3121 iter--; 3122 if (qla2x00_read_flash_byte(ha, iter) == ' ') 3123 do_next++; 3124 } 3125 if (!do_next) 3126 break; 3127 3128 /* 3129 * Mark end of version tag, and find previous ' ' (space) or 3130 * string length (recent FCODE images -- major hack ahead!!!). 3131 */ 3132 vend = iter - 1; 3133 do_next = 0; 3134 while ((iter > istart) && !do_next) { 3135 iter--; 3136 rbyte = qla2x00_read_flash_byte(ha, iter); 3137 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 3138 do_next++; 3139 } 3140 if (!do_next) 3141 break; 3142 3143 /* Mark beginning of version tag, and copy data. */ 3144 iter++; 3145 if ((vend - iter) && 3146 ((vend - iter) < sizeof(ha->fcode_revision))) { 3147 vbyte = ha->fcode_revision; 3148 while (iter <= vend) { 3149 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 3150 iter++; 3151 } 3152 ret = QLA_SUCCESS; 3153 } 3154 } while (0); 3155 3156 if (ret != QLA_SUCCESS) 3157 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3158 } 3159 3160 int 3161 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3162 { 3163 int ret = QLA_SUCCESS; 3164 uint8_t code_type, last_image; 3165 uint32_t pcihdr, pcids; 3166 uint8_t *dbyte; 3167 uint16_t *dcode; 3168 struct qla_hw_data *ha = vha->hw; 3169 3170 if (!ha->pio_address || !mbuf) 3171 return QLA_FUNCTION_FAILED; 3172 3173 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3174 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3175 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3176 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3177 3178 qla2x00_flash_enable(ha); 3179 3180 /* Begin with first PCI expansion ROM header. */ 3181 pcihdr = 0; 3182 last_image = 1; 3183 do { 3184 /* Verify PCI expansion ROM header. */ 3185 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 3186 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 3187 /* No signature */ 3188 ql_log(ql_log_fatal, vha, 0x0050, 3189 "No matching ROM signature.\n"); 3190 ret = QLA_FUNCTION_FAILED; 3191 break; 3192 } 3193 3194 /* Locate PCI data structure. */ 3195 pcids = pcihdr + 3196 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 3197 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 3198 3199 /* Validate signature of PCI data structure. */ 3200 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 3201 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 3202 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 3203 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 3204 /* Incorrect header. */ 3205 ql_log(ql_log_fatal, vha, 0x0051, 3206 "PCI data struct not found pcir_adr=%x.\n", pcids); 3207 ret = QLA_FUNCTION_FAILED; 3208 break; 3209 } 3210 3211 /* Read version */ 3212 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 3213 switch (code_type) { 3214 case ROM_CODE_TYPE_BIOS: 3215 /* Intel x86, PC-AT compatible. */ 3216 ha->bios_revision[0] = 3217 qla2x00_read_flash_byte(ha, pcids + 0x12); 3218 ha->bios_revision[1] = 3219 qla2x00_read_flash_byte(ha, pcids + 0x13); 3220 ql_dbg(ql_dbg_init, vha, 0x0052, 3221 "Read BIOS %d.%d.\n", 3222 ha->bios_revision[1], ha->bios_revision[0]); 3223 break; 3224 case ROM_CODE_TYPE_FCODE: 3225 /* Open Firmware standard for PCI (FCode). */ 3226 /* Eeeewww... */ 3227 qla2x00_get_fcode_version(ha, pcids); 3228 break; 3229 case ROM_CODE_TYPE_EFI: 3230 /* Extensible Firmware Interface (EFI). */ 3231 ha->efi_revision[0] = 3232 qla2x00_read_flash_byte(ha, pcids + 0x12); 3233 ha->efi_revision[1] = 3234 qla2x00_read_flash_byte(ha, pcids + 0x13); 3235 ql_dbg(ql_dbg_init, vha, 0x0053, 3236 "Read EFI %d.%d.\n", 3237 ha->efi_revision[1], ha->efi_revision[0]); 3238 break; 3239 default: 3240 ql_log(ql_log_warn, vha, 0x0054, 3241 "Unrecognized code type %x at pcids %x.\n", 3242 code_type, pcids); 3243 break; 3244 } 3245 3246 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 3247 3248 /* Locate next PCI expansion ROM. */ 3249 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 3250 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 3251 } while (!last_image); 3252 3253 if (IS_QLA2322(ha)) { 3254 /* Read firmware image information. */ 3255 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3256 dbyte = mbuf; 3257 memset(dbyte, 0, 8); 3258 dcode = (uint16_t *)dbyte; 3259 3260 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, 3261 8); 3262 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a, 3263 "Dumping fw " 3264 "ver from flash:.\n"); 3265 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b, 3266 dbyte, 32); 3267 3268 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 3269 dcode[2] == 0xffff && dcode[3] == 0xffff) || 3270 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 3271 dcode[3] == 0)) { 3272 ql_log(ql_log_warn, vha, 0x0057, 3273 "Unrecognized fw revision at %x.\n", 3274 ha->flt_region_fw * 4); 3275 } else { 3276 /* values are in big endian */ 3277 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 3278 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 3279 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 3280 ql_dbg(ql_dbg_init, vha, 0x0058, 3281 "FW Version: " 3282 "%d.%d.%d.\n", ha->fw_revision[0], 3283 ha->fw_revision[1], ha->fw_revision[2]); 3284 } 3285 } 3286 3287 qla2x00_flash_disable(ha); 3288 3289 return ret; 3290 } 3291 3292 int 3293 qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3294 { 3295 int ret = QLA_SUCCESS; 3296 uint32_t pcihdr, pcids; 3297 uint32_t *dcode = mbuf; 3298 uint8_t *bcode = mbuf; 3299 uint8_t code_type, last_image; 3300 struct qla_hw_data *ha = vha->hw; 3301 3302 if (!mbuf) 3303 return QLA_FUNCTION_FAILED; 3304 3305 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3306 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3307 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3308 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3309 3310 /* Begin with first PCI expansion ROM header. */ 3311 pcihdr = ha->flt_region_boot << 2; 3312 last_image = 1; 3313 do { 3314 /* Verify PCI expansion ROM header. */ 3315 ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4); 3316 bcode = mbuf + (pcihdr % 4); 3317 if (memcmp(bcode, "\x55\xaa", 2)) { 3318 /* No signature */ 3319 ql_log(ql_log_fatal, vha, 0x0154, 3320 "No matching ROM signature.\n"); 3321 ret = QLA_FUNCTION_FAILED; 3322 break; 3323 } 3324 3325 /* Locate PCI data structure. */ 3326 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3327 3328 ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4); 3329 bcode = mbuf + (pcihdr % 4); 3330 3331 /* Validate signature of PCI data structure. */ 3332 if (memcmp(bcode, "PCIR", 4)) { 3333 /* Incorrect header. */ 3334 ql_log(ql_log_fatal, vha, 0x0155, 3335 "PCI data struct not found pcir_adr=%x.\n", pcids); 3336 ret = QLA_FUNCTION_FAILED; 3337 break; 3338 } 3339 3340 /* Read version */ 3341 code_type = bcode[0x14]; 3342 switch (code_type) { 3343 case ROM_CODE_TYPE_BIOS: 3344 /* Intel x86, PC-AT compatible. */ 3345 ha->bios_revision[0] = bcode[0x12]; 3346 ha->bios_revision[1] = bcode[0x13]; 3347 ql_dbg(ql_dbg_init, vha, 0x0156, 3348 "Read BIOS %d.%d.\n", 3349 ha->bios_revision[1], ha->bios_revision[0]); 3350 break; 3351 case ROM_CODE_TYPE_FCODE: 3352 /* Open Firmware standard for PCI (FCode). */ 3353 ha->fcode_revision[0] = bcode[0x12]; 3354 ha->fcode_revision[1] = bcode[0x13]; 3355 ql_dbg(ql_dbg_init, vha, 0x0157, 3356 "Read FCODE %d.%d.\n", 3357 ha->fcode_revision[1], ha->fcode_revision[0]); 3358 break; 3359 case ROM_CODE_TYPE_EFI: 3360 /* Extensible Firmware Interface (EFI). */ 3361 ha->efi_revision[0] = bcode[0x12]; 3362 ha->efi_revision[1] = bcode[0x13]; 3363 ql_dbg(ql_dbg_init, vha, 0x0158, 3364 "Read EFI %d.%d.\n", 3365 ha->efi_revision[1], ha->efi_revision[0]); 3366 break; 3367 default: 3368 ql_log(ql_log_warn, vha, 0x0159, 3369 "Unrecognized code type %x at pcids %x.\n", 3370 code_type, pcids); 3371 break; 3372 } 3373 3374 last_image = bcode[0x15] & BIT_7; 3375 3376 /* Locate next PCI expansion ROM. */ 3377 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3378 } while (!last_image); 3379 3380 /* Read firmware image information. */ 3381 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3382 dcode = mbuf; 3383 ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20); 3384 bcode = mbuf + (pcihdr % 4); 3385 3386 /* Validate signature of PCI data structure. */ 3387 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 && 3388 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) { 3389 ha->fw_revision[0] = bcode[0x4]; 3390 ha->fw_revision[1] = bcode[0x5]; 3391 ha->fw_revision[2] = bcode[0x6]; 3392 ql_dbg(ql_dbg_init, vha, 0x0153, 3393 "Firmware revision %d.%d.%d\n", 3394 ha->fw_revision[0], ha->fw_revision[1], 3395 ha->fw_revision[2]); 3396 } 3397 3398 return ret; 3399 } 3400 3401 int 3402 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3403 { 3404 int ret = QLA_SUCCESS; 3405 uint32_t pcihdr = 0, pcids = 0; 3406 uint32_t *dcode = mbuf; 3407 uint8_t *bcode = mbuf; 3408 uint8_t code_type, last_image; 3409 int i; 3410 struct qla_hw_data *ha = vha->hw; 3411 uint32_t faddr = 0; 3412 struct active_regions active_regions = { }; 3413 3414 if (IS_P3P_TYPE(ha)) 3415 return ret; 3416 3417 if (!mbuf) 3418 return QLA_FUNCTION_FAILED; 3419 3420 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3421 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3422 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3423 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3424 3425 pcihdr = ha->flt_region_boot << 2; 3426 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3427 qla27xx_get_active_image(vha, &active_regions); 3428 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) { 3429 pcihdr = ha->flt_region_boot_sec << 2; 3430 } 3431 } 3432 3433 do { 3434 /* Verify PCI expansion ROM header. */ 3435 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 3436 bcode = mbuf + (pcihdr % 4); 3437 if (memcmp(bcode, "\x55\xaa", 2)) { 3438 /* No signature */ 3439 ql_log(ql_log_fatal, vha, 0x0059, 3440 "No matching ROM signature.\n"); 3441 ret = QLA_FUNCTION_FAILED; 3442 break; 3443 } 3444 3445 /* Locate PCI data structure. */ 3446 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3447 3448 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 3449 bcode = mbuf + (pcihdr % 4); 3450 3451 /* Validate signature of PCI data structure. */ 3452 if (memcmp(bcode, "PCIR", 4)) { 3453 /* Incorrect header. */ 3454 ql_log(ql_log_fatal, vha, 0x005a, 3455 "PCI data struct not found pcir_adr=%x.\n", pcids); 3456 ql_dump_buffer(ql_dbg_init, vha, 0x0059, dcode, 32); 3457 ret = QLA_FUNCTION_FAILED; 3458 break; 3459 } 3460 3461 /* Read version */ 3462 code_type = bcode[0x14]; 3463 switch (code_type) { 3464 case ROM_CODE_TYPE_BIOS: 3465 /* Intel x86, PC-AT compatible. */ 3466 ha->bios_revision[0] = bcode[0x12]; 3467 ha->bios_revision[1] = bcode[0x13]; 3468 ql_dbg(ql_dbg_init, vha, 0x005b, 3469 "Read BIOS %d.%d.\n", 3470 ha->bios_revision[1], ha->bios_revision[0]); 3471 break; 3472 case ROM_CODE_TYPE_FCODE: 3473 /* Open Firmware standard for PCI (FCode). */ 3474 ha->fcode_revision[0] = bcode[0x12]; 3475 ha->fcode_revision[1] = bcode[0x13]; 3476 ql_dbg(ql_dbg_init, vha, 0x005c, 3477 "Read FCODE %d.%d.\n", 3478 ha->fcode_revision[1], ha->fcode_revision[0]); 3479 break; 3480 case ROM_CODE_TYPE_EFI: 3481 /* Extensible Firmware Interface (EFI). */ 3482 ha->efi_revision[0] = bcode[0x12]; 3483 ha->efi_revision[1] = bcode[0x13]; 3484 ql_dbg(ql_dbg_init, vha, 0x005d, 3485 "Read EFI %d.%d.\n", 3486 ha->efi_revision[1], ha->efi_revision[0]); 3487 break; 3488 default: 3489 ql_log(ql_log_warn, vha, 0x005e, 3490 "Unrecognized code type %x at pcids %x.\n", 3491 code_type, pcids); 3492 break; 3493 } 3494 3495 last_image = bcode[0x15] & BIT_7; 3496 3497 /* Locate next PCI expansion ROM. */ 3498 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3499 } while (!last_image); 3500 3501 /* Read firmware image information. */ 3502 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3503 faddr = ha->flt_region_fw; 3504 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3505 qla27xx_get_active_image(vha, &active_regions); 3506 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) 3507 faddr = ha->flt_region_fw_sec; 3508 } 3509 3510 qla24xx_read_flash_data(vha, dcode, faddr, 8); 3511 if (qla24xx_risc_firmware_invalid(dcode)) { 3512 ql_log(ql_log_warn, vha, 0x005f, 3513 "Unrecognized fw revision at %x.\n", 3514 ha->flt_region_fw * 4); 3515 ql_dump_buffer(ql_dbg_init, vha, 0x005f, dcode, 32); 3516 } else { 3517 for (i = 0; i < 4; i++) 3518 ha->fw_revision[i] = 3519 be32_to_cpu((__force __be32)dcode[4+i]); 3520 ql_dbg(ql_dbg_init, vha, 0x0060, 3521 "Firmware revision (flash) %u.%u.%u (%x).\n", 3522 ha->fw_revision[0], ha->fw_revision[1], 3523 ha->fw_revision[2], ha->fw_revision[3]); 3524 } 3525 3526 /* Check for golden firmware and get version if available */ 3527 if (!IS_QLA81XX(ha)) { 3528 /* Golden firmware is not present in non 81XX adapters */ 3529 return ret; 3530 } 3531 3532 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); 3533 faddr = ha->flt_region_gold_fw; 3534 qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8); 3535 if (qla24xx_risc_firmware_invalid(dcode)) { 3536 ql_log(ql_log_warn, vha, 0x0056, 3537 "Unrecognized golden fw at %#x.\n", faddr); 3538 ql_dump_buffer(ql_dbg_init, vha, 0x0056, dcode, 32); 3539 return ret; 3540 } 3541 3542 for (i = 0; i < 4; i++) 3543 ha->gold_fw_version[i] = 3544 be32_to_cpu((__force __be32)dcode[4+i]); 3545 3546 return ret; 3547 } 3548 3549 static int 3550 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) 3551 { 3552 if (pos >= end || *pos != 0x82) 3553 return 0; 3554 3555 pos += 3 + pos[1]; 3556 if (pos >= end || *pos != 0x90) 3557 return 0; 3558 3559 pos += 3 + pos[1]; 3560 if (pos >= end || *pos != 0x78) 3561 return 0; 3562 3563 return 1; 3564 } 3565 3566 int 3567 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) 3568 { 3569 struct qla_hw_data *ha = vha->hw; 3570 uint8_t *pos = ha->vpd; 3571 uint8_t *end = pos + ha->vpd_size; 3572 int len = 0; 3573 3574 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) 3575 return 0; 3576 3577 while (pos < end && *pos != 0x78) { 3578 len = (*pos == 0x82) ? pos[1] : pos[2]; 3579 3580 if (!strncmp(pos, key, strlen(key))) 3581 break; 3582 3583 if (*pos != 0x90 && *pos != 0x91) 3584 pos += len; 3585 3586 pos += 3; 3587 } 3588 3589 if (pos < end - len && *pos != 0x78) 3590 return scnprintf(str, size, "%.*s", len, pos + 3); 3591 3592 return 0; 3593 } 3594 3595 int 3596 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha) 3597 { 3598 int len, max_len; 3599 uint32_t fcp_prio_addr; 3600 struct qla_hw_data *ha = vha->hw; 3601 3602 if (!ha->fcp_prio_cfg) { 3603 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); 3604 if (!ha->fcp_prio_cfg) { 3605 ql_log(ql_log_warn, vha, 0x00d5, 3606 "Unable to allocate memory for fcp priority data (%x).\n", 3607 FCP_PRIO_CFG_SIZE); 3608 return QLA_FUNCTION_FAILED; 3609 } 3610 } 3611 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); 3612 3613 fcp_prio_addr = ha->flt_region_fcp_prio; 3614 3615 /* first read the fcp priority data header from flash */ 3616 ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg, 3617 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE); 3618 3619 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0)) 3620 goto fail; 3621 3622 /* read remaining FCP CMD config data from flash */ 3623 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2); 3624 len = ha->fcp_prio_cfg->num_entries * sizeof(struct qla_fcp_prio_entry); 3625 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; 3626 3627 ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0], 3628 fcp_prio_addr << 2, (len < max_len ? len : max_len)); 3629 3630 /* revalidate the entire FCP priority config data, including entries */ 3631 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1)) 3632 goto fail; 3633 3634 ha->flags.fcp_prio_enabled = 1; 3635 return QLA_SUCCESS; 3636 fail: 3637 vfree(ha->fcp_prio_cfg); 3638 ha->fcp_prio_cfg = NULL; 3639 return QLA_FUNCTION_FAILED; 3640 } 3641