1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 #include <asm/uaccess.h> 13 14 /* 15 * NVRAM support routines 16 */ 17 18 /** 19 * qla2x00_lock_nvram_access() - 20 * @ha: HA context 21 */ 22 static void 23 qla2x00_lock_nvram_access(struct qla_hw_data *ha) 24 { 25 uint16_t data; 26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 27 28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 29 data = RD_REG_WORD(®->nvram); 30 while (data & NVR_BUSY) { 31 udelay(100); 32 data = RD_REG_WORD(®->nvram); 33 } 34 35 /* Lock resource */ 36 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 37 RD_REG_WORD(®->u.isp2300.host_semaphore); 38 udelay(5); 39 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 40 while ((data & BIT_0) == 0) { 41 /* Lock failed */ 42 udelay(100); 43 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 44 RD_REG_WORD(®->u.isp2300.host_semaphore); 45 udelay(5); 46 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 47 } 48 } 49 } 50 51 /** 52 * qla2x00_unlock_nvram_access() - 53 * @ha: HA context 54 */ 55 static void 56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha) 57 { 58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 59 60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 61 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); 62 RD_REG_WORD(®->u.isp2300.host_semaphore); 63 } 64 } 65 66 /** 67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 68 * @ha: HA context 69 * @data: Serial interface selector 70 */ 71 static void 72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data) 73 { 74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 75 76 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 77 RD_REG_WORD(®->nvram); /* PCI Posting. */ 78 NVRAM_DELAY(); 79 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK | 80 NVR_WRT_ENABLE); 81 RD_REG_WORD(®->nvram); /* PCI Posting. */ 82 NVRAM_DELAY(); 83 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 84 RD_REG_WORD(®->nvram); /* PCI Posting. */ 85 NVRAM_DELAY(); 86 } 87 88 /** 89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 90 * NVRAM. 91 * @ha: HA context 92 * @nv_cmd: NVRAM command 93 * 94 * Bit definitions for NVRAM command: 95 * 96 * Bit 26 = start bit 97 * Bit 25, 24 = opcode 98 * Bit 23-16 = address 99 * Bit 15-0 = write data 100 * 101 * Returns the word read from nvram @addr. 102 */ 103 static uint16_t 104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) 105 { 106 uint8_t cnt; 107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 108 uint16_t data = 0; 109 uint16_t reg_data; 110 111 /* Send command to NVRAM. */ 112 nv_cmd <<= 5; 113 for (cnt = 0; cnt < 11; cnt++) { 114 if (nv_cmd & BIT_31) 115 qla2x00_nv_write(ha, NVR_DATA_OUT); 116 else 117 qla2x00_nv_write(ha, 0); 118 nv_cmd <<= 1; 119 } 120 121 /* Read data from NVRAM. */ 122 for (cnt = 0; cnt < 16; cnt++) { 123 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); 124 RD_REG_WORD(®->nvram); /* PCI Posting. */ 125 NVRAM_DELAY(); 126 data <<= 1; 127 reg_data = RD_REG_WORD(®->nvram); 128 if (reg_data & NVR_DATA_IN) 129 data |= BIT_0; 130 WRT_REG_WORD(®->nvram, NVR_SELECT); 131 RD_REG_WORD(®->nvram); /* PCI Posting. */ 132 NVRAM_DELAY(); 133 } 134 135 /* Deselect chip. */ 136 WRT_REG_WORD(®->nvram, NVR_DESELECT); 137 RD_REG_WORD(®->nvram); /* PCI Posting. */ 138 NVRAM_DELAY(); 139 140 return data; 141 } 142 143 144 /** 145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 146 * request routine to get the word from NVRAM. 147 * @ha: HA context 148 * @addr: Address in NVRAM to read 149 * 150 * Returns the word read from nvram @addr. 151 */ 152 static uint16_t 153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) 154 { 155 uint16_t data; 156 uint32_t nv_cmd; 157 158 nv_cmd = addr << 16; 159 nv_cmd |= NV_READ_OP; 160 data = qla2x00_nvram_request(ha, nv_cmd); 161 162 return (data); 163 } 164 165 /** 166 * qla2x00_nv_deselect() - Deselect NVRAM operations. 167 * @ha: HA context 168 */ 169 static void 170 qla2x00_nv_deselect(struct qla_hw_data *ha) 171 { 172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 173 174 WRT_REG_WORD(®->nvram, NVR_DESELECT); 175 RD_REG_WORD(®->nvram); /* PCI Posting. */ 176 NVRAM_DELAY(); 177 } 178 179 /** 180 * qla2x00_write_nvram_word() - Write NVRAM data. 181 * @ha: HA context 182 * @addr: Address in NVRAM to write 183 * @data: word to program 184 */ 185 static void 186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data) 187 { 188 int count; 189 uint16_t word; 190 uint32_t nv_cmd, wait_cnt; 191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 192 193 qla2x00_nv_write(ha, NVR_DATA_OUT); 194 qla2x00_nv_write(ha, 0); 195 qla2x00_nv_write(ha, 0); 196 197 for (word = 0; word < 8; word++) 198 qla2x00_nv_write(ha, NVR_DATA_OUT); 199 200 qla2x00_nv_deselect(ha); 201 202 /* Write data */ 203 nv_cmd = (addr << 16) | NV_WRITE_OP; 204 nv_cmd |= data; 205 nv_cmd <<= 5; 206 for (count = 0; count < 27; count++) { 207 if (nv_cmd & BIT_31) 208 qla2x00_nv_write(ha, NVR_DATA_OUT); 209 else 210 qla2x00_nv_write(ha, 0); 211 212 nv_cmd <<= 1; 213 } 214 215 qla2x00_nv_deselect(ha); 216 217 /* Wait for NVRAM to become ready */ 218 WRT_REG_WORD(®->nvram, NVR_SELECT); 219 RD_REG_WORD(®->nvram); /* PCI Posting. */ 220 wait_cnt = NVR_WAIT_CNT; 221 do { 222 if (!--wait_cnt) { 223 DEBUG9_10(qla_printk(KERN_WARNING, ha, 224 "NVRAM didn't go ready...\n")); 225 break; 226 } 227 NVRAM_DELAY(); 228 word = RD_REG_WORD(®->nvram); 229 } while ((word & NVR_DATA_IN) == 0); 230 231 qla2x00_nv_deselect(ha); 232 233 /* Disable writes */ 234 qla2x00_nv_write(ha, NVR_DATA_OUT); 235 for (count = 0; count < 10; count++) 236 qla2x00_nv_write(ha, 0); 237 238 qla2x00_nv_deselect(ha); 239 } 240 241 static int 242 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, 243 uint16_t data, uint32_t tmo) 244 { 245 int ret, count; 246 uint16_t word; 247 uint32_t nv_cmd; 248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 249 250 ret = QLA_SUCCESS; 251 252 qla2x00_nv_write(ha, NVR_DATA_OUT); 253 qla2x00_nv_write(ha, 0); 254 qla2x00_nv_write(ha, 0); 255 256 for (word = 0; word < 8; word++) 257 qla2x00_nv_write(ha, NVR_DATA_OUT); 258 259 qla2x00_nv_deselect(ha); 260 261 /* Write data */ 262 nv_cmd = (addr << 16) | NV_WRITE_OP; 263 nv_cmd |= data; 264 nv_cmd <<= 5; 265 for (count = 0; count < 27; count++) { 266 if (nv_cmd & BIT_31) 267 qla2x00_nv_write(ha, NVR_DATA_OUT); 268 else 269 qla2x00_nv_write(ha, 0); 270 271 nv_cmd <<= 1; 272 } 273 274 qla2x00_nv_deselect(ha); 275 276 /* Wait for NVRAM to become ready */ 277 WRT_REG_WORD(®->nvram, NVR_SELECT); 278 RD_REG_WORD(®->nvram); /* PCI Posting. */ 279 do { 280 NVRAM_DELAY(); 281 word = RD_REG_WORD(®->nvram); 282 if (!--tmo) { 283 ret = QLA_FUNCTION_FAILED; 284 break; 285 } 286 } while ((word & NVR_DATA_IN) == 0); 287 288 qla2x00_nv_deselect(ha); 289 290 /* Disable writes */ 291 qla2x00_nv_write(ha, NVR_DATA_OUT); 292 for (count = 0; count < 10; count++) 293 qla2x00_nv_write(ha, 0); 294 295 qla2x00_nv_deselect(ha); 296 297 return ret; 298 } 299 300 /** 301 * qla2x00_clear_nvram_protection() - 302 * @ha: HA context 303 */ 304 static int 305 qla2x00_clear_nvram_protection(struct qla_hw_data *ha) 306 { 307 int ret, stat; 308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 309 uint32_t word, wait_cnt; 310 uint16_t wprot, wprot_old; 311 312 /* Clear NVRAM write protection. */ 313 ret = QLA_FUNCTION_FAILED; 314 315 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 316 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 317 __constant_cpu_to_le16(0x1234), 100000); 318 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 319 if (stat != QLA_SUCCESS || wprot != 0x1234) { 320 /* Write enable. */ 321 qla2x00_nv_write(ha, NVR_DATA_OUT); 322 qla2x00_nv_write(ha, 0); 323 qla2x00_nv_write(ha, 0); 324 for (word = 0; word < 8; word++) 325 qla2x00_nv_write(ha, NVR_DATA_OUT); 326 327 qla2x00_nv_deselect(ha); 328 329 /* Enable protection register. */ 330 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 331 qla2x00_nv_write(ha, NVR_PR_ENABLE); 332 qla2x00_nv_write(ha, NVR_PR_ENABLE); 333 for (word = 0; word < 8; word++) 334 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 335 336 qla2x00_nv_deselect(ha); 337 338 /* Clear protection register (ffff is cleared). */ 339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 for (word = 0; word < 8; word++) 343 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 344 345 qla2x00_nv_deselect(ha); 346 347 /* Wait for NVRAM to become ready. */ 348 WRT_REG_WORD(®->nvram, NVR_SELECT); 349 RD_REG_WORD(®->nvram); /* PCI Posting. */ 350 wait_cnt = NVR_WAIT_CNT; 351 do { 352 if (!--wait_cnt) { 353 DEBUG9_10(qla_printk(KERN_WARNING, ha, 354 "NVRAM didn't go ready...\n")); 355 break; 356 } 357 NVRAM_DELAY(); 358 word = RD_REG_WORD(®->nvram); 359 } while ((word & NVR_DATA_IN) == 0); 360 361 if (wait_cnt) 362 ret = QLA_SUCCESS; 363 } else 364 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 365 366 return ret; 367 } 368 369 static void 370 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) 371 { 372 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 373 uint32_t word, wait_cnt; 374 375 if (stat != QLA_SUCCESS) 376 return; 377 378 /* Set NVRAM write protection. */ 379 /* Write enable. */ 380 qla2x00_nv_write(ha, NVR_DATA_OUT); 381 qla2x00_nv_write(ha, 0); 382 qla2x00_nv_write(ha, 0); 383 for (word = 0; word < 8; word++) 384 qla2x00_nv_write(ha, NVR_DATA_OUT); 385 386 qla2x00_nv_deselect(ha); 387 388 /* Enable protection register. */ 389 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 390 qla2x00_nv_write(ha, NVR_PR_ENABLE); 391 qla2x00_nv_write(ha, NVR_PR_ENABLE); 392 for (word = 0; word < 8; word++) 393 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 394 395 qla2x00_nv_deselect(ha); 396 397 /* Enable protection register. */ 398 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 399 qla2x00_nv_write(ha, NVR_PR_ENABLE); 400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 401 for (word = 0; word < 8; word++) 402 qla2x00_nv_write(ha, NVR_PR_ENABLE); 403 404 qla2x00_nv_deselect(ha); 405 406 /* Wait for NVRAM to become ready. */ 407 WRT_REG_WORD(®->nvram, NVR_SELECT); 408 RD_REG_WORD(®->nvram); /* PCI Posting. */ 409 wait_cnt = NVR_WAIT_CNT; 410 do { 411 if (!--wait_cnt) { 412 DEBUG9_10(qla_printk(KERN_WARNING, ha, 413 "NVRAM didn't go ready...\n")); 414 break; 415 } 416 NVRAM_DELAY(); 417 word = RD_REG_WORD(®->nvram); 418 } while ((word & NVR_DATA_IN) == 0); 419 } 420 421 422 /*****************************************************************************/ 423 /* Flash Manipulation Routines */ 424 /*****************************************************************************/ 425 426 static inline uint32_t 427 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) 428 { 429 return ha->flash_conf_off | faddr; 430 } 431 432 static inline uint32_t 433 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) 434 { 435 return ha->flash_data_off | faddr; 436 } 437 438 static inline uint32_t 439 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) 440 { 441 return ha->nvram_conf_off | naddr; 442 } 443 444 static inline uint32_t 445 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) 446 { 447 return ha->nvram_data_off | naddr; 448 } 449 450 static uint32_t 451 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr) 452 { 453 int rval; 454 uint32_t cnt, data; 455 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 456 457 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); 458 /* Wait for READ cycle to complete. */ 459 rval = QLA_SUCCESS; 460 for (cnt = 3000; 461 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && 462 rval == QLA_SUCCESS; cnt--) { 463 if (cnt) 464 udelay(10); 465 else 466 rval = QLA_FUNCTION_TIMEOUT; 467 cond_resched(); 468 } 469 470 /* TODO: What happens if we time out? */ 471 data = 0xDEADDEAD; 472 if (rval == QLA_SUCCESS) 473 data = RD_REG_DWORD(®->flash_data); 474 475 return data; 476 } 477 478 uint32_t * 479 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 480 uint32_t dwords) 481 { 482 uint32_t i; 483 struct qla_hw_data *ha = vha->hw; 484 485 /* Dword reads to flash. */ 486 for (i = 0; i < dwords; i++, faddr++) 487 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 488 flash_data_addr(ha, faddr))); 489 490 return dwptr; 491 } 492 493 static int 494 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) 495 { 496 int rval; 497 uint32_t cnt; 498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 499 500 WRT_REG_DWORD(®->flash_data, data); 501 RD_REG_DWORD(®->flash_data); /* PCI Posting. */ 502 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); 503 /* Wait for Write cycle to complete. */ 504 rval = QLA_SUCCESS; 505 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && 506 rval == QLA_SUCCESS; cnt--) { 507 if (cnt) 508 udelay(10); 509 else 510 rval = QLA_FUNCTION_TIMEOUT; 511 cond_resched(); 512 } 513 return rval; 514 } 515 516 static void 517 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 518 uint8_t *flash_id) 519 { 520 uint32_t ids; 521 522 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab)); 523 *man_id = LSB(ids); 524 *flash_id = MSB(ids); 525 526 /* Check if man_id and flash_id are valid. */ 527 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 528 /* Read information using 0x9f opcode 529 * Device ID, Mfg ID would be read in the format: 530 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 531 * Example: ATMEL 0x00 01 45 1F 532 * Extract MFG and Dev ID from last two bytes. 533 */ 534 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f)); 535 *man_id = LSB(ids); 536 *flash_id = MSB(ids); 537 } 538 } 539 540 static int 541 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) 542 { 543 const char *loc, *locations[] = { "DEF", "PCI" }; 544 uint32_t pcihdr, pcids; 545 uint32_t *dcode; 546 uint8_t *buf, *bcode, last_image; 547 uint16_t cnt, chksum, *wptr; 548 struct qla_flt_location *fltl; 549 struct qla_hw_data *ha = vha->hw; 550 struct req_que *req = ha->req_q_map[0]; 551 552 /* 553 * FLT-location structure resides after the last PCI region. 554 */ 555 556 /* Begin with sane defaults. */ 557 loc = locations[0]; 558 *start = 0; 559 if (IS_QLA24XX_TYPE(ha)) 560 *start = FA_FLASH_LAYOUT_ADDR_24; 561 else if (IS_QLA25XX(ha)) 562 *start = FA_FLASH_LAYOUT_ADDR; 563 else if (IS_QLA81XX(ha)) 564 *start = FA_FLASH_LAYOUT_ADDR_81; 565 else if (IS_QLA82XX(ha)) { 566 *start = FA_FLASH_LAYOUT_ADDR_82; 567 goto end; 568 } 569 /* Begin with first PCI expansion ROM header. */ 570 buf = (uint8_t *)req->ring; 571 dcode = (uint32_t *)req->ring; 572 pcihdr = 0; 573 last_image = 1; 574 do { 575 /* Verify PCI expansion ROM header. */ 576 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 577 bcode = buf + (pcihdr % 4); 578 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) 579 goto end; 580 581 /* Locate PCI data structure. */ 582 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 583 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 584 bcode = buf + (pcihdr % 4); 585 586 /* Validate signature of PCI data structure. */ 587 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 588 bcode[0x2] != 'I' || bcode[0x3] != 'R') 589 goto end; 590 591 last_image = bcode[0x15] & BIT_7; 592 593 /* Locate next PCI expansion ROM. */ 594 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 595 } while (!last_image); 596 597 /* Now verify FLT-location structure. */ 598 fltl = (struct qla_flt_location *)req->ring; 599 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 600 sizeof(struct qla_flt_location) >> 2); 601 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' || 602 fltl->sig[2] != 'L' || fltl->sig[3] != 'T') 603 goto end; 604 605 wptr = (uint16_t *)req->ring; 606 cnt = sizeof(struct qla_flt_location) >> 1; 607 for (chksum = 0; cnt; cnt--) 608 chksum += le16_to_cpu(*wptr++); 609 if (chksum) { 610 qla_printk(KERN_ERR, ha, 611 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); 612 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location)); 613 return QLA_FUNCTION_FAILED; 614 } 615 616 /* Good data. Use specified location. */ 617 loc = locations[1]; 618 *start = (le16_to_cpu(fltl->start_hi) << 16 | 619 le16_to_cpu(fltl->start_lo)) >> 2; 620 end: 621 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 622 return QLA_SUCCESS; 623 } 624 625 static void 626 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) 627 { 628 const char *loc, *locations[] = { "DEF", "FLT" }; 629 const uint32_t def_fw[] = 630 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 }; 631 const uint32_t def_boot[] = 632 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 }; 633 const uint32_t def_vpd_nvram[] = 634 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 }; 635 const uint32_t def_vpd0[] = 636 { 0, 0, FA_VPD0_ADDR_81 }; 637 const uint32_t def_vpd1[] = 638 { 0, 0, FA_VPD1_ADDR_81 }; 639 const uint32_t def_nvram0[] = 640 { 0, 0, FA_NVRAM0_ADDR_81 }; 641 const uint32_t def_nvram1[] = 642 { 0, 0, FA_NVRAM1_ADDR_81 }; 643 const uint32_t def_fdt[] = 644 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR, 645 FA_FLASH_DESCR_ADDR_81 }; 646 const uint32_t def_npiv_conf0[] = 647 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR, 648 FA_NPIV_CONF0_ADDR_81 }; 649 const uint32_t def_npiv_conf1[] = 650 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR, 651 FA_NPIV_CONF1_ADDR_81 }; 652 const uint32_t fcp_prio_cfg0[] = 653 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25, 654 0 }; 655 const uint32_t fcp_prio_cfg1[] = 656 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25, 657 0 }; 658 uint32_t def; 659 uint16_t *wptr; 660 uint16_t cnt, chksum; 661 uint32_t start; 662 struct qla_flt_header *flt; 663 struct qla_flt_region *region; 664 struct qla_hw_data *ha = vha->hw; 665 struct req_que *req = ha->req_q_map[0]; 666 667 def = 0; 668 if (IS_QLA25XX(ha)) 669 def = 1; 670 else if (IS_QLA81XX(ha)) 671 def = 2; 672 ha->flt_region_flt = flt_addr; 673 wptr = (uint16_t *)req->ring; 674 flt = (struct qla_flt_header *)req->ring; 675 region = (struct qla_flt_region *)&flt[1]; 676 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, 677 flt_addr << 2, OPTROM_BURST_SIZE); 678 if (*wptr == __constant_cpu_to_le16(0xffff)) 679 goto no_flash_data; 680 if (flt->version != __constant_cpu_to_le16(1)) { 681 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: " 682 "version=0x%x length=0x%x checksum=0x%x.\n", 683 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 684 le16_to_cpu(flt->checksum))); 685 goto no_flash_data; 686 } 687 688 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 689 for (chksum = 0; cnt; cnt--) 690 chksum += le16_to_cpu(*wptr++); 691 if (chksum) { 692 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 693 "version=0x%x length=0x%x checksum=0x%x.\n", 694 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 695 chksum)); 696 goto no_flash_data; 697 } 698 699 /* Assign FCP prio region since older FLT's may not have it */ 700 ha->flt_region_fcp_prio = ha->flags.port0 ? 701 fcp_prio_cfg0[def] : fcp_prio_cfg1[def]; 702 703 loc = locations[1]; 704 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 705 for ( ; cnt; cnt--, region++) { 706 /* Store addresses as DWORD offsets. */ 707 start = le32_to_cpu(region->start) >> 2; 708 709 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 710 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 711 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 712 713 switch (le32_to_cpu(region->code) & 0xff) { 714 case FLT_REG_FW: 715 ha->flt_region_fw = start; 716 break; 717 case FLT_REG_BOOT_CODE: 718 ha->flt_region_boot = start; 719 break; 720 case FLT_REG_VPD_0: 721 ha->flt_region_vpd_nvram = start; 722 if (IS_QLA82XX(ha)) 723 break; 724 if (ha->flags.port0) 725 ha->flt_region_vpd = start; 726 break; 727 case FLT_REG_VPD_1: 728 if (IS_QLA82XX(ha)) 729 break; 730 if (!ha->flags.port0) 731 ha->flt_region_vpd = start; 732 break; 733 case FLT_REG_NVRAM_0: 734 if (ha->flags.port0) 735 ha->flt_region_nvram = start; 736 break; 737 case FLT_REG_NVRAM_1: 738 if (!ha->flags.port0) 739 ha->flt_region_nvram = start; 740 break; 741 case FLT_REG_FDT: 742 ha->flt_region_fdt = start; 743 break; 744 case FLT_REG_NPIV_CONF_0: 745 if (ha->flags.port0) 746 ha->flt_region_npiv_conf = start; 747 break; 748 case FLT_REG_NPIV_CONF_1: 749 if (!ha->flags.port0) 750 ha->flt_region_npiv_conf = start; 751 break; 752 case FLT_REG_GOLD_FW: 753 ha->flt_region_gold_fw = start; 754 break; 755 case FLT_REG_FCP_PRIO_0: 756 if (ha->flags.port0) 757 ha->flt_region_fcp_prio = start; 758 break; 759 case FLT_REG_FCP_PRIO_1: 760 if (!ha->flags.port0) 761 ha->flt_region_fcp_prio = start; 762 break; 763 case FLT_REG_BOOT_CODE_82XX: 764 ha->flt_region_boot = start; 765 break; 766 case FLT_REG_FW_82XX: 767 ha->flt_region_fw = start; 768 break; 769 case FLT_REG_GOLD_FW_82XX: 770 ha->flt_region_gold_fw = start; 771 break; 772 case FLT_REG_BOOTLOAD_82XX: 773 ha->flt_region_bootload = start; 774 break; 775 case FLT_REG_VPD_82XX: 776 ha->flt_region_vpd = start; 777 break; 778 } 779 } 780 goto done; 781 782 no_flash_data: 783 /* Use hardcoded defaults. */ 784 loc = locations[0]; 785 ha->flt_region_fw = def_fw[def]; 786 ha->flt_region_boot = def_boot[def]; 787 ha->flt_region_vpd_nvram = def_vpd_nvram[def]; 788 ha->flt_region_vpd = ha->flags.port0 ? 789 def_vpd0[def] : def_vpd1[def]; 790 ha->flt_region_nvram = ha->flags.port0 ? 791 def_nvram0[def] : def_nvram1[def]; 792 ha->flt_region_fdt = def_fdt[def]; 793 ha->flt_region_npiv_conf = ha->flags.port0 ? 794 def_npiv_conf0[def] : def_npiv_conf1[def]; 795 done: 796 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x " 797 "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x " 798 "npiv=0x%x. fcp_prio_cfg=0x%x\n", loc, ha->flt_region_boot, 799 ha->flt_region_fw, ha->flt_region_vpd_nvram, ha->flt_region_vpd, 800 ha->flt_region_nvram, ha->flt_region_fdt, ha->flt_region_flt, 801 ha->flt_region_npiv_conf, ha->flt_region_fcp_prio)); 802 } 803 804 static void 805 qla2xxx_get_fdt_info(scsi_qla_host_t *vha) 806 { 807 #define FLASH_BLK_SIZE_4K 0x1000 808 #define FLASH_BLK_SIZE_32K 0x8000 809 #define FLASH_BLK_SIZE_64K 0x10000 810 const char *loc, *locations[] = { "MID", "FDT" }; 811 uint16_t cnt, chksum; 812 uint16_t *wptr; 813 struct qla_fdt_layout *fdt; 814 uint8_t man_id, flash_id; 815 uint16_t mid = 0, fid = 0; 816 struct qla_hw_data *ha = vha->hw; 817 struct req_que *req = ha->req_q_map[0]; 818 819 wptr = (uint16_t *)req->ring; 820 fdt = (struct qla_fdt_layout *)req->ring; 821 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, 822 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE); 823 if (*wptr == __constant_cpu_to_le16(0xffff)) 824 goto no_flash_data; 825 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 826 fdt->sig[3] != 'D') 827 goto no_flash_data; 828 829 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 830 cnt++) 831 chksum += le16_to_cpu(*wptr++); 832 if (chksum) { 833 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 834 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 835 le16_to_cpu(fdt->version))); 836 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt))); 837 goto no_flash_data; 838 } 839 840 loc = locations[1]; 841 mid = le16_to_cpu(fdt->man_id); 842 fid = le16_to_cpu(fdt->id); 843 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 844 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); 845 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 846 if (fdt->unprotect_sec_cmd) { 847 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | 848 fdt->unprotect_sec_cmd); 849 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 850 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd): 851 flash_conf_addr(ha, 0x0336); 852 } 853 goto done; 854 no_flash_data: 855 loc = locations[0]; 856 if (IS_QLA82XX(ha)) { 857 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 858 goto done; 859 } 860 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 861 mid = man_id; 862 fid = flash_id; 863 ha->fdt_wrt_disable = 0x9c; 864 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); 865 switch (man_id) { 866 case 0xbf: /* STT flash. */ 867 if (flash_id == 0x8e) 868 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 869 else 870 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 871 872 if (flash_id == 0x80) 873 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); 874 break; 875 case 0x13: /* ST M25P80. */ 876 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 877 break; 878 case 0x1f: /* Atmel 26DF081A. */ 879 ha->fdt_block_size = FLASH_BLK_SIZE_4K; 880 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); 881 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); 882 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); 883 break; 884 default: 885 /* Default to 64 kb sector size. */ 886 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 887 break; 888 } 889 done: 890 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 891 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 892 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, 893 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable, 894 ha->fdt_block_size)); 895 } 896 897 static void 898 qla2xxx_get_idc_param(scsi_qla_host_t *vha) 899 { 900 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 901 uint32_t *wptr; 902 struct qla_hw_data *ha = vha->hw; 903 struct req_que *req = ha->req_q_map[0]; 904 905 if (!IS_QLA82XX(ha)) 906 return; 907 908 wptr = (uint32_t *)req->ring; 909 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, 910 QLA82XX_IDC_PARAM_ADDR , 8); 911 912 if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 913 ha->nx_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; 914 ha->nx_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; 915 } else { 916 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 917 ha->nx_reset_timeout = le32_to_cpu(*wptr); 918 } 919 return; 920 } 921 922 int 923 qla2xxx_get_flash_info(scsi_qla_host_t *vha) 924 { 925 int ret; 926 uint32_t flt_addr; 927 struct qla_hw_data *ha = vha->hw; 928 929 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha)) 930 return QLA_SUCCESS; 931 932 ret = qla2xxx_find_flt_start(vha, &flt_addr); 933 if (ret != QLA_SUCCESS) 934 return ret; 935 936 qla2xxx_get_flt_info(vha, flt_addr); 937 qla2xxx_get_fdt_info(vha); 938 qla2xxx_get_idc_param(vha); 939 940 return QLA_SUCCESS; 941 } 942 943 void 944 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) 945 { 946 #define NPIV_CONFIG_SIZE (16*1024) 947 void *data; 948 uint16_t *wptr; 949 uint16_t cnt, chksum; 950 int i; 951 struct qla_npiv_header hdr; 952 struct qla_npiv_entry *entry; 953 struct qla_hw_data *ha = vha->hw; 954 955 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha)) 956 return; 957 958 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr, 959 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header)); 960 if (hdr.version == __constant_cpu_to_le16(0xffff)) 961 return; 962 if (hdr.version != __constant_cpu_to_le16(1)) { 963 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config " 964 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 965 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 966 le16_to_cpu(hdr.checksum))); 967 return; 968 } 969 970 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); 971 if (!data) { 972 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to " 973 "allocate memory.\n")); 974 return; 975 } 976 977 ha->isp_ops->read_optrom(vha, (uint8_t *)data, 978 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE); 979 980 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) * 981 sizeof(struct qla_npiv_entry)) >> 1; 982 for (wptr = data, chksum = 0; cnt; cnt--) 983 chksum += le16_to_cpu(*wptr++); 984 if (chksum) { 985 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config " 986 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 987 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 988 chksum)); 989 goto done; 990 } 991 992 entry = data + sizeof(struct qla_npiv_header); 993 cnt = le16_to_cpu(hdr.entries); 994 for (i = 0; cnt; cnt--, entry++, i++) { 995 uint16_t flags; 996 struct fc_vport_identifiers vid; 997 struct fc_vport *vport; 998 999 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); 1000 1001 flags = le16_to_cpu(entry->flags); 1002 if (flags == 0xffff) 1003 continue; 1004 if ((flags & BIT_0) == 0) 1005 continue; 1006 1007 memset(&vid, 0, sizeof(vid)); 1008 vid.roles = FC_PORT_ROLE_FCP_INITIATOR; 1009 vid.vport_type = FC_PORTTYPE_NPIV; 1010 vid.disable = false; 1011 vid.port_name = wwn_to_u64(entry->port_name); 1012 vid.node_name = wwn_to_u64(entry->node_name); 1013 1014 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV[%02x]: wwpn=%llx " 1015 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt, 1016 (unsigned long long)vid.port_name, 1017 (unsigned long long)vid.node_name, 1018 le16_to_cpu(entry->vf_id), 1019 entry->q_qos, entry->f_qos)); 1020 1021 if (i < QLA_PRECONFIG_VPORTS) { 1022 vport = fc_vport_create(vha->host, 0, &vid); 1023 if (!vport) 1024 qla_printk(KERN_INFO, ha, 1025 "NPIV-Config: Failed to create vport [%02x]: " 1026 "wwpn=%llx wwnn=%llx.\n", cnt, 1027 (unsigned long long)vid.port_name, 1028 (unsigned long long)vid.node_name); 1029 } 1030 } 1031 done: 1032 kfree(data); 1033 } 1034 1035 static int 1036 qla24xx_unprotect_flash(scsi_qla_host_t *vha) 1037 { 1038 struct qla_hw_data *ha = vha->hw; 1039 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1040 1041 if (ha->flags.fac_supported) 1042 return qla81xx_fac_do_write_enable(vha, 1); 1043 1044 /* Enable flash write. */ 1045 WRT_REG_DWORD(®->ctrl_status, 1046 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1047 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1048 1049 if (!ha->fdt_wrt_disable) 1050 goto done; 1051 1052 /* Disable flash write-protection, first clear SR protection bit */ 1053 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1054 /* Then write zero again to clear remaining SR bits.*/ 1055 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1056 done: 1057 return QLA_SUCCESS; 1058 } 1059 1060 static int 1061 qla24xx_protect_flash(scsi_qla_host_t *vha) 1062 { 1063 uint32_t cnt; 1064 struct qla_hw_data *ha = vha->hw; 1065 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1066 1067 if (ha->flags.fac_supported) 1068 return qla81xx_fac_do_write_enable(vha, 0); 1069 1070 if (!ha->fdt_wrt_disable) 1071 goto skip_wrt_protect; 1072 1073 /* Enable flash write-protection and wait for completion. */ 1074 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 1075 ha->fdt_wrt_disable); 1076 for (cnt = 300; cnt && 1077 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0; 1078 cnt--) { 1079 udelay(10); 1080 } 1081 1082 skip_wrt_protect: 1083 /* Disable flash write. */ 1084 WRT_REG_DWORD(®->ctrl_status, 1085 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1086 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1087 1088 return QLA_SUCCESS; 1089 } 1090 1091 static int 1092 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) 1093 { 1094 struct qla_hw_data *ha = vha->hw; 1095 uint32_t start, finish; 1096 1097 if (ha->flags.fac_supported) { 1098 start = fdata >> 2; 1099 finish = start + (ha->fdt_block_size >> 2) - 1; 1100 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha, 1101 start), flash_data_addr(ha, finish)); 1102 } 1103 1104 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, 1105 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) | 1106 ((fdata >> 16) & 0xff)); 1107 } 1108 1109 static int 1110 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 1111 uint32_t dwords) 1112 { 1113 int ret; 1114 uint32_t liter; 1115 uint32_t sec_mask, rest_addr; 1116 uint32_t fdata; 1117 dma_addr_t optrom_dma; 1118 void *optrom = NULL; 1119 struct qla_hw_data *ha = vha->hw; 1120 1121 /* Prepare burst-capable write on supported ISPs. */ 1122 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) && 1123 dwords > OPTROM_BURST_DWORDS) { 1124 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 1125 &optrom_dma, GFP_KERNEL); 1126 if (!optrom) { 1127 qla_printk(KERN_DEBUG, ha, 1128 "Unable to allocate memory for optrom burst write " 1129 "(%x KB).\n", OPTROM_BURST_SIZE / 1024); 1130 } 1131 } 1132 1133 rest_addr = (ha->fdt_block_size >> 2) - 1; 1134 sec_mask = ~rest_addr; 1135 1136 ret = qla24xx_unprotect_flash(vha); 1137 if (ret != QLA_SUCCESS) { 1138 qla_printk(KERN_WARNING, ha, 1139 "Unable to unprotect flash for update.\n"); 1140 goto done; 1141 } 1142 1143 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 1144 fdata = (faddr & sec_mask) << 2; 1145 1146 /* Are we at the beginning of a sector? */ 1147 if ((faddr & rest_addr) == 0) { 1148 /* Do sector unprotect. */ 1149 if (ha->fdt_unprotect_sec_cmd) 1150 qla24xx_write_flash_dword(ha, 1151 ha->fdt_unprotect_sec_cmd, 1152 (fdata & 0xff00) | ((fdata << 16) & 1153 0xff0000) | ((fdata >> 16) & 0xff)); 1154 ret = qla24xx_erase_sector(vha, fdata); 1155 if (ret != QLA_SUCCESS) { 1156 DEBUG9(qla_printk(KERN_WARNING, ha, 1157 "Unable to erase sector: address=%x.\n", 1158 faddr)); 1159 break; 1160 } 1161 } 1162 1163 /* Go with burst-write. */ 1164 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 1165 /* Copy data to DMA'ble buffer. */ 1166 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 1167 1168 ret = qla2x00_load_ram(vha, optrom_dma, 1169 flash_data_addr(ha, faddr), 1170 OPTROM_BURST_DWORDS); 1171 if (ret != QLA_SUCCESS) { 1172 qla_printk(KERN_WARNING, ha, 1173 "Unable to burst-write optrom segment " 1174 "(%x/%x/%llx).\n", ret, 1175 flash_data_addr(ha, faddr), 1176 (unsigned long long)optrom_dma); 1177 qla_printk(KERN_WARNING, ha, 1178 "Reverting to slow-write.\n"); 1179 1180 dma_free_coherent(&ha->pdev->dev, 1181 OPTROM_BURST_SIZE, optrom, optrom_dma); 1182 optrom = NULL; 1183 } else { 1184 liter += OPTROM_BURST_DWORDS - 1; 1185 faddr += OPTROM_BURST_DWORDS - 1; 1186 dwptr += OPTROM_BURST_DWORDS - 1; 1187 continue; 1188 } 1189 } 1190 1191 ret = qla24xx_write_flash_dword(ha, 1192 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr)); 1193 if (ret != QLA_SUCCESS) { 1194 DEBUG9(printk("%s(%ld) Unable to program flash " 1195 "address=%x data=%x.\n", __func__, 1196 vha->host_no, faddr, *dwptr)); 1197 break; 1198 } 1199 1200 /* Do sector protect. */ 1201 if (ha->fdt_unprotect_sec_cmd && 1202 ((faddr & rest_addr) == rest_addr)) 1203 qla24xx_write_flash_dword(ha, 1204 ha->fdt_protect_sec_cmd, 1205 (fdata & 0xff00) | ((fdata << 16) & 1206 0xff0000) | ((fdata >> 16) & 0xff)); 1207 } 1208 1209 ret = qla24xx_protect_flash(vha); 1210 if (ret != QLA_SUCCESS) 1211 qla_printk(KERN_WARNING, ha, 1212 "Unable to protect flash after update.\n"); 1213 done: 1214 if (optrom) 1215 dma_free_coherent(&ha->pdev->dev, 1216 OPTROM_BURST_SIZE, optrom, optrom_dma); 1217 1218 return ret; 1219 } 1220 1221 uint8_t * 1222 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1223 uint32_t bytes) 1224 { 1225 uint32_t i; 1226 uint16_t *wptr; 1227 struct qla_hw_data *ha = vha->hw; 1228 1229 /* Word reads to NVRAM via registers. */ 1230 wptr = (uint16_t *)buf; 1231 qla2x00_lock_nvram_access(ha); 1232 for (i = 0; i < bytes >> 1; i++, naddr++) 1233 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 1234 naddr)); 1235 qla2x00_unlock_nvram_access(ha); 1236 1237 return buf; 1238 } 1239 1240 uint8_t * 1241 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1242 uint32_t bytes) 1243 { 1244 uint32_t i; 1245 uint32_t *dwptr; 1246 struct qla_hw_data *ha = vha->hw; 1247 1248 if (IS_QLA82XX(ha)) 1249 return buf; 1250 1251 /* Dword reads to flash. */ 1252 dwptr = (uint32_t *)buf; 1253 for (i = 0; i < bytes >> 2; i++, naddr++) 1254 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 1255 nvram_data_addr(ha, naddr))); 1256 1257 return buf; 1258 } 1259 1260 int 1261 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1262 uint32_t bytes) 1263 { 1264 int ret, stat; 1265 uint32_t i; 1266 uint16_t *wptr; 1267 unsigned long flags; 1268 struct qla_hw_data *ha = vha->hw; 1269 1270 ret = QLA_SUCCESS; 1271 1272 spin_lock_irqsave(&ha->hardware_lock, flags); 1273 qla2x00_lock_nvram_access(ha); 1274 1275 /* Disable NVRAM write-protection. */ 1276 stat = qla2x00_clear_nvram_protection(ha); 1277 1278 wptr = (uint16_t *)buf; 1279 for (i = 0; i < bytes >> 1; i++, naddr++) { 1280 qla2x00_write_nvram_word(ha, naddr, 1281 cpu_to_le16(*wptr)); 1282 wptr++; 1283 } 1284 1285 /* Enable NVRAM write-protection. */ 1286 qla2x00_set_nvram_protection(ha, stat); 1287 1288 qla2x00_unlock_nvram_access(ha); 1289 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1290 1291 return ret; 1292 } 1293 1294 int 1295 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1296 uint32_t bytes) 1297 { 1298 int ret; 1299 uint32_t i; 1300 uint32_t *dwptr; 1301 struct qla_hw_data *ha = vha->hw; 1302 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1303 1304 ret = QLA_SUCCESS; 1305 1306 if (IS_QLA82XX(ha)) 1307 return ret; 1308 1309 /* Enable flash write. */ 1310 WRT_REG_DWORD(®->ctrl_status, 1311 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1312 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1313 1314 /* Disable NVRAM write-protection. */ 1315 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1316 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1317 1318 /* Dword writes to flash. */ 1319 dwptr = (uint32_t *)buf; 1320 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) { 1321 ret = qla24xx_write_flash_dword(ha, 1322 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr)); 1323 if (ret != QLA_SUCCESS) { 1324 DEBUG9(qla_printk(KERN_WARNING, ha, 1325 "Unable to program nvram address=%x data=%x.\n", 1326 naddr, *dwptr)); 1327 break; 1328 } 1329 } 1330 1331 /* Enable NVRAM write-protection. */ 1332 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c); 1333 1334 /* Disable flash write. */ 1335 WRT_REG_DWORD(®->ctrl_status, 1336 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1337 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1338 1339 return ret; 1340 } 1341 1342 uint8_t * 1343 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1344 uint32_t bytes) 1345 { 1346 uint32_t i; 1347 uint32_t *dwptr; 1348 struct qla_hw_data *ha = vha->hw; 1349 1350 /* Dword reads to flash. */ 1351 dwptr = (uint32_t *)buf; 1352 for (i = 0; i < bytes >> 2; i++, naddr++) 1353 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 1354 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr))); 1355 1356 return buf; 1357 } 1358 1359 int 1360 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1361 uint32_t bytes) 1362 { 1363 struct qla_hw_data *ha = vha->hw; 1364 #define RMW_BUFFER_SIZE (64 * 1024) 1365 uint8_t *dbuf; 1366 1367 dbuf = vmalloc(RMW_BUFFER_SIZE); 1368 if (!dbuf) 1369 return QLA_MEMORY_ALLOC_FAILED; 1370 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1371 RMW_BUFFER_SIZE); 1372 memcpy(dbuf + (naddr << 2), buf, bytes); 1373 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1374 RMW_BUFFER_SIZE); 1375 vfree(dbuf); 1376 1377 return QLA_SUCCESS; 1378 } 1379 1380 static inline void 1381 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1382 { 1383 if (IS_QLA2322(ha)) { 1384 /* Flip all colors. */ 1385 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1386 /* Turn off. */ 1387 ha->beacon_color_state = 0; 1388 *pflags = GPIO_LED_ALL_OFF; 1389 } else { 1390 /* Turn on. */ 1391 ha->beacon_color_state = QLA_LED_ALL_ON; 1392 *pflags = GPIO_LED_RGA_ON; 1393 } 1394 } else { 1395 /* Flip green led only. */ 1396 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 1397 /* Turn off. */ 1398 ha->beacon_color_state = 0; 1399 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 1400 } else { 1401 /* Turn on. */ 1402 ha->beacon_color_state = QLA_LED_GRN_ON; 1403 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 1404 } 1405 } 1406 } 1407 1408 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) 1409 1410 void 1411 qla2x00_beacon_blink(struct scsi_qla_host *vha) 1412 { 1413 uint16_t gpio_enable; 1414 uint16_t gpio_data; 1415 uint16_t led_color = 0; 1416 unsigned long flags; 1417 struct qla_hw_data *ha = vha->hw; 1418 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1419 1420 if (IS_QLA82XX(ha)) 1421 return; 1422 1423 spin_lock_irqsave(&ha->hardware_lock, flags); 1424 1425 /* Save the Original GPIOE. */ 1426 if (ha->pio_address) { 1427 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1428 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1429 } else { 1430 gpio_enable = RD_REG_WORD(®->gpioe); 1431 gpio_data = RD_REG_WORD(®->gpiod); 1432 } 1433 1434 /* Set the modified gpio_enable values */ 1435 gpio_enable |= GPIO_LED_MASK; 1436 1437 if (ha->pio_address) { 1438 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1439 } else { 1440 WRT_REG_WORD(®->gpioe, gpio_enable); 1441 RD_REG_WORD(®->gpioe); 1442 } 1443 1444 qla2x00_flip_colors(ha, &led_color); 1445 1446 /* Clear out any previously set LED color. */ 1447 gpio_data &= ~GPIO_LED_MASK; 1448 1449 /* Set the new input LED color to GPIOD. */ 1450 gpio_data |= led_color; 1451 1452 /* Set the modified gpio_data values */ 1453 if (ha->pio_address) { 1454 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1455 } else { 1456 WRT_REG_WORD(®->gpiod, gpio_data); 1457 RD_REG_WORD(®->gpiod); 1458 } 1459 1460 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1461 } 1462 1463 int 1464 qla2x00_beacon_on(struct scsi_qla_host *vha) 1465 { 1466 uint16_t gpio_enable; 1467 uint16_t gpio_data; 1468 unsigned long flags; 1469 struct qla_hw_data *ha = vha->hw; 1470 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1471 1472 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1473 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 1474 1475 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1476 qla_printk(KERN_WARNING, ha, 1477 "Unable to update fw options (beacon on).\n"); 1478 return QLA_FUNCTION_FAILED; 1479 } 1480 1481 /* Turn off LEDs. */ 1482 spin_lock_irqsave(&ha->hardware_lock, flags); 1483 if (ha->pio_address) { 1484 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1485 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1486 } else { 1487 gpio_enable = RD_REG_WORD(®->gpioe); 1488 gpio_data = RD_REG_WORD(®->gpiod); 1489 } 1490 gpio_enable |= GPIO_LED_MASK; 1491 1492 /* Set the modified gpio_enable values. */ 1493 if (ha->pio_address) { 1494 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1495 } else { 1496 WRT_REG_WORD(®->gpioe, gpio_enable); 1497 RD_REG_WORD(®->gpioe); 1498 } 1499 1500 /* Clear out previously set LED colour. */ 1501 gpio_data &= ~GPIO_LED_MASK; 1502 if (ha->pio_address) { 1503 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1504 } else { 1505 WRT_REG_WORD(®->gpiod, gpio_data); 1506 RD_REG_WORD(®->gpiod); 1507 } 1508 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1509 1510 /* 1511 * Let the per HBA timer kick off the blinking process based on 1512 * the following flags. No need to do anything else now. 1513 */ 1514 ha->beacon_blink_led = 1; 1515 ha->beacon_color_state = 0; 1516 1517 return QLA_SUCCESS; 1518 } 1519 1520 int 1521 qla2x00_beacon_off(struct scsi_qla_host *vha) 1522 { 1523 int rval = QLA_SUCCESS; 1524 struct qla_hw_data *ha = vha->hw; 1525 1526 ha->beacon_blink_led = 0; 1527 1528 /* Set the on flag so when it gets flipped it will be off. */ 1529 if (IS_QLA2322(ha)) 1530 ha->beacon_color_state = QLA_LED_ALL_ON; 1531 else 1532 ha->beacon_color_state = QLA_LED_GRN_ON; 1533 1534 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ 1535 1536 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1537 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 1538 1539 rval = qla2x00_set_fw_options(vha, ha->fw_options); 1540 if (rval != QLA_SUCCESS) 1541 qla_printk(KERN_WARNING, ha, 1542 "Unable to update fw options (beacon off).\n"); 1543 return rval; 1544 } 1545 1546 1547 static inline void 1548 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1549 { 1550 /* Flip all colors. */ 1551 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1552 /* Turn off. */ 1553 ha->beacon_color_state = 0; 1554 *pflags = 0; 1555 } else { 1556 /* Turn on. */ 1557 ha->beacon_color_state = QLA_LED_ALL_ON; 1558 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 1559 } 1560 } 1561 1562 void 1563 qla24xx_beacon_blink(struct scsi_qla_host *vha) 1564 { 1565 uint16_t led_color = 0; 1566 uint32_t gpio_data; 1567 unsigned long flags; 1568 struct qla_hw_data *ha = vha->hw; 1569 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1570 1571 /* Save the Original GPIOD. */ 1572 spin_lock_irqsave(&ha->hardware_lock, flags); 1573 gpio_data = RD_REG_DWORD(®->gpiod); 1574 1575 /* Enable the gpio_data reg for update. */ 1576 gpio_data |= GPDX_LED_UPDATE_MASK; 1577 1578 WRT_REG_DWORD(®->gpiod, gpio_data); 1579 gpio_data = RD_REG_DWORD(®->gpiod); 1580 1581 /* Set the color bits. */ 1582 qla24xx_flip_colors(ha, &led_color); 1583 1584 /* Clear out any previously set LED color. */ 1585 gpio_data &= ~GPDX_LED_COLOR_MASK; 1586 1587 /* Set the new input LED color to GPIOD. */ 1588 gpio_data |= led_color; 1589 1590 /* Set the modified gpio_data values. */ 1591 WRT_REG_DWORD(®->gpiod, gpio_data); 1592 gpio_data = RD_REG_DWORD(®->gpiod); 1593 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1594 } 1595 1596 int 1597 qla24xx_beacon_on(struct scsi_qla_host *vha) 1598 { 1599 uint32_t gpio_data; 1600 unsigned long flags; 1601 struct qla_hw_data *ha = vha->hw; 1602 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1603 1604 if (IS_QLA82XX(ha)) 1605 return QLA_SUCCESS; 1606 1607 if (ha->beacon_blink_led == 0) { 1608 /* Enable firmware for update */ 1609 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1610 1611 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) 1612 return QLA_FUNCTION_FAILED; 1613 1614 if (qla2x00_get_fw_options(vha, ha->fw_options) != 1615 QLA_SUCCESS) { 1616 qla_printk(KERN_WARNING, ha, 1617 "Unable to update fw options (beacon on).\n"); 1618 return QLA_FUNCTION_FAILED; 1619 } 1620 1621 spin_lock_irqsave(&ha->hardware_lock, flags); 1622 gpio_data = RD_REG_DWORD(®->gpiod); 1623 1624 /* Enable the gpio_data reg for update. */ 1625 gpio_data |= GPDX_LED_UPDATE_MASK; 1626 WRT_REG_DWORD(®->gpiod, gpio_data); 1627 RD_REG_DWORD(®->gpiod); 1628 1629 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1630 } 1631 1632 /* So all colors blink together. */ 1633 ha->beacon_color_state = 0; 1634 1635 /* Let the per HBA timer kick off the blinking process. */ 1636 ha->beacon_blink_led = 1; 1637 1638 return QLA_SUCCESS; 1639 } 1640 1641 int 1642 qla24xx_beacon_off(struct scsi_qla_host *vha) 1643 { 1644 uint32_t gpio_data; 1645 unsigned long flags; 1646 struct qla_hw_data *ha = vha->hw; 1647 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1648 1649 if (IS_QLA82XX(ha)) 1650 return QLA_SUCCESS; 1651 1652 ha->beacon_blink_led = 0; 1653 ha->beacon_color_state = QLA_LED_ALL_ON; 1654 1655 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ 1656 1657 /* Give control back to firmware. */ 1658 spin_lock_irqsave(&ha->hardware_lock, flags); 1659 gpio_data = RD_REG_DWORD(®->gpiod); 1660 1661 /* Disable the gpio_data reg for update. */ 1662 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1663 WRT_REG_DWORD(®->gpiod, gpio_data); 1664 RD_REG_DWORD(®->gpiod); 1665 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1666 1667 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1668 1669 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1670 qla_printk(KERN_WARNING, ha, 1671 "Unable to update fw options (beacon off).\n"); 1672 return QLA_FUNCTION_FAILED; 1673 } 1674 1675 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1676 qla_printk(KERN_WARNING, ha, 1677 "Unable to get fw options (beacon off).\n"); 1678 return QLA_FUNCTION_FAILED; 1679 } 1680 1681 return QLA_SUCCESS; 1682 } 1683 1684 1685 /* 1686 * Flash support routines 1687 */ 1688 1689 /** 1690 * qla2x00_flash_enable() - Setup flash for reading and writing. 1691 * @ha: HA context 1692 */ 1693 static void 1694 qla2x00_flash_enable(struct qla_hw_data *ha) 1695 { 1696 uint16_t data; 1697 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1698 1699 data = RD_REG_WORD(®->ctrl_status); 1700 data |= CSR_FLASH_ENABLE; 1701 WRT_REG_WORD(®->ctrl_status, data); 1702 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1703 } 1704 1705 /** 1706 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1707 * @ha: HA context 1708 */ 1709 static void 1710 qla2x00_flash_disable(struct qla_hw_data *ha) 1711 { 1712 uint16_t data; 1713 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1714 1715 data = RD_REG_WORD(®->ctrl_status); 1716 data &= ~(CSR_FLASH_ENABLE); 1717 WRT_REG_WORD(®->ctrl_status, data); 1718 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1719 } 1720 1721 /** 1722 * qla2x00_read_flash_byte() - Reads a byte from flash 1723 * @ha: HA context 1724 * @addr: Address in flash to read 1725 * 1726 * A word is read from the chip, but, only the lower byte is valid. 1727 * 1728 * Returns the byte read from flash @addr. 1729 */ 1730 static uint8_t 1731 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) 1732 { 1733 uint16_t data; 1734 uint16_t bank_select; 1735 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1736 1737 bank_select = RD_REG_WORD(®->ctrl_status); 1738 1739 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1740 /* Specify 64K address range: */ 1741 /* clear out Module Select and Flash Address bits [19:16]. */ 1742 bank_select &= ~0xf8; 1743 bank_select |= addr >> 12 & 0xf0; 1744 bank_select |= CSR_FLASH_64K_BANK; 1745 WRT_REG_WORD(®->ctrl_status, bank_select); 1746 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1747 1748 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1749 data = RD_REG_WORD(®->flash_data); 1750 1751 return (uint8_t)data; 1752 } 1753 1754 /* Setup bit 16 of flash address. */ 1755 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 1756 bank_select |= CSR_FLASH_64K_BANK; 1757 WRT_REG_WORD(®->ctrl_status, bank_select); 1758 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1759 } else if (((addr & BIT_16) == 0) && 1760 (bank_select & CSR_FLASH_64K_BANK)) { 1761 bank_select &= ~(CSR_FLASH_64K_BANK); 1762 WRT_REG_WORD(®->ctrl_status, bank_select); 1763 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1764 } 1765 1766 /* Always perform IO mapped accesses to the FLASH registers. */ 1767 if (ha->pio_address) { 1768 uint16_t data2; 1769 1770 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 1771 do { 1772 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 1773 barrier(); 1774 cpu_relax(); 1775 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 1776 } while (data != data2); 1777 } else { 1778 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1779 data = qla2x00_debounce_register(®->flash_data); 1780 } 1781 1782 return (uint8_t)data; 1783 } 1784 1785 /** 1786 * qla2x00_write_flash_byte() - Write a byte to flash 1787 * @ha: HA context 1788 * @addr: Address in flash to write 1789 * @data: Data to write 1790 */ 1791 static void 1792 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) 1793 { 1794 uint16_t bank_select; 1795 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1796 1797 bank_select = RD_REG_WORD(®->ctrl_status); 1798 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1799 /* Specify 64K address range: */ 1800 /* clear out Module Select and Flash Address bits [19:16]. */ 1801 bank_select &= ~0xf8; 1802 bank_select |= addr >> 12 & 0xf0; 1803 bank_select |= CSR_FLASH_64K_BANK; 1804 WRT_REG_WORD(®->ctrl_status, bank_select); 1805 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1806 1807 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1808 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1809 WRT_REG_WORD(®->flash_data, (uint16_t)data); 1810 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1811 1812 return; 1813 } 1814 1815 /* Setup bit 16 of flash address. */ 1816 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 1817 bank_select |= CSR_FLASH_64K_BANK; 1818 WRT_REG_WORD(®->ctrl_status, bank_select); 1819 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1820 } else if (((addr & BIT_16) == 0) && 1821 (bank_select & CSR_FLASH_64K_BANK)) { 1822 bank_select &= ~(CSR_FLASH_64K_BANK); 1823 WRT_REG_WORD(®->ctrl_status, bank_select); 1824 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1825 } 1826 1827 /* Always perform IO mapped accesses to the FLASH registers. */ 1828 if (ha->pio_address) { 1829 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 1830 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); 1831 } else { 1832 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1833 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1834 WRT_REG_WORD(®->flash_data, (uint16_t)data); 1835 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1836 } 1837 } 1838 1839 /** 1840 * qla2x00_poll_flash() - Polls flash for completion. 1841 * @ha: HA context 1842 * @addr: Address in flash to poll 1843 * @poll_data: Data to be polled 1844 * @man_id: Flash manufacturer ID 1845 * @flash_id: Flash ID 1846 * 1847 * This function polls the device until bit 7 of what is read matches data 1848 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed 1849 * out (a fatal error). The flash book recommeds reading bit 7 again after 1850 * reading bit 5 as a 1. 1851 * 1852 * Returns 0 on success, else non-zero. 1853 */ 1854 static int 1855 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, 1856 uint8_t man_id, uint8_t flash_id) 1857 { 1858 int status; 1859 uint8_t flash_data; 1860 uint32_t cnt; 1861 1862 status = 1; 1863 1864 /* Wait for 30 seconds for command to finish. */ 1865 poll_data &= BIT_7; 1866 for (cnt = 3000000; cnt; cnt--) { 1867 flash_data = qla2x00_read_flash_byte(ha, addr); 1868 if ((flash_data & BIT_7) == poll_data) { 1869 status = 0; 1870 break; 1871 } 1872 1873 if (man_id != 0x40 && man_id != 0xda) { 1874 if ((flash_data & BIT_5) && cnt > 2) 1875 cnt = 2; 1876 } 1877 udelay(10); 1878 barrier(); 1879 cond_resched(); 1880 } 1881 return status; 1882 } 1883 1884 /** 1885 * qla2x00_program_flash_address() - Programs a flash address 1886 * @ha: HA context 1887 * @addr: Address in flash to program 1888 * @data: Data to be written in flash 1889 * @man_id: Flash manufacturer ID 1890 * @flash_id: Flash ID 1891 * 1892 * Returns 0 on success, else non-zero. 1893 */ 1894 static int 1895 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, 1896 uint8_t data, uint8_t man_id, uint8_t flash_id) 1897 { 1898 /* Write Program Command Sequence. */ 1899 if (IS_OEM_001(ha)) { 1900 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1901 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1902 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 1903 qla2x00_write_flash_byte(ha, addr, data); 1904 } else { 1905 if (man_id == 0xda && flash_id == 0xc1) { 1906 qla2x00_write_flash_byte(ha, addr, data); 1907 if (addr & 0x7e) 1908 return 0; 1909 } else { 1910 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1911 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1912 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 1913 qla2x00_write_flash_byte(ha, addr, data); 1914 } 1915 } 1916 1917 udelay(150); 1918 1919 /* Wait for write to complete. */ 1920 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 1921 } 1922 1923 /** 1924 * qla2x00_erase_flash() - Erase the flash. 1925 * @ha: HA context 1926 * @man_id: Flash manufacturer ID 1927 * @flash_id: Flash ID 1928 * 1929 * Returns 0 on success, else non-zero. 1930 */ 1931 static int 1932 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id) 1933 { 1934 /* Individual Sector Erase Command Sequence */ 1935 if (IS_OEM_001(ha)) { 1936 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1937 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1938 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 1939 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1940 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1941 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 1942 } else { 1943 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1944 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1945 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 1946 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1947 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1948 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 1949 } 1950 1951 udelay(150); 1952 1953 /* Wait for erase to complete. */ 1954 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 1955 } 1956 1957 /** 1958 * qla2x00_erase_flash_sector() - Erase a flash sector. 1959 * @ha: HA context 1960 * @addr: Flash sector to erase 1961 * @sec_mask: Sector address mask 1962 * @man_id: Flash manufacturer ID 1963 * @flash_id: Flash ID 1964 * 1965 * Returns 0 on success, else non-zero. 1966 */ 1967 static int 1968 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, 1969 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 1970 { 1971 /* Individual Sector Erase Command Sequence */ 1972 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1973 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1974 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 1975 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1976 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1977 if (man_id == 0x1f && flash_id == 0x13) 1978 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 1979 else 1980 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 1981 1982 udelay(150); 1983 1984 /* Wait for erase to complete. */ 1985 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 1986 } 1987 1988 /** 1989 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 1990 * @man_id: Flash manufacturer ID 1991 * @flash_id: Flash ID 1992 */ 1993 static void 1994 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 1995 uint8_t *flash_id) 1996 { 1997 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1998 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1999 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 2000 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 2001 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 2002 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2003 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2004 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 2005 } 2006 2007 static void 2008 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf, 2009 uint32_t saddr, uint32_t length) 2010 { 2011 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2012 uint32_t midpoint, ilength; 2013 uint8_t data; 2014 2015 midpoint = length / 2; 2016 2017 WRT_REG_WORD(®->nvram, 0); 2018 RD_REG_WORD(®->nvram); 2019 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 2020 if (ilength == midpoint) { 2021 WRT_REG_WORD(®->nvram, NVR_SELECT); 2022 RD_REG_WORD(®->nvram); 2023 } 2024 data = qla2x00_read_flash_byte(ha, saddr); 2025 if (saddr % 100) 2026 udelay(10); 2027 *tmp_buf = data; 2028 cond_resched(); 2029 } 2030 } 2031 2032 static inline void 2033 qla2x00_suspend_hba(struct scsi_qla_host *vha) 2034 { 2035 int cnt; 2036 unsigned long flags; 2037 struct qla_hw_data *ha = vha->hw; 2038 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2039 2040 /* Suspend HBA. */ 2041 scsi_block_requests(vha->host); 2042 ha->isp_ops->disable_intrs(ha); 2043 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2044 2045 /* Pause RISC. */ 2046 spin_lock_irqsave(&ha->hardware_lock, flags); 2047 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 2048 RD_REG_WORD(®->hccr); 2049 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2050 for (cnt = 0; cnt < 30000; cnt++) { 2051 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 2052 break; 2053 udelay(100); 2054 } 2055 } else { 2056 udelay(10); 2057 } 2058 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2059 } 2060 2061 static inline void 2062 qla2x00_resume_hba(struct scsi_qla_host *vha) 2063 { 2064 struct qla_hw_data *ha = vha->hw; 2065 2066 /* Resume HBA. */ 2067 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2068 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2069 qla2xxx_wake_dpc(vha); 2070 qla2x00_wait_for_chip_reset(vha); 2071 scsi_unblock_requests(vha->host); 2072 } 2073 2074 uint8_t * 2075 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2076 uint32_t offset, uint32_t length) 2077 { 2078 uint32_t addr, midpoint; 2079 uint8_t *data; 2080 struct qla_hw_data *ha = vha->hw; 2081 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2082 2083 /* Suspend HBA. */ 2084 qla2x00_suspend_hba(vha); 2085 2086 /* Go with read. */ 2087 midpoint = ha->optrom_size / 2; 2088 2089 qla2x00_flash_enable(ha); 2090 WRT_REG_WORD(®->nvram, 0); 2091 RD_REG_WORD(®->nvram); /* PCI Posting. */ 2092 for (addr = offset, data = buf; addr < length; addr++, data++) { 2093 if (addr == midpoint) { 2094 WRT_REG_WORD(®->nvram, NVR_SELECT); 2095 RD_REG_WORD(®->nvram); /* PCI Posting. */ 2096 } 2097 2098 *data = qla2x00_read_flash_byte(ha, addr); 2099 } 2100 qla2x00_flash_disable(ha); 2101 2102 /* Resume HBA. */ 2103 qla2x00_resume_hba(vha); 2104 2105 return buf; 2106 } 2107 2108 int 2109 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2110 uint32_t offset, uint32_t length) 2111 { 2112 2113 int rval; 2114 uint8_t man_id, flash_id, sec_number, data; 2115 uint16_t wd; 2116 uint32_t addr, liter, sec_mask, rest_addr; 2117 struct qla_hw_data *ha = vha->hw; 2118 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2119 2120 /* Suspend HBA. */ 2121 qla2x00_suspend_hba(vha); 2122 2123 rval = QLA_SUCCESS; 2124 sec_number = 0; 2125 2126 /* Reset ISP chip. */ 2127 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 2128 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2129 2130 /* Go with write. */ 2131 qla2x00_flash_enable(ha); 2132 do { /* Loop once to provide quick error exit */ 2133 /* Structure of flash memory based on manufacturer */ 2134 if (IS_OEM_001(ha)) { 2135 /* OEM variant with special flash part. */ 2136 man_id = flash_id = 0; 2137 rest_addr = 0xffff; 2138 sec_mask = 0x10000; 2139 goto update_flash; 2140 } 2141 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 2142 switch (man_id) { 2143 case 0x20: /* ST flash. */ 2144 if (flash_id == 0xd2 || flash_id == 0xe3) { 2145 /* 2146 * ST m29w008at part - 64kb sector size with 2147 * 32kb,8kb,8kb,16kb sectors at memory address 2148 * 0xf0000. 2149 */ 2150 rest_addr = 0xffff; 2151 sec_mask = 0x10000; 2152 break; 2153 } 2154 /* 2155 * ST m29w010b part - 16kb sector size 2156 * Default to 16kb sectors 2157 */ 2158 rest_addr = 0x3fff; 2159 sec_mask = 0x1c000; 2160 break; 2161 case 0x40: /* Mostel flash. */ 2162 /* Mostel v29c51001 part - 512 byte sector size. */ 2163 rest_addr = 0x1ff; 2164 sec_mask = 0x1fe00; 2165 break; 2166 case 0xbf: /* SST flash. */ 2167 /* SST39sf10 part - 4kb sector size. */ 2168 rest_addr = 0xfff; 2169 sec_mask = 0x1f000; 2170 break; 2171 case 0xda: /* Winbond flash. */ 2172 /* Winbond W29EE011 part - 256 byte sector size. */ 2173 rest_addr = 0x7f; 2174 sec_mask = 0x1ff80; 2175 break; 2176 case 0xc2: /* Macronix flash. */ 2177 /* 64k sector size. */ 2178 if (flash_id == 0x38 || flash_id == 0x4f) { 2179 rest_addr = 0xffff; 2180 sec_mask = 0x10000; 2181 break; 2182 } 2183 /* Fall through... */ 2184 2185 case 0x1f: /* Atmel flash. */ 2186 /* 512k sector size. */ 2187 if (flash_id == 0x13) { 2188 rest_addr = 0x7fffffff; 2189 sec_mask = 0x80000000; 2190 break; 2191 } 2192 /* Fall through... */ 2193 2194 case 0x01: /* AMD flash. */ 2195 if (flash_id == 0x38 || flash_id == 0x40 || 2196 flash_id == 0x4f) { 2197 /* Am29LV081 part - 64kb sector size. */ 2198 /* Am29LV002BT part - 64kb sector size. */ 2199 rest_addr = 0xffff; 2200 sec_mask = 0x10000; 2201 break; 2202 } else if (flash_id == 0x3e) { 2203 /* 2204 * Am29LV008b part - 64kb sector size with 2205 * 32kb,8kb,8kb,16kb sector at memory address 2206 * h0xf0000. 2207 */ 2208 rest_addr = 0xffff; 2209 sec_mask = 0x10000; 2210 break; 2211 } else if (flash_id == 0x20 || flash_id == 0x6e) { 2212 /* 2213 * Am29LV010 part or AM29f010 - 16kb sector 2214 * size. 2215 */ 2216 rest_addr = 0x3fff; 2217 sec_mask = 0x1c000; 2218 break; 2219 } else if (flash_id == 0x6d) { 2220 /* Am29LV001 part - 8kb sector size. */ 2221 rest_addr = 0x1fff; 2222 sec_mask = 0x1e000; 2223 break; 2224 } 2225 default: 2226 /* Default to 16 kb sector size. */ 2227 rest_addr = 0x3fff; 2228 sec_mask = 0x1c000; 2229 break; 2230 } 2231 2232 update_flash: 2233 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2234 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 2235 rval = QLA_FUNCTION_FAILED; 2236 break; 2237 } 2238 } 2239 2240 for (addr = offset, liter = 0; liter < length; liter++, 2241 addr++) { 2242 data = buf[liter]; 2243 /* Are we at the beginning of a sector? */ 2244 if ((addr & rest_addr) == 0) { 2245 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2246 if (addr >= 0x10000UL) { 2247 if (((addr >> 12) & 0xf0) && 2248 ((man_id == 0x01 && 2249 flash_id == 0x3e) || 2250 (man_id == 0x20 && 2251 flash_id == 0xd2))) { 2252 sec_number++; 2253 if (sec_number == 1) { 2254 rest_addr = 2255 0x7fff; 2256 sec_mask = 2257 0x18000; 2258 } else if ( 2259 sec_number == 2 || 2260 sec_number == 3) { 2261 rest_addr = 2262 0x1fff; 2263 sec_mask = 2264 0x1e000; 2265 } else if ( 2266 sec_number == 4) { 2267 rest_addr = 2268 0x3fff; 2269 sec_mask = 2270 0x1c000; 2271 } 2272 } 2273 } 2274 } else if (addr == ha->optrom_size / 2) { 2275 WRT_REG_WORD(®->nvram, NVR_SELECT); 2276 RD_REG_WORD(®->nvram); 2277 } 2278 2279 if (flash_id == 0xda && man_id == 0xc1) { 2280 qla2x00_write_flash_byte(ha, 0x5555, 2281 0xaa); 2282 qla2x00_write_flash_byte(ha, 0x2aaa, 2283 0x55); 2284 qla2x00_write_flash_byte(ha, 0x5555, 2285 0xa0); 2286 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 2287 /* Then erase it */ 2288 if (qla2x00_erase_flash_sector(ha, 2289 addr, sec_mask, man_id, 2290 flash_id)) { 2291 rval = QLA_FUNCTION_FAILED; 2292 break; 2293 } 2294 if (man_id == 0x01 && flash_id == 0x6d) 2295 sec_number++; 2296 } 2297 } 2298 2299 if (man_id == 0x01 && flash_id == 0x6d) { 2300 if (sec_number == 1 && 2301 addr == (rest_addr - 1)) { 2302 rest_addr = 0x0fff; 2303 sec_mask = 0x1f000; 2304 } else if (sec_number == 3 && (addr & 0x7ffe)) { 2305 rest_addr = 0x3fff; 2306 sec_mask = 0x1c000; 2307 } 2308 } 2309 2310 if (qla2x00_program_flash_address(ha, addr, data, 2311 man_id, flash_id)) { 2312 rval = QLA_FUNCTION_FAILED; 2313 break; 2314 } 2315 cond_resched(); 2316 } 2317 } while (0); 2318 qla2x00_flash_disable(ha); 2319 2320 /* Resume HBA. */ 2321 qla2x00_resume_hba(vha); 2322 2323 return rval; 2324 } 2325 2326 uint8_t * 2327 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2328 uint32_t offset, uint32_t length) 2329 { 2330 struct qla_hw_data *ha = vha->hw; 2331 2332 /* Suspend HBA. */ 2333 scsi_block_requests(vha->host); 2334 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2335 2336 /* Go with read. */ 2337 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2); 2338 2339 /* Resume HBA. */ 2340 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2341 scsi_unblock_requests(vha->host); 2342 2343 return buf; 2344 } 2345 2346 int 2347 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2348 uint32_t offset, uint32_t length) 2349 { 2350 int rval; 2351 struct qla_hw_data *ha = vha->hw; 2352 2353 /* Suspend HBA. */ 2354 scsi_block_requests(vha->host); 2355 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2356 2357 /* Go with write. */ 2358 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2, 2359 length >> 2); 2360 2361 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2362 scsi_unblock_requests(vha->host); 2363 2364 return rval; 2365 } 2366 2367 uint8_t * 2368 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2369 uint32_t offset, uint32_t length) 2370 { 2371 int rval; 2372 dma_addr_t optrom_dma; 2373 void *optrom; 2374 uint8_t *pbuf; 2375 uint32_t faddr, left, burst; 2376 struct qla_hw_data *ha = vha->hw; 2377 2378 if (IS_QLA25XX(ha) || IS_QLA81XX(ha)) 2379 goto try_fast; 2380 if (offset & 0xfff) 2381 goto slow_read; 2382 if (length < OPTROM_BURST_SIZE) 2383 goto slow_read; 2384 2385 try_fast: 2386 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2387 &optrom_dma, GFP_KERNEL); 2388 if (!optrom) { 2389 qla_printk(KERN_DEBUG, ha, 2390 "Unable to allocate memory for optrom burst read " 2391 "(%x KB).\n", OPTROM_BURST_SIZE / 1024); 2392 2393 goto slow_read; 2394 } 2395 2396 pbuf = buf; 2397 faddr = offset >> 2; 2398 left = length >> 2; 2399 burst = OPTROM_BURST_DWORDS; 2400 while (left != 0) { 2401 if (burst > left) 2402 burst = left; 2403 2404 rval = qla2x00_dump_ram(vha, optrom_dma, 2405 flash_data_addr(ha, faddr), burst); 2406 if (rval) { 2407 qla_printk(KERN_WARNING, ha, 2408 "Unable to burst-read optrom segment " 2409 "(%x/%x/%llx).\n", rval, 2410 flash_data_addr(ha, faddr), 2411 (unsigned long long)optrom_dma); 2412 qla_printk(KERN_WARNING, ha, 2413 "Reverting to slow-read.\n"); 2414 2415 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2416 optrom, optrom_dma); 2417 goto slow_read; 2418 } 2419 2420 memcpy(pbuf, optrom, burst * 4); 2421 2422 left -= burst; 2423 faddr += burst; 2424 pbuf += burst * 4; 2425 } 2426 2427 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, 2428 optrom_dma); 2429 2430 return buf; 2431 2432 slow_read: 2433 return qla24xx_read_optrom_data(vha, buf, offset, length); 2434 } 2435 2436 /** 2437 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 2438 * @ha: HA context 2439 * @pcids: Pointer to the FCODE PCI data structure 2440 * 2441 * The process of retrieving the FCODE version information is at best 2442 * described as interesting. 2443 * 2444 * Within the first 100h bytes of the image an ASCII string is present 2445 * which contains several pieces of information including the FCODE 2446 * version. Unfortunately it seems the only reliable way to retrieve 2447 * the version is by scanning for another sentinel within the string, 2448 * the FCODE build date: 2449 * 2450 * ... 2.00.02 10/17/02 ... 2451 * 2452 * Returns QLA_SUCCESS on successful retrieval of version. 2453 */ 2454 static void 2455 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) 2456 { 2457 int ret = QLA_FUNCTION_FAILED; 2458 uint32_t istart, iend, iter, vend; 2459 uint8_t do_next, rbyte, *vbyte; 2460 2461 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2462 2463 /* Skip the PCI data structure. */ 2464 istart = pcids + 2465 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 2466 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 2467 iend = istart + 0x100; 2468 do { 2469 /* Scan for the sentinel date string...eeewww. */ 2470 do_next = 0; 2471 iter = istart; 2472 while ((iter < iend) && !do_next) { 2473 iter++; 2474 if (qla2x00_read_flash_byte(ha, iter) == '/') { 2475 if (qla2x00_read_flash_byte(ha, iter + 2) == 2476 '/') 2477 do_next++; 2478 else if (qla2x00_read_flash_byte(ha, 2479 iter + 3) == '/') 2480 do_next++; 2481 } 2482 } 2483 if (!do_next) 2484 break; 2485 2486 /* Backtrack to previous ' ' (space). */ 2487 do_next = 0; 2488 while ((iter > istart) && !do_next) { 2489 iter--; 2490 if (qla2x00_read_flash_byte(ha, iter) == ' ') 2491 do_next++; 2492 } 2493 if (!do_next) 2494 break; 2495 2496 /* 2497 * Mark end of version tag, and find previous ' ' (space) or 2498 * string length (recent FCODE images -- major hack ahead!!!). 2499 */ 2500 vend = iter - 1; 2501 do_next = 0; 2502 while ((iter > istart) && !do_next) { 2503 iter--; 2504 rbyte = qla2x00_read_flash_byte(ha, iter); 2505 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 2506 do_next++; 2507 } 2508 if (!do_next) 2509 break; 2510 2511 /* Mark beginning of version tag, and copy data. */ 2512 iter++; 2513 if ((vend - iter) && 2514 ((vend - iter) < sizeof(ha->fcode_revision))) { 2515 vbyte = ha->fcode_revision; 2516 while (iter <= vend) { 2517 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 2518 iter++; 2519 } 2520 ret = QLA_SUCCESS; 2521 } 2522 } while (0); 2523 2524 if (ret != QLA_SUCCESS) 2525 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2526 } 2527 2528 int 2529 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 2530 { 2531 int ret = QLA_SUCCESS; 2532 uint8_t code_type, last_image; 2533 uint32_t pcihdr, pcids; 2534 uint8_t *dbyte; 2535 uint16_t *dcode; 2536 struct qla_hw_data *ha = vha->hw; 2537 2538 if (!ha->pio_address || !mbuf) 2539 return QLA_FUNCTION_FAILED; 2540 2541 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 2542 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 2543 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2544 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2545 2546 qla2x00_flash_enable(ha); 2547 2548 /* Begin with first PCI expansion ROM header. */ 2549 pcihdr = 0; 2550 last_image = 1; 2551 do { 2552 /* Verify PCI expansion ROM header. */ 2553 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 2554 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 2555 /* No signature */ 2556 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM " 2557 "signature.\n")); 2558 ret = QLA_FUNCTION_FAILED; 2559 break; 2560 } 2561 2562 /* Locate PCI data structure. */ 2563 pcids = pcihdr + 2564 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 2565 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 2566 2567 /* Validate signature of PCI data structure. */ 2568 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 2569 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 2570 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 2571 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 2572 /* Incorrect header. */ 2573 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not " 2574 "found pcir_adr=%x.\n", pcids)); 2575 ret = QLA_FUNCTION_FAILED; 2576 break; 2577 } 2578 2579 /* Read version */ 2580 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 2581 switch (code_type) { 2582 case ROM_CODE_TYPE_BIOS: 2583 /* Intel x86, PC-AT compatible. */ 2584 ha->bios_revision[0] = 2585 qla2x00_read_flash_byte(ha, pcids + 0x12); 2586 ha->bios_revision[1] = 2587 qla2x00_read_flash_byte(ha, pcids + 0x13); 2588 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n", 2589 ha->bios_revision[1], ha->bios_revision[0])); 2590 break; 2591 case ROM_CODE_TYPE_FCODE: 2592 /* Open Firmware standard for PCI (FCode). */ 2593 /* Eeeewww... */ 2594 qla2x00_get_fcode_version(ha, pcids); 2595 break; 2596 case ROM_CODE_TYPE_EFI: 2597 /* Extensible Firmware Interface (EFI). */ 2598 ha->efi_revision[0] = 2599 qla2x00_read_flash_byte(ha, pcids + 0x12); 2600 ha->efi_revision[1] = 2601 qla2x00_read_flash_byte(ha, pcids + 0x13); 2602 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n", 2603 ha->efi_revision[1], ha->efi_revision[0])); 2604 break; 2605 default: 2606 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code " 2607 "type %x at pcids %x.\n", code_type, pcids)); 2608 break; 2609 } 2610 2611 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 2612 2613 /* Locate next PCI expansion ROM. */ 2614 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 2615 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 2616 } while (!last_image); 2617 2618 if (IS_QLA2322(ha)) { 2619 /* Read firmware image information. */ 2620 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2621 dbyte = mbuf; 2622 memset(dbyte, 0, 8); 2623 dcode = (uint16_t *)dbyte; 2624 2625 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, 2626 8); 2627 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from " 2628 "flash:\n")); 2629 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8)); 2630 2631 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 2632 dcode[2] == 0xffff && dcode[3] == 0xffff) || 2633 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 2634 dcode[3] == 0)) { 2635 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw " 2636 "revision at %x.\n", ha->flt_region_fw * 4)); 2637 } else { 2638 /* values are in big endian */ 2639 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 2640 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 2641 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 2642 } 2643 } 2644 2645 qla2x00_flash_disable(ha); 2646 2647 return ret; 2648 } 2649 2650 int 2651 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 2652 { 2653 int ret = QLA_SUCCESS; 2654 uint32_t pcihdr, pcids; 2655 uint32_t *dcode; 2656 uint8_t *bcode; 2657 uint8_t code_type, last_image; 2658 int i; 2659 struct qla_hw_data *ha = vha->hw; 2660 2661 if (IS_QLA82XX(ha)) 2662 return ret; 2663 2664 if (!mbuf) 2665 return QLA_FUNCTION_FAILED; 2666 2667 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 2668 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 2669 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2670 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2671 2672 dcode = mbuf; 2673 2674 /* Begin with first PCI expansion ROM header. */ 2675 pcihdr = ha->flt_region_boot << 2; 2676 last_image = 1; 2677 do { 2678 /* Verify PCI expansion ROM header. */ 2679 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 2680 bcode = mbuf + (pcihdr % 4); 2681 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) { 2682 /* No signature */ 2683 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM " 2684 "signature.\n")); 2685 ret = QLA_FUNCTION_FAILED; 2686 break; 2687 } 2688 2689 /* Locate PCI data structure. */ 2690 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 2691 2692 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 2693 bcode = mbuf + (pcihdr % 4); 2694 2695 /* Validate signature of PCI data structure. */ 2696 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 2697 bcode[0x2] != 'I' || bcode[0x3] != 'R') { 2698 /* Incorrect header. */ 2699 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not " 2700 "found pcir_adr=%x.\n", pcids)); 2701 ret = QLA_FUNCTION_FAILED; 2702 break; 2703 } 2704 2705 /* Read version */ 2706 code_type = bcode[0x14]; 2707 switch (code_type) { 2708 case ROM_CODE_TYPE_BIOS: 2709 /* Intel x86, PC-AT compatible. */ 2710 ha->bios_revision[0] = bcode[0x12]; 2711 ha->bios_revision[1] = bcode[0x13]; 2712 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n", 2713 ha->bios_revision[1], ha->bios_revision[0])); 2714 break; 2715 case ROM_CODE_TYPE_FCODE: 2716 /* Open Firmware standard for PCI (FCode). */ 2717 ha->fcode_revision[0] = bcode[0x12]; 2718 ha->fcode_revision[1] = bcode[0x13]; 2719 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n", 2720 ha->fcode_revision[1], ha->fcode_revision[0])); 2721 break; 2722 case ROM_CODE_TYPE_EFI: 2723 /* Extensible Firmware Interface (EFI). */ 2724 ha->efi_revision[0] = bcode[0x12]; 2725 ha->efi_revision[1] = bcode[0x13]; 2726 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n", 2727 ha->efi_revision[1], ha->efi_revision[0])); 2728 break; 2729 default: 2730 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code " 2731 "type %x at pcids %x.\n", code_type, pcids)); 2732 break; 2733 } 2734 2735 last_image = bcode[0x15] & BIT_7; 2736 2737 /* Locate next PCI expansion ROM. */ 2738 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 2739 } while (!last_image); 2740 2741 /* Read firmware image information. */ 2742 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2743 dcode = mbuf; 2744 2745 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4); 2746 for (i = 0; i < 4; i++) 2747 dcode[i] = be32_to_cpu(dcode[i]); 2748 2749 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 2750 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 2751 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 2752 dcode[3] == 0)) { 2753 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw " 2754 "revision at %x.\n", ha->flt_region_fw * 4)); 2755 } else { 2756 ha->fw_revision[0] = dcode[0]; 2757 ha->fw_revision[1] = dcode[1]; 2758 ha->fw_revision[2] = dcode[2]; 2759 ha->fw_revision[3] = dcode[3]; 2760 } 2761 2762 /* Check for golden firmware and get version if available */ 2763 if (!IS_QLA81XX(ha)) { 2764 /* Golden firmware is not present in non 81XX adapters */ 2765 return ret; 2766 } 2767 2768 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); 2769 dcode = mbuf; 2770 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, 2771 ha->flt_region_gold_fw << 2, 32); 2772 2773 if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF && 2774 dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) { 2775 DEBUG2(qla_printk(KERN_INFO, ha, 2776 "%s(%ld): Unrecognized golden fw at 0x%x.\n", 2777 __func__, vha->host_no, ha->flt_region_gold_fw * 4)); 2778 return ret; 2779 } 2780 2781 for (i = 4; i < 8; i++) 2782 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]); 2783 2784 return ret; 2785 } 2786 2787 static int 2788 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) 2789 { 2790 if (pos >= end || *pos != 0x82) 2791 return 0; 2792 2793 pos += 3 + pos[1]; 2794 if (pos >= end || *pos != 0x90) 2795 return 0; 2796 2797 pos += 3 + pos[1]; 2798 if (pos >= end || *pos != 0x78) 2799 return 0; 2800 2801 return 1; 2802 } 2803 2804 int 2805 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) 2806 { 2807 struct qla_hw_data *ha = vha->hw; 2808 uint8_t *pos = ha->vpd; 2809 uint8_t *end = pos + ha->vpd_size; 2810 int len = 0; 2811 2812 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) 2813 return 0; 2814 2815 while (pos < end && *pos != 0x78) { 2816 len = (*pos == 0x82) ? pos[1] : pos[2]; 2817 2818 if (!strncmp(pos, key, strlen(key))) 2819 break; 2820 2821 if (*pos != 0x90 && *pos != 0x91) 2822 pos += len; 2823 2824 pos += 3; 2825 } 2826 2827 if (pos < end - len && *pos != 0x78) 2828 return snprintf(str, size, "%.*s", len, pos + 3); 2829 2830 return 0; 2831 } 2832 2833 int 2834 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha) 2835 { 2836 int len, max_len; 2837 uint32_t fcp_prio_addr; 2838 struct qla_hw_data *ha = vha->hw; 2839 2840 if (!ha->fcp_prio_cfg) { 2841 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); 2842 if (!ha->fcp_prio_cfg) { 2843 qla_printk(KERN_WARNING, ha, 2844 "Unable to allocate memory for fcp priority data " 2845 "(%x).\n", FCP_PRIO_CFG_SIZE); 2846 return QLA_FUNCTION_FAILED; 2847 } 2848 } 2849 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); 2850 2851 fcp_prio_addr = ha->flt_region_fcp_prio; 2852 2853 /* first read the fcp priority data header from flash */ 2854 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg, 2855 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE); 2856 2857 if (!qla24xx_fcp_prio_cfg_valid(ha->fcp_prio_cfg, 0)) 2858 goto fail; 2859 2860 /* read remaining FCP CMD config data from flash */ 2861 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2); 2862 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE; 2863 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; 2864 2865 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0], 2866 fcp_prio_addr << 2, (len < max_len ? len : max_len)); 2867 2868 /* revalidate the entire FCP priority config data, including entries */ 2869 if (!qla24xx_fcp_prio_cfg_valid(ha->fcp_prio_cfg, 1)) 2870 goto fail; 2871 2872 ha->flags.fcp_prio_enabled = 1; 2873 return QLA_SUCCESS; 2874 fail: 2875 vfree(ha->fcp_prio_cfg); 2876 ha->fcp_prio_cfg = NULL; 2877 return QLA_FUNCTION_FAILED; 2878 } 2879