1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 #include <linux/uaccess.h> 13 14 /* 15 * NVRAM support routines 16 */ 17 18 /** 19 * qla2x00_lock_nvram_access() - 20 * @ha: HA context 21 */ 22 static void 23 qla2x00_lock_nvram_access(struct qla_hw_data *ha) 24 { 25 uint16_t data; 26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 27 28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 29 data = RD_REG_WORD(®->nvram); 30 while (data & NVR_BUSY) { 31 udelay(100); 32 data = RD_REG_WORD(®->nvram); 33 } 34 35 /* Lock resource */ 36 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 37 RD_REG_WORD(®->u.isp2300.host_semaphore); 38 udelay(5); 39 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 40 while ((data & BIT_0) == 0) { 41 /* Lock failed */ 42 udelay(100); 43 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 44 RD_REG_WORD(®->u.isp2300.host_semaphore); 45 udelay(5); 46 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 47 } 48 } 49 } 50 51 /** 52 * qla2x00_unlock_nvram_access() - 53 * @ha: HA context 54 */ 55 static void 56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha) 57 { 58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 59 60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 61 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); 62 RD_REG_WORD(®->u.isp2300.host_semaphore); 63 } 64 } 65 66 /** 67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 68 * @ha: HA context 69 * @data: Serial interface selector 70 */ 71 static void 72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data) 73 { 74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 75 76 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 77 RD_REG_WORD(®->nvram); /* PCI Posting. */ 78 NVRAM_DELAY(); 79 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK | 80 NVR_WRT_ENABLE); 81 RD_REG_WORD(®->nvram); /* PCI Posting. */ 82 NVRAM_DELAY(); 83 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 84 RD_REG_WORD(®->nvram); /* PCI Posting. */ 85 NVRAM_DELAY(); 86 } 87 88 /** 89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 90 * NVRAM. 91 * @ha: HA context 92 * @nv_cmd: NVRAM command 93 * 94 * Bit definitions for NVRAM command: 95 * 96 * Bit 26 = start bit 97 * Bit 25, 24 = opcode 98 * Bit 23-16 = address 99 * Bit 15-0 = write data 100 * 101 * Returns the word read from nvram @addr. 102 */ 103 static uint16_t 104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) 105 { 106 uint8_t cnt; 107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 108 uint16_t data = 0; 109 uint16_t reg_data; 110 111 /* Send command to NVRAM. */ 112 nv_cmd <<= 5; 113 for (cnt = 0; cnt < 11; cnt++) { 114 if (nv_cmd & BIT_31) 115 qla2x00_nv_write(ha, NVR_DATA_OUT); 116 else 117 qla2x00_nv_write(ha, 0); 118 nv_cmd <<= 1; 119 } 120 121 /* Read data from NVRAM. */ 122 for (cnt = 0; cnt < 16; cnt++) { 123 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); 124 RD_REG_WORD(®->nvram); /* PCI Posting. */ 125 NVRAM_DELAY(); 126 data <<= 1; 127 reg_data = RD_REG_WORD(®->nvram); 128 if (reg_data & NVR_DATA_IN) 129 data |= BIT_0; 130 WRT_REG_WORD(®->nvram, NVR_SELECT); 131 RD_REG_WORD(®->nvram); /* PCI Posting. */ 132 NVRAM_DELAY(); 133 } 134 135 /* Deselect chip. */ 136 WRT_REG_WORD(®->nvram, NVR_DESELECT); 137 RD_REG_WORD(®->nvram); /* PCI Posting. */ 138 NVRAM_DELAY(); 139 140 return data; 141 } 142 143 144 /** 145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 146 * request routine to get the word from NVRAM. 147 * @ha: HA context 148 * @addr: Address in NVRAM to read 149 * 150 * Returns the word read from nvram @addr. 151 */ 152 static uint16_t 153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) 154 { 155 uint16_t data; 156 uint32_t nv_cmd; 157 158 nv_cmd = addr << 16; 159 nv_cmd |= NV_READ_OP; 160 data = qla2x00_nvram_request(ha, nv_cmd); 161 162 return (data); 163 } 164 165 /** 166 * qla2x00_nv_deselect() - Deselect NVRAM operations. 167 * @ha: HA context 168 */ 169 static void 170 qla2x00_nv_deselect(struct qla_hw_data *ha) 171 { 172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 173 174 WRT_REG_WORD(®->nvram, NVR_DESELECT); 175 RD_REG_WORD(®->nvram); /* PCI Posting. */ 176 NVRAM_DELAY(); 177 } 178 179 /** 180 * qla2x00_write_nvram_word() - Write NVRAM data. 181 * @ha: HA context 182 * @addr: Address in NVRAM to write 183 * @data: word to program 184 */ 185 static void 186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data) 187 { 188 int count; 189 uint16_t word; 190 uint32_t nv_cmd, wait_cnt; 191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 192 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 193 194 qla2x00_nv_write(ha, NVR_DATA_OUT); 195 qla2x00_nv_write(ha, 0); 196 qla2x00_nv_write(ha, 0); 197 198 for (word = 0; word < 8; word++) 199 qla2x00_nv_write(ha, NVR_DATA_OUT); 200 201 qla2x00_nv_deselect(ha); 202 203 /* Write data */ 204 nv_cmd = (addr << 16) | NV_WRITE_OP; 205 nv_cmd |= data; 206 nv_cmd <<= 5; 207 for (count = 0; count < 27; count++) { 208 if (nv_cmd & BIT_31) 209 qla2x00_nv_write(ha, NVR_DATA_OUT); 210 else 211 qla2x00_nv_write(ha, 0); 212 213 nv_cmd <<= 1; 214 } 215 216 qla2x00_nv_deselect(ha); 217 218 /* Wait for NVRAM to become ready */ 219 WRT_REG_WORD(®->nvram, NVR_SELECT); 220 RD_REG_WORD(®->nvram); /* PCI Posting. */ 221 wait_cnt = NVR_WAIT_CNT; 222 do { 223 if (!--wait_cnt) { 224 ql_dbg(ql_dbg_user, vha, 0x708d, 225 "NVRAM didn't go ready...\n"); 226 break; 227 } 228 NVRAM_DELAY(); 229 word = RD_REG_WORD(®->nvram); 230 } while ((word & NVR_DATA_IN) == 0); 231 232 qla2x00_nv_deselect(ha); 233 234 /* Disable writes */ 235 qla2x00_nv_write(ha, NVR_DATA_OUT); 236 for (count = 0; count < 10; count++) 237 qla2x00_nv_write(ha, 0); 238 239 qla2x00_nv_deselect(ha); 240 } 241 242 static int 243 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, 244 uint16_t data, uint32_t tmo) 245 { 246 int ret, count; 247 uint16_t word; 248 uint32_t nv_cmd; 249 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 250 251 ret = QLA_SUCCESS; 252 253 qla2x00_nv_write(ha, NVR_DATA_OUT); 254 qla2x00_nv_write(ha, 0); 255 qla2x00_nv_write(ha, 0); 256 257 for (word = 0; word < 8; word++) 258 qla2x00_nv_write(ha, NVR_DATA_OUT); 259 260 qla2x00_nv_deselect(ha); 261 262 /* Write data */ 263 nv_cmd = (addr << 16) | NV_WRITE_OP; 264 nv_cmd |= data; 265 nv_cmd <<= 5; 266 for (count = 0; count < 27; count++) { 267 if (nv_cmd & BIT_31) 268 qla2x00_nv_write(ha, NVR_DATA_OUT); 269 else 270 qla2x00_nv_write(ha, 0); 271 272 nv_cmd <<= 1; 273 } 274 275 qla2x00_nv_deselect(ha); 276 277 /* Wait for NVRAM to become ready */ 278 WRT_REG_WORD(®->nvram, NVR_SELECT); 279 RD_REG_WORD(®->nvram); /* PCI Posting. */ 280 do { 281 NVRAM_DELAY(); 282 word = RD_REG_WORD(®->nvram); 283 if (!--tmo) { 284 ret = QLA_FUNCTION_FAILED; 285 break; 286 } 287 } while ((word & NVR_DATA_IN) == 0); 288 289 qla2x00_nv_deselect(ha); 290 291 /* Disable writes */ 292 qla2x00_nv_write(ha, NVR_DATA_OUT); 293 for (count = 0; count < 10; count++) 294 qla2x00_nv_write(ha, 0); 295 296 qla2x00_nv_deselect(ha); 297 298 return ret; 299 } 300 301 /** 302 * qla2x00_clear_nvram_protection() - 303 * @ha: HA context 304 */ 305 static int 306 qla2x00_clear_nvram_protection(struct qla_hw_data *ha) 307 { 308 int ret, stat; 309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 310 uint32_t word, wait_cnt; 311 uint16_t wprot, wprot_old; 312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 313 314 /* Clear NVRAM write protection. */ 315 ret = QLA_FUNCTION_FAILED; 316 317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 319 cpu_to_le16(0x1234), 100000); 320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 321 if (stat != QLA_SUCCESS || wprot != 0x1234) { 322 /* Write enable. */ 323 qla2x00_nv_write(ha, NVR_DATA_OUT); 324 qla2x00_nv_write(ha, 0); 325 qla2x00_nv_write(ha, 0); 326 for (word = 0; word < 8; word++) 327 qla2x00_nv_write(ha, NVR_DATA_OUT); 328 329 qla2x00_nv_deselect(ha); 330 331 /* Enable protection register. */ 332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 333 qla2x00_nv_write(ha, NVR_PR_ENABLE); 334 qla2x00_nv_write(ha, NVR_PR_ENABLE); 335 for (word = 0; word < 8; word++) 336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 337 338 qla2x00_nv_deselect(ha); 339 340 /* Clear protection register (ffff is cleared). */ 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 344 for (word = 0; word < 8; word++) 345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 346 347 qla2x00_nv_deselect(ha); 348 349 /* Wait for NVRAM to become ready. */ 350 WRT_REG_WORD(®->nvram, NVR_SELECT); 351 RD_REG_WORD(®->nvram); /* PCI Posting. */ 352 wait_cnt = NVR_WAIT_CNT; 353 do { 354 if (!--wait_cnt) { 355 ql_dbg(ql_dbg_user, vha, 0x708e, 356 "NVRAM didn't go ready...\n"); 357 break; 358 } 359 NVRAM_DELAY(); 360 word = RD_REG_WORD(®->nvram); 361 } while ((word & NVR_DATA_IN) == 0); 362 363 if (wait_cnt) 364 ret = QLA_SUCCESS; 365 } else 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 367 368 return ret; 369 } 370 371 static void 372 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) 373 { 374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 375 uint32_t word, wait_cnt; 376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 377 378 if (stat != QLA_SUCCESS) 379 return; 380 381 /* Set NVRAM write protection. */ 382 /* Write enable. */ 383 qla2x00_nv_write(ha, NVR_DATA_OUT); 384 qla2x00_nv_write(ha, 0); 385 qla2x00_nv_write(ha, 0); 386 for (word = 0; word < 8; word++) 387 qla2x00_nv_write(ha, NVR_DATA_OUT); 388 389 qla2x00_nv_deselect(ha); 390 391 /* Enable protection register. */ 392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 393 qla2x00_nv_write(ha, NVR_PR_ENABLE); 394 qla2x00_nv_write(ha, NVR_PR_ENABLE); 395 for (word = 0; word < 8; word++) 396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 397 398 qla2x00_nv_deselect(ha); 399 400 /* Enable protection register. */ 401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 402 qla2x00_nv_write(ha, NVR_PR_ENABLE); 403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 404 for (word = 0; word < 8; word++) 405 qla2x00_nv_write(ha, NVR_PR_ENABLE); 406 407 qla2x00_nv_deselect(ha); 408 409 /* Wait for NVRAM to become ready. */ 410 WRT_REG_WORD(®->nvram, NVR_SELECT); 411 RD_REG_WORD(®->nvram); /* PCI Posting. */ 412 wait_cnt = NVR_WAIT_CNT; 413 do { 414 if (!--wait_cnt) { 415 ql_dbg(ql_dbg_user, vha, 0x708f, 416 "NVRAM didn't go ready...\n"); 417 break; 418 } 419 NVRAM_DELAY(); 420 word = RD_REG_WORD(®->nvram); 421 } while ((word & NVR_DATA_IN) == 0); 422 } 423 424 425 /*****************************************************************************/ 426 /* Flash Manipulation Routines */ 427 /*****************************************************************************/ 428 429 static inline uint32_t 430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) 431 { 432 return ha->flash_conf_off + faddr; 433 } 434 435 static inline uint32_t 436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) 437 { 438 return ha->flash_data_off + faddr; 439 } 440 441 static inline uint32_t 442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) 443 { 444 return ha->nvram_conf_off + naddr; 445 } 446 447 static inline uint32_t 448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) 449 { 450 return ha->nvram_data_off + naddr; 451 } 452 453 static int 454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t *data) 455 { 456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 457 ulong cnt = 30000; 458 459 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); 460 461 while (cnt--) { 462 if (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) { 463 *data = RD_REG_DWORD(®->flash_data); 464 return QLA_SUCCESS; 465 } 466 udelay(10); 467 cond_resched(); 468 } 469 470 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 471 "Flash read dword at %x timeout.\n", addr); 472 *data = 0xDEADDEAD; 473 return QLA_FUNCTION_TIMEOUT; 474 } 475 476 int 477 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 478 uint32_t dwords) 479 { 480 ulong i; 481 int ret = QLA_SUCCESS; 482 struct qla_hw_data *ha = vha->hw; 483 484 /* Dword reads to flash. */ 485 faddr = flash_data_addr(ha, faddr); 486 for (i = 0; i < dwords; i++, faddr++, dwptr++) { 487 ret = qla24xx_read_flash_dword(ha, faddr, dwptr); 488 if (ret != QLA_SUCCESS) 489 break; 490 cpu_to_le32s(dwptr); 491 } 492 493 return ret; 494 } 495 496 static int 497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) 498 { 499 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 500 ulong cnt = 500000; 501 502 WRT_REG_DWORD(®->flash_data, data); 503 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); 504 505 while (cnt--) { 506 if (!(RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG)) 507 return QLA_SUCCESS; 508 udelay(10); 509 cond_resched(); 510 } 511 512 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 513 "Flash write dword at %x timeout.\n", addr); 514 return QLA_FUNCTION_TIMEOUT; 515 } 516 517 static void 518 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 519 uint8_t *flash_id) 520 { 521 uint32_t faddr, ids = 0; 522 523 *man_id = *flash_id = 0; 524 525 faddr = flash_conf_addr(ha, 0x03ab); 526 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 527 *man_id = LSB(ids); 528 *flash_id = MSB(ids); 529 } 530 531 /* Check if man_id and flash_id are valid. */ 532 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 533 /* Read information using 0x9f opcode 534 * Device ID, Mfg ID would be read in the format: 535 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 536 * Example: ATMEL 0x00 01 45 1F 537 * Extract MFG and Dev ID from last two bytes. 538 */ 539 faddr = flash_conf_addr(ha, 0x009f); 540 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 541 *man_id = LSB(ids); 542 *flash_id = MSB(ids); 543 } 544 } 545 } 546 547 static int 548 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) 549 { 550 const char *loc, *locations[] = { "DEF", "PCI" }; 551 uint32_t pcihdr, pcids; 552 uint16_t cnt, chksum, *wptr; 553 struct qla_hw_data *ha = vha->hw; 554 struct req_que *req = ha->req_q_map[0]; 555 struct qla_flt_location *fltl = (void *)req->ring; 556 uint32_t *dcode = (void *)req->ring; 557 uint8_t *buf = (void *)req->ring, *bcode, last_image; 558 559 /* 560 * FLT-location structure resides after the last PCI region. 561 */ 562 563 /* Begin with sane defaults. */ 564 loc = locations[0]; 565 *start = 0; 566 if (IS_QLA24XX_TYPE(ha)) 567 *start = FA_FLASH_LAYOUT_ADDR_24; 568 else if (IS_QLA25XX(ha)) 569 *start = FA_FLASH_LAYOUT_ADDR; 570 else if (IS_QLA81XX(ha)) 571 *start = FA_FLASH_LAYOUT_ADDR_81; 572 else if (IS_P3P_TYPE(ha)) { 573 *start = FA_FLASH_LAYOUT_ADDR_82; 574 goto end; 575 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 576 *start = FA_FLASH_LAYOUT_ADDR_83; 577 goto end; 578 } else if (IS_QLA28XX(ha)) { 579 *start = FA_FLASH_LAYOUT_ADDR_28; 580 goto end; 581 } 582 583 /* Begin with first PCI expansion ROM header. */ 584 pcihdr = 0; 585 do { 586 /* Verify PCI expansion ROM header. */ 587 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 588 bcode = buf + (pcihdr % 4); 589 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) 590 goto end; 591 592 /* Locate PCI data structure. */ 593 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 594 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 595 bcode = buf + (pcihdr % 4); 596 597 /* Validate signature of PCI data structure. */ 598 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 599 bcode[0x2] != 'I' || bcode[0x3] != 'R') 600 goto end; 601 602 last_image = bcode[0x15] & BIT_7; 603 604 /* Locate next PCI expansion ROM. */ 605 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 606 } while (!last_image); 607 608 /* Now verify FLT-location structure. */ 609 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, sizeof(*fltl) >> 2); 610 if (memcmp(fltl->sig, "QFLT", 4)) 611 goto end; 612 613 wptr = (void *)req->ring; 614 cnt = sizeof(*fltl) / sizeof(*wptr); 615 for (chksum = 0; cnt--; wptr++) 616 chksum += le16_to_cpu(*wptr); 617 if (chksum) { 618 ql_log(ql_log_fatal, vha, 0x0045, 619 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); 620 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e, 621 fltl, sizeof(*fltl)); 622 return QLA_FUNCTION_FAILED; 623 } 624 625 /* Good data. Use specified location. */ 626 loc = locations[1]; 627 *start = (le16_to_cpu(fltl->start_hi) << 16 | 628 le16_to_cpu(fltl->start_lo)) >> 2; 629 end: 630 ql_dbg(ql_dbg_init, vha, 0x0046, 631 "FLTL[%s] = 0x%x.\n", 632 loc, *start); 633 return QLA_SUCCESS; 634 } 635 636 static void 637 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) 638 { 639 const char *locations[] = { "DEF", "FLT" }, *loc = locations[1]; 640 const uint32_t def_fw[] = 641 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 }; 642 const uint32_t def_boot[] = 643 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 }; 644 const uint32_t def_vpd_nvram[] = 645 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 }; 646 const uint32_t def_vpd0[] = 647 { 0, 0, FA_VPD0_ADDR_81 }; 648 const uint32_t def_vpd1[] = 649 { 0, 0, FA_VPD1_ADDR_81 }; 650 const uint32_t def_nvram0[] = 651 { 0, 0, FA_NVRAM0_ADDR_81 }; 652 const uint32_t def_nvram1[] = 653 { 0, 0, FA_NVRAM1_ADDR_81 }; 654 const uint32_t def_fdt[] = 655 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR, 656 FA_FLASH_DESCR_ADDR_81 }; 657 const uint32_t def_npiv_conf0[] = 658 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR, 659 FA_NPIV_CONF0_ADDR_81 }; 660 const uint32_t def_npiv_conf1[] = 661 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR, 662 FA_NPIV_CONF1_ADDR_81 }; 663 const uint32_t fcp_prio_cfg0[] = 664 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25, 665 0 }; 666 const uint32_t fcp_prio_cfg1[] = 667 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25, 668 0 }; 669 670 struct qla_hw_data *ha = vha->hw; 671 uint32_t def = IS_QLA81XX(ha) ? 2 : IS_QLA25XX(ha) ? 1 : 0; 672 struct qla_flt_header *flt = (void *)ha->flt; 673 struct qla_flt_region *region = (void *)&flt[1]; 674 uint16_t *wptr, cnt, chksum; 675 uint32_t start; 676 677 /* Assign FCP prio region since older adapters may not have FLT, or 678 FCP prio region in it's FLT. 679 */ 680 ha->flt_region_fcp_prio = (ha->port_no == 0) ? 681 fcp_prio_cfg0[def] : fcp_prio_cfg1[def]; 682 683 ha->flt_region_flt = flt_addr; 684 wptr = (uint16_t *)ha->flt; 685 ha->isp_ops->read_optrom(vha, (void *)flt, flt_addr << 2, 686 (sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE)); 687 688 if (le16_to_cpu(*wptr) == 0xffff) 689 goto no_flash_data; 690 if (flt->version != cpu_to_le16(1)) { 691 ql_log(ql_log_warn, vha, 0x0047, 692 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 693 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 694 le16_to_cpu(flt->checksum)); 695 goto no_flash_data; 696 } 697 698 cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr); 699 for (chksum = 0; cnt--; wptr++) 700 chksum += le16_to_cpu(*wptr); 701 if (chksum) { 702 ql_log(ql_log_fatal, vha, 0x0048, 703 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 704 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 705 le16_to_cpu(flt->checksum)); 706 goto no_flash_data; 707 } 708 709 cnt = le16_to_cpu(flt->length) / sizeof(*region); 710 for ( ; cnt; cnt--, region++) { 711 /* Store addresses as DWORD offsets. */ 712 start = le32_to_cpu(region->start) >> 2; 713 ql_dbg(ql_dbg_init, vha, 0x0049, 714 "FLT[%#x]: start=%#x end=%#x size=%#x.\n", 715 le16_to_cpu(region->code), start, 716 le32_to_cpu(region->end) >> 2, 717 le32_to_cpu(region->size) >> 2); 718 if (region->attribute) 719 ql_log(ql_dbg_init, vha, 0xffff, 720 "Region %x is secure\n", region->code); 721 722 switch (le16_to_cpu(region->code)) { 723 case FLT_REG_FCOE_FW: 724 if (!IS_QLA8031(ha)) 725 break; 726 ha->flt_region_fw = start; 727 break; 728 case FLT_REG_FW: 729 if (IS_QLA8031(ha)) 730 break; 731 ha->flt_region_fw = start; 732 break; 733 case FLT_REG_BOOT_CODE: 734 ha->flt_region_boot = start; 735 break; 736 case FLT_REG_VPD_0: 737 if (IS_QLA8031(ha)) 738 break; 739 ha->flt_region_vpd_nvram = start; 740 if (IS_P3P_TYPE(ha)) 741 break; 742 if (ha->port_no == 0) 743 ha->flt_region_vpd = start; 744 break; 745 case FLT_REG_VPD_1: 746 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 747 break; 748 if (ha->port_no == 1) 749 ha->flt_region_vpd = start; 750 break; 751 case FLT_REG_VPD_2: 752 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 753 break; 754 if (ha->port_no == 2) 755 ha->flt_region_vpd = start; 756 break; 757 case FLT_REG_VPD_3: 758 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 759 break; 760 if (ha->port_no == 3) 761 ha->flt_region_vpd = start; 762 break; 763 case FLT_REG_NVRAM_0: 764 if (IS_QLA8031(ha)) 765 break; 766 if (ha->port_no == 0) 767 ha->flt_region_nvram = start; 768 break; 769 case FLT_REG_NVRAM_1: 770 if (IS_QLA8031(ha)) 771 break; 772 if (ha->port_no == 1) 773 ha->flt_region_nvram = start; 774 break; 775 case FLT_REG_NVRAM_2: 776 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 777 break; 778 if (ha->port_no == 2) 779 ha->flt_region_nvram = start; 780 break; 781 case FLT_REG_NVRAM_3: 782 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 783 break; 784 if (ha->port_no == 3) 785 ha->flt_region_nvram = start; 786 break; 787 case FLT_REG_FDT: 788 ha->flt_region_fdt = start; 789 break; 790 case FLT_REG_NPIV_CONF_0: 791 if (ha->port_no == 0) 792 ha->flt_region_npiv_conf = start; 793 break; 794 case FLT_REG_NPIV_CONF_1: 795 if (ha->port_no == 1) 796 ha->flt_region_npiv_conf = start; 797 break; 798 case FLT_REG_GOLD_FW: 799 ha->flt_region_gold_fw = start; 800 break; 801 case FLT_REG_FCP_PRIO_0: 802 if (ha->port_no == 0) 803 ha->flt_region_fcp_prio = start; 804 break; 805 case FLT_REG_FCP_PRIO_1: 806 if (ha->port_no == 1) 807 ha->flt_region_fcp_prio = start; 808 break; 809 case FLT_REG_BOOT_CODE_82XX: 810 ha->flt_region_boot = start; 811 break; 812 case FLT_REG_BOOT_CODE_8044: 813 if (IS_QLA8044(ha)) 814 ha->flt_region_boot = start; 815 break; 816 case FLT_REG_FW_82XX: 817 ha->flt_region_fw = start; 818 break; 819 case FLT_REG_CNA_FW: 820 if (IS_CNA_CAPABLE(ha)) 821 ha->flt_region_fw = start; 822 break; 823 case FLT_REG_GOLD_FW_82XX: 824 ha->flt_region_gold_fw = start; 825 break; 826 case FLT_REG_BOOTLOAD_82XX: 827 ha->flt_region_bootload = start; 828 break; 829 case FLT_REG_VPD_8XXX: 830 if (IS_CNA_CAPABLE(ha)) 831 ha->flt_region_vpd = start; 832 break; 833 case FLT_REG_FCOE_NVRAM_0: 834 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 835 break; 836 if (ha->port_no == 0) 837 ha->flt_region_nvram = start; 838 break; 839 case FLT_REG_FCOE_NVRAM_1: 840 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 841 break; 842 if (ha->port_no == 1) 843 ha->flt_region_nvram = start; 844 break; 845 case FLT_REG_IMG_PRI_27XX: 846 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 847 ha->flt_region_img_status_pri = start; 848 break; 849 case FLT_REG_IMG_SEC_27XX: 850 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 851 ha->flt_region_img_status_sec = start; 852 break; 853 case FLT_REG_FW_SEC_27XX: 854 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 855 ha->flt_region_fw_sec = start; 856 break; 857 case FLT_REG_BOOTLOAD_SEC_27XX: 858 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 859 ha->flt_region_boot_sec = start; 860 break; 861 case FLT_REG_AUX_IMG_PRI_28XX: 862 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 863 ha->flt_region_aux_img_status_pri = start; 864 break; 865 case FLT_REG_AUX_IMG_SEC_28XX: 866 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 867 ha->flt_region_aux_img_status_sec = start; 868 break; 869 case FLT_REG_NVRAM_SEC_28XX_0: 870 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 871 if (ha->port_no == 0) 872 ha->flt_region_nvram_sec = start; 873 break; 874 case FLT_REG_NVRAM_SEC_28XX_1: 875 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 876 if (ha->port_no == 1) 877 ha->flt_region_nvram_sec = start; 878 break; 879 case FLT_REG_NVRAM_SEC_28XX_2: 880 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 881 if (ha->port_no == 2) 882 ha->flt_region_nvram_sec = start; 883 break; 884 case FLT_REG_NVRAM_SEC_28XX_3: 885 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 886 if (ha->port_no == 3) 887 ha->flt_region_nvram_sec = start; 888 break; 889 case FLT_REG_VPD_SEC_27XX_0: 890 case FLT_REG_VPD_SEC_28XX_0: 891 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 892 ha->flt_region_vpd_nvram_sec = start; 893 if (ha->port_no == 0) 894 ha->flt_region_vpd_sec = start; 895 } 896 break; 897 case FLT_REG_VPD_SEC_27XX_1: 898 case FLT_REG_VPD_SEC_28XX_1: 899 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 900 if (ha->port_no == 1) 901 ha->flt_region_vpd_sec = start; 902 break; 903 case FLT_REG_VPD_SEC_27XX_2: 904 case FLT_REG_VPD_SEC_28XX_2: 905 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 906 if (ha->port_no == 2) 907 ha->flt_region_vpd_sec = start; 908 break; 909 case FLT_REG_VPD_SEC_27XX_3: 910 case FLT_REG_VPD_SEC_28XX_3: 911 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 912 if (ha->port_no == 3) 913 ha->flt_region_vpd_sec = start; 914 break; 915 } 916 } 917 goto done; 918 919 no_flash_data: 920 /* Use hardcoded defaults. */ 921 loc = locations[0]; 922 ha->flt_region_fw = def_fw[def]; 923 ha->flt_region_boot = def_boot[def]; 924 ha->flt_region_vpd_nvram = def_vpd_nvram[def]; 925 ha->flt_region_vpd = (ha->port_no == 0) ? 926 def_vpd0[def] : def_vpd1[def]; 927 ha->flt_region_nvram = (ha->port_no == 0) ? 928 def_nvram0[def] : def_nvram1[def]; 929 ha->flt_region_fdt = def_fdt[def]; 930 ha->flt_region_npiv_conf = (ha->port_no == 0) ? 931 def_npiv_conf0[def] : def_npiv_conf1[def]; 932 done: 933 ql_dbg(ql_dbg_init, vha, 0x004a, 934 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x " 935 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n", 936 loc, ha->flt_region_boot, ha->flt_region_fw, 937 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram, 938 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf, 939 ha->flt_region_fcp_prio); 940 } 941 942 static void 943 qla2xxx_get_fdt_info(scsi_qla_host_t *vha) 944 { 945 #define FLASH_BLK_SIZE_4K 0x1000 946 #define FLASH_BLK_SIZE_32K 0x8000 947 #define FLASH_BLK_SIZE_64K 0x10000 948 const char *loc, *locations[] = { "MID", "FDT" }; 949 struct qla_hw_data *ha = vha->hw; 950 struct req_que *req = ha->req_q_map[0]; 951 uint16_t cnt, chksum; 952 uint16_t *wptr = (void *)req->ring; 953 struct qla_fdt_layout *fdt = (struct qla_fdt_layout *)req->ring; 954 uint8_t man_id, flash_id; 955 uint16_t mid = 0, fid = 0; 956 957 ha->isp_ops->read_optrom(vha, fdt, ha->flt_region_fdt << 2, 958 OPTROM_BURST_DWORDS); 959 if (le16_to_cpu(*wptr) == 0xffff) 960 goto no_flash_data; 961 if (memcmp(fdt->sig, "QLID", 4)) 962 goto no_flash_data; 963 964 for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++) 965 chksum += le16_to_cpu(*wptr); 966 if (chksum) { 967 ql_dbg(ql_dbg_init, vha, 0x004c, 968 "Inconsistent FDT detected:" 969 " checksum=0x%x id=%c version0x%x.\n", chksum, 970 fdt->sig[0], le16_to_cpu(fdt->version)); 971 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113, 972 fdt, sizeof(*fdt)); 973 goto no_flash_data; 974 } 975 976 loc = locations[1]; 977 mid = le16_to_cpu(fdt->man_id); 978 fid = le16_to_cpu(fdt->id); 979 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 980 ha->fdt_wrt_enable = fdt->wrt_enable_bits; 981 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd; 982 if (IS_QLA8044(ha)) 983 ha->fdt_erase_cmd = fdt->erase_cmd; 984 else 985 ha->fdt_erase_cmd = 986 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); 987 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 988 if (fdt->unprotect_sec_cmd) { 989 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | 990 fdt->unprotect_sec_cmd); 991 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 992 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd) : 993 flash_conf_addr(ha, 0x0336); 994 } 995 goto done; 996 no_flash_data: 997 loc = locations[0]; 998 if (IS_P3P_TYPE(ha)) { 999 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1000 goto done; 1001 } 1002 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 1003 mid = man_id; 1004 fid = flash_id; 1005 ha->fdt_wrt_disable = 0x9c; 1006 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); 1007 switch (man_id) { 1008 case 0xbf: /* STT flash. */ 1009 if (flash_id == 0x8e) 1010 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1011 else 1012 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 1013 1014 if (flash_id == 0x80) 1015 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); 1016 break; 1017 case 0x13: /* ST M25P80. */ 1018 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1019 break; 1020 case 0x1f: /* Atmel 26DF081A. */ 1021 ha->fdt_block_size = FLASH_BLK_SIZE_4K; 1022 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); 1023 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); 1024 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); 1025 break; 1026 default: 1027 /* Default to 64 kb sector size. */ 1028 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1029 break; 1030 } 1031 done: 1032 ql_dbg(ql_dbg_init, vha, 0x004d, 1033 "FDT[%s]: (0x%x/0x%x) erase=0x%x " 1034 "pr=%x wrtd=0x%x blk=0x%x.\n", 1035 loc, mid, fid, 1036 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, 1037 ha->fdt_wrt_disable, ha->fdt_block_size); 1038 1039 } 1040 1041 static void 1042 qla2xxx_get_idc_param(scsi_qla_host_t *vha) 1043 { 1044 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 1045 uint32_t *wptr; 1046 struct qla_hw_data *ha = vha->hw; 1047 struct req_que *req = ha->req_q_map[0]; 1048 1049 if (!(IS_P3P_TYPE(ha))) 1050 return; 1051 1052 wptr = (uint32_t *)req->ring; 1053 ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8); 1054 1055 if (*wptr == cpu_to_le32(0xffffffff)) { 1056 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; 1057 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; 1058 } else { 1059 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr); 1060 wptr++; 1061 ha->fcoe_reset_timeout = le32_to_cpu(*wptr); 1062 } 1063 ql_dbg(ql_dbg_init, vha, 0x004e, 1064 "fcoe_dev_init_timeout=%d " 1065 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout, 1066 ha->fcoe_reset_timeout); 1067 return; 1068 } 1069 1070 int 1071 qla2xxx_get_flash_info(scsi_qla_host_t *vha) 1072 { 1073 int ret; 1074 uint32_t flt_addr; 1075 struct qla_hw_data *ha = vha->hw; 1076 1077 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1078 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && 1079 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1080 return QLA_SUCCESS; 1081 1082 ret = qla2xxx_find_flt_start(vha, &flt_addr); 1083 if (ret != QLA_SUCCESS) 1084 return ret; 1085 1086 qla2xxx_get_flt_info(vha, flt_addr); 1087 qla2xxx_get_fdt_info(vha); 1088 qla2xxx_get_idc_param(vha); 1089 1090 return QLA_SUCCESS; 1091 } 1092 1093 void 1094 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) 1095 { 1096 #define NPIV_CONFIG_SIZE (16*1024) 1097 void *data; 1098 uint16_t *wptr; 1099 uint16_t cnt, chksum; 1100 int i; 1101 struct qla_npiv_header hdr; 1102 struct qla_npiv_entry *entry; 1103 struct qla_hw_data *ha = vha->hw; 1104 1105 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1106 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha)) 1107 return; 1108 1109 if (ha->flags.nic_core_reset_hdlr_active) 1110 return; 1111 1112 if (IS_QLA8044(ha)) 1113 return; 1114 1115 ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2, 1116 sizeof(struct qla_npiv_header)); 1117 if (hdr.version == cpu_to_le16(0xffff)) 1118 return; 1119 if (hdr.version != cpu_to_le16(1)) { 1120 ql_dbg(ql_dbg_user, vha, 0x7090, 1121 "Unsupported NPIV-Config " 1122 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1123 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1124 le16_to_cpu(hdr.checksum)); 1125 return; 1126 } 1127 1128 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); 1129 if (!data) { 1130 ql_log(ql_log_warn, vha, 0x7091, 1131 "Unable to allocate memory for data.\n"); 1132 return; 1133 } 1134 1135 ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2, 1136 NPIV_CONFIG_SIZE); 1137 1138 cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1; 1139 for (wptr = data, chksum = 0; cnt--; wptr++) 1140 chksum += le16_to_cpu(*wptr); 1141 if (chksum) { 1142 ql_dbg(ql_dbg_user, vha, 0x7092, 1143 "Inconsistent NPIV-Config " 1144 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1145 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1146 le16_to_cpu(hdr.checksum)); 1147 goto done; 1148 } 1149 1150 entry = data + sizeof(struct qla_npiv_header); 1151 cnt = le16_to_cpu(hdr.entries); 1152 for (i = 0; cnt; cnt--, entry++, i++) { 1153 uint16_t flags; 1154 struct fc_vport_identifiers vid; 1155 struct fc_vport *vport; 1156 1157 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); 1158 1159 flags = le16_to_cpu(entry->flags); 1160 if (flags == 0xffff) 1161 continue; 1162 if ((flags & BIT_0) == 0) 1163 continue; 1164 1165 memset(&vid, 0, sizeof(vid)); 1166 vid.roles = FC_PORT_ROLE_FCP_INITIATOR; 1167 vid.vport_type = FC_PORTTYPE_NPIV; 1168 vid.disable = false; 1169 vid.port_name = wwn_to_u64(entry->port_name); 1170 vid.node_name = wwn_to_u64(entry->node_name); 1171 1172 ql_dbg(ql_dbg_user, vha, 0x7093, 1173 "NPIV[%02x]: wwpn=%llx wwnn=%llx vf_id=%#x Q_qos=%#x F_qos=%#x.\n", 1174 cnt, vid.port_name, vid.node_name, 1175 le16_to_cpu(entry->vf_id), 1176 entry->q_qos, entry->f_qos); 1177 1178 if (i < QLA_PRECONFIG_VPORTS) { 1179 vport = fc_vport_create(vha->host, 0, &vid); 1180 if (!vport) 1181 ql_log(ql_log_warn, vha, 0x7094, 1182 "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n", 1183 cnt, vid.port_name, vid.node_name); 1184 } 1185 } 1186 done: 1187 kfree(data); 1188 } 1189 1190 static int 1191 qla24xx_unprotect_flash(scsi_qla_host_t *vha) 1192 { 1193 struct qla_hw_data *ha = vha->hw; 1194 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1195 1196 if (ha->flags.fac_supported) 1197 return qla81xx_fac_do_write_enable(vha, 1); 1198 1199 /* Enable flash write. */ 1200 WRT_REG_DWORD(®->ctrl_status, 1201 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1202 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1203 1204 if (!ha->fdt_wrt_disable) 1205 goto done; 1206 1207 /* Disable flash write-protection, first clear SR protection bit */ 1208 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1209 /* Then write zero again to clear remaining SR bits.*/ 1210 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1211 done: 1212 return QLA_SUCCESS; 1213 } 1214 1215 static int 1216 qla24xx_protect_flash(scsi_qla_host_t *vha) 1217 { 1218 struct qla_hw_data *ha = vha->hw; 1219 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1220 ulong cnt = 300; 1221 uint32_t faddr, dword; 1222 1223 if (ha->flags.fac_supported) 1224 return qla81xx_fac_do_write_enable(vha, 0); 1225 1226 if (!ha->fdt_wrt_disable) 1227 goto skip_wrt_protect; 1228 1229 /* Enable flash write-protection and wait for completion. */ 1230 faddr = flash_conf_addr(ha, 0x101); 1231 qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable); 1232 faddr = flash_conf_addr(ha, 0x5); 1233 while (cnt--) { 1234 if (!qla24xx_read_flash_dword(ha, faddr, &dword)) { 1235 if (!(dword & BIT_0)) 1236 break; 1237 } 1238 udelay(10); 1239 } 1240 1241 skip_wrt_protect: 1242 /* Disable flash write. */ 1243 WRT_REG_DWORD(®->ctrl_status, 1244 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1245 1246 return QLA_SUCCESS; 1247 } 1248 1249 static int 1250 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) 1251 { 1252 struct qla_hw_data *ha = vha->hw; 1253 uint32_t start, finish; 1254 1255 if (ha->flags.fac_supported) { 1256 start = fdata >> 2; 1257 finish = start + (ha->fdt_block_size >> 2) - 1; 1258 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha, 1259 start), flash_data_addr(ha, finish)); 1260 } 1261 1262 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, 1263 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) | 1264 ((fdata >> 16) & 0xff)); 1265 } 1266 1267 static int 1268 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 1269 uint32_t dwords) 1270 { 1271 int ret; 1272 ulong liter; 1273 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 1274 uint32_t sec_mask, rest_addr, fdata; 1275 dma_addr_t optrom_dma; 1276 void *optrom = NULL; 1277 struct qla_hw_data *ha = vha->hw; 1278 1279 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 1280 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1281 goto next; 1282 1283 /* Allocate dma buffer for burst write */ 1284 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 1285 &optrom_dma, GFP_KERNEL); 1286 if (!optrom) { 1287 ql_log(ql_log_warn, vha, 0x7095, 1288 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 1289 } 1290 1291 next: 1292 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1293 "Unprotect flash...\n"); 1294 ret = qla24xx_unprotect_flash(vha); 1295 if (ret) { 1296 ql_log(ql_log_warn, vha, 0x7096, 1297 "Failed to unprotect flash.\n"); 1298 goto done; 1299 } 1300 1301 rest_addr = (ha->fdt_block_size >> 2) - 1; 1302 sec_mask = ~rest_addr; 1303 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 1304 fdata = (faddr & sec_mask) << 2; 1305 1306 /* Are we at the beginning of a sector? */ 1307 if (!(faddr & rest_addr)) { 1308 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1309 "Erase sector %#x...\n", faddr); 1310 1311 ret = qla24xx_erase_sector(vha, fdata); 1312 if (ret) { 1313 ql_dbg(ql_dbg_user, vha, 0x7007, 1314 "Failed to erase sector %x.\n", faddr); 1315 break; 1316 } 1317 } 1318 1319 if (optrom) { 1320 /* If smaller than a burst remaining */ 1321 if (dwords - liter < dburst) 1322 dburst = dwords - liter; 1323 1324 /* Copy to dma buffer */ 1325 memcpy(optrom, dwptr, dburst << 2); 1326 1327 /* Burst write */ 1328 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1329 "Write burst (%#lx dwords)...\n", dburst); 1330 ret = qla2x00_load_ram(vha, optrom_dma, 1331 flash_data_addr(ha, faddr), dburst); 1332 if (!ret) { 1333 liter += dburst - 1; 1334 faddr += dburst - 1; 1335 dwptr += dburst - 1; 1336 continue; 1337 } 1338 1339 ql_log(ql_log_warn, vha, 0x7097, 1340 "Failed burst-write at %x (%p/%#llx)....\n", 1341 flash_data_addr(ha, faddr), optrom, 1342 (u64)optrom_dma); 1343 1344 dma_free_coherent(&ha->pdev->dev, 1345 OPTROM_BURST_SIZE, optrom, optrom_dma); 1346 optrom = NULL; 1347 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1348 break; 1349 ql_log(ql_log_warn, vha, 0x7098, 1350 "Reverting to slow write...\n"); 1351 } 1352 1353 /* Slow write */ 1354 ret = qla24xx_write_flash_dword(ha, 1355 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr)); 1356 if (ret) { 1357 ql_dbg(ql_dbg_user, vha, 0x7006, 1358 "Failed slopw write %x (%x)\n", faddr, *dwptr); 1359 break; 1360 } 1361 } 1362 1363 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1364 "Protect flash...\n"); 1365 ret = qla24xx_protect_flash(vha); 1366 if (ret) 1367 ql_log(ql_log_warn, vha, 0x7099, 1368 "Failed to protect flash\n"); 1369 done: 1370 if (optrom) 1371 dma_free_coherent(&ha->pdev->dev, 1372 OPTROM_BURST_SIZE, optrom, optrom_dma); 1373 1374 return ret; 1375 } 1376 1377 uint8_t * 1378 qla2x00_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1379 uint32_t bytes) 1380 { 1381 uint32_t i; 1382 uint16_t *wptr; 1383 struct qla_hw_data *ha = vha->hw; 1384 1385 /* Word reads to NVRAM via registers. */ 1386 wptr = (uint16_t *)buf; 1387 qla2x00_lock_nvram_access(ha); 1388 for (i = 0; i < bytes >> 1; i++, naddr++) 1389 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 1390 naddr)); 1391 qla2x00_unlock_nvram_access(ha); 1392 1393 return buf; 1394 } 1395 1396 uint8_t * 1397 qla24xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1398 uint32_t bytes) 1399 { 1400 struct qla_hw_data *ha = vha->hw; 1401 uint32_t *dwptr = buf; 1402 uint32_t i; 1403 1404 if (IS_P3P_TYPE(ha)) 1405 return buf; 1406 1407 /* Dword reads to flash. */ 1408 naddr = nvram_data_addr(ha, naddr); 1409 bytes >>= 2; 1410 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1411 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1412 break; 1413 cpu_to_le32s(dwptr); 1414 } 1415 1416 return buf; 1417 } 1418 1419 int 1420 qla2x00_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1421 uint32_t bytes) 1422 { 1423 int ret, stat; 1424 uint32_t i; 1425 uint16_t *wptr; 1426 unsigned long flags; 1427 struct qla_hw_data *ha = vha->hw; 1428 1429 ret = QLA_SUCCESS; 1430 1431 spin_lock_irqsave(&ha->hardware_lock, flags); 1432 qla2x00_lock_nvram_access(ha); 1433 1434 /* Disable NVRAM write-protection. */ 1435 stat = qla2x00_clear_nvram_protection(ha); 1436 1437 wptr = (uint16_t *)buf; 1438 for (i = 0; i < bytes >> 1; i++, naddr++) { 1439 qla2x00_write_nvram_word(ha, naddr, 1440 cpu_to_le16(*wptr)); 1441 wptr++; 1442 } 1443 1444 /* Enable NVRAM write-protection. */ 1445 qla2x00_set_nvram_protection(ha, stat); 1446 1447 qla2x00_unlock_nvram_access(ha); 1448 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1449 1450 return ret; 1451 } 1452 1453 int 1454 qla24xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1455 uint32_t bytes) 1456 { 1457 struct qla_hw_data *ha = vha->hw; 1458 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1459 uint32_t *dwptr = buf; 1460 uint32_t i; 1461 int ret; 1462 1463 ret = QLA_SUCCESS; 1464 1465 if (IS_P3P_TYPE(ha)) 1466 return ret; 1467 1468 /* Enable flash write. */ 1469 WRT_REG_DWORD(®->ctrl_status, 1470 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1471 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1472 1473 /* Disable NVRAM write-protection. */ 1474 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1475 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1476 1477 /* Dword writes to flash. */ 1478 naddr = nvram_data_addr(ha, naddr); 1479 bytes >>= 2; 1480 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1481 if (qla24xx_write_flash_dword(ha, naddr, cpu_to_le32(*dwptr))) { 1482 ql_dbg(ql_dbg_user, vha, 0x709a, 1483 "Unable to program nvram address=%x data=%x.\n", 1484 naddr, *dwptr); 1485 break; 1486 } 1487 } 1488 1489 /* Enable NVRAM write-protection. */ 1490 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c); 1491 1492 /* Disable flash write. */ 1493 WRT_REG_DWORD(®->ctrl_status, 1494 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1495 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1496 1497 return ret; 1498 } 1499 1500 uint8_t * 1501 qla25xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1502 uint32_t bytes) 1503 { 1504 struct qla_hw_data *ha = vha->hw; 1505 uint32_t *dwptr = buf; 1506 uint32_t i; 1507 1508 /* Dword reads to flash. */ 1509 naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr); 1510 bytes >>= 2; 1511 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1512 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1513 break; 1514 1515 cpu_to_le32s(dwptr); 1516 } 1517 1518 return buf; 1519 } 1520 1521 #define RMW_BUFFER_SIZE (64 * 1024) 1522 int 1523 qla25xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1524 uint32_t bytes) 1525 { 1526 struct qla_hw_data *ha = vha->hw; 1527 uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE); 1528 1529 if (!dbuf) 1530 return QLA_MEMORY_ALLOC_FAILED; 1531 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1532 RMW_BUFFER_SIZE); 1533 memcpy(dbuf + (naddr << 2), buf, bytes); 1534 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1535 RMW_BUFFER_SIZE); 1536 vfree(dbuf); 1537 1538 return QLA_SUCCESS; 1539 } 1540 1541 static inline void 1542 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1543 { 1544 if (IS_QLA2322(ha)) { 1545 /* Flip all colors. */ 1546 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1547 /* Turn off. */ 1548 ha->beacon_color_state = 0; 1549 *pflags = GPIO_LED_ALL_OFF; 1550 } else { 1551 /* Turn on. */ 1552 ha->beacon_color_state = QLA_LED_ALL_ON; 1553 *pflags = GPIO_LED_RGA_ON; 1554 } 1555 } else { 1556 /* Flip green led only. */ 1557 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 1558 /* Turn off. */ 1559 ha->beacon_color_state = 0; 1560 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 1561 } else { 1562 /* Turn on. */ 1563 ha->beacon_color_state = QLA_LED_GRN_ON; 1564 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 1565 } 1566 } 1567 } 1568 1569 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) 1570 1571 void 1572 qla2x00_beacon_blink(struct scsi_qla_host *vha) 1573 { 1574 uint16_t gpio_enable; 1575 uint16_t gpio_data; 1576 uint16_t led_color = 0; 1577 unsigned long flags; 1578 struct qla_hw_data *ha = vha->hw; 1579 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1580 1581 if (IS_P3P_TYPE(ha)) 1582 return; 1583 1584 spin_lock_irqsave(&ha->hardware_lock, flags); 1585 1586 /* Save the Original GPIOE. */ 1587 if (ha->pio_address) { 1588 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1589 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1590 } else { 1591 gpio_enable = RD_REG_WORD(®->gpioe); 1592 gpio_data = RD_REG_WORD(®->gpiod); 1593 } 1594 1595 /* Set the modified gpio_enable values */ 1596 gpio_enable |= GPIO_LED_MASK; 1597 1598 if (ha->pio_address) { 1599 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1600 } else { 1601 WRT_REG_WORD(®->gpioe, gpio_enable); 1602 RD_REG_WORD(®->gpioe); 1603 } 1604 1605 qla2x00_flip_colors(ha, &led_color); 1606 1607 /* Clear out any previously set LED color. */ 1608 gpio_data &= ~GPIO_LED_MASK; 1609 1610 /* Set the new input LED color to GPIOD. */ 1611 gpio_data |= led_color; 1612 1613 /* Set the modified gpio_data values */ 1614 if (ha->pio_address) { 1615 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1616 } else { 1617 WRT_REG_WORD(®->gpiod, gpio_data); 1618 RD_REG_WORD(®->gpiod); 1619 } 1620 1621 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1622 } 1623 1624 int 1625 qla2x00_beacon_on(struct scsi_qla_host *vha) 1626 { 1627 uint16_t gpio_enable; 1628 uint16_t gpio_data; 1629 unsigned long flags; 1630 struct qla_hw_data *ha = vha->hw; 1631 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1632 1633 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1634 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 1635 1636 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1637 ql_log(ql_log_warn, vha, 0x709b, 1638 "Unable to update fw options (beacon on).\n"); 1639 return QLA_FUNCTION_FAILED; 1640 } 1641 1642 /* Turn off LEDs. */ 1643 spin_lock_irqsave(&ha->hardware_lock, flags); 1644 if (ha->pio_address) { 1645 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1646 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1647 } else { 1648 gpio_enable = RD_REG_WORD(®->gpioe); 1649 gpio_data = RD_REG_WORD(®->gpiod); 1650 } 1651 gpio_enable |= GPIO_LED_MASK; 1652 1653 /* Set the modified gpio_enable values. */ 1654 if (ha->pio_address) { 1655 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1656 } else { 1657 WRT_REG_WORD(®->gpioe, gpio_enable); 1658 RD_REG_WORD(®->gpioe); 1659 } 1660 1661 /* Clear out previously set LED colour. */ 1662 gpio_data &= ~GPIO_LED_MASK; 1663 if (ha->pio_address) { 1664 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1665 } else { 1666 WRT_REG_WORD(®->gpiod, gpio_data); 1667 RD_REG_WORD(®->gpiod); 1668 } 1669 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1670 1671 /* 1672 * Let the per HBA timer kick off the blinking process based on 1673 * the following flags. No need to do anything else now. 1674 */ 1675 ha->beacon_blink_led = 1; 1676 ha->beacon_color_state = 0; 1677 1678 return QLA_SUCCESS; 1679 } 1680 1681 int 1682 qla2x00_beacon_off(struct scsi_qla_host *vha) 1683 { 1684 int rval = QLA_SUCCESS; 1685 struct qla_hw_data *ha = vha->hw; 1686 1687 ha->beacon_blink_led = 0; 1688 1689 /* Set the on flag so when it gets flipped it will be off. */ 1690 if (IS_QLA2322(ha)) 1691 ha->beacon_color_state = QLA_LED_ALL_ON; 1692 else 1693 ha->beacon_color_state = QLA_LED_GRN_ON; 1694 1695 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ 1696 1697 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1698 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 1699 1700 rval = qla2x00_set_fw_options(vha, ha->fw_options); 1701 if (rval != QLA_SUCCESS) 1702 ql_log(ql_log_warn, vha, 0x709c, 1703 "Unable to update fw options (beacon off).\n"); 1704 return rval; 1705 } 1706 1707 1708 static inline void 1709 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1710 { 1711 /* Flip all colors. */ 1712 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1713 /* Turn off. */ 1714 ha->beacon_color_state = 0; 1715 *pflags = 0; 1716 } else { 1717 /* Turn on. */ 1718 ha->beacon_color_state = QLA_LED_ALL_ON; 1719 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 1720 } 1721 } 1722 1723 void 1724 qla24xx_beacon_blink(struct scsi_qla_host *vha) 1725 { 1726 uint16_t led_color = 0; 1727 uint32_t gpio_data; 1728 unsigned long flags; 1729 struct qla_hw_data *ha = vha->hw; 1730 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1731 1732 /* Save the Original GPIOD. */ 1733 spin_lock_irqsave(&ha->hardware_lock, flags); 1734 gpio_data = RD_REG_DWORD(®->gpiod); 1735 1736 /* Enable the gpio_data reg for update. */ 1737 gpio_data |= GPDX_LED_UPDATE_MASK; 1738 1739 WRT_REG_DWORD(®->gpiod, gpio_data); 1740 gpio_data = RD_REG_DWORD(®->gpiod); 1741 1742 /* Set the color bits. */ 1743 qla24xx_flip_colors(ha, &led_color); 1744 1745 /* Clear out any previously set LED color. */ 1746 gpio_data &= ~GPDX_LED_COLOR_MASK; 1747 1748 /* Set the new input LED color to GPIOD. */ 1749 gpio_data |= led_color; 1750 1751 /* Set the modified gpio_data values. */ 1752 WRT_REG_DWORD(®->gpiod, gpio_data); 1753 gpio_data = RD_REG_DWORD(®->gpiod); 1754 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1755 } 1756 1757 static uint32_t 1758 qla83xx_select_led_port(struct qla_hw_data *ha) 1759 { 1760 uint32_t led_select_value = 0; 1761 1762 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1763 goto out; 1764 1765 if (ha->port_no == 0) 1766 led_select_value = QLA83XX_LED_PORT0; 1767 else 1768 led_select_value = QLA83XX_LED_PORT1; 1769 1770 out: 1771 return led_select_value; 1772 } 1773 1774 void 1775 qla83xx_beacon_blink(struct scsi_qla_host *vha) 1776 { 1777 uint32_t led_select_value; 1778 struct qla_hw_data *ha = vha->hw; 1779 uint16_t led_cfg[6]; 1780 uint16_t orig_led_cfg[6]; 1781 uint32_t led_10_value, led_43_value; 1782 1783 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha) && 1784 !IS_QLA28XX(ha)) 1785 return; 1786 1787 if (!ha->beacon_blink_led) 1788 return; 1789 1790 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 1791 qla2x00_write_ram_word(vha, 0x1003, 0x40000230); 1792 qla2x00_write_ram_word(vha, 0x1004, 0x40000230); 1793 } else if (IS_QLA2031(ha)) { 1794 led_select_value = qla83xx_select_led_port(ha); 1795 1796 qla83xx_wr_reg(vha, led_select_value, 0x40000230); 1797 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230); 1798 } else if (IS_QLA8031(ha)) { 1799 led_select_value = qla83xx_select_led_port(ha); 1800 1801 qla83xx_rd_reg(vha, led_select_value, &led_10_value); 1802 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value); 1803 qla83xx_wr_reg(vha, led_select_value, 0x01f44000); 1804 msleep(500); 1805 qla83xx_wr_reg(vha, led_select_value, 0x400001f4); 1806 msleep(1000); 1807 qla83xx_wr_reg(vha, led_select_value, led_10_value); 1808 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value); 1809 } else if (IS_QLA81XX(ha)) { 1810 int rval; 1811 1812 /* Save Current */ 1813 rval = qla81xx_get_led_config(vha, orig_led_cfg); 1814 /* Do the blink */ 1815 if (rval == QLA_SUCCESS) { 1816 if (IS_QLA81XX(ha)) { 1817 led_cfg[0] = 0x4000; 1818 led_cfg[1] = 0x2000; 1819 led_cfg[2] = 0; 1820 led_cfg[3] = 0; 1821 led_cfg[4] = 0; 1822 led_cfg[5] = 0; 1823 } else { 1824 led_cfg[0] = 0x4000; 1825 led_cfg[1] = 0x4000; 1826 led_cfg[2] = 0x4000; 1827 led_cfg[3] = 0x2000; 1828 led_cfg[4] = 0; 1829 led_cfg[5] = 0x2000; 1830 } 1831 rval = qla81xx_set_led_config(vha, led_cfg); 1832 msleep(1000); 1833 if (IS_QLA81XX(ha)) { 1834 led_cfg[0] = 0x4000; 1835 led_cfg[1] = 0x2000; 1836 led_cfg[2] = 0; 1837 } else { 1838 led_cfg[0] = 0x4000; 1839 led_cfg[1] = 0x2000; 1840 led_cfg[2] = 0x4000; 1841 led_cfg[3] = 0x4000; 1842 led_cfg[4] = 0; 1843 led_cfg[5] = 0x2000; 1844 } 1845 rval = qla81xx_set_led_config(vha, led_cfg); 1846 } 1847 /* On exit, restore original (presumes no status change) */ 1848 qla81xx_set_led_config(vha, orig_led_cfg); 1849 } 1850 } 1851 1852 int 1853 qla24xx_beacon_on(struct scsi_qla_host *vha) 1854 { 1855 uint32_t gpio_data; 1856 unsigned long flags; 1857 struct qla_hw_data *ha = vha->hw; 1858 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1859 1860 if (IS_P3P_TYPE(ha)) 1861 return QLA_SUCCESS; 1862 1863 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1864 goto skip_gpio; /* let blink handle it */ 1865 1866 if (ha->beacon_blink_led == 0) { 1867 /* Enable firmware for update */ 1868 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1869 1870 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) 1871 return QLA_FUNCTION_FAILED; 1872 1873 if (qla2x00_get_fw_options(vha, ha->fw_options) != 1874 QLA_SUCCESS) { 1875 ql_log(ql_log_warn, vha, 0x7009, 1876 "Unable to update fw options (beacon on).\n"); 1877 return QLA_FUNCTION_FAILED; 1878 } 1879 1880 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1881 goto skip_gpio; 1882 1883 spin_lock_irqsave(&ha->hardware_lock, flags); 1884 gpio_data = RD_REG_DWORD(®->gpiod); 1885 1886 /* Enable the gpio_data reg for update. */ 1887 gpio_data |= GPDX_LED_UPDATE_MASK; 1888 WRT_REG_DWORD(®->gpiod, gpio_data); 1889 RD_REG_DWORD(®->gpiod); 1890 1891 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1892 } 1893 1894 /* So all colors blink together. */ 1895 ha->beacon_color_state = 0; 1896 1897 skip_gpio: 1898 /* Let the per HBA timer kick off the blinking process. */ 1899 ha->beacon_blink_led = 1; 1900 1901 return QLA_SUCCESS; 1902 } 1903 1904 int 1905 qla24xx_beacon_off(struct scsi_qla_host *vha) 1906 { 1907 uint32_t gpio_data; 1908 unsigned long flags; 1909 struct qla_hw_data *ha = vha->hw; 1910 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1911 1912 if (IS_P3P_TYPE(ha)) 1913 return QLA_SUCCESS; 1914 1915 if (!ha->flags.fw_started) 1916 return QLA_SUCCESS; 1917 1918 ha->beacon_blink_led = 0; 1919 1920 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1921 goto set_fw_options; 1922 1923 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1924 return QLA_SUCCESS; 1925 1926 ha->beacon_color_state = QLA_LED_ALL_ON; 1927 1928 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ 1929 1930 /* Give control back to firmware. */ 1931 spin_lock_irqsave(&ha->hardware_lock, flags); 1932 gpio_data = RD_REG_DWORD(®->gpiod); 1933 1934 /* Disable the gpio_data reg for update. */ 1935 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1936 WRT_REG_DWORD(®->gpiod, gpio_data); 1937 RD_REG_DWORD(®->gpiod); 1938 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1939 1940 set_fw_options: 1941 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1942 1943 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1944 ql_log(ql_log_warn, vha, 0x704d, 1945 "Unable to update fw options (beacon on).\n"); 1946 return QLA_FUNCTION_FAILED; 1947 } 1948 1949 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1950 ql_log(ql_log_warn, vha, 0x704e, 1951 "Unable to update fw options (beacon on).\n"); 1952 return QLA_FUNCTION_FAILED; 1953 } 1954 1955 return QLA_SUCCESS; 1956 } 1957 1958 1959 /* 1960 * Flash support routines 1961 */ 1962 1963 /** 1964 * qla2x00_flash_enable() - Setup flash for reading and writing. 1965 * @ha: HA context 1966 */ 1967 static void 1968 qla2x00_flash_enable(struct qla_hw_data *ha) 1969 { 1970 uint16_t data; 1971 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1972 1973 data = RD_REG_WORD(®->ctrl_status); 1974 data |= CSR_FLASH_ENABLE; 1975 WRT_REG_WORD(®->ctrl_status, data); 1976 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1977 } 1978 1979 /** 1980 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1981 * @ha: HA context 1982 */ 1983 static void 1984 qla2x00_flash_disable(struct qla_hw_data *ha) 1985 { 1986 uint16_t data; 1987 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1988 1989 data = RD_REG_WORD(®->ctrl_status); 1990 data &= ~(CSR_FLASH_ENABLE); 1991 WRT_REG_WORD(®->ctrl_status, data); 1992 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1993 } 1994 1995 /** 1996 * qla2x00_read_flash_byte() - Reads a byte from flash 1997 * @ha: HA context 1998 * @addr: Address in flash to read 1999 * 2000 * A word is read from the chip, but, only the lower byte is valid. 2001 * 2002 * Returns the byte read from flash @addr. 2003 */ 2004 static uint8_t 2005 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) 2006 { 2007 uint16_t data; 2008 uint16_t bank_select; 2009 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2010 2011 bank_select = RD_REG_WORD(®->ctrl_status); 2012 2013 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2014 /* Specify 64K address range: */ 2015 /* clear out Module Select and Flash Address bits [19:16]. */ 2016 bank_select &= ~0xf8; 2017 bank_select |= addr >> 12 & 0xf0; 2018 bank_select |= CSR_FLASH_64K_BANK; 2019 WRT_REG_WORD(®->ctrl_status, bank_select); 2020 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2021 2022 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2023 data = RD_REG_WORD(®->flash_data); 2024 2025 return (uint8_t)data; 2026 } 2027 2028 /* Setup bit 16 of flash address. */ 2029 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2030 bank_select |= CSR_FLASH_64K_BANK; 2031 WRT_REG_WORD(®->ctrl_status, bank_select); 2032 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2033 } else if (((addr & BIT_16) == 0) && 2034 (bank_select & CSR_FLASH_64K_BANK)) { 2035 bank_select &= ~(CSR_FLASH_64K_BANK); 2036 WRT_REG_WORD(®->ctrl_status, bank_select); 2037 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2038 } 2039 2040 /* Always perform IO mapped accesses to the FLASH registers. */ 2041 if (ha->pio_address) { 2042 uint16_t data2; 2043 2044 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2045 do { 2046 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2047 barrier(); 2048 cpu_relax(); 2049 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2050 } while (data != data2); 2051 } else { 2052 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2053 data = qla2x00_debounce_register(®->flash_data); 2054 } 2055 2056 return (uint8_t)data; 2057 } 2058 2059 /** 2060 * qla2x00_write_flash_byte() - Write a byte to flash 2061 * @ha: HA context 2062 * @addr: Address in flash to write 2063 * @data: Data to write 2064 */ 2065 static void 2066 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) 2067 { 2068 uint16_t bank_select; 2069 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2070 2071 bank_select = RD_REG_WORD(®->ctrl_status); 2072 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2073 /* Specify 64K address range: */ 2074 /* clear out Module Select and Flash Address bits [19:16]. */ 2075 bank_select &= ~0xf8; 2076 bank_select |= addr >> 12 & 0xf0; 2077 bank_select |= CSR_FLASH_64K_BANK; 2078 WRT_REG_WORD(®->ctrl_status, bank_select); 2079 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2080 2081 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2082 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2083 WRT_REG_WORD(®->flash_data, (uint16_t)data); 2084 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2085 2086 return; 2087 } 2088 2089 /* Setup bit 16 of flash address. */ 2090 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2091 bank_select |= CSR_FLASH_64K_BANK; 2092 WRT_REG_WORD(®->ctrl_status, bank_select); 2093 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2094 } else if (((addr & BIT_16) == 0) && 2095 (bank_select & CSR_FLASH_64K_BANK)) { 2096 bank_select &= ~(CSR_FLASH_64K_BANK); 2097 WRT_REG_WORD(®->ctrl_status, bank_select); 2098 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2099 } 2100 2101 /* Always perform IO mapped accesses to the FLASH registers. */ 2102 if (ha->pio_address) { 2103 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2104 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); 2105 } else { 2106 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2107 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2108 WRT_REG_WORD(®->flash_data, (uint16_t)data); 2109 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2110 } 2111 } 2112 2113 /** 2114 * qla2x00_poll_flash() - Polls flash for completion. 2115 * @ha: HA context 2116 * @addr: Address in flash to poll 2117 * @poll_data: Data to be polled 2118 * @man_id: Flash manufacturer ID 2119 * @flash_id: Flash ID 2120 * 2121 * This function polls the device until bit 7 of what is read matches data 2122 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed 2123 * out (a fatal error). The flash book recommeds reading bit 7 again after 2124 * reading bit 5 as a 1. 2125 * 2126 * Returns 0 on success, else non-zero. 2127 */ 2128 static int 2129 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, 2130 uint8_t man_id, uint8_t flash_id) 2131 { 2132 int status; 2133 uint8_t flash_data; 2134 uint32_t cnt; 2135 2136 status = 1; 2137 2138 /* Wait for 30 seconds for command to finish. */ 2139 poll_data &= BIT_7; 2140 for (cnt = 3000000; cnt; cnt--) { 2141 flash_data = qla2x00_read_flash_byte(ha, addr); 2142 if ((flash_data & BIT_7) == poll_data) { 2143 status = 0; 2144 break; 2145 } 2146 2147 if (man_id != 0x40 && man_id != 0xda) { 2148 if ((flash_data & BIT_5) && cnt > 2) 2149 cnt = 2; 2150 } 2151 udelay(10); 2152 barrier(); 2153 cond_resched(); 2154 } 2155 return status; 2156 } 2157 2158 /** 2159 * qla2x00_program_flash_address() - Programs a flash address 2160 * @ha: HA context 2161 * @addr: Address in flash to program 2162 * @data: Data to be written in flash 2163 * @man_id: Flash manufacturer ID 2164 * @flash_id: Flash ID 2165 * 2166 * Returns 0 on success, else non-zero. 2167 */ 2168 static int 2169 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, 2170 uint8_t data, uint8_t man_id, uint8_t flash_id) 2171 { 2172 /* Write Program Command Sequence. */ 2173 if (IS_OEM_001(ha)) { 2174 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2175 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2176 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 2177 qla2x00_write_flash_byte(ha, addr, data); 2178 } else { 2179 if (man_id == 0xda && flash_id == 0xc1) { 2180 qla2x00_write_flash_byte(ha, addr, data); 2181 if (addr & 0x7e) 2182 return 0; 2183 } else { 2184 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2185 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2186 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 2187 qla2x00_write_flash_byte(ha, addr, data); 2188 } 2189 } 2190 2191 udelay(150); 2192 2193 /* Wait for write to complete. */ 2194 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 2195 } 2196 2197 /** 2198 * qla2x00_erase_flash() - Erase the flash. 2199 * @ha: HA context 2200 * @man_id: Flash manufacturer ID 2201 * @flash_id: Flash ID 2202 * 2203 * Returns 0 on success, else non-zero. 2204 */ 2205 static int 2206 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id) 2207 { 2208 /* Individual Sector Erase Command Sequence */ 2209 if (IS_OEM_001(ha)) { 2210 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2211 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2212 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 2213 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2214 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2215 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 2216 } else { 2217 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2218 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2219 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2220 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2221 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2222 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 2223 } 2224 2225 udelay(150); 2226 2227 /* Wait for erase to complete. */ 2228 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 2229 } 2230 2231 /** 2232 * qla2x00_erase_flash_sector() - Erase a flash sector. 2233 * @ha: HA context 2234 * @addr: Flash sector to erase 2235 * @sec_mask: Sector address mask 2236 * @man_id: Flash manufacturer ID 2237 * @flash_id: Flash ID 2238 * 2239 * Returns 0 on success, else non-zero. 2240 */ 2241 static int 2242 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, 2243 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 2244 { 2245 /* Individual Sector Erase Command Sequence */ 2246 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2247 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2248 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2249 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2250 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2251 if (man_id == 0x1f && flash_id == 0x13) 2252 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 2253 else 2254 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 2255 2256 udelay(150); 2257 2258 /* Wait for erase to complete. */ 2259 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 2260 } 2261 2262 /** 2263 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 2264 * @ha: host adapter 2265 * @man_id: Flash manufacturer ID 2266 * @flash_id: Flash ID 2267 */ 2268 static void 2269 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 2270 uint8_t *flash_id) 2271 { 2272 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2273 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2274 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 2275 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 2276 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 2277 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2278 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2279 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 2280 } 2281 2282 static void 2283 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf, 2284 uint32_t saddr, uint32_t length) 2285 { 2286 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2287 uint32_t midpoint, ilength; 2288 uint8_t data; 2289 2290 midpoint = length / 2; 2291 2292 WRT_REG_WORD(®->nvram, 0); 2293 RD_REG_WORD(®->nvram); 2294 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 2295 if (ilength == midpoint) { 2296 WRT_REG_WORD(®->nvram, NVR_SELECT); 2297 RD_REG_WORD(®->nvram); 2298 } 2299 data = qla2x00_read_flash_byte(ha, saddr); 2300 if (saddr % 100) 2301 udelay(10); 2302 *tmp_buf = data; 2303 cond_resched(); 2304 } 2305 } 2306 2307 static inline void 2308 qla2x00_suspend_hba(struct scsi_qla_host *vha) 2309 { 2310 int cnt; 2311 unsigned long flags; 2312 struct qla_hw_data *ha = vha->hw; 2313 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2314 2315 /* Suspend HBA. */ 2316 scsi_block_requests(vha->host); 2317 ha->isp_ops->disable_intrs(ha); 2318 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2319 2320 /* Pause RISC. */ 2321 spin_lock_irqsave(&ha->hardware_lock, flags); 2322 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 2323 RD_REG_WORD(®->hccr); 2324 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2325 for (cnt = 0; cnt < 30000; cnt++) { 2326 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 2327 break; 2328 udelay(100); 2329 } 2330 } else { 2331 udelay(10); 2332 } 2333 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2334 } 2335 2336 static inline void 2337 qla2x00_resume_hba(struct scsi_qla_host *vha) 2338 { 2339 struct qla_hw_data *ha = vha->hw; 2340 2341 /* Resume HBA. */ 2342 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2343 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2344 qla2xxx_wake_dpc(vha); 2345 qla2x00_wait_for_chip_reset(vha); 2346 scsi_unblock_requests(vha->host); 2347 } 2348 2349 void * 2350 qla2x00_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2351 uint32_t offset, uint32_t length) 2352 { 2353 uint32_t addr, midpoint; 2354 uint8_t *data; 2355 struct qla_hw_data *ha = vha->hw; 2356 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2357 2358 /* Suspend HBA. */ 2359 qla2x00_suspend_hba(vha); 2360 2361 /* Go with read. */ 2362 midpoint = ha->optrom_size / 2; 2363 2364 qla2x00_flash_enable(ha); 2365 WRT_REG_WORD(®->nvram, 0); 2366 RD_REG_WORD(®->nvram); /* PCI Posting. */ 2367 for (addr = offset, data = buf; addr < length; addr++, data++) { 2368 if (addr == midpoint) { 2369 WRT_REG_WORD(®->nvram, NVR_SELECT); 2370 RD_REG_WORD(®->nvram); /* PCI Posting. */ 2371 } 2372 2373 *data = qla2x00_read_flash_byte(ha, addr); 2374 } 2375 qla2x00_flash_disable(ha); 2376 2377 /* Resume HBA. */ 2378 qla2x00_resume_hba(vha); 2379 2380 return buf; 2381 } 2382 2383 int 2384 qla2x00_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2385 uint32_t offset, uint32_t length) 2386 { 2387 2388 int rval; 2389 uint8_t man_id, flash_id, sec_number, *data; 2390 uint16_t wd; 2391 uint32_t addr, liter, sec_mask, rest_addr; 2392 struct qla_hw_data *ha = vha->hw; 2393 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2394 2395 /* Suspend HBA. */ 2396 qla2x00_suspend_hba(vha); 2397 2398 rval = QLA_SUCCESS; 2399 sec_number = 0; 2400 2401 /* Reset ISP chip. */ 2402 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 2403 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2404 2405 /* Go with write. */ 2406 qla2x00_flash_enable(ha); 2407 do { /* Loop once to provide quick error exit */ 2408 /* Structure of flash memory based on manufacturer */ 2409 if (IS_OEM_001(ha)) { 2410 /* OEM variant with special flash part. */ 2411 man_id = flash_id = 0; 2412 rest_addr = 0xffff; 2413 sec_mask = 0x10000; 2414 goto update_flash; 2415 } 2416 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 2417 switch (man_id) { 2418 case 0x20: /* ST flash. */ 2419 if (flash_id == 0xd2 || flash_id == 0xe3) { 2420 /* 2421 * ST m29w008at part - 64kb sector size with 2422 * 32kb,8kb,8kb,16kb sectors at memory address 2423 * 0xf0000. 2424 */ 2425 rest_addr = 0xffff; 2426 sec_mask = 0x10000; 2427 break; 2428 } 2429 /* 2430 * ST m29w010b part - 16kb sector size 2431 * Default to 16kb sectors 2432 */ 2433 rest_addr = 0x3fff; 2434 sec_mask = 0x1c000; 2435 break; 2436 case 0x40: /* Mostel flash. */ 2437 /* Mostel v29c51001 part - 512 byte sector size. */ 2438 rest_addr = 0x1ff; 2439 sec_mask = 0x1fe00; 2440 break; 2441 case 0xbf: /* SST flash. */ 2442 /* SST39sf10 part - 4kb sector size. */ 2443 rest_addr = 0xfff; 2444 sec_mask = 0x1f000; 2445 break; 2446 case 0xda: /* Winbond flash. */ 2447 /* Winbond W29EE011 part - 256 byte sector size. */ 2448 rest_addr = 0x7f; 2449 sec_mask = 0x1ff80; 2450 break; 2451 case 0xc2: /* Macronix flash. */ 2452 /* 64k sector size. */ 2453 if (flash_id == 0x38 || flash_id == 0x4f) { 2454 rest_addr = 0xffff; 2455 sec_mask = 0x10000; 2456 break; 2457 } 2458 /* Fall through... */ 2459 2460 case 0x1f: /* Atmel flash. */ 2461 /* 512k sector size. */ 2462 if (flash_id == 0x13) { 2463 rest_addr = 0x7fffffff; 2464 sec_mask = 0x80000000; 2465 break; 2466 } 2467 /* Fall through... */ 2468 2469 case 0x01: /* AMD flash. */ 2470 if (flash_id == 0x38 || flash_id == 0x40 || 2471 flash_id == 0x4f) { 2472 /* Am29LV081 part - 64kb sector size. */ 2473 /* Am29LV002BT part - 64kb sector size. */ 2474 rest_addr = 0xffff; 2475 sec_mask = 0x10000; 2476 break; 2477 } else if (flash_id == 0x3e) { 2478 /* 2479 * Am29LV008b part - 64kb sector size with 2480 * 32kb,8kb,8kb,16kb sector at memory address 2481 * h0xf0000. 2482 */ 2483 rest_addr = 0xffff; 2484 sec_mask = 0x10000; 2485 break; 2486 } else if (flash_id == 0x20 || flash_id == 0x6e) { 2487 /* 2488 * Am29LV010 part or AM29f010 - 16kb sector 2489 * size. 2490 */ 2491 rest_addr = 0x3fff; 2492 sec_mask = 0x1c000; 2493 break; 2494 } else if (flash_id == 0x6d) { 2495 /* Am29LV001 part - 8kb sector size. */ 2496 rest_addr = 0x1fff; 2497 sec_mask = 0x1e000; 2498 break; 2499 } 2500 /* fall through */ 2501 default: 2502 /* Default to 16 kb sector size. */ 2503 rest_addr = 0x3fff; 2504 sec_mask = 0x1c000; 2505 break; 2506 } 2507 2508 update_flash: 2509 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2510 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 2511 rval = QLA_FUNCTION_FAILED; 2512 break; 2513 } 2514 } 2515 2516 for (addr = offset, liter = 0; liter < length; liter++, 2517 addr++) { 2518 data = buf + liter; 2519 /* Are we at the beginning of a sector? */ 2520 if ((addr & rest_addr) == 0) { 2521 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2522 if (addr >= 0x10000UL) { 2523 if (((addr >> 12) & 0xf0) && 2524 ((man_id == 0x01 && 2525 flash_id == 0x3e) || 2526 (man_id == 0x20 && 2527 flash_id == 0xd2))) { 2528 sec_number++; 2529 if (sec_number == 1) { 2530 rest_addr = 2531 0x7fff; 2532 sec_mask = 2533 0x18000; 2534 } else if ( 2535 sec_number == 2 || 2536 sec_number == 3) { 2537 rest_addr = 2538 0x1fff; 2539 sec_mask = 2540 0x1e000; 2541 } else if ( 2542 sec_number == 4) { 2543 rest_addr = 2544 0x3fff; 2545 sec_mask = 2546 0x1c000; 2547 } 2548 } 2549 } 2550 } else if (addr == ha->optrom_size / 2) { 2551 WRT_REG_WORD(®->nvram, NVR_SELECT); 2552 RD_REG_WORD(®->nvram); 2553 } 2554 2555 if (flash_id == 0xda && man_id == 0xc1) { 2556 qla2x00_write_flash_byte(ha, 0x5555, 2557 0xaa); 2558 qla2x00_write_flash_byte(ha, 0x2aaa, 2559 0x55); 2560 qla2x00_write_flash_byte(ha, 0x5555, 2561 0xa0); 2562 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 2563 /* Then erase it */ 2564 if (qla2x00_erase_flash_sector(ha, 2565 addr, sec_mask, man_id, 2566 flash_id)) { 2567 rval = QLA_FUNCTION_FAILED; 2568 break; 2569 } 2570 if (man_id == 0x01 && flash_id == 0x6d) 2571 sec_number++; 2572 } 2573 } 2574 2575 if (man_id == 0x01 && flash_id == 0x6d) { 2576 if (sec_number == 1 && 2577 addr == (rest_addr - 1)) { 2578 rest_addr = 0x0fff; 2579 sec_mask = 0x1f000; 2580 } else if (sec_number == 3 && (addr & 0x7ffe)) { 2581 rest_addr = 0x3fff; 2582 sec_mask = 0x1c000; 2583 } 2584 } 2585 2586 if (qla2x00_program_flash_address(ha, addr, *data, 2587 man_id, flash_id)) { 2588 rval = QLA_FUNCTION_FAILED; 2589 break; 2590 } 2591 cond_resched(); 2592 } 2593 } while (0); 2594 qla2x00_flash_disable(ha); 2595 2596 /* Resume HBA. */ 2597 qla2x00_resume_hba(vha); 2598 2599 return rval; 2600 } 2601 2602 void * 2603 qla24xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2604 uint32_t offset, uint32_t length) 2605 { 2606 struct qla_hw_data *ha = vha->hw; 2607 2608 /* Suspend HBA. */ 2609 scsi_block_requests(vha->host); 2610 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2611 2612 /* Go with read. */ 2613 qla24xx_read_flash_data(vha, (void *)buf, offset >> 2, length >> 2); 2614 2615 /* Resume HBA. */ 2616 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2617 scsi_unblock_requests(vha->host); 2618 2619 return buf; 2620 } 2621 2622 static int 2623 qla28xx_extract_sfub_and_verify(struct scsi_qla_host *vha, uint32_t *buf, 2624 uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf) 2625 { 2626 uint32_t *p, check_sum = 0; 2627 int i; 2628 2629 p = buf + buf_size_without_sfub; 2630 2631 /* Extract SFUB from end of file */ 2632 memcpy(sfub_buf, (uint8_t *)p, 2633 sizeof(struct secure_flash_update_block)); 2634 2635 for (i = 0; i < (sizeof(struct secure_flash_update_block) >> 2); i++) 2636 check_sum += p[i]; 2637 2638 check_sum = (~check_sum) + 1; 2639 2640 if (check_sum != p[i]) { 2641 ql_log(ql_log_warn, vha, 0x7097, 2642 "SFUB checksum failed, 0x%x, 0x%x\n", 2643 check_sum, p[i]); 2644 return QLA_COMMAND_ERROR; 2645 } 2646 2647 return QLA_SUCCESS; 2648 } 2649 2650 static int 2651 qla28xx_get_flash_region(struct scsi_qla_host *vha, uint32_t start, 2652 struct qla_flt_region *region) 2653 { 2654 struct qla_hw_data *ha = vha->hw; 2655 struct qla_flt_header *flt; 2656 struct qla_flt_region *flt_reg; 2657 uint16_t cnt; 2658 int rval = QLA_FUNCTION_FAILED; 2659 2660 if (!ha->flt) 2661 return QLA_FUNCTION_FAILED; 2662 2663 flt = (struct qla_flt_header *)ha->flt; 2664 flt_reg = (struct qla_flt_region *)&flt[1]; 2665 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 2666 2667 for (; cnt; cnt--, flt_reg++) { 2668 if (flt_reg->start == start) { 2669 memcpy((uint8_t *)region, flt_reg, 2670 sizeof(struct qla_flt_region)); 2671 rval = QLA_SUCCESS; 2672 break; 2673 } 2674 } 2675 2676 return rval; 2677 } 2678 2679 static int 2680 qla28xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2681 uint32_t dwords) 2682 { 2683 struct qla_hw_data *ha = vha->hw; 2684 ulong liter; 2685 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 2686 uint32_t sec_mask, rest_addr, fdata; 2687 void *optrom = NULL; 2688 dma_addr_t optrom_dma; 2689 int rval; 2690 struct secure_flash_update_block *sfub; 2691 dma_addr_t sfub_dma; 2692 uint32_t offset = faddr << 2; 2693 uint32_t buf_size_without_sfub = 0; 2694 struct qla_flt_region region; 2695 bool reset_to_rom = false; 2696 uint32_t risc_size, risc_attr = 0; 2697 uint32_t *fw_array = NULL; 2698 2699 /* Retrieve region info - must be a start address passed in */ 2700 rval = qla28xx_get_flash_region(vha, offset, ®ion); 2701 2702 if (rval != QLA_SUCCESS) { 2703 ql_log(ql_log_warn, vha, 0xffff, 2704 "Invalid address %x - not a region start address\n", 2705 offset); 2706 goto done; 2707 } 2708 2709 /* Allocate dma buffer for burst write */ 2710 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2711 &optrom_dma, GFP_KERNEL); 2712 if (!optrom) { 2713 ql_log(ql_log_warn, vha, 0x7095, 2714 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 2715 rval = QLA_COMMAND_ERROR; 2716 goto done; 2717 } 2718 2719 /* 2720 * If adapter supports secure flash and region is secure 2721 * extract secure flash update block (SFUB) and verify 2722 */ 2723 if (ha->flags.secure_adapter && region.attribute) { 2724 2725 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2726 "Region %x is secure\n", region.code); 2727 2728 if (region.code == FLT_REG_FW || 2729 region.code == FLT_REG_FW_SEC_27XX) { 2730 fw_array = dwptr; 2731 2732 /* 1st fw array */ 2733 risc_size = be32_to_cpu(fw_array[3]); 2734 risc_attr = be32_to_cpu(fw_array[9]); 2735 2736 buf_size_without_sfub = risc_size; 2737 fw_array += risc_size; 2738 2739 /* 2nd fw array */ 2740 risc_size = be32_to_cpu(fw_array[3]); 2741 2742 buf_size_without_sfub += risc_size; 2743 fw_array += risc_size; 2744 2745 /* 1st dump template */ 2746 risc_size = be32_to_cpu(fw_array[2]); 2747 2748 /* skip header and ignore checksum */ 2749 buf_size_without_sfub += risc_size; 2750 fw_array += risc_size; 2751 2752 if (risc_attr & BIT_9) { 2753 /* 2nd dump template */ 2754 risc_size = be32_to_cpu(fw_array[2]); 2755 2756 /* skip header and ignore checksum */ 2757 buf_size_without_sfub += risc_size; 2758 fw_array += risc_size; 2759 } 2760 } else { 2761 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2762 "Secure region %x not supported\n", 2763 region.code); 2764 rval = QLA_COMMAND_ERROR; 2765 goto done; 2766 } 2767 2768 sfub = dma_alloc_coherent(&ha->pdev->dev, 2769 sizeof(struct secure_flash_update_block), &sfub_dma, 2770 GFP_KERNEL); 2771 if (!sfub) { 2772 ql_log(ql_log_warn, vha, 0xffff, 2773 "Unable to allocate memory for SFUB\n"); 2774 rval = QLA_COMMAND_ERROR; 2775 goto done; 2776 } 2777 2778 rval = qla28xx_extract_sfub_and_verify(vha, dwptr, dwords, 2779 buf_size_without_sfub, (uint8_t *)sfub); 2780 2781 if (rval != QLA_SUCCESS) 2782 goto done; 2783 2784 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2785 "SFUB extract and verify successful\n"); 2786 } 2787 2788 rest_addr = (ha->fdt_block_size >> 2) - 1; 2789 sec_mask = ~rest_addr; 2790 2791 /* Lock semaphore */ 2792 rval = qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_LOCK); 2793 if (rval != QLA_SUCCESS) { 2794 ql_log(ql_log_warn, vha, 0xffff, 2795 "Unable to lock flash semaphore."); 2796 goto done; 2797 } 2798 2799 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2800 "Unprotect flash...\n"); 2801 rval = qla24xx_unprotect_flash(vha); 2802 if (rval) { 2803 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2804 ql_log(ql_log_warn, vha, 0x7096, "Failed unprotect flash\n"); 2805 goto done; 2806 } 2807 2808 for (liter = 0; liter < dwords; liter++, faddr++) { 2809 fdata = (faddr & sec_mask) << 2; 2810 2811 /* If start of sector */ 2812 if (!(faddr & rest_addr)) { 2813 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2814 "Erase sector %#x...\n", faddr); 2815 rval = qla24xx_erase_sector(vha, fdata); 2816 if (rval) { 2817 ql_dbg(ql_dbg_user, vha, 0x7007, 2818 "Failed erase sector %#x\n", faddr); 2819 goto write_protect; 2820 } 2821 } 2822 } 2823 2824 if (ha->flags.secure_adapter) { 2825 /* 2826 * If adapter supports secure flash but FW doesn't, 2827 * disable write protect, release semaphore and reset 2828 * chip to execute ROM code in order to update region securely 2829 */ 2830 if (!ha->flags.secure_fw) { 2831 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2832 "Disable Write and Release Semaphore."); 2833 rval = qla24xx_protect_flash(vha); 2834 if (rval != QLA_SUCCESS) { 2835 qla81xx_fac_semaphore_access(vha, 2836 FAC_SEMAPHORE_UNLOCK); 2837 ql_log(ql_log_warn, vha, 0xffff, 2838 "Unable to protect flash."); 2839 goto done; 2840 } 2841 2842 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2843 "Reset chip to ROM."); 2844 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2845 set_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags); 2846 qla2xxx_wake_dpc(vha); 2847 rval = qla2x00_wait_for_chip_reset(vha); 2848 if (rval != QLA_SUCCESS) { 2849 ql_log(ql_log_warn, vha, 0xffff, 2850 "Unable to reset to ROM code."); 2851 goto done; 2852 } 2853 reset_to_rom = true; 2854 ha->flags.fac_supported = 0; 2855 2856 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2857 "Lock Semaphore"); 2858 rval = qla2xxx_write_remote_register(vha, 2859 FLASH_SEMAPHORE_REGISTER_ADDR, 0x00020002); 2860 if (rval != QLA_SUCCESS) { 2861 ql_log(ql_log_warn, vha, 0xffff, 2862 "Unable to lock flash semaphore."); 2863 goto done; 2864 } 2865 2866 /* Unprotect flash */ 2867 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2868 "Enable Write."); 2869 rval = qla2x00_write_ram_word(vha, 0x7ffd0101, 0); 2870 if (rval) { 2871 ql_log(ql_log_warn, vha, 0x7096, 2872 "Failed unprotect flash\n"); 2873 goto done; 2874 } 2875 } 2876 2877 /* If region is secure, send Secure Flash MB Cmd */ 2878 if (region.attribute && buf_size_without_sfub) { 2879 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2880 "Sending Secure Flash MB Cmd\n"); 2881 rval = qla28xx_secure_flash_update(vha, 0, region.code, 2882 buf_size_without_sfub, sfub_dma, 2883 sizeof(struct secure_flash_update_block)); 2884 if (rval != QLA_SUCCESS) { 2885 ql_log(ql_log_warn, vha, 0xffff, 2886 "Secure Flash MB Cmd failed %x.", rval); 2887 goto write_protect; 2888 } 2889 } 2890 2891 } 2892 2893 /* re-init flash offset */ 2894 faddr = offset >> 2; 2895 2896 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 2897 fdata = (faddr & sec_mask) << 2; 2898 2899 /* If smaller than a burst remaining */ 2900 if (dwords - liter < dburst) 2901 dburst = dwords - liter; 2902 2903 /* Copy to dma buffer */ 2904 memcpy(optrom, dwptr, dburst << 2); 2905 2906 /* Burst write */ 2907 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2908 "Write burst (%#lx dwords)...\n", dburst); 2909 rval = qla2x00_load_ram(vha, optrom_dma, 2910 flash_data_addr(ha, faddr), dburst); 2911 if (rval != QLA_SUCCESS) { 2912 ql_log(ql_log_warn, vha, 0x7097, 2913 "Failed burst write at %x (%p/%#llx)...\n", 2914 flash_data_addr(ha, faddr), optrom, 2915 (u64)optrom_dma); 2916 break; 2917 } 2918 2919 liter += dburst - 1; 2920 faddr += dburst - 1; 2921 dwptr += dburst - 1; 2922 continue; 2923 } 2924 2925 write_protect: 2926 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2927 "Protect flash...\n"); 2928 rval = qla24xx_protect_flash(vha); 2929 if (rval) { 2930 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2931 ql_log(ql_log_warn, vha, 0x7099, 2932 "Failed protect flash\n"); 2933 } 2934 2935 if (reset_to_rom == true) { 2936 /* Schedule DPC to restart the RISC */ 2937 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2938 qla2xxx_wake_dpc(vha); 2939 2940 rval = qla2x00_wait_for_hba_online(vha); 2941 if (rval != QLA_SUCCESS) 2942 ql_log(ql_log_warn, vha, 0xffff, 2943 "Adapter did not come out of reset\n"); 2944 } 2945 2946 done: 2947 if (optrom) 2948 dma_free_coherent(&ha->pdev->dev, 2949 OPTROM_BURST_SIZE, optrom, optrom_dma); 2950 2951 return rval; 2952 } 2953 2954 int 2955 qla24xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2956 uint32_t offset, uint32_t length) 2957 { 2958 int rval; 2959 struct qla_hw_data *ha = vha->hw; 2960 2961 /* Suspend HBA. */ 2962 scsi_block_requests(vha->host); 2963 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2964 2965 /* Go with write. */ 2966 if (IS_QLA28XX(ha)) 2967 rval = qla28xx_write_flash_data(vha, (uint32_t *)buf, 2968 offset >> 2, length >> 2); 2969 else 2970 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, 2971 offset >> 2, length >> 2); 2972 2973 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2974 scsi_unblock_requests(vha->host); 2975 2976 return rval; 2977 } 2978 2979 void * 2980 qla25xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2981 uint32_t offset, uint32_t length) 2982 { 2983 int rval; 2984 dma_addr_t optrom_dma; 2985 void *optrom; 2986 uint8_t *pbuf; 2987 uint32_t faddr, left, burst; 2988 struct qla_hw_data *ha = vha->hw; 2989 2990 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 2991 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2992 goto try_fast; 2993 if (offset & 0xfff) 2994 goto slow_read; 2995 if (length < OPTROM_BURST_SIZE) 2996 goto slow_read; 2997 2998 try_fast: 2999 if (offset & 0xff) 3000 goto slow_read; 3001 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3002 &optrom_dma, GFP_KERNEL); 3003 if (!optrom) { 3004 ql_log(ql_log_warn, vha, 0x00cc, 3005 "Unable to allocate memory for optrom burst read (%x KB).\n", 3006 OPTROM_BURST_SIZE / 1024); 3007 goto slow_read; 3008 } 3009 3010 pbuf = buf; 3011 faddr = offset >> 2; 3012 left = length >> 2; 3013 burst = OPTROM_BURST_DWORDS; 3014 while (left != 0) { 3015 if (burst > left) 3016 burst = left; 3017 3018 rval = qla2x00_dump_ram(vha, optrom_dma, 3019 flash_data_addr(ha, faddr), burst); 3020 if (rval) { 3021 ql_log(ql_log_warn, vha, 0x00f5, 3022 "Unable to burst-read optrom segment (%x/%x/%llx).\n", 3023 rval, flash_data_addr(ha, faddr), 3024 (unsigned long long)optrom_dma); 3025 ql_log(ql_log_warn, vha, 0x00f6, 3026 "Reverting to slow-read.\n"); 3027 3028 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3029 optrom, optrom_dma); 3030 goto slow_read; 3031 } 3032 3033 memcpy(pbuf, optrom, burst * 4); 3034 3035 left -= burst; 3036 faddr += burst; 3037 pbuf += burst * 4; 3038 } 3039 3040 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, 3041 optrom_dma); 3042 3043 return buf; 3044 3045 slow_read: 3046 return qla24xx_read_optrom_data(vha, buf, offset, length); 3047 } 3048 3049 /** 3050 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 3051 * @ha: HA context 3052 * @pcids: Pointer to the FCODE PCI data structure 3053 * 3054 * The process of retrieving the FCODE version information is at best 3055 * described as interesting. 3056 * 3057 * Within the first 100h bytes of the image an ASCII string is present 3058 * which contains several pieces of information including the FCODE 3059 * version. Unfortunately it seems the only reliable way to retrieve 3060 * the version is by scanning for another sentinel within the string, 3061 * the FCODE build date: 3062 * 3063 * ... 2.00.02 10/17/02 ... 3064 * 3065 * Returns QLA_SUCCESS on successful retrieval of version. 3066 */ 3067 static void 3068 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) 3069 { 3070 int ret = QLA_FUNCTION_FAILED; 3071 uint32_t istart, iend, iter, vend; 3072 uint8_t do_next, rbyte, *vbyte; 3073 3074 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3075 3076 /* Skip the PCI data structure. */ 3077 istart = pcids + 3078 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 3079 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 3080 iend = istart + 0x100; 3081 do { 3082 /* Scan for the sentinel date string...eeewww. */ 3083 do_next = 0; 3084 iter = istart; 3085 while ((iter < iend) && !do_next) { 3086 iter++; 3087 if (qla2x00_read_flash_byte(ha, iter) == '/') { 3088 if (qla2x00_read_flash_byte(ha, iter + 2) == 3089 '/') 3090 do_next++; 3091 else if (qla2x00_read_flash_byte(ha, 3092 iter + 3) == '/') 3093 do_next++; 3094 } 3095 } 3096 if (!do_next) 3097 break; 3098 3099 /* Backtrack to previous ' ' (space). */ 3100 do_next = 0; 3101 while ((iter > istart) && !do_next) { 3102 iter--; 3103 if (qla2x00_read_flash_byte(ha, iter) == ' ') 3104 do_next++; 3105 } 3106 if (!do_next) 3107 break; 3108 3109 /* 3110 * Mark end of version tag, and find previous ' ' (space) or 3111 * string length (recent FCODE images -- major hack ahead!!!). 3112 */ 3113 vend = iter - 1; 3114 do_next = 0; 3115 while ((iter > istart) && !do_next) { 3116 iter--; 3117 rbyte = qla2x00_read_flash_byte(ha, iter); 3118 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 3119 do_next++; 3120 } 3121 if (!do_next) 3122 break; 3123 3124 /* Mark beginning of version tag, and copy data. */ 3125 iter++; 3126 if ((vend - iter) && 3127 ((vend - iter) < sizeof(ha->fcode_revision))) { 3128 vbyte = ha->fcode_revision; 3129 while (iter <= vend) { 3130 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 3131 iter++; 3132 } 3133 ret = QLA_SUCCESS; 3134 } 3135 } while (0); 3136 3137 if (ret != QLA_SUCCESS) 3138 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3139 } 3140 3141 int 3142 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3143 { 3144 int ret = QLA_SUCCESS; 3145 uint8_t code_type, last_image; 3146 uint32_t pcihdr, pcids; 3147 uint8_t *dbyte; 3148 uint16_t *dcode; 3149 struct qla_hw_data *ha = vha->hw; 3150 3151 if (!ha->pio_address || !mbuf) 3152 return QLA_FUNCTION_FAILED; 3153 3154 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3155 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3156 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3157 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3158 3159 qla2x00_flash_enable(ha); 3160 3161 /* Begin with first PCI expansion ROM header. */ 3162 pcihdr = 0; 3163 last_image = 1; 3164 do { 3165 /* Verify PCI expansion ROM header. */ 3166 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 3167 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 3168 /* No signature */ 3169 ql_log(ql_log_fatal, vha, 0x0050, 3170 "No matching ROM signature.\n"); 3171 ret = QLA_FUNCTION_FAILED; 3172 break; 3173 } 3174 3175 /* Locate PCI data structure. */ 3176 pcids = pcihdr + 3177 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 3178 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 3179 3180 /* Validate signature of PCI data structure. */ 3181 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 3182 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 3183 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 3184 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 3185 /* Incorrect header. */ 3186 ql_log(ql_log_fatal, vha, 0x0051, 3187 "PCI data struct not found pcir_adr=%x.\n", pcids); 3188 ret = QLA_FUNCTION_FAILED; 3189 break; 3190 } 3191 3192 /* Read version */ 3193 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 3194 switch (code_type) { 3195 case ROM_CODE_TYPE_BIOS: 3196 /* Intel x86, PC-AT compatible. */ 3197 ha->bios_revision[0] = 3198 qla2x00_read_flash_byte(ha, pcids + 0x12); 3199 ha->bios_revision[1] = 3200 qla2x00_read_flash_byte(ha, pcids + 0x13); 3201 ql_dbg(ql_dbg_init, vha, 0x0052, 3202 "Read BIOS %d.%d.\n", 3203 ha->bios_revision[1], ha->bios_revision[0]); 3204 break; 3205 case ROM_CODE_TYPE_FCODE: 3206 /* Open Firmware standard for PCI (FCode). */ 3207 /* Eeeewww... */ 3208 qla2x00_get_fcode_version(ha, pcids); 3209 break; 3210 case ROM_CODE_TYPE_EFI: 3211 /* Extensible Firmware Interface (EFI). */ 3212 ha->efi_revision[0] = 3213 qla2x00_read_flash_byte(ha, pcids + 0x12); 3214 ha->efi_revision[1] = 3215 qla2x00_read_flash_byte(ha, pcids + 0x13); 3216 ql_dbg(ql_dbg_init, vha, 0x0053, 3217 "Read EFI %d.%d.\n", 3218 ha->efi_revision[1], ha->efi_revision[0]); 3219 break; 3220 default: 3221 ql_log(ql_log_warn, vha, 0x0054, 3222 "Unrecognized code type %x at pcids %x.\n", 3223 code_type, pcids); 3224 break; 3225 } 3226 3227 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 3228 3229 /* Locate next PCI expansion ROM. */ 3230 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 3231 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 3232 } while (!last_image); 3233 3234 if (IS_QLA2322(ha)) { 3235 /* Read firmware image information. */ 3236 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3237 dbyte = mbuf; 3238 memset(dbyte, 0, 8); 3239 dcode = (uint16_t *)dbyte; 3240 3241 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, 3242 8); 3243 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a, 3244 "Dumping fw " 3245 "ver from flash:.\n"); 3246 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b, 3247 dbyte, 32); 3248 3249 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 3250 dcode[2] == 0xffff && dcode[3] == 0xffff) || 3251 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 3252 dcode[3] == 0)) { 3253 ql_log(ql_log_warn, vha, 0x0057, 3254 "Unrecognized fw revision at %x.\n", 3255 ha->flt_region_fw * 4); 3256 } else { 3257 /* values are in big endian */ 3258 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 3259 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 3260 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 3261 ql_dbg(ql_dbg_init, vha, 0x0058, 3262 "FW Version: " 3263 "%d.%d.%d.\n", ha->fw_revision[0], 3264 ha->fw_revision[1], ha->fw_revision[2]); 3265 } 3266 } 3267 3268 qla2x00_flash_disable(ha); 3269 3270 return ret; 3271 } 3272 3273 int 3274 qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3275 { 3276 int ret = QLA_SUCCESS; 3277 uint32_t pcihdr, pcids; 3278 uint32_t *dcode = mbuf; 3279 uint8_t *bcode = mbuf; 3280 uint8_t code_type, last_image; 3281 struct qla_hw_data *ha = vha->hw; 3282 3283 if (!mbuf) 3284 return QLA_FUNCTION_FAILED; 3285 3286 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3287 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3288 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3289 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3290 3291 /* Begin with first PCI expansion ROM header. */ 3292 pcihdr = ha->flt_region_boot << 2; 3293 last_image = 1; 3294 do { 3295 /* Verify PCI expansion ROM header. */ 3296 ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4); 3297 bcode = mbuf + (pcihdr % 4); 3298 if (memcmp(bcode, "\x55\xaa", 2)) { 3299 /* No signature */ 3300 ql_log(ql_log_fatal, vha, 0x0154, 3301 "No matching ROM signature.\n"); 3302 ret = QLA_FUNCTION_FAILED; 3303 break; 3304 } 3305 3306 /* Locate PCI data structure. */ 3307 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3308 3309 ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4); 3310 bcode = mbuf + (pcihdr % 4); 3311 3312 /* Validate signature of PCI data structure. */ 3313 if (memcmp(bcode, "PCIR", 4)) { 3314 /* Incorrect header. */ 3315 ql_log(ql_log_fatal, vha, 0x0155, 3316 "PCI data struct not found pcir_adr=%x.\n", pcids); 3317 ret = QLA_FUNCTION_FAILED; 3318 break; 3319 } 3320 3321 /* Read version */ 3322 code_type = bcode[0x14]; 3323 switch (code_type) { 3324 case ROM_CODE_TYPE_BIOS: 3325 /* Intel x86, PC-AT compatible. */ 3326 ha->bios_revision[0] = bcode[0x12]; 3327 ha->bios_revision[1] = bcode[0x13]; 3328 ql_dbg(ql_dbg_init, vha, 0x0156, 3329 "Read BIOS %d.%d.\n", 3330 ha->bios_revision[1], ha->bios_revision[0]); 3331 break; 3332 case ROM_CODE_TYPE_FCODE: 3333 /* Open Firmware standard for PCI (FCode). */ 3334 ha->fcode_revision[0] = bcode[0x12]; 3335 ha->fcode_revision[1] = bcode[0x13]; 3336 ql_dbg(ql_dbg_init, vha, 0x0157, 3337 "Read FCODE %d.%d.\n", 3338 ha->fcode_revision[1], ha->fcode_revision[0]); 3339 break; 3340 case ROM_CODE_TYPE_EFI: 3341 /* Extensible Firmware Interface (EFI). */ 3342 ha->efi_revision[0] = bcode[0x12]; 3343 ha->efi_revision[1] = bcode[0x13]; 3344 ql_dbg(ql_dbg_init, vha, 0x0158, 3345 "Read EFI %d.%d.\n", 3346 ha->efi_revision[1], ha->efi_revision[0]); 3347 break; 3348 default: 3349 ql_log(ql_log_warn, vha, 0x0159, 3350 "Unrecognized code type %x at pcids %x.\n", 3351 code_type, pcids); 3352 break; 3353 } 3354 3355 last_image = bcode[0x15] & BIT_7; 3356 3357 /* Locate next PCI expansion ROM. */ 3358 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3359 } while (!last_image); 3360 3361 /* Read firmware image information. */ 3362 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3363 dcode = mbuf; 3364 ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20); 3365 bcode = mbuf + (pcihdr % 4); 3366 3367 /* Validate signature of PCI data structure. */ 3368 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 && 3369 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) { 3370 ha->fw_revision[0] = bcode[0x4]; 3371 ha->fw_revision[1] = bcode[0x5]; 3372 ha->fw_revision[2] = bcode[0x6]; 3373 ql_dbg(ql_dbg_init, vha, 0x0153, 3374 "Firmware revision %d.%d.%d\n", 3375 ha->fw_revision[0], ha->fw_revision[1], 3376 ha->fw_revision[2]); 3377 } 3378 3379 return ret; 3380 } 3381 3382 int 3383 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3384 { 3385 int ret = QLA_SUCCESS; 3386 uint32_t pcihdr = 0, pcids = 0; 3387 uint32_t *dcode = mbuf; 3388 uint8_t *bcode = mbuf; 3389 uint8_t code_type, last_image; 3390 int i; 3391 struct qla_hw_data *ha = vha->hw; 3392 uint32_t faddr = 0; 3393 struct active_regions active_regions = { }; 3394 3395 if (IS_P3P_TYPE(ha)) 3396 return ret; 3397 3398 if (!mbuf) 3399 return QLA_FUNCTION_FAILED; 3400 3401 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3402 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3403 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3404 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3405 3406 pcihdr = ha->flt_region_boot << 2; 3407 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3408 qla27xx_get_active_image(vha, &active_regions); 3409 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) { 3410 pcihdr = ha->flt_region_boot_sec << 2; 3411 } 3412 } 3413 3414 do { 3415 /* Verify PCI expansion ROM header. */ 3416 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 3417 bcode = mbuf + (pcihdr % 4); 3418 if (memcmp(bcode, "\x55\xaa", 2)) { 3419 /* No signature */ 3420 ql_log(ql_log_fatal, vha, 0x0059, 3421 "No matching ROM signature.\n"); 3422 ret = QLA_FUNCTION_FAILED; 3423 break; 3424 } 3425 3426 /* Locate PCI data structure. */ 3427 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3428 3429 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 3430 bcode = mbuf + (pcihdr % 4); 3431 3432 /* Validate signature of PCI data structure. */ 3433 if (memcmp(bcode, "PCIR", 4)) { 3434 /* Incorrect header. */ 3435 ql_log(ql_log_fatal, vha, 0x005a, 3436 "PCI data struct not found pcir_adr=%x.\n", pcids); 3437 ql_dump_buffer(ql_dbg_init, vha, 0x0059, dcode, 32); 3438 ret = QLA_FUNCTION_FAILED; 3439 break; 3440 } 3441 3442 /* Read version */ 3443 code_type = bcode[0x14]; 3444 switch (code_type) { 3445 case ROM_CODE_TYPE_BIOS: 3446 /* Intel x86, PC-AT compatible. */ 3447 ha->bios_revision[0] = bcode[0x12]; 3448 ha->bios_revision[1] = bcode[0x13]; 3449 ql_dbg(ql_dbg_init, vha, 0x005b, 3450 "Read BIOS %d.%d.\n", 3451 ha->bios_revision[1], ha->bios_revision[0]); 3452 break; 3453 case ROM_CODE_TYPE_FCODE: 3454 /* Open Firmware standard for PCI (FCode). */ 3455 ha->fcode_revision[0] = bcode[0x12]; 3456 ha->fcode_revision[1] = bcode[0x13]; 3457 ql_dbg(ql_dbg_init, vha, 0x005c, 3458 "Read FCODE %d.%d.\n", 3459 ha->fcode_revision[1], ha->fcode_revision[0]); 3460 break; 3461 case ROM_CODE_TYPE_EFI: 3462 /* Extensible Firmware Interface (EFI). */ 3463 ha->efi_revision[0] = bcode[0x12]; 3464 ha->efi_revision[1] = bcode[0x13]; 3465 ql_dbg(ql_dbg_init, vha, 0x005d, 3466 "Read EFI %d.%d.\n", 3467 ha->efi_revision[1], ha->efi_revision[0]); 3468 break; 3469 default: 3470 ql_log(ql_log_warn, vha, 0x005e, 3471 "Unrecognized code type %x at pcids %x.\n", 3472 code_type, pcids); 3473 break; 3474 } 3475 3476 last_image = bcode[0x15] & BIT_7; 3477 3478 /* Locate next PCI expansion ROM. */ 3479 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3480 } while (!last_image); 3481 3482 /* Read firmware image information. */ 3483 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3484 faddr = ha->flt_region_fw; 3485 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3486 qla27xx_get_active_image(vha, &active_regions); 3487 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) 3488 faddr = ha->flt_region_fw_sec; 3489 } 3490 3491 qla24xx_read_flash_data(vha, dcode, faddr, 8); 3492 if (qla24xx_risc_firmware_invalid(dcode)) { 3493 ql_log(ql_log_warn, vha, 0x005f, 3494 "Unrecognized fw revision at %x.\n", 3495 ha->flt_region_fw * 4); 3496 ql_dump_buffer(ql_dbg_init, vha, 0x005f, dcode, 32); 3497 } else { 3498 for (i = 0; i < 4; i++) 3499 ha->fw_revision[i] = be32_to_cpu(dcode[4+i]); 3500 ql_dbg(ql_dbg_init, vha, 0x0060, 3501 "Firmware revision (flash) %u.%u.%u (%x).\n", 3502 ha->fw_revision[0], ha->fw_revision[1], 3503 ha->fw_revision[2], ha->fw_revision[3]); 3504 } 3505 3506 /* Check for golden firmware and get version if available */ 3507 if (!IS_QLA81XX(ha)) { 3508 /* Golden firmware is not present in non 81XX adapters */ 3509 return ret; 3510 } 3511 3512 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); 3513 faddr = ha->flt_region_gold_fw; 3514 qla24xx_read_flash_data(vha, (void *)dcode, ha->flt_region_gold_fw, 8); 3515 if (qla24xx_risc_firmware_invalid(dcode)) { 3516 ql_log(ql_log_warn, vha, 0x0056, 3517 "Unrecognized golden fw at %#x.\n", faddr); 3518 ql_dump_buffer(ql_dbg_init, vha, 0x0056, dcode, 32); 3519 return ret; 3520 } 3521 3522 for (i = 0; i < 4; i++) 3523 ha->gold_fw_version[i] = be32_to_cpu(dcode[4+i]); 3524 3525 return ret; 3526 } 3527 3528 static int 3529 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) 3530 { 3531 if (pos >= end || *pos != 0x82) 3532 return 0; 3533 3534 pos += 3 + pos[1]; 3535 if (pos >= end || *pos != 0x90) 3536 return 0; 3537 3538 pos += 3 + pos[1]; 3539 if (pos >= end || *pos != 0x78) 3540 return 0; 3541 3542 return 1; 3543 } 3544 3545 int 3546 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) 3547 { 3548 struct qla_hw_data *ha = vha->hw; 3549 uint8_t *pos = ha->vpd; 3550 uint8_t *end = pos + ha->vpd_size; 3551 int len = 0; 3552 3553 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) 3554 return 0; 3555 3556 while (pos < end && *pos != 0x78) { 3557 len = (*pos == 0x82) ? pos[1] : pos[2]; 3558 3559 if (!strncmp(pos, key, strlen(key))) 3560 break; 3561 3562 if (*pos != 0x90 && *pos != 0x91) 3563 pos += len; 3564 3565 pos += 3; 3566 } 3567 3568 if (pos < end - len && *pos != 0x78) 3569 return scnprintf(str, size, "%.*s", len, pos + 3); 3570 3571 return 0; 3572 } 3573 3574 int 3575 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha) 3576 { 3577 int len, max_len; 3578 uint32_t fcp_prio_addr; 3579 struct qla_hw_data *ha = vha->hw; 3580 3581 if (!ha->fcp_prio_cfg) { 3582 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); 3583 if (!ha->fcp_prio_cfg) { 3584 ql_log(ql_log_warn, vha, 0x00d5, 3585 "Unable to allocate memory for fcp priority data (%x).\n", 3586 FCP_PRIO_CFG_SIZE); 3587 return QLA_FUNCTION_FAILED; 3588 } 3589 } 3590 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); 3591 3592 fcp_prio_addr = ha->flt_region_fcp_prio; 3593 3594 /* first read the fcp priority data header from flash */ 3595 ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg, 3596 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE); 3597 3598 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0)) 3599 goto fail; 3600 3601 /* read remaining FCP CMD config data from flash */ 3602 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2); 3603 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE; 3604 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; 3605 3606 ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0], 3607 fcp_prio_addr << 2, (len < max_len ? len : max_len)); 3608 3609 /* revalidate the entire FCP priority config data, including entries */ 3610 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1)) 3611 goto fail; 3612 3613 ha->flags.fcp_prio_enabled = 1; 3614 return QLA_SUCCESS; 3615 fail: 3616 vfree(ha->fcp_prio_cfg); 3617 ha->fcp_prio_cfg = NULL; 3618 return QLA_FUNCTION_FAILED; 3619 } 3620