1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2008 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 #include <linux/vmalloc.h> 11 #include <asm/uaccess.h> 12 13 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t); 14 static void qla2x00_nv_deselect(scsi_qla_host_t *); 15 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t); 16 17 /* 18 * NVRAM support routines 19 */ 20 21 /** 22 * qla2x00_lock_nvram_access() - 23 * @ha: HA context 24 */ 25 static void 26 qla2x00_lock_nvram_access(scsi_qla_host_t *ha) 27 { 28 uint16_t data; 29 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 30 31 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 32 data = RD_REG_WORD(®->nvram); 33 while (data & NVR_BUSY) { 34 udelay(100); 35 data = RD_REG_WORD(®->nvram); 36 } 37 38 /* Lock resource */ 39 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 40 RD_REG_WORD(®->u.isp2300.host_semaphore); 41 udelay(5); 42 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 43 while ((data & BIT_0) == 0) { 44 /* Lock failed */ 45 udelay(100); 46 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 47 RD_REG_WORD(®->u.isp2300.host_semaphore); 48 udelay(5); 49 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 50 } 51 } 52 } 53 54 /** 55 * qla2x00_unlock_nvram_access() - 56 * @ha: HA context 57 */ 58 static void 59 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha) 60 { 61 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 62 63 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 64 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); 65 RD_REG_WORD(®->u.isp2300.host_semaphore); 66 } 67 } 68 69 /** 70 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 71 * request routine to get the word from NVRAM. 72 * @ha: HA context 73 * @addr: Address in NVRAM to read 74 * 75 * Returns the word read from nvram @addr. 76 */ 77 static uint16_t 78 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr) 79 { 80 uint16_t data; 81 uint32_t nv_cmd; 82 83 nv_cmd = addr << 16; 84 nv_cmd |= NV_READ_OP; 85 data = qla2x00_nvram_request(ha, nv_cmd); 86 87 return (data); 88 } 89 90 /** 91 * qla2x00_write_nvram_word() - Write NVRAM data. 92 * @ha: HA context 93 * @addr: Address in NVRAM to write 94 * @data: word to program 95 */ 96 static void 97 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data) 98 { 99 int count; 100 uint16_t word; 101 uint32_t nv_cmd, wait_cnt; 102 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 103 104 qla2x00_nv_write(ha, NVR_DATA_OUT); 105 qla2x00_nv_write(ha, 0); 106 qla2x00_nv_write(ha, 0); 107 108 for (word = 0; word < 8; word++) 109 qla2x00_nv_write(ha, NVR_DATA_OUT); 110 111 qla2x00_nv_deselect(ha); 112 113 /* Write data */ 114 nv_cmd = (addr << 16) | NV_WRITE_OP; 115 nv_cmd |= data; 116 nv_cmd <<= 5; 117 for (count = 0; count < 27; count++) { 118 if (nv_cmd & BIT_31) 119 qla2x00_nv_write(ha, NVR_DATA_OUT); 120 else 121 qla2x00_nv_write(ha, 0); 122 123 nv_cmd <<= 1; 124 } 125 126 qla2x00_nv_deselect(ha); 127 128 /* Wait for NVRAM to become ready */ 129 WRT_REG_WORD(®->nvram, NVR_SELECT); 130 RD_REG_WORD(®->nvram); /* PCI Posting. */ 131 wait_cnt = NVR_WAIT_CNT; 132 do { 133 if (!--wait_cnt) { 134 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n", 135 __func__, ha->host_no)); 136 break; 137 } 138 NVRAM_DELAY(); 139 word = RD_REG_WORD(®->nvram); 140 } while ((word & NVR_DATA_IN) == 0); 141 142 qla2x00_nv_deselect(ha); 143 144 /* Disable writes */ 145 qla2x00_nv_write(ha, NVR_DATA_OUT); 146 for (count = 0; count < 10; count++) 147 qla2x00_nv_write(ha, 0); 148 149 qla2x00_nv_deselect(ha); 150 } 151 152 static int 153 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data, 154 uint32_t tmo) 155 { 156 int ret, count; 157 uint16_t word; 158 uint32_t nv_cmd; 159 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 160 161 ret = QLA_SUCCESS; 162 163 qla2x00_nv_write(ha, NVR_DATA_OUT); 164 qla2x00_nv_write(ha, 0); 165 qla2x00_nv_write(ha, 0); 166 167 for (word = 0; word < 8; word++) 168 qla2x00_nv_write(ha, NVR_DATA_OUT); 169 170 qla2x00_nv_deselect(ha); 171 172 /* Write data */ 173 nv_cmd = (addr << 16) | NV_WRITE_OP; 174 nv_cmd |= data; 175 nv_cmd <<= 5; 176 for (count = 0; count < 27; count++) { 177 if (nv_cmd & BIT_31) 178 qla2x00_nv_write(ha, NVR_DATA_OUT); 179 else 180 qla2x00_nv_write(ha, 0); 181 182 nv_cmd <<= 1; 183 } 184 185 qla2x00_nv_deselect(ha); 186 187 /* Wait for NVRAM to become ready */ 188 WRT_REG_WORD(®->nvram, NVR_SELECT); 189 RD_REG_WORD(®->nvram); /* PCI Posting. */ 190 do { 191 NVRAM_DELAY(); 192 word = RD_REG_WORD(®->nvram); 193 if (!--tmo) { 194 ret = QLA_FUNCTION_FAILED; 195 break; 196 } 197 } while ((word & NVR_DATA_IN) == 0); 198 199 qla2x00_nv_deselect(ha); 200 201 /* Disable writes */ 202 qla2x00_nv_write(ha, NVR_DATA_OUT); 203 for (count = 0; count < 10; count++) 204 qla2x00_nv_write(ha, 0); 205 206 qla2x00_nv_deselect(ha); 207 208 return ret; 209 } 210 211 /** 212 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 213 * NVRAM. 214 * @ha: HA context 215 * @nv_cmd: NVRAM command 216 * 217 * Bit definitions for NVRAM command: 218 * 219 * Bit 26 = start bit 220 * Bit 25, 24 = opcode 221 * Bit 23-16 = address 222 * Bit 15-0 = write data 223 * 224 * Returns the word read from nvram @addr. 225 */ 226 static uint16_t 227 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd) 228 { 229 uint8_t cnt; 230 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 231 uint16_t data = 0; 232 uint16_t reg_data; 233 234 /* Send command to NVRAM. */ 235 nv_cmd <<= 5; 236 for (cnt = 0; cnt < 11; cnt++) { 237 if (nv_cmd & BIT_31) 238 qla2x00_nv_write(ha, NVR_DATA_OUT); 239 else 240 qla2x00_nv_write(ha, 0); 241 nv_cmd <<= 1; 242 } 243 244 /* Read data from NVRAM. */ 245 for (cnt = 0; cnt < 16; cnt++) { 246 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); 247 RD_REG_WORD(®->nvram); /* PCI Posting. */ 248 NVRAM_DELAY(); 249 data <<= 1; 250 reg_data = RD_REG_WORD(®->nvram); 251 if (reg_data & NVR_DATA_IN) 252 data |= BIT_0; 253 WRT_REG_WORD(®->nvram, NVR_SELECT); 254 RD_REG_WORD(®->nvram); /* PCI Posting. */ 255 NVRAM_DELAY(); 256 } 257 258 /* Deselect chip. */ 259 WRT_REG_WORD(®->nvram, NVR_DESELECT); 260 RD_REG_WORD(®->nvram); /* PCI Posting. */ 261 NVRAM_DELAY(); 262 263 return (data); 264 } 265 266 /** 267 * qla2x00_nv_write() - Clean NVRAM operations. 268 * @ha: HA context 269 */ 270 static void 271 qla2x00_nv_deselect(scsi_qla_host_t *ha) 272 { 273 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 274 275 WRT_REG_WORD(®->nvram, NVR_DESELECT); 276 RD_REG_WORD(®->nvram); /* PCI Posting. */ 277 NVRAM_DELAY(); 278 } 279 280 /** 281 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 282 * @ha: HA context 283 * @data: Serial interface selector 284 */ 285 static void 286 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data) 287 { 288 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 289 290 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 291 RD_REG_WORD(®->nvram); /* PCI Posting. */ 292 NVRAM_DELAY(); 293 WRT_REG_WORD(®->nvram, data | NVR_SELECT| NVR_CLOCK | 294 NVR_WRT_ENABLE); 295 RD_REG_WORD(®->nvram); /* PCI Posting. */ 296 NVRAM_DELAY(); 297 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 298 RD_REG_WORD(®->nvram); /* PCI Posting. */ 299 NVRAM_DELAY(); 300 } 301 302 /** 303 * qla2x00_clear_nvram_protection() - 304 * @ha: HA context 305 */ 306 static int 307 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha) 308 { 309 int ret, stat; 310 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 311 uint32_t word, wait_cnt; 312 uint16_t wprot, wprot_old; 313 314 /* Clear NVRAM write protection. */ 315 ret = QLA_FUNCTION_FAILED; 316 317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 319 __constant_cpu_to_le16(0x1234), 100000); 320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 321 if (stat != QLA_SUCCESS || wprot != 0x1234) { 322 /* Write enable. */ 323 qla2x00_nv_write(ha, NVR_DATA_OUT); 324 qla2x00_nv_write(ha, 0); 325 qla2x00_nv_write(ha, 0); 326 for (word = 0; word < 8; word++) 327 qla2x00_nv_write(ha, NVR_DATA_OUT); 328 329 qla2x00_nv_deselect(ha); 330 331 /* Enable protection register. */ 332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 333 qla2x00_nv_write(ha, NVR_PR_ENABLE); 334 qla2x00_nv_write(ha, NVR_PR_ENABLE); 335 for (word = 0; word < 8; word++) 336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 337 338 qla2x00_nv_deselect(ha); 339 340 /* Clear protection register (ffff is cleared). */ 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 344 for (word = 0; word < 8; word++) 345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 346 347 qla2x00_nv_deselect(ha); 348 349 /* Wait for NVRAM to become ready. */ 350 WRT_REG_WORD(®->nvram, NVR_SELECT); 351 RD_REG_WORD(®->nvram); /* PCI Posting. */ 352 wait_cnt = NVR_WAIT_CNT; 353 do { 354 if (!--wait_cnt) { 355 DEBUG9_10(printk("%s(%ld): NVRAM didn't go " 356 "ready...\n", __func__, 357 ha->host_no)); 358 break; 359 } 360 NVRAM_DELAY(); 361 word = RD_REG_WORD(®->nvram); 362 } while ((word & NVR_DATA_IN) == 0); 363 364 if (wait_cnt) 365 ret = QLA_SUCCESS; 366 } else 367 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 368 369 return ret; 370 } 371 372 static void 373 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat) 374 { 375 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 376 uint32_t word, wait_cnt; 377 378 if (stat != QLA_SUCCESS) 379 return; 380 381 /* Set NVRAM write protection. */ 382 /* Write enable. */ 383 qla2x00_nv_write(ha, NVR_DATA_OUT); 384 qla2x00_nv_write(ha, 0); 385 qla2x00_nv_write(ha, 0); 386 for (word = 0; word < 8; word++) 387 qla2x00_nv_write(ha, NVR_DATA_OUT); 388 389 qla2x00_nv_deselect(ha); 390 391 /* Enable protection register. */ 392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 393 qla2x00_nv_write(ha, NVR_PR_ENABLE); 394 qla2x00_nv_write(ha, NVR_PR_ENABLE); 395 for (word = 0; word < 8; word++) 396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 397 398 qla2x00_nv_deselect(ha); 399 400 /* Enable protection register. */ 401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 402 qla2x00_nv_write(ha, NVR_PR_ENABLE); 403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 404 for (word = 0; word < 8; word++) 405 qla2x00_nv_write(ha, NVR_PR_ENABLE); 406 407 qla2x00_nv_deselect(ha); 408 409 /* Wait for NVRAM to become ready. */ 410 WRT_REG_WORD(®->nvram, NVR_SELECT); 411 RD_REG_WORD(®->nvram); /* PCI Posting. */ 412 wait_cnt = NVR_WAIT_CNT; 413 do { 414 if (!--wait_cnt) { 415 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n", 416 __func__, ha->host_no)); 417 break; 418 } 419 NVRAM_DELAY(); 420 word = RD_REG_WORD(®->nvram); 421 } while ((word & NVR_DATA_IN) == 0); 422 } 423 424 425 /*****************************************************************************/ 426 /* Flash Manipulation Routines */ 427 /*****************************************************************************/ 428 429 #define OPTROM_BURST_SIZE 0x1000 430 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 431 432 static inline uint32_t 433 flash_conf_to_access_addr(uint32_t faddr) 434 { 435 return FARX_ACCESS_FLASH_CONF | faddr; 436 } 437 438 static inline uint32_t 439 flash_data_to_access_addr(uint32_t faddr) 440 { 441 return FARX_ACCESS_FLASH_DATA | faddr; 442 } 443 444 static inline uint32_t 445 nvram_conf_to_access_addr(uint32_t naddr) 446 { 447 return FARX_ACCESS_NVRAM_CONF | naddr; 448 } 449 450 static inline uint32_t 451 nvram_data_to_access_addr(uint32_t naddr) 452 { 453 return FARX_ACCESS_NVRAM_DATA | naddr; 454 } 455 456 static uint32_t 457 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr) 458 { 459 int rval; 460 uint32_t cnt, data; 461 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 462 463 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); 464 /* Wait for READ cycle to complete. */ 465 rval = QLA_SUCCESS; 466 for (cnt = 3000; 467 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && 468 rval == QLA_SUCCESS; cnt--) { 469 if (cnt) 470 udelay(10); 471 else 472 rval = QLA_FUNCTION_TIMEOUT; 473 cond_resched(); 474 } 475 476 /* TODO: What happens if we time out? */ 477 data = 0xDEADDEAD; 478 if (rval == QLA_SUCCESS) 479 data = RD_REG_DWORD(®->flash_data); 480 481 return data; 482 } 483 484 uint32_t * 485 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, 486 uint32_t dwords) 487 { 488 uint32_t i; 489 490 /* Dword reads to flash. */ 491 for (i = 0; i < dwords; i++, faddr++) 492 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 493 flash_data_to_access_addr(faddr))); 494 495 return dwptr; 496 } 497 498 static int 499 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data) 500 { 501 int rval; 502 uint32_t cnt; 503 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 504 505 WRT_REG_DWORD(®->flash_data, data); 506 RD_REG_DWORD(®->flash_data); /* PCI Posting. */ 507 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); 508 /* Wait for Write cycle to complete. */ 509 rval = QLA_SUCCESS; 510 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && 511 rval == QLA_SUCCESS; cnt--) { 512 if (cnt) 513 udelay(10); 514 else 515 rval = QLA_FUNCTION_TIMEOUT; 516 cond_resched(); 517 } 518 return rval; 519 } 520 521 static void 522 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id, 523 uint8_t *flash_id) 524 { 525 uint32_t ids; 526 527 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab)); 528 *man_id = LSB(ids); 529 *flash_id = MSB(ids); 530 531 /* Check if man_id and flash_id are valid. */ 532 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 533 /* Read information using 0x9f opcode 534 * Device ID, Mfg ID would be read in the format: 535 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 536 * Example: ATMEL 0x00 01 45 1F 537 * Extract MFG and Dev ID from last two bytes. 538 */ 539 ids = qla24xx_read_flash_dword(ha, 540 flash_data_to_access_addr(0xd009f)); 541 *man_id = LSB(ids); 542 *flash_id = MSB(ids); 543 } 544 } 545 546 static int 547 qla2xxx_find_flt_start(scsi_qla_host_t *ha, uint32_t *start) 548 { 549 const char *loc, *locations[] = { "DEF", "PCI" }; 550 uint32_t pcihdr, pcids; 551 uint32_t *dcode; 552 uint8_t *buf, *bcode, last_image; 553 uint16_t cnt, chksum, *wptr; 554 struct qla_flt_location *fltl; 555 556 /* 557 * FLT-location structure resides after the last PCI region. 558 */ 559 560 /* Begin with sane defaults. */ 561 loc = locations[0]; 562 *start = IS_QLA24XX_TYPE(ha) ? FA_FLASH_LAYOUT_ADDR_24: 563 FA_FLASH_LAYOUT_ADDR; 564 565 /* Begin with first PCI expansion ROM header. */ 566 buf = (uint8_t *)ha->request_ring; 567 dcode = (uint32_t *)ha->request_ring; 568 pcihdr = 0; 569 last_image = 1; 570 do { 571 /* Verify PCI expansion ROM header. */ 572 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20); 573 bcode = buf + (pcihdr % 4); 574 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) 575 goto end; 576 577 /* Locate PCI data structure. */ 578 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 579 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20); 580 bcode = buf + (pcihdr % 4); 581 582 /* Validate signature of PCI data structure. */ 583 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 584 bcode[0x2] != 'I' || bcode[0x3] != 'R') 585 goto end; 586 587 last_image = bcode[0x15] & BIT_7; 588 589 /* Locate next PCI expansion ROM. */ 590 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 591 } while (!last_image); 592 593 /* Now verify FLT-location structure. */ 594 fltl = (struct qla_flt_location *)ha->request_ring; 595 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 596 sizeof(struct qla_flt_location) >> 2); 597 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' || 598 fltl->sig[2] != 'L' || fltl->sig[3] != 'T') 599 goto end; 600 601 wptr = (uint16_t *)ha->request_ring; 602 cnt = sizeof(struct qla_flt_location) >> 1; 603 for (chksum = 0; cnt; cnt--) 604 chksum += le16_to_cpu(*wptr++); 605 if (chksum) { 606 qla_printk(KERN_ERR, ha, 607 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); 608 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location)); 609 return QLA_FUNCTION_FAILED; 610 } 611 612 /* Good data. Use specified location. */ 613 loc = locations[1]; 614 *start = le16_to_cpu(fltl->start_hi) << 16 | 615 le16_to_cpu(fltl->start_lo); 616 end: 617 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 618 return QLA_SUCCESS; 619 } 620 621 static void 622 qla2xxx_get_flt_info(scsi_qla_host_t *ha, uint32_t flt_addr) 623 { 624 const char *loc, *locations[] = { "DEF", "FLT" }; 625 uint16_t *wptr; 626 uint16_t cnt, chksum; 627 uint32_t start; 628 struct qla_flt_header *flt; 629 struct qla_flt_region *region; 630 631 ha->flt_region_flt = flt_addr; 632 wptr = (uint16_t *)ha->request_ring; 633 flt = (struct qla_flt_header *)ha->request_ring; 634 region = (struct qla_flt_region *)&flt[1]; 635 ha->isp_ops->read_optrom(ha, (uint8_t *)ha->request_ring, 636 flt_addr << 2, OPTROM_BURST_SIZE); 637 if (*wptr == __constant_cpu_to_le16(0xffff)) 638 goto no_flash_data; 639 if (flt->version != __constant_cpu_to_le16(1)) { 640 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: " 641 "version=0x%x length=0x%x checksum=0x%x.\n", 642 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 643 le16_to_cpu(flt->checksum))); 644 goto no_flash_data; 645 } 646 647 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 648 for (chksum = 0; cnt; cnt--) 649 chksum += le16_to_cpu(*wptr++); 650 if (chksum) { 651 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 652 "version=0x%x length=0x%x checksum=0x%x.\n", 653 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 654 chksum)); 655 goto no_flash_data; 656 } 657 658 loc = locations[1]; 659 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 660 for ( ; cnt; cnt--, region++) { 661 /* Store addresses as DWORD offsets. */ 662 start = le32_to_cpu(region->start) >> 2; 663 664 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 665 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 666 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 667 668 switch (le32_to_cpu(region->code)) { 669 case FLT_REG_FW: 670 ha->flt_region_fw = start; 671 break; 672 case FLT_REG_BOOT_CODE: 673 ha->flt_region_boot = start; 674 break; 675 case FLT_REG_VPD_0: 676 ha->flt_region_vpd_nvram = start; 677 break; 678 case FLT_REG_FDT: 679 ha->flt_region_fdt = start; 680 break; 681 case FLT_REG_HW_EVENT_0: 682 if (!PCI_FUNC(ha->pdev->devfn)) 683 ha->flt_region_hw_event = start; 684 break; 685 case FLT_REG_HW_EVENT_1: 686 if (PCI_FUNC(ha->pdev->devfn)) 687 ha->flt_region_hw_event = start; 688 break; 689 case FLT_REG_NPIV_CONF_0: 690 if (!PCI_FUNC(ha->pdev->devfn)) 691 ha->flt_region_npiv_conf = start; 692 break; 693 case FLT_REG_NPIV_CONF_1: 694 if (PCI_FUNC(ha->pdev->devfn)) 695 ha->flt_region_npiv_conf = start; 696 break; 697 } 698 } 699 goto done; 700 701 no_flash_data: 702 /* Use hardcoded defaults. */ 703 loc = locations[0]; 704 ha->flt_region_fw = FA_RISC_CODE_ADDR; 705 ha->flt_region_boot = FA_BOOT_CODE_ADDR; 706 ha->flt_region_vpd_nvram = FA_VPD_NVRAM_ADDR; 707 ha->flt_region_fdt = IS_QLA24XX_TYPE(ha) ? FA_FLASH_DESCR_ADDR_24: 708 FA_FLASH_DESCR_ADDR; 709 ha->flt_region_hw_event = !PCI_FUNC(ha->pdev->devfn) ? 710 FA_HW_EVENT0_ADDR: FA_HW_EVENT1_ADDR; 711 ha->flt_region_npiv_conf = !PCI_FUNC(ha->pdev->devfn) ? 712 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF0_ADDR_24: FA_NPIV_CONF0_ADDR): 713 (IS_QLA24XX_TYPE(ha) ? FA_NPIV_CONF1_ADDR_24: FA_NPIV_CONF1_ADDR); 714 done: 715 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x " 716 "vpd_nvram=0x%x fdt=0x%x flt=0x%x hwe=0x%x npiv=0x%x.\n", loc, 717 ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram, 718 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_hw_event, 719 ha->flt_region_npiv_conf)); 720 } 721 722 static void 723 qla2xxx_get_fdt_info(scsi_qla_host_t *ha) 724 { 725 #define FLASH_BLK_SIZE_32K 0x8000 726 #define FLASH_BLK_SIZE_64K 0x10000 727 const char *loc, *locations[] = { "MID", "FDT" }; 728 uint16_t cnt, chksum; 729 uint16_t *wptr; 730 struct qla_fdt_layout *fdt; 731 uint8_t man_id, flash_id; 732 uint16_t mid, fid; 733 734 wptr = (uint16_t *)ha->request_ring; 735 fdt = (struct qla_fdt_layout *)ha->request_ring; 736 ha->isp_ops->read_optrom(ha, (uint8_t *)ha->request_ring, 737 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE); 738 if (*wptr == __constant_cpu_to_le16(0xffff)) 739 goto no_flash_data; 740 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 741 fdt->sig[3] != 'D') 742 goto no_flash_data; 743 744 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 745 cnt++) 746 chksum += le16_to_cpu(*wptr++); 747 if (chksum) { 748 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 749 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 750 le16_to_cpu(fdt->version))); 751 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt))); 752 goto no_flash_data; 753 } 754 755 loc = locations[1]; 756 mid = le16_to_cpu(fdt->man_id); 757 fid = le16_to_cpu(fdt->id); 758 ha->fdt_odd_index = mid == 0x1f; 759 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 760 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd); 761 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 762 if (fdt->unprotect_sec_cmd) { 763 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 | 764 fdt->unprotect_sec_cmd); 765 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 766 flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd): 767 flash_conf_to_access_addr(0x0336); 768 } 769 goto done; 770 no_flash_data: 771 loc = locations[0]; 772 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 773 mid = man_id; 774 fid = flash_id; 775 ha->fdt_wrt_disable = 0x9c; 776 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8); 777 switch (man_id) { 778 case 0xbf: /* STT flash. */ 779 if (flash_id == 0x8e) 780 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 781 else 782 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 783 784 if (flash_id == 0x80) 785 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352); 786 break; 787 case 0x13: /* ST M25P80. */ 788 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 789 break; 790 case 0x1f: /* Atmel 26DF081A. */ 791 ha->fdt_odd_index = 1; 792 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 793 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320); 794 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339); 795 ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336); 796 break; 797 default: 798 /* Default to 64 kb sector size. */ 799 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 800 break; 801 } 802 done: 803 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 804 "pro=%x upro=%x idx=%d wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 805 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, 806 ha->fdt_unprotect_sec_cmd, ha->fdt_odd_index, ha->fdt_wrt_disable, 807 ha->fdt_block_size)); 808 } 809 810 int 811 qla2xxx_get_flash_info(scsi_qla_host_t *ha) 812 { 813 int ret; 814 uint32_t flt_addr; 815 816 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 817 return QLA_SUCCESS; 818 819 ret = qla2xxx_find_flt_start(ha, &flt_addr); 820 if (ret != QLA_SUCCESS) 821 return ret; 822 823 qla2xxx_get_flt_info(ha, flt_addr); 824 qla2xxx_get_fdt_info(ha); 825 826 return QLA_SUCCESS; 827 } 828 829 void 830 qla2xxx_flash_npiv_conf(scsi_qla_host_t *ha) 831 { 832 #define NPIV_CONFIG_SIZE (16*1024) 833 void *data; 834 uint16_t *wptr; 835 uint16_t cnt, chksum; 836 struct qla_npiv_header hdr; 837 struct qla_npiv_entry *entry; 838 839 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha)) 840 return; 841 842 ha->isp_ops->read_optrom(ha, (uint8_t *)&hdr, 843 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header)); 844 if (hdr.version == __constant_cpu_to_le16(0xffff)) 845 return; 846 if (hdr.version != __constant_cpu_to_le16(1)) { 847 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config " 848 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 849 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 850 le16_to_cpu(hdr.checksum))); 851 return; 852 } 853 854 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); 855 if (!data) { 856 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to " 857 "allocate memory.\n")); 858 return; 859 } 860 861 ha->isp_ops->read_optrom(ha, (uint8_t *)data, 862 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE); 863 864 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) * 865 sizeof(struct qla_npiv_entry)) >> 1; 866 for (wptr = data, chksum = 0; cnt; cnt--) 867 chksum += le16_to_cpu(*wptr++); 868 if (chksum) { 869 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config " 870 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 871 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 872 chksum)); 873 goto done; 874 } 875 876 entry = data + sizeof(struct qla_npiv_header); 877 cnt = le16_to_cpu(hdr.entries); 878 for ( ; cnt; cnt--, entry++) { 879 uint16_t flags; 880 struct fc_vport_identifiers vid; 881 struct fc_vport *vport; 882 883 flags = le16_to_cpu(entry->flags); 884 if (flags == 0xffff) 885 continue; 886 if ((flags & BIT_0) == 0) 887 continue; 888 889 memset(&vid, 0, sizeof(vid)); 890 vid.roles = FC_PORT_ROLE_FCP_INITIATOR; 891 vid.vport_type = FC_PORTTYPE_NPIV; 892 vid.disable = false; 893 vid.port_name = wwn_to_u64(entry->port_name); 894 vid.node_name = wwn_to_u64(entry->node_name); 895 896 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx " 897 "wwnn=%llx vf_id=0x%x qos=0x%x.\n", cnt, 898 (unsigned long long)vid.port_name, 899 (unsigned long long)vid.node_name, 900 le16_to_cpu(entry->vf_id), le16_to_cpu(entry->qos))); 901 902 vport = fc_vport_create(ha->host, 0, &vid); 903 if (!vport) 904 qla_printk(KERN_INFO, ha, "NPIV-Config: Failed to " 905 "create vport [%02x]: wwpn=%llx wwnn=%llx.\n", cnt, 906 (unsigned long long)vid.port_name, 907 (unsigned long long)vid.node_name); 908 } 909 done: 910 kfree(data); 911 } 912 913 static void 914 qla24xx_unprotect_flash(scsi_qla_host_t *ha) 915 { 916 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 917 918 /* Enable flash write. */ 919 WRT_REG_DWORD(®->ctrl_status, 920 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 921 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 922 923 if (!ha->fdt_wrt_disable) 924 return; 925 926 /* Disable flash write-protection. */ 927 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); 928 /* Some flash parts need an additional zero-write to clear bits.*/ 929 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0); 930 } 931 932 static void 933 qla24xx_protect_flash(scsi_qla_host_t *ha) 934 { 935 uint32_t cnt; 936 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 937 938 if (!ha->fdt_wrt_disable) 939 goto skip_wrt_protect; 940 941 /* Enable flash write-protection and wait for completion. */ 942 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 943 ha->fdt_wrt_disable); 944 for (cnt = 300; cnt && 945 qla24xx_read_flash_dword(ha, 946 flash_conf_to_access_addr(0x005)) & BIT_0; 947 cnt--) { 948 udelay(10); 949 } 950 951 skip_wrt_protect: 952 /* Disable flash write. */ 953 WRT_REG_DWORD(®->ctrl_status, 954 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 955 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 956 } 957 958 static int 959 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr, 960 uint32_t dwords) 961 { 962 int ret; 963 uint32_t liter, miter; 964 uint32_t sec_mask, rest_addr; 965 uint32_t fdata, findex; 966 dma_addr_t optrom_dma; 967 void *optrom = NULL; 968 uint32_t *s, *d; 969 970 ret = QLA_SUCCESS; 971 972 /* Prepare burst-capable write on supported ISPs. */ 973 if (IS_QLA25XX(ha) && !(faddr & 0xfff) && 974 dwords > OPTROM_BURST_DWORDS) { 975 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 976 &optrom_dma, GFP_KERNEL); 977 if (!optrom) { 978 qla_printk(KERN_DEBUG, ha, 979 "Unable to allocate memory for optrom burst write " 980 "(%x KB).\n", OPTROM_BURST_SIZE / 1024); 981 } 982 } 983 984 rest_addr = (ha->fdt_block_size >> 2) - 1; 985 sec_mask = 0x80000 - (ha->fdt_block_size >> 2); 986 987 qla24xx_unprotect_flash(ha); 988 989 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 990 if (ha->fdt_odd_index) { 991 findex = faddr << 2; 992 fdata = findex & sec_mask; 993 } else { 994 findex = faddr; 995 fdata = (findex & sec_mask) << 2; 996 } 997 998 /* Are we at the beginning of a sector? */ 999 if ((findex & rest_addr) == 0) { 1000 /* Do sector unprotect. */ 1001 if (ha->fdt_unprotect_sec_cmd) 1002 qla24xx_write_flash_dword(ha, 1003 ha->fdt_unprotect_sec_cmd, 1004 (fdata & 0xff00) | ((fdata << 16) & 1005 0xff0000) | ((fdata >> 16) & 0xff)); 1006 ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, 1007 (fdata & 0xff00) |((fdata << 16) & 1008 0xff0000) | ((fdata >> 16) & 0xff)); 1009 if (ret != QLA_SUCCESS) { 1010 DEBUG9(printk("%s(%ld) Unable to flash " 1011 "sector: address=%x.\n", __func__, 1012 ha->host_no, faddr)); 1013 break; 1014 } 1015 } 1016 1017 /* Go with burst-write. */ 1018 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 1019 /* Copy data to DMA'ble buffer. */ 1020 for (miter = 0, s = optrom, d = dwptr; 1021 miter < OPTROM_BURST_DWORDS; miter++, s++, d++) 1022 *s = cpu_to_le32(*d); 1023 1024 ret = qla2x00_load_ram(ha, optrom_dma, 1025 flash_data_to_access_addr(faddr), 1026 OPTROM_BURST_DWORDS); 1027 if (ret != QLA_SUCCESS) { 1028 qla_printk(KERN_WARNING, ha, 1029 "Unable to burst-write optrom segment " 1030 "(%x/%x/%llx).\n", ret, 1031 flash_data_to_access_addr(faddr), 1032 (unsigned long long)optrom_dma); 1033 qla_printk(KERN_WARNING, ha, 1034 "Reverting to slow-write.\n"); 1035 1036 dma_free_coherent(&ha->pdev->dev, 1037 OPTROM_BURST_SIZE, optrom, optrom_dma); 1038 optrom = NULL; 1039 } else { 1040 liter += OPTROM_BURST_DWORDS - 1; 1041 faddr += OPTROM_BURST_DWORDS - 1; 1042 dwptr += OPTROM_BURST_DWORDS - 1; 1043 continue; 1044 } 1045 } 1046 1047 ret = qla24xx_write_flash_dword(ha, 1048 flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr)); 1049 if (ret != QLA_SUCCESS) { 1050 DEBUG9(printk("%s(%ld) Unable to program flash " 1051 "address=%x data=%x.\n", __func__, 1052 ha->host_no, faddr, *dwptr)); 1053 break; 1054 } 1055 1056 /* Do sector protect. */ 1057 if (ha->fdt_unprotect_sec_cmd && 1058 ((faddr & rest_addr) == rest_addr)) 1059 qla24xx_write_flash_dword(ha, 1060 ha->fdt_protect_sec_cmd, 1061 (fdata & 0xff00) | ((fdata << 16) & 1062 0xff0000) | ((fdata >> 16) & 0xff)); 1063 } 1064 1065 qla24xx_protect_flash(ha); 1066 1067 if (optrom) 1068 dma_free_coherent(&ha->pdev->dev, 1069 OPTROM_BURST_SIZE, optrom, optrom_dma); 1070 1071 return ret; 1072 } 1073 1074 uint8_t * 1075 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 1076 uint32_t bytes) 1077 { 1078 uint32_t i; 1079 uint16_t *wptr; 1080 1081 /* Word reads to NVRAM via registers. */ 1082 wptr = (uint16_t *)buf; 1083 qla2x00_lock_nvram_access(ha); 1084 for (i = 0; i < bytes >> 1; i++, naddr++) 1085 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 1086 naddr)); 1087 qla2x00_unlock_nvram_access(ha); 1088 1089 return buf; 1090 } 1091 1092 uint8_t * 1093 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 1094 uint32_t bytes) 1095 { 1096 uint32_t i; 1097 uint32_t *dwptr; 1098 1099 /* Dword reads to flash. */ 1100 dwptr = (uint32_t *)buf; 1101 for (i = 0; i < bytes >> 2; i++, naddr++) 1102 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 1103 nvram_data_to_access_addr(naddr))); 1104 1105 return buf; 1106 } 1107 1108 int 1109 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 1110 uint32_t bytes) 1111 { 1112 int ret, stat; 1113 uint32_t i; 1114 uint16_t *wptr; 1115 unsigned long flags; 1116 1117 ret = QLA_SUCCESS; 1118 1119 spin_lock_irqsave(&ha->hardware_lock, flags); 1120 qla2x00_lock_nvram_access(ha); 1121 1122 /* Disable NVRAM write-protection. */ 1123 stat = qla2x00_clear_nvram_protection(ha); 1124 1125 wptr = (uint16_t *)buf; 1126 for (i = 0; i < bytes >> 1; i++, naddr++) { 1127 qla2x00_write_nvram_word(ha, naddr, 1128 cpu_to_le16(*wptr)); 1129 wptr++; 1130 } 1131 1132 /* Enable NVRAM write-protection. */ 1133 qla2x00_set_nvram_protection(ha, stat); 1134 1135 qla2x00_unlock_nvram_access(ha); 1136 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1137 1138 return ret; 1139 } 1140 1141 int 1142 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 1143 uint32_t bytes) 1144 { 1145 int ret; 1146 uint32_t i; 1147 uint32_t *dwptr; 1148 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1149 1150 ret = QLA_SUCCESS; 1151 1152 /* Enable flash write. */ 1153 WRT_REG_DWORD(®->ctrl_status, 1154 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1155 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1156 1157 /* Disable NVRAM write-protection. */ 1158 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 1159 0); 1160 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 1161 0); 1162 1163 /* Dword writes to flash. */ 1164 dwptr = (uint32_t *)buf; 1165 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) { 1166 ret = qla24xx_write_flash_dword(ha, 1167 nvram_data_to_access_addr(naddr), 1168 cpu_to_le32(*dwptr)); 1169 if (ret != QLA_SUCCESS) { 1170 DEBUG9(printk("%s(%ld) Unable to program " 1171 "nvram address=%x data=%x.\n", __func__, 1172 ha->host_no, naddr, *dwptr)); 1173 break; 1174 } 1175 } 1176 1177 /* Enable NVRAM write-protection. */ 1178 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101), 1179 0x8c); 1180 1181 /* Disable flash write. */ 1182 WRT_REG_DWORD(®->ctrl_status, 1183 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1184 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1185 1186 return ret; 1187 } 1188 1189 uint8_t * 1190 qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 1191 uint32_t bytes) 1192 { 1193 uint32_t i; 1194 uint32_t *dwptr; 1195 1196 /* Dword reads to flash. */ 1197 dwptr = (uint32_t *)buf; 1198 for (i = 0; i < bytes >> 2; i++, naddr++) 1199 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 1200 flash_data_to_access_addr(ha->flt_region_vpd_nvram | 1201 naddr))); 1202 1203 return buf; 1204 } 1205 1206 int 1207 qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr, 1208 uint32_t bytes) 1209 { 1210 #define RMW_BUFFER_SIZE (64 * 1024) 1211 uint8_t *dbuf; 1212 1213 dbuf = vmalloc(RMW_BUFFER_SIZE); 1214 if (!dbuf) 1215 return QLA_MEMORY_ALLOC_FAILED; 1216 ha->isp_ops->read_optrom(ha, dbuf, ha->flt_region_vpd_nvram << 2, 1217 RMW_BUFFER_SIZE); 1218 memcpy(dbuf + (naddr << 2), buf, bytes); 1219 ha->isp_ops->write_optrom(ha, dbuf, ha->flt_region_vpd_nvram << 2, 1220 RMW_BUFFER_SIZE); 1221 vfree(dbuf); 1222 1223 return QLA_SUCCESS; 1224 } 1225 1226 static inline void 1227 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) 1228 { 1229 if (IS_QLA2322(ha)) { 1230 /* Flip all colors. */ 1231 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1232 /* Turn off. */ 1233 ha->beacon_color_state = 0; 1234 *pflags = GPIO_LED_ALL_OFF; 1235 } else { 1236 /* Turn on. */ 1237 ha->beacon_color_state = QLA_LED_ALL_ON; 1238 *pflags = GPIO_LED_RGA_ON; 1239 } 1240 } else { 1241 /* Flip green led only. */ 1242 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 1243 /* Turn off. */ 1244 ha->beacon_color_state = 0; 1245 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 1246 } else { 1247 /* Turn on. */ 1248 ha->beacon_color_state = QLA_LED_GRN_ON; 1249 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 1250 } 1251 } 1252 } 1253 1254 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) 1255 1256 void 1257 qla2x00_beacon_blink(struct scsi_qla_host *ha) 1258 { 1259 uint16_t gpio_enable; 1260 uint16_t gpio_data; 1261 uint16_t led_color = 0; 1262 unsigned long flags; 1263 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1264 1265 spin_lock_irqsave(&ha->hardware_lock, flags); 1266 1267 /* Save the Original GPIOE. */ 1268 if (ha->pio_address) { 1269 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1270 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1271 } else { 1272 gpio_enable = RD_REG_WORD(®->gpioe); 1273 gpio_data = RD_REG_WORD(®->gpiod); 1274 } 1275 1276 /* Set the modified gpio_enable values */ 1277 gpio_enable |= GPIO_LED_MASK; 1278 1279 if (ha->pio_address) { 1280 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1281 } else { 1282 WRT_REG_WORD(®->gpioe, gpio_enable); 1283 RD_REG_WORD(®->gpioe); 1284 } 1285 1286 qla2x00_flip_colors(ha, &led_color); 1287 1288 /* Clear out any previously set LED color. */ 1289 gpio_data &= ~GPIO_LED_MASK; 1290 1291 /* Set the new input LED color to GPIOD. */ 1292 gpio_data |= led_color; 1293 1294 /* Set the modified gpio_data values */ 1295 if (ha->pio_address) { 1296 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1297 } else { 1298 WRT_REG_WORD(®->gpiod, gpio_data); 1299 RD_REG_WORD(®->gpiod); 1300 } 1301 1302 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1303 } 1304 1305 int 1306 qla2x00_beacon_on(struct scsi_qla_host *ha) 1307 { 1308 uint16_t gpio_enable; 1309 uint16_t gpio_data; 1310 unsigned long flags; 1311 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1312 1313 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1314 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 1315 1316 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { 1317 qla_printk(KERN_WARNING, ha, 1318 "Unable to update fw options (beacon on).\n"); 1319 return QLA_FUNCTION_FAILED; 1320 } 1321 1322 /* Turn off LEDs. */ 1323 spin_lock_irqsave(&ha->hardware_lock, flags); 1324 if (ha->pio_address) { 1325 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1326 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1327 } else { 1328 gpio_enable = RD_REG_WORD(®->gpioe); 1329 gpio_data = RD_REG_WORD(®->gpiod); 1330 } 1331 gpio_enable |= GPIO_LED_MASK; 1332 1333 /* Set the modified gpio_enable values. */ 1334 if (ha->pio_address) { 1335 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1336 } else { 1337 WRT_REG_WORD(®->gpioe, gpio_enable); 1338 RD_REG_WORD(®->gpioe); 1339 } 1340 1341 /* Clear out previously set LED colour. */ 1342 gpio_data &= ~GPIO_LED_MASK; 1343 if (ha->pio_address) { 1344 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1345 } else { 1346 WRT_REG_WORD(®->gpiod, gpio_data); 1347 RD_REG_WORD(®->gpiod); 1348 } 1349 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1350 1351 /* 1352 * Let the per HBA timer kick off the blinking process based on 1353 * the following flags. No need to do anything else now. 1354 */ 1355 ha->beacon_blink_led = 1; 1356 ha->beacon_color_state = 0; 1357 1358 return QLA_SUCCESS; 1359 } 1360 1361 int 1362 qla2x00_beacon_off(struct scsi_qla_host *ha) 1363 { 1364 int rval = QLA_SUCCESS; 1365 1366 ha->beacon_blink_led = 0; 1367 1368 /* Set the on flag so when it gets flipped it will be off. */ 1369 if (IS_QLA2322(ha)) 1370 ha->beacon_color_state = QLA_LED_ALL_ON; 1371 else 1372 ha->beacon_color_state = QLA_LED_GRN_ON; 1373 1374 ha->isp_ops->beacon_blink(ha); /* This turns green LED off */ 1375 1376 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1377 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 1378 1379 rval = qla2x00_set_fw_options(ha, ha->fw_options); 1380 if (rval != QLA_SUCCESS) 1381 qla_printk(KERN_WARNING, ha, 1382 "Unable to update fw options (beacon off).\n"); 1383 return rval; 1384 } 1385 1386 1387 static inline void 1388 qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags) 1389 { 1390 /* Flip all colors. */ 1391 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1392 /* Turn off. */ 1393 ha->beacon_color_state = 0; 1394 *pflags = 0; 1395 } else { 1396 /* Turn on. */ 1397 ha->beacon_color_state = QLA_LED_ALL_ON; 1398 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 1399 } 1400 } 1401 1402 void 1403 qla24xx_beacon_blink(struct scsi_qla_host *ha) 1404 { 1405 uint16_t led_color = 0; 1406 uint32_t gpio_data; 1407 unsigned long flags; 1408 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1409 1410 /* Save the Original GPIOD. */ 1411 spin_lock_irqsave(&ha->hardware_lock, flags); 1412 gpio_data = RD_REG_DWORD(®->gpiod); 1413 1414 /* Enable the gpio_data reg for update. */ 1415 gpio_data |= GPDX_LED_UPDATE_MASK; 1416 1417 WRT_REG_DWORD(®->gpiod, gpio_data); 1418 gpio_data = RD_REG_DWORD(®->gpiod); 1419 1420 /* Set the color bits. */ 1421 qla24xx_flip_colors(ha, &led_color); 1422 1423 /* Clear out any previously set LED color. */ 1424 gpio_data &= ~GPDX_LED_COLOR_MASK; 1425 1426 /* Set the new input LED color to GPIOD. */ 1427 gpio_data |= led_color; 1428 1429 /* Set the modified gpio_data values. */ 1430 WRT_REG_DWORD(®->gpiod, gpio_data); 1431 gpio_data = RD_REG_DWORD(®->gpiod); 1432 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1433 } 1434 1435 int 1436 qla24xx_beacon_on(struct scsi_qla_host *ha) 1437 { 1438 uint32_t gpio_data; 1439 unsigned long flags; 1440 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1441 1442 if (ha->beacon_blink_led == 0) { 1443 /* Enable firmware for update */ 1444 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1445 1446 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) 1447 return QLA_FUNCTION_FAILED; 1448 1449 if (qla2x00_get_fw_options(ha, ha->fw_options) != 1450 QLA_SUCCESS) { 1451 qla_printk(KERN_WARNING, ha, 1452 "Unable to update fw options (beacon on).\n"); 1453 return QLA_FUNCTION_FAILED; 1454 } 1455 1456 spin_lock_irqsave(&ha->hardware_lock, flags); 1457 gpio_data = RD_REG_DWORD(®->gpiod); 1458 1459 /* Enable the gpio_data reg for update. */ 1460 gpio_data |= GPDX_LED_UPDATE_MASK; 1461 WRT_REG_DWORD(®->gpiod, gpio_data); 1462 RD_REG_DWORD(®->gpiod); 1463 1464 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1465 } 1466 1467 /* So all colors blink together. */ 1468 ha->beacon_color_state = 0; 1469 1470 /* Let the per HBA timer kick off the blinking process. */ 1471 ha->beacon_blink_led = 1; 1472 1473 return QLA_SUCCESS; 1474 } 1475 1476 int 1477 qla24xx_beacon_off(struct scsi_qla_host *ha) 1478 { 1479 uint32_t gpio_data; 1480 unsigned long flags; 1481 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1482 1483 ha->beacon_blink_led = 0; 1484 ha->beacon_color_state = QLA_LED_ALL_ON; 1485 1486 ha->isp_ops->beacon_blink(ha); /* Will flip to all off. */ 1487 1488 /* Give control back to firmware. */ 1489 spin_lock_irqsave(&ha->hardware_lock, flags); 1490 gpio_data = RD_REG_DWORD(®->gpiod); 1491 1492 /* Disable the gpio_data reg for update. */ 1493 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1494 WRT_REG_DWORD(®->gpiod, gpio_data); 1495 RD_REG_DWORD(®->gpiod); 1496 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1497 1498 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1499 1500 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { 1501 qla_printk(KERN_WARNING, ha, 1502 "Unable to update fw options (beacon off).\n"); 1503 return QLA_FUNCTION_FAILED; 1504 } 1505 1506 if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) { 1507 qla_printk(KERN_WARNING, ha, 1508 "Unable to get fw options (beacon off).\n"); 1509 return QLA_FUNCTION_FAILED; 1510 } 1511 1512 return QLA_SUCCESS; 1513 } 1514 1515 1516 /* 1517 * Flash support routines 1518 */ 1519 1520 /** 1521 * qla2x00_flash_enable() - Setup flash for reading and writing. 1522 * @ha: HA context 1523 */ 1524 static void 1525 qla2x00_flash_enable(scsi_qla_host_t *ha) 1526 { 1527 uint16_t data; 1528 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1529 1530 data = RD_REG_WORD(®->ctrl_status); 1531 data |= CSR_FLASH_ENABLE; 1532 WRT_REG_WORD(®->ctrl_status, data); 1533 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1534 } 1535 1536 /** 1537 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1538 * @ha: HA context 1539 */ 1540 static void 1541 qla2x00_flash_disable(scsi_qla_host_t *ha) 1542 { 1543 uint16_t data; 1544 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1545 1546 data = RD_REG_WORD(®->ctrl_status); 1547 data &= ~(CSR_FLASH_ENABLE); 1548 WRT_REG_WORD(®->ctrl_status, data); 1549 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1550 } 1551 1552 /** 1553 * qla2x00_read_flash_byte() - Reads a byte from flash 1554 * @ha: HA context 1555 * @addr: Address in flash to read 1556 * 1557 * A word is read from the chip, but, only the lower byte is valid. 1558 * 1559 * Returns the byte read from flash @addr. 1560 */ 1561 static uint8_t 1562 qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr) 1563 { 1564 uint16_t data; 1565 uint16_t bank_select; 1566 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1567 1568 bank_select = RD_REG_WORD(®->ctrl_status); 1569 1570 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1571 /* Specify 64K address range: */ 1572 /* clear out Module Select and Flash Address bits [19:16]. */ 1573 bank_select &= ~0xf8; 1574 bank_select |= addr >> 12 & 0xf0; 1575 bank_select |= CSR_FLASH_64K_BANK; 1576 WRT_REG_WORD(®->ctrl_status, bank_select); 1577 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1578 1579 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1580 data = RD_REG_WORD(®->flash_data); 1581 1582 return (uint8_t)data; 1583 } 1584 1585 /* Setup bit 16 of flash address. */ 1586 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 1587 bank_select |= CSR_FLASH_64K_BANK; 1588 WRT_REG_WORD(®->ctrl_status, bank_select); 1589 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1590 } else if (((addr & BIT_16) == 0) && 1591 (bank_select & CSR_FLASH_64K_BANK)) { 1592 bank_select &= ~(CSR_FLASH_64K_BANK); 1593 WRT_REG_WORD(®->ctrl_status, bank_select); 1594 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1595 } 1596 1597 /* Always perform IO mapped accesses to the FLASH registers. */ 1598 if (ha->pio_address) { 1599 uint16_t data2; 1600 1601 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 1602 do { 1603 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 1604 barrier(); 1605 cpu_relax(); 1606 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 1607 } while (data != data2); 1608 } else { 1609 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1610 data = qla2x00_debounce_register(®->flash_data); 1611 } 1612 1613 return (uint8_t)data; 1614 } 1615 1616 /** 1617 * qla2x00_write_flash_byte() - Write a byte to flash 1618 * @ha: HA context 1619 * @addr: Address in flash to write 1620 * @data: Data to write 1621 */ 1622 static void 1623 qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data) 1624 { 1625 uint16_t bank_select; 1626 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1627 1628 bank_select = RD_REG_WORD(®->ctrl_status); 1629 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1630 /* Specify 64K address range: */ 1631 /* clear out Module Select and Flash Address bits [19:16]. */ 1632 bank_select &= ~0xf8; 1633 bank_select |= addr >> 12 & 0xf0; 1634 bank_select |= CSR_FLASH_64K_BANK; 1635 WRT_REG_WORD(®->ctrl_status, bank_select); 1636 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1637 1638 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1639 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1640 WRT_REG_WORD(®->flash_data, (uint16_t)data); 1641 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1642 1643 return; 1644 } 1645 1646 /* Setup bit 16 of flash address. */ 1647 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 1648 bank_select |= CSR_FLASH_64K_BANK; 1649 WRT_REG_WORD(®->ctrl_status, bank_select); 1650 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1651 } else if (((addr & BIT_16) == 0) && 1652 (bank_select & CSR_FLASH_64K_BANK)) { 1653 bank_select &= ~(CSR_FLASH_64K_BANK); 1654 WRT_REG_WORD(®->ctrl_status, bank_select); 1655 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1656 } 1657 1658 /* Always perform IO mapped accesses to the FLASH registers. */ 1659 if (ha->pio_address) { 1660 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 1661 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); 1662 } else { 1663 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1664 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1665 WRT_REG_WORD(®->flash_data, (uint16_t)data); 1666 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1667 } 1668 } 1669 1670 /** 1671 * qla2x00_poll_flash() - Polls flash for completion. 1672 * @ha: HA context 1673 * @addr: Address in flash to poll 1674 * @poll_data: Data to be polled 1675 * @man_id: Flash manufacturer ID 1676 * @flash_id: Flash ID 1677 * 1678 * This function polls the device until bit 7 of what is read matches data 1679 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed 1680 * out (a fatal error). The flash book recommeds reading bit 7 again after 1681 * reading bit 5 as a 1. 1682 * 1683 * Returns 0 on success, else non-zero. 1684 */ 1685 static int 1686 qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data, 1687 uint8_t man_id, uint8_t flash_id) 1688 { 1689 int status; 1690 uint8_t flash_data; 1691 uint32_t cnt; 1692 1693 status = 1; 1694 1695 /* Wait for 30 seconds for command to finish. */ 1696 poll_data &= BIT_7; 1697 for (cnt = 3000000; cnt; cnt--) { 1698 flash_data = qla2x00_read_flash_byte(ha, addr); 1699 if ((flash_data & BIT_7) == poll_data) { 1700 status = 0; 1701 break; 1702 } 1703 1704 if (man_id != 0x40 && man_id != 0xda) { 1705 if ((flash_data & BIT_5) && cnt > 2) 1706 cnt = 2; 1707 } 1708 udelay(10); 1709 barrier(); 1710 cond_resched(); 1711 } 1712 return status; 1713 } 1714 1715 /** 1716 * qla2x00_program_flash_address() - Programs a flash address 1717 * @ha: HA context 1718 * @addr: Address in flash to program 1719 * @data: Data to be written in flash 1720 * @man_id: Flash manufacturer ID 1721 * @flash_id: Flash ID 1722 * 1723 * Returns 0 on success, else non-zero. 1724 */ 1725 static int 1726 qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data, 1727 uint8_t man_id, uint8_t flash_id) 1728 { 1729 /* Write Program Command Sequence. */ 1730 if (IS_OEM_001(ha)) { 1731 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1732 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1733 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 1734 qla2x00_write_flash_byte(ha, addr, data); 1735 } else { 1736 if (man_id == 0xda && flash_id == 0xc1) { 1737 qla2x00_write_flash_byte(ha, addr, data); 1738 if (addr & 0x7e) 1739 return 0; 1740 } else { 1741 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1742 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1743 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 1744 qla2x00_write_flash_byte(ha, addr, data); 1745 } 1746 } 1747 1748 udelay(150); 1749 1750 /* Wait for write to complete. */ 1751 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 1752 } 1753 1754 /** 1755 * qla2x00_erase_flash() - Erase the flash. 1756 * @ha: HA context 1757 * @man_id: Flash manufacturer ID 1758 * @flash_id: Flash ID 1759 * 1760 * Returns 0 on success, else non-zero. 1761 */ 1762 static int 1763 qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id) 1764 { 1765 /* Individual Sector Erase Command Sequence */ 1766 if (IS_OEM_001(ha)) { 1767 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1768 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1769 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 1770 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1771 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1772 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 1773 } else { 1774 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1775 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1776 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 1777 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1778 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1779 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 1780 } 1781 1782 udelay(150); 1783 1784 /* Wait for erase to complete. */ 1785 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 1786 } 1787 1788 /** 1789 * qla2x00_erase_flash_sector() - Erase a flash sector. 1790 * @ha: HA context 1791 * @addr: Flash sector to erase 1792 * @sec_mask: Sector address mask 1793 * @man_id: Flash manufacturer ID 1794 * @flash_id: Flash ID 1795 * 1796 * Returns 0 on success, else non-zero. 1797 */ 1798 static int 1799 qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr, 1800 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 1801 { 1802 /* Individual Sector Erase Command Sequence */ 1803 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1804 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1805 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 1806 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1807 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1808 if (man_id == 0x1f && flash_id == 0x13) 1809 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 1810 else 1811 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 1812 1813 udelay(150); 1814 1815 /* Wait for erase to complete. */ 1816 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 1817 } 1818 1819 /** 1820 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 1821 * @man_id: Flash manufacturer ID 1822 * @flash_id: Flash ID 1823 */ 1824 static void 1825 qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id, 1826 uint8_t *flash_id) 1827 { 1828 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1829 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1830 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 1831 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 1832 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 1833 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1834 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1835 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 1836 } 1837 1838 static void 1839 qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr, 1840 uint32_t length) 1841 { 1842 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1843 uint32_t midpoint, ilength; 1844 uint8_t data; 1845 1846 midpoint = length / 2; 1847 1848 WRT_REG_WORD(®->nvram, 0); 1849 RD_REG_WORD(®->nvram); 1850 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 1851 if (ilength == midpoint) { 1852 WRT_REG_WORD(®->nvram, NVR_SELECT); 1853 RD_REG_WORD(®->nvram); 1854 } 1855 data = qla2x00_read_flash_byte(ha, saddr); 1856 if (saddr % 100) 1857 udelay(10); 1858 *tmp_buf = data; 1859 cond_resched(); 1860 } 1861 } 1862 1863 static inline void 1864 qla2x00_suspend_hba(struct scsi_qla_host *ha) 1865 { 1866 int cnt; 1867 unsigned long flags; 1868 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1869 1870 /* Suspend HBA. */ 1871 scsi_block_requests(ha->host); 1872 ha->isp_ops->disable_intrs(ha); 1873 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1874 1875 /* Pause RISC. */ 1876 spin_lock_irqsave(&ha->hardware_lock, flags); 1877 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 1878 RD_REG_WORD(®->hccr); 1879 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 1880 for (cnt = 0; cnt < 30000; cnt++) { 1881 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 1882 break; 1883 udelay(100); 1884 } 1885 } else { 1886 udelay(10); 1887 } 1888 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1889 } 1890 1891 static inline void 1892 qla2x00_resume_hba(struct scsi_qla_host *ha) 1893 { 1894 /* Resume HBA. */ 1895 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 1896 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); 1897 qla2xxx_wake_dpc(ha); 1898 qla2x00_wait_for_hba_online(ha); 1899 scsi_unblock_requests(ha->host); 1900 } 1901 1902 uint8_t * 1903 qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1904 uint32_t offset, uint32_t length) 1905 { 1906 uint32_t addr, midpoint; 1907 uint8_t *data; 1908 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1909 1910 /* Suspend HBA. */ 1911 qla2x00_suspend_hba(ha); 1912 1913 /* Go with read. */ 1914 midpoint = ha->optrom_size / 2; 1915 1916 qla2x00_flash_enable(ha); 1917 WRT_REG_WORD(®->nvram, 0); 1918 RD_REG_WORD(®->nvram); /* PCI Posting. */ 1919 for (addr = offset, data = buf; addr < length; addr++, data++) { 1920 if (addr == midpoint) { 1921 WRT_REG_WORD(®->nvram, NVR_SELECT); 1922 RD_REG_WORD(®->nvram); /* PCI Posting. */ 1923 } 1924 1925 *data = qla2x00_read_flash_byte(ha, addr); 1926 } 1927 qla2x00_flash_disable(ha); 1928 1929 /* Resume HBA. */ 1930 qla2x00_resume_hba(ha); 1931 1932 return buf; 1933 } 1934 1935 int 1936 qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1937 uint32_t offset, uint32_t length) 1938 { 1939 1940 int rval; 1941 uint8_t man_id, flash_id, sec_number, data; 1942 uint16_t wd; 1943 uint32_t addr, liter, sec_mask, rest_addr; 1944 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1945 1946 /* Suspend HBA. */ 1947 qla2x00_suspend_hba(ha); 1948 1949 rval = QLA_SUCCESS; 1950 sec_number = 0; 1951 1952 /* Reset ISP chip. */ 1953 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 1954 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 1955 1956 /* Go with write. */ 1957 qla2x00_flash_enable(ha); 1958 do { /* Loop once to provide quick error exit */ 1959 /* Structure of flash memory based on manufacturer */ 1960 if (IS_OEM_001(ha)) { 1961 /* OEM variant with special flash part. */ 1962 man_id = flash_id = 0; 1963 rest_addr = 0xffff; 1964 sec_mask = 0x10000; 1965 goto update_flash; 1966 } 1967 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 1968 switch (man_id) { 1969 case 0x20: /* ST flash. */ 1970 if (flash_id == 0xd2 || flash_id == 0xe3) { 1971 /* 1972 * ST m29w008at part - 64kb sector size with 1973 * 32kb,8kb,8kb,16kb sectors at memory address 1974 * 0xf0000. 1975 */ 1976 rest_addr = 0xffff; 1977 sec_mask = 0x10000; 1978 break; 1979 } 1980 /* 1981 * ST m29w010b part - 16kb sector size 1982 * Default to 16kb sectors 1983 */ 1984 rest_addr = 0x3fff; 1985 sec_mask = 0x1c000; 1986 break; 1987 case 0x40: /* Mostel flash. */ 1988 /* Mostel v29c51001 part - 512 byte sector size. */ 1989 rest_addr = 0x1ff; 1990 sec_mask = 0x1fe00; 1991 break; 1992 case 0xbf: /* SST flash. */ 1993 /* SST39sf10 part - 4kb sector size. */ 1994 rest_addr = 0xfff; 1995 sec_mask = 0x1f000; 1996 break; 1997 case 0xda: /* Winbond flash. */ 1998 /* Winbond W29EE011 part - 256 byte sector size. */ 1999 rest_addr = 0x7f; 2000 sec_mask = 0x1ff80; 2001 break; 2002 case 0xc2: /* Macronix flash. */ 2003 /* 64k sector size. */ 2004 if (flash_id == 0x38 || flash_id == 0x4f) { 2005 rest_addr = 0xffff; 2006 sec_mask = 0x10000; 2007 break; 2008 } 2009 /* Fall through... */ 2010 2011 case 0x1f: /* Atmel flash. */ 2012 /* 512k sector size. */ 2013 if (flash_id == 0x13) { 2014 rest_addr = 0x7fffffff; 2015 sec_mask = 0x80000000; 2016 break; 2017 } 2018 /* Fall through... */ 2019 2020 case 0x01: /* AMD flash. */ 2021 if (flash_id == 0x38 || flash_id == 0x40 || 2022 flash_id == 0x4f) { 2023 /* Am29LV081 part - 64kb sector size. */ 2024 /* Am29LV002BT part - 64kb sector size. */ 2025 rest_addr = 0xffff; 2026 sec_mask = 0x10000; 2027 break; 2028 } else if (flash_id == 0x3e) { 2029 /* 2030 * Am29LV008b part - 64kb sector size with 2031 * 32kb,8kb,8kb,16kb sector at memory address 2032 * h0xf0000. 2033 */ 2034 rest_addr = 0xffff; 2035 sec_mask = 0x10000; 2036 break; 2037 } else if (flash_id == 0x20 || flash_id == 0x6e) { 2038 /* 2039 * Am29LV010 part or AM29f010 - 16kb sector 2040 * size. 2041 */ 2042 rest_addr = 0x3fff; 2043 sec_mask = 0x1c000; 2044 break; 2045 } else if (flash_id == 0x6d) { 2046 /* Am29LV001 part - 8kb sector size. */ 2047 rest_addr = 0x1fff; 2048 sec_mask = 0x1e000; 2049 break; 2050 } 2051 default: 2052 /* Default to 16 kb sector size. */ 2053 rest_addr = 0x3fff; 2054 sec_mask = 0x1c000; 2055 break; 2056 } 2057 2058 update_flash: 2059 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2060 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 2061 rval = QLA_FUNCTION_FAILED; 2062 break; 2063 } 2064 } 2065 2066 for (addr = offset, liter = 0; liter < length; liter++, 2067 addr++) { 2068 data = buf[liter]; 2069 /* Are we at the beginning of a sector? */ 2070 if ((addr & rest_addr) == 0) { 2071 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2072 if (addr >= 0x10000UL) { 2073 if (((addr >> 12) & 0xf0) && 2074 ((man_id == 0x01 && 2075 flash_id == 0x3e) || 2076 (man_id == 0x20 && 2077 flash_id == 0xd2))) { 2078 sec_number++; 2079 if (sec_number == 1) { 2080 rest_addr = 2081 0x7fff; 2082 sec_mask = 2083 0x18000; 2084 } else if ( 2085 sec_number == 2 || 2086 sec_number == 3) { 2087 rest_addr = 2088 0x1fff; 2089 sec_mask = 2090 0x1e000; 2091 } else if ( 2092 sec_number == 4) { 2093 rest_addr = 2094 0x3fff; 2095 sec_mask = 2096 0x1c000; 2097 } 2098 } 2099 } 2100 } else if (addr == ha->optrom_size / 2) { 2101 WRT_REG_WORD(®->nvram, NVR_SELECT); 2102 RD_REG_WORD(®->nvram); 2103 } 2104 2105 if (flash_id == 0xda && man_id == 0xc1) { 2106 qla2x00_write_flash_byte(ha, 0x5555, 2107 0xaa); 2108 qla2x00_write_flash_byte(ha, 0x2aaa, 2109 0x55); 2110 qla2x00_write_flash_byte(ha, 0x5555, 2111 0xa0); 2112 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 2113 /* Then erase it */ 2114 if (qla2x00_erase_flash_sector(ha, 2115 addr, sec_mask, man_id, 2116 flash_id)) { 2117 rval = QLA_FUNCTION_FAILED; 2118 break; 2119 } 2120 if (man_id == 0x01 && flash_id == 0x6d) 2121 sec_number++; 2122 } 2123 } 2124 2125 if (man_id == 0x01 && flash_id == 0x6d) { 2126 if (sec_number == 1 && 2127 addr == (rest_addr - 1)) { 2128 rest_addr = 0x0fff; 2129 sec_mask = 0x1f000; 2130 } else if (sec_number == 3 && (addr & 0x7ffe)) { 2131 rest_addr = 0x3fff; 2132 sec_mask = 0x1c000; 2133 } 2134 } 2135 2136 if (qla2x00_program_flash_address(ha, addr, data, 2137 man_id, flash_id)) { 2138 rval = QLA_FUNCTION_FAILED; 2139 break; 2140 } 2141 cond_resched(); 2142 } 2143 } while (0); 2144 qla2x00_flash_disable(ha); 2145 2146 /* Resume HBA. */ 2147 qla2x00_resume_hba(ha); 2148 2149 return rval; 2150 } 2151 2152 uint8_t * 2153 qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 2154 uint32_t offset, uint32_t length) 2155 { 2156 /* Suspend HBA. */ 2157 scsi_block_requests(ha->host); 2158 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2159 2160 /* Go with read. */ 2161 qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2); 2162 2163 /* Resume HBA. */ 2164 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2165 scsi_unblock_requests(ha->host); 2166 2167 return buf; 2168 } 2169 2170 int 2171 qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 2172 uint32_t offset, uint32_t length) 2173 { 2174 int rval; 2175 2176 /* Suspend HBA. */ 2177 scsi_block_requests(ha->host); 2178 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2179 2180 /* Go with write. */ 2181 rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2, 2182 length >> 2); 2183 2184 /* Resume HBA -- RISC reset needed. */ 2185 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2186 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags); 2187 qla2xxx_wake_dpc(ha); 2188 qla2x00_wait_for_hba_online(ha); 2189 scsi_unblock_requests(ha->host); 2190 2191 return rval; 2192 } 2193 2194 uint8_t * 2195 qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 2196 uint32_t offset, uint32_t length) 2197 { 2198 int rval; 2199 dma_addr_t optrom_dma; 2200 void *optrom; 2201 uint8_t *pbuf; 2202 uint32_t faddr, left, burst; 2203 2204 if (offset & 0xfff) 2205 goto slow_read; 2206 if (length < OPTROM_BURST_SIZE) 2207 goto slow_read; 2208 2209 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2210 &optrom_dma, GFP_KERNEL); 2211 if (!optrom) { 2212 qla_printk(KERN_DEBUG, ha, 2213 "Unable to allocate memory for optrom burst read " 2214 "(%x KB).\n", OPTROM_BURST_SIZE / 1024); 2215 2216 goto slow_read; 2217 } 2218 2219 pbuf = buf; 2220 faddr = offset >> 2; 2221 left = length >> 2; 2222 burst = OPTROM_BURST_DWORDS; 2223 while (left != 0) { 2224 if (burst > left) 2225 burst = left; 2226 2227 rval = qla2x00_dump_ram(ha, optrom_dma, 2228 flash_data_to_access_addr(faddr), burst); 2229 if (rval) { 2230 qla_printk(KERN_WARNING, ha, 2231 "Unable to burst-read optrom segment " 2232 "(%x/%x/%llx).\n", rval, 2233 flash_data_to_access_addr(faddr), 2234 (unsigned long long)optrom_dma); 2235 qla_printk(KERN_WARNING, ha, 2236 "Reverting to slow-read.\n"); 2237 2238 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2239 optrom, optrom_dma); 2240 goto slow_read; 2241 } 2242 2243 memcpy(pbuf, optrom, burst * 4); 2244 2245 left -= burst; 2246 faddr += burst; 2247 pbuf += burst * 4; 2248 } 2249 2250 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, 2251 optrom_dma); 2252 2253 return buf; 2254 2255 slow_read: 2256 return qla24xx_read_optrom_data(ha, buf, offset, length); 2257 } 2258 2259 /** 2260 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 2261 * @ha: HA context 2262 * @pcids: Pointer to the FCODE PCI data structure 2263 * 2264 * The process of retrieving the FCODE version information is at best 2265 * described as interesting. 2266 * 2267 * Within the first 100h bytes of the image an ASCII string is present 2268 * which contains several pieces of information including the FCODE 2269 * version. Unfortunately it seems the only reliable way to retrieve 2270 * the version is by scanning for another sentinel within the string, 2271 * the FCODE build date: 2272 * 2273 * ... 2.00.02 10/17/02 ... 2274 * 2275 * Returns QLA_SUCCESS on successful retrieval of version. 2276 */ 2277 static void 2278 qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids) 2279 { 2280 int ret = QLA_FUNCTION_FAILED; 2281 uint32_t istart, iend, iter, vend; 2282 uint8_t do_next, rbyte, *vbyte; 2283 2284 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2285 2286 /* Skip the PCI data structure. */ 2287 istart = pcids + 2288 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 2289 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 2290 iend = istart + 0x100; 2291 do { 2292 /* Scan for the sentinel date string...eeewww. */ 2293 do_next = 0; 2294 iter = istart; 2295 while ((iter < iend) && !do_next) { 2296 iter++; 2297 if (qla2x00_read_flash_byte(ha, iter) == '/') { 2298 if (qla2x00_read_flash_byte(ha, iter + 2) == 2299 '/') 2300 do_next++; 2301 else if (qla2x00_read_flash_byte(ha, 2302 iter + 3) == '/') 2303 do_next++; 2304 } 2305 } 2306 if (!do_next) 2307 break; 2308 2309 /* Backtrack to previous ' ' (space). */ 2310 do_next = 0; 2311 while ((iter > istart) && !do_next) { 2312 iter--; 2313 if (qla2x00_read_flash_byte(ha, iter) == ' ') 2314 do_next++; 2315 } 2316 if (!do_next) 2317 break; 2318 2319 /* 2320 * Mark end of version tag, and find previous ' ' (space) or 2321 * string length (recent FCODE images -- major hack ahead!!!). 2322 */ 2323 vend = iter - 1; 2324 do_next = 0; 2325 while ((iter > istart) && !do_next) { 2326 iter--; 2327 rbyte = qla2x00_read_flash_byte(ha, iter); 2328 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 2329 do_next++; 2330 } 2331 if (!do_next) 2332 break; 2333 2334 /* Mark beginning of version tag, and copy data. */ 2335 iter++; 2336 if ((vend - iter) && 2337 ((vend - iter) < sizeof(ha->fcode_revision))) { 2338 vbyte = ha->fcode_revision; 2339 while (iter <= vend) { 2340 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 2341 iter++; 2342 } 2343 ret = QLA_SUCCESS; 2344 } 2345 } while (0); 2346 2347 if (ret != QLA_SUCCESS) 2348 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2349 } 2350 2351 int 2352 qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf) 2353 { 2354 int ret = QLA_SUCCESS; 2355 uint8_t code_type, last_image; 2356 uint32_t pcihdr, pcids; 2357 uint8_t *dbyte; 2358 uint16_t *dcode; 2359 2360 if (!ha->pio_address || !mbuf) 2361 return QLA_FUNCTION_FAILED; 2362 2363 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 2364 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 2365 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2366 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2367 2368 qla2x00_flash_enable(ha); 2369 2370 /* Begin with first PCI expansion ROM header. */ 2371 pcihdr = 0; 2372 last_image = 1; 2373 do { 2374 /* Verify PCI expansion ROM header. */ 2375 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 2376 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 2377 /* No signature */ 2378 DEBUG2(printk("scsi(%ld): No matching ROM " 2379 "signature.\n", ha->host_no)); 2380 ret = QLA_FUNCTION_FAILED; 2381 break; 2382 } 2383 2384 /* Locate PCI data structure. */ 2385 pcids = pcihdr + 2386 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 2387 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 2388 2389 /* Validate signature of PCI data structure. */ 2390 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 2391 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 2392 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 2393 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 2394 /* Incorrect header. */ 2395 DEBUG2(printk("%s(): PCI data struct not found " 2396 "pcir_adr=%x.\n", __func__, pcids)); 2397 ret = QLA_FUNCTION_FAILED; 2398 break; 2399 } 2400 2401 /* Read version */ 2402 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 2403 switch (code_type) { 2404 case ROM_CODE_TYPE_BIOS: 2405 /* Intel x86, PC-AT compatible. */ 2406 ha->bios_revision[0] = 2407 qla2x00_read_flash_byte(ha, pcids + 0x12); 2408 ha->bios_revision[1] = 2409 qla2x00_read_flash_byte(ha, pcids + 0x13); 2410 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__, 2411 ha->bios_revision[1], ha->bios_revision[0])); 2412 break; 2413 case ROM_CODE_TYPE_FCODE: 2414 /* Open Firmware standard for PCI (FCode). */ 2415 /* Eeeewww... */ 2416 qla2x00_get_fcode_version(ha, pcids); 2417 break; 2418 case ROM_CODE_TYPE_EFI: 2419 /* Extensible Firmware Interface (EFI). */ 2420 ha->efi_revision[0] = 2421 qla2x00_read_flash_byte(ha, pcids + 0x12); 2422 ha->efi_revision[1] = 2423 qla2x00_read_flash_byte(ha, pcids + 0x13); 2424 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__, 2425 ha->efi_revision[1], ha->efi_revision[0])); 2426 break; 2427 default: 2428 DEBUG2(printk("%s(): Unrecognized code type %x at " 2429 "pcids %x.\n", __func__, code_type, pcids)); 2430 break; 2431 } 2432 2433 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 2434 2435 /* Locate next PCI expansion ROM. */ 2436 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 2437 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 2438 } while (!last_image); 2439 2440 if (IS_QLA2322(ha)) { 2441 /* Read firmware image information. */ 2442 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2443 dbyte = mbuf; 2444 memset(dbyte, 0, 8); 2445 dcode = (uint16_t *)dbyte; 2446 2447 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, 2448 8); 2449 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n", 2450 __func__, ha->host_no)); 2451 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8)); 2452 2453 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 2454 dcode[2] == 0xffff && dcode[3] == 0xffff) || 2455 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 2456 dcode[3] == 0)) { 2457 DEBUG2(printk("%s(): Unrecognized fw revision at " 2458 "%x.\n", __func__, ha->flt_region_fw * 4)); 2459 } else { 2460 /* values are in big endian */ 2461 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 2462 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 2463 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 2464 } 2465 } 2466 2467 qla2x00_flash_disable(ha); 2468 2469 return ret; 2470 } 2471 2472 int 2473 qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf) 2474 { 2475 int ret = QLA_SUCCESS; 2476 uint32_t pcihdr, pcids; 2477 uint32_t *dcode; 2478 uint8_t *bcode; 2479 uint8_t code_type, last_image; 2480 int i; 2481 2482 if (!mbuf) 2483 return QLA_FUNCTION_FAILED; 2484 2485 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 2486 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 2487 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2488 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2489 2490 dcode = mbuf; 2491 2492 /* Begin with first PCI expansion ROM header. */ 2493 pcihdr = ha->flt_region_boot; 2494 last_image = 1; 2495 do { 2496 /* Verify PCI expansion ROM header. */ 2497 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20); 2498 bcode = mbuf + (pcihdr % 4); 2499 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) { 2500 /* No signature */ 2501 DEBUG2(printk("scsi(%ld): No matching ROM " 2502 "signature.\n", ha->host_no)); 2503 ret = QLA_FUNCTION_FAILED; 2504 break; 2505 } 2506 2507 /* Locate PCI data structure. */ 2508 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 2509 2510 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20); 2511 bcode = mbuf + (pcihdr % 4); 2512 2513 /* Validate signature of PCI data structure. */ 2514 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 2515 bcode[0x2] != 'I' || bcode[0x3] != 'R') { 2516 /* Incorrect header. */ 2517 DEBUG2(printk("%s(): PCI data struct not found " 2518 "pcir_adr=%x.\n", __func__, pcids)); 2519 ret = QLA_FUNCTION_FAILED; 2520 break; 2521 } 2522 2523 /* Read version */ 2524 code_type = bcode[0x14]; 2525 switch (code_type) { 2526 case ROM_CODE_TYPE_BIOS: 2527 /* Intel x86, PC-AT compatible. */ 2528 ha->bios_revision[0] = bcode[0x12]; 2529 ha->bios_revision[1] = bcode[0x13]; 2530 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__, 2531 ha->bios_revision[1], ha->bios_revision[0])); 2532 break; 2533 case ROM_CODE_TYPE_FCODE: 2534 /* Open Firmware standard for PCI (FCode). */ 2535 ha->fcode_revision[0] = bcode[0x12]; 2536 ha->fcode_revision[1] = bcode[0x13]; 2537 DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__, 2538 ha->fcode_revision[1], ha->fcode_revision[0])); 2539 break; 2540 case ROM_CODE_TYPE_EFI: 2541 /* Extensible Firmware Interface (EFI). */ 2542 ha->efi_revision[0] = bcode[0x12]; 2543 ha->efi_revision[1] = bcode[0x13]; 2544 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__, 2545 ha->efi_revision[1], ha->efi_revision[0])); 2546 break; 2547 default: 2548 DEBUG2(printk("%s(): Unrecognized code type %x at " 2549 "pcids %x.\n", __func__, code_type, pcids)); 2550 break; 2551 } 2552 2553 last_image = bcode[0x15] & BIT_7; 2554 2555 /* Locate next PCI expansion ROM. */ 2556 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 2557 } while (!last_image); 2558 2559 /* Read firmware image information. */ 2560 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2561 dcode = mbuf; 2562 2563 qla24xx_read_flash_data(ha, dcode, ha->flt_region_fw + 4, 4); 2564 for (i = 0; i < 4; i++) 2565 dcode[i] = be32_to_cpu(dcode[i]); 2566 2567 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 2568 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 2569 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 2570 dcode[3] == 0)) { 2571 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n", 2572 __func__, ha->flt_region_fw)); 2573 } else { 2574 ha->fw_revision[0] = dcode[0]; 2575 ha->fw_revision[1] = dcode[1]; 2576 ha->fw_revision[2] = dcode[2]; 2577 ha->fw_revision[3] = dcode[3]; 2578 } 2579 2580 return ret; 2581 } 2582 2583 static int 2584 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) 2585 { 2586 if (pos >= end || *pos != 0x82) 2587 return 0; 2588 2589 pos += 3 + pos[1]; 2590 if (pos >= end || *pos != 0x90) 2591 return 0; 2592 2593 pos += 3 + pos[1]; 2594 if (pos >= end || *pos != 0x78) 2595 return 0; 2596 2597 return 1; 2598 } 2599 2600 int 2601 qla2xxx_get_vpd_field(scsi_qla_host_t *ha, char *key, char *str, size_t size) 2602 { 2603 uint8_t *pos = ha->vpd; 2604 uint8_t *end = pos + ha->vpd_size; 2605 int len = 0; 2606 2607 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) 2608 return 0; 2609 2610 while (pos < end && *pos != 0x78) { 2611 len = (*pos == 0x82) ? pos[1] : pos[2]; 2612 2613 if (!strncmp(pos, key, strlen(key))) 2614 break; 2615 2616 if (*pos != 0x90 && *pos != 0x91) 2617 pos += len; 2618 2619 pos += 3; 2620 } 2621 2622 if (pos < end - len && *pos != 0x78) 2623 return snprintf(str, size, "%.*s", len, pos + 3); 2624 2625 return 0; 2626 } 2627 2628 static int 2629 qla2xxx_hw_event_store(scsi_qla_host_t *ha, uint32_t *fdata) 2630 { 2631 uint32_t d[2], faddr; 2632 2633 /* Locate first empty entry. */ 2634 for (;;) { 2635 if (ha->hw_event_ptr >= 2636 ha->flt_region_hw_event + FA_HW_EVENT_SIZE) { 2637 DEBUG2(qla_printk(KERN_WARNING, ha, 2638 "HW event -- Log Full!\n")); 2639 return QLA_MEMORY_ALLOC_FAILED; 2640 } 2641 2642 qla24xx_read_flash_data(ha, d, ha->hw_event_ptr, 2); 2643 faddr = flash_data_to_access_addr(ha->hw_event_ptr); 2644 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE; 2645 if (d[0] == __constant_cpu_to_le32(0xffffffff) && 2646 d[1] == __constant_cpu_to_le32(0xffffffff)) { 2647 qla24xx_unprotect_flash(ha); 2648 2649 qla24xx_write_flash_dword(ha, faddr++, 2650 cpu_to_le32(jiffies)); 2651 qla24xx_write_flash_dword(ha, faddr++, 0); 2652 qla24xx_write_flash_dword(ha, faddr++, *fdata++); 2653 qla24xx_write_flash_dword(ha, faddr++, *fdata); 2654 2655 qla24xx_protect_flash(ha); 2656 break; 2657 } 2658 } 2659 return QLA_SUCCESS; 2660 } 2661 2662 int 2663 qla2xxx_hw_event_log(scsi_qla_host_t *ha, uint16_t code, uint16_t d1, 2664 uint16_t d2, uint16_t d3) 2665 { 2666 #define QMARK(a, b, c, d) \ 2667 cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d)) 2668 2669 int rval; 2670 uint32_t marker[2], fdata[4]; 2671 2672 if (ha->flt_region_hw_event == 0) 2673 return QLA_FUNCTION_FAILED; 2674 2675 DEBUG2(qla_printk(KERN_WARNING, ha, 2676 "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code, d1, d2, d3)); 2677 2678 /* If marker not already found, locate or write. */ 2679 if (!ha->flags.hw_event_marker_found) { 2680 /* Create marker. */ 2681 marker[0] = QMARK('L', ha->fw_major_version, 2682 ha->fw_minor_version, ha->fw_subminor_version); 2683 marker[1] = QMARK(QLA_DRIVER_MAJOR_VER, QLA_DRIVER_MINOR_VER, 2684 QLA_DRIVER_PATCH_VER, QLA_DRIVER_BETA_VER); 2685 2686 /* Locate marker. */ 2687 ha->hw_event_ptr = ha->flt_region_hw_event; 2688 for (;;) { 2689 qla24xx_read_flash_data(ha, fdata, ha->hw_event_ptr, 2690 4); 2691 if (fdata[0] == __constant_cpu_to_le32(0xffffffff) && 2692 fdata[1] == __constant_cpu_to_le32(0xffffffff)) 2693 break; 2694 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE; 2695 if (ha->hw_event_ptr >= 2696 ha->flt_region_hw_event + FA_HW_EVENT_SIZE) { 2697 DEBUG2(qla_printk(KERN_WARNING, ha, 2698 "HW event -- Log Full!\n")); 2699 return QLA_MEMORY_ALLOC_FAILED; 2700 } 2701 if (fdata[2] == marker[0] && fdata[3] == marker[1]) { 2702 ha->flags.hw_event_marker_found = 1; 2703 break; 2704 } 2705 } 2706 /* No marker, write it. */ 2707 if (!ha->flags.hw_event_marker_found) { 2708 rval = qla2xxx_hw_event_store(ha, marker); 2709 if (rval != QLA_SUCCESS) { 2710 DEBUG2(qla_printk(KERN_WARNING, ha, 2711 "HW event -- Failed marker write=%x.!\n", 2712 rval)); 2713 return rval; 2714 } 2715 ha->flags.hw_event_marker_found = 1; 2716 } 2717 } 2718 2719 /* Store error. */ 2720 fdata[0] = cpu_to_le32(code << 16 | d1); 2721 fdata[1] = cpu_to_le32(d2 << 16 | d3); 2722 rval = qla2xxx_hw_event_store(ha, fdata); 2723 if (rval != QLA_SUCCESS) { 2724 DEBUG2(qla_printk(KERN_WARNING, ha, 2725 "HW event -- Failed error write=%x.!\n", 2726 rval)); 2727 } 2728 2729 return rval; 2730 } 2731