1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 #include <linux/uaccess.h> 13 14 /* 15 * NVRAM support routines 16 */ 17 18 /** 19 * qla2x00_lock_nvram_access() - 20 * @ha: HA context 21 */ 22 static void 23 qla2x00_lock_nvram_access(struct qla_hw_data *ha) 24 { 25 uint16_t data; 26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 27 28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 29 data = rd_reg_word(®->nvram); 30 while (data & NVR_BUSY) { 31 udelay(100); 32 data = rd_reg_word(®->nvram); 33 } 34 35 /* Lock resource */ 36 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); 37 rd_reg_word(®->u.isp2300.host_semaphore); 38 udelay(5); 39 data = rd_reg_word(®->u.isp2300.host_semaphore); 40 while ((data & BIT_0) == 0) { 41 /* Lock failed */ 42 udelay(100); 43 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); 44 rd_reg_word(®->u.isp2300.host_semaphore); 45 udelay(5); 46 data = rd_reg_word(®->u.isp2300.host_semaphore); 47 } 48 } 49 } 50 51 /** 52 * qla2x00_unlock_nvram_access() - 53 * @ha: HA context 54 */ 55 static void 56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha) 57 { 58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 59 60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 61 wrt_reg_word(®->u.isp2300.host_semaphore, 0); 62 rd_reg_word(®->u.isp2300.host_semaphore); 63 } 64 } 65 66 /** 67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 68 * @ha: HA context 69 * @data: Serial interface selector 70 */ 71 static void 72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data) 73 { 74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 75 76 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 77 rd_reg_word(®->nvram); /* PCI Posting. */ 78 NVRAM_DELAY(); 79 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_CLOCK | 80 NVR_WRT_ENABLE); 81 rd_reg_word(®->nvram); /* PCI Posting. */ 82 NVRAM_DELAY(); 83 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 84 rd_reg_word(®->nvram); /* PCI Posting. */ 85 NVRAM_DELAY(); 86 } 87 88 /** 89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 90 * NVRAM. 91 * @ha: HA context 92 * @nv_cmd: NVRAM command 93 * 94 * Bit definitions for NVRAM command: 95 * 96 * Bit 26 = start bit 97 * Bit 25, 24 = opcode 98 * Bit 23-16 = address 99 * Bit 15-0 = write data 100 * 101 * Returns the word read from nvram @addr. 102 */ 103 static uint16_t 104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) 105 { 106 uint8_t cnt; 107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 108 uint16_t data = 0; 109 uint16_t reg_data; 110 111 /* Send command to NVRAM. */ 112 nv_cmd <<= 5; 113 for (cnt = 0; cnt < 11; cnt++) { 114 if (nv_cmd & BIT_31) 115 qla2x00_nv_write(ha, NVR_DATA_OUT); 116 else 117 qla2x00_nv_write(ha, 0); 118 nv_cmd <<= 1; 119 } 120 121 /* Read data from NVRAM. */ 122 for (cnt = 0; cnt < 16; cnt++) { 123 wrt_reg_word(®->nvram, NVR_SELECT | NVR_CLOCK); 124 rd_reg_word(®->nvram); /* PCI Posting. */ 125 NVRAM_DELAY(); 126 data <<= 1; 127 reg_data = rd_reg_word(®->nvram); 128 if (reg_data & NVR_DATA_IN) 129 data |= BIT_0; 130 wrt_reg_word(®->nvram, NVR_SELECT); 131 rd_reg_word(®->nvram); /* PCI Posting. */ 132 NVRAM_DELAY(); 133 } 134 135 /* Deselect chip. */ 136 wrt_reg_word(®->nvram, NVR_DESELECT); 137 rd_reg_word(®->nvram); /* PCI Posting. */ 138 NVRAM_DELAY(); 139 140 return data; 141 } 142 143 144 /** 145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 146 * request routine to get the word from NVRAM. 147 * @ha: HA context 148 * @addr: Address in NVRAM to read 149 * 150 * Returns the word read from nvram @addr. 151 */ 152 static uint16_t 153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) 154 { 155 uint16_t data; 156 uint32_t nv_cmd; 157 158 nv_cmd = addr << 16; 159 nv_cmd |= NV_READ_OP; 160 data = qla2x00_nvram_request(ha, nv_cmd); 161 162 return (data); 163 } 164 165 /** 166 * qla2x00_nv_deselect() - Deselect NVRAM operations. 167 * @ha: HA context 168 */ 169 static void 170 qla2x00_nv_deselect(struct qla_hw_data *ha) 171 { 172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 173 174 wrt_reg_word(®->nvram, NVR_DESELECT); 175 rd_reg_word(®->nvram); /* PCI Posting. */ 176 NVRAM_DELAY(); 177 } 178 179 /** 180 * qla2x00_write_nvram_word() - Write NVRAM data. 181 * @ha: HA context 182 * @addr: Address in NVRAM to write 183 * @data: word to program 184 */ 185 static void 186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, __le16 data) 187 { 188 int count; 189 uint16_t word; 190 uint32_t nv_cmd, wait_cnt; 191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 192 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 193 194 qla2x00_nv_write(ha, NVR_DATA_OUT); 195 qla2x00_nv_write(ha, 0); 196 qla2x00_nv_write(ha, 0); 197 198 for (word = 0; word < 8; word++) 199 qla2x00_nv_write(ha, NVR_DATA_OUT); 200 201 qla2x00_nv_deselect(ha); 202 203 /* Write data */ 204 nv_cmd = (addr << 16) | NV_WRITE_OP; 205 nv_cmd |= (__force u16)data; 206 nv_cmd <<= 5; 207 for (count = 0; count < 27; count++) { 208 if (nv_cmd & BIT_31) 209 qla2x00_nv_write(ha, NVR_DATA_OUT); 210 else 211 qla2x00_nv_write(ha, 0); 212 213 nv_cmd <<= 1; 214 } 215 216 qla2x00_nv_deselect(ha); 217 218 /* Wait for NVRAM to become ready */ 219 wrt_reg_word(®->nvram, NVR_SELECT); 220 rd_reg_word(®->nvram); /* PCI Posting. */ 221 wait_cnt = NVR_WAIT_CNT; 222 do { 223 if (!--wait_cnt) { 224 ql_dbg(ql_dbg_user, vha, 0x708d, 225 "NVRAM didn't go ready...\n"); 226 break; 227 } 228 NVRAM_DELAY(); 229 word = rd_reg_word(®->nvram); 230 } while ((word & NVR_DATA_IN) == 0); 231 232 qla2x00_nv_deselect(ha); 233 234 /* Disable writes */ 235 qla2x00_nv_write(ha, NVR_DATA_OUT); 236 for (count = 0; count < 10; count++) 237 qla2x00_nv_write(ha, 0); 238 239 qla2x00_nv_deselect(ha); 240 } 241 242 static int 243 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, 244 __le16 data, uint32_t tmo) 245 { 246 int ret, count; 247 uint16_t word; 248 uint32_t nv_cmd; 249 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 250 251 ret = QLA_SUCCESS; 252 253 qla2x00_nv_write(ha, NVR_DATA_OUT); 254 qla2x00_nv_write(ha, 0); 255 qla2x00_nv_write(ha, 0); 256 257 for (word = 0; word < 8; word++) 258 qla2x00_nv_write(ha, NVR_DATA_OUT); 259 260 qla2x00_nv_deselect(ha); 261 262 /* Write data */ 263 nv_cmd = (addr << 16) | NV_WRITE_OP; 264 nv_cmd |= (__force u16)data; 265 nv_cmd <<= 5; 266 for (count = 0; count < 27; count++) { 267 if (nv_cmd & BIT_31) 268 qla2x00_nv_write(ha, NVR_DATA_OUT); 269 else 270 qla2x00_nv_write(ha, 0); 271 272 nv_cmd <<= 1; 273 } 274 275 qla2x00_nv_deselect(ha); 276 277 /* Wait for NVRAM to become ready */ 278 wrt_reg_word(®->nvram, NVR_SELECT); 279 rd_reg_word(®->nvram); /* PCI Posting. */ 280 do { 281 NVRAM_DELAY(); 282 word = rd_reg_word(®->nvram); 283 if (!--tmo) { 284 ret = QLA_FUNCTION_FAILED; 285 break; 286 } 287 } while ((word & NVR_DATA_IN) == 0); 288 289 qla2x00_nv_deselect(ha); 290 291 /* Disable writes */ 292 qla2x00_nv_write(ha, NVR_DATA_OUT); 293 for (count = 0; count < 10; count++) 294 qla2x00_nv_write(ha, 0); 295 296 qla2x00_nv_deselect(ha); 297 298 return ret; 299 } 300 301 /** 302 * qla2x00_clear_nvram_protection() - 303 * @ha: HA context 304 */ 305 static int 306 qla2x00_clear_nvram_protection(struct qla_hw_data *ha) 307 { 308 int ret, stat; 309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 310 uint32_t word, wait_cnt; 311 __le16 wprot, wprot_old; 312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 313 314 /* Clear NVRAM write protection. */ 315 ret = QLA_FUNCTION_FAILED; 316 317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 319 cpu_to_le16(0x1234), 100000); 320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 321 if (stat != QLA_SUCCESS || wprot != cpu_to_le16(0x1234)) { 322 /* Write enable. */ 323 qla2x00_nv_write(ha, NVR_DATA_OUT); 324 qla2x00_nv_write(ha, 0); 325 qla2x00_nv_write(ha, 0); 326 for (word = 0; word < 8; word++) 327 qla2x00_nv_write(ha, NVR_DATA_OUT); 328 329 qla2x00_nv_deselect(ha); 330 331 /* Enable protection register. */ 332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 333 qla2x00_nv_write(ha, NVR_PR_ENABLE); 334 qla2x00_nv_write(ha, NVR_PR_ENABLE); 335 for (word = 0; word < 8; word++) 336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 337 338 qla2x00_nv_deselect(ha); 339 340 /* Clear protection register (ffff is cleared). */ 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 344 for (word = 0; word < 8; word++) 345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 346 347 qla2x00_nv_deselect(ha); 348 349 /* Wait for NVRAM to become ready. */ 350 wrt_reg_word(®->nvram, NVR_SELECT); 351 rd_reg_word(®->nvram); /* PCI Posting. */ 352 wait_cnt = NVR_WAIT_CNT; 353 do { 354 if (!--wait_cnt) { 355 ql_dbg(ql_dbg_user, vha, 0x708e, 356 "NVRAM didn't go ready...\n"); 357 break; 358 } 359 NVRAM_DELAY(); 360 word = rd_reg_word(®->nvram); 361 } while ((word & NVR_DATA_IN) == 0); 362 363 if (wait_cnt) 364 ret = QLA_SUCCESS; 365 } else 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 367 368 return ret; 369 } 370 371 static void 372 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) 373 { 374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 375 uint32_t word, wait_cnt; 376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 377 378 if (stat != QLA_SUCCESS) 379 return; 380 381 /* Set NVRAM write protection. */ 382 /* Write enable. */ 383 qla2x00_nv_write(ha, NVR_DATA_OUT); 384 qla2x00_nv_write(ha, 0); 385 qla2x00_nv_write(ha, 0); 386 for (word = 0; word < 8; word++) 387 qla2x00_nv_write(ha, NVR_DATA_OUT); 388 389 qla2x00_nv_deselect(ha); 390 391 /* Enable protection register. */ 392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 393 qla2x00_nv_write(ha, NVR_PR_ENABLE); 394 qla2x00_nv_write(ha, NVR_PR_ENABLE); 395 for (word = 0; word < 8; word++) 396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 397 398 qla2x00_nv_deselect(ha); 399 400 /* Enable protection register. */ 401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 402 qla2x00_nv_write(ha, NVR_PR_ENABLE); 403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 404 for (word = 0; word < 8; word++) 405 qla2x00_nv_write(ha, NVR_PR_ENABLE); 406 407 qla2x00_nv_deselect(ha); 408 409 /* Wait for NVRAM to become ready. */ 410 wrt_reg_word(®->nvram, NVR_SELECT); 411 rd_reg_word(®->nvram); /* PCI Posting. */ 412 wait_cnt = NVR_WAIT_CNT; 413 do { 414 if (!--wait_cnt) { 415 ql_dbg(ql_dbg_user, vha, 0x708f, 416 "NVRAM didn't go ready...\n"); 417 break; 418 } 419 NVRAM_DELAY(); 420 word = rd_reg_word(®->nvram); 421 } while ((word & NVR_DATA_IN) == 0); 422 } 423 424 425 /*****************************************************************************/ 426 /* Flash Manipulation Routines */ 427 /*****************************************************************************/ 428 429 static inline uint32_t 430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) 431 { 432 return ha->flash_conf_off + faddr; 433 } 434 435 static inline uint32_t 436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) 437 { 438 return ha->flash_data_off + faddr; 439 } 440 441 static inline uint32_t 442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) 443 { 444 return ha->nvram_conf_off + naddr; 445 } 446 447 static inline uint32_t 448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) 449 { 450 return ha->nvram_data_off + naddr; 451 } 452 453 static int 454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t *data) 455 { 456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 457 ulong cnt = 30000; 458 459 wrt_reg_dword(®->flash_addr, addr & ~FARX_DATA_FLAG); 460 461 while (cnt--) { 462 if (rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG) { 463 *data = rd_reg_dword(®->flash_data); 464 return QLA_SUCCESS; 465 } 466 udelay(10); 467 cond_resched(); 468 } 469 470 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 471 "Flash read dword at %x timeout.\n", addr); 472 *data = 0xDEADDEAD; 473 return QLA_FUNCTION_TIMEOUT; 474 } 475 476 int 477 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 478 uint32_t dwords) 479 { 480 ulong i; 481 int ret = QLA_SUCCESS; 482 struct qla_hw_data *ha = vha->hw; 483 484 /* Dword reads to flash. */ 485 faddr = flash_data_addr(ha, faddr); 486 for (i = 0; i < dwords; i++, faddr++, dwptr++) { 487 ret = qla24xx_read_flash_dword(ha, faddr, dwptr); 488 if (ret != QLA_SUCCESS) 489 break; 490 cpu_to_le32s(dwptr); 491 } 492 493 return ret; 494 } 495 496 static int 497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) 498 { 499 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 500 ulong cnt = 500000; 501 502 wrt_reg_dword(®->flash_data, data); 503 wrt_reg_dword(®->flash_addr, addr | FARX_DATA_FLAG); 504 505 while (cnt--) { 506 if (!(rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG)) 507 return QLA_SUCCESS; 508 udelay(10); 509 cond_resched(); 510 } 511 512 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 513 "Flash write dword at %x timeout.\n", addr); 514 return QLA_FUNCTION_TIMEOUT; 515 } 516 517 static void 518 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 519 uint8_t *flash_id) 520 { 521 uint32_t faddr, ids = 0; 522 523 *man_id = *flash_id = 0; 524 525 faddr = flash_conf_addr(ha, 0x03ab); 526 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 527 *man_id = LSB(ids); 528 *flash_id = MSB(ids); 529 } 530 531 /* Check if man_id and flash_id are valid. */ 532 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 533 /* Read information using 0x9f opcode 534 * Device ID, Mfg ID would be read in the format: 535 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 536 * Example: ATMEL 0x00 01 45 1F 537 * Extract MFG and Dev ID from last two bytes. 538 */ 539 faddr = flash_conf_addr(ha, 0x009f); 540 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 541 *man_id = LSB(ids); 542 *flash_id = MSB(ids); 543 } 544 } 545 } 546 547 static int 548 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) 549 { 550 const char *loc, *locations[] = { "DEF", "PCI" }; 551 uint32_t pcihdr, pcids; 552 uint16_t cnt, chksum; 553 __le16 *wptr; 554 struct qla_hw_data *ha = vha->hw; 555 struct req_que *req = ha->req_q_map[0]; 556 struct qla_flt_location *fltl = (void *)req->ring; 557 uint32_t *dcode = (uint32_t *)req->ring; 558 uint8_t *buf = (void *)req->ring, *bcode, last_image; 559 560 /* 561 * FLT-location structure resides after the last PCI region. 562 */ 563 564 /* Begin with sane defaults. */ 565 loc = locations[0]; 566 *start = 0; 567 if (IS_QLA24XX_TYPE(ha)) 568 *start = FA_FLASH_LAYOUT_ADDR_24; 569 else if (IS_QLA25XX(ha)) 570 *start = FA_FLASH_LAYOUT_ADDR; 571 else if (IS_QLA81XX(ha)) 572 *start = FA_FLASH_LAYOUT_ADDR_81; 573 else if (IS_P3P_TYPE(ha)) { 574 *start = FA_FLASH_LAYOUT_ADDR_82; 575 goto end; 576 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 577 *start = FA_FLASH_LAYOUT_ADDR_83; 578 goto end; 579 } else if (IS_QLA28XX(ha)) { 580 *start = FA_FLASH_LAYOUT_ADDR_28; 581 goto end; 582 } 583 584 /* Begin with first PCI expansion ROM header. */ 585 pcihdr = 0; 586 do { 587 /* Verify PCI expansion ROM header. */ 588 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 589 bcode = buf + (pcihdr % 4); 590 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) 591 goto end; 592 593 /* Locate PCI data structure. */ 594 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 595 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 596 bcode = buf + (pcihdr % 4); 597 598 /* Validate signature of PCI data structure. */ 599 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 600 bcode[0x2] != 'I' || bcode[0x3] != 'R') 601 goto end; 602 603 last_image = bcode[0x15] & BIT_7; 604 605 /* Locate next PCI expansion ROM. */ 606 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 607 } while (!last_image); 608 609 /* Now verify FLT-location structure. */ 610 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, sizeof(*fltl) >> 2); 611 if (memcmp(fltl->sig, "QFLT", 4)) 612 goto end; 613 614 wptr = (__force __le16 *)req->ring; 615 cnt = sizeof(*fltl) / sizeof(*wptr); 616 for (chksum = 0; cnt--; wptr++) 617 chksum += le16_to_cpu(*wptr); 618 if (chksum) { 619 ql_log(ql_log_fatal, vha, 0x0045, 620 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); 621 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e, 622 fltl, sizeof(*fltl)); 623 return QLA_FUNCTION_FAILED; 624 } 625 626 /* Good data. Use specified location. */ 627 loc = locations[1]; 628 *start = (le16_to_cpu(fltl->start_hi) << 16 | 629 le16_to_cpu(fltl->start_lo)) >> 2; 630 end: 631 ql_dbg(ql_dbg_init, vha, 0x0046, 632 "FLTL[%s] = 0x%x.\n", 633 loc, *start); 634 return QLA_SUCCESS; 635 } 636 637 static void 638 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) 639 { 640 const char *locations[] = { "DEF", "FLT" }, *loc = locations[1]; 641 const uint32_t def_fw[] = 642 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 }; 643 const uint32_t def_boot[] = 644 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 }; 645 const uint32_t def_vpd_nvram[] = 646 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 }; 647 const uint32_t def_vpd0[] = 648 { 0, 0, FA_VPD0_ADDR_81 }; 649 const uint32_t def_vpd1[] = 650 { 0, 0, FA_VPD1_ADDR_81 }; 651 const uint32_t def_nvram0[] = 652 { 0, 0, FA_NVRAM0_ADDR_81 }; 653 const uint32_t def_nvram1[] = 654 { 0, 0, FA_NVRAM1_ADDR_81 }; 655 const uint32_t def_fdt[] = 656 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR, 657 FA_FLASH_DESCR_ADDR_81 }; 658 const uint32_t def_npiv_conf0[] = 659 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR, 660 FA_NPIV_CONF0_ADDR_81 }; 661 const uint32_t def_npiv_conf1[] = 662 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR, 663 FA_NPIV_CONF1_ADDR_81 }; 664 const uint32_t fcp_prio_cfg0[] = 665 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25, 666 0 }; 667 const uint32_t fcp_prio_cfg1[] = 668 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25, 669 0 }; 670 671 struct qla_hw_data *ha = vha->hw; 672 uint32_t def = IS_QLA81XX(ha) ? 2 : IS_QLA25XX(ha) ? 1 : 0; 673 struct qla_flt_header *flt = ha->flt; 674 struct qla_flt_region *region = &flt->region[0]; 675 __le16 *wptr; 676 uint16_t cnt, chksum; 677 uint32_t start; 678 679 /* Assign FCP prio region since older adapters may not have FLT, or 680 FCP prio region in it's FLT. 681 */ 682 ha->flt_region_fcp_prio = (ha->port_no == 0) ? 683 fcp_prio_cfg0[def] : fcp_prio_cfg1[def]; 684 685 ha->flt_region_flt = flt_addr; 686 wptr = (__force __le16 *)ha->flt; 687 ha->isp_ops->read_optrom(vha, flt, flt_addr << 2, 688 (sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE)); 689 690 if (le16_to_cpu(*wptr) == 0xffff) 691 goto no_flash_data; 692 if (flt->version != cpu_to_le16(1)) { 693 ql_log(ql_log_warn, vha, 0x0047, 694 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 695 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 696 le16_to_cpu(flt->checksum)); 697 goto no_flash_data; 698 } 699 700 cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr); 701 for (chksum = 0; cnt--; wptr++) 702 chksum += le16_to_cpu(*wptr); 703 if (chksum) { 704 ql_log(ql_log_fatal, vha, 0x0048, 705 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 706 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 707 le16_to_cpu(flt->checksum)); 708 goto no_flash_data; 709 } 710 711 cnt = le16_to_cpu(flt->length) / sizeof(*region); 712 for ( ; cnt; cnt--, region++) { 713 /* Store addresses as DWORD offsets. */ 714 start = le32_to_cpu(region->start) >> 2; 715 ql_dbg(ql_dbg_init, vha, 0x0049, 716 "FLT[%#x]: start=%#x end=%#x size=%#x.\n", 717 le16_to_cpu(region->code), start, 718 le32_to_cpu(region->end) >> 2, 719 le32_to_cpu(region->size) >> 2); 720 if (region->attribute) 721 ql_log(ql_dbg_init, vha, 0xffff, 722 "Region %x is secure\n", region->code); 723 724 switch (le16_to_cpu(region->code)) { 725 case FLT_REG_FCOE_FW: 726 if (!IS_QLA8031(ha)) 727 break; 728 ha->flt_region_fw = start; 729 break; 730 case FLT_REG_FW: 731 if (IS_QLA8031(ha)) 732 break; 733 ha->flt_region_fw = start; 734 break; 735 case FLT_REG_BOOT_CODE: 736 ha->flt_region_boot = start; 737 break; 738 case FLT_REG_VPD_0: 739 if (IS_QLA8031(ha)) 740 break; 741 ha->flt_region_vpd_nvram = start; 742 if (IS_P3P_TYPE(ha)) 743 break; 744 if (ha->port_no == 0) 745 ha->flt_region_vpd = start; 746 break; 747 case FLT_REG_VPD_1: 748 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 749 break; 750 if (ha->port_no == 1) 751 ha->flt_region_vpd = start; 752 break; 753 case FLT_REG_VPD_2: 754 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 755 break; 756 if (ha->port_no == 2) 757 ha->flt_region_vpd = start; 758 break; 759 case FLT_REG_VPD_3: 760 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 761 break; 762 if (ha->port_no == 3) 763 ha->flt_region_vpd = start; 764 break; 765 case FLT_REG_NVRAM_0: 766 if (IS_QLA8031(ha)) 767 break; 768 if (ha->port_no == 0) 769 ha->flt_region_nvram = start; 770 break; 771 case FLT_REG_NVRAM_1: 772 if (IS_QLA8031(ha)) 773 break; 774 if (ha->port_no == 1) 775 ha->flt_region_nvram = start; 776 break; 777 case FLT_REG_NVRAM_2: 778 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 779 break; 780 if (ha->port_no == 2) 781 ha->flt_region_nvram = start; 782 break; 783 case FLT_REG_NVRAM_3: 784 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 785 break; 786 if (ha->port_no == 3) 787 ha->flt_region_nvram = start; 788 break; 789 case FLT_REG_FDT: 790 ha->flt_region_fdt = start; 791 break; 792 case FLT_REG_NPIV_CONF_0: 793 if (ha->port_no == 0) 794 ha->flt_region_npiv_conf = start; 795 break; 796 case FLT_REG_NPIV_CONF_1: 797 if (ha->port_no == 1) 798 ha->flt_region_npiv_conf = start; 799 break; 800 case FLT_REG_GOLD_FW: 801 ha->flt_region_gold_fw = start; 802 break; 803 case FLT_REG_FCP_PRIO_0: 804 if (ha->port_no == 0) 805 ha->flt_region_fcp_prio = start; 806 break; 807 case FLT_REG_FCP_PRIO_1: 808 if (ha->port_no == 1) 809 ha->flt_region_fcp_prio = start; 810 break; 811 case FLT_REG_BOOT_CODE_82XX: 812 ha->flt_region_boot = start; 813 break; 814 case FLT_REG_BOOT_CODE_8044: 815 if (IS_QLA8044(ha)) 816 ha->flt_region_boot = start; 817 break; 818 case FLT_REG_FW_82XX: 819 ha->flt_region_fw = start; 820 break; 821 case FLT_REG_CNA_FW: 822 if (IS_CNA_CAPABLE(ha)) 823 ha->flt_region_fw = start; 824 break; 825 case FLT_REG_GOLD_FW_82XX: 826 ha->flt_region_gold_fw = start; 827 break; 828 case FLT_REG_BOOTLOAD_82XX: 829 ha->flt_region_bootload = start; 830 break; 831 case FLT_REG_VPD_8XXX: 832 if (IS_CNA_CAPABLE(ha)) 833 ha->flt_region_vpd = start; 834 break; 835 case FLT_REG_FCOE_NVRAM_0: 836 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 837 break; 838 if (ha->port_no == 0) 839 ha->flt_region_nvram = start; 840 break; 841 case FLT_REG_FCOE_NVRAM_1: 842 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 843 break; 844 if (ha->port_no == 1) 845 ha->flt_region_nvram = start; 846 break; 847 case FLT_REG_IMG_PRI_27XX: 848 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 849 ha->flt_region_img_status_pri = start; 850 break; 851 case FLT_REG_IMG_SEC_27XX: 852 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 853 ha->flt_region_img_status_sec = start; 854 break; 855 case FLT_REG_FW_SEC_27XX: 856 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 857 ha->flt_region_fw_sec = start; 858 break; 859 case FLT_REG_BOOTLOAD_SEC_27XX: 860 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 861 ha->flt_region_boot_sec = start; 862 break; 863 case FLT_REG_AUX_IMG_PRI_28XX: 864 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 865 ha->flt_region_aux_img_status_pri = start; 866 break; 867 case FLT_REG_AUX_IMG_SEC_28XX: 868 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 869 ha->flt_region_aux_img_status_sec = start; 870 break; 871 case FLT_REG_NVRAM_SEC_28XX_0: 872 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 873 if (ha->port_no == 0) 874 ha->flt_region_nvram_sec = start; 875 break; 876 case FLT_REG_NVRAM_SEC_28XX_1: 877 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 878 if (ha->port_no == 1) 879 ha->flt_region_nvram_sec = start; 880 break; 881 case FLT_REG_NVRAM_SEC_28XX_2: 882 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 883 if (ha->port_no == 2) 884 ha->flt_region_nvram_sec = start; 885 break; 886 case FLT_REG_NVRAM_SEC_28XX_3: 887 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 888 if (ha->port_no == 3) 889 ha->flt_region_nvram_sec = start; 890 break; 891 case FLT_REG_VPD_SEC_27XX_0: 892 case FLT_REG_VPD_SEC_28XX_0: 893 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 894 ha->flt_region_vpd_nvram_sec = start; 895 if (ha->port_no == 0) 896 ha->flt_region_vpd_sec = start; 897 } 898 break; 899 case FLT_REG_VPD_SEC_27XX_1: 900 case FLT_REG_VPD_SEC_28XX_1: 901 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 902 if (ha->port_no == 1) 903 ha->flt_region_vpd_sec = start; 904 break; 905 case FLT_REG_VPD_SEC_27XX_2: 906 case FLT_REG_VPD_SEC_28XX_2: 907 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 908 if (ha->port_no == 2) 909 ha->flt_region_vpd_sec = start; 910 break; 911 case FLT_REG_VPD_SEC_27XX_3: 912 case FLT_REG_VPD_SEC_28XX_3: 913 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 914 if (ha->port_no == 3) 915 ha->flt_region_vpd_sec = start; 916 break; 917 } 918 } 919 goto done; 920 921 no_flash_data: 922 /* Use hardcoded defaults. */ 923 loc = locations[0]; 924 ha->flt_region_fw = def_fw[def]; 925 ha->flt_region_boot = def_boot[def]; 926 ha->flt_region_vpd_nvram = def_vpd_nvram[def]; 927 ha->flt_region_vpd = (ha->port_no == 0) ? 928 def_vpd0[def] : def_vpd1[def]; 929 ha->flt_region_nvram = (ha->port_no == 0) ? 930 def_nvram0[def] : def_nvram1[def]; 931 ha->flt_region_fdt = def_fdt[def]; 932 ha->flt_region_npiv_conf = (ha->port_no == 0) ? 933 def_npiv_conf0[def] : def_npiv_conf1[def]; 934 done: 935 ql_dbg(ql_dbg_init, vha, 0x004a, 936 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x " 937 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n", 938 loc, ha->flt_region_boot, ha->flt_region_fw, 939 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram, 940 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf, 941 ha->flt_region_fcp_prio); 942 } 943 944 static void 945 qla2xxx_get_fdt_info(scsi_qla_host_t *vha) 946 { 947 #define FLASH_BLK_SIZE_4K 0x1000 948 #define FLASH_BLK_SIZE_32K 0x8000 949 #define FLASH_BLK_SIZE_64K 0x10000 950 const char *loc, *locations[] = { "MID", "FDT" }; 951 struct qla_hw_data *ha = vha->hw; 952 struct req_que *req = ha->req_q_map[0]; 953 uint16_t cnt, chksum; 954 __le16 *wptr = (__force __le16 *)req->ring; 955 struct qla_fdt_layout *fdt = (struct qla_fdt_layout *)req->ring; 956 uint8_t man_id, flash_id; 957 uint16_t mid = 0, fid = 0; 958 959 ha->isp_ops->read_optrom(vha, fdt, ha->flt_region_fdt << 2, 960 OPTROM_BURST_DWORDS); 961 if (le16_to_cpu(*wptr) == 0xffff) 962 goto no_flash_data; 963 if (memcmp(fdt->sig, "QLID", 4)) 964 goto no_flash_data; 965 966 for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++) 967 chksum += le16_to_cpu(*wptr); 968 if (chksum) { 969 ql_dbg(ql_dbg_init, vha, 0x004c, 970 "Inconsistent FDT detected:" 971 " checksum=0x%x id=%c version0x%x.\n", chksum, 972 fdt->sig[0], le16_to_cpu(fdt->version)); 973 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113, 974 fdt, sizeof(*fdt)); 975 goto no_flash_data; 976 } 977 978 loc = locations[1]; 979 mid = le16_to_cpu(fdt->man_id); 980 fid = le16_to_cpu(fdt->id); 981 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 982 ha->fdt_wrt_enable = fdt->wrt_enable_bits; 983 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd; 984 if (IS_QLA8044(ha)) 985 ha->fdt_erase_cmd = fdt->erase_cmd; 986 else 987 ha->fdt_erase_cmd = 988 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); 989 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 990 if (fdt->unprotect_sec_cmd) { 991 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | 992 fdt->unprotect_sec_cmd); 993 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 994 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd) : 995 flash_conf_addr(ha, 0x0336); 996 } 997 goto done; 998 no_flash_data: 999 loc = locations[0]; 1000 if (IS_P3P_TYPE(ha)) { 1001 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1002 goto done; 1003 } 1004 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 1005 mid = man_id; 1006 fid = flash_id; 1007 ha->fdt_wrt_disable = 0x9c; 1008 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); 1009 switch (man_id) { 1010 case 0xbf: /* STT flash. */ 1011 if (flash_id == 0x8e) 1012 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1013 else 1014 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 1015 1016 if (flash_id == 0x80) 1017 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); 1018 break; 1019 case 0x13: /* ST M25P80. */ 1020 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1021 break; 1022 case 0x1f: /* Atmel 26DF081A. */ 1023 ha->fdt_block_size = FLASH_BLK_SIZE_4K; 1024 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); 1025 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); 1026 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); 1027 break; 1028 default: 1029 /* Default to 64 kb sector size. */ 1030 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1031 break; 1032 } 1033 done: 1034 ql_dbg(ql_dbg_init, vha, 0x004d, 1035 "FDT[%s]: (0x%x/0x%x) erase=0x%x " 1036 "pr=%x wrtd=0x%x blk=0x%x.\n", 1037 loc, mid, fid, 1038 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, 1039 ha->fdt_wrt_disable, ha->fdt_block_size); 1040 1041 } 1042 1043 static void 1044 qla2xxx_get_idc_param(scsi_qla_host_t *vha) 1045 { 1046 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 1047 __le32 *wptr; 1048 struct qla_hw_data *ha = vha->hw; 1049 struct req_que *req = ha->req_q_map[0]; 1050 1051 if (!(IS_P3P_TYPE(ha))) 1052 return; 1053 1054 wptr = (__force __le32 *)req->ring; 1055 ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8); 1056 1057 if (*wptr == cpu_to_le32(0xffffffff)) { 1058 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; 1059 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; 1060 } else { 1061 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr); 1062 wptr++; 1063 ha->fcoe_reset_timeout = le32_to_cpu(*wptr); 1064 } 1065 ql_dbg(ql_dbg_init, vha, 0x004e, 1066 "fcoe_dev_init_timeout=%d " 1067 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout, 1068 ha->fcoe_reset_timeout); 1069 return; 1070 } 1071 1072 int 1073 qla2xxx_get_flash_info(scsi_qla_host_t *vha) 1074 { 1075 int ret; 1076 uint32_t flt_addr; 1077 struct qla_hw_data *ha = vha->hw; 1078 1079 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1080 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && 1081 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1082 return QLA_SUCCESS; 1083 1084 ret = qla2xxx_find_flt_start(vha, &flt_addr); 1085 if (ret != QLA_SUCCESS) 1086 return ret; 1087 1088 qla2xxx_get_flt_info(vha, flt_addr); 1089 qla2xxx_get_fdt_info(vha); 1090 qla2xxx_get_idc_param(vha); 1091 1092 return QLA_SUCCESS; 1093 } 1094 1095 void 1096 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) 1097 { 1098 #define NPIV_CONFIG_SIZE (16*1024) 1099 void *data; 1100 __le16 *wptr; 1101 uint16_t cnt, chksum; 1102 int i; 1103 struct qla_npiv_header hdr; 1104 struct qla_npiv_entry *entry; 1105 struct qla_hw_data *ha = vha->hw; 1106 1107 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1108 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha)) 1109 return; 1110 1111 if (ha->flags.nic_core_reset_hdlr_active) 1112 return; 1113 1114 if (IS_QLA8044(ha)) 1115 return; 1116 1117 ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2, 1118 sizeof(struct qla_npiv_header)); 1119 if (hdr.version == cpu_to_le16(0xffff)) 1120 return; 1121 if (hdr.version != cpu_to_le16(1)) { 1122 ql_dbg(ql_dbg_user, vha, 0x7090, 1123 "Unsupported NPIV-Config " 1124 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1125 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1126 le16_to_cpu(hdr.checksum)); 1127 return; 1128 } 1129 1130 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); 1131 if (!data) { 1132 ql_log(ql_log_warn, vha, 0x7091, 1133 "Unable to allocate memory for data.\n"); 1134 return; 1135 } 1136 1137 ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2, 1138 NPIV_CONFIG_SIZE); 1139 1140 cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1; 1141 for (wptr = data, chksum = 0; cnt--; wptr++) 1142 chksum += le16_to_cpu(*wptr); 1143 if (chksum) { 1144 ql_dbg(ql_dbg_user, vha, 0x7092, 1145 "Inconsistent NPIV-Config " 1146 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1147 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1148 le16_to_cpu(hdr.checksum)); 1149 goto done; 1150 } 1151 1152 entry = data + sizeof(struct qla_npiv_header); 1153 cnt = le16_to_cpu(hdr.entries); 1154 for (i = 0; cnt; cnt--, entry++, i++) { 1155 uint16_t flags; 1156 struct fc_vport_identifiers vid; 1157 struct fc_vport *vport; 1158 1159 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); 1160 1161 flags = le16_to_cpu(entry->flags); 1162 if (flags == 0xffff) 1163 continue; 1164 if ((flags & BIT_0) == 0) 1165 continue; 1166 1167 memset(&vid, 0, sizeof(vid)); 1168 vid.roles = FC_PORT_ROLE_FCP_INITIATOR; 1169 vid.vport_type = FC_PORTTYPE_NPIV; 1170 vid.disable = false; 1171 vid.port_name = wwn_to_u64(entry->port_name); 1172 vid.node_name = wwn_to_u64(entry->node_name); 1173 1174 ql_dbg(ql_dbg_user, vha, 0x7093, 1175 "NPIV[%02x]: wwpn=%llx wwnn=%llx vf_id=%#x Q_qos=%#x F_qos=%#x.\n", 1176 cnt, vid.port_name, vid.node_name, 1177 le16_to_cpu(entry->vf_id), 1178 entry->q_qos, entry->f_qos); 1179 1180 if (i < QLA_PRECONFIG_VPORTS) { 1181 vport = fc_vport_create(vha->host, 0, &vid); 1182 if (!vport) 1183 ql_log(ql_log_warn, vha, 0x7094, 1184 "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n", 1185 cnt, vid.port_name, vid.node_name); 1186 } 1187 } 1188 done: 1189 kfree(data); 1190 } 1191 1192 static int 1193 qla24xx_unprotect_flash(scsi_qla_host_t *vha) 1194 { 1195 struct qla_hw_data *ha = vha->hw; 1196 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1197 1198 if (ha->flags.fac_supported) 1199 return qla81xx_fac_do_write_enable(vha, 1); 1200 1201 /* Enable flash write. */ 1202 wrt_reg_dword(®->ctrl_status, 1203 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); 1204 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1205 1206 if (!ha->fdt_wrt_disable) 1207 goto done; 1208 1209 /* Disable flash write-protection, first clear SR protection bit */ 1210 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1211 /* Then write zero again to clear remaining SR bits.*/ 1212 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1213 done: 1214 return QLA_SUCCESS; 1215 } 1216 1217 static int 1218 qla24xx_protect_flash(scsi_qla_host_t *vha) 1219 { 1220 struct qla_hw_data *ha = vha->hw; 1221 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1222 ulong cnt = 300; 1223 uint32_t faddr, dword; 1224 1225 if (ha->flags.fac_supported) 1226 return qla81xx_fac_do_write_enable(vha, 0); 1227 1228 if (!ha->fdt_wrt_disable) 1229 goto skip_wrt_protect; 1230 1231 /* Enable flash write-protection and wait for completion. */ 1232 faddr = flash_conf_addr(ha, 0x101); 1233 qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable); 1234 faddr = flash_conf_addr(ha, 0x5); 1235 while (cnt--) { 1236 if (!qla24xx_read_flash_dword(ha, faddr, &dword)) { 1237 if (!(dword & BIT_0)) 1238 break; 1239 } 1240 udelay(10); 1241 } 1242 1243 skip_wrt_protect: 1244 /* Disable flash write. */ 1245 wrt_reg_dword(®->ctrl_status, 1246 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1247 1248 return QLA_SUCCESS; 1249 } 1250 1251 static int 1252 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) 1253 { 1254 struct qla_hw_data *ha = vha->hw; 1255 uint32_t start, finish; 1256 1257 if (ha->flags.fac_supported) { 1258 start = fdata >> 2; 1259 finish = start + (ha->fdt_block_size >> 2) - 1; 1260 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha, 1261 start), flash_data_addr(ha, finish)); 1262 } 1263 1264 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, 1265 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) | 1266 ((fdata >> 16) & 0xff)); 1267 } 1268 1269 static int 1270 qla24xx_write_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr, 1271 uint32_t dwords) 1272 { 1273 int ret; 1274 ulong liter; 1275 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 1276 uint32_t sec_mask, rest_addr, fdata; 1277 dma_addr_t optrom_dma; 1278 void *optrom = NULL; 1279 struct qla_hw_data *ha = vha->hw; 1280 1281 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 1282 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1283 goto next; 1284 1285 /* Allocate dma buffer for burst write */ 1286 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 1287 &optrom_dma, GFP_KERNEL); 1288 if (!optrom) { 1289 ql_log(ql_log_warn, vha, 0x7095, 1290 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 1291 } 1292 1293 next: 1294 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1295 "Unprotect flash...\n"); 1296 ret = qla24xx_unprotect_flash(vha); 1297 if (ret) { 1298 ql_log(ql_log_warn, vha, 0x7096, 1299 "Failed to unprotect flash.\n"); 1300 goto done; 1301 } 1302 1303 rest_addr = (ha->fdt_block_size >> 2) - 1; 1304 sec_mask = ~rest_addr; 1305 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 1306 fdata = (faddr & sec_mask) << 2; 1307 1308 /* Are we at the beginning of a sector? */ 1309 if (!(faddr & rest_addr)) { 1310 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1311 "Erase sector %#x...\n", faddr); 1312 1313 ret = qla24xx_erase_sector(vha, fdata); 1314 if (ret) { 1315 ql_dbg(ql_dbg_user, vha, 0x7007, 1316 "Failed to erase sector %x.\n", faddr); 1317 break; 1318 } 1319 } 1320 1321 if (optrom) { 1322 /* If smaller than a burst remaining */ 1323 if (dwords - liter < dburst) 1324 dburst = dwords - liter; 1325 1326 /* Copy to dma buffer */ 1327 memcpy(optrom, dwptr, dburst << 2); 1328 1329 /* Burst write */ 1330 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1331 "Write burst (%#lx dwords)...\n", dburst); 1332 ret = qla2x00_load_ram(vha, optrom_dma, 1333 flash_data_addr(ha, faddr), dburst); 1334 if (!ret) { 1335 liter += dburst - 1; 1336 faddr += dburst - 1; 1337 dwptr += dburst - 1; 1338 continue; 1339 } 1340 1341 ql_log(ql_log_warn, vha, 0x7097, 1342 "Failed burst-write at %x (%p/%#llx)....\n", 1343 flash_data_addr(ha, faddr), optrom, 1344 (u64)optrom_dma); 1345 1346 dma_free_coherent(&ha->pdev->dev, 1347 OPTROM_BURST_SIZE, optrom, optrom_dma); 1348 optrom = NULL; 1349 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1350 break; 1351 ql_log(ql_log_warn, vha, 0x7098, 1352 "Reverting to slow write...\n"); 1353 } 1354 1355 /* Slow write */ 1356 ret = qla24xx_write_flash_dword(ha, 1357 flash_data_addr(ha, faddr), le32_to_cpu(*dwptr)); 1358 if (ret) { 1359 ql_dbg(ql_dbg_user, vha, 0x7006, 1360 "Failed slopw write %x (%x)\n", faddr, *dwptr); 1361 break; 1362 } 1363 } 1364 1365 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1366 "Protect flash...\n"); 1367 ret = qla24xx_protect_flash(vha); 1368 if (ret) 1369 ql_log(ql_log_warn, vha, 0x7099, 1370 "Failed to protect flash\n"); 1371 done: 1372 if (optrom) 1373 dma_free_coherent(&ha->pdev->dev, 1374 OPTROM_BURST_SIZE, optrom, optrom_dma); 1375 1376 return ret; 1377 } 1378 1379 uint8_t * 1380 qla2x00_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1381 uint32_t bytes) 1382 { 1383 uint32_t i; 1384 __le16 *wptr; 1385 struct qla_hw_data *ha = vha->hw; 1386 1387 /* Word reads to NVRAM via registers. */ 1388 wptr = buf; 1389 qla2x00_lock_nvram_access(ha); 1390 for (i = 0; i < bytes >> 1; i++, naddr++) 1391 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 1392 naddr)); 1393 qla2x00_unlock_nvram_access(ha); 1394 1395 return buf; 1396 } 1397 1398 uint8_t * 1399 qla24xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1400 uint32_t bytes) 1401 { 1402 struct qla_hw_data *ha = vha->hw; 1403 uint32_t *dwptr = buf; 1404 uint32_t i; 1405 1406 if (IS_P3P_TYPE(ha)) 1407 return buf; 1408 1409 /* Dword reads to flash. */ 1410 naddr = nvram_data_addr(ha, naddr); 1411 bytes >>= 2; 1412 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1413 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1414 break; 1415 cpu_to_le32s(dwptr); 1416 } 1417 1418 return buf; 1419 } 1420 1421 int 1422 qla2x00_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1423 uint32_t bytes) 1424 { 1425 int ret, stat; 1426 uint32_t i; 1427 uint16_t *wptr; 1428 unsigned long flags; 1429 struct qla_hw_data *ha = vha->hw; 1430 1431 ret = QLA_SUCCESS; 1432 1433 spin_lock_irqsave(&ha->hardware_lock, flags); 1434 qla2x00_lock_nvram_access(ha); 1435 1436 /* Disable NVRAM write-protection. */ 1437 stat = qla2x00_clear_nvram_protection(ha); 1438 1439 wptr = (uint16_t *)buf; 1440 for (i = 0; i < bytes >> 1; i++, naddr++) { 1441 qla2x00_write_nvram_word(ha, naddr, 1442 cpu_to_le16(*wptr)); 1443 wptr++; 1444 } 1445 1446 /* Enable NVRAM write-protection. */ 1447 qla2x00_set_nvram_protection(ha, stat); 1448 1449 qla2x00_unlock_nvram_access(ha); 1450 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1451 1452 return ret; 1453 } 1454 1455 int 1456 qla24xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1457 uint32_t bytes) 1458 { 1459 struct qla_hw_data *ha = vha->hw; 1460 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1461 __le32 *dwptr = buf; 1462 uint32_t i; 1463 int ret; 1464 1465 ret = QLA_SUCCESS; 1466 1467 if (IS_P3P_TYPE(ha)) 1468 return ret; 1469 1470 /* Enable flash write. */ 1471 wrt_reg_dword(®->ctrl_status, 1472 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); 1473 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1474 1475 /* Disable NVRAM write-protection. */ 1476 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1477 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1478 1479 /* Dword writes to flash. */ 1480 naddr = nvram_data_addr(ha, naddr); 1481 bytes >>= 2; 1482 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1483 if (qla24xx_write_flash_dword(ha, naddr, le32_to_cpu(*dwptr))) { 1484 ql_dbg(ql_dbg_user, vha, 0x709a, 1485 "Unable to program nvram address=%x data=%x.\n", 1486 naddr, *dwptr); 1487 break; 1488 } 1489 } 1490 1491 /* Enable NVRAM write-protection. */ 1492 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c); 1493 1494 /* Disable flash write. */ 1495 wrt_reg_dword(®->ctrl_status, 1496 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1497 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1498 1499 return ret; 1500 } 1501 1502 uint8_t * 1503 qla25xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1504 uint32_t bytes) 1505 { 1506 struct qla_hw_data *ha = vha->hw; 1507 uint32_t *dwptr = buf; 1508 uint32_t i; 1509 1510 /* Dword reads to flash. */ 1511 naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr); 1512 bytes >>= 2; 1513 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1514 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1515 break; 1516 1517 cpu_to_le32s(dwptr); 1518 } 1519 1520 return buf; 1521 } 1522 1523 #define RMW_BUFFER_SIZE (64 * 1024) 1524 int 1525 qla25xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1526 uint32_t bytes) 1527 { 1528 struct qla_hw_data *ha = vha->hw; 1529 uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE); 1530 1531 if (!dbuf) 1532 return QLA_MEMORY_ALLOC_FAILED; 1533 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1534 RMW_BUFFER_SIZE); 1535 memcpy(dbuf + (naddr << 2), buf, bytes); 1536 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1537 RMW_BUFFER_SIZE); 1538 vfree(dbuf); 1539 1540 return QLA_SUCCESS; 1541 } 1542 1543 static inline void 1544 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1545 { 1546 if (IS_QLA2322(ha)) { 1547 /* Flip all colors. */ 1548 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1549 /* Turn off. */ 1550 ha->beacon_color_state = 0; 1551 *pflags = GPIO_LED_ALL_OFF; 1552 } else { 1553 /* Turn on. */ 1554 ha->beacon_color_state = QLA_LED_ALL_ON; 1555 *pflags = GPIO_LED_RGA_ON; 1556 } 1557 } else { 1558 /* Flip green led only. */ 1559 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 1560 /* Turn off. */ 1561 ha->beacon_color_state = 0; 1562 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 1563 } else { 1564 /* Turn on. */ 1565 ha->beacon_color_state = QLA_LED_GRN_ON; 1566 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 1567 } 1568 } 1569 } 1570 1571 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) 1572 1573 void 1574 qla2x00_beacon_blink(struct scsi_qla_host *vha) 1575 { 1576 uint16_t gpio_enable; 1577 uint16_t gpio_data; 1578 uint16_t led_color = 0; 1579 unsigned long flags; 1580 struct qla_hw_data *ha = vha->hw; 1581 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1582 1583 if (IS_P3P_TYPE(ha)) 1584 return; 1585 1586 spin_lock_irqsave(&ha->hardware_lock, flags); 1587 1588 /* Save the Original GPIOE. */ 1589 if (ha->pio_address) { 1590 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1591 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1592 } else { 1593 gpio_enable = rd_reg_word(®->gpioe); 1594 gpio_data = rd_reg_word(®->gpiod); 1595 } 1596 1597 /* Set the modified gpio_enable values */ 1598 gpio_enable |= GPIO_LED_MASK; 1599 1600 if (ha->pio_address) { 1601 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1602 } else { 1603 wrt_reg_word(®->gpioe, gpio_enable); 1604 rd_reg_word(®->gpioe); 1605 } 1606 1607 qla2x00_flip_colors(ha, &led_color); 1608 1609 /* Clear out any previously set LED color. */ 1610 gpio_data &= ~GPIO_LED_MASK; 1611 1612 /* Set the new input LED color to GPIOD. */ 1613 gpio_data |= led_color; 1614 1615 /* Set the modified gpio_data values */ 1616 if (ha->pio_address) { 1617 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1618 } else { 1619 wrt_reg_word(®->gpiod, gpio_data); 1620 rd_reg_word(®->gpiod); 1621 } 1622 1623 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1624 } 1625 1626 int 1627 qla2x00_beacon_on(struct scsi_qla_host *vha) 1628 { 1629 uint16_t gpio_enable; 1630 uint16_t gpio_data; 1631 unsigned long flags; 1632 struct qla_hw_data *ha = vha->hw; 1633 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1634 1635 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1636 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 1637 1638 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1639 ql_log(ql_log_warn, vha, 0x709b, 1640 "Unable to update fw options (beacon on).\n"); 1641 return QLA_FUNCTION_FAILED; 1642 } 1643 1644 /* Turn off LEDs. */ 1645 spin_lock_irqsave(&ha->hardware_lock, flags); 1646 if (ha->pio_address) { 1647 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1648 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1649 } else { 1650 gpio_enable = rd_reg_word(®->gpioe); 1651 gpio_data = rd_reg_word(®->gpiod); 1652 } 1653 gpio_enable |= GPIO_LED_MASK; 1654 1655 /* Set the modified gpio_enable values. */ 1656 if (ha->pio_address) { 1657 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1658 } else { 1659 wrt_reg_word(®->gpioe, gpio_enable); 1660 rd_reg_word(®->gpioe); 1661 } 1662 1663 /* Clear out previously set LED colour. */ 1664 gpio_data &= ~GPIO_LED_MASK; 1665 if (ha->pio_address) { 1666 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1667 } else { 1668 wrt_reg_word(®->gpiod, gpio_data); 1669 rd_reg_word(®->gpiod); 1670 } 1671 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1672 1673 /* 1674 * Let the per HBA timer kick off the blinking process based on 1675 * the following flags. No need to do anything else now. 1676 */ 1677 ha->beacon_blink_led = 1; 1678 ha->beacon_color_state = 0; 1679 1680 return QLA_SUCCESS; 1681 } 1682 1683 int 1684 qla2x00_beacon_off(struct scsi_qla_host *vha) 1685 { 1686 int rval = QLA_SUCCESS; 1687 struct qla_hw_data *ha = vha->hw; 1688 1689 ha->beacon_blink_led = 0; 1690 1691 /* Set the on flag so when it gets flipped it will be off. */ 1692 if (IS_QLA2322(ha)) 1693 ha->beacon_color_state = QLA_LED_ALL_ON; 1694 else 1695 ha->beacon_color_state = QLA_LED_GRN_ON; 1696 1697 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ 1698 1699 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1700 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 1701 1702 rval = qla2x00_set_fw_options(vha, ha->fw_options); 1703 if (rval != QLA_SUCCESS) 1704 ql_log(ql_log_warn, vha, 0x709c, 1705 "Unable to update fw options (beacon off).\n"); 1706 return rval; 1707 } 1708 1709 1710 static inline void 1711 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1712 { 1713 /* Flip all colors. */ 1714 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1715 /* Turn off. */ 1716 ha->beacon_color_state = 0; 1717 *pflags = 0; 1718 } else { 1719 /* Turn on. */ 1720 ha->beacon_color_state = QLA_LED_ALL_ON; 1721 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 1722 } 1723 } 1724 1725 void 1726 qla24xx_beacon_blink(struct scsi_qla_host *vha) 1727 { 1728 uint16_t led_color = 0; 1729 uint32_t gpio_data; 1730 unsigned long flags; 1731 struct qla_hw_data *ha = vha->hw; 1732 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1733 1734 /* Save the Original GPIOD. */ 1735 spin_lock_irqsave(&ha->hardware_lock, flags); 1736 gpio_data = rd_reg_dword(®->gpiod); 1737 1738 /* Enable the gpio_data reg for update. */ 1739 gpio_data |= GPDX_LED_UPDATE_MASK; 1740 1741 wrt_reg_dword(®->gpiod, gpio_data); 1742 gpio_data = rd_reg_dword(®->gpiod); 1743 1744 /* Set the color bits. */ 1745 qla24xx_flip_colors(ha, &led_color); 1746 1747 /* Clear out any previously set LED color. */ 1748 gpio_data &= ~GPDX_LED_COLOR_MASK; 1749 1750 /* Set the new input LED color to GPIOD. */ 1751 gpio_data |= led_color; 1752 1753 /* Set the modified gpio_data values. */ 1754 wrt_reg_dword(®->gpiod, gpio_data); 1755 gpio_data = rd_reg_dword(®->gpiod); 1756 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1757 } 1758 1759 static uint32_t 1760 qla83xx_select_led_port(struct qla_hw_data *ha) 1761 { 1762 uint32_t led_select_value = 0; 1763 1764 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1765 goto out; 1766 1767 if (ha->port_no == 0) 1768 led_select_value = QLA83XX_LED_PORT0; 1769 else 1770 led_select_value = QLA83XX_LED_PORT1; 1771 1772 out: 1773 return led_select_value; 1774 } 1775 1776 void 1777 qla83xx_beacon_blink(struct scsi_qla_host *vha) 1778 { 1779 uint32_t led_select_value; 1780 struct qla_hw_data *ha = vha->hw; 1781 uint16_t led_cfg[6]; 1782 uint16_t orig_led_cfg[6]; 1783 uint32_t led_10_value, led_43_value; 1784 1785 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha) && 1786 !IS_QLA28XX(ha)) 1787 return; 1788 1789 if (!ha->beacon_blink_led) 1790 return; 1791 1792 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 1793 qla2x00_write_ram_word(vha, 0x1003, 0x40000230); 1794 qla2x00_write_ram_word(vha, 0x1004, 0x40000230); 1795 } else if (IS_QLA2031(ha)) { 1796 led_select_value = qla83xx_select_led_port(ha); 1797 1798 qla83xx_wr_reg(vha, led_select_value, 0x40000230); 1799 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230); 1800 } else if (IS_QLA8031(ha)) { 1801 led_select_value = qla83xx_select_led_port(ha); 1802 1803 qla83xx_rd_reg(vha, led_select_value, &led_10_value); 1804 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value); 1805 qla83xx_wr_reg(vha, led_select_value, 0x01f44000); 1806 msleep(500); 1807 qla83xx_wr_reg(vha, led_select_value, 0x400001f4); 1808 msleep(1000); 1809 qla83xx_wr_reg(vha, led_select_value, led_10_value); 1810 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value); 1811 } else if (IS_QLA81XX(ha)) { 1812 int rval; 1813 1814 /* Save Current */ 1815 rval = qla81xx_get_led_config(vha, orig_led_cfg); 1816 /* Do the blink */ 1817 if (rval == QLA_SUCCESS) { 1818 if (IS_QLA81XX(ha)) { 1819 led_cfg[0] = 0x4000; 1820 led_cfg[1] = 0x2000; 1821 led_cfg[2] = 0; 1822 led_cfg[3] = 0; 1823 led_cfg[4] = 0; 1824 led_cfg[5] = 0; 1825 } else { 1826 led_cfg[0] = 0x4000; 1827 led_cfg[1] = 0x4000; 1828 led_cfg[2] = 0x4000; 1829 led_cfg[3] = 0x2000; 1830 led_cfg[4] = 0; 1831 led_cfg[5] = 0x2000; 1832 } 1833 rval = qla81xx_set_led_config(vha, led_cfg); 1834 msleep(1000); 1835 if (IS_QLA81XX(ha)) { 1836 led_cfg[0] = 0x4000; 1837 led_cfg[1] = 0x2000; 1838 led_cfg[2] = 0; 1839 } else { 1840 led_cfg[0] = 0x4000; 1841 led_cfg[1] = 0x2000; 1842 led_cfg[2] = 0x4000; 1843 led_cfg[3] = 0x4000; 1844 led_cfg[4] = 0; 1845 led_cfg[5] = 0x2000; 1846 } 1847 rval = qla81xx_set_led_config(vha, led_cfg); 1848 } 1849 /* On exit, restore original (presumes no status change) */ 1850 qla81xx_set_led_config(vha, orig_led_cfg); 1851 } 1852 } 1853 1854 int 1855 qla24xx_beacon_on(struct scsi_qla_host *vha) 1856 { 1857 uint32_t gpio_data; 1858 unsigned long flags; 1859 struct qla_hw_data *ha = vha->hw; 1860 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1861 1862 if (IS_P3P_TYPE(ha)) 1863 return QLA_SUCCESS; 1864 1865 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1866 goto skip_gpio; /* let blink handle it */ 1867 1868 if (ha->beacon_blink_led == 0) { 1869 /* Enable firmware for update */ 1870 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1871 1872 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) 1873 return QLA_FUNCTION_FAILED; 1874 1875 if (qla2x00_get_fw_options(vha, ha->fw_options) != 1876 QLA_SUCCESS) { 1877 ql_log(ql_log_warn, vha, 0x7009, 1878 "Unable to update fw options (beacon on).\n"); 1879 return QLA_FUNCTION_FAILED; 1880 } 1881 1882 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1883 goto skip_gpio; 1884 1885 spin_lock_irqsave(&ha->hardware_lock, flags); 1886 gpio_data = rd_reg_dword(®->gpiod); 1887 1888 /* Enable the gpio_data reg for update. */ 1889 gpio_data |= GPDX_LED_UPDATE_MASK; 1890 wrt_reg_dword(®->gpiod, gpio_data); 1891 rd_reg_dword(®->gpiod); 1892 1893 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1894 } 1895 1896 /* So all colors blink together. */ 1897 ha->beacon_color_state = 0; 1898 1899 skip_gpio: 1900 /* Let the per HBA timer kick off the blinking process. */ 1901 ha->beacon_blink_led = 1; 1902 1903 return QLA_SUCCESS; 1904 } 1905 1906 int 1907 qla24xx_beacon_off(struct scsi_qla_host *vha) 1908 { 1909 uint32_t gpio_data; 1910 unsigned long flags; 1911 struct qla_hw_data *ha = vha->hw; 1912 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1913 1914 if (IS_P3P_TYPE(ha)) 1915 return QLA_SUCCESS; 1916 1917 if (!ha->flags.fw_started) 1918 return QLA_SUCCESS; 1919 1920 ha->beacon_blink_led = 0; 1921 1922 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1923 goto set_fw_options; 1924 1925 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1926 return QLA_SUCCESS; 1927 1928 ha->beacon_color_state = QLA_LED_ALL_ON; 1929 1930 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ 1931 1932 /* Give control back to firmware. */ 1933 spin_lock_irqsave(&ha->hardware_lock, flags); 1934 gpio_data = rd_reg_dword(®->gpiod); 1935 1936 /* Disable the gpio_data reg for update. */ 1937 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1938 wrt_reg_dword(®->gpiod, gpio_data); 1939 rd_reg_dword(®->gpiod); 1940 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1941 1942 set_fw_options: 1943 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1944 1945 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1946 ql_log(ql_log_warn, vha, 0x704d, 1947 "Unable to update fw options (beacon on).\n"); 1948 return QLA_FUNCTION_FAILED; 1949 } 1950 1951 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1952 ql_log(ql_log_warn, vha, 0x704e, 1953 "Unable to update fw options (beacon on).\n"); 1954 return QLA_FUNCTION_FAILED; 1955 } 1956 1957 return QLA_SUCCESS; 1958 } 1959 1960 1961 /* 1962 * Flash support routines 1963 */ 1964 1965 /** 1966 * qla2x00_flash_enable() - Setup flash for reading and writing. 1967 * @ha: HA context 1968 */ 1969 static void 1970 qla2x00_flash_enable(struct qla_hw_data *ha) 1971 { 1972 uint16_t data; 1973 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1974 1975 data = rd_reg_word(®->ctrl_status); 1976 data |= CSR_FLASH_ENABLE; 1977 wrt_reg_word(®->ctrl_status, data); 1978 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 1979 } 1980 1981 /** 1982 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1983 * @ha: HA context 1984 */ 1985 static void 1986 qla2x00_flash_disable(struct qla_hw_data *ha) 1987 { 1988 uint16_t data; 1989 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1990 1991 data = rd_reg_word(®->ctrl_status); 1992 data &= ~(CSR_FLASH_ENABLE); 1993 wrt_reg_word(®->ctrl_status, data); 1994 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 1995 } 1996 1997 /** 1998 * qla2x00_read_flash_byte() - Reads a byte from flash 1999 * @ha: HA context 2000 * @addr: Address in flash to read 2001 * 2002 * A word is read from the chip, but, only the lower byte is valid. 2003 * 2004 * Returns the byte read from flash @addr. 2005 */ 2006 static uint8_t 2007 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) 2008 { 2009 uint16_t data; 2010 uint16_t bank_select; 2011 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2012 2013 bank_select = rd_reg_word(®->ctrl_status); 2014 2015 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2016 /* Specify 64K address range: */ 2017 /* clear out Module Select and Flash Address bits [19:16]. */ 2018 bank_select &= ~0xf8; 2019 bank_select |= addr >> 12 & 0xf0; 2020 bank_select |= CSR_FLASH_64K_BANK; 2021 wrt_reg_word(®->ctrl_status, bank_select); 2022 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2023 2024 wrt_reg_word(®->flash_address, (uint16_t)addr); 2025 data = rd_reg_word(®->flash_data); 2026 2027 return (uint8_t)data; 2028 } 2029 2030 /* Setup bit 16 of flash address. */ 2031 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2032 bank_select |= CSR_FLASH_64K_BANK; 2033 wrt_reg_word(®->ctrl_status, bank_select); 2034 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2035 } else if (((addr & BIT_16) == 0) && 2036 (bank_select & CSR_FLASH_64K_BANK)) { 2037 bank_select &= ~(CSR_FLASH_64K_BANK); 2038 wrt_reg_word(®->ctrl_status, bank_select); 2039 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2040 } 2041 2042 /* Always perform IO mapped accesses to the FLASH registers. */ 2043 if (ha->pio_address) { 2044 uint16_t data2; 2045 2046 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2047 do { 2048 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2049 barrier(); 2050 cpu_relax(); 2051 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2052 } while (data != data2); 2053 } else { 2054 wrt_reg_word(®->flash_address, (uint16_t)addr); 2055 data = qla2x00_debounce_register(®->flash_data); 2056 } 2057 2058 return (uint8_t)data; 2059 } 2060 2061 /** 2062 * qla2x00_write_flash_byte() - Write a byte to flash 2063 * @ha: HA context 2064 * @addr: Address in flash to write 2065 * @data: Data to write 2066 */ 2067 static void 2068 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) 2069 { 2070 uint16_t bank_select; 2071 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2072 2073 bank_select = rd_reg_word(®->ctrl_status); 2074 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2075 /* Specify 64K address range: */ 2076 /* clear out Module Select and Flash Address bits [19:16]. */ 2077 bank_select &= ~0xf8; 2078 bank_select |= addr >> 12 & 0xf0; 2079 bank_select |= CSR_FLASH_64K_BANK; 2080 wrt_reg_word(®->ctrl_status, bank_select); 2081 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2082 2083 wrt_reg_word(®->flash_address, (uint16_t)addr); 2084 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2085 wrt_reg_word(®->flash_data, (uint16_t)data); 2086 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2087 2088 return; 2089 } 2090 2091 /* Setup bit 16 of flash address. */ 2092 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2093 bank_select |= CSR_FLASH_64K_BANK; 2094 wrt_reg_word(®->ctrl_status, bank_select); 2095 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2096 } else if (((addr & BIT_16) == 0) && 2097 (bank_select & CSR_FLASH_64K_BANK)) { 2098 bank_select &= ~(CSR_FLASH_64K_BANK); 2099 wrt_reg_word(®->ctrl_status, bank_select); 2100 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2101 } 2102 2103 /* Always perform IO mapped accesses to the FLASH registers. */ 2104 if (ha->pio_address) { 2105 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2106 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); 2107 } else { 2108 wrt_reg_word(®->flash_address, (uint16_t)addr); 2109 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2110 wrt_reg_word(®->flash_data, (uint16_t)data); 2111 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2112 } 2113 } 2114 2115 /** 2116 * qla2x00_poll_flash() - Polls flash for completion. 2117 * @ha: HA context 2118 * @addr: Address in flash to poll 2119 * @poll_data: Data to be polled 2120 * @man_id: Flash manufacturer ID 2121 * @flash_id: Flash ID 2122 * 2123 * This function polls the device until bit 7 of what is read matches data 2124 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed 2125 * out (a fatal error). The flash book recommeds reading bit 7 again after 2126 * reading bit 5 as a 1. 2127 * 2128 * Returns 0 on success, else non-zero. 2129 */ 2130 static int 2131 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, 2132 uint8_t man_id, uint8_t flash_id) 2133 { 2134 int status; 2135 uint8_t flash_data; 2136 uint32_t cnt; 2137 2138 status = 1; 2139 2140 /* Wait for 30 seconds for command to finish. */ 2141 poll_data &= BIT_7; 2142 for (cnt = 3000000; cnt; cnt--) { 2143 flash_data = qla2x00_read_flash_byte(ha, addr); 2144 if ((flash_data & BIT_7) == poll_data) { 2145 status = 0; 2146 break; 2147 } 2148 2149 if (man_id != 0x40 && man_id != 0xda) { 2150 if ((flash_data & BIT_5) && cnt > 2) 2151 cnt = 2; 2152 } 2153 udelay(10); 2154 barrier(); 2155 cond_resched(); 2156 } 2157 return status; 2158 } 2159 2160 /** 2161 * qla2x00_program_flash_address() - Programs a flash address 2162 * @ha: HA context 2163 * @addr: Address in flash to program 2164 * @data: Data to be written in flash 2165 * @man_id: Flash manufacturer ID 2166 * @flash_id: Flash ID 2167 * 2168 * Returns 0 on success, else non-zero. 2169 */ 2170 static int 2171 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, 2172 uint8_t data, uint8_t man_id, uint8_t flash_id) 2173 { 2174 /* Write Program Command Sequence. */ 2175 if (IS_OEM_001(ha)) { 2176 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2177 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2178 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 2179 qla2x00_write_flash_byte(ha, addr, data); 2180 } else { 2181 if (man_id == 0xda && flash_id == 0xc1) { 2182 qla2x00_write_flash_byte(ha, addr, data); 2183 if (addr & 0x7e) 2184 return 0; 2185 } else { 2186 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2187 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2188 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 2189 qla2x00_write_flash_byte(ha, addr, data); 2190 } 2191 } 2192 2193 udelay(150); 2194 2195 /* Wait for write to complete. */ 2196 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 2197 } 2198 2199 /** 2200 * qla2x00_erase_flash() - Erase the flash. 2201 * @ha: HA context 2202 * @man_id: Flash manufacturer ID 2203 * @flash_id: Flash ID 2204 * 2205 * Returns 0 on success, else non-zero. 2206 */ 2207 static int 2208 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id) 2209 { 2210 /* Individual Sector Erase Command Sequence */ 2211 if (IS_OEM_001(ha)) { 2212 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2213 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2214 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 2215 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2216 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2217 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 2218 } else { 2219 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2220 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2221 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2222 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2223 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2224 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 2225 } 2226 2227 udelay(150); 2228 2229 /* Wait for erase to complete. */ 2230 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 2231 } 2232 2233 /** 2234 * qla2x00_erase_flash_sector() - Erase a flash sector. 2235 * @ha: HA context 2236 * @addr: Flash sector to erase 2237 * @sec_mask: Sector address mask 2238 * @man_id: Flash manufacturer ID 2239 * @flash_id: Flash ID 2240 * 2241 * Returns 0 on success, else non-zero. 2242 */ 2243 static int 2244 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, 2245 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 2246 { 2247 /* Individual Sector Erase Command Sequence */ 2248 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2249 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2250 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2251 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2252 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2253 if (man_id == 0x1f && flash_id == 0x13) 2254 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 2255 else 2256 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 2257 2258 udelay(150); 2259 2260 /* Wait for erase to complete. */ 2261 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 2262 } 2263 2264 /** 2265 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 2266 * @ha: host adapter 2267 * @man_id: Flash manufacturer ID 2268 * @flash_id: Flash ID 2269 */ 2270 static void 2271 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 2272 uint8_t *flash_id) 2273 { 2274 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2275 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2276 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 2277 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 2278 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 2279 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2280 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2281 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 2282 } 2283 2284 static void 2285 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf, 2286 uint32_t saddr, uint32_t length) 2287 { 2288 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2289 uint32_t midpoint, ilength; 2290 uint8_t data; 2291 2292 midpoint = length / 2; 2293 2294 wrt_reg_word(®->nvram, 0); 2295 rd_reg_word(®->nvram); 2296 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 2297 if (ilength == midpoint) { 2298 wrt_reg_word(®->nvram, NVR_SELECT); 2299 rd_reg_word(®->nvram); 2300 } 2301 data = qla2x00_read_flash_byte(ha, saddr); 2302 if (saddr % 100) 2303 udelay(10); 2304 *tmp_buf = data; 2305 cond_resched(); 2306 } 2307 } 2308 2309 static inline void 2310 qla2x00_suspend_hba(struct scsi_qla_host *vha) 2311 { 2312 int cnt; 2313 unsigned long flags; 2314 struct qla_hw_data *ha = vha->hw; 2315 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2316 2317 /* Suspend HBA. */ 2318 scsi_block_requests(vha->host); 2319 ha->isp_ops->disable_intrs(ha); 2320 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2321 2322 /* Pause RISC. */ 2323 spin_lock_irqsave(&ha->hardware_lock, flags); 2324 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2325 rd_reg_word(®->hccr); 2326 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2327 for (cnt = 0; cnt < 30000; cnt++) { 2328 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) 2329 break; 2330 udelay(100); 2331 } 2332 } else { 2333 udelay(10); 2334 } 2335 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2336 } 2337 2338 static inline void 2339 qla2x00_resume_hba(struct scsi_qla_host *vha) 2340 { 2341 struct qla_hw_data *ha = vha->hw; 2342 2343 /* Resume HBA. */ 2344 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2345 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2346 qla2xxx_wake_dpc(vha); 2347 qla2x00_wait_for_chip_reset(vha); 2348 scsi_unblock_requests(vha->host); 2349 } 2350 2351 void * 2352 qla2x00_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2353 uint32_t offset, uint32_t length) 2354 { 2355 uint32_t addr, midpoint; 2356 uint8_t *data; 2357 struct qla_hw_data *ha = vha->hw; 2358 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2359 2360 /* Suspend HBA. */ 2361 qla2x00_suspend_hba(vha); 2362 2363 /* Go with read. */ 2364 midpoint = ha->optrom_size / 2; 2365 2366 qla2x00_flash_enable(ha); 2367 wrt_reg_word(®->nvram, 0); 2368 rd_reg_word(®->nvram); /* PCI Posting. */ 2369 for (addr = offset, data = buf; addr < length; addr++, data++) { 2370 if (addr == midpoint) { 2371 wrt_reg_word(®->nvram, NVR_SELECT); 2372 rd_reg_word(®->nvram); /* PCI Posting. */ 2373 } 2374 2375 *data = qla2x00_read_flash_byte(ha, addr); 2376 } 2377 qla2x00_flash_disable(ha); 2378 2379 /* Resume HBA. */ 2380 qla2x00_resume_hba(vha); 2381 2382 return buf; 2383 } 2384 2385 int 2386 qla2x00_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2387 uint32_t offset, uint32_t length) 2388 { 2389 2390 int rval; 2391 uint8_t man_id, flash_id, sec_number, *data; 2392 uint16_t wd; 2393 uint32_t addr, liter, sec_mask, rest_addr; 2394 struct qla_hw_data *ha = vha->hw; 2395 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2396 2397 /* Suspend HBA. */ 2398 qla2x00_suspend_hba(vha); 2399 2400 rval = QLA_SUCCESS; 2401 sec_number = 0; 2402 2403 /* Reset ISP chip. */ 2404 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 2405 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2406 2407 /* Go with write. */ 2408 qla2x00_flash_enable(ha); 2409 do { /* Loop once to provide quick error exit */ 2410 /* Structure of flash memory based on manufacturer */ 2411 if (IS_OEM_001(ha)) { 2412 /* OEM variant with special flash part. */ 2413 man_id = flash_id = 0; 2414 rest_addr = 0xffff; 2415 sec_mask = 0x10000; 2416 goto update_flash; 2417 } 2418 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 2419 switch (man_id) { 2420 case 0x20: /* ST flash. */ 2421 if (flash_id == 0xd2 || flash_id == 0xe3) { 2422 /* 2423 * ST m29w008at part - 64kb sector size with 2424 * 32kb,8kb,8kb,16kb sectors at memory address 2425 * 0xf0000. 2426 */ 2427 rest_addr = 0xffff; 2428 sec_mask = 0x10000; 2429 break; 2430 } 2431 /* 2432 * ST m29w010b part - 16kb sector size 2433 * Default to 16kb sectors 2434 */ 2435 rest_addr = 0x3fff; 2436 sec_mask = 0x1c000; 2437 break; 2438 case 0x40: /* Mostel flash. */ 2439 /* Mostel v29c51001 part - 512 byte sector size. */ 2440 rest_addr = 0x1ff; 2441 sec_mask = 0x1fe00; 2442 break; 2443 case 0xbf: /* SST flash. */ 2444 /* SST39sf10 part - 4kb sector size. */ 2445 rest_addr = 0xfff; 2446 sec_mask = 0x1f000; 2447 break; 2448 case 0xda: /* Winbond flash. */ 2449 /* Winbond W29EE011 part - 256 byte sector size. */ 2450 rest_addr = 0x7f; 2451 sec_mask = 0x1ff80; 2452 break; 2453 case 0xc2: /* Macronix flash. */ 2454 /* 64k sector size. */ 2455 if (flash_id == 0x38 || flash_id == 0x4f) { 2456 rest_addr = 0xffff; 2457 sec_mask = 0x10000; 2458 break; 2459 } 2460 /* Fall through... */ 2461 2462 case 0x1f: /* Atmel flash. */ 2463 /* 512k sector size. */ 2464 if (flash_id == 0x13) { 2465 rest_addr = 0x7fffffff; 2466 sec_mask = 0x80000000; 2467 break; 2468 } 2469 /* Fall through... */ 2470 2471 case 0x01: /* AMD flash. */ 2472 if (flash_id == 0x38 || flash_id == 0x40 || 2473 flash_id == 0x4f) { 2474 /* Am29LV081 part - 64kb sector size. */ 2475 /* Am29LV002BT part - 64kb sector size. */ 2476 rest_addr = 0xffff; 2477 sec_mask = 0x10000; 2478 break; 2479 } else if (flash_id == 0x3e) { 2480 /* 2481 * Am29LV008b part - 64kb sector size with 2482 * 32kb,8kb,8kb,16kb sector at memory address 2483 * h0xf0000. 2484 */ 2485 rest_addr = 0xffff; 2486 sec_mask = 0x10000; 2487 break; 2488 } else if (flash_id == 0x20 || flash_id == 0x6e) { 2489 /* 2490 * Am29LV010 part or AM29f010 - 16kb sector 2491 * size. 2492 */ 2493 rest_addr = 0x3fff; 2494 sec_mask = 0x1c000; 2495 break; 2496 } else if (flash_id == 0x6d) { 2497 /* Am29LV001 part - 8kb sector size. */ 2498 rest_addr = 0x1fff; 2499 sec_mask = 0x1e000; 2500 break; 2501 } 2502 /* fall through */ 2503 default: 2504 /* Default to 16 kb sector size. */ 2505 rest_addr = 0x3fff; 2506 sec_mask = 0x1c000; 2507 break; 2508 } 2509 2510 update_flash: 2511 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2512 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 2513 rval = QLA_FUNCTION_FAILED; 2514 break; 2515 } 2516 } 2517 2518 for (addr = offset, liter = 0; liter < length; liter++, 2519 addr++) { 2520 data = buf + liter; 2521 /* Are we at the beginning of a sector? */ 2522 if ((addr & rest_addr) == 0) { 2523 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2524 if (addr >= 0x10000UL) { 2525 if (((addr >> 12) & 0xf0) && 2526 ((man_id == 0x01 && 2527 flash_id == 0x3e) || 2528 (man_id == 0x20 && 2529 flash_id == 0xd2))) { 2530 sec_number++; 2531 if (sec_number == 1) { 2532 rest_addr = 2533 0x7fff; 2534 sec_mask = 2535 0x18000; 2536 } else if ( 2537 sec_number == 2 || 2538 sec_number == 3) { 2539 rest_addr = 2540 0x1fff; 2541 sec_mask = 2542 0x1e000; 2543 } else if ( 2544 sec_number == 4) { 2545 rest_addr = 2546 0x3fff; 2547 sec_mask = 2548 0x1c000; 2549 } 2550 } 2551 } 2552 } else if (addr == ha->optrom_size / 2) { 2553 wrt_reg_word(®->nvram, NVR_SELECT); 2554 rd_reg_word(®->nvram); 2555 } 2556 2557 if (flash_id == 0xda && man_id == 0xc1) { 2558 qla2x00_write_flash_byte(ha, 0x5555, 2559 0xaa); 2560 qla2x00_write_flash_byte(ha, 0x2aaa, 2561 0x55); 2562 qla2x00_write_flash_byte(ha, 0x5555, 2563 0xa0); 2564 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 2565 /* Then erase it */ 2566 if (qla2x00_erase_flash_sector(ha, 2567 addr, sec_mask, man_id, 2568 flash_id)) { 2569 rval = QLA_FUNCTION_FAILED; 2570 break; 2571 } 2572 if (man_id == 0x01 && flash_id == 0x6d) 2573 sec_number++; 2574 } 2575 } 2576 2577 if (man_id == 0x01 && flash_id == 0x6d) { 2578 if (sec_number == 1 && 2579 addr == (rest_addr - 1)) { 2580 rest_addr = 0x0fff; 2581 sec_mask = 0x1f000; 2582 } else if (sec_number == 3 && (addr & 0x7ffe)) { 2583 rest_addr = 0x3fff; 2584 sec_mask = 0x1c000; 2585 } 2586 } 2587 2588 if (qla2x00_program_flash_address(ha, addr, *data, 2589 man_id, flash_id)) { 2590 rval = QLA_FUNCTION_FAILED; 2591 break; 2592 } 2593 cond_resched(); 2594 } 2595 } while (0); 2596 qla2x00_flash_disable(ha); 2597 2598 /* Resume HBA. */ 2599 qla2x00_resume_hba(vha); 2600 2601 return rval; 2602 } 2603 2604 void * 2605 qla24xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2606 uint32_t offset, uint32_t length) 2607 { 2608 struct qla_hw_data *ha = vha->hw; 2609 2610 /* Suspend HBA. */ 2611 scsi_block_requests(vha->host); 2612 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2613 2614 /* Go with read. */ 2615 qla24xx_read_flash_data(vha, buf, offset >> 2, length >> 2); 2616 2617 /* Resume HBA. */ 2618 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2619 scsi_unblock_requests(vha->host); 2620 2621 return buf; 2622 } 2623 2624 static int 2625 qla28xx_extract_sfub_and_verify(struct scsi_qla_host *vha, uint32_t *buf, 2626 uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf) 2627 { 2628 uint32_t *p, check_sum = 0; 2629 int i; 2630 2631 p = buf + buf_size_without_sfub; 2632 2633 /* Extract SFUB from end of file */ 2634 memcpy(sfub_buf, (uint8_t *)p, 2635 sizeof(struct secure_flash_update_block)); 2636 2637 for (i = 0; i < (sizeof(struct secure_flash_update_block) >> 2); i++) 2638 check_sum += p[i]; 2639 2640 check_sum = (~check_sum) + 1; 2641 2642 if (check_sum != p[i]) { 2643 ql_log(ql_log_warn, vha, 0x7097, 2644 "SFUB checksum failed, 0x%x, 0x%x\n", 2645 check_sum, p[i]); 2646 return QLA_COMMAND_ERROR; 2647 } 2648 2649 return QLA_SUCCESS; 2650 } 2651 2652 static int 2653 qla28xx_get_flash_region(struct scsi_qla_host *vha, uint32_t start, 2654 struct qla_flt_region *region) 2655 { 2656 struct qla_hw_data *ha = vha->hw; 2657 struct qla_flt_header *flt = ha->flt; 2658 struct qla_flt_region *flt_reg = &flt->region[0]; 2659 uint16_t cnt; 2660 int rval = QLA_FUNCTION_FAILED; 2661 2662 if (!ha->flt) 2663 return QLA_FUNCTION_FAILED; 2664 2665 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 2666 for (; cnt; cnt--, flt_reg++) { 2667 if (le32_to_cpu(flt_reg->start) == start) { 2668 memcpy((uint8_t *)region, flt_reg, 2669 sizeof(struct qla_flt_region)); 2670 rval = QLA_SUCCESS; 2671 break; 2672 } 2673 } 2674 2675 return rval; 2676 } 2677 2678 static int 2679 qla28xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2680 uint32_t dwords) 2681 { 2682 struct qla_hw_data *ha = vha->hw; 2683 ulong liter; 2684 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 2685 uint32_t sec_mask, rest_addr, fdata; 2686 void *optrom = NULL; 2687 dma_addr_t optrom_dma; 2688 int rval, ret; 2689 struct secure_flash_update_block *sfub; 2690 dma_addr_t sfub_dma; 2691 uint32_t offset = faddr << 2; 2692 uint32_t buf_size_without_sfub = 0; 2693 struct qla_flt_region region; 2694 bool reset_to_rom = false; 2695 uint32_t risc_size, risc_attr = 0; 2696 __be32 *fw_array = NULL; 2697 2698 /* Retrieve region info - must be a start address passed in */ 2699 rval = qla28xx_get_flash_region(vha, offset, ®ion); 2700 2701 if (rval != QLA_SUCCESS) { 2702 ql_log(ql_log_warn, vha, 0xffff, 2703 "Invalid address %x - not a region start address\n", 2704 offset); 2705 goto done; 2706 } 2707 2708 /* Allocate dma buffer for burst write */ 2709 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2710 &optrom_dma, GFP_KERNEL); 2711 if (!optrom) { 2712 ql_log(ql_log_warn, vha, 0x7095, 2713 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 2714 rval = QLA_COMMAND_ERROR; 2715 goto done; 2716 } 2717 2718 /* 2719 * If adapter supports secure flash and region is secure 2720 * extract secure flash update block (SFUB) and verify 2721 */ 2722 if (ha->flags.secure_adapter && region.attribute) { 2723 2724 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2725 "Region %x is secure\n", region.code); 2726 2727 switch (le16_to_cpu(region.code)) { 2728 case FLT_REG_FW: 2729 case FLT_REG_FW_SEC_27XX: 2730 case FLT_REG_MPI_PRI_28XX: 2731 case FLT_REG_MPI_SEC_28XX: 2732 fw_array = (__force __be32 *)dwptr; 2733 2734 /* 1st fw array */ 2735 risc_size = be32_to_cpu(fw_array[3]); 2736 risc_attr = be32_to_cpu(fw_array[9]); 2737 2738 buf_size_without_sfub = risc_size; 2739 fw_array += risc_size; 2740 2741 /* 2nd fw array */ 2742 risc_size = be32_to_cpu(fw_array[3]); 2743 2744 buf_size_without_sfub += risc_size; 2745 fw_array += risc_size; 2746 2747 /* 1st dump template */ 2748 risc_size = be32_to_cpu(fw_array[2]); 2749 2750 /* skip header and ignore checksum */ 2751 buf_size_without_sfub += risc_size; 2752 fw_array += risc_size; 2753 2754 if (risc_attr & BIT_9) { 2755 /* 2nd dump template */ 2756 risc_size = be32_to_cpu(fw_array[2]); 2757 2758 /* skip header and ignore checksum */ 2759 buf_size_without_sfub += risc_size; 2760 fw_array += risc_size; 2761 } 2762 break; 2763 2764 case FLT_REG_PEP_PRI_28XX: 2765 case FLT_REG_PEP_SEC_28XX: 2766 fw_array = (__force __be32 *)dwptr; 2767 2768 /* 1st fw array */ 2769 risc_size = be32_to_cpu(fw_array[3]); 2770 risc_attr = be32_to_cpu(fw_array[9]); 2771 2772 buf_size_without_sfub = risc_size; 2773 fw_array += risc_size; 2774 break; 2775 2776 default: 2777 ql_log(ql_log_warn + ql_dbg_verbose, vha, 2778 0xffff, "Secure region %x not supported\n", 2779 region.code); 2780 rval = QLA_COMMAND_ERROR; 2781 goto done; 2782 } 2783 2784 sfub = dma_alloc_coherent(&ha->pdev->dev, 2785 sizeof(struct secure_flash_update_block), &sfub_dma, 2786 GFP_KERNEL); 2787 if (!sfub) { 2788 ql_log(ql_log_warn, vha, 0xffff, 2789 "Unable to allocate memory for SFUB\n"); 2790 rval = QLA_COMMAND_ERROR; 2791 goto done; 2792 } 2793 2794 rval = qla28xx_extract_sfub_and_verify(vha, dwptr, dwords, 2795 buf_size_without_sfub, (uint8_t *)sfub); 2796 2797 if (rval != QLA_SUCCESS) 2798 goto done; 2799 2800 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2801 "SFUB extract and verify successful\n"); 2802 } 2803 2804 rest_addr = (ha->fdt_block_size >> 2) - 1; 2805 sec_mask = ~rest_addr; 2806 2807 /* Lock semaphore */ 2808 rval = qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_LOCK); 2809 if (rval != QLA_SUCCESS) { 2810 ql_log(ql_log_warn, vha, 0xffff, 2811 "Unable to lock flash semaphore."); 2812 goto done; 2813 } 2814 2815 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2816 "Unprotect flash...\n"); 2817 rval = qla24xx_unprotect_flash(vha); 2818 if (rval) { 2819 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2820 ql_log(ql_log_warn, vha, 0x7096, "Failed unprotect flash\n"); 2821 goto done; 2822 } 2823 2824 for (liter = 0; liter < dwords; liter++, faddr++) { 2825 fdata = (faddr & sec_mask) << 2; 2826 2827 /* If start of sector */ 2828 if (!(faddr & rest_addr)) { 2829 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2830 "Erase sector %#x...\n", faddr); 2831 rval = qla24xx_erase_sector(vha, fdata); 2832 if (rval) { 2833 ql_dbg(ql_dbg_user, vha, 0x7007, 2834 "Failed erase sector %#x\n", faddr); 2835 goto write_protect; 2836 } 2837 } 2838 } 2839 2840 if (ha->flags.secure_adapter) { 2841 /* 2842 * If adapter supports secure flash but FW doesn't, 2843 * disable write protect, release semaphore and reset 2844 * chip to execute ROM code in order to update region securely 2845 */ 2846 if (!ha->flags.secure_fw) { 2847 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2848 "Disable Write and Release Semaphore."); 2849 rval = qla24xx_protect_flash(vha); 2850 if (rval != QLA_SUCCESS) { 2851 qla81xx_fac_semaphore_access(vha, 2852 FAC_SEMAPHORE_UNLOCK); 2853 ql_log(ql_log_warn, vha, 0xffff, 2854 "Unable to protect flash."); 2855 goto done; 2856 } 2857 2858 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2859 "Reset chip to ROM."); 2860 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2861 set_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags); 2862 qla2xxx_wake_dpc(vha); 2863 rval = qla2x00_wait_for_chip_reset(vha); 2864 if (rval != QLA_SUCCESS) { 2865 ql_log(ql_log_warn, vha, 0xffff, 2866 "Unable to reset to ROM code."); 2867 goto done; 2868 } 2869 reset_to_rom = true; 2870 ha->flags.fac_supported = 0; 2871 2872 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2873 "Lock Semaphore"); 2874 rval = qla2xxx_write_remote_register(vha, 2875 FLASH_SEMAPHORE_REGISTER_ADDR, 0x00020002); 2876 if (rval != QLA_SUCCESS) { 2877 ql_log(ql_log_warn, vha, 0xffff, 2878 "Unable to lock flash semaphore."); 2879 goto done; 2880 } 2881 2882 /* Unprotect flash */ 2883 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2884 "Enable Write."); 2885 rval = qla2x00_write_ram_word(vha, 0x7ffd0101, 0); 2886 if (rval) { 2887 ql_log(ql_log_warn, vha, 0x7096, 2888 "Failed unprotect flash\n"); 2889 goto done; 2890 } 2891 } 2892 2893 /* If region is secure, send Secure Flash MB Cmd */ 2894 if (region.attribute && buf_size_without_sfub) { 2895 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2896 "Sending Secure Flash MB Cmd\n"); 2897 rval = qla28xx_secure_flash_update(vha, 0, 2898 le16_to_cpu(region.code), 2899 buf_size_without_sfub, sfub_dma, 2900 sizeof(struct secure_flash_update_block) >> 2); 2901 if (rval != QLA_SUCCESS) { 2902 ql_log(ql_log_warn, vha, 0xffff, 2903 "Secure Flash MB Cmd failed %x.", rval); 2904 goto write_protect; 2905 } 2906 } 2907 2908 } 2909 2910 /* re-init flash offset */ 2911 faddr = offset >> 2; 2912 2913 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 2914 fdata = (faddr & sec_mask) << 2; 2915 2916 /* If smaller than a burst remaining */ 2917 if (dwords - liter < dburst) 2918 dburst = dwords - liter; 2919 2920 /* Copy to dma buffer */ 2921 memcpy(optrom, dwptr, dburst << 2); 2922 2923 /* Burst write */ 2924 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2925 "Write burst (%#lx dwords)...\n", dburst); 2926 rval = qla2x00_load_ram(vha, optrom_dma, 2927 flash_data_addr(ha, faddr), dburst); 2928 if (rval != QLA_SUCCESS) { 2929 ql_log(ql_log_warn, vha, 0x7097, 2930 "Failed burst write at %x (%p/%#llx)...\n", 2931 flash_data_addr(ha, faddr), optrom, 2932 (u64)optrom_dma); 2933 break; 2934 } 2935 2936 liter += dburst - 1; 2937 faddr += dburst - 1; 2938 dwptr += dburst - 1; 2939 continue; 2940 } 2941 2942 write_protect: 2943 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2944 "Protect flash...\n"); 2945 ret = qla24xx_protect_flash(vha); 2946 if (ret) { 2947 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2948 ql_log(ql_log_warn, vha, 0x7099, 2949 "Failed protect flash\n"); 2950 rval = QLA_COMMAND_ERROR; 2951 } 2952 2953 if (reset_to_rom == true) { 2954 /* Schedule DPC to restart the RISC */ 2955 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2956 qla2xxx_wake_dpc(vha); 2957 2958 ret = qla2x00_wait_for_hba_online(vha); 2959 if (ret != QLA_SUCCESS) { 2960 ql_log(ql_log_warn, vha, 0xffff, 2961 "Adapter did not come out of reset\n"); 2962 rval = QLA_COMMAND_ERROR; 2963 } 2964 } 2965 2966 done: 2967 if (optrom) 2968 dma_free_coherent(&ha->pdev->dev, 2969 OPTROM_BURST_SIZE, optrom, optrom_dma); 2970 2971 return rval; 2972 } 2973 2974 int 2975 qla24xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2976 uint32_t offset, uint32_t length) 2977 { 2978 int rval; 2979 struct qla_hw_data *ha = vha->hw; 2980 2981 /* Suspend HBA. */ 2982 scsi_block_requests(vha->host); 2983 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2984 2985 /* Go with write. */ 2986 if (IS_QLA28XX(ha)) 2987 rval = qla28xx_write_flash_data(vha, buf, offset >> 2, 2988 length >> 2); 2989 else 2990 rval = qla24xx_write_flash_data(vha, buf, offset >> 2, 2991 length >> 2); 2992 2993 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2994 scsi_unblock_requests(vha->host); 2995 2996 return rval; 2997 } 2998 2999 void * 3000 qla25xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 3001 uint32_t offset, uint32_t length) 3002 { 3003 int rval; 3004 dma_addr_t optrom_dma; 3005 void *optrom; 3006 uint8_t *pbuf; 3007 uint32_t faddr, left, burst; 3008 struct qla_hw_data *ha = vha->hw; 3009 3010 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 3011 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3012 goto try_fast; 3013 if (offset & 0xfff) 3014 goto slow_read; 3015 if (length < OPTROM_BURST_SIZE) 3016 goto slow_read; 3017 3018 try_fast: 3019 if (offset & 0xff) 3020 goto slow_read; 3021 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3022 &optrom_dma, GFP_KERNEL); 3023 if (!optrom) { 3024 ql_log(ql_log_warn, vha, 0x00cc, 3025 "Unable to allocate memory for optrom burst read (%x KB).\n", 3026 OPTROM_BURST_SIZE / 1024); 3027 goto slow_read; 3028 } 3029 3030 pbuf = buf; 3031 faddr = offset >> 2; 3032 left = length >> 2; 3033 burst = OPTROM_BURST_DWORDS; 3034 while (left != 0) { 3035 if (burst > left) 3036 burst = left; 3037 3038 rval = qla2x00_dump_ram(vha, optrom_dma, 3039 flash_data_addr(ha, faddr), burst); 3040 if (rval) { 3041 ql_log(ql_log_warn, vha, 0x00f5, 3042 "Unable to burst-read optrom segment (%x/%x/%llx).\n", 3043 rval, flash_data_addr(ha, faddr), 3044 (unsigned long long)optrom_dma); 3045 ql_log(ql_log_warn, vha, 0x00f6, 3046 "Reverting to slow-read.\n"); 3047 3048 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3049 optrom, optrom_dma); 3050 goto slow_read; 3051 } 3052 3053 memcpy(pbuf, optrom, burst * 4); 3054 3055 left -= burst; 3056 faddr += burst; 3057 pbuf += burst * 4; 3058 } 3059 3060 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, 3061 optrom_dma); 3062 3063 return buf; 3064 3065 slow_read: 3066 return qla24xx_read_optrom_data(vha, buf, offset, length); 3067 } 3068 3069 /** 3070 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 3071 * @ha: HA context 3072 * @pcids: Pointer to the FCODE PCI data structure 3073 * 3074 * The process of retrieving the FCODE version information is at best 3075 * described as interesting. 3076 * 3077 * Within the first 100h bytes of the image an ASCII string is present 3078 * which contains several pieces of information including the FCODE 3079 * version. Unfortunately it seems the only reliable way to retrieve 3080 * the version is by scanning for another sentinel within the string, 3081 * the FCODE build date: 3082 * 3083 * ... 2.00.02 10/17/02 ... 3084 * 3085 * Returns QLA_SUCCESS on successful retrieval of version. 3086 */ 3087 static void 3088 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) 3089 { 3090 int ret = QLA_FUNCTION_FAILED; 3091 uint32_t istart, iend, iter, vend; 3092 uint8_t do_next, rbyte, *vbyte; 3093 3094 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3095 3096 /* Skip the PCI data structure. */ 3097 istart = pcids + 3098 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 3099 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 3100 iend = istart + 0x100; 3101 do { 3102 /* Scan for the sentinel date string...eeewww. */ 3103 do_next = 0; 3104 iter = istart; 3105 while ((iter < iend) && !do_next) { 3106 iter++; 3107 if (qla2x00_read_flash_byte(ha, iter) == '/') { 3108 if (qla2x00_read_flash_byte(ha, iter + 2) == 3109 '/') 3110 do_next++; 3111 else if (qla2x00_read_flash_byte(ha, 3112 iter + 3) == '/') 3113 do_next++; 3114 } 3115 } 3116 if (!do_next) 3117 break; 3118 3119 /* Backtrack to previous ' ' (space). */ 3120 do_next = 0; 3121 while ((iter > istart) && !do_next) { 3122 iter--; 3123 if (qla2x00_read_flash_byte(ha, iter) == ' ') 3124 do_next++; 3125 } 3126 if (!do_next) 3127 break; 3128 3129 /* 3130 * Mark end of version tag, and find previous ' ' (space) or 3131 * string length (recent FCODE images -- major hack ahead!!!). 3132 */ 3133 vend = iter - 1; 3134 do_next = 0; 3135 while ((iter > istart) && !do_next) { 3136 iter--; 3137 rbyte = qla2x00_read_flash_byte(ha, iter); 3138 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 3139 do_next++; 3140 } 3141 if (!do_next) 3142 break; 3143 3144 /* Mark beginning of version tag, and copy data. */ 3145 iter++; 3146 if ((vend - iter) && 3147 ((vend - iter) < sizeof(ha->fcode_revision))) { 3148 vbyte = ha->fcode_revision; 3149 while (iter <= vend) { 3150 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 3151 iter++; 3152 } 3153 ret = QLA_SUCCESS; 3154 } 3155 } while (0); 3156 3157 if (ret != QLA_SUCCESS) 3158 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3159 } 3160 3161 int 3162 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3163 { 3164 int ret = QLA_SUCCESS; 3165 uint8_t code_type, last_image; 3166 uint32_t pcihdr, pcids; 3167 uint8_t *dbyte; 3168 uint16_t *dcode; 3169 struct qla_hw_data *ha = vha->hw; 3170 3171 if (!ha->pio_address || !mbuf) 3172 return QLA_FUNCTION_FAILED; 3173 3174 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3175 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3176 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3177 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3178 3179 qla2x00_flash_enable(ha); 3180 3181 /* Begin with first PCI expansion ROM header. */ 3182 pcihdr = 0; 3183 last_image = 1; 3184 do { 3185 /* Verify PCI expansion ROM header. */ 3186 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 3187 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 3188 /* No signature */ 3189 ql_log(ql_log_fatal, vha, 0x0050, 3190 "No matching ROM signature.\n"); 3191 ret = QLA_FUNCTION_FAILED; 3192 break; 3193 } 3194 3195 /* Locate PCI data structure. */ 3196 pcids = pcihdr + 3197 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 3198 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 3199 3200 /* Validate signature of PCI data structure. */ 3201 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 3202 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 3203 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 3204 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 3205 /* Incorrect header. */ 3206 ql_log(ql_log_fatal, vha, 0x0051, 3207 "PCI data struct not found pcir_adr=%x.\n", pcids); 3208 ret = QLA_FUNCTION_FAILED; 3209 break; 3210 } 3211 3212 /* Read version */ 3213 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 3214 switch (code_type) { 3215 case ROM_CODE_TYPE_BIOS: 3216 /* Intel x86, PC-AT compatible. */ 3217 ha->bios_revision[0] = 3218 qla2x00_read_flash_byte(ha, pcids + 0x12); 3219 ha->bios_revision[1] = 3220 qla2x00_read_flash_byte(ha, pcids + 0x13); 3221 ql_dbg(ql_dbg_init, vha, 0x0052, 3222 "Read BIOS %d.%d.\n", 3223 ha->bios_revision[1], ha->bios_revision[0]); 3224 break; 3225 case ROM_CODE_TYPE_FCODE: 3226 /* Open Firmware standard for PCI (FCode). */ 3227 /* Eeeewww... */ 3228 qla2x00_get_fcode_version(ha, pcids); 3229 break; 3230 case ROM_CODE_TYPE_EFI: 3231 /* Extensible Firmware Interface (EFI). */ 3232 ha->efi_revision[0] = 3233 qla2x00_read_flash_byte(ha, pcids + 0x12); 3234 ha->efi_revision[1] = 3235 qla2x00_read_flash_byte(ha, pcids + 0x13); 3236 ql_dbg(ql_dbg_init, vha, 0x0053, 3237 "Read EFI %d.%d.\n", 3238 ha->efi_revision[1], ha->efi_revision[0]); 3239 break; 3240 default: 3241 ql_log(ql_log_warn, vha, 0x0054, 3242 "Unrecognized code type %x at pcids %x.\n", 3243 code_type, pcids); 3244 break; 3245 } 3246 3247 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 3248 3249 /* Locate next PCI expansion ROM. */ 3250 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 3251 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 3252 } while (!last_image); 3253 3254 if (IS_QLA2322(ha)) { 3255 /* Read firmware image information. */ 3256 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3257 dbyte = mbuf; 3258 memset(dbyte, 0, 8); 3259 dcode = (uint16_t *)dbyte; 3260 3261 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, 3262 8); 3263 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a, 3264 "Dumping fw " 3265 "ver from flash:.\n"); 3266 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b, 3267 dbyte, 32); 3268 3269 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 3270 dcode[2] == 0xffff && dcode[3] == 0xffff) || 3271 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 3272 dcode[3] == 0)) { 3273 ql_log(ql_log_warn, vha, 0x0057, 3274 "Unrecognized fw revision at %x.\n", 3275 ha->flt_region_fw * 4); 3276 } else { 3277 /* values are in big endian */ 3278 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 3279 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 3280 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 3281 ql_dbg(ql_dbg_init, vha, 0x0058, 3282 "FW Version: " 3283 "%d.%d.%d.\n", ha->fw_revision[0], 3284 ha->fw_revision[1], ha->fw_revision[2]); 3285 } 3286 } 3287 3288 qla2x00_flash_disable(ha); 3289 3290 return ret; 3291 } 3292 3293 int 3294 qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3295 { 3296 int ret = QLA_SUCCESS; 3297 uint32_t pcihdr, pcids; 3298 uint32_t *dcode = mbuf; 3299 uint8_t *bcode = mbuf; 3300 uint8_t code_type, last_image; 3301 struct qla_hw_data *ha = vha->hw; 3302 3303 if (!mbuf) 3304 return QLA_FUNCTION_FAILED; 3305 3306 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3307 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3308 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3309 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3310 3311 /* Begin with first PCI expansion ROM header. */ 3312 pcihdr = ha->flt_region_boot << 2; 3313 last_image = 1; 3314 do { 3315 /* Verify PCI expansion ROM header. */ 3316 ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4); 3317 bcode = mbuf + (pcihdr % 4); 3318 if (memcmp(bcode, "\x55\xaa", 2)) { 3319 /* No signature */ 3320 ql_log(ql_log_fatal, vha, 0x0154, 3321 "No matching ROM signature.\n"); 3322 ret = QLA_FUNCTION_FAILED; 3323 break; 3324 } 3325 3326 /* Locate PCI data structure. */ 3327 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3328 3329 ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4); 3330 bcode = mbuf + (pcihdr % 4); 3331 3332 /* Validate signature of PCI data structure. */ 3333 if (memcmp(bcode, "PCIR", 4)) { 3334 /* Incorrect header. */ 3335 ql_log(ql_log_fatal, vha, 0x0155, 3336 "PCI data struct not found pcir_adr=%x.\n", pcids); 3337 ret = QLA_FUNCTION_FAILED; 3338 break; 3339 } 3340 3341 /* Read version */ 3342 code_type = bcode[0x14]; 3343 switch (code_type) { 3344 case ROM_CODE_TYPE_BIOS: 3345 /* Intel x86, PC-AT compatible. */ 3346 ha->bios_revision[0] = bcode[0x12]; 3347 ha->bios_revision[1] = bcode[0x13]; 3348 ql_dbg(ql_dbg_init, vha, 0x0156, 3349 "Read BIOS %d.%d.\n", 3350 ha->bios_revision[1], ha->bios_revision[0]); 3351 break; 3352 case ROM_CODE_TYPE_FCODE: 3353 /* Open Firmware standard for PCI (FCode). */ 3354 ha->fcode_revision[0] = bcode[0x12]; 3355 ha->fcode_revision[1] = bcode[0x13]; 3356 ql_dbg(ql_dbg_init, vha, 0x0157, 3357 "Read FCODE %d.%d.\n", 3358 ha->fcode_revision[1], ha->fcode_revision[0]); 3359 break; 3360 case ROM_CODE_TYPE_EFI: 3361 /* Extensible Firmware Interface (EFI). */ 3362 ha->efi_revision[0] = bcode[0x12]; 3363 ha->efi_revision[1] = bcode[0x13]; 3364 ql_dbg(ql_dbg_init, vha, 0x0158, 3365 "Read EFI %d.%d.\n", 3366 ha->efi_revision[1], ha->efi_revision[0]); 3367 break; 3368 default: 3369 ql_log(ql_log_warn, vha, 0x0159, 3370 "Unrecognized code type %x at pcids %x.\n", 3371 code_type, pcids); 3372 break; 3373 } 3374 3375 last_image = bcode[0x15] & BIT_7; 3376 3377 /* Locate next PCI expansion ROM. */ 3378 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3379 } while (!last_image); 3380 3381 /* Read firmware image information. */ 3382 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3383 dcode = mbuf; 3384 ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20); 3385 bcode = mbuf + (pcihdr % 4); 3386 3387 /* Validate signature of PCI data structure. */ 3388 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 && 3389 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) { 3390 ha->fw_revision[0] = bcode[0x4]; 3391 ha->fw_revision[1] = bcode[0x5]; 3392 ha->fw_revision[2] = bcode[0x6]; 3393 ql_dbg(ql_dbg_init, vha, 0x0153, 3394 "Firmware revision %d.%d.%d\n", 3395 ha->fw_revision[0], ha->fw_revision[1], 3396 ha->fw_revision[2]); 3397 } 3398 3399 return ret; 3400 } 3401 3402 int 3403 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3404 { 3405 int ret = QLA_SUCCESS; 3406 uint32_t pcihdr = 0, pcids = 0; 3407 uint32_t *dcode = mbuf; 3408 uint8_t *bcode = mbuf; 3409 uint8_t code_type, last_image; 3410 int i; 3411 struct qla_hw_data *ha = vha->hw; 3412 uint32_t faddr = 0; 3413 struct active_regions active_regions = { }; 3414 3415 if (IS_P3P_TYPE(ha)) 3416 return ret; 3417 3418 if (!mbuf) 3419 return QLA_FUNCTION_FAILED; 3420 3421 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3422 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3423 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3424 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3425 3426 pcihdr = ha->flt_region_boot << 2; 3427 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3428 qla27xx_get_active_image(vha, &active_regions); 3429 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) { 3430 pcihdr = ha->flt_region_boot_sec << 2; 3431 } 3432 } 3433 3434 do { 3435 /* Verify PCI expansion ROM header. */ 3436 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 3437 bcode = mbuf + (pcihdr % 4); 3438 if (memcmp(bcode, "\x55\xaa", 2)) { 3439 /* No signature */ 3440 ql_log(ql_log_fatal, vha, 0x0059, 3441 "No matching ROM signature.\n"); 3442 ret = QLA_FUNCTION_FAILED; 3443 break; 3444 } 3445 3446 /* Locate PCI data structure. */ 3447 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3448 3449 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 3450 bcode = mbuf + (pcihdr % 4); 3451 3452 /* Validate signature of PCI data structure. */ 3453 if (memcmp(bcode, "PCIR", 4)) { 3454 /* Incorrect header. */ 3455 ql_log(ql_log_fatal, vha, 0x005a, 3456 "PCI data struct not found pcir_adr=%x.\n", pcids); 3457 ql_dump_buffer(ql_dbg_init, vha, 0x0059, dcode, 32); 3458 ret = QLA_FUNCTION_FAILED; 3459 break; 3460 } 3461 3462 /* Read version */ 3463 code_type = bcode[0x14]; 3464 switch (code_type) { 3465 case ROM_CODE_TYPE_BIOS: 3466 /* Intel x86, PC-AT compatible. */ 3467 ha->bios_revision[0] = bcode[0x12]; 3468 ha->bios_revision[1] = bcode[0x13]; 3469 ql_dbg(ql_dbg_init, vha, 0x005b, 3470 "Read BIOS %d.%d.\n", 3471 ha->bios_revision[1], ha->bios_revision[0]); 3472 break; 3473 case ROM_CODE_TYPE_FCODE: 3474 /* Open Firmware standard for PCI (FCode). */ 3475 ha->fcode_revision[0] = bcode[0x12]; 3476 ha->fcode_revision[1] = bcode[0x13]; 3477 ql_dbg(ql_dbg_init, vha, 0x005c, 3478 "Read FCODE %d.%d.\n", 3479 ha->fcode_revision[1], ha->fcode_revision[0]); 3480 break; 3481 case ROM_CODE_TYPE_EFI: 3482 /* Extensible Firmware Interface (EFI). */ 3483 ha->efi_revision[0] = bcode[0x12]; 3484 ha->efi_revision[1] = bcode[0x13]; 3485 ql_dbg(ql_dbg_init, vha, 0x005d, 3486 "Read EFI %d.%d.\n", 3487 ha->efi_revision[1], ha->efi_revision[0]); 3488 break; 3489 default: 3490 ql_log(ql_log_warn, vha, 0x005e, 3491 "Unrecognized code type %x at pcids %x.\n", 3492 code_type, pcids); 3493 break; 3494 } 3495 3496 last_image = bcode[0x15] & BIT_7; 3497 3498 /* Locate next PCI expansion ROM. */ 3499 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3500 } while (!last_image); 3501 3502 /* Read firmware image information. */ 3503 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3504 faddr = ha->flt_region_fw; 3505 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3506 qla27xx_get_active_image(vha, &active_regions); 3507 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) 3508 faddr = ha->flt_region_fw_sec; 3509 } 3510 3511 qla24xx_read_flash_data(vha, dcode, faddr, 8); 3512 if (qla24xx_risc_firmware_invalid(dcode)) { 3513 ql_log(ql_log_warn, vha, 0x005f, 3514 "Unrecognized fw revision at %x.\n", 3515 ha->flt_region_fw * 4); 3516 ql_dump_buffer(ql_dbg_init, vha, 0x005f, dcode, 32); 3517 } else { 3518 for (i = 0; i < 4; i++) 3519 ha->fw_revision[i] = 3520 be32_to_cpu((__force __be32)dcode[4+i]); 3521 ql_dbg(ql_dbg_init, vha, 0x0060, 3522 "Firmware revision (flash) %u.%u.%u (%x).\n", 3523 ha->fw_revision[0], ha->fw_revision[1], 3524 ha->fw_revision[2], ha->fw_revision[3]); 3525 } 3526 3527 /* Check for golden firmware and get version if available */ 3528 if (!IS_QLA81XX(ha)) { 3529 /* Golden firmware is not present in non 81XX adapters */ 3530 return ret; 3531 } 3532 3533 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); 3534 faddr = ha->flt_region_gold_fw; 3535 qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8); 3536 if (qla24xx_risc_firmware_invalid(dcode)) { 3537 ql_log(ql_log_warn, vha, 0x0056, 3538 "Unrecognized golden fw at %#x.\n", faddr); 3539 ql_dump_buffer(ql_dbg_init, vha, 0x0056, dcode, 32); 3540 return ret; 3541 } 3542 3543 for (i = 0; i < 4; i++) 3544 ha->gold_fw_version[i] = 3545 be32_to_cpu((__force __be32)dcode[4+i]); 3546 3547 return ret; 3548 } 3549 3550 static int 3551 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) 3552 { 3553 if (pos >= end || *pos != 0x82) 3554 return 0; 3555 3556 pos += 3 + pos[1]; 3557 if (pos >= end || *pos != 0x90) 3558 return 0; 3559 3560 pos += 3 + pos[1]; 3561 if (pos >= end || *pos != 0x78) 3562 return 0; 3563 3564 return 1; 3565 } 3566 3567 int 3568 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) 3569 { 3570 struct qla_hw_data *ha = vha->hw; 3571 uint8_t *pos = ha->vpd; 3572 uint8_t *end = pos + ha->vpd_size; 3573 int len = 0; 3574 3575 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) 3576 return 0; 3577 3578 while (pos < end && *pos != 0x78) { 3579 len = (*pos == 0x82) ? pos[1] : pos[2]; 3580 3581 if (!strncmp(pos, key, strlen(key))) 3582 break; 3583 3584 if (*pos != 0x90 && *pos != 0x91) 3585 pos += len; 3586 3587 pos += 3; 3588 } 3589 3590 if (pos < end - len && *pos != 0x78) 3591 return scnprintf(str, size, "%.*s", len, pos + 3); 3592 3593 return 0; 3594 } 3595 3596 int 3597 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha) 3598 { 3599 int len, max_len; 3600 uint32_t fcp_prio_addr; 3601 struct qla_hw_data *ha = vha->hw; 3602 3603 if (!ha->fcp_prio_cfg) { 3604 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); 3605 if (!ha->fcp_prio_cfg) { 3606 ql_log(ql_log_warn, vha, 0x00d5, 3607 "Unable to allocate memory for fcp priority data (%x).\n", 3608 FCP_PRIO_CFG_SIZE); 3609 return QLA_FUNCTION_FAILED; 3610 } 3611 } 3612 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); 3613 3614 fcp_prio_addr = ha->flt_region_fcp_prio; 3615 3616 /* first read the fcp priority data header from flash */ 3617 ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg, 3618 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE); 3619 3620 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0)) 3621 goto fail; 3622 3623 /* read remaining FCP CMD config data from flash */ 3624 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2); 3625 len = ha->fcp_prio_cfg->num_entries * sizeof(struct qla_fcp_prio_entry); 3626 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; 3627 3628 ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0], 3629 fcp_prio_addr << 2, (len < max_len ? len : max_len)); 3630 3631 /* revalidate the entire FCP priority config data, including entries */ 3632 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1)) 3633 goto fail; 3634 3635 ha->flags.fcp_prio_enabled = 1; 3636 return QLA_SUCCESS; 3637 fail: 3638 vfree(ha->fcp_prio_cfg); 3639 ha->fcp_prio_cfg = NULL; 3640 return QLA_FUNCTION_FAILED; 3641 } 3642