1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 #include <asm/uaccess.h> 13 14 /* 15 * NVRAM support routines 16 */ 17 18 /** 19 * qla2x00_lock_nvram_access() - 20 * @ha: HA context 21 */ 22 static void 23 qla2x00_lock_nvram_access(struct qla_hw_data *ha) 24 { 25 uint16_t data; 26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 27 28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 29 data = RD_REG_WORD(®->nvram); 30 while (data & NVR_BUSY) { 31 udelay(100); 32 data = RD_REG_WORD(®->nvram); 33 } 34 35 /* Lock resource */ 36 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 37 RD_REG_WORD(®->u.isp2300.host_semaphore); 38 udelay(5); 39 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 40 while ((data & BIT_0) == 0) { 41 /* Lock failed */ 42 udelay(100); 43 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 44 RD_REG_WORD(®->u.isp2300.host_semaphore); 45 udelay(5); 46 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 47 } 48 } 49 } 50 51 /** 52 * qla2x00_unlock_nvram_access() - 53 * @ha: HA context 54 */ 55 static void 56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha) 57 { 58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 59 60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 61 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); 62 RD_REG_WORD(®->u.isp2300.host_semaphore); 63 } 64 } 65 66 /** 67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 68 * @ha: HA context 69 * @data: Serial interface selector 70 */ 71 static void 72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data) 73 { 74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 75 76 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 77 RD_REG_WORD(®->nvram); /* PCI Posting. */ 78 NVRAM_DELAY(); 79 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK | 80 NVR_WRT_ENABLE); 81 RD_REG_WORD(®->nvram); /* PCI Posting. */ 82 NVRAM_DELAY(); 83 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 84 RD_REG_WORD(®->nvram); /* PCI Posting. */ 85 NVRAM_DELAY(); 86 } 87 88 /** 89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 90 * NVRAM. 91 * @ha: HA context 92 * @nv_cmd: NVRAM command 93 * 94 * Bit definitions for NVRAM command: 95 * 96 * Bit 26 = start bit 97 * Bit 25, 24 = opcode 98 * Bit 23-16 = address 99 * Bit 15-0 = write data 100 * 101 * Returns the word read from nvram @addr. 102 */ 103 static uint16_t 104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) 105 { 106 uint8_t cnt; 107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 108 uint16_t data = 0; 109 uint16_t reg_data; 110 111 /* Send command to NVRAM. */ 112 nv_cmd <<= 5; 113 for (cnt = 0; cnt < 11; cnt++) { 114 if (nv_cmd & BIT_31) 115 qla2x00_nv_write(ha, NVR_DATA_OUT); 116 else 117 qla2x00_nv_write(ha, 0); 118 nv_cmd <<= 1; 119 } 120 121 /* Read data from NVRAM. */ 122 for (cnt = 0; cnt < 16; cnt++) { 123 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); 124 RD_REG_WORD(®->nvram); /* PCI Posting. */ 125 NVRAM_DELAY(); 126 data <<= 1; 127 reg_data = RD_REG_WORD(®->nvram); 128 if (reg_data & NVR_DATA_IN) 129 data |= BIT_0; 130 WRT_REG_WORD(®->nvram, NVR_SELECT); 131 RD_REG_WORD(®->nvram); /* PCI Posting. */ 132 NVRAM_DELAY(); 133 } 134 135 /* Deselect chip. */ 136 WRT_REG_WORD(®->nvram, NVR_DESELECT); 137 RD_REG_WORD(®->nvram); /* PCI Posting. */ 138 NVRAM_DELAY(); 139 140 return data; 141 } 142 143 144 /** 145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 146 * request routine to get the word from NVRAM. 147 * @ha: HA context 148 * @addr: Address in NVRAM to read 149 * 150 * Returns the word read from nvram @addr. 151 */ 152 static uint16_t 153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) 154 { 155 uint16_t data; 156 uint32_t nv_cmd; 157 158 nv_cmd = addr << 16; 159 nv_cmd |= NV_READ_OP; 160 data = qla2x00_nvram_request(ha, nv_cmd); 161 162 return (data); 163 } 164 165 /** 166 * qla2x00_nv_deselect() - Deselect NVRAM operations. 167 * @ha: HA context 168 */ 169 static void 170 qla2x00_nv_deselect(struct qla_hw_data *ha) 171 { 172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 173 174 WRT_REG_WORD(®->nvram, NVR_DESELECT); 175 RD_REG_WORD(®->nvram); /* PCI Posting. */ 176 NVRAM_DELAY(); 177 } 178 179 /** 180 * qla2x00_write_nvram_word() - Write NVRAM data. 181 * @ha: HA context 182 * @addr: Address in NVRAM to write 183 * @data: word to program 184 */ 185 static void 186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data) 187 { 188 int count; 189 uint16_t word; 190 uint32_t nv_cmd, wait_cnt; 191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 192 193 qla2x00_nv_write(ha, NVR_DATA_OUT); 194 qla2x00_nv_write(ha, 0); 195 qla2x00_nv_write(ha, 0); 196 197 for (word = 0; word < 8; word++) 198 qla2x00_nv_write(ha, NVR_DATA_OUT); 199 200 qla2x00_nv_deselect(ha); 201 202 /* Write data */ 203 nv_cmd = (addr << 16) | NV_WRITE_OP; 204 nv_cmd |= data; 205 nv_cmd <<= 5; 206 for (count = 0; count < 27; count++) { 207 if (nv_cmd & BIT_31) 208 qla2x00_nv_write(ha, NVR_DATA_OUT); 209 else 210 qla2x00_nv_write(ha, 0); 211 212 nv_cmd <<= 1; 213 } 214 215 qla2x00_nv_deselect(ha); 216 217 /* Wait for NVRAM to become ready */ 218 WRT_REG_WORD(®->nvram, NVR_SELECT); 219 RD_REG_WORD(®->nvram); /* PCI Posting. */ 220 wait_cnt = NVR_WAIT_CNT; 221 do { 222 if (!--wait_cnt) { 223 DEBUG9_10(qla_printk(KERN_WARNING, ha, 224 "NVRAM didn't go ready...\n")); 225 break; 226 } 227 NVRAM_DELAY(); 228 word = RD_REG_WORD(®->nvram); 229 } while ((word & NVR_DATA_IN) == 0); 230 231 qla2x00_nv_deselect(ha); 232 233 /* Disable writes */ 234 qla2x00_nv_write(ha, NVR_DATA_OUT); 235 for (count = 0; count < 10; count++) 236 qla2x00_nv_write(ha, 0); 237 238 qla2x00_nv_deselect(ha); 239 } 240 241 static int 242 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, 243 uint16_t data, uint32_t tmo) 244 { 245 int ret, count; 246 uint16_t word; 247 uint32_t nv_cmd; 248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 249 250 ret = QLA_SUCCESS; 251 252 qla2x00_nv_write(ha, NVR_DATA_OUT); 253 qla2x00_nv_write(ha, 0); 254 qla2x00_nv_write(ha, 0); 255 256 for (word = 0; word < 8; word++) 257 qla2x00_nv_write(ha, NVR_DATA_OUT); 258 259 qla2x00_nv_deselect(ha); 260 261 /* Write data */ 262 nv_cmd = (addr << 16) | NV_WRITE_OP; 263 nv_cmd |= data; 264 nv_cmd <<= 5; 265 for (count = 0; count < 27; count++) { 266 if (nv_cmd & BIT_31) 267 qla2x00_nv_write(ha, NVR_DATA_OUT); 268 else 269 qla2x00_nv_write(ha, 0); 270 271 nv_cmd <<= 1; 272 } 273 274 qla2x00_nv_deselect(ha); 275 276 /* Wait for NVRAM to become ready */ 277 WRT_REG_WORD(®->nvram, NVR_SELECT); 278 RD_REG_WORD(®->nvram); /* PCI Posting. */ 279 do { 280 NVRAM_DELAY(); 281 word = RD_REG_WORD(®->nvram); 282 if (!--tmo) { 283 ret = QLA_FUNCTION_FAILED; 284 break; 285 } 286 } while ((word & NVR_DATA_IN) == 0); 287 288 qla2x00_nv_deselect(ha); 289 290 /* Disable writes */ 291 qla2x00_nv_write(ha, NVR_DATA_OUT); 292 for (count = 0; count < 10; count++) 293 qla2x00_nv_write(ha, 0); 294 295 qla2x00_nv_deselect(ha); 296 297 return ret; 298 } 299 300 /** 301 * qla2x00_clear_nvram_protection() - 302 * @ha: HA context 303 */ 304 static int 305 qla2x00_clear_nvram_protection(struct qla_hw_data *ha) 306 { 307 int ret, stat; 308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 309 uint32_t word, wait_cnt; 310 uint16_t wprot, wprot_old; 311 312 /* Clear NVRAM write protection. */ 313 ret = QLA_FUNCTION_FAILED; 314 315 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 316 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 317 __constant_cpu_to_le16(0x1234), 100000); 318 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 319 if (stat != QLA_SUCCESS || wprot != 0x1234) { 320 /* Write enable. */ 321 qla2x00_nv_write(ha, NVR_DATA_OUT); 322 qla2x00_nv_write(ha, 0); 323 qla2x00_nv_write(ha, 0); 324 for (word = 0; word < 8; word++) 325 qla2x00_nv_write(ha, NVR_DATA_OUT); 326 327 qla2x00_nv_deselect(ha); 328 329 /* Enable protection register. */ 330 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 331 qla2x00_nv_write(ha, NVR_PR_ENABLE); 332 qla2x00_nv_write(ha, NVR_PR_ENABLE); 333 for (word = 0; word < 8; word++) 334 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 335 336 qla2x00_nv_deselect(ha); 337 338 /* Clear protection register (ffff is cleared). */ 339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 for (word = 0; word < 8; word++) 343 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 344 345 qla2x00_nv_deselect(ha); 346 347 /* Wait for NVRAM to become ready. */ 348 WRT_REG_WORD(®->nvram, NVR_SELECT); 349 RD_REG_WORD(®->nvram); /* PCI Posting. */ 350 wait_cnt = NVR_WAIT_CNT; 351 do { 352 if (!--wait_cnt) { 353 DEBUG9_10(qla_printk(KERN_WARNING, ha, 354 "NVRAM didn't go ready...\n")); 355 break; 356 } 357 NVRAM_DELAY(); 358 word = RD_REG_WORD(®->nvram); 359 } while ((word & NVR_DATA_IN) == 0); 360 361 if (wait_cnt) 362 ret = QLA_SUCCESS; 363 } else 364 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 365 366 return ret; 367 } 368 369 static void 370 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) 371 { 372 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 373 uint32_t word, wait_cnt; 374 375 if (stat != QLA_SUCCESS) 376 return; 377 378 /* Set NVRAM write protection. */ 379 /* Write enable. */ 380 qla2x00_nv_write(ha, NVR_DATA_OUT); 381 qla2x00_nv_write(ha, 0); 382 qla2x00_nv_write(ha, 0); 383 for (word = 0; word < 8; word++) 384 qla2x00_nv_write(ha, NVR_DATA_OUT); 385 386 qla2x00_nv_deselect(ha); 387 388 /* Enable protection register. */ 389 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 390 qla2x00_nv_write(ha, NVR_PR_ENABLE); 391 qla2x00_nv_write(ha, NVR_PR_ENABLE); 392 for (word = 0; word < 8; word++) 393 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 394 395 qla2x00_nv_deselect(ha); 396 397 /* Enable protection register. */ 398 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 399 qla2x00_nv_write(ha, NVR_PR_ENABLE); 400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 401 for (word = 0; word < 8; word++) 402 qla2x00_nv_write(ha, NVR_PR_ENABLE); 403 404 qla2x00_nv_deselect(ha); 405 406 /* Wait for NVRAM to become ready. */ 407 WRT_REG_WORD(®->nvram, NVR_SELECT); 408 RD_REG_WORD(®->nvram); /* PCI Posting. */ 409 wait_cnt = NVR_WAIT_CNT; 410 do { 411 if (!--wait_cnt) { 412 DEBUG9_10(qla_printk(KERN_WARNING, ha, 413 "NVRAM didn't go ready...\n")); 414 break; 415 } 416 NVRAM_DELAY(); 417 word = RD_REG_WORD(®->nvram); 418 } while ((word & NVR_DATA_IN) == 0); 419 } 420 421 422 /*****************************************************************************/ 423 /* Flash Manipulation Routines */ 424 /*****************************************************************************/ 425 426 static inline uint32_t 427 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) 428 { 429 return ha->flash_conf_off | faddr; 430 } 431 432 static inline uint32_t 433 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) 434 { 435 return ha->flash_data_off | faddr; 436 } 437 438 static inline uint32_t 439 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) 440 { 441 return ha->nvram_conf_off | naddr; 442 } 443 444 static inline uint32_t 445 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) 446 { 447 return ha->nvram_data_off | naddr; 448 } 449 450 static uint32_t 451 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr) 452 { 453 int rval; 454 uint32_t cnt, data; 455 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 456 457 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); 458 /* Wait for READ cycle to complete. */ 459 rval = QLA_SUCCESS; 460 for (cnt = 3000; 461 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && 462 rval == QLA_SUCCESS; cnt--) { 463 if (cnt) 464 udelay(10); 465 else 466 rval = QLA_FUNCTION_TIMEOUT; 467 cond_resched(); 468 } 469 470 /* TODO: What happens if we time out? */ 471 data = 0xDEADDEAD; 472 if (rval == QLA_SUCCESS) 473 data = RD_REG_DWORD(®->flash_data); 474 475 return data; 476 } 477 478 uint32_t * 479 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 480 uint32_t dwords) 481 { 482 uint32_t i; 483 struct qla_hw_data *ha = vha->hw; 484 485 /* Dword reads to flash. */ 486 for (i = 0; i < dwords; i++, faddr++) 487 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 488 flash_data_addr(ha, faddr))); 489 490 return dwptr; 491 } 492 493 static int 494 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) 495 { 496 int rval; 497 uint32_t cnt; 498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 499 500 WRT_REG_DWORD(®->flash_data, data); 501 RD_REG_DWORD(®->flash_data); /* PCI Posting. */ 502 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); 503 /* Wait for Write cycle to complete. */ 504 rval = QLA_SUCCESS; 505 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && 506 rval == QLA_SUCCESS; cnt--) { 507 if (cnt) 508 udelay(10); 509 else 510 rval = QLA_FUNCTION_TIMEOUT; 511 cond_resched(); 512 } 513 return rval; 514 } 515 516 static void 517 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 518 uint8_t *flash_id) 519 { 520 uint32_t ids; 521 522 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab)); 523 *man_id = LSB(ids); 524 *flash_id = MSB(ids); 525 526 /* Check if man_id and flash_id are valid. */ 527 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 528 /* Read information using 0x9f opcode 529 * Device ID, Mfg ID would be read in the format: 530 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 531 * Example: ATMEL 0x00 01 45 1F 532 * Extract MFG and Dev ID from last two bytes. 533 */ 534 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f)); 535 *man_id = LSB(ids); 536 *flash_id = MSB(ids); 537 } 538 } 539 540 static int 541 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) 542 { 543 const char *loc, *locations[] = { "DEF", "PCI" }; 544 uint32_t pcihdr, pcids; 545 uint32_t *dcode; 546 uint8_t *buf, *bcode, last_image; 547 uint16_t cnt, chksum, *wptr; 548 struct qla_flt_location *fltl; 549 struct qla_hw_data *ha = vha->hw; 550 struct req_que *req = ha->req_q_map[0]; 551 552 /* 553 * FLT-location structure resides after the last PCI region. 554 */ 555 556 /* Begin with sane defaults. */ 557 loc = locations[0]; 558 *start = 0; 559 if (IS_QLA24XX_TYPE(ha)) 560 *start = FA_FLASH_LAYOUT_ADDR_24; 561 else if (IS_QLA25XX(ha)) 562 *start = FA_FLASH_LAYOUT_ADDR; 563 else if (IS_QLA81XX(ha)) 564 *start = FA_FLASH_LAYOUT_ADDR_81; 565 else if (IS_QLA82XX(ha)) { 566 *start = FA_FLASH_LAYOUT_ADDR_82; 567 goto end; 568 } 569 /* Begin with first PCI expansion ROM header. */ 570 buf = (uint8_t *)req->ring; 571 dcode = (uint32_t *)req->ring; 572 pcihdr = 0; 573 last_image = 1; 574 do { 575 /* Verify PCI expansion ROM header. */ 576 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 577 bcode = buf + (pcihdr % 4); 578 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) 579 goto end; 580 581 /* Locate PCI data structure. */ 582 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 583 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 584 bcode = buf + (pcihdr % 4); 585 586 /* Validate signature of PCI data structure. */ 587 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 588 bcode[0x2] != 'I' || bcode[0x3] != 'R') 589 goto end; 590 591 last_image = bcode[0x15] & BIT_7; 592 593 /* Locate next PCI expansion ROM. */ 594 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 595 } while (!last_image); 596 597 /* Now verify FLT-location structure. */ 598 fltl = (struct qla_flt_location *)req->ring; 599 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 600 sizeof(struct qla_flt_location) >> 2); 601 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' || 602 fltl->sig[2] != 'L' || fltl->sig[3] != 'T') 603 goto end; 604 605 wptr = (uint16_t *)req->ring; 606 cnt = sizeof(struct qla_flt_location) >> 1; 607 for (chksum = 0; cnt; cnt--) 608 chksum += le16_to_cpu(*wptr++); 609 if (chksum) { 610 qla_printk(KERN_ERR, ha, 611 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); 612 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location)); 613 return QLA_FUNCTION_FAILED; 614 } 615 616 /* Good data. Use specified location. */ 617 loc = locations[1]; 618 *start = (le16_to_cpu(fltl->start_hi) << 16 | 619 le16_to_cpu(fltl->start_lo)) >> 2; 620 end: 621 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 622 return QLA_SUCCESS; 623 } 624 625 static void 626 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) 627 { 628 const char *loc, *locations[] = { "DEF", "FLT" }; 629 const uint32_t def_fw[] = 630 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 }; 631 const uint32_t def_boot[] = 632 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 }; 633 const uint32_t def_vpd_nvram[] = 634 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 }; 635 const uint32_t def_vpd0[] = 636 { 0, 0, FA_VPD0_ADDR_81 }; 637 const uint32_t def_vpd1[] = 638 { 0, 0, FA_VPD1_ADDR_81 }; 639 const uint32_t def_nvram0[] = 640 { 0, 0, FA_NVRAM0_ADDR_81 }; 641 const uint32_t def_nvram1[] = 642 { 0, 0, FA_NVRAM1_ADDR_81 }; 643 const uint32_t def_fdt[] = 644 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR, 645 FA_FLASH_DESCR_ADDR_81 }; 646 const uint32_t def_npiv_conf0[] = 647 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR, 648 FA_NPIV_CONF0_ADDR_81 }; 649 const uint32_t def_npiv_conf1[] = 650 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR, 651 FA_NPIV_CONF1_ADDR_81 }; 652 const uint32_t fcp_prio_cfg0[] = 653 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25, 654 0 }; 655 const uint32_t fcp_prio_cfg1[] = 656 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25, 657 0 }; 658 uint32_t def; 659 uint16_t *wptr; 660 uint16_t cnt, chksum; 661 uint32_t start; 662 struct qla_flt_header *flt; 663 struct qla_flt_region *region; 664 struct qla_hw_data *ha = vha->hw; 665 struct req_que *req = ha->req_q_map[0]; 666 667 def = 0; 668 if (IS_QLA25XX(ha)) 669 def = 1; 670 else if (IS_QLA81XX(ha)) 671 def = 2; 672 673 /* Assign FCP prio region since older adapters may not have FLT, or 674 FCP prio region in it's FLT. 675 */ 676 ha->flt_region_fcp_prio = ha->flags.port0 ? 677 fcp_prio_cfg0[def] : fcp_prio_cfg1[def]; 678 679 ha->flt_region_flt = flt_addr; 680 wptr = (uint16_t *)req->ring; 681 flt = (struct qla_flt_header *)req->ring; 682 region = (struct qla_flt_region *)&flt[1]; 683 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, 684 flt_addr << 2, OPTROM_BURST_SIZE); 685 if (*wptr == __constant_cpu_to_le16(0xffff)) 686 goto no_flash_data; 687 if (flt->version != __constant_cpu_to_le16(1)) { 688 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: " 689 "version=0x%x length=0x%x checksum=0x%x.\n", 690 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 691 le16_to_cpu(flt->checksum))); 692 goto no_flash_data; 693 } 694 695 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 696 for (chksum = 0; cnt; cnt--) 697 chksum += le16_to_cpu(*wptr++); 698 if (chksum) { 699 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 700 "version=0x%x length=0x%x checksum=0x%x.\n", 701 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 702 chksum)); 703 goto no_flash_data; 704 } 705 706 loc = locations[1]; 707 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 708 for ( ; cnt; cnt--, region++) { 709 /* Store addresses as DWORD offsets. */ 710 start = le32_to_cpu(region->start) >> 2; 711 712 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 713 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 714 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 715 716 switch (le32_to_cpu(region->code) & 0xff) { 717 case FLT_REG_FW: 718 ha->flt_region_fw = start; 719 break; 720 case FLT_REG_BOOT_CODE: 721 ha->flt_region_boot = start; 722 break; 723 case FLT_REG_VPD_0: 724 ha->flt_region_vpd_nvram = start; 725 if (IS_QLA82XX(ha)) 726 break; 727 if (ha->flags.port0) 728 ha->flt_region_vpd = start; 729 break; 730 case FLT_REG_VPD_1: 731 if (IS_QLA82XX(ha)) 732 break; 733 if (!ha->flags.port0) 734 ha->flt_region_vpd = start; 735 break; 736 case FLT_REG_NVRAM_0: 737 if (ha->flags.port0) 738 ha->flt_region_nvram = start; 739 break; 740 case FLT_REG_NVRAM_1: 741 if (!ha->flags.port0) 742 ha->flt_region_nvram = start; 743 break; 744 case FLT_REG_FDT: 745 ha->flt_region_fdt = start; 746 break; 747 case FLT_REG_NPIV_CONF_0: 748 if (ha->flags.port0) 749 ha->flt_region_npiv_conf = start; 750 break; 751 case FLT_REG_NPIV_CONF_1: 752 if (!ha->flags.port0) 753 ha->flt_region_npiv_conf = start; 754 break; 755 case FLT_REG_GOLD_FW: 756 ha->flt_region_gold_fw = start; 757 break; 758 case FLT_REG_FCP_PRIO_0: 759 if (ha->flags.port0) 760 ha->flt_region_fcp_prio = start; 761 break; 762 case FLT_REG_FCP_PRIO_1: 763 if (!ha->flags.port0) 764 ha->flt_region_fcp_prio = start; 765 break; 766 case FLT_REG_BOOT_CODE_82XX: 767 ha->flt_region_boot = start; 768 break; 769 case FLT_REG_FW_82XX: 770 ha->flt_region_fw = start; 771 break; 772 case FLT_REG_GOLD_FW_82XX: 773 ha->flt_region_gold_fw = start; 774 break; 775 case FLT_REG_BOOTLOAD_82XX: 776 ha->flt_region_bootload = start; 777 break; 778 case FLT_REG_VPD_82XX: 779 ha->flt_region_vpd = start; 780 break; 781 } 782 } 783 goto done; 784 785 no_flash_data: 786 /* Use hardcoded defaults. */ 787 loc = locations[0]; 788 ha->flt_region_fw = def_fw[def]; 789 ha->flt_region_boot = def_boot[def]; 790 ha->flt_region_vpd_nvram = def_vpd_nvram[def]; 791 ha->flt_region_vpd = ha->flags.port0 ? 792 def_vpd0[def] : def_vpd1[def]; 793 ha->flt_region_nvram = ha->flags.port0 ? 794 def_nvram0[def] : def_nvram1[def]; 795 ha->flt_region_fdt = def_fdt[def]; 796 ha->flt_region_npiv_conf = ha->flags.port0 ? 797 def_npiv_conf0[def] : def_npiv_conf1[def]; 798 done: 799 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x " 800 "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x " 801 "npiv=0x%x. fcp_prio_cfg=0x%x\n", loc, ha->flt_region_boot, 802 ha->flt_region_fw, ha->flt_region_vpd_nvram, ha->flt_region_vpd, 803 ha->flt_region_nvram, ha->flt_region_fdt, ha->flt_region_flt, 804 ha->flt_region_npiv_conf, ha->flt_region_fcp_prio)); 805 } 806 807 static void 808 qla2xxx_get_fdt_info(scsi_qla_host_t *vha) 809 { 810 #define FLASH_BLK_SIZE_4K 0x1000 811 #define FLASH_BLK_SIZE_32K 0x8000 812 #define FLASH_BLK_SIZE_64K 0x10000 813 const char *loc, *locations[] = { "MID", "FDT" }; 814 uint16_t cnt, chksum; 815 uint16_t *wptr; 816 struct qla_fdt_layout *fdt; 817 uint8_t man_id, flash_id; 818 uint16_t mid = 0, fid = 0; 819 struct qla_hw_data *ha = vha->hw; 820 struct req_que *req = ha->req_q_map[0]; 821 822 wptr = (uint16_t *)req->ring; 823 fdt = (struct qla_fdt_layout *)req->ring; 824 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, 825 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE); 826 if (*wptr == __constant_cpu_to_le16(0xffff)) 827 goto no_flash_data; 828 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 829 fdt->sig[3] != 'D') 830 goto no_flash_data; 831 832 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 833 cnt++) 834 chksum += le16_to_cpu(*wptr++); 835 if (chksum) { 836 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 837 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 838 le16_to_cpu(fdt->version))); 839 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt))); 840 goto no_flash_data; 841 } 842 843 loc = locations[1]; 844 mid = le16_to_cpu(fdt->man_id); 845 fid = le16_to_cpu(fdt->id); 846 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 847 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); 848 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 849 if (fdt->unprotect_sec_cmd) { 850 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | 851 fdt->unprotect_sec_cmd); 852 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 853 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd): 854 flash_conf_addr(ha, 0x0336); 855 } 856 goto done; 857 no_flash_data: 858 loc = locations[0]; 859 if (IS_QLA82XX(ha)) { 860 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 861 goto done; 862 } 863 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 864 mid = man_id; 865 fid = flash_id; 866 ha->fdt_wrt_disable = 0x9c; 867 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); 868 switch (man_id) { 869 case 0xbf: /* STT flash. */ 870 if (flash_id == 0x8e) 871 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 872 else 873 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 874 875 if (flash_id == 0x80) 876 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); 877 break; 878 case 0x13: /* ST M25P80. */ 879 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 880 break; 881 case 0x1f: /* Atmel 26DF081A. */ 882 ha->fdt_block_size = FLASH_BLK_SIZE_4K; 883 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); 884 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); 885 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); 886 break; 887 default: 888 /* Default to 64 kb sector size. */ 889 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 890 break; 891 } 892 done: 893 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 894 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 895 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, 896 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable, 897 ha->fdt_block_size)); 898 } 899 900 static void 901 qla2xxx_get_idc_param(scsi_qla_host_t *vha) 902 { 903 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 904 uint32_t *wptr; 905 struct qla_hw_data *ha = vha->hw; 906 struct req_que *req = ha->req_q_map[0]; 907 908 if (!IS_QLA82XX(ha)) 909 return; 910 911 wptr = (uint32_t *)req->ring; 912 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, 913 QLA82XX_IDC_PARAM_ADDR , 8); 914 915 if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 916 ha->nx_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; 917 ha->nx_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; 918 } else { 919 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 920 ha->nx_reset_timeout = le32_to_cpu(*wptr); 921 } 922 return; 923 } 924 925 int 926 qla2xxx_get_flash_info(scsi_qla_host_t *vha) 927 { 928 int ret; 929 uint32_t flt_addr; 930 struct qla_hw_data *ha = vha->hw; 931 932 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha)) 933 return QLA_SUCCESS; 934 935 ret = qla2xxx_find_flt_start(vha, &flt_addr); 936 if (ret != QLA_SUCCESS) 937 return ret; 938 939 qla2xxx_get_flt_info(vha, flt_addr); 940 qla2xxx_get_fdt_info(vha); 941 qla2xxx_get_idc_param(vha); 942 943 return QLA_SUCCESS; 944 } 945 946 void 947 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) 948 { 949 #define NPIV_CONFIG_SIZE (16*1024) 950 void *data; 951 uint16_t *wptr; 952 uint16_t cnt, chksum; 953 int i; 954 struct qla_npiv_header hdr; 955 struct qla_npiv_entry *entry; 956 struct qla_hw_data *ha = vha->hw; 957 958 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha)) 959 return; 960 961 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr, 962 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header)); 963 if (hdr.version == __constant_cpu_to_le16(0xffff)) 964 return; 965 if (hdr.version != __constant_cpu_to_le16(1)) { 966 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config " 967 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 968 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 969 le16_to_cpu(hdr.checksum))); 970 return; 971 } 972 973 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); 974 if (!data) { 975 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to " 976 "allocate memory.\n")); 977 return; 978 } 979 980 ha->isp_ops->read_optrom(vha, (uint8_t *)data, 981 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE); 982 983 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) * 984 sizeof(struct qla_npiv_entry)) >> 1; 985 for (wptr = data, chksum = 0; cnt; cnt--) 986 chksum += le16_to_cpu(*wptr++); 987 if (chksum) { 988 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config " 989 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 990 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 991 chksum)); 992 goto done; 993 } 994 995 entry = data + sizeof(struct qla_npiv_header); 996 cnt = le16_to_cpu(hdr.entries); 997 for (i = 0; cnt; cnt--, entry++, i++) { 998 uint16_t flags; 999 struct fc_vport_identifiers vid; 1000 struct fc_vport *vport; 1001 1002 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); 1003 1004 flags = le16_to_cpu(entry->flags); 1005 if (flags == 0xffff) 1006 continue; 1007 if ((flags & BIT_0) == 0) 1008 continue; 1009 1010 memset(&vid, 0, sizeof(vid)); 1011 vid.roles = FC_PORT_ROLE_FCP_INITIATOR; 1012 vid.vport_type = FC_PORTTYPE_NPIV; 1013 vid.disable = false; 1014 vid.port_name = wwn_to_u64(entry->port_name); 1015 vid.node_name = wwn_to_u64(entry->node_name); 1016 1017 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV[%02x]: wwpn=%llx " 1018 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt, 1019 (unsigned long long)vid.port_name, 1020 (unsigned long long)vid.node_name, 1021 le16_to_cpu(entry->vf_id), 1022 entry->q_qos, entry->f_qos)); 1023 1024 if (i < QLA_PRECONFIG_VPORTS) { 1025 vport = fc_vport_create(vha->host, 0, &vid); 1026 if (!vport) 1027 qla_printk(KERN_INFO, ha, 1028 "NPIV-Config: Failed to create vport [%02x]: " 1029 "wwpn=%llx wwnn=%llx.\n", cnt, 1030 (unsigned long long)vid.port_name, 1031 (unsigned long long)vid.node_name); 1032 } 1033 } 1034 done: 1035 kfree(data); 1036 } 1037 1038 static int 1039 qla24xx_unprotect_flash(scsi_qla_host_t *vha) 1040 { 1041 struct qla_hw_data *ha = vha->hw; 1042 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1043 1044 if (ha->flags.fac_supported) 1045 return qla81xx_fac_do_write_enable(vha, 1); 1046 1047 /* Enable flash write. */ 1048 WRT_REG_DWORD(®->ctrl_status, 1049 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1050 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1051 1052 if (!ha->fdt_wrt_disable) 1053 goto done; 1054 1055 /* Disable flash write-protection, first clear SR protection bit */ 1056 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1057 /* Then write zero again to clear remaining SR bits.*/ 1058 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1059 done: 1060 return QLA_SUCCESS; 1061 } 1062 1063 static int 1064 qla24xx_protect_flash(scsi_qla_host_t *vha) 1065 { 1066 uint32_t cnt; 1067 struct qla_hw_data *ha = vha->hw; 1068 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1069 1070 if (ha->flags.fac_supported) 1071 return qla81xx_fac_do_write_enable(vha, 0); 1072 1073 if (!ha->fdt_wrt_disable) 1074 goto skip_wrt_protect; 1075 1076 /* Enable flash write-protection and wait for completion. */ 1077 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 1078 ha->fdt_wrt_disable); 1079 for (cnt = 300; cnt && 1080 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0; 1081 cnt--) { 1082 udelay(10); 1083 } 1084 1085 skip_wrt_protect: 1086 /* Disable flash write. */ 1087 WRT_REG_DWORD(®->ctrl_status, 1088 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1089 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1090 1091 return QLA_SUCCESS; 1092 } 1093 1094 static int 1095 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) 1096 { 1097 struct qla_hw_data *ha = vha->hw; 1098 uint32_t start, finish; 1099 1100 if (ha->flags.fac_supported) { 1101 start = fdata >> 2; 1102 finish = start + (ha->fdt_block_size >> 2) - 1; 1103 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha, 1104 start), flash_data_addr(ha, finish)); 1105 } 1106 1107 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, 1108 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) | 1109 ((fdata >> 16) & 0xff)); 1110 } 1111 1112 static int 1113 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 1114 uint32_t dwords) 1115 { 1116 int ret; 1117 uint32_t liter; 1118 uint32_t sec_mask, rest_addr; 1119 uint32_t fdata; 1120 dma_addr_t optrom_dma; 1121 void *optrom = NULL; 1122 struct qla_hw_data *ha = vha->hw; 1123 1124 /* Prepare burst-capable write on supported ISPs. */ 1125 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) && 1126 dwords > OPTROM_BURST_DWORDS) { 1127 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 1128 &optrom_dma, GFP_KERNEL); 1129 if (!optrom) { 1130 qla_printk(KERN_DEBUG, ha, 1131 "Unable to allocate memory for optrom burst write " 1132 "(%x KB).\n", OPTROM_BURST_SIZE / 1024); 1133 } 1134 } 1135 1136 rest_addr = (ha->fdt_block_size >> 2) - 1; 1137 sec_mask = ~rest_addr; 1138 1139 ret = qla24xx_unprotect_flash(vha); 1140 if (ret != QLA_SUCCESS) { 1141 qla_printk(KERN_WARNING, ha, 1142 "Unable to unprotect flash for update.\n"); 1143 goto done; 1144 } 1145 1146 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 1147 fdata = (faddr & sec_mask) << 2; 1148 1149 /* Are we at the beginning of a sector? */ 1150 if ((faddr & rest_addr) == 0) { 1151 /* Do sector unprotect. */ 1152 if (ha->fdt_unprotect_sec_cmd) 1153 qla24xx_write_flash_dword(ha, 1154 ha->fdt_unprotect_sec_cmd, 1155 (fdata & 0xff00) | ((fdata << 16) & 1156 0xff0000) | ((fdata >> 16) & 0xff)); 1157 ret = qla24xx_erase_sector(vha, fdata); 1158 if (ret != QLA_SUCCESS) { 1159 DEBUG9(qla_printk(KERN_WARNING, ha, 1160 "Unable to erase sector: address=%x.\n", 1161 faddr)); 1162 break; 1163 } 1164 } 1165 1166 /* Go with burst-write. */ 1167 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { 1168 /* Copy data to DMA'ble buffer. */ 1169 memcpy(optrom, dwptr, OPTROM_BURST_SIZE); 1170 1171 ret = qla2x00_load_ram(vha, optrom_dma, 1172 flash_data_addr(ha, faddr), 1173 OPTROM_BURST_DWORDS); 1174 if (ret != QLA_SUCCESS) { 1175 qla_printk(KERN_WARNING, ha, 1176 "Unable to burst-write optrom segment " 1177 "(%x/%x/%llx).\n", ret, 1178 flash_data_addr(ha, faddr), 1179 (unsigned long long)optrom_dma); 1180 qla_printk(KERN_WARNING, ha, 1181 "Reverting to slow-write.\n"); 1182 1183 dma_free_coherent(&ha->pdev->dev, 1184 OPTROM_BURST_SIZE, optrom, optrom_dma); 1185 optrom = NULL; 1186 } else { 1187 liter += OPTROM_BURST_DWORDS - 1; 1188 faddr += OPTROM_BURST_DWORDS - 1; 1189 dwptr += OPTROM_BURST_DWORDS - 1; 1190 continue; 1191 } 1192 } 1193 1194 ret = qla24xx_write_flash_dword(ha, 1195 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr)); 1196 if (ret != QLA_SUCCESS) { 1197 DEBUG9(printk("%s(%ld) Unable to program flash " 1198 "address=%x data=%x.\n", __func__, 1199 vha->host_no, faddr, *dwptr)); 1200 break; 1201 } 1202 1203 /* Do sector protect. */ 1204 if (ha->fdt_unprotect_sec_cmd && 1205 ((faddr & rest_addr) == rest_addr)) 1206 qla24xx_write_flash_dword(ha, 1207 ha->fdt_protect_sec_cmd, 1208 (fdata & 0xff00) | ((fdata << 16) & 1209 0xff0000) | ((fdata >> 16) & 0xff)); 1210 } 1211 1212 ret = qla24xx_protect_flash(vha); 1213 if (ret != QLA_SUCCESS) 1214 qla_printk(KERN_WARNING, ha, 1215 "Unable to protect flash after update.\n"); 1216 done: 1217 if (optrom) 1218 dma_free_coherent(&ha->pdev->dev, 1219 OPTROM_BURST_SIZE, optrom, optrom_dma); 1220 1221 return ret; 1222 } 1223 1224 uint8_t * 1225 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1226 uint32_t bytes) 1227 { 1228 uint32_t i; 1229 uint16_t *wptr; 1230 struct qla_hw_data *ha = vha->hw; 1231 1232 /* Word reads to NVRAM via registers. */ 1233 wptr = (uint16_t *)buf; 1234 qla2x00_lock_nvram_access(ha); 1235 for (i = 0; i < bytes >> 1; i++, naddr++) 1236 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 1237 naddr)); 1238 qla2x00_unlock_nvram_access(ha); 1239 1240 return buf; 1241 } 1242 1243 uint8_t * 1244 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1245 uint32_t bytes) 1246 { 1247 uint32_t i; 1248 uint32_t *dwptr; 1249 struct qla_hw_data *ha = vha->hw; 1250 1251 if (IS_QLA82XX(ha)) 1252 return buf; 1253 1254 /* Dword reads to flash. */ 1255 dwptr = (uint32_t *)buf; 1256 for (i = 0; i < bytes >> 2; i++, naddr++) 1257 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 1258 nvram_data_addr(ha, naddr))); 1259 1260 return buf; 1261 } 1262 1263 int 1264 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1265 uint32_t bytes) 1266 { 1267 int ret, stat; 1268 uint32_t i; 1269 uint16_t *wptr; 1270 unsigned long flags; 1271 struct qla_hw_data *ha = vha->hw; 1272 1273 ret = QLA_SUCCESS; 1274 1275 spin_lock_irqsave(&ha->hardware_lock, flags); 1276 qla2x00_lock_nvram_access(ha); 1277 1278 /* Disable NVRAM write-protection. */ 1279 stat = qla2x00_clear_nvram_protection(ha); 1280 1281 wptr = (uint16_t *)buf; 1282 for (i = 0; i < bytes >> 1; i++, naddr++) { 1283 qla2x00_write_nvram_word(ha, naddr, 1284 cpu_to_le16(*wptr)); 1285 wptr++; 1286 } 1287 1288 /* Enable NVRAM write-protection. */ 1289 qla2x00_set_nvram_protection(ha, stat); 1290 1291 qla2x00_unlock_nvram_access(ha); 1292 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1293 1294 return ret; 1295 } 1296 1297 int 1298 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1299 uint32_t bytes) 1300 { 1301 int ret; 1302 uint32_t i; 1303 uint32_t *dwptr; 1304 struct qla_hw_data *ha = vha->hw; 1305 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1306 1307 ret = QLA_SUCCESS; 1308 1309 if (IS_QLA82XX(ha)) 1310 return ret; 1311 1312 /* Enable flash write. */ 1313 WRT_REG_DWORD(®->ctrl_status, 1314 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1315 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1316 1317 /* Disable NVRAM write-protection. */ 1318 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1319 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1320 1321 /* Dword writes to flash. */ 1322 dwptr = (uint32_t *)buf; 1323 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) { 1324 ret = qla24xx_write_flash_dword(ha, 1325 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr)); 1326 if (ret != QLA_SUCCESS) { 1327 DEBUG9(qla_printk(KERN_WARNING, ha, 1328 "Unable to program nvram address=%x data=%x.\n", 1329 naddr, *dwptr)); 1330 break; 1331 } 1332 } 1333 1334 /* Enable NVRAM write-protection. */ 1335 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c); 1336 1337 /* Disable flash write. */ 1338 WRT_REG_DWORD(®->ctrl_status, 1339 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1340 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1341 1342 return ret; 1343 } 1344 1345 uint8_t * 1346 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1347 uint32_t bytes) 1348 { 1349 uint32_t i; 1350 uint32_t *dwptr; 1351 struct qla_hw_data *ha = vha->hw; 1352 1353 /* Dword reads to flash. */ 1354 dwptr = (uint32_t *)buf; 1355 for (i = 0; i < bytes >> 2; i++, naddr++) 1356 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha, 1357 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr))); 1358 1359 return buf; 1360 } 1361 1362 int 1363 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, 1364 uint32_t bytes) 1365 { 1366 struct qla_hw_data *ha = vha->hw; 1367 #define RMW_BUFFER_SIZE (64 * 1024) 1368 uint8_t *dbuf; 1369 1370 dbuf = vmalloc(RMW_BUFFER_SIZE); 1371 if (!dbuf) 1372 return QLA_MEMORY_ALLOC_FAILED; 1373 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1374 RMW_BUFFER_SIZE); 1375 memcpy(dbuf + (naddr << 2), buf, bytes); 1376 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1377 RMW_BUFFER_SIZE); 1378 vfree(dbuf); 1379 1380 return QLA_SUCCESS; 1381 } 1382 1383 static inline void 1384 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1385 { 1386 if (IS_QLA2322(ha)) { 1387 /* Flip all colors. */ 1388 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1389 /* Turn off. */ 1390 ha->beacon_color_state = 0; 1391 *pflags = GPIO_LED_ALL_OFF; 1392 } else { 1393 /* Turn on. */ 1394 ha->beacon_color_state = QLA_LED_ALL_ON; 1395 *pflags = GPIO_LED_RGA_ON; 1396 } 1397 } else { 1398 /* Flip green led only. */ 1399 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 1400 /* Turn off. */ 1401 ha->beacon_color_state = 0; 1402 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 1403 } else { 1404 /* Turn on. */ 1405 ha->beacon_color_state = QLA_LED_GRN_ON; 1406 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 1407 } 1408 } 1409 } 1410 1411 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) 1412 1413 void 1414 qla2x00_beacon_blink(struct scsi_qla_host *vha) 1415 { 1416 uint16_t gpio_enable; 1417 uint16_t gpio_data; 1418 uint16_t led_color = 0; 1419 unsigned long flags; 1420 struct qla_hw_data *ha = vha->hw; 1421 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1422 1423 if (IS_QLA82XX(ha)) 1424 return; 1425 1426 spin_lock_irqsave(&ha->hardware_lock, flags); 1427 1428 /* Save the Original GPIOE. */ 1429 if (ha->pio_address) { 1430 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1431 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1432 } else { 1433 gpio_enable = RD_REG_WORD(®->gpioe); 1434 gpio_data = RD_REG_WORD(®->gpiod); 1435 } 1436 1437 /* Set the modified gpio_enable values */ 1438 gpio_enable |= GPIO_LED_MASK; 1439 1440 if (ha->pio_address) { 1441 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1442 } else { 1443 WRT_REG_WORD(®->gpioe, gpio_enable); 1444 RD_REG_WORD(®->gpioe); 1445 } 1446 1447 qla2x00_flip_colors(ha, &led_color); 1448 1449 /* Clear out any previously set LED color. */ 1450 gpio_data &= ~GPIO_LED_MASK; 1451 1452 /* Set the new input LED color to GPIOD. */ 1453 gpio_data |= led_color; 1454 1455 /* Set the modified gpio_data values */ 1456 if (ha->pio_address) { 1457 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1458 } else { 1459 WRT_REG_WORD(®->gpiod, gpio_data); 1460 RD_REG_WORD(®->gpiod); 1461 } 1462 1463 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1464 } 1465 1466 int 1467 qla2x00_beacon_on(struct scsi_qla_host *vha) 1468 { 1469 uint16_t gpio_enable; 1470 uint16_t gpio_data; 1471 unsigned long flags; 1472 struct qla_hw_data *ha = vha->hw; 1473 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1474 1475 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1476 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 1477 1478 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1479 qla_printk(KERN_WARNING, ha, 1480 "Unable to update fw options (beacon on).\n"); 1481 return QLA_FUNCTION_FAILED; 1482 } 1483 1484 /* Turn off LEDs. */ 1485 spin_lock_irqsave(&ha->hardware_lock, flags); 1486 if (ha->pio_address) { 1487 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1488 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1489 } else { 1490 gpio_enable = RD_REG_WORD(®->gpioe); 1491 gpio_data = RD_REG_WORD(®->gpiod); 1492 } 1493 gpio_enable |= GPIO_LED_MASK; 1494 1495 /* Set the modified gpio_enable values. */ 1496 if (ha->pio_address) { 1497 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1498 } else { 1499 WRT_REG_WORD(®->gpioe, gpio_enable); 1500 RD_REG_WORD(®->gpioe); 1501 } 1502 1503 /* Clear out previously set LED colour. */ 1504 gpio_data &= ~GPIO_LED_MASK; 1505 if (ha->pio_address) { 1506 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1507 } else { 1508 WRT_REG_WORD(®->gpiod, gpio_data); 1509 RD_REG_WORD(®->gpiod); 1510 } 1511 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1512 1513 /* 1514 * Let the per HBA timer kick off the blinking process based on 1515 * the following flags. No need to do anything else now. 1516 */ 1517 ha->beacon_blink_led = 1; 1518 ha->beacon_color_state = 0; 1519 1520 return QLA_SUCCESS; 1521 } 1522 1523 int 1524 qla2x00_beacon_off(struct scsi_qla_host *vha) 1525 { 1526 int rval = QLA_SUCCESS; 1527 struct qla_hw_data *ha = vha->hw; 1528 1529 ha->beacon_blink_led = 0; 1530 1531 /* Set the on flag so when it gets flipped it will be off. */ 1532 if (IS_QLA2322(ha)) 1533 ha->beacon_color_state = QLA_LED_ALL_ON; 1534 else 1535 ha->beacon_color_state = QLA_LED_GRN_ON; 1536 1537 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ 1538 1539 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1540 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 1541 1542 rval = qla2x00_set_fw_options(vha, ha->fw_options); 1543 if (rval != QLA_SUCCESS) 1544 qla_printk(KERN_WARNING, ha, 1545 "Unable to update fw options (beacon off).\n"); 1546 return rval; 1547 } 1548 1549 1550 static inline void 1551 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1552 { 1553 /* Flip all colors. */ 1554 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1555 /* Turn off. */ 1556 ha->beacon_color_state = 0; 1557 *pflags = 0; 1558 } else { 1559 /* Turn on. */ 1560 ha->beacon_color_state = QLA_LED_ALL_ON; 1561 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 1562 } 1563 } 1564 1565 void 1566 qla24xx_beacon_blink(struct scsi_qla_host *vha) 1567 { 1568 uint16_t led_color = 0; 1569 uint32_t gpio_data; 1570 unsigned long flags; 1571 struct qla_hw_data *ha = vha->hw; 1572 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1573 1574 /* Save the Original GPIOD. */ 1575 spin_lock_irqsave(&ha->hardware_lock, flags); 1576 gpio_data = RD_REG_DWORD(®->gpiod); 1577 1578 /* Enable the gpio_data reg for update. */ 1579 gpio_data |= GPDX_LED_UPDATE_MASK; 1580 1581 WRT_REG_DWORD(®->gpiod, gpio_data); 1582 gpio_data = RD_REG_DWORD(®->gpiod); 1583 1584 /* Set the color bits. */ 1585 qla24xx_flip_colors(ha, &led_color); 1586 1587 /* Clear out any previously set LED color. */ 1588 gpio_data &= ~GPDX_LED_COLOR_MASK; 1589 1590 /* Set the new input LED color to GPIOD. */ 1591 gpio_data |= led_color; 1592 1593 /* Set the modified gpio_data values. */ 1594 WRT_REG_DWORD(®->gpiod, gpio_data); 1595 gpio_data = RD_REG_DWORD(®->gpiod); 1596 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1597 } 1598 1599 int 1600 qla24xx_beacon_on(struct scsi_qla_host *vha) 1601 { 1602 uint32_t gpio_data; 1603 unsigned long flags; 1604 struct qla_hw_data *ha = vha->hw; 1605 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1606 1607 if (IS_QLA82XX(ha)) 1608 return QLA_SUCCESS; 1609 1610 if (ha->beacon_blink_led == 0) { 1611 /* Enable firmware for update */ 1612 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1613 1614 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) 1615 return QLA_FUNCTION_FAILED; 1616 1617 if (qla2x00_get_fw_options(vha, ha->fw_options) != 1618 QLA_SUCCESS) { 1619 qla_printk(KERN_WARNING, ha, 1620 "Unable to update fw options (beacon on).\n"); 1621 return QLA_FUNCTION_FAILED; 1622 } 1623 1624 spin_lock_irqsave(&ha->hardware_lock, flags); 1625 gpio_data = RD_REG_DWORD(®->gpiod); 1626 1627 /* Enable the gpio_data reg for update. */ 1628 gpio_data |= GPDX_LED_UPDATE_MASK; 1629 WRT_REG_DWORD(®->gpiod, gpio_data); 1630 RD_REG_DWORD(®->gpiod); 1631 1632 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1633 } 1634 1635 /* So all colors blink together. */ 1636 ha->beacon_color_state = 0; 1637 1638 /* Let the per HBA timer kick off the blinking process. */ 1639 ha->beacon_blink_led = 1; 1640 1641 return QLA_SUCCESS; 1642 } 1643 1644 int 1645 qla24xx_beacon_off(struct scsi_qla_host *vha) 1646 { 1647 uint32_t gpio_data; 1648 unsigned long flags; 1649 struct qla_hw_data *ha = vha->hw; 1650 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1651 1652 if (IS_QLA82XX(ha)) 1653 return QLA_SUCCESS; 1654 1655 ha->beacon_blink_led = 0; 1656 ha->beacon_color_state = QLA_LED_ALL_ON; 1657 1658 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ 1659 1660 /* Give control back to firmware. */ 1661 spin_lock_irqsave(&ha->hardware_lock, flags); 1662 gpio_data = RD_REG_DWORD(®->gpiod); 1663 1664 /* Disable the gpio_data reg for update. */ 1665 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1666 WRT_REG_DWORD(®->gpiod, gpio_data); 1667 RD_REG_DWORD(®->gpiod); 1668 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1669 1670 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1671 1672 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1673 qla_printk(KERN_WARNING, ha, 1674 "Unable to update fw options (beacon off).\n"); 1675 return QLA_FUNCTION_FAILED; 1676 } 1677 1678 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1679 qla_printk(KERN_WARNING, ha, 1680 "Unable to get fw options (beacon off).\n"); 1681 return QLA_FUNCTION_FAILED; 1682 } 1683 1684 return QLA_SUCCESS; 1685 } 1686 1687 1688 /* 1689 * Flash support routines 1690 */ 1691 1692 /** 1693 * qla2x00_flash_enable() - Setup flash for reading and writing. 1694 * @ha: HA context 1695 */ 1696 static void 1697 qla2x00_flash_enable(struct qla_hw_data *ha) 1698 { 1699 uint16_t data; 1700 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1701 1702 data = RD_REG_WORD(®->ctrl_status); 1703 data |= CSR_FLASH_ENABLE; 1704 WRT_REG_WORD(®->ctrl_status, data); 1705 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1706 } 1707 1708 /** 1709 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1710 * @ha: HA context 1711 */ 1712 static void 1713 qla2x00_flash_disable(struct qla_hw_data *ha) 1714 { 1715 uint16_t data; 1716 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1717 1718 data = RD_REG_WORD(®->ctrl_status); 1719 data &= ~(CSR_FLASH_ENABLE); 1720 WRT_REG_WORD(®->ctrl_status, data); 1721 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1722 } 1723 1724 /** 1725 * qla2x00_read_flash_byte() - Reads a byte from flash 1726 * @ha: HA context 1727 * @addr: Address in flash to read 1728 * 1729 * A word is read from the chip, but, only the lower byte is valid. 1730 * 1731 * Returns the byte read from flash @addr. 1732 */ 1733 static uint8_t 1734 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) 1735 { 1736 uint16_t data; 1737 uint16_t bank_select; 1738 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1739 1740 bank_select = RD_REG_WORD(®->ctrl_status); 1741 1742 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1743 /* Specify 64K address range: */ 1744 /* clear out Module Select and Flash Address bits [19:16]. */ 1745 bank_select &= ~0xf8; 1746 bank_select |= addr >> 12 & 0xf0; 1747 bank_select |= CSR_FLASH_64K_BANK; 1748 WRT_REG_WORD(®->ctrl_status, bank_select); 1749 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1750 1751 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1752 data = RD_REG_WORD(®->flash_data); 1753 1754 return (uint8_t)data; 1755 } 1756 1757 /* Setup bit 16 of flash address. */ 1758 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 1759 bank_select |= CSR_FLASH_64K_BANK; 1760 WRT_REG_WORD(®->ctrl_status, bank_select); 1761 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1762 } else if (((addr & BIT_16) == 0) && 1763 (bank_select & CSR_FLASH_64K_BANK)) { 1764 bank_select &= ~(CSR_FLASH_64K_BANK); 1765 WRT_REG_WORD(®->ctrl_status, bank_select); 1766 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1767 } 1768 1769 /* Always perform IO mapped accesses to the FLASH registers. */ 1770 if (ha->pio_address) { 1771 uint16_t data2; 1772 1773 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 1774 do { 1775 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 1776 barrier(); 1777 cpu_relax(); 1778 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 1779 } while (data != data2); 1780 } else { 1781 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1782 data = qla2x00_debounce_register(®->flash_data); 1783 } 1784 1785 return (uint8_t)data; 1786 } 1787 1788 /** 1789 * qla2x00_write_flash_byte() - Write a byte to flash 1790 * @ha: HA context 1791 * @addr: Address in flash to write 1792 * @data: Data to write 1793 */ 1794 static void 1795 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) 1796 { 1797 uint16_t bank_select; 1798 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1799 1800 bank_select = RD_REG_WORD(®->ctrl_status); 1801 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 1802 /* Specify 64K address range: */ 1803 /* clear out Module Select and Flash Address bits [19:16]. */ 1804 bank_select &= ~0xf8; 1805 bank_select |= addr >> 12 & 0xf0; 1806 bank_select |= CSR_FLASH_64K_BANK; 1807 WRT_REG_WORD(®->ctrl_status, bank_select); 1808 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1809 1810 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1811 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1812 WRT_REG_WORD(®->flash_data, (uint16_t)data); 1813 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1814 1815 return; 1816 } 1817 1818 /* Setup bit 16 of flash address. */ 1819 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 1820 bank_select |= CSR_FLASH_64K_BANK; 1821 WRT_REG_WORD(®->ctrl_status, bank_select); 1822 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1823 } else if (((addr & BIT_16) == 0) && 1824 (bank_select & CSR_FLASH_64K_BANK)) { 1825 bank_select &= ~(CSR_FLASH_64K_BANK); 1826 WRT_REG_WORD(®->ctrl_status, bank_select); 1827 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1828 } 1829 1830 /* Always perform IO mapped accesses to the FLASH registers. */ 1831 if (ha->pio_address) { 1832 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 1833 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); 1834 } else { 1835 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 1836 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1837 WRT_REG_WORD(®->flash_data, (uint16_t)data); 1838 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1839 } 1840 } 1841 1842 /** 1843 * qla2x00_poll_flash() - Polls flash for completion. 1844 * @ha: HA context 1845 * @addr: Address in flash to poll 1846 * @poll_data: Data to be polled 1847 * @man_id: Flash manufacturer ID 1848 * @flash_id: Flash ID 1849 * 1850 * This function polls the device until bit 7 of what is read matches data 1851 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed 1852 * out (a fatal error). The flash book recommeds reading bit 7 again after 1853 * reading bit 5 as a 1. 1854 * 1855 * Returns 0 on success, else non-zero. 1856 */ 1857 static int 1858 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, 1859 uint8_t man_id, uint8_t flash_id) 1860 { 1861 int status; 1862 uint8_t flash_data; 1863 uint32_t cnt; 1864 1865 status = 1; 1866 1867 /* Wait for 30 seconds for command to finish. */ 1868 poll_data &= BIT_7; 1869 for (cnt = 3000000; cnt; cnt--) { 1870 flash_data = qla2x00_read_flash_byte(ha, addr); 1871 if ((flash_data & BIT_7) == poll_data) { 1872 status = 0; 1873 break; 1874 } 1875 1876 if (man_id != 0x40 && man_id != 0xda) { 1877 if ((flash_data & BIT_5) && cnt > 2) 1878 cnt = 2; 1879 } 1880 udelay(10); 1881 barrier(); 1882 cond_resched(); 1883 } 1884 return status; 1885 } 1886 1887 /** 1888 * qla2x00_program_flash_address() - Programs a flash address 1889 * @ha: HA context 1890 * @addr: Address in flash to program 1891 * @data: Data to be written in flash 1892 * @man_id: Flash manufacturer ID 1893 * @flash_id: Flash ID 1894 * 1895 * Returns 0 on success, else non-zero. 1896 */ 1897 static int 1898 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, 1899 uint8_t data, uint8_t man_id, uint8_t flash_id) 1900 { 1901 /* Write Program Command Sequence. */ 1902 if (IS_OEM_001(ha)) { 1903 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1904 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1905 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 1906 qla2x00_write_flash_byte(ha, addr, data); 1907 } else { 1908 if (man_id == 0xda && flash_id == 0xc1) { 1909 qla2x00_write_flash_byte(ha, addr, data); 1910 if (addr & 0x7e) 1911 return 0; 1912 } else { 1913 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1914 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1915 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 1916 qla2x00_write_flash_byte(ha, addr, data); 1917 } 1918 } 1919 1920 udelay(150); 1921 1922 /* Wait for write to complete. */ 1923 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 1924 } 1925 1926 /** 1927 * qla2x00_erase_flash() - Erase the flash. 1928 * @ha: HA context 1929 * @man_id: Flash manufacturer ID 1930 * @flash_id: Flash ID 1931 * 1932 * Returns 0 on success, else non-zero. 1933 */ 1934 static int 1935 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id) 1936 { 1937 /* Individual Sector Erase Command Sequence */ 1938 if (IS_OEM_001(ha)) { 1939 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1940 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1941 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 1942 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 1943 qla2x00_write_flash_byte(ha, 0x555, 0x55); 1944 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 1945 } else { 1946 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1947 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1948 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 1949 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1950 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1951 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 1952 } 1953 1954 udelay(150); 1955 1956 /* Wait for erase to complete. */ 1957 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 1958 } 1959 1960 /** 1961 * qla2x00_erase_flash_sector() - Erase a flash sector. 1962 * @ha: HA context 1963 * @addr: Flash sector to erase 1964 * @sec_mask: Sector address mask 1965 * @man_id: Flash manufacturer ID 1966 * @flash_id: Flash ID 1967 * 1968 * Returns 0 on success, else non-zero. 1969 */ 1970 static int 1971 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, 1972 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 1973 { 1974 /* Individual Sector Erase Command Sequence */ 1975 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1976 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1977 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 1978 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 1979 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 1980 if (man_id == 0x1f && flash_id == 0x13) 1981 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 1982 else 1983 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 1984 1985 udelay(150); 1986 1987 /* Wait for erase to complete. */ 1988 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 1989 } 1990 1991 /** 1992 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 1993 * @man_id: Flash manufacturer ID 1994 * @flash_id: Flash ID 1995 */ 1996 static void 1997 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 1998 uint8_t *flash_id) 1999 { 2000 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2001 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2002 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 2003 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 2004 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 2005 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2006 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2007 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 2008 } 2009 2010 static void 2011 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf, 2012 uint32_t saddr, uint32_t length) 2013 { 2014 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2015 uint32_t midpoint, ilength; 2016 uint8_t data; 2017 2018 midpoint = length / 2; 2019 2020 WRT_REG_WORD(®->nvram, 0); 2021 RD_REG_WORD(®->nvram); 2022 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 2023 if (ilength == midpoint) { 2024 WRT_REG_WORD(®->nvram, NVR_SELECT); 2025 RD_REG_WORD(®->nvram); 2026 } 2027 data = qla2x00_read_flash_byte(ha, saddr); 2028 if (saddr % 100) 2029 udelay(10); 2030 *tmp_buf = data; 2031 cond_resched(); 2032 } 2033 } 2034 2035 static inline void 2036 qla2x00_suspend_hba(struct scsi_qla_host *vha) 2037 { 2038 int cnt; 2039 unsigned long flags; 2040 struct qla_hw_data *ha = vha->hw; 2041 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2042 2043 /* Suspend HBA. */ 2044 scsi_block_requests(vha->host); 2045 ha->isp_ops->disable_intrs(ha); 2046 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2047 2048 /* Pause RISC. */ 2049 spin_lock_irqsave(&ha->hardware_lock, flags); 2050 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 2051 RD_REG_WORD(®->hccr); 2052 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2053 for (cnt = 0; cnt < 30000; cnt++) { 2054 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 2055 break; 2056 udelay(100); 2057 } 2058 } else { 2059 udelay(10); 2060 } 2061 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2062 } 2063 2064 static inline void 2065 qla2x00_resume_hba(struct scsi_qla_host *vha) 2066 { 2067 struct qla_hw_data *ha = vha->hw; 2068 2069 /* Resume HBA. */ 2070 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2071 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2072 qla2xxx_wake_dpc(vha); 2073 qla2x00_wait_for_chip_reset(vha); 2074 scsi_unblock_requests(vha->host); 2075 } 2076 2077 uint8_t * 2078 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2079 uint32_t offset, uint32_t length) 2080 { 2081 uint32_t addr, midpoint; 2082 uint8_t *data; 2083 struct qla_hw_data *ha = vha->hw; 2084 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2085 2086 /* Suspend HBA. */ 2087 qla2x00_suspend_hba(vha); 2088 2089 /* Go with read. */ 2090 midpoint = ha->optrom_size / 2; 2091 2092 qla2x00_flash_enable(ha); 2093 WRT_REG_WORD(®->nvram, 0); 2094 RD_REG_WORD(®->nvram); /* PCI Posting. */ 2095 for (addr = offset, data = buf; addr < length; addr++, data++) { 2096 if (addr == midpoint) { 2097 WRT_REG_WORD(®->nvram, NVR_SELECT); 2098 RD_REG_WORD(®->nvram); /* PCI Posting. */ 2099 } 2100 2101 *data = qla2x00_read_flash_byte(ha, addr); 2102 } 2103 qla2x00_flash_disable(ha); 2104 2105 /* Resume HBA. */ 2106 qla2x00_resume_hba(vha); 2107 2108 return buf; 2109 } 2110 2111 int 2112 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2113 uint32_t offset, uint32_t length) 2114 { 2115 2116 int rval; 2117 uint8_t man_id, flash_id, sec_number, data; 2118 uint16_t wd; 2119 uint32_t addr, liter, sec_mask, rest_addr; 2120 struct qla_hw_data *ha = vha->hw; 2121 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2122 2123 /* Suspend HBA. */ 2124 qla2x00_suspend_hba(vha); 2125 2126 rval = QLA_SUCCESS; 2127 sec_number = 0; 2128 2129 /* Reset ISP chip. */ 2130 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 2131 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2132 2133 /* Go with write. */ 2134 qla2x00_flash_enable(ha); 2135 do { /* Loop once to provide quick error exit */ 2136 /* Structure of flash memory based on manufacturer */ 2137 if (IS_OEM_001(ha)) { 2138 /* OEM variant with special flash part. */ 2139 man_id = flash_id = 0; 2140 rest_addr = 0xffff; 2141 sec_mask = 0x10000; 2142 goto update_flash; 2143 } 2144 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 2145 switch (man_id) { 2146 case 0x20: /* ST flash. */ 2147 if (flash_id == 0xd2 || flash_id == 0xe3) { 2148 /* 2149 * ST m29w008at part - 64kb sector size with 2150 * 32kb,8kb,8kb,16kb sectors at memory address 2151 * 0xf0000. 2152 */ 2153 rest_addr = 0xffff; 2154 sec_mask = 0x10000; 2155 break; 2156 } 2157 /* 2158 * ST m29w010b part - 16kb sector size 2159 * Default to 16kb sectors 2160 */ 2161 rest_addr = 0x3fff; 2162 sec_mask = 0x1c000; 2163 break; 2164 case 0x40: /* Mostel flash. */ 2165 /* Mostel v29c51001 part - 512 byte sector size. */ 2166 rest_addr = 0x1ff; 2167 sec_mask = 0x1fe00; 2168 break; 2169 case 0xbf: /* SST flash. */ 2170 /* SST39sf10 part - 4kb sector size. */ 2171 rest_addr = 0xfff; 2172 sec_mask = 0x1f000; 2173 break; 2174 case 0xda: /* Winbond flash. */ 2175 /* Winbond W29EE011 part - 256 byte sector size. */ 2176 rest_addr = 0x7f; 2177 sec_mask = 0x1ff80; 2178 break; 2179 case 0xc2: /* Macronix flash. */ 2180 /* 64k sector size. */ 2181 if (flash_id == 0x38 || flash_id == 0x4f) { 2182 rest_addr = 0xffff; 2183 sec_mask = 0x10000; 2184 break; 2185 } 2186 /* Fall through... */ 2187 2188 case 0x1f: /* Atmel flash. */ 2189 /* 512k sector size. */ 2190 if (flash_id == 0x13) { 2191 rest_addr = 0x7fffffff; 2192 sec_mask = 0x80000000; 2193 break; 2194 } 2195 /* Fall through... */ 2196 2197 case 0x01: /* AMD flash. */ 2198 if (flash_id == 0x38 || flash_id == 0x40 || 2199 flash_id == 0x4f) { 2200 /* Am29LV081 part - 64kb sector size. */ 2201 /* Am29LV002BT part - 64kb sector size. */ 2202 rest_addr = 0xffff; 2203 sec_mask = 0x10000; 2204 break; 2205 } else if (flash_id == 0x3e) { 2206 /* 2207 * Am29LV008b part - 64kb sector size with 2208 * 32kb,8kb,8kb,16kb sector at memory address 2209 * h0xf0000. 2210 */ 2211 rest_addr = 0xffff; 2212 sec_mask = 0x10000; 2213 break; 2214 } else if (flash_id == 0x20 || flash_id == 0x6e) { 2215 /* 2216 * Am29LV010 part or AM29f010 - 16kb sector 2217 * size. 2218 */ 2219 rest_addr = 0x3fff; 2220 sec_mask = 0x1c000; 2221 break; 2222 } else if (flash_id == 0x6d) { 2223 /* Am29LV001 part - 8kb sector size. */ 2224 rest_addr = 0x1fff; 2225 sec_mask = 0x1e000; 2226 break; 2227 } 2228 default: 2229 /* Default to 16 kb sector size. */ 2230 rest_addr = 0x3fff; 2231 sec_mask = 0x1c000; 2232 break; 2233 } 2234 2235 update_flash: 2236 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2237 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 2238 rval = QLA_FUNCTION_FAILED; 2239 break; 2240 } 2241 } 2242 2243 for (addr = offset, liter = 0; liter < length; liter++, 2244 addr++) { 2245 data = buf[liter]; 2246 /* Are we at the beginning of a sector? */ 2247 if ((addr & rest_addr) == 0) { 2248 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2249 if (addr >= 0x10000UL) { 2250 if (((addr >> 12) & 0xf0) && 2251 ((man_id == 0x01 && 2252 flash_id == 0x3e) || 2253 (man_id == 0x20 && 2254 flash_id == 0xd2))) { 2255 sec_number++; 2256 if (sec_number == 1) { 2257 rest_addr = 2258 0x7fff; 2259 sec_mask = 2260 0x18000; 2261 } else if ( 2262 sec_number == 2 || 2263 sec_number == 3) { 2264 rest_addr = 2265 0x1fff; 2266 sec_mask = 2267 0x1e000; 2268 } else if ( 2269 sec_number == 4) { 2270 rest_addr = 2271 0x3fff; 2272 sec_mask = 2273 0x1c000; 2274 } 2275 } 2276 } 2277 } else if (addr == ha->optrom_size / 2) { 2278 WRT_REG_WORD(®->nvram, NVR_SELECT); 2279 RD_REG_WORD(®->nvram); 2280 } 2281 2282 if (flash_id == 0xda && man_id == 0xc1) { 2283 qla2x00_write_flash_byte(ha, 0x5555, 2284 0xaa); 2285 qla2x00_write_flash_byte(ha, 0x2aaa, 2286 0x55); 2287 qla2x00_write_flash_byte(ha, 0x5555, 2288 0xa0); 2289 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 2290 /* Then erase it */ 2291 if (qla2x00_erase_flash_sector(ha, 2292 addr, sec_mask, man_id, 2293 flash_id)) { 2294 rval = QLA_FUNCTION_FAILED; 2295 break; 2296 } 2297 if (man_id == 0x01 && flash_id == 0x6d) 2298 sec_number++; 2299 } 2300 } 2301 2302 if (man_id == 0x01 && flash_id == 0x6d) { 2303 if (sec_number == 1 && 2304 addr == (rest_addr - 1)) { 2305 rest_addr = 0x0fff; 2306 sec_mask = 0x1f000; 2307 } else if (sec_number == 3 && (addr & 0x7ffe)) { 2308 rest_addr = 0x3fff; 2309 sec_mask = 0x1c000; 2310 } 2311 } 2312 2313 if (qla2x00_program_flash_address(ha, addr, data, 2314 man_id, flash_id)) { 2315 rval = QLA_FUNCTION_FAILED; 2316 break; 2317 } 2318 cond_resched(); 2319 } 2320 } while (0); 2321 qla2x00_flash_disable(ha); 2322 2323 /* Resume HBA. */ 2324 qla2x00_resume_hba(vha); 2325 2326 return rval; 2327 } 2328 2329 uint8_t * 2330 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2331 uint32_t offset, uint32_t length) 2332 { 2333 struct qla_hw_data *ha = vha->hw; 2334 2335 /* Suspend HBA. */ 2336 scsi_block_requests(vha->host); 2337 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2338 2339 /* Go with read. */ 2340 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2); 2341 2342 /* Resume HBA. */ 2343 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2344 scsi_unblock_requests(vha->host); 2345 2346 return buf; 2347 } 2348 2349 int 2350 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2351 uint32_t offset, uint32_t length) 2352 { 2353 int rval; 2354 struct qla_hw_data *ha = vha->hw; 2355 2356 /* Suspend HBA. */ 2357 scsi_block_requests(vha->host); 2358 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2359 2360 /* Go with write. */ 2361 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2, 2362 length >> 2); 2363 2364 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2365 scsi_unblock_requests(vha->host); 2366 2367 return rval; 2368 } 2369 2370 uint8_t * 2371 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 2372 uint32_t offset, uint32_t length) 2373 { 2374 int rval; 2375 dma_addr_t optrom_dma; 2376 void *optrom; 2377 uint8_t *pbuf; 2378 uint32_t faddr, left, burst; 2379 struct qla_hw_data *ha = vha->hw; 2380 2381 if (IS_QLA25XX(ha) || IS_QLA81XX(ha)) 2382 goto try_fast; 2383 if (offset & 0xfff) 2384 goto slow_read; 2385 if (length < OPTROM_BURST_SIZE) 2386 goto slow_read; 2387 2388 try_fast: 2389 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2390 &optrom_dma, GFP_KERNEL); 2391 if (!optrom) { 2392 qla_printk(KERN_DEBUG, ha, 2393 "Unable to allocate memory for optrom burst read " 2394 "(%x KB).\n", OPTROM_BURST_SIZE / 1024); 2395 2396 goto slow_read; 2397 } 2398 2399 pbuf = buf; 2400 faddr = offset >> 2; 2401 left = length >> 2; 2402 burst = OPTROM_BURST_DWORDS; 2403 while (left != 0) { 2404 if (burst > left) 2405 burst = left; 2406 2407 rval = qla2x00_dump_ram(vha, optrom_dma, 2408 flash_data_addr(ha, faddr), burst); 2409 if (rval) { 2410 qla_printk(KERN_WARNING, ha, 2411 "Unable to burst-read optrom segment " 2412 "(%x/%x/%llx).\n", rval, 2413 flash_data_addr(ha, faddr), 2414 (unsigned long long)optrom_dma); 2415 qla_printk(KERN_WARNING, ha, 2416 "Reverting to slow-read.\n"); 2417 2418 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2419 optrom, optrom_dma); 2420 goto slow_read; 2421 } 2422 2423 memcpy(pbuf, optrom, burst * 4); 2424 2425 left -= burst; 2426 faddr += burst; 2427 pbuf += burst * 4; 2428 } 2429 2430 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, 2431 optrom_dma); 2432 2433 return buf; 2434 2435 slow_read: 2436 return qla24xx_read_optrom_data(vha, buf, offset, length); 2437 } 2438 2439 /** 2440 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 2441 * @ha: HA context 2442 * @pcids: Pointer to the FCODE PCI data structure 2443 * 2444 * The process of retrieving the FCODE version information is at best 2445 * described as interesting. 2446 * 2447 * Within the first 100h bytes of the image an ASCII string is present 2448 * which contains several pieces of information including the FCODE 2449 * version. Unfortunately it seems the only reliable way to retrieve 2450 * the version is by scanning for another sentinel within the string, 2451 * the FCODE build date: 2452 * 2453 * ... 2.00.02 10/17/02 ... 2454 * 2455 * Returns QLA_SUCCESS on successful retrieval of version. 2456 */ 2457 static void 2458 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) 2459 { 2460 int ret = QLA_FUNCTION_FAILED; 2461 uint32_t istart, iend, iter, vend; 2462 uint8_t do_next, rbyte, *vbyte; 2463 2464 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2465 2466 /* Skip the PCI data structure. */ 2467 istart = pcids + 2468 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 2469 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 2470 iend = istart + 0x100; 2471 do { 2472 /* Scan for the sentinel date string...eeewww. */ 2473 do_next = 0; 2474 iter = istart; 2475 while ((iter < iend) && !do_next) { 2476 iter++; 2477 if (qla2x00_read_flash_byte(ha, iter) == '/') { 2478 if (qla2x00_read_flash_byte(ha, iter + 2) == 2479 '/') 2480 do_next++; 2481 else if (qla2x00_read_flash_byte(ha, 2482 iter + 3) == '/') 2483 do_next++; 2484 } 2485 } 2486 if (!do_next) 2487 break; 2488 2489 /* Backtrack to previous ' ' (space). */ 2490 do_next = 0; 2491 while ((iter > istart) && !do_next) { 2492 iter--; 2493 if (qla2x00_read_flash_byte(ha, iter) == ' ') 2494 do_next++; 2495 } 2496 if (!do_next) 2497 break; 2498 2499 /* 2500 * Mark end of version tag, and find previous ' ' (space) or 2501 * string length (recent FCODE images -- major hack ahead!!!). 2502 */ 2503 vend = iter - 1; 2504 do_next = 0; 2505 while ((iter > istart) && !do_next) { 2506 iter--; 2507 rbyte = qla2x00_read_flash_byte(ha, iter); 2508 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 2509 do_next++; 2510 } 2511 if (!do_next) 2512 break; 2513 2514 /* Mark beginning of version tag, and copy data. */ 2515 iter++; 2516 if ((vend - iter) && 2517 ((vend - iter) < sizeof(ha->fcode_revision))) { 2518 vbyte = ha->fcode_revision; 2519 while (iter <= vend) { 2520 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 2521 iter++; 2522 } 2523 ret = QLA_SUCCESS; 2524 } 2525 } while (0); 2526 2527 if (ret != QLA_SUCCESS) 2528 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2529 } 2530 2531 int 2532 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 2533 { 2534 int ret = QLA_SUCCESS; 2535 uint8_t code_type, last_image; 2536 uint32_t pcihdr, pcids; 2537 uint8_t *dbyte; 2538 uint16_t *dcode; 2539 struct qla_hw_data *ha = vha->hw; 2540 2541 if (!ha->pio_address || !mbuf) 2542 return QLA_FUNCTION_FAILED; 2543 2544 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 2545 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 2546 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2547 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2548 2549 qla2x00_flash_enable(ha); 2550 2551 /* Begin with first PCI expansion ROM header. */ 2552 pcihdr = 0; 2553 last_image = 1; 2554 do { 2555 /* Verify PCI expansion ROM header. */ 2556 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 2557 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 2558 /* No signature */ 2559 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM " 2560 "signature.\n")); 2561 ret = QLA_FUNCTION_FAILED; 2562 break; 2563 } 2564 2565 /* Locate PCI data structure. */ 2566 pcids = pcihdr + 2567 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 2568 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 2569 2570 /* Validate signature of PCI data structure. */ 2571 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 2572 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 2573 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 2574 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 2575 /* Incorrect header. */ 2576 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not " 2577 "found pcir_adr=%x.\n", pcids)); 2578 ret = QLA_FUNCTION_FAILED; 2579 break; 2580 } 2581 2582 /* Read version */ 2583 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 2584 switch (code_type) { 2585 case ROM_CODE_TYPE_BIOS: 2586 /* Intel x86, PC-AT compatible. */ 2587 ha->bios_revision[0] = 2588 qla2x00_read_flash_byte(ha, pcids + 0x12); 2589 ha->bios_revision[1] = 2590 qla2x00_read_flash_byte(ha, pcids + 0x13); 2591 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n", 2592 ha->bios_revision[1], ha->bios_revision[0])); 2593 break; 2594 case ROM_CODE_TYPE_FCODE: 2595 /* Open Firmware standard for PCI (FCode). */ 2596 /* Eeeewww... */ 2597 qla2x00_get_fcode_version(ha, pcids); 2598 break; 2599 case ROM_CODE_TYPE_EFI: 2600 /* Extensible Firmware Interface (EFI). */ 2601 ha->efi_revision[0] = 2602 qla2x00_read_flash_byte(ha, pcids + 0x12); 2603 ha->efi_revision[1] = 2604 qla2x00_read_flash_byte(ha, pcids + 0x13); 2605 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n", 2606 ha->efi_revision[1], ha->efi_revision[0])); 2607 break; 2608 default: 2609 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code " 2610 "type %x at pcids %x.\n", code_type, pcids)); 2611 break; 2612 } 2613 2614 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 2615 2616 /* Locate next PCI expansion ROM. */ 2617 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 2618 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 2619 } while (!last_image); 2620 2621 if (IS_QLA2322(ha)) { 2622 /* Read firmware image information. */ 2623 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2624 dbyte = mbuf; 2625 memset(dbyte, 0, 8); 2626 dcode = (uint16_t *)dbyte; 2627 2628 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, 2629 8); 2630 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from " 2631 "flash:\n")); 2632 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8)); 2633 2634 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 2635 dcode[2] == 0xffff && dcode[3] == 0xffff) || 2636 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 2637 dcode[3] == 0)) { 2638 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw " 2639 "revision at %x.\n", ha->flt_region_fw * 4)); 2640 } else { 2641 /* values are in big endian */ 2642 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 2643 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 2644 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 2645 } 2646 } 2647 2648 qla2x00_flash_disable(ha); 2649 2650 return ret; 2651 } 2652 2653 int 2654 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 2655 { 2656 int ret = QLA_SUCCESS; 2657 uint32_t pcihdr, pcids; 2658 uint32_t *dcode; 2659 uint8_t *bcode; 2660 uint8_t code_type, last_image; 2661 int i; 2662 struct qla_hw_data *ha = vha->hw; 2663 2664 if (IS_QLA82XX(ha)) 2665 return ret; 2666 2667 if (!mbuf) 2668 return QLA_FUNCTION_FAILED; 2669 2670 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 2671 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 2672 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 2673 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2674 2675 dcode = mbuf; 2676 2677 /* Begin with first PCI expansion ROM header. */ 2678 pcihdr = ha->flt_region_boot << 2; 2679 last_image = 1; 2680 do { 2681 /* Verify PCI expansion ROM header. */ 2682 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 2683 bcode = mbuf + (pcihdr % 4); 2684 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) { 2685 /* No signature */ 2686 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM " 2687 "signature.\n")); 2688 ret = QLA_FUNCTION_FAILED; 2689 break; 2690 } 2691 2692 /* Locate PCI data structure. */ 2693 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 2694 2695 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 2696 bcode = mbuf + (pcihdr % 4); 2697 2698 /* Validate signature of PCI data structure. */ 2699 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 2700 bcode[0x2] != 'I' || bcode[0x3] != 'R') { 2701 /* Incorrect header. */ 2702 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not " 2703 "found pcir_adr=%x.\n", pcids)); 2704 ret = QLA_FUNCTION_FAILED; 2705 break; 2706 } 2707 2708 /* Read version */ 2709 code_type = bcode[0x14]; 2710 switch (code_type) { 2711 case ROM_CODE_TYPE_BIOS: 2712 /* Intel x86, PC-AT compatible. */ 2713 ha->bios_revision[0] = bcode[0x12]; 2714 ha->bios_revision[1] = bcode[0x13]; 2715 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n", 2716 ha->bios_revision[1], ha->bios_revision[0])); 2717 break; 2718 case ROM_CODE_TYPE_FCODE: 2719 /* Open Firmware standard for PCI (FCode). */ 2720 ha->fcode_revision[0] = bcode[0x12]; 2721 ha->fcode_revision[1] = bcode[0x13]; 2722 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n", 2723 ha->fcode_revision[1], ha->fcode_revision[0])); 2724 break; 2725 case ROM_CODE_TYPE_EFI: 2726 /* Extensible Firmware Interface (EFI). */ 2727 ha->efi_revision[0] = bcode[0x12]; 2728 ha->efi_revision[1] = bcode[0x13]; 2729 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n", 2730 ha->efi_revision[1], ha->efi_revision[0])); 2731 break; 2732 default: 2733 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code " 2734 "type %x at pcids %x.\n", code_type, pcids)); 2735 break; 2736 } 2737 2738 last_image = bcode[0x15] & BIT_7; 2739 2740 /* Locate next PCI expansion ROM. */ 2741 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 2742 } while (!last_image); 2743 2744 /* Read firmware image information. */ 2745 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 2746 dcode = mbuf; 2747 2748 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4); 2749 for (i = 0; i < 4; i++) 2750 dcode[i] = be32_to_cpu(dcode[i]); 2751 2752 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff && 2753 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) || 2754 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 2755 dcode[3] == 0)) { 2756 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw " 2757 "revision at %x.\n", ha->flt_region_fw * 4)); 2758 } else { 2759 ha->fw_revision[0] = dcode[0]; 2760 ha->fw_revision[1] = dcode[1]; 2761 ha->fw_revision[2] = dcode[2]; 2762 ha->fw_revision[3] = dcode[3]; 2763 } 2764 2765 /* Check for golden firmware and get version if available */ 2766 if (!IS_QLA81XX(ha)) { 2767 /* Golden firmware is not present in non 81XX adapters */ 2768 return ret; 2769 } 2770 2771 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); 2772 dcode = mbuf; 2773 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, 2774 ha->flt_region_gold_fw << 2, 32); 2775 2776 if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF && 2777 dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) { 2778 DEBUG2(qla_printk(KERN_INFO, ha, 2779 "%s(%ld): Unrecognized golden fw at 0x%x.\n", 2780 __func__, vha->host_no, ha->flt_region_gold_fw * 4)); 2781 return ret; 2782 } 2783 2784 for (i = 4; i < 8; i++) 2785 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]); 2786 2787 return ret; 2788 } 2789 2790 static int 2791 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) 2792 { 2793 if (pos >= end || *pos != 0x82) 2794 return 0; 2795 2796 pos += 3 + pos[1]; 2797 if (pos >= end || *pos != 0x90) 2798 return 0; 2799 2800 pos += 3 + pos[1]; 2801 if (pos >= end || *pos != 0x78) 2802 return 0; 2803 2804 return 1; 2805 } 2806 2807 int 2808 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) 2809 { 2810 struct qla_hw_data *ha = vha->hw; 2811 uint8_t *pos = ha->vpd; 2812 uint8_t *end = pos + ha->vpd_size; 2813 int len = 0; 2814 2815 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) 2816 return 0; 2817 2818 while (pos < end && *pos != 0x78) { 2819 len = (*pos == 0x82) ? pos[1] : pos[2]; 2820 2821 if (!strncmp(pos, key, strlen(key))) 2822 break; 2823 2824 if (*pos != 0x90 && *pos != 0x91) 2825 pos += len; 2826 2827 pos += 3; 2828 } 2829 2830 if (pos < end - len && *pos != 0x78) 2831 return snprintf(str, size, "%.*s", len, pos + 3); 2832 2833 return 0; 2834 } 2835 2836 int 2837 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha) 2838 { 2839 int len, max_len; 2840 uint32_t fcp_prio_addr; 2841 struct qla_hw_data *ha = vha->hw; 2842 2843 if (!ha->fcp_prio_cfg) { 2844 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); 2845 if (!ha->fcp_prio_cfg) { 2846 qla_printk(KERN_WARNING, ha, 2847 "Unable to allocate memory for fcp priority data " 2848 "(%x).\n", FCP_PRIO_CFG_SIZE); 2849 return QLA_FUNCTION_FAILED; 2850 } 2851 } 2852 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); 2853 2854 fcp_prio_addr = ha->flt_region_fcp_prio; 2855 2856 /* first read the fcp priority data header from flash */ 2857 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg, 2858 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE); 2859 2860 if (!qla24xx_fcp_prio_cfg_valid(ha->fcp_prio_cfg, 0)) 2861 goto fail; 2862 2863 /* read remaining FCP CMD config data from flash */ 2864 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2); 2865 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE; 2866 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; 2867 2868 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0], 2869 fcp_prio_addr << 2, (len < max_len ? len : max_len)); 2870 2871 /* revalidate the entire FCP priority config data, including entries */ 2872 if (!qla24xx_fcp_prio_cfg_valid(ha->fcp_prio_cfg, 1)) 2873 goto fail; 2874 2875 ha->flags.fcp_prio_enabled = 1; 2876 return QLA_SUCCESS; 2877 fail: 2878 vfree(ha->fcp_prio_cfg); 2879 ha->fcp_prio_cfg = NULL; 2880 return QLA_FUNCTION_FAILED; 2881 } 2882