1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 #include <linux/uaccess.h> 13 14 /* 15 * NVRAM support routines 16 */ 17 18 /** 19 * qla2x00_lock_nvram_access() - 20 * @ha: HA context 21 */ 22 static void 23 qla2x00_lock_nvram_access(struct qla_hw_data *ha) 24 { 25 uint16_t data; 26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 27 28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 29 data = RD_REG_WORD(®->nvram); 30 while (data & NVR_BUSY) { 31 udelay(100); 32 data = RD_REG_WORD(®->nvram); 33 } 34 35 /* Lock resource */ 36 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 37 RD_REG_WORD(®->u.isp2300.host_semaphore); 38 udelay(5); 39 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 40 while ((data & BIT_0) == 0) { 41 /* Lock failed */ 42 udelay(100); 43 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1); 44 RD_REG_WORD(®->u.isp2300.host_semaphore); 45 udelay(5); 46 data = RD_REG_WORD(®->u.isp2300.host_semaphore); 47 } 48 } 49 } 50 51 /** 52 * qla2x00_unlock_nvram_access() - 53 * @ha: HA context 54 */ 55 static void 56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha) 57 { 58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 59 60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 61 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0); 62 RD_REG_WORD(®->u.isp2300.host_semaphore); 63 } 64 } 65 66 /** 67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 68 * @ha: HA context 69 * @data: Serial interface selector 70 */ 71 static void 72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data) 73 { 74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 75 76 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 77 RD_REG_WORD(®->nvram); /* PCI Posting. */ 78 NVRAM_DELAY(); 79 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK | 80 NVR_WRT_ENABLE); 81 RD_REG_WORD(®->nvram); /* PCI Posting. */ 82 NVRAM_DELAY(); 83 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 84 RD_REG_WORD(®->nvram); /* PCI Posting. */ 85 NVRAM_DELAY(); 86 } 87 88 /** 89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 90 * NVRAM. 91 * @ha: HA context 92 * @nv_cmd: NVRAM command 93 * 94 * Bit definitions for NVRAM command: 95 * 96 * Bit 26 = start bit 97 * Bit 25, 24 = opcode 98 * Bit 23-16 = address 99 * Bit 15-0 = write data 100 * 101 * Returns the word read from nvram @addr. 102 */ 103 static uint16_t 104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) 105 { 106 uint8_t cnt; 107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 108 uint16_t data = 0; 109 uint16_t reg_data; 110 111 /* Send command to NVRAM. */ 112 nv_cmd <<= 5; 113 for (cnt = 0; cnt < 11; cnt++) { 114 if (nv_cmd & BIT_31) 115 qla2x00_nv_write(ha, NVR_DATA_OUT); 116 else 117 qla2x00_nv_write(ha, 0); 118 nv_cmd <<= 1; 119 } 120 121 /* Read data from NVRAM. */ 122 for (cnt = 0; cnt < 16; cnt++) { 123 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK); 124 RD_REG_WORD(®->nvram); /* PCI Posting. */ 125 NVRAM_DELAY(); 126 data <<= 1; 127 reg_data = RD_REG_WORD(®->nvram); 128 if (reg_data & NVR_DATA_IN) 129 data |= BIT_0; 130 WRT_REG_WORD(®->nvram, NVR_SELECT); 131 RD_REG_WORD(®->nvram); /* PCI Posting. */ 132 NVRAM_DELAY(); 133 } 134 135 /* Deselect chip. */ 136 WRT_REG_WORD(®->nvram, NVR_DESELECT); 137 RD_REG_WORD(®->nvram); /* PCI Posting. */ 138 NVRAM_DELAY(); 139 140 return data; 141 } 142 143 144 /** 145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 146 * request routine to get the word from NVRAM. 147 * @ha: HA context 148 * @addr: Address in NVRAM to read 149 * 150 * Returns the word read from nvram @addr. 151 */ 152 static uint16_t 153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) 154 { 155 uint16_t data; 156 uint32_t nv_cmd; 157 158 nv_cmd = addr << 16; 159 nv_cmd |= NV_READ_OP; 160 data = qla2x00_nvram_request(ha, nv_cmd); 161 162 return (data); 163 } 164 165 /** 166 * qla2x00_nv_deselect() - Deselect NVRAM operations. 167 * @ha: HA context 168 */ 169 static void 170 qla2x00_nv_deselect(struct qla_hw_data *ha) 171 { 172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 173 174 WRT_REG_WORD(®->nvram, NVR_DESELECT); 175 RD_REG_WORD(®->nvram); /* PCI Posting. */ 176 NVRAM_DELAY(); 177 } 178 179 /** 180 * qla2x00_write_nvram_word() - Write NVRAM data. 181 * @ha: HA context 182 * @addr: Address in NVRAM to write 183 * @data: word to program 184 */ 185 static void 186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data) 187 { 188 int count; 189 uint16_t word; 190 uint32_t nv_cmd, wait_cnt; 191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 192 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 193 194 qla2x00_nv_write(ha, NVR_DATA_OUT); 195 qla2x00_nv_write(ha, 0); 196 qla2x00_nv_write(ha, 0); 197 198 for (word = 0; word < 8; word++) 199 qla2x00_nv_write(ha, NVR_DATA_OUT); 200 201 qla2x00_nv_deselect(ha); 202 203 /* Write data */ 204 nv_cmd = (addr << 16) | NV_WRITE_OP; 205 nv_cmd |= data; 206 nv_cmd <<= 5; 207 for (count = 0; count < 27; count++) { 208 if (nv_cmd & BIT_31) 209 qla2x00_nv_write(ha, NVR_DATA_OUT); 210 else 211 qla2x00_nv_write(ha, 0); 212 213 nv_cmd <<= 1; 214 } 215 216 qla2x00_nv_deselect(ha); 217 218 /* Wait for NVRAM to become ready */ 219 WRT_REG_WORD(®->nvram, NVR_SELECT); 220 RD_REG_WORD(®->nvram); /* PCI Posting. */ 221 wait_cnt = NVR_WAIT_CNT; 222 do { 223 if (!--wait_cnt) { 224 ql_dbg(ql_dbg_user, vha, 0x708d, 225 "NVRAM didn't go ready...\n"); 226 break; 227 } 228 NVRAM_DELAY(); 229 word = RD_REG_WORD(®->nvram); 230 } while ((word & NVR_DATA_IN) == 0); 231 232 qla2x00_nv_deselect(ha); 233 234 /* Disable writes */ 235 qla2x00_nv_write(ha, NVR_DATA_OUT); 236 for (count = 0; count < 10; count++) 237 qla2x00_nv_write(ha, 0); 238 239 qla2x00_nv_deselect(ha); 240 } 241 242 static int 243 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, 244 uint16_t data, uint32_t tmo) 245 { 246 int ret, count; 247 uint16_t word; 248 uint32_t nv_cmd; 249 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 250 251 ret = QLA_SUCCESS; 252 253 qla2x00_nv_write(ha, NVR_DATA_OUT); 254 qla2x00_nv_write(ha, 0); 255 qla2x00_nv_write(ha, 0); 256 257 for (word = 0; word < 8; word++) 258 qla2x00_nv_write(ha, NVR_DATA_OUT); 259 260 qla2x00_nv_deselect(ha); 261 262 /* Write data */ 263 nv_cmd = (addr << 16) | NV_WRITE_OP; 264 nv_cmd |= data; 265 nv_cmd <<= 5; 266 for (count = 0; count < 27; count++) { 267 if (nv_cmd & BIT_31) 268 qla2x00_nv_write(ha, NVR_DATA_OUT); 269 else 270 qla2x00_nv_write(ha, 0); 271 272 nv_cmd <<= 1; 273 } 274 275 qla2x00_nv_deselect(ha); 276 277 /* Wait for NVRAM to become ready */ 278 WRT_REG_WORD(®->nvram, NVR_SELECT); 279 RD_REG_WORD(®->nvram); /* PCI Posting. */ 280 do { 281 NVRAM_DELAY(); 282 word = RD_REG_WORD(®->nvram); 283 if (!--tmo) { 284 ret = QLA_FUNCTION_FAILED; 285 break; 286 } 287 } while ((word & NVR_DATA_IN) == 0); 288 289 qla2x00_nv_deselect(ha); 290 291 /* Disable writes */ 292 qla2x00_nv_write(ha, NVR_DATA_OUT); 293 for (count = 0; count < 10; count++) 294 qla2x00_nv_write(ha, 0); 295 296 qla2x00_nv_deselect(ha); 297 298 return ret; 299 } 300 301 /** 302 * qla2x00_clear_nvram_protection() - 303 * @ha: HA context 304 */ 305 static int 306 qla2x00_clear_nvram_protection(struct qla_hw_data *ha) 307 { 308 int ret, stat; 309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 310 uint32_t word, wait_cnt; 311 uint16_t wprot, wprot_old; 312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 313 314 /* Clear NVRAM write protection. */ 315 ret = QLA_FUNCTION_FAILED; 316 317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 319 cpu_to_le16(0x1234), 100000); 320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 321 if (stat != QLA_SUCCESS || wprot != 0x1234) { 322 /* Write enable. */ 323 qla2x00_nv_write(ha, NVR_DATA_OUT); 324 qla2x00_nv_write(ha, 0); 325 qla2x00_nv_write(ha, 0); 326 for (word = 0; word < 8; word++) 327 qla2x00_nv_write(ha, NVR_DATA_OUT); 328 329 qla2x00_nv_deselect(ha); 330 331 /* Enable protection register. */ 332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 333 qla2x00_nv_write(ha, NVR_PR_ENABLE); 334 qla2x00_nv_write(ha, NVR_PR_ENABLE); 335 for (word = 0; word < 8; word++) 336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 337 338 qla2x00_nv_deselect(ha); 339 340 /* Clear protection register (ffff is cleared). */ 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 344 for (word = 0; word < 8; word++) 345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 346 347 qla2x00_nv_deselect(ha); 348 349 /* Wait for NVRAM to become ready. */ 350 WRT_REG_WORD(®->nvram, NVR_SELECT); 351 RD_REG_WORD(®->nvram); /* PCI Posting. */ 352 wait_cnt = NVR_WAIT_CNT; 353 do { 354 if (!--wait_cnt) { 355 ql_dbg(ql_dbg_user, vha, 0x708e, 356 "NVRAM didn't go ready...\n"); 357 break; 358 } 359 NVRAM_DELAY(); 360 word = RD_REG_WORD(®->nvram); 361 } while ((word & NVR_DATA_IN) == 0); 362 363 if (wait_cnt) 364 ret = QLA_SUCCESS; 365 } else 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 367 368 return ret; 369 } 370 371 static void 372 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) 373 { 374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 375 uint32_t word, wait_cnt; 376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 377 378 if (stat != QLA_SUCCESS) 379 return; 380 381 /* Set NVRAM write protection. */ 382 /* Write enable. */ 383 qla2x00_nv_write(ha, NVR_DATA_OUT); 384 qla2x00_nv_write(ha, 0); 385 qla2x00_nv_write(ha, 0); 386 for (word = 0; word < 8; word++) 387 qla2x00_nv_write(ha, NVR_DATA_OUT); 388 389 qla2x00_nv_deselect(ha); 390 391 /* Enable protection register. */ 392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 393 qla2x00_nv_write(ha, NVR_PR_ENABLE); 394 qla2x00_nv_write(ha, NVR_PR_ENABLE); 395 for (word = 0; word < 8; word++) 396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 397 398 qla2x00_nv_deselect(ha); 399 400 /* Enable protection register. */ 401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 402 qla2x00_nv_write(ha, NVR_PR_ENABLE); 403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 404 for (word = 0; word < 8; word++) 405 qla2x00_nv_write(ha, NVR_PR_ENABLE); 406 407 qla2x00_nv_deselect(ha); 408 409 /* Wait for NVRAM to become ready. */ 410 WRT_REG_WORD(®->nvram, NVR_SELECT); 411 RD_REG_WORD(®->nvram); /* PCI Posting. */ 412 wait_cnt = NVR_WAIT_CNT; 413 do { 414 if (!--wait_cnt) { 415 ql_dbg(ql_dbg_user, vha, 0x708f, 416 "NVRAM didn't go ready...\n"); 417 break; 418 } 419 NVRAM_DELAY(); 420 word = RD_REG_WORD(®->nvram); 421 } while ((word & NVR_DATA_IN) == 0); 422 } 423 424 425 /*****************************************************************************/ 426 /* Flash Manipulation Routines */ 427 /*****************************************************************************/ 428 429 static inline uint32_t 430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) 431 { 432 return ha->flash_conf_off + faddr; 433 } 434 435 static inline uint32_t 436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) 437 { 438 return ha->flash_data_off + faddr; 439 } 440 441 static inline uint32_t 442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) 443 { 444 return ha->nvram_conf_off + naddr; 445 } 446 447 static inline uint32_t 448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) 449 { 450 return ha->nvram_data_off + naddr; 451 } 452 453 static int 454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t *data) 455 { 456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 457 ulong cnt = 30000; 458 459 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG); 460 461 while (cnt--) { 462 if (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) { 463 *data = RD_REG_DWORD(®->flash_data); 464 return QLA_SUCCESS; 465 } 466 udelay(10); 467 cond_resched(); 468 } 469 470 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 471 "Flash read dword at %x timeout.\n", addr); 472 *data = 0xDEADDEAD; 473 return QLA_FUNCTION_TIMEOUT; 474 } 475 476 uint32_t * 477 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 478 uint32_t dwords) 479 { 480 ulong i; 481 struct qla_hw_data *ha = vha->hw; 482 483 /* Dword reads to flash. */ 484 faddr = flash_data_addr(ha, faddr); 485 for (i = 0; i < dwords; i++, faddr++, dwptr++) { 486 if (qla24xx_read_flash_dword(ha, faddr, dwptr)) 487 break; 488 cpu_to_le32s(dwptr); 489 } 490 491 return dwptr; 492 } 493 494 static int 495 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) 496 { 497 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 498 ulong cnt = 500000; 499 500 WRT_REG_DWORD(®->flash_data, data); 501 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG); 502 503 while (cnt--) { 504 if (!(RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG)) 505 return QLA_SUCCESS; 506 udelay(10); 507 cond_resched(); 508 } 509 510 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 511 "Flash write dword at %x timeout.\n", addr); 512 return QLA_FUNCTION_TIMEOUT; 513 } 514 515 static void 516 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 517 uint8_t *flash_id) 518 { 519 uint32_t faddr, ids = 0; 520 521 *man_id = *flash_id = 0; 522 523 faddr = flash_conf_addr(ha, 0x03ab); 524 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 525 *man_id = LSB(ids); 526 *flash_id = MSB(ids); 527 } 528 529 /* Check if man_id and flash_id are valid. */ 530 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 531 /* Read information using 0x9f opcode 532 * Device ID, Mfg ID would be read in the format: 533 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 534 * Example: ATMEL 0x00 01 45 1F 535 * Extract MFG and Dev ID from last two bytes. 536 */ 537 faddr = flash_conf_addr(ha, 0x009f); 538 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 539 *man_id = LSB(ids); 540 *flash_id = MSB(ids); 541 } 542 } 543 } 544 545 static int 546 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) 547 { 548 const char *loc, *locations[] = { "DEF", "PCI" }; 549 uint32_t pcihdr, pcids; 550 uint16_t cnt, chksum, *wptr; 551 struct qla_hw_data *ha = vha->hw; 552 struct req_que *req = ha->req_q_map[0]; 553 struct qla_flt_location *fltl = (void *)req->ring; 554 uint32_t *dcode = (void *)req->ring; 555 uint8_t *buf = (void *)req->ring, *bcode, last_image; 556 557 /* 558 * FLT-location structure resides after the last PCI region. 559 */ 560 561 /* Begin with sane defaults. */ 562 loc = locations[0]; 563 *start = 0; 564 if (IS_QLA24XX_TYPE(ha)) 565 *start = FA_FLASH_LAYOUT_ADDR_24; 566 else if (IS_QLA25XX(ha)) 567 *start = FA_FLASH_LAYOUT_ADDR; 568 else if (IS_QLA81XX(ha)) 569 *start = FA_FLASH_LAYOUT_ADDR_81; 570 else if (IS_P3P_TYPE(ha)) { 571 *start = FA_FLASH_LAYOUT_ADDR_82; 572 goto end; 573 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 574 *start = FA_FLASH_LAYOUT_ADDR_83; 575 goto end; 576 } else if (IS_QLA28XX(ha)) { 577 *start = FA_FLASH_LAYOUT_ADDR_28; 578 goto end; 579 } 580 581 /* Begin with first PCI expansion ROM header. */ 582 pcihdr = 0; 583 do { 584 /* Verify PCI expansion ROM header. */ 585 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 586 bcode = buf + (pcihdr % 4); 587 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) 588 goto end; 589 590 /* Locate PCI data structure. */ 591 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 592 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 593 bcode = buf + (pcihdr % 4); 594 595 /* Validate signature of PCI data structure. */ 596 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 597 bcode[0x2] != 'I' || bcode[0x3] != 'R') 598 goto end; 599 600 last_image = bcode[0x15] & BIT_7; 601 602 /* Locate next PCI expansion ROM. */ 603 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 604 } while (!last_image); 605 606 /* Now verify FLT-location structure. */ 607 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, sizeof(*fltl) >> 2); 608 if (memcmp(fltl->sig, "QFLT", 4)) 609 goto end; 610 611 wptr = (void *)req->ring; 612 cnt = sizeof(*fltl) / sizeof(*wptr); 613 for (chksum = 0; cnt--; wptr++) 614 chksum += le16_to_cpu(*wptr); 615 if (chksum) { 616 ql_log(ql_log_fatal, vha, 0x0045, 617 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); 618 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e, 619 fltl, sizeof(*fltl)); 620 return QLA_FUNCTION_FAILED; 621 } 622 623 /* Good data. Use specified location. */ 624 loc = locations[1]; 625 *start = (le16_to_cpu(fltl->start_hi) << 16 | 626 le16_to_cpu(fltl->start_lo)) >> 2; 627 end: 628 ql_dbg(ql_dbg_init, vha, 0x0046, 629 "FLTL[%s] = 0x%x.\n", 630 loc, *start); 631 return QLA_SUCCESS; 632 } 633 634 static void 635 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) 636 { 637 const char *locations[] = { "DEF", "FLT" }, *loc = locations[1]; 638 const uint32_t def_fw[] = 639 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 }; 640 const uint32_t def_boot[] = 641 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 }; 642 const uint32_t def_vpd_nvram[] = 643 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 }; 644 const uint32_t def_vpd0[] = 645 { 0, 0, FA_VPD0_ADDR_81 }; 646 const uint32_t def_vpd1[] = 647 { 0, 0, FA_VPD1_ADDR_81 }; 648 const uint32_t def_nvram0[] = 649 { 0, 0, FA_NVRAM0_ADDR_81 }; 650 const uint32_t def_nvram1[] = 651 { 0, 0, FA_NVRAM1_ADDR_81 }; 652 const uint32_t def_fdt[] = 653 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR, 654 FA_FLASH_DESCR_ADDR_81 }; 655 const uint32_t def_npiv_conf0[] = 656 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR, 657 FA_NPIV_CONF0_ADDR_81 }; 658 const uint32_t def_npiv_conf1[] = 659 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR, 660 FA_NPIV_CONF1_ADDR_81 }; 661 const uint32_t fcp_prio_cfg0[] = 662 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25, 663 0 }; 664 const uint32_t fcp_prio_cfg1[] = 665 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25, 666 0 }; 667 668 struct qla_hw_data *ha = vha->hw; 669 uint32_t def = IS_QLA81XX(ha) ? 2 : IS_QLA25XX(ha) ? 1 : 0; 670 struct qla_flt_header *flt = (void *)ha->flt; 671 struct qla_flt_region *region = (void *)&flt[1]; 672 uint16_t *wptr, cnt, chksum; 673 uint32_t start; 674 675 /* Assign FCP prio region since older adapters may not have FLT, or 676 FCP prio region in it's FLT. 677 */ 678 ha->flt_region_fcp_prio = (ha->port_no == 0) ? 679 fcp_prio_cfg0[def] : fcp_prio_cfg1[def]; 680 681 ha->flt_region_flt = flt_addr; 682 wptr = (uint16_t *)ha->flt; 683 qla24xx_read_flash_data(vha, (void *)flt, flt_addr, 684 (sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE) >> 2); 685 686 if (le16_to_cpu(*wptr) == 0xffff) 687 goto no_flash_data; 688 if (flt->version != cpu_to_le16(1)) { 689 ql_log(ql_log_warn, vha, 0x0047, 690 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 691 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 692 le16_to_cpu(flt->checksum)); 693 goto no_flash_data; 694 } 695 696 cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr); 697 for (chksum = 0; cnt--; wptr++) 698 chksum += le16_to_cpu(*wptr); 699 if (chksum) { 700 ql_log(ql_log_fatal, vha, 0x0048, 701 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 702 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 703 le16_to_cpu(flt->checksum)); 704 goto no_flash_data; 705 } 706 707 cnt = le16_to_cpu(flt->length) / sizeof(*region); 708 for ( ; cnt; cnt--, region++) { 709 /* Store addresses as DWORD offsets. */ 710 start = le32_to_cpu(region->start) >> 2; 711 ql_dbg(ql_dbg_init, vha, 0x0049, 712 "FLT[%#x]: start=%#x end=%#x size=%#x.\n", 713 le16_to_cpu(region->code), start, 714 le32_to_cpu(region->end) >> 2, 715 le32_to_cpu(region->size) >> 2); 716 if (region->attribute) 717 ql_log(ql_dbg_init, vha, 0xffff, 718 "Region %x is secure\n", region->code); 719 720 switch (le16_to_cpu(region->code)) { 721 case FLT_REG_FCOE_FW: 722 if (!IS_QLA8031(ha)) 723 break; 724 ha->flt_region_fw = start; 725 break; 726 case FLT_REG_FW: 727 if (IS_QLA8031(ha)) 728 break; 729 ha->flt_region_fw = start; 730 break; 731 case FLT_REG_BOOT_CODE: 732 ha->flt_region_boot = start; 733 break; 734 case FLT_REG_VPD_0: 735 if (IS_QLA8031(ha)) 736 break; 737 ha->flt_region_vpd_nvram = start; 738 if (IS_P3P_TYPE(ha)) 739 break; 740 if (ha->port_no == 0) 741 ha->flt_region_vpd = start; 742 break; 743 case FLT_REG_VPD_1: 744 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 745 break; 746 if (ha->port_no == 1) 747 ha->flt_region_vpd = start; 748 break; 749 case FLT_REG_VPD_2: 750 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 751 break; 752 if (ha->port_no == 2) 753 ha->flt_region_vpd = start; 754 break; 755 case FLT_REG_VPD_3: 756 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 757 break; 758 if (ha->port_no == 3) 759 ha->flt_region_vpd = start; 760 break; 761 case FLT_REG_NVRAM_0: 762 if (IS_QLA8031(ha)) 763 break; 764 if (ha->port_no == 0) 765 ha->flt_region_nvram = start; 766 break; 767 case FLT_REG_NVRAM_1: 768 if (IS_QLA8031(ha)) 769 break; 770 if (ha->port_no == 1) 771 ha->flt_region_nvram = start; 772 break; 773 case FLT_REG_NVRAM_2: 774 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 775 break; 776 if (ha->port_no == 2) 777 ha->flt_region_nvram = start; 778 break; 779 case FLT_REG_NVRAM_3: 780 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 781 break; 782 if (ha->port_no == 3) 783 ha->flt_region_nvram = start; 784 break; 785 case FLT_REG_FDT: 786 ha->flt_region_fdt = start; 787 break; 788 case FLT_REG_NPIV_CONF_0: 789 if (ha->port_no == 0) 790 ha->flt_region_npiv_conf = start; 791 break; 792 case FLT_REG_NPIV_CONF_1: 793 if (ha->port_no == 1) 794 ha->flt_region_npiv_conf = start; 795 break; 796 case FLT_REG_GOLD_FW: 797 ha->flt_region_gold_fw = start; 798 break; 799 case FLT_REG_FCP_PRIO_0: 800 if (ha->port_no == 0) 801 ha->flt_region_fcp_prio = start; 802 break; 803 case FLT_REG_FCP_PRIO_1: 804 if (ha->port_no == 1) 805 ha->flt_region_fcp_prio = start; 806 break; 807 case FLT_REG_BOOT_CODE_82XX: 808 ha->flt_region_boot = start; 809 break; 810 case FLT_REG_BOOT_CODE_8044: 811 if (IS_QLA8044(ha)) 812 ha->flt_region_boot = start; 813 break; 814 case FLT_REG_FW_82XX: 815 ha->flt_region_fw = start; 816 break; 817 case FLT_REG_CNA_FW: 818 if (IS_CNA_CAPABLE(ha)) 819 ha->flt_region_fw = start; 820 break; 821 case FLT_REG_GOLD_FW_82XX: 822 ha->flt_region_gold_fw = start; 823 break; 824 case FLT_REG_BOOTLOAD_82XX: 825 ha->flt_region_bootload = start; 826 break; 827 case FLT_REG_VPD_8XXX: 828 if (IS_CNA_CAPABLE(ha)) 829 ha->flt_region_vpd = start; 830 break; 831 case FLT_REG_FCOE_NVRAM_0: 832 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 833 break; 834 if (ha->port_no == 0) 835 ha->flt_region_nvram = start; 836 break; 837 case FLT_REG_FCOE_NVRAM_1: 838 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 839 break; 840 if (ha->port_no == 1) 841 ha->flt_region_nvram = start; 842 break; 843 case FLT_REG_IMG_PRI_27XX: 844 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 845 ha->flt_region_img_status_pri = start; 846 break; 847 case FLT_REG_IMG_SEC_27XX: 848 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 849 ha->flt_region_img_status_sec = start; 850 break; 851 case FLT_REG_FW_SEC_27XX: 852 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 853 ha->flt_region_fw_sec = start; 854 break; 855 case FLT_REG_BOOTLOAD_SEC_27XX: 856 if (IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 857 ha->flt_region_boot_sec = start; 858 break; 859 case FLT_REG_AUX_IMG_PRI_28XX: 860 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 861 ha->flt_region_aux_img_status_pri = start; 862 break; 863 case FLT_REG_AUX_IMG_SEC_28XX: 864 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 865 ha->flt_region_aux_img_status_sec = start; 866 break; 867 case FLT_REG_NVRAM_SEC_28XX_0: 868 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 869 if (ha->port_no == 0) 870 ha->flt_region_nvram_sec = start; 871 break; 872 case FLT_REG_NVRAM_SEC_28XX_1: 873 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 874 if (ha->port_no == 1) 875 ha->flt_region_nvram_sec = start; 876 break; 877 case FLT_REG_NVRAM_SEC_28XX_2: 878 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 879 if (ha->port_no == 2) 880 ha->flt_region_nvram_sec = start; 881 break; 882 case FLT_REG_NVRAM_SEC_28XX_3: 883 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 884 if (ha->port_no == 3) 885 ha->flt_region_nvram_sec = start; 886 break; 887 case FLT_REG_VPD_SEC_27XX_0: 888 case FLT_REG_VPD_SEC_28XX_0: 889 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 890 ha->flt_region_vpd_nvram_sec = start; 891 if (ha->port_no == 0) 892 ha->flt_region_vpd_sec = start; 893 } 894 break; 895 case FLT_REG_VPD_SEC_27XX_1: 896 case FLT_REG_VPD_SEC_28XX_1: 897 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 898 if (ha->port_no == 1) 899 ha->flt_region_vpd_sec = start; 900 break; 901 case FLT_REG_VPD_SEC_27XX_2: 902 case FLT_REG_VPD_SEC_28XX_2: 903 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 904 if (ha->port_no == 2) 905 ha->flt_region_vpd_sec = start; 906 break; 907 case FLT_REG_VPD_SEC_27XX_3: 908 case FLT_REG_VPD_SEC_28XX_3: 909 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 910 if (ha->port_no == 3) 911 ha->flt_region_vpd_sec = start; 912 break; 913 } 914 } 915 goto done; 916 917 no_flash_data: 918 /* Use hardcoded defaults. */ 919 loc = locations[0]; 920 ha->flt_region_fw = def_fw[def]; 921 ha->flt_region_boot = def_boot[def]; 922 ha->flt_region_vpd_nvram = def_vpd_nvram[def]; 923 ha->flt_region_vpd = (ha->port_no == 0) ? 924 def_vpd0[def] : def_vpd1[def]; 925 ha->flt_region_nvram = (ha->port_no == 0) ? 926 def_nvram0[def] : def_nvram1[def]; 927 ha->flt_region_fdt = def_fdt[def]; 928 ha->flt_region_npiv_conf = (ha->port_no == 0) ? 929 def_npiv_conf0[def] : def_npiv_conf1[def]; 930 done: 931 ql_dbg(ql_dbg_init, vha, 0x004a, 932 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x " 933 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n", 934 loc, ha->flt_region_boot, ha->flt_region_fw, 935 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram, 936 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf, 937 ha->flt_region_fcp_prio); 938 } 939 940 static void 941 qla2xxx_get_fdt_info(scsi_qla_host_t *vha) 942 { 943 #define FLASH_BLK_SIZE_4K 0x1000 944 #define FLASH_BLK_SIZE_32K 0x8000 945 #define FLASH_BLK_SIZE_64K 0x10000 946 const char *loc, *locations[] = { "MID", "FDT" }; 947 struct qla_hw_data *ha = vha->hw; 948 struct req_que *req = ha->req_q_map[0]; 949 uint16_t cnt, chksum; 950 uint16_t *wptr = (void *)req->ring; 951 struct qla_fdt_layout *fdt = (void *)req->ring; 952 uint8_t man_id, flash_id; 953 uint16_t mid = 0, fid = 0; 954 955 qla24xx_read_flash_data(vha, (void *)fdt, ha->flt_region_fdt, 956 OPTROM_BURST_DWORDS); 957 if (le16_to_cpu(*wptr) == 0xffff) 958 goto no_flash_data; 959 if (memcmp(fdt->sig, "QLID", 4)) 960 goto no_flash_data; 961 962 for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++) 963 chksum += le16_to_cpu(*wptr); 964 if (chksum) { 965 ql_dbg(ql_dbg_init, vha, 0x004c, 966 "Inconsistent FDT detected:" 967 " checksum=0x%x id=%c version0x%x.\n", chksum, 968 fdt->sig[0], le16_to_cpu(fdt->version)); 969 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113, 970 fdt, sizeof(*fdt)); 971 goto no_flash_data; 972 } 973 974 loc = locations[1]; 975 mid = le16_to_cpu(fdt->man_id); 976 fid = le16_to_cpu(fdt->id); 977 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 978 ha->fdt_wrt_enable = fdt->wrt_enable_bits; 979 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd; 980 if (IS_QLA8044(ha)) 981 ha->fdt_erase_cmd = fdt->erase_cmd; 982 else 983 ha->fdt_erase_cmd = 984 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); 985 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 986 if (fdt->unprotect_sec_cmd) { 987 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | 988 fdt->unprotect_sec_cmd); 989 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 990 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd) : 991 flash_conf_addr(ha, 0x0336); 992 } 993 goto done; 994 no_flash_data: 995 loc = locations[0]; 996 if (IS_P3P_TYPE(ha)) { 997 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 998 goto done; 999 } 1000 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 1001 mid = man_id; 1002 fid = flash_id; 1003 ha->fdt_wrt_disable = 0x9c; 1004 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); 1005 switch (man_id) { 1006 case 0xbf: /* STT flash. */ 1007 if (flash_id == 0x8e) 1008 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1009 else 1010 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 1011 1012 if (flash_id == 0x80) 1013 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); 1014 break; 1015 case 0x13: /* ST M25P80. */ 1016 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1017 break; 1018 case 0x1f: /* Atmel 26DF081A. */ 1019 ha->fdt_block_size = FLASH_BLK_SIZE_4K; 1020 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); 1021 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); 1022 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); 1023 break; 1024 default: 1025 /* Default to 64 kb sector size. */ 1026 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1027 break; 1028 } 1029 done: 1030 ql_dbg(ql_dbg_init, vha, 0x004d, 1031 "FDT[%s]: (0x%x/0x%x) erase=0x%x " 1032 "pr=%x wrtd=0x%x blk=0x%x.\n", 1033 loc, mid, fid, 1034 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, 1035 ha->fdt_wrt_disable, ha->fdt_block_size); 1036 1037 } 1038 1039 static void 1040 qla2xxx_get_idc_param(scsi_qla_host_t *vha) 1041 { 1042 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 1043 uint32_t *wptr; 1044 struct qla_hw_data *ha = vha->hw; 1045 struct req_que *req = ha->req_q_map[0]; 1046 1047 if (!(IS_P3P_TYPE(ha))) 1048 return; 1049 1050 wptr = (uint32_t *)req->ring; 1051 ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8); 1052 1053 if (*wptr == cpu_to_le32(0xffffffff)) { 1054 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; 1055 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; 1056 } else { 1057 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr); 1058 wptr++; 1059 ha->fcoe_reset_timeout = le32_to_cpu(*wptr); 1060 } 1061 ql_dbg(ql_dbg_init, vha, 0x004e, 1062 "fcoe_dev_init_timeout=%d " 1063 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout, 1064 ha->fcoe_reset_timeout); 1065 return; 1066 } 1067 1068 int 1069 qla2xxx_get_flash_info(scsi_qla_host_t *vha) 1070 { 1071 int ret; 1072 uint32_t flt_addr; 1073 struct qla_hw_data *ha = vha->hw; 1074 1075 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1076 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && 1077 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1078 return QLA_SUCCESS; 1079 1080 ret = qla2xxx_find_flt_start(vha, &flt_addr); 1081 if (ret != QLA_SUCCESS) 1082 return ret; 1083 1084 qla2xxx_get_flt_info(vha, flt_addr); 1085 qla2xxx_get_fdt_info(vha); 1086 qla2xxx_get_idc_param(vha); 1087 1088 return QLA_SUCCESS; 1089 } 1090 1091 void 1092 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) 1093 { 1094 #define NPIV_CONFIG_SIZE (16*1024) 1095 void *data; 1096 uint16_t *wptr; 1097 uint16_t cnt, chksum; 1098 int i; 1099 struct qla_npiv_header hdr; 1100 struct qla_npiv_entry *entry; 1101 struct qla_hw_data *ha = vha->hw; 1102 1103 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1104 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha)) 1105 return; 1106 1107 if (ha->flags.nic_core_reset_hdlr_active) 1108 return; 1109 1110 if (IS_QLA8044(ha)) 1111 return; 1112 1113 ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2, 1114 sizeof(struct qla_npiv_header)); 1115 if (hdr.version == cpu_to_le16(0xffff)) 1116 return; 1117 if (hdr.version != cpu_to_le16(1)) { 1118 ql_dbg(ql_dbg_user, vha, 0x7090, 1119 "Unsupported NPIV-Config " 1120 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1121 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1122 le16_to_cpu(hdr.checksum)); 1123 return; 1124 } 1125 1126 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); 1127 if (!data) { 1128 ql_log(ql_log_warn, vha, 0x7091, 1129 "Unable to allocate memory for data.\n"); 1130 return; 1131 } 1132 1133 ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2, 1134 NPIV_CONFIG_SIZE); 1135 1136 cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1; 1137 for (wptr = data, chksum = 0; cnt--; wptr++) 1138 chksum += le16_to_cpu(*wptr); 1139 if (chksum) { 1140 ql_dbg(ql_dbg_user, vha, 0x7092, 1141 "Inconsistent NPIV-Config " 1142 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1143 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1144 le16_to_cpu(hdr.checksum)); 1145 goto done; 1146 } 1147 1148 entry = data + sizeof(struct qla_npiv_header); 1149 cnt = le16_to_cpu(hdr.entries); 1150 for (i = 0; cnt; cnt--, entry++, i++) { 1151 uint16_t flags; 1152 struct fc_vport_identifiers vid; 1153 struct fc_vport *vport; 1154 1155 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); 1156 1157 flags = le16_to_cpu(entry->flags); 1158 if (flags == 0xffff) 1159 continue; 1160 if ((flags & BIT_0) == 0) 1161 continue; 1162 1163 memset(&vid, 0, sizeof(vid)); 1164 vid.roles = FC_PORT_ROLE_FCP_INITIATOR; 1165 vid.vport_type = FC_PORTTYPE_NPIV; 1166 vid.disable = false; 1167 vid.port_name = wwn_to_u64(entry->port_name); 1168 vid.node_name = wwn_to_u64(entry->node_name); 1169 1170 ql_dbg(ql_dbg_user, vha, 0x7093, 1171 "NPIV[%02x]: wwpn=%llx wwnn=%llx vf_id=%#x Q_qos=%#x F_qos=%#x.\n", 1172 cnt, vid.port_name, vid.node_name, 1173 le16_to_cpu(entry->vf_id), 1174 entry->q_qos, entry->f_qos); 1175 1176 if (i < QLA_PRECONFIG_VPORTS) { 1177 vport = fc_vport_create(vha->host, 0, &vid); 1178 if (!vport) 1179 ql_log(ql_log_warn, vha, 0x7094, 1180 "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n", 1181 cnt, vid.port_name, vid.node_name); 1182 } 1183 } 1184 done: 1185 kfree(data); 1186 } 1187 1188 static int 1189 qla24xx_unprotect_flash(scsi_qla_host_t *vha) 1190 { 1191 struct qla_hw_data *ha = vha->hw; 1192 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1193 1194 if (ha->flags.fac_supported) 1195 return qla81xx_fac_do_write_enable(vha, 1); 1196 1197 /* Enable flash write. */ 1198 WRT_REG_DWORD(®->ctrl_status, 1199 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1200 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1201 1202 if (!ha->fdt_wrt_disable) 1203 goto done; 1204 1205 /* Disable flash write-protection, first clear SR protection bit */ 1206 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1207 /* Then write zero again to clear remaining SR bits.*/ 1208 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1209 done: 1210 return QLA_SUCCESS; 1211 } 1212 1213 static int 1214 qla24xx_protect_flash(scsi_qla_host_t *vha) 1215 { 1216 struct qla_hw_data *ha = vha->hw; 1217 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1218 ulong cnt = 300; 1219 uint32_t faddr, dword; 1220 1221 if (ha->flags.fac_supported) 1222 return qla81xx_fac_do_write_enable(vha, 0); 1223 1224 if (!ha->fdt_wrt_disable) 1225 goto skip_wrt_protect; 1226 1227 /* Enable flash write-protection and wait for completion. */ 1228 faddr = flash_conf_addr(ha, 0x101); 1229 qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable); 1230 faddr = flash_conf_addr(ha, 0x5); 1231 while (cnt--) { 1232 if (!qla24xx_read_flash_dword(ha, faddr, &dword)) { 1233 if (!(dword & BIT_0)) 1234 break; 1235 } 1236 udelay(10); 1237 } 1238 1239 skip_wrt_protect: 1240 /* Disable flash write. */ 1241 WRT_REG_DWORD(®->ctrl_status, 1242 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1243 1244 return QLA_SUCCESS; 1245 } 1246 1247 static int 1248 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) 1249 { 1250 struct qla_hw_data *ha = vha->hw; 1251 uint32_t start, finish; 1252 1253 if (ha->flags.fac_supported) { 1254 start = fdata >> 2; 1255 finish = start + (ha->fdt_block_size >> 2) - 1; 1256 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha, 1257 start), flash_data_addr(ha, finish)); 1258 } 1259 1260 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, 1261 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) | 1262 ((fdata >> 16) & 0xff)); 1263 } 1264 1265 static int 1266 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 1267 uint32_t dwords) 1268 { 1269 int ret; 1270 ulong liter; 1271 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 1272 uint32_t sec_mask, rest_addr, fdata; 1273 dma_addr_t optrom_dma; 1274 void *optrom = NULL; 1275 struct qla_hw_data *ha = vha->hw; 1276 1277 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 1278 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1279 goto next; 1280 1281 /* Allocate dma buffer for burst write */ 1282 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 1283 &optrom_dma, GFP_KERNEL); 1284 if (!optrom) { 1285 ql_log(ql_log_warn, vha, 0x7095, 1286 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 1287 } 1288 1289 next: 1290 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1291 "Unprotect flash...\n"); 1292 ret = qla24xx_unprotect_flash(vha); 1293 if (ret) { 1294 ql_log(ql_log_warn, vha, 0x7096, 1295 "Failed to unprotect flash.\n"); 1296 goto done; 1297 } 1298 1299 rest_addr = (ha->fdt_block_size >> 2) - 1; 1300 sec_mask = ~rest_addr; 1301 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 1302 fdata = (faddr & sec_mask) << 2; 1303 1304 /* Are we at the beginning of a sector? */ 1305 if (!(faddr & rest_addr)) { 1306 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1307 "Erase sector %#x...\n", faddr); 1308 1309 ret = qla24xx_erase_sector(vha, fdata); 1310 if (ret) { 1311 ql_dbg(ql_dbg_user, vha, 0x7007, 1312 "Failed to erase sector %x.\n", faddr); 1313 break; 1314 } 1315 } 1316 1317 if (optrom) { 1318 /* If smaller than a burst remaining */ 1319 if (dwords - liter < dburst) 1320 dburst = dwords - liter; 1321 1322 /* Copy to dma buffer */ 1323 memcpy(optrom, dwptr, dburst << 2); 1324 1325 /* Burst write */ 1326 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1327 "Write burst (%#lx dwords)...\n", dburst); 1328 ret = qla2x00_load_ram(vha, optrom_dma, 1329 flash_data_addr(ha, faddr), dburst); 1330 if (!ret) { 1331 liter += dburst - 1; 1332 faddr += dburst - 1; 1333 dwptr += dburst - 1; 1334 continue; 1335 } 1336 1337 ql_log(ql_log_warn, vha, 0x7097, 1338 "Failed burst-write at %x (%p/%#llx)....\n", 1339 flash_data_addr(ha, faddr), optrom, 1340 (u64)optrom_dma); 1341 1342 dma_free_coherent(&ha->pdev->dev, 1343 OPTROM_BURST_SIZE, optrom, optrom_dma); 1344 optrom = NULL; 1345 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1346 break; 1347 ql_log(ql_log_warn, vha, 0x7098, 1348 "Reverting to slow write...\n"); 1349 } 1350 1351 /* Slow write */ 1352 ret = qla24xx_write_flash_dword(ha, 1353 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr)); 1354 if (ret) { 1355 ql_dbg(ql_dbg_user, vha, 0x7006, 1356 "Failed slopw write %x (%x)\n", faddr, *dwptr); 1357 break; 1358 } 1359 } 1360 1361 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1362 "Protect flash...\n"); 1363 ret = qla24xx_protect_flash(vha); 1364 if (ret) 1365 ql_log(ql_log_warn, vha, 0x7099, 1366 "Failed to protect flash\n"); 1367 done: 1368 if (optrom) 1369 dma_free_coherent(&ha->pdev->dev, 1370 OPTROM_BURST_SIZE, optrom, optrom_dma); 1371 1372 return ret; 1373 } 1374 1375 uint8_t * 1376 qla2x00_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1377 uint32_t bytes) 1378 { 1379 uint32_t i; 1380 uint16_t *wptr; 1381 struct qla_hw_data *ha = vha->hw; 1382 1383 /* Word reads to NVRAM via registers. */ 1384 wptr = (uint16_t *)buf; 1385 qla2x00_lock_nvram_access(ha); 1386 for (i = 0; i < bytes >> 1; i++, naddr++) 1387 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 1388 naddr)); 1389 qla2x00_unlock_nvram_access(ha); 1390 1391 return buf; 1392 } 1393 1394 uint8_t * 1395 qla24xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1396 uint32_t bytes) 1397 { 1398 struct qla_hw_data *ha = vha->hw; 1399 uint32_t *dwptr = buf; 1400 uint32_t i; 1401 1402 if (IS_P3P_TYPE(ha)) 1403 return buf; 1404 1405 /* Dword reads to flash. */ 1406 naddr = nvram_data_addr(ha, naddr); 1407 bytes >>= 2; 1408 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1409 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1410 break; 1411 cpu_to_le32s(dwptr); 1412 } 1413 1414 return buf; 1415 } 1416 1417 int 1418 qla2x00_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1419 uint32_t bytes) 1420 { 1421 int ret, stat; 1422 uint32_t i; 1423 uint16_t *wptr; 1424 unsigned long flags; 1425 struct qla_hw_data *ha = vha->hw; 1426 1427 ret = QLA_SUCCESS; 1428 1429 spin_lock_irqsave(&ha->hardware_lock, flags); 1430 qla2x00_lock_nvram_access(ha); 1431 1432 /* Disable NVRAM write-protection. */ 1433 stat = qla2x00_clear_nvram_protection(ha); 1434 1435 wptr = (uint16_t *)buf; 1436 for (i = 0; i < bytes >> 1; i++, naddr++) { 1437 qla2x00_write_nvram_word(ha, naddr, 1438 cpu_to_le16(*wptr)); 1439 wptr++; 1440 } 1441 1442 /* Enable NVRAM write-protection. */ 1443 qla2x00_set_nvram_protection(ha, stat); 1444 1445 qla2x00_unlock_nvram_access(ha); 1446 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1447 1448 return ret; 1449 } 1450 1451 int 1452 qla24xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1453 uint32_t bytes) 1454 { 1455 struct qla_hw_data *ha = vha->hw; 1456 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1457 uint32_t *dwptr = buf; 1458 uint32_t i; 1459 int ret; 1460 1461 ret = QLA_SUCCESS; 1462 1463 if (IS_P3P_TYPE(ha)) 1464 return ret; 1465 1466 /* Enable flash write. */ 1467 WRT_REG_DWORD(®->ctrl_status, 1468 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); 1469 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1470 1471 /* Disable NVRAM write-protection. */ 1472 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1473 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1474 1475 /* Dword writes to flash. */ 1476 naddr = nvram_data_addr(ha, naddr); 1477 bytes >>= 2; 1478 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1479 if (qla24xx_write_flash_dword(ha, naddr, cpu_to_le32(*dwptr))) { 1480 ql_dbg(ql_dbg_user, vha, 0x709a, 1481 "Unable to program nvram address=%x data=%x.\n", 1482 naddr, *dwptr); 1483 break; 1484 } 1485 } 1486 1487 /* Enable NVRAM write-protection. */ 1488 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c); 1489 1490 /* Disable flash write. */ 1491 WRT_REG_DWORD(®->ctrl_status, 1492 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1493 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ 1494 1495 return ret; 1496 } 1497 1498 uint8_t * 1499 qla25xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1500 uint32_t bytes) 1501 { 1502 struct qla_hw_data *ha = vha->hw; 1503 uint32_t *dwptr = buf; 1504 uint32_t i; 1505 1506 /* Dword reads to flash. */ 1507 naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr); 1508 bytes >>= 2; 1509 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1510 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1511 break; 1512 1513 cpu_to_le32s(dwptr); 1514 } 1515 1516 return buf; 1517 } 1518 1519 #define RMW_BUFFER_SIZE (64 * 1024) 1520 int 1521 qla25xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1522 uint32_t bytes) 1523 { 1524 struct qla_hw_data *ha = vha->hw; 1525 uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE); 1526 1527 if (!dbuf) 1528 return QLA_MEMORY_ALLOC_FAILED; 1529 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1530 RMW_BUFFER_SIZE); 1531 memcpy(dbuf + (naddr << 2), buf, bytes); 1532 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1533 RMW_BUFFER_SIZE); 1534 vfree(dbuf); 1535 1536 return QLA_SUCCESS; 1537 } 1538 1539 static inline void 1540 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1541 { 1542 if (IS_QLA2322(ha)) { 1543 /* Flip all colors. */ 1544 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1545 /* Turn off. */ 1546 ha->beacon_color_state = 0; 1547 *pflags = GPIO_LED_ALL_OFF; 1548 } else { 1549 /* Turn on. */ 1550 ha->beacon_color_state = QLA_LED_ALL_ON; 1551 *pflags = GPIO_LED_RGA_ON; 1552 } 1553 } else { 1554 /* Flip green led only. */ 1555 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 1556 /* Turn off. */ 1557 ha->beacon_color_state = 0; 1558 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 1559 } else { 1560 /* Turn on. */ 1561 ha->beacon_color_state = QLA_LED_GRN_ON; 1562 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 1563 } 1564 } 1565 } 1566 1567 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) 1568 1569 void 1570 qla2x00_beacon_blink(struct scsi_qla_host *vha) 1571 { 1572 uint16_t gpio_enable; 1573 uint16_t gpio_data; 1574 uint16_t led_color = 0; 1575 unsigned long flags; 1576 struct qla_hw_data *ha = vha->hw; 1577 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1578 1579 if (IS_P3P_TYPE(ha)) 1580 return; 1581 1582 spin_lock_irqsave(&ha->hardware_lock, flags); 1583 1584 /* Save the Original GPIOE. */ 1585 if (ha->pio_address) { 1586 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1587 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1588 } else { 1589 gpio_enable = RD_REG_WORD(®->gpioe); 1590 gpio_data = RD_REG_WORD(®->gpiod); 1591 } 1592 1593 /* Set the modified gpio_enable values */ 1594 gpio_enable |= GPIO_LED_MASK; 1595 1596 if (ha->pio_address) { 1597 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1598 } else { 1599 WRT_REG_WORD(®->gpioe, gpio_enable); 1600 RD_REG_WORD(®->gpioe); 1601 } 1602 1603 qla2x00_flip_colors(ha, &led_color); 1604 1605 /* Clear out any previously set LED color. */ 1606 gpio_data &= ~GPIO_LED_MASK; 1607 1608 /* Set the new input LED color to GPIOD. */ 1609 gpio_data |= led_color; 1610 1611 /* Set the modified gpio_data values */ 1612 if (ha->pio_address) { 1613 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1614 } else { 1615 WRT_REG_WORD(®->gpiod, gpio_data); 1616 RD_REG_WORD(®->gpiod); 1617 } 1618 1619 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1620 } 1621 1622 int 1623 qla2x00_beacon_on(struct scsi_qla_host *vha) 1624 { 1625 uint16_t gpio_enable; 1626 uint16_t gpio_data; 1627 unsigned long flags; 1628 struct qla_hw_data *ha = vha->hw; 1629 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1630 1631 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1632 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 1633 1634 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1635 ql_log(ql_log_warn, vha, 0x709b, 1636 "Unable to update fw options (beacon on).\n"); 1637 return QLA_FUNCTION_FAILED; 1638 } 1639 1640 /* Turn off LEDs. */ 1641 spin_lock_irqsave(&ha->hardware_lock, flags); 1642 if (ha->pio_address) { 1643 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1644 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1645 } else { 1646 gpio_enable = RD_REG_WORD(®->gpioe); 1647 gpio_data = RD_REG_WORD(®->gpiod); 1648 } 1649 gpio_enable |= GPIO_LED_MASK; 1650 1651 /* Set the modified gpio_enable values. */ 1652 if (ha->pio_address) { 1653 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1654 } else { 1655 WRT_REG_WORD(®->gpioe, gpio_enable); 1656 RD_REG_WORD(®->gpioe); 1657 } 1658 1659 /* Clear out previously set LED colour. */ 1660 gpio_data &= ~GPIO_LED_MASK; 1661 if (ha->pio_address) { 1662 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1663 } else { 1664 WRT_REG_WORD(®->gpiod, gpio_data); 1665 RD_REG_WORD(®->gpiod); 1666 } 1667 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1668 1669 /* 1670 * Let the per HBA timer kick off the blinking process based on 1671 * the following flags. No need to do anything else now. 1672 */ 1673 ha->beacon_blink_led = 1; 1674 ha->beacon_color_state = 0; 1675 1676 return QLA_SUCCESS; 1677 } 1678 1679 int 1680 qla2x00_beacon_off(struct scsi_qla_host *vha) 1681 { 1682 int rval = QLA_SUCCESS; 1683 struct qla_hw_data *ha = vha->hw; 1684 1685 ha->beacon_blink_led = 0; 1686 1687 /* Set the on flag so when it gets flipped it will be off. */ 1688 if (IS_QLA2322(ha)) 1689 ha->beacon_color_state = QLA_LED_ALL_ON; 1690 else 1691 ha->beacon_color_state = QLA_LED_GRN_ON; 1692 1693 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ 1694 1695 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1696 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 1697 1698 rval = qla2x00_set_fw_options(vha, ha->fw_options); 1699 if (rval != QLA_SUCCESS) 1700 ql_log(ql_log_warn, vha, 0x709c, 1701 "Unable to update fw options (beacon off).\n"); 1702 return rval; 1703 } 1704 1705 1706 static inline void 1707 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1708 { 1709 /* Flip all colors. */ 1710 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1711 /* Turn off. */ 1712 ha->beacon_color_state = 0; 1713 *pflags = 0; 1714 } else { 1715 /* Turn on. */ 1716 ha->beacon_color_state = QLA_LED_ALL_ON; 1717 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 1718 } 1719 } 1720 1721 void 1722 qla24xx_beacon_blink(struct scsi_qla_host *vha) 1723 { 1724 uint16_t led_color = 0; 1725 uint32_t gpio_data; 1726 unsigned long flags; 1727 struct qla_hw_data *ha = vha->hw; 1728 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1729 1730 /* Save the Original GPIOD. */ 1731 spin_lock_irqsave(&ha->hardware_lock, flags); 1732 gpio_data = RD_REG_DWORD(®->gpiod); 1733 1734 /* Enable the gpio_data reg for update. */ 1735 gpio_data |= GPDX_LED_UPDATE_MASK; 1736 1737 WRT_REG_DWORD(®->gpiod, gpio_data); 1738 gpio_data = RD_REG_DWORD(®->gpiod); 1739 1740 /* Set the color bits. */ 1741 qla24xx_flip_colors(ha, &led_color); 1742 1743 /* Clear out any previously set LED color. */ 1744 gpio_data &= ~GPDX_LED_COLOR_MASK; 1745 1746 /* Set the new input LED color to GPIOD. */ 1747 gpio_data |= led_color; 1748 1749 /* Set the modified gpio_data values. */ 1750 WRT_REG_DWORD(®->gpiod, gpio_data); 1751 gpio_data = RD_REG_DWORD(®->gpiod); 1752 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1753 } 1754 1755 static uint32_t 1756 qla83xx_select_led_port(struct qla_hw_data *ha) 1757 { 1758 uint32_t led_select_value = 0; 1759 1760 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1761 goto out; 1762 1763 if (ha->port_no == 0) 1764 led_select_value = QLA83XX_LED_PORT0; 1765 else 1766 led_select_value = QLA83XX_LED_PORT1; 1767 1768 out: 1769 return led_select_value; 1770 } 1771 1772 void 1773 qla83xx_beacon_blink(struct scsi_qla_host *vha) 1774 { 1775 uint32_t led_select_value; 1776 struct qla_hw_data *ha = vha->hw; 1777 uint16_t led_cfg[6]; 1778 uint16_t orig_led_cfg[6]; 1779 uint32_t led_10_value, led_43_value; 1780 1781 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha) && 1782 !IS_QLA28XX(ha)) 1783 return; 1784 1785 if (!ha->beacon_blink_led) 1786 return; 1787 1788 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 1789 qla2x00_write_ram_word(vha, 0x1003, 0x40000230); 1790 qla2x00_write_ram_word(vha, 0x1004, 0x40000230); 1791 } else if (IS_QLA2031(ha)) { 1792 led_select_value = qla83xx_select_led_port(ha); 1793 1794 qla83xx_wr_reg(vha, led_select_value, 0x40000230); 1795 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230); 1796 } else if (IS_QLA8031(ha)) { 1797 led_select_value = qla83xx_select_led_port(ha); 1798 1799 qla83xx_rd_reg(vha, led_select_value, &led_10_value); 1800 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value); 1801 qla83xx_wr_reg(vha, led_select_value, 0x01f44000); 1802 msleep(500); 1803 qla83xx_wr_reg(vha, led_select_value, 0x400001f4); 1804 msleep(1000); 1805 qla83xx_wr_reg(vha, led_select_value, led_10_value); 1806 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value); 1807 } else if (IS_QLA81XX(ha)) { 1808 int rval; 1809 1810 /* Save Current */ 1811 rval = qla81xx_get_led_config(vha, orig_led_cfg); 1812 /* Do the blink */ 1813 if (rval == QLA_SUCCESS) { 1814 if (IS_QLA81XX(ha)) { 1815 led_cfg[0] = 0x4000; 1816 led_cfg[1] = 0x2000; 1817 led_cfg[2] = 0; 1818 led_cfg[3] = 0; 1819 led_cfg[4] = 0; 1820 led_cfg[5] = 0; 1821 } else { 1822 led_cfg[0] = 0x4000; 1823 led_cfg[1] = 0x4000; 1824 led_cfg[2] = 0x4000; 1825 led_cfg[3] = 0x2000; 1826 led_cfg[4] = 0; 1827 led_cfg[5] = 0x2000; 1828 } 1829 rval = qla81xx_set_led_config(vha, led_cfg); 1830 msleep(1000); 1831 if (IS_QLA81XX(ha)) { 1832 led_cfg[0] = 0x4000; 1833 led_cfg[1] = 0x2000; 1834 led_cfg[2] = 0; 1835 } else { 1836 led_cfg[0] = 0x4000; 1837 led_cfg[1] = 0x2000; 1838 led_cfg[2] = 0x4000; 1839 led_cfg[3] = 0x4000; 1840 led_cfg[4] = 0; 1841 led_cfg[5] = 0x2000; 1842 } 1843 rval = qla81xx_set_led_config(vha, led_cfg); 1844 } 1845 /* On exit, restore original (presumes no status change) */ 1846 qla81xx_set_led_config(vha, orig_led_cfg); 1847 } 1848 } 1849 1850 int 1851 qla24xx_beacon_on(struct scsi_qla_host *vha) 1852 { 1853 uint32_t gpio_data; 1854 unsigned long flags; 1855 struct qla_hw_data *ha = vha->hw; 1856 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1857 1858 if (IS_P3P_TYPE(ha)) 1859 return QLA_SUCCESS; 1860 1861 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1862 goto skip_gpio; /* let blink handle it */ 1863 1864 if (ha->beacon_blink_led == 0) { 1865 /* Enable firmware for update */ 1866 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1867 1868 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) 1869 return QLA_FUNCTION_FAILED; 1870 1871 if (qla2x00_get_fw_options(vha, ha->fw_options) != 1872 QLA_SUCCESS) { 1873 ql_log(ql_log_warn, vha, 0x7009, 1874 "Unable to update fw options (beacon on).\n"); 1875 return QLA_FUNCTION_FAILED; 1876 } 1877 1878 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1879 goto skip_gpio; 1880 1881 spin_lock_irqsave(&ha->hardware_lock, flags); 1882 gpio_data = RD_REG_DWORD(®->gpiod); 1883 1884 /* Enable the gpio_data reg for update. */ 1885 gpio_data |= GPDX_LED_UPDATE_MASK; 1886 WRT_REG_DWORD(®->gpiod, gpio_data); 1887 RD_REG_DWORD(®->gpiod); 1888 1889 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1890 } 1891 1892 /* So all colors blink together. */ 1893 ha->beacon_color_state = 0; 1894 1895 skip_gpio: 1896 /* Let the per HBA timer kick off the blinking process. */ 1897 ha->beacon_blink_led = 1; 1898 1899 return QLA_SUCCESS; 1900 } 1901 1902 int 1903 qla24xx_beacon_off(struct scsi_qla_host *vha) 1904 { 1905 uint32_t gpio_data; 1906 unsigned long flags; 1907 struct qla_hw_data *ha = vha->hw; 1908 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1909 1910 if (IS_P3P_TYPE(ha)) 1911 return QLA_SUCCESS; 1912 1913 if (!ha->flags.fw_started) 1914 return QLA_SUCCESS; 1915 1916 ha->beacon_blink_led = 0; 1917 1918 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1919 goto set_fw_options; 1920 1921 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1922 return QLA_SUCCESS; 1923 1924 ha->beacon_color_state = QLA_LED_ALL_ON; 1925 1926 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ 1927 1928 /* Give control back to firmware. */ 1929 spin_lock_irqsave(&ha->hardware_lock, flags); 1930 gpio_data = RD_REG_DWORD(®->gpiod); 1931 1932 /* Disable the gpio_data reg for update. */ 1933 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1934 WRT_REG_DWORD(®->gpiod, gpio_data); 1935 RD_REG_DWORD(®->gpiod); 1936 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1937 1938 set_fw_options: 1939 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1940 1941 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1942 ql_log(ql_log_warn, vha, 0x704d, 1943 "Unable to update fw options (beacon on).\n"); 1944 return QLA_FUNCTION_FAILED; 1945 } 1946 1947 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1948 ql_log(ql_log_warn, vha, 0x704e, 1949 "Unable to update fw options (beacon on).\n"); 1950 return QLA_FUNCTION_FAILED; 1951 } 1952 1953 return QLA_SUCCESS; 1954 } 1955 1956 1957 /* 1958 * Flash support routines 1959 */ 1960 1961 /** 1962 * qla2x00_flash_enable() - Setup flash for reading and writing. 1963 * @ha: HA context 1964 */ 1965 static void 1966 qla2x00_flash_enable(struct qla_hw_data *ha) 1967 { 1968 uint16_t data; 1969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1970 1971 data = RD_REG_WORD(®->ctrl_status); 1972 data |= CSR_FLASH_ENABLE; 1973 WRT_REG_WORD(®->ctrl_status, data); 1974 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1975 } 1976 1977 /** 1978 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 1979 * @ha: HA context 1980 */ 1981 static void 1982 qla2x00_flash_disable(struct qla_hw_data *ha) 1983 { 1984 uint16_t data; 1985 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1986 1987 data = RD_REG_WORD(®->ctrl_status); 1988 data &= ~(CSR_FLASH_ENABLE); 1989 WRT_REG_WORD(®->ctrl_status, data); 1990 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 1991 } 1992 1993 /** 1994 * qla2x00_read_flash_byte() - Reads a byte from flash 1995 * @ha: HA context 1996 * @addr: Address in flash to read 1997 * 1998 * A word is read from the chip, but, only the lower byte is valid. 1999 * 2000 * Returns the byte read from flash @addr. 2001 */ 2002 static uint8_t 2003 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) 2004 { 2005 uint16_t data; 2006 uint16_t bank_select; 2007 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2008 2009 bank_select = RD_REG_WORD(®->ctrl_status); 2010 2011 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2012 /* Specify 64K address range: */ 2013 /* clear out Module Select and Flash Address bits [19:16]. */ 2014 bank_select &= ~0xf8; 2015 bank_select |= addr >> 12 & 0xf0; 2016 bank_select |= CSR_FLASH_64K_BANK; 2017 WRT_REG_WORD(®->ctrl_status, bank_select); 2018 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2019 2020 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2021 data = RD_REG_WORD(®->flash_data); 2022 2023 return (uint8_t)data; 2024 } 2025 2026 /* Setup bit 16 of flash address. */ 2027 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2028 bank_select |= CSR_FLASH_64K_BANK; 2029 WRT_REG_WORD(®->ctrl_status, bank_select); 2030 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2031 } else if (((addr & BIT_16) == 0) && 2032 (bank_select & CSR_FLASH_64K_BANK)) { 2033 bank_select &= ~(CSR_FLASH_64K_BANK); 2034 WRT_REG_WORD(®->ctrl_status, bank_select); 2035 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2036 } 2037 2038 /* Always perform IO mapped accesses to the FLASH registers. */ 2039 if (ha->pio_address) { 2040 uint16_t data2; 2041 2042 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2043 do { 2044 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2045 barrier(); 2046 cpu_relax(); 2047 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2048 } while (data != data2); 2049 } else { 2050 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2051 data = qla2x00_debounce_register(®->flash_data); 2052 } 2053 2054 return (uint8_t)data; 2055 } 2056 2057 /** 2058 * qla2x00_write_flash_byte() - Write a byte to flash 2059 * @ha: HA context 2060 * @addr: Address in flash to write 2061 * @data: Data to write 2062 */ 2063 static void 2064 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) 2065 { 2066 uint16_t bank_select; 2067 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2068 2069 bank_select = RD_REG_WORD(®->ctrl_status); 2070 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2071 /* Specify 64K address range: */ 2072 /* clear out Module Select and Flash Address bits [19:16]. */ 2073 bank_select &= ~0xf8; 2074 bank_select |= addr >> 12 & 0xf0; 2075 bank_select |= CSR_FLASH_64K_BANK; 2076 WRT_REG_WORD(®->ctrl_status, bank_select); 2077 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2078 2079 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2080 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2081 WRT_REG_WORD(®->flash_data, (uint16_t)data); 2082 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2083 2084 return; 2085 } 2086 2087 /* Setup bit 16 of flash address. */ 2088 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2089 bank_select |= CSR_FLASH_64K_BANK; 2090 WRT_REG_WORD(®->ctrl_status, bank_select); 2091 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2092 } else if (((addr & BIT_16) == 0) && 2093 (bank_select & CSR_FLASH_64K_BANK)) { 2094 bank_select &= ~(CSR_FLASH_64K_BANK); 2095 WRT_REG_WORD(®->ctrl_status, bank_select); 2096 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2097 } 2098 2099 /* Always perform IO mapped accesses to the FLASH registers. */ 2100 if (ha->pio_address) { 2101 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2102 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); 2103 } else { 2104 WRT_REG_WORD(®->flash_address, (uint16_t)addr); 2105 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2106 WRT_REG_WORD(®->flash_data, (uint16_t)data); 2107 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ 2108 } 2109 } 2110 2111 /** 2112 * qla2x00_poll_flash() - Polls flash for completion. 2113 * @ha: HA context 2114 * @addr: Address in flash to poll 2115 * @poll_data: Data to be polled 2116 * @man_id: Flash manufacturer ID 2117 * @flash_id: Flash ID 2118 * 2119 * This function polls the device until bit 7 of what is read matches data 2120 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed 2121 * out (a fatal error). The flash book recommeds reading bit 7 again after 2122 * reading bit 5 as a 1. 2123 * 2124 * Returns 0 on success, else non-zero. 2125 */ 2126 static int 2127 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, 2128 uint8_t man_id, uint8_t flash_id) 2129 { 2130 int status; 2131 uint8_t flash_data; 2132 uint32_t cnt; 2133 2134 status = 1; 2135 2136 /* Wait for 30 seconds for command to finish. */ 2137 poll_data &= BIT_7; 2138 for (cnt = 3000000; cnt; cnt--) { 2139 flash_data = qla2x00_read_flash_byte(ha, addr); 2140 if ((flash_data & BIT_7) == poll_data) { 2141 status = 0; 2142 break; 2143 } 2144 2145 if (man_id != 0x40 && man_id != 0xda) { 2146 if ((flash_data & BIT_5) && cnt > 2) 2147 cnt = 2; 2148 } 2149 udelay(10); 2150 barrier(); 2151 cond_resched(); 2152 } 2153 return status; 2154 } 2155 2156 /** 2157 * qla2x00_program_flash_address() - Programs a flash address 2158 * @ha: HA context 2159 * @addr: Address in flash to program 2160 * @data: Data to be written in flash 2161 * @man_id: Flash manufacturer ID 2162 * @flash_id: Flash ID 2163 * 2164 * Returns 0 on success, else non-zero. 2165 */ 2166 static int 2167 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, 2168 uint8_t data, uint8_t man_id, uint8_t flash_id) 2169 { 2170 /* Write Program Command Sequence. */ 2171 if (IS_OEM_001(ha)) { 2172 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2173 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2174 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 2175 qla2x00_write_flash_byte(ha, addr, data); 2176 } else { 2177 if (man_id == 0xda && flash_id == 0xc1) { 2178 qla2x00_write_flash_byte(ha, addr, data); 2179 if (addr & 0x7e) 2180 return 0; 2181 } else { 2182 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2183 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2184 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 2185 qla2x00_write_flash_byte(ha, addr, data); 2186 } 2187 } 2188 2189 udelay(150); 2190 2191 /* Wait for write to complete. */ 2192 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 2193 } 2194 2195 /** 2196 * qla2x00_erase_flash() - Erase the flash. 2197 * @ha: HA context 2198 * @man_id: Flash manufacturer ID 2199 * @flash_id: Flash ID 2200 * 2201 * Returns 0 on success, else non-zero. 2202 */ 2203 static int 2204 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id) 2205 { 2206 /* Individual Sector Erase Command Sequence */ 2207 if (IS_OEM_001(ha)) { 2208 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2209 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2210 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 2211 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2212 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2213 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 2214 } else { 2215 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2216 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2217 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2218 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2219 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2220 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 2221 } 2222 2223 udelay(150); 2224 2225 /* Wait for erase to complete. */ 2226 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 2227 } 2228 2229 /** 2230 * qla2x00_erase_flash_sector() - Erase a flash sector. 2231 * @ha: HA context 2232 * @addr: Flash sector to erase 2233 * @sec_mask: Sector address mask 2234 * @man_id: Flash manufacturer ID 2235 * @flash_id: Flash ID 2236 * 2237 * Returns 0 on success, else non-zero. 2238 */ 2239 static int 2240 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, 2241 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 2242 { 2243 /* Individual Sector Erase Command Sequence */ 2244 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2245 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2246 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2247 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2248 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2249 if (man_id == 0x1f && flash_id == 0x13) 2250 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 2251 else 2252 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 2253 2254 udelay(150); 2255 2256 /* Wait for erase to complete. */ 2257 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 2258 } 2259 2260 /** 2261 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 2262 * @ha: host adapter 2263 * @man_id: Flash manufacturer ID 2264 * @flash_id: Flash ID 2265 */ 2266 static void 2267 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 2268 uint8_t *flash_id) 2269 { 2270 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2271 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2272 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 2273 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 2274 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 2275 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2276 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2277 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 2278 } 2279 2280 static void 2281 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf, 2282 uint32_t saddr, uint32_t length) 2283 { 2284 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2285 uint32_t midpoint, ilength; 2286 uint8_t data; 2287 2288 midpoint = length / 2; 2289 2290 WRT_REG_WORD(®->nvram, 0); 2291 RD_REG_WORD(®->nvram); 2292 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 2293 if (ilength == midpoint) { 2294 WRT_REG_WORD(®->nvram, NVR_SELECT); 2295 RD_REG_WORD(®->nvram); 2296 } 2297 data = qla2x00_read_flash_byte(ha, saddr); 2298 if (saddr % 100) 2299 udelay(10); 2300 *tmp_buf = data; 2301 cond_resched(); 2302 } 2303 } 2304 2305 static inline void 2306 qla2x00_suspend_hba(struct scsi_qla_host *vha) 2307 { 2308 int cnt; 2309 unsigned long flags; 2310 struct qla_hw_data *ha = vha->hw; 2311 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2312 2313 /* Suspend HBA. */ 2314 scsi_block_requests(vha->host); 2315 ha->isp_ops->disable_intrs(ha); 2316 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2317 2318 /* Pause RISC. */ 2319 spin_lock_irqsave(&ha->hardware_lock, flags); 2320 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); 2321 RD_REG_WORD(®->hccr); 2322 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2323 for (cnt = 0; cnt < 30000; cnt++) { 2324 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) 2325 break; 2326 udelay(100); 2327 } 2328 } else { 2329 udelay(10); 2330 } 2331 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2332 } 2333 2334 static inline void 2335 qla2x00_resume_hba(struct scsi_qla_host *vha) 2336 { 2337 struct qla_hw_data *ha = vha->hw; 2338 2339 /* Resume HBA. */ 2340 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2341 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2342 qla2xxx_wake_dpc(vha); 2343 qla2x00_wait_for_chip_reset(vha); 2344 scsi_unblock_requests(vha->host); 2345 } 2346 2347 void * 2348 qla2x00_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2349 uint32_t offset, uint32_t length) 2350 { 2351 uint32_t addr, midpoint; 2352 uint8_t *data; 2353 struct qla_hw_data *ha = vha->hw; 2354 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2355 2356 /* Suspend HBA. */ 2357 qla2x00_suspend_hba(vha); 2358 2359 /* Go with read. */ 2360 midpoint = ha->optrom_size / 2; 2361 2362 qla2x00_flash_enable(ha); 2363 WRT_REG_WORD(®->nvram, 0); 2364 RD_REG_WORD(®->nvram); /* PCI Posting. */ 2365 for (addr = offset, data = buf; addr < length; addr++, data++) { 2366 if (addr == midpoint) { 2367 WRT_REG_WORD(®->nvram, NVR_SELECT); 2368 RD_REG_WORD(®->nvram); /* PCI Posting. */ 2369 } 2370 2371 *data = qla2x00_read_flash_byte(ha, addr); 2372 } 2373 qla2x00_flash_disable(ha); 2374 2375 /* Resume HBA. */ 2376 qla2x00_resume_hba(vha); 2377 2378 return buf; 2379 } 2380 2381 int 2382 qla2x00_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2383 uint32_t offset, uint32_t length) 2384 { 2385 2386 int rval; 2387 uint8_t man_id, flash_id, sec_number, *data; 2388 uint16_t wd; 2389 uint32_t addr, liter, sec_mask, rest_addr; 2390 struct qla_hw_data *ha = vha->hw; 2391 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2392 2393 /* Suspend HBA. */ 2394 qla2x00_suspend_hba(vha); 2395 2396 rval = QLA_SUCCESS; 2397 sec_number = 0; 2398 2399 /* Reset ISP chip. */ 2400 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); 2401 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2402 2403 /* Go with write. */ 2404 qla2x00_flash_enable(ha); 2405 do { /* Loop once to provide quick error exit */ 2406 /* Structure of flash memory based on manufacturer */ 2407 if (IS_OEM_001(ha)) { 2408 /* OEM variant with special flash part. */ 2409 man_id = flash_id = 0; 2410 rest_addr = 0xffff; 2411 sec_mask = 0x10000; 2412 goto update_flash; 2413 } 2414 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 2415 switch (man_id) { 2416 case 0x20: /* ST flash. */ 2417 if (flash_id == 0xd2 || flash_id == 0xe3) { 2418 /* 2419 * ST m29w008at part - 64kb sector size with 2420 * 32kb,8kb,8kb,16kb sectors at memory address 2421 * 0xf0000. 2422 */ 2423 rest_addr = 0xffff; 2424 sec_mask = 0x10000; 2425 break; 2426 } 2427 /* 2428 * ST m29w010b part - 16kb sector size 2429 * Default to 16kb sectors 2430 */ 2431 rest_addr = 0x3fff; 2432 sec_mask = 0x1c000; 2433 break; 2434 case 0x40: /* Mostel flash. */ 2435 /* Mostel v29c51001 part - 512 byte sector size. */ 2436 rest_addr = 0x1ff; 2437 sec_mask = 0x1fe00; 2438 break; 2439 case 0xbf: /* SST flash. */ 2440 /* SST39sf10 part - 4kb sector size. */ 2441 rest_addr = 0xfff; 2442 sec_mask = 0x1f000; 2443 break; 2444 case 0xda: /* Winbond flash. */ 2445 /* Winbond W29EE011 part - 256 byte sector size. */ 2446 rest_addr = 0x7f; 2447 sec_mask = 0x1ff80; 2448 break; 2449 case 0xc2: /* Macronix flash. */ 2450 /* 64k sector size. */ 2451 if (flash_id == 0x38 || flash_id == 0x4f) { 2452 rest_addr = 0xffff; 2453 sec_mask = 0x10000; 2454 break; 2455 } 2456 /* Fall through... */ 2457 2458 case 0x1f: /* Atmel flash. */ 2459 /* 512k sector size. */ 2460 if (flash_id == 0x13) { 2461 rest_addr = 0x7fffffff; 2462 sec_mask = 0x80000000; 2463 break; 2464 } 2465 /* Fall through... */ 2466 2467 case 0x01: /* AMD flash. */ 2468 if (flash_id == 0x38 || flash_id == 0x40 || 2469 flash_id == 0x4f) { 2470 /* Am29LV081 part - 64kb sector size. */ 2471 /* Am29LV002BT part - 64kb sector size. */ 2472 rest_addr = 0xffff; 2473 sec_mask = 0x10000; 2474 break; 2475 } else if (flash_id == 0x3e) { 2476 /* 2477 * Am29LV008b part - 64kb sector size with 2478 * 32kb,8kb,8kb,16kb sector at memory address 2479 * h0xf0000. 2480 */ 2481 rest_addr = 0xffff; 2482 sec_mask = 0x10000; 2483 break; 2484 } else if (flash_id == 0x20 || flash_id == 0x6e) { 2485 /* 2486 * Am29LV010 part or AM29f010 - 16kb sector 2487 * size. 2488 */ 2489 rest_addr = 0x3fff; 2490 sec_mask = 0x1c000; 2491 break; 2492 } else if (flash_id == 0x6d) { 2493 /* Am29LV001 part - 8kb sector size. */ 2494 rest_addr = 0x1fff; 2495 sec_mask = 0x1e000; 2496 break; 2497 } 2498 /* fall through */ 2499 default: 2500 /* Default to 16 kb sector size. */ 2501 rest_addr = 0x3fff; 2502 sec_mask = 0x1c000; 2503 break; 2504 } 2505 2506 update_flash: 2507 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2508 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 2509 rval = QLA_FUNCTION_FAILED; 2510 break; 2511 } 2512 } 2513 2514 for (addr = offset, liter = 0; liter < length; liter++, 2515 addr++) { 2516 data = buf + liter; 2517 /* Are we at the beginning of a sector? */ 2518 if ((addr & rest_addr) == 0) { 2519 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2520 if (addr >= 0x10000UL) { 2521 if (((addr >> 12) & 0xf0) && 2522 ((man_id == 0x01 && 2523 flash_id == 0x3e) || 2524 (man_id == 0x20 && 2525 flash_id == 0xd2))) { 2526 sec_number++; 2527 if (sec_number == 1) { 2528 rest_addr = 2529 0x7fff; 2530 sec_mask = 2531 0x18000; 2532 } else if ( 2533 sec_number == 2 || 2534 sec_number == 3) { 2535 rest_addr = 2536 0x1fff; 2537 sec_mask = 2538 0x1e000; 2539 } else if ( 2540 sec_number == 4) { 2541 rest_addr = 2542 0x3fff; 2543 sec_mask = 2544 0x1c000; 2545 } 2546 } 2547 } 2548 } else if (addr == ha->optrom_size / 2) { 2549 WRT_REG_WORD(®->nvram, NVR_SELECT); 2550 RD_REG_WORD(®->nvram); 2551 } 2552 2553 if (flash_id == 0xda && man_id == 0xc1) { 2554 qla2x00_write_flash_byte(ha, 0x5555, 2555 0xaa); 2556 qla2x00_write_flash_byte(ha, 0x2aaa, 2557 0x55); 2558 qla2x00_write_flash_byte(ha, 0x5555, 2559 0xa0); 2560 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 2561 /* Then erase it */ 2562 if (qla2x00_erase_flash_sector(ha, 2563 addr, sec_mask, man_id, 2564 flash_id)) { 2565 rval = QLA_FUNCTION_FAILED; 2566 break; 2567 } 2568 if (man_id == 0x01 && flash_id == 0x6d) 2569 sec_number++; 2570 } 2571 } 2572 2573 if (man_id == 0x01 && flash_id == 0x6d) { 2574 if (sec_number == 1 && 2575 addr == (rest_addr - 1)) { 2576 rest_addr = 0x0fff; 2577 sec_mask = 0x1f000; 2578 } else if (sec_number == 3 && (addr & 0x7ffe)) { 2579 rest_addr = 0x3fff; 2580 sec_mask = 0x1c000; 2581 } 2582 } 2583 2584 if (qla2x00_program_flash_address(ha, addr, *data, 2585 man_id, flash_id)) { 2586 rval = QLA_FUNCTION_FAILED; 2587 break; 2588 } 2589 cond_resched(); 2590 } 2591 } while (0); 2592 qla2x00_flash_disable(ha); 2593 2594 /* Resume HBA. */ 2595 qla2x00_resume_hba(vha); 2596 2597 return rval; 2598 } 2599 2600 void * 2601 qla24xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2602 uint32_t offset, uint32_t length) 2603 { 2604 struct qla_hw_data *ha = vha->hw; 2605 2606 /* Suspend HBA. */ 2607 scsi_block_requests(vha->host); 2608 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2609 2610 /* Go with read. */ 2611 qla24xx_read_flash_data(vha, (void *)buf, offset >> 2, length >> 2); 2612 2613 /* Resume HBA. */ 2614 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2615 scsi_unblock_requests(vha->host); 2616 2617 return buf; 2618 } 2619 2620 static int 2621 qla28xx_extract_sfub_and_verify(struct scsi_qla_host *vha, uint32_t *buf, 2622 uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf) 2623 { 2624 uint32_t *p, check_sum = 0; 2625 int i; 2626 2627 p = buf + buf_size_without_sfub; 2628 2629 /* Extract SFUB from end of file */ 2630 memcpy(sfub_buf, (uint8_t *)p, 2631 sizeof(struct secure_flash_update_block)); 2632 2633 for (i = 0; i < (sizeof(struct secure_flash_update_block) >> 2); i++) 2634 check_sum += p[i]; 2635 2636 check_sum = (~check_sum) + 1; 2637 2638 if (check_sum != p[i]) { 2639 ql_log(ql_log_warn, vha, 0x7097, 2640 "SFUB checksum failed, 0x%x, 0x%x\n", 2641 check_sum, p[i]); 2642 return QLA_COMMAND_ERROR; 2643 } 2644 2645 return QLA_SUCCESS; 2646 } 2647 2648 static int 2649 qla28xx_get_flash_region(struct scsi_qla_host *vha, uint32_t start, 2650 struct qla_flt_region *region) 2651 { 2652 struct qla_hw_data *ha = vha->hw; 2653 struct qla_flt_header *flt; 2654 struct qla_flt_region *flt_reg; 2655 uint16_t cnt; 2656 int rval = QLA_FUNCTION_FAILED; 2657 2658 if (!ha->flt) 2659 return QLA_FUNCTION_FAILED; 2660 2661 flt = (struct qla_flt_header *)ha->flt; 2662 flt_reg = (struct qla_flt_region *)&flt[1]; 2663 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 2664 2665 for (; cnt; cnt--, flt_reg++) { 2666 if (flt_reg->start == start) { 2667 memcpy((uint8_t *)region, flt_reg, 2668 sizeof(struct qla_flt_region)); 2669 rval = QLA_SUCCESS; 2670 break; 2671 } 2672 } 2673 2674 return rval; 2675 } 2676 2677 static int 2678 qla28xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2679 uint32_t dwords) 2680 { 2681 struct qla_hw_data *ha = vha->hw; 2682 ulong liter; 2683 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 2684 uint32_t sec_mask, rest_addr, fdata; 2685 void *optrom = NULL; 2686 dma_addr_t optrom_dma; 2687 int rval; 2688 struct secure_flash_update_block *sfub; 2689 dma_addr_t sfub_dma; 2690 uint32_t offset = faddr << 2; 2691 uint32_t buf_size_without_sfub = 0; 2692 struct qla_flt_region region; 2693 bool reset_to_rom = false; 2694 uint32_t risc_size, risc_attr = 0; 2695 uint32_t *fw_array = NULL; 2696 2697 /* Retrieve region info - must be a start address passed in */ 2698 rval = qla28xx_get_flash_region(vha, offset, ®ion); 2699 2700 if (rval != QLA_SUCCESS) { 2701 ql_log(ql_log_warn, vha, 0xffff, 2702 "Invalid address %x - not a region start address\n", 2703 offset); 2704 goto done; 2705 } 2706 2707 /* Allocate dma buffer for burst write */ 2708 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2709 &optrom_dma, GFP_KERNEL); 2710 if (!optrom) { 2711 ql_log(ql_log_warn, vha, 0x7095, 2712 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 2713 rval = QLA_COMMAND_ERROR; 2714 goto done; 2715 } 2716 2717 /* 2718 * If adapter supports secure flash and region is secure 2719 * extract secure flash update block (SFUB) and verify 2720 */ 2721 if (ha->flags.secure_adapter && region.attribute) { 2722 2723 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2724 "Region %x is secure\n", region.code); 2725 2726 if (region.code == FLT_REG_FW || 2727 region.code == FLT_REG_FW_SEC_27XX) { 2728 fw_array = dwptr; 2729 2730 /* 1st fw array */ 2731 risc_size = be32_to_cpu(fw_array[3]); 2732 risc_attr = be32_to_cpu(fw_array[9]); 2733 2734 buf_size_without_sfub = risc_size; 2735 fw_array += risc_size; 2736 2737 /* 2nd fw array */ 2738 risc_size = be32_to_cpu(fw_array[3]); 2739 2740 buf_size_without_sfub += risc_size; 2741 fw_array += risc_size; 2742 2743 /* 1st dump template */ 2744 risc_size = be32_to_cpu(fw_array[2]); 2745 2746 /* skip header and ignore checksum */ 2747 buf_size_without_sfub += risc_size; 2748 fw_array += risc_size; 2749 2750 if (risc_attr & BIT_9) { 2751 /* 2nd dump template */ 2752 risc_size = be32_to_cpu(fw_array[2]); 2753 2754 /* skip header and ignore checksum */ 2755 buf_size_without_sfub += risc_size; 2756 fw_array += risc_size; 2757 } 2758 } else { 2759 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2760 "Secure region %x not supported\n", 2761 region.code); 2762 rval = QLA_COMMAND_ERROR; 2763 goto done; 2764 } 2765 2766 sfub = dma_alloc_coherent(&ha->pdev->dev, 2767 sizeof(struct secure_flash_update_block), &sfub_dma, 2768 GFP_KERNEL); 2769 if (!sfub) { 2770 ql_log(ql_log_warn, vha, 0xffff, 2771 "Unable to allocate memory for SFUB\n"); 2772 rval = QLA_COMMAND_ERROR; 2773 goto done; 2774 } 2775 2776 rval = qla28xx_extract_sfub_and_verify(vha, dwptr, dwords, 2777 buf_size_without_sfub, (uint8_t *)sfub); 2778 2779 if (rval != QLA_SUCCESS) 2780 goto done; 2781 2782 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2783 "SFUB extract and verify successful\n"); 2784 } 2785 2786 rest_addr = (ha->fdt_block_size >> 2) - 1; 2787 sec_mask = ~rest_addr; 2788 2789 /* Lock semaphore */ 2790 rval = qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_LOCK); 2791 if (rval != QLA_SUCCESS) { 2792 ql_log(ql_log_warn, vha, 0xffff, 2793 "Unable to lock flash semaphore."); 2794 goto done; 2795 } 2796 2797 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2798 "Unprotect flash...\n"); 2799 rval = qla24xx_unprotect_flash(vha); 2800 if (rval) { 2801 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2802 ql_log(ql_log_warn, vha, 0x7096, "Failed unprotect flash\n"); 2803 goto done; 2804 } 2805 2806 for (liter = 0; liter < dwords; liter++, faddr++) { 2807 fdata = (faddr & sec_mask) << 2; 2808 2809 /* If start of sector */ 2810 if (!(faddr & rest_addr)) { 2811 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2812 "Erase sector %#x...\n", faddr); 2813 rval = qla24xx_erase_sector(vha, fdata); 2814 if (rval) { 2815 ql_dbg(ql_dbg_user, vha, 0x7007, 2816 "Failed erase sector %#x\n", faddr); 2817 goto write_protect; 2818 } 2819 } 2820 } 2821 2822 if (ha->flags.secure_adapter) { 2823 /* 2824 * If adapter supports secure flash but FW doesn't, 2825 * disable write protect, release semaphore and reset 2826 * chip to execute ROM code in order to update region securely 2827 */ 2828 if (!ha->flags.secure_fw) { 2829 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2830 "Disable Write and Release Semaphore."); 2831 rval = qla24xx_protect_flash(vha); 2832 if (rval != QLA_SUCCESS) { 2833 qla81xx_fac_semaphore_access(vha, 2834 FAC_SEMAPHORE_UNLOCK); 2835 ql_log(ql_log_warn, vha, 0xffff, 2836 "Unable to protect flash."); 2837 goto done; 2838 } 2839 2840 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2841 "Reset chip to ROM."); 2842 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2843 set_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags); 2844 qla2xxx_wake_dpc(vha); 2845 rval = qla2x00_wait_for_chip_reset(vha); 2846 if (rval != QLA_SUCCESS) { 2847 ql_log(ql_log_warn, vha, 0xffff, 2848 "Unable to reset to ROM code."); 2849 goto done; 2850 } 2851 reset_to_rom = true; 2852 ha->flags.fac_supported = 0; 2853 2854 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2855 "Lock Semaphore"); 2856 rval = qla2xxx_write_remote_register(vha, 2857 FLASH_SEMAPHORE_REGISTER_ADDR, 0x00020002); 2858 if (rval != QLA_SUCCESS) { 2859 ql_log(ql_log_warn, vha, 0xffff, 2860 "Unable to lock flash semaphore."); 2861 goto done; 2862 } 2863 2864 /* Unprotect flash */ 2865 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2866 "Enable Write."); 2867 rval = qla2x00_write_ram_word(vha, 0x7ffd0101, 0); 2868 if (rval) { 2869 ql_log(ql_log_warn, vha, 0x7096, 2870 "Failed unprotect flash\n"); 2871 goto done; 2872 } 2873 } 2874 2875 /* If region is secure, send Secure Flash MB Cmd */ 2876 if (region.attribute && buf_size_without_sfub) { 2877 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2878 "Sending Secure Flash MB Cmd\n"); 2879 rval = qla28xx_secure_flash_update(vha, 0, region.code, 2880 buf_size_without_sfub, sfub_dma, 2881 sizeof(struct secure_flash_update_block)); 2882 if (rval != QLA_SUCCESS) { 2883 ql_log(ql_log_warn, vha, 0xffff, 2884 "Secure Flash MB Cmd failed %x.", rval); 2885 goto write_protect; 2886 } 2887 } 2888 2889 } 2890 2891 /* re-init flash offset */ 2892 faddr = offset >> 2; 2893 2894 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 2895 fdata = (faddr & sec_mask) << 2; 2896 2897 /* If smaller than a burst remaining */ 2898 if (dwords - liter < dburst) 2899 dburst = dwords - liter; 2900 2901 /* Copy to dma buffer */ 2902 memcpy(optrom, dwptr, dburst << 2); 2903 2904 /* Burst write */ 2905 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2906 "Write burst (%#lx dwords)...\n", dburst); 2907 rval = qla2x00_load_ram(vha, optrom_dma, 2908 flash_data_addr(ha, faddr), dburst); 2909 if (rval != QLA_SUCCESS) { 2910 ql_log(ql_log_warn, vha, 0x7097, 2911 "Failed burst write at %x (%p/%#llx)...\n", 2912 flash_data_addr(ha, faddr), optrom, 2913 (u64)optrom_dma); 2914 break; 2915 } 2916 2917 liter += dburst - 1; 2918 faddr += dburst - 1; 2919 dwptr += dburst - 1; 2920 continue; 2921 } 2922 2923 write_protect: 2924 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2925 "Protect flash...\n"); 2926 rval = qla24xx_protect_flash(vha); 2927 if (rval) { 2928 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2929 ql_log(ql_log_warn, vha, 0x7099, 2930 "Failed protect flash\n"); 2931 } 2932 2933 if (reset_to_rom == true) { 2934 /* Schedule DPC to restart the RISC */ 2935 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2936 qla2xxx_wake_dpc(vha); 2937 2938 rval = qla2x00_wait_for_hba_online(vha); 2939 if (rval != QLA_SUCCESS) 2940 ql_log(ql_log_warn, vha, 0xffff, 2941 "Adapter did not come out of reset\n"); 2942 } 2943 2944 done: 2945 if (optrom) 2946 dma_free_coherent(&ha->pdev->dev, 2947 OPTROM_BURST_SIZE, optrom, optrom_dma); 2948 2949 return rval; 2950 } 2951 2952 int 2953 qla24xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2954 uint32_t offset, uint32_t length) 2955 { 2956 int rval; 2957 struct qla_hw_data *ha = vha->hw; 2958 2959 /* Suspend HBA. */ 2960 scsi_block_requests(vha->host); 2961 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2962 2963 /* Go with write. */ 2964 if (IS_QLA28XX(ha)) 2965 rval = qla28xx_write_flash_data(vha, (uint32_t *)buf, 2966 offset >> 2, length >> 2); 2967 else 2968 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, 2969 offset >> 2, length >> 2); 2970 2971 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2972 scsi_unblock_requests(vha->host); 2973 2974 return rval; 2975 } 2976 2977 void * 2978 qla25xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2979 uint32_t offset, uint32_t length) 2980 { 2981 int rval; 2982 dma_addr_t optrom_dma; 2983 void *optrom; 2984 uint8_t *pbuf; 2985 uint32_t faddr, left, burst; 2986 struct qla_hw_data *ha = vha->hw; 2987 2988 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 2989 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2990 goto try_fast; 2991 if (offset & 0xfff) 2992 goto slow_read; 2993 if (length < OPTROM_BURST_SIZE) 2994 goto slow_read; 2995 2996 try_fast: 2997 if (offset & 0xff) 2998 goto slow_read; 2999 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3000 &optrom_dma, GFP_KERNEL); 3001 if (!optrom) { 3002 ql_log(ql_log_warn, vha, 0x00cc, 3003 "Unable to allocate memory for optrom burst read (%x KB).\n", 3004 OPTROM_BURST_SIZE / 1024); 3005 goto slow_read; 3006 } 3007 3008 pbuf = buf; 3009 faddr = offset >> 2; 3010 left = length >> 2; 3011 burst = OPTROM_BURST_DWORDS; 3012 while (left != 0) { 3013 if (burst > left) 3014 burst = left; 3015 3016 rval = qla2x00_dump_ram(vha, optrom_dma, 3017 flash_data_addr(ha, faddr), burst); 3018 if (rval) { 3019 ql_log(ql_log_warn, vha, 0x00f5, 3020 "Unable to burst-read optrom segment (%x/%x/%llx).\n", 3021 rval, flash_data_addr(ha, faddr), 3022 (unsigned long long)optrom_dma); 3023 ql_log(ql_log_warn, vha, 0x00f6, 3024 "Reverting to slow-read.\n"); 3025 3026 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3027 optrom, optrom_dma); 3028 goto slow_read; 3029 } 3030 3031 memcpy(pbuf, optrom, burst * 4); 3032 3033 left -= burst; 3034 faddr += burst; 3035 pbuf += burst * 4; 3036 } 3037 3038 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, 3039 optrom_dma); 3040 3041 return buf; 3042 3043 slow_read: 3044 return qla24xx_read_optrom_data(vha, buf, offset, length); 3045 } 3046 3047 /** 3048 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 3049 * @ha: HA context 3050 * @pcids: Pointer to the FCODE PCI data structure 3051 * 3052 * The process of retrieving the FCODE version information is at best 3053 * described as interesting. 3054 * 3055 * Within the first 100h bytes of the image an ASCII string is present 3056 * which contains several pieces of information including the FCODE 3057 * version. Unfortunately it seems the only reliable way to retrieve 3058 * the version is by scanning for another sentinel within the string, 3059 * the FCODE build date: 3060 * 3061 * ... 2.00.02 10/17/02 ... 3062 * 3063 * Returns QLA_SUCCESS on successful retrieval of version. 3064 */ 3065 static void 3066 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) 3067 { 3068 int ret = QLA_FUNCTION_FAILED; 3069 uint32_t istart, iend, iter, vend; 3070 uint8_t do_next, rbyte, *vbyte; 3071 3072 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3073 3074 /* Skip the PCI data structure. */ 3075 istart = pcids + 3076 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 3077 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 3078 iend = istart + 0x100; 3079 do { 3080 /* Scan for the sentinel date string...eeewww. */ 3081 do_next = 0; 3082 iter = istart; 3083 while ((iter < iend) && !do_next) { 3084 iter++; 3085 if (qla2x00_read_flash_byte(ha, iter) == '/') { 3086 if (qla2x00_read_flash_byte(ha, iter + 2) == 3087 '/') 3088 do_next++; 3089 else if (qla2x00_read_flash_byte(ha, 3090 iter + 3) == '/') 3091 do_next++; 3092 } 3093 } 3094 if (!do_next) 3095 break; 3096 3097 /* Backtrack to previous ' ' (space). */ 3098 do_next = 0; 3099 while ((iter > istart) && !do_next) { 3100 iter--; 3101 if (qla2x00_read_flash_byte(ha, iter) == ' ') 3102 do_next++; 3103 } 3104 if (!do_next) 3105 break; 3106 3107 /* 3108 * Mark end of version tag, and find previous ' ' (space) or 3109 * string length (recent FCODE images -- major hack ahead!!!). 3110 */ 3111 vend = iter - 1; 3112 do_next = 0; 3113 while ((iter > istart) && !do_next) { 3114 iter--; 3115 rbyte = qla2x00_read_flash_byte(ha, iter); 3116 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 3117 do_next++; 3118 } 3119 if (!do_next) 3120 break; 3121 3122 /* Mark beginning of version tag, and copy data. */ 3123 iter++; 3124 if ((vend - iter) && 3125 ((vend - iter) < sizeof(ha->fcode_revision))) { 3126 vbyte = ha->fcode_revision; 3127 while (iter <= vend) { 3128 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 3129 iter++; 3130 } 3131 ret = QLA_SUCCESS; 3132 } 3133 } while (0); 3134 3135 if (ret != QLA_SUCCESS) 3136 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3137 } 3138 3139 int 3140 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3141 { 3142 int ret = QLA_SUCCESS; 3143 uint8_t code_type, last_image; 3144 uint32_t pcihdr, pcids; 3145 uint8_t *dbyte; 3146 uint16_t *dcode; 3147 struct qla_hw_data *ha = vha->hw; 3148 3149 if (!ha->pio_address || !mbuf) 3150 return QLA_FUNCTION_FAILED; 3151 3152 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3153 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3154 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3155 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3156 3157 qla2x00_flash_enable(ha); 3158 3159 /* Begin with first PCI expansion ROM header. */ 3160 pcihdr = 0; 3161 last_image = 1; 3162 do { 3163 /* Verify PCI expansion ROM header. */ 3164 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 3165 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 3166 /* No signature */ 3167 ql_log(ql_log_fatal, vha, 0x0050, 3168 "No matching ROM signature.\n"); 3169 ret = QLA_FUNCTION_FAILED; 3170 break; 3171 } 3172 3173 /* Locate PCI data structure. */ 3174 pcids = pcihdr + 3175 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 3176 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 3177 3178 /* Validate signature of PCI data structure. */ 3179 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 3180 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 3181 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 3182 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 3183 /* Incorrect header. */ 3184 ql_log(ql_log_fatal, vha, 0x0051, 3185 "PCI data struct not found pcir_adr=%x.\n", pcids); 3186 ret = QLA_FUNCTION_FAILED; 3187 break; 3188 } 3189 3190 /* Read version */ 3191 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 3192 switch (code_type) { 3193 case ROM_CODE_TYPE_BIOS: 3194 /* Intel x86, PC-AT compatible. */ 3195 ha->bios_revision[0] = 3196 qla2x00_read_flash_byte(ha, pcids + 0x12); 3197 ha->bios_revision[1] = 3198 qla2x00_read_flash_byte(ha, pcids + 0x13); 3199 ql_dbg(ql_dbg_init, vha, 0x0052, 3200 "Read BIOS %d.%d.\n", 3201 ha->bios_revision[1], ha->bios_revision[0]); 3202 break; 3203 case ROM_CODE_TYPE_FCODE: 3204 /* Open Firmware standard for PCI (FCode). */ 3205 /* Eeeewww... */ 3206 qla2x00_get_fcode_version(ha, pcids); 3207 break; 3208 case ROM_CODE_TYPE_EFI: 3209 /* Extensible Firmware Interface (EFI). */ 3210 ha->efi_revision[0] = 3211 qla2x00_read_flash_byte(ha, pcids + 0x12); 3212 ha->efi_revision[1] = 3213 qla2x00_read_flash_byte(ha, pcids + 0x13); 3214 ql_dbg(ql_dbg_init, vha, 0x0053, 3215 "Read EFI %d.%d.\n", 3216 ha->efi_revision[1], ha->efi_revision[0]); 3217 break; 3218 default: 3219 ql_log(ql_log_warn, vha, 0x0054, 3220 "Unrecognized code type %x at pcids %x.\n", 3221 code_type, pcids); 3222 break; 3223 } 3224 3225 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 3226 3227 /* Locate next PCI expansion ROM. */ 3228 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 3229 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 3230 } while (!last_image); 3231 3232 if (IS_QLA2322(ha)) { 3233 /* Read firmware image information. */ 3234 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3235 dbyte = mbuf; 3236 memset(dbyte, 0, 8); 3237 dcode = (uint16_t *)dbyte; 3238 3239 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, 3240 8); 3241 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a, 3242 "Dumping fw " 3243 "ver from flash:.\n"); 3244 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b, 3245 dbyte, 32); 3246 3247 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 3248 dcode[2] == 0xffff && dcode[3] == 0xffff) || 3249 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 3250 dcode[3] == 0)) { 3251 ql_log(ql_log_warn, vha, 0x0057, 3252 "Unrecognized fw revision at %x.\n", 3253 ha->flt_region_fw * 4); 3254 } else { 3255 /* values are in big endian */ 3256 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 3257 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 3258 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 3259 ql_dbg(ql_dbg_init, vha, 0x0058, 3260 "FW Version: " 3261 "%d.%d.%d.\n", ha->fw_revision[0], 3262 ha->fw_revision[1], ha->fw_revision[2]); 3263 } 3264 } 3265 3266 qla2x00_flash_disable(ha); 3267 3268 return ret; 3269 } 3270 3271 int 3272 qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3273 { 3274 int ret = QLA_SUCCESS; 3275 uint32_t pcihdr, pcids; 3276 uint32_t *dcode = mbuf; 3277 uint8_t *bcode = mbuf; 3278 uint8_t code_type, last_image; 3279 struct qla_hw_data *ha = vha->hw; 3280 3281 if (!mbuf) 3282 return QLA_FUNCTION_FAILED; 3283 3284 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3285 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3286 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3287 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3288 3289 /* Begin with first PCI expansion ROM header. */ 3290 pcihdr = ha->flt_region_boot << 2; 3291 last_image = 1; 3292 do { 3293 /* Verify PCI expansion ROM header. */ 3294 ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4); 3295 bcode = mbuf + (pcihdr % 4); 3296 if (memcmp(bcode, "\x55\xaa", 2)) { 3297 /* No signature */ 3298 ql_log(ql_log_fatal, vha, 0x0154, 3299 "No matching ROM signature.\n"); 3300 ret = QLA_FUNCTION_FAILED; 3301 break; 3302 } 3303 3304 /* Locate PCI data structure. */ 3305 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3306 3307 ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4); 3308 bcode = mbuf + (pcihdr % 4); 3309 3310 /* Validate signature of PCI data structure. */ 3311 if (memcmp(bcode, "PCIR", 4)) { 3312 /* Incorrect header. */ 3313 ql_log(ql_log_fatal, vha, 0x0155, 3314 "PCI data struct not found pcir_adr=%x.\n", pcids); 3315 ret = QLA_FUNCTION_FAILED; 3316 break; 3317 } 3318 3319 /* Read version */ 3320 code_type = bcode[0x14]; 3321 switch (code_type) { 3322 case ROM_CODE_TYPE_BIOS: 3323 /* Intel x86, PC-AT compatible. */ 3324 ha->bios_revision[0] = bcode[0x12]; 3325 ha->bios_revision[1] = bcode[0x13]; 3326 ql_dbg(ql_dbg_init, vha, 0x0156, 3327 "Read BIOS %d.%d.\n", 3328 ha->bios_revision[1], ha->bios_revision[0]); 3329 break; 3330 case ROM_CODE_TYPE_FCODE: 3331 /* Open Firmware standard for PCI (FCode). */ 3332 ha->fcode_revision[0] = bcode[0x12]; 3333 ha->fcode_revision[1] = bcode[0x13]; 3334 ql_dbg(ql_dbg_init, vha, 0x0157, 3335 "Read FCODE %d.%d.\n", 3336 ha->fcode_revision[1], ha->fcode_revision[0]); 3337 break; 3338 case ROM_CODE_TYPE_EFI: 3339 /* Extensible Firmware Interface (EFI). */ 3340 ha->efi_revision[0] = bcode[0x12]; 3341 ha->efi_revision[1] = bcode[0x13]; 3342 ql_dbg(ql_dbg_init, vha, 0x0158, 3343 "Read EFI %d.%d.\n", 3344 ha->efi_revision[1], ha->efi_revision[0]); 3345 break; 3346 default: 3347 ql_log(ql_log_warn, vha, 0x0159, 3348 "Unrecognized code type %x at pcids %x.\n", 3349 code_type, pcids); 3350 break; 3351 } 3352 3353 last_image = bcode[0x15] & BIT_7; 3354 3355 /* Locate next PCI expansion ROM. */ 3356 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3357 } while (!last_image); 3358 3359 /* Read firmware image information. */ 3360 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3361 dcode = mbuf; 3362 ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20); 3363 bcode = mbuf + (pcihdr % 4); 3364 3365 /* Validate signature of PCI data structure. */ 3366 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 && 3367 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) { 3368 ha->fw_revision[0] = bcode[0x4]; 3369 ha->fw_revision[1] = bcode[0x5]; 3370 ha->fw_revision[2] = bcode[0x6]; 3371 ql_dbg(ql_dbg_init, vha, 0x0153, 3372 "Firmware revision %d.%d.%d\n", 3373 ha->fw_revision[0], ha->fw_revision[1], 3374 ha->fw_revision[2]); 3375 } 3376 3377 return ret; 3378 } 3379 3380 int 3381 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3382 { 3383 int ret = QLA_SUCCESS; 3384 uint32_t pcihdr = 0, pcids = 0; 3385 uint32_t *dcode = mbuf; 3386 uint8_t *bcode = mbuf; 3387 uint8_t code_type, last_image; 3388 int i; 3389 struct qla_hw_data *ha = vha->hw; 3390 uint32_t faddr = 0; 3391 struct active_regions active_regions = { }; 3392 3393 if (IS_P3P_TYPE(ha)) 3394 return ret; 3395 3396 if (!mbuf) 3397 return QLA_FUNCTION_FAILED; 3398 3399 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3400 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3401 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3402 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3403 3404 pcihdr = ha->flt_region_boot << 2; 3405 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3406 qla27xx_get_active_image(vha, &active_regions); 3407 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) { 3408 pcihdr = ha->flt_region_boot_sec << 2; 3409 } 3410 } 3411 3412 do { 3413 /* Verify PCI expansion ROM header. */ 3414 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 3415 bcode = mbuf + (pcihdr % 4); 3416 if (memcmp(bcode, "\x55\xaa", 2)) { 3417 /* No signature */ 3418 ql_log(ql_log_fatal, vha, 0x0059, 3419 "No matching ROM signature.\n"); 3420 ret = QLA_FUNCTION_FAILED; 3421 break; 3422 } 3423 3424 /* Locate PCI data structure. */ 3425 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3426 3427 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 3428 bcode = mbuf + (pcihdr % 4); 3429 3430 /* Validate signature of PCI data structure. */ 3431 if (memcmp(bcode, "PCIR", 4)) { 3432 /* Incorrect header. */ 3433 ql_log(ql_log_fatal, vha, 0x005a, 3434 "PCI data struct not found pcir_adr=%x.\n", pcids); 3435 ql_dump_buffer(ql_dbg_init, vha, 0x0059, dcode, 32); 3436 ret = QLA_FUNCTION_FAILED; 3437 break; 3438 } 3439 3440 /* Read version */ 3441 code_type = bcode[0x14]; 3442 switch (code_type) { 3443 case ROM_CODE_TYPE_BIOS: 3444 /* Intel x86, PC-AT compatible. */ 3445 ha->bios_revision[0] = bcode[0x12]; 3446 ha->bios_revision[1] = bcode[0x13]; 3447 ql_dbg(ql_dbg_init, vha, 0x005b, 3448 "Read BIOS %d.%d.\n", 3449 ha->bios_revision[1], ha->bios_revision[0]); 3450 break; 3451 case ROM_CODE_TYPE_FCODE: 3452 /* Open Firmware standard for PCI (FCode). */ 3453 ha->fcode_revision[0] = bcode[0x12]; 3454 ha->fcode_revision[1] = bcode[0x13]; 3455 ql_dbg(ql_dbg_init, vha, 0x005c, 3456 "Read FCODE %d.%d.\n", 3457 ha->fcode_revision[1], ha->fcode_revision[0]); 3458 break; 3459 case ROM_CODE_TYPE_EFI: 3460 /* Extensible Firmware Interface (EFI). */ 3461 ha->efi_revision[0] = bcode[0x12]; 3462 ha->efi_revision[1] = bcode[0x13]; 3463 ql_dbg(ql_dbg_init, vha, 0x005d, 3464 "Read EFI %d.%d.\n", 3465 ha->efi_revision[1], ha->efi_revision[0]); 3466 break; 3467 default: 3468 ql_log(ql_log_warn, vha, 0x005e, 3469 "Unrecognized code type %x at pcids %x.\n", 3470 code_type, pcids); 3471 break; 3472 } 3473 3474 last_image = bcode[0x15] & BIT_7; 3475 3476 /* Locate next PCI expansion ROM. */ 3477 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3478 } while (!last_image); 3479 3480 /* Read firmware image information. */ 3481 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3482 faddr = ha->flt_region_fw; 3483 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3484 qla27xx_get_active_image(vha, &active_regions); 3485 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) 3486 faddr = ha->flt_region_fw_sec; 3487 } 3488 3489 qla24xx_read_flash_data(vha, dcode, faddr, 8); 3490 if (qla24xx_risc_firmware_invalid(dcode)) { 3491 ql_log(ql_log_warn, vha, 0x005f, 3492 "Unrecognized fw revision at %x.\n", 3493 ha->flt_region_fw * 4); 3494 ql_dump_buffer(ql_dbg_init, vha, 0x005f, dcode, 32); 3495 } else { 3496 for (i = 0; i < 4; i++) 3497 ha->fw_revision[i] = be32_to_cpu(dcode[4+i]); 3498 ql_dbg(ql_dbg_init, vha, 0x0060, 3499 "Firmware revision (flash) %u.%u.%u (%x).\n", 3500 ha->fw_revision[0], ha->fw_revision[1], 3501 ha->fw_revision[2], ha->fw_revision[3]); 3502 } 3503 3504 /* Check for golden firmware and get version if available */ 3505 if (!IS_QLA81XX(ha)) { 3506 /* Golden firmware is not present in non 81XX adapters */ 3507 return ret; 3508 } 3509 3510 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); 3511 faddr = ha->flt_region_gold_fw; 3512 qla24xx_read_flash_data(vha, (void *)dcode, ha->flt_region_gold_fw, 8); 3513 if (qla24xx_risc_firmware_invalid(dcode)) { 3514 ql_log(ql_log_warn, vha, 0x0056, 3515 "Unrecognized golden fw at %#x.\n", faddr); 3516 ql_dump_buffer(ql_dbg_init, vha, 0x0056, dcode, 32); 3517 return ret; 3518 } 3519 3520 for (i = 0; i < 4; i++) 3521 ha->gold_fw_version[i] = be32_to_cpu(dcode[4+i]); 3522 3523 return ret; 3524 } 3525 3526 static int 3527 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) 3528 { 3529 if (pos >= end || *pos != 0x82) 3530 return 0; 3531 3532 pos += 3 + pos[1]; 3533 if (pos >= end || *pos != 0x90) 3534 return 0; 3535 3536 pos += 3 + pos[1]; 3537 if (pos >= end || *pos != 0x78) 3538 return 0; 3539 3540 return 1; 3541 } 3542 3543 int 3544 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) 3545 { 3546 struct qla_hw_data *ha = vha->hw; 3547 uint8_t *pos = ha->vpd; 3548 uint8_t *end = pos + ha->vpd_size; 3549 int len = 0; 3550 3551 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) 3552 return 0; 3553 3554 while (pos < end && *pos != 0x78) { 3555 len = (*pos == 0x82) ? pos[1] : pos[2]; 3556 3557 if (!strncmp(pos, key, strlen(key))) 3558 break; 3559 3560 if (*pos != 0x90 && *pos != 0x91) 3561 pos += len; 3562 3563 pos += 3; 3564 } 3565 3566 if (pos < end - len && *pos != 0x78) 3567 return scnprintf(str, size, "%.*s", len, pos + 3); 3568 3569 return 0; 3570 } 3571 3572 int 3573 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha) 3574 { 3575 int len, max_len; 3576 uint32_t fcp_prio_addr; 3577 struct qla_hw_data *ha = vha->hw; 3578 3579 if (!ha->fcp_prio_cfg) { 3580 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); 3581 if (!ha->fcp_prio_cfg) { 3582 ql_log(ql_log_warn, vha, 0x00d5, 3583 "Unable to allocate memory for fcp priority data (%x).\n", 3584 FCP_PRIO_CFG_SIZE); 3585 return QLA_FUNCTION_FAILED; 3586 } 3587 } 3588 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); 3589 3590 fcp_prio_addr = ha->flt_region_fcp_prio; 3591 3592 /* first read the fcp priority data header from flash */ 3593 ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg, 3594 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE); 3595 3596 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0)) 3597 goto fail; 3598 3599 /* read remaining FCP CMD config data from flash */ 3600 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2); 3601 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE; 3602 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; 3603 3604 ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0], 3605 fcp_prio_addr << 2, (len < max_len ? len : max_len)); 3606 3607 /* revalidate the entire FCP priority config data, including entries */ 3608 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1)) 3609 goto fail; 3610 3611 ha->flags.fcp_prio_enabled = 1; 3612 return QLA_SUCCESS; 3613 fail: 3614 vfree(ha->fcp_prio_cfg); 3615 ha->fcp_prio_cfg = NULL; 3616 return QLA_FUNCTION_FAILED; 3617 } 3618