1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 #include <linux/trace_events.h> 19 #include <linux/trace.h> 20 21 #include <scsi/scsi_tcq.h> 22 #include <scsi/scsicam.h> 23 #include <scsi/scsi_transport.h> 24 #include <scsi/scsi_transport_fc.h> 25 26 #include "qla_target.h" 27 28 /* 29 * Driver version 30 */ 31 char qla2x00_version_str[40]; 32 33 static int apidev_major; 34 35 /* 36 * SRB allocation cache 37 */ 38 struct kmem_cache *srb_cachep; 39 40 static struct trace_array *qla_trc_array; 41 42 int ql2xfulldump_on_mpifail; 43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 45 "Set this to take full dump on MPI hang."); 46 47 int ql2xenforce_iocb_limit = 1; 48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 49 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 50 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 51 52 /* 53 * CT6 CTX allocation cache 54 */ 55 static struct kmem_cache *ctx_cachep; 56 /* 57 * error level for logging 58 */ 59 uint ql_errlev = 0x8001; 60 61 int ql2xsecenable; 62 module_param(ql2xsecenable, int, S_IRUGO); 63 MODULE_PARM_DESC(ql2xsecenable, 64 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 65 66 static int ql2xenableclass2; 67 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 68 MODULE_PARM_DESC(ql2xenableclass2, 69 "Specify if Class 2 operations are supported from the very " 70 "beginning. Default is 0 - class 2 not supported."); 71 72 73 int ql2xlogintimeout = 20; 74 module_param(ql2xlogintimeout, int, S_IRUGO); 75 MODULE_PARM_DESC(ql2xlogintimeout, 76 "Login timeout value in seconds."); 77 78 int qlport_down_retry; 79 module_param(qlport_down_retry, int, S_IRUGO); 80 MODULE_PARM_DESC(qlport_down_retry, 81 "Maximum number of command retries to a port that returns " 82 "a PORT-DOWN status."); 83 84 int ql2xplogiabsentdevice; 85 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 86 MODULE_PARM_DESC(ql2xplogiabsentdevice, 87 "Option to enable PLOGI to devices that are not present after " 88 "a Fabric scan. This is needed for several broken switches. " 89 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 90 91 int ql2xloginretrycount; 92 module_param(ql2xloginretrycount, int, S_IRUGO); 93 MODULE_PARM_DESC(ql2xloginretrycount, 94 "Specify an alternate value for the NVRAM login retry count."); 95 96 int ql2xallocfwdump = 1; 97 module_param(ql2xallocfwdump, int, S_IRUGO); 98 MODULE_PARM_DESC(ql2xallocfwdump, 99 "Option to enable allocation of memory for a firmware dump " 100 "during HBA initialization. Memory allocation requirements " 101 "vary by ISP type. Default is 1 - allocate memory."); 102 103 int ql2xextended_error_logging; 104 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 105 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 106 MODULE_PARM_DESC(ql2xextended_error_logging, 107 "Option to enable extended error logging,\n" 108 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 109 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 110 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 111 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 112 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 113 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 114 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 115 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 116 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 117 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 118 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 119 "\t\t0x1e400000 - Preferred value for capturing essential " 120 "debug information (equivalent to old " 121 "ql2xextended_error_logging=1).\n" 122 "\t\tDo LOGICAL OR of the value to enable more than one level"); 123 124 int ql2xextended_error_logging_ktrace = 1; 125 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR); 126 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace, 127 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n"); 128 129 int ql2xshiftctondsd = 6; 130 module_param(ql2xshiftctondsd, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xshiftctondsd, 132 "Set to control shifting of command type processing " 133 "based on total number of SG elements."); 134 135 int ql2xfdmienable = 1; 136 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 137 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 138 MODULE_PARM_DESC(ql2xfdmienable, 139 "Enables FDMI registrations. " 140 "0 - no FDMI registrations. " 141 "1 - provide FDMI registrations (default)."); 142 143 #define MAX_Q_DEPTH 64 144 static int ql2xmaxqdepth = MAX_Q_DEPTH; 145 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 146 MODULE_PARM_DESC(ql2xmaxqdepth, 147 "Maximum queue depth to set for each LUN. " 148 "Default is 64."); 149 150 int ql2xenabledif = 2; 151 module_param(ql2xenabledif, int, S_IRUGO); 152 MODULE_PARM_DESC(ql2xenabledif, 153 " Enable T10-CRC-DIF:\n" 154 " Default is 2.\n" 155 " 0 -- No DIF Support\n" 156 " 1 -- Enable DIF for all types\n" 157 " 2 -- Enable DIF for all types, except Type 0.\n"); 158 159 #if (IS_ENABLED(CONFIG_NVME_FC)) 160 int ql2xnvmeenable = 1; 161 #else 162 int ql2xnvmeenable; 163 #endif 164 module_param(ql2xnvmeenable, int, 0644); 165 MODULE_PARM_DESC(ql2xnvmeenable, 166 "Enables NVME support. " 167 "0 - no NVMe. Default is Y"); 168 169 int ql2xenablehba_err_chk = 2; 170 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xenablehba_err_chk, 172 " Enable T10-CRC-DIF Error isolation by HBA:\n" 173 " Default is 2.\n" 174 " 0 -- Error isolation disabled\n" 175 " 1 -- Error isolation enabled only for DIX Type 0\n" 176 " 2 -- Error isolation enabled for all Types\n"); 177 178 int ql2xiidmaenable = 1; 179 module_param(ql2xiidmaenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xiidmaenable, 181 "Enables iIDMA settings " 182 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 183 184 int ql2xmqsupport = 1; 185 module_param(ql2xmqsupport, int, S_IRUGO); 186 MODULE_PARM_DESC(ql2xmqsupport, 187 "Enable on demand multiple queue pairs support " 188 "Default is 1 for supported. " 189 "Set it to 0 to turn off mq qpair support."); 190 191 int ql2xfwloadbin; 192 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 193 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 194 MODULE_PARM_DESC(ql2xfwloadbin, 195 "Option to specify location from which to load ISP firmware:.\n" 196 " 2 -- load firmware via the request_firmware() (hotplug).\n" 197 " interface.\n" 198 " 1 -- load firmware from flash.\n" 199 " 0 -- use default semantics.\n"); 200 201 int ql2xetsenable; 202 module_param(ql2xetsenable, int, S_IRUGO); 203 MODULE_PARM_DESC(ql2xetsenable, 204 "Enables firmware ETS burst." 205 "Default is 0 - skip ETS enablement."); 206 207 int ql2xdbwr = 1; 208 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 209 MODULE_PARM_DESC(ql2xdbwr, 210 "Option to specify scheme for request queue posting.\n" 211 " 0 -- Regular doorbell.\n" 212 " 1 -- CAMRAM doorbell (faster).\n"); 213 214 int ql2xgffidenable; 215 module_param(ql2xgffidenable, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xgffidenable, 217 "Enables GFF_ID checks of port type. " 218 "Default is 0 - Do not use GFF_ID information."); 219 220 int ql2xasynctmfenable = 1; 221 module_param(ql2xasynctmfenable, int, S_IRUGO); 222 MODULE_PARM_DESC(ql2xasynctmfenable, 223 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 224 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 225 226 int ql2xdontresethba; 227 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 228 MODULE_PARM_DESC(ql2xdontresethba, 229 "Option to specify reset behaviour.\n" 230 " 0 (Default) -- Reset on failure.\n" 231 " 1 -- Do not reset on failure.\n"); 232 233 uint64_t ql2xmaxlun = MAX_LUNS; 234 module_param(ql2xmaxlun, ullong, S_IRUGO); 235 MODULE_PARM_DESC(ql2xmaxlun, 236 "Defines the maximum LU number to register with the SCSI " 237 "midlayer. Default is 65535."); 238 239 int ql2xmdcapmask = 0x1F; 240 module_param(ql2xmdcapmask, int, S_IRUGO); 241 MODULE_PARM_DESC(ql2xmdcapmask, 242 "Set the Minidump driver capture mask level. " 243 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 244 245 int ql2xmdenable = 1; 246 module_param(ql2xmdenable, int, S_IRUGO); 247 MODULE_PARM_DESC(ql2xmdenable, 248 "Enable/disable MiniDump. " 249 "0 - MiniDump disabled. " 250 "1 (Default) - MiniDump enabled."); 251 252 int ql2xexlogins; 253 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 254 MODULE_PARM_DESC(ql2xexlogins, 255 "Number of extended Logins. " 256 "0 (Default)- Disabled."); 257 258 int ql2xexchoffld = 1024; 259 module_param(ql2xexchoffld, uint, 0644); 260 MODULE_PARM_DESC(ql2xexchoffld, 261 "Number of target exchanges."); 262 263 int ql2xiniexchg = 1024; 264 module_param(ql2xiniexchg, uint, 0644); 265 MODULE_PARM_DESC(ql2xiniexchg, 266 "Number of initiator exchanges."); 267 268 int ql2xfwholdabts; 269 module_param(ql2xfwholdabts, int, S_IRUGO); 270 MODULE_PARM_DESC(ql2xfwholdabts, 271 "Allow FW to hold status IOCB until ABTS rsp received. " 272 "0 (Default) Do not set fw option. " 273 "1 - Set fw option to hold ABTS."); 274 275 int ql2xmvasynctoatio = 1; 276 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 277 MODULE_PARM_DESC(ql2xmvasynctoatio, 278 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 279 "0 (Default). Do not move IOCBs" 280 "1 - Move IOCBs."); 281 282 int ql2xautodetectsfp = 1; 283 module_param(ql2xautodetectsfp, int, 0444); 284 MODULE_PARM_DESC(ql2xautodetectsfp, 285 "Detect SFP range and set appropriate distance.\n" 286 "1 (Default): Enable\n"); 287 288 int ql2xenablemsix = 1; 289 module_param(ql2xenablemsix, int, 0444); 290 MODULE_PARM_DESC(ql2xenablemsix, 291 "Set to enable MSI or MSI-X interrupt mechanism.\n" 292 " Default is 1, enable MSI-X interrupt mechanism.\n" 293 " 0 -- enable traditional pin-based mechanism.\n" 294 " 1 -- enable MSI-X interrupt mechanism.\n" 295 " 2 -- enable MSI interrupt mechanism.\n"); 296 297 int qla2xuseresexchforels; 298 module_param(qla2xuseresexchforels, int, 0444); 299 MODULE_PARM_DESC(qla2xuseresexchforels, 300 "Reserve 1/2 of emergency exchanges for ELS.\n" 301 " 0 (default): disabled"); 302 303 static int ql2xprotmask; 304 module_param(ql2xprotmask, int, 0644); 305 MODULE_PARM_DESC(ql2xprotmask, 306 "Override DIF/DIX protection capabilities mask\n" 307 "Default is 0 which sets protection mask based on " 308 "capabilities reported by HBA firmware.\n"); 309 310 static int ql2xprotguard; 311 module_param(ql2xprotguard, int, 0644); 312 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 313 " 0 -- Let HBA firmware decide\n" 314 " 1 -- Force T10 CRC\n" 315 " 2 -- Force IP checksum\n"); 316 317 int ql2xdifbundlinginternalbuffers; 318 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 319 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 320 "Force using internal buffers for DIF information\n" 321 "0 (Default). Based on check.\n" 322 "1 Force using internal buffers\n"); 323 324 int ql2xsmartsan; 325 module_param(ql2xsmartsan, int, 0444); 326 module_param_named(smartsan, ql2xsmartsan, int, 0444); 327 MODULE_PARM_DESC(ql2xsmartsan, 328 "Send SmartSAN Management Attributes for FDMI Registration." 329 " Default is 0 - No SmartSAN registration," 330 " 1 - Register SmartSAN Management Attributes."); 331 332 int ql2xrdpenable; 333 module_param(ql2xrdpenable, int, 0444); 334 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 335 MODULE_PARM_DESC(ql2xrdpenable, 336 "Enables RDP responses. " 337 "0 - no RDP responses (default). " 338 "1 - provide RDP responses."); 339 int ql2xabts_wait_nvme = 1; 340 module_param(ql2xabts_wait_nvme, int, 0444); 341 MODULE_PARM_DESC(ql2xabts_wait_nvme, 342 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 343 344 345 static u32 ql2xdelay_before_pci_error_handling = 5; 346 module_param(ql2xdelay_before_pci_error_handling, uint, 0644); 347 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling, 348 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n"); 349 350 static void qla2x00_clear_drv_active(struct qla_hw_data *); 351 static void qla2x00_free_device(scsi_qla_host_t *); 352 static void qla2xxx_map_queues(struct Scsi_Host *shost); 353 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 354 355 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES; 356 module_param(ql2xnvme_queues, uint, S_IRUGO); 357 MODULE_PARM_DESC(ql2xnvme_queues, 358 "Number of NVMe Queues that can be configured.\n" 359 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n" 360 "1 - Minimum number of queues supported\n" 361 "8 - Default value"); 362 363 int ql2xfc2target = 1; 364 module_param(ql2xfc2target, int, 0444); 365 MODULE_PARM_DESC(qla2xfc2target, 366 "Enables FC2 Target support. " 367 "0 - FC2 Target support is disabled. " 368 "1 - FC2 Target support is enabled (default)."); 369 370 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 371 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 372 373 /* TODO Convert to inlines 374 * 375 * Timer routines 376 */ 377 378 __inline__ void 379 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 380 { 381 timer_setup(&vha->timer, qla2x00_timer, 0); 382 vha->timer.expires = jiffies + interval * HZ; 383 add_timer(&vha->timer); 384 vha->timer_active = 1; 385 } 386 387 static inline void 388 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 389 { 390 /* Currently used for 82XX only. */ 391 if (vha->device_flags & DFLG_DEV_FAILED) { 392 ql_dbg(ql_dbg_timer, vha, 0x600d, 393 "Device in a failed state, returning.\n"); 394 return; 395 } 396 397 mod_timer(&vha->timer, jiffies + interval * HZ); 398 } 399 400 static __inline__ void 401 qla2x00_stop_timer(scsi_qla_host_t *vha) 402 { 403 del_timer_sync(&vha->timer); 404 vha->timer_active = 0; 405 } 406 407 static int qla2x00_do_dpc(void *data); 408 409 static void qla2x00_rst_aen(scsi_qla_host_t *); 410 411 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 412 struct req_que **, struct rsp_que **); 413 static void qla2x00_free_fw_dump(struct qla_hw_data *); 414 static void qla2x00_mem_free(struct qla_hw_data *); 415 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 416 struct qla_qpair *qpair); 417 418 /* -------------------------------------------------------------------------- */ 419 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 420 struct rsp_que *rsp) 421 { 422 struct qla_hw_data *ha = vha->hw; 423 424 rsp->qpair = ha->base_qpair; 425 rsp->req = req; 426 ha->base_qpair->hw = ha; 427 ha->base_qpair->req = req; 428 ha->base_qpair->rsp = rsp; 429 ha->base_qpair->vha = vha; 430 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 431 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 432 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 433 ha->base_qpair->srb_mempool = ha->srb_mempool; 434 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 435 ha->base_qpair->enable_class_2 = ql2xenableclass2; 436 /* init qpair to this cpu. Will adjust at run time. */ 437 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 438 ha->base_qpair->pdev = ha->pdev; 439 440 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 441 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 442 } 443 444 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 445 struct rsp_que *rsp) 446 { 447 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 448 449 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 450 GFP_KERNEL); 451 if (!ha->req_q_map) { 452 ql_log(ql_log_fatal, vha, 0x003b, 453 "Unable to allocate memory for request queue ptrs.\n"); 454 goto fail_req_map; 455 } 456 457 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 458 GFP_KERNEL); 459 if (!ha->rsp_q_map) { 460 ql_log(ql_log_fatal, vha, 0x003c, 461 "Unable to allocate memory for response queue ptrs.\n"); 462 goto fail_rsp_map; 463 } 464 465 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 466 if (ha->base_qpair == NULL) { 467 ql_log(ql_log_warn, vha, 0x00e0, 468 "Failed to allocate base queue pair memory.\n"); 469 goto fail_base_qpair; 470 } 471 472 qla_init_base_qpair(vha, req, rsp); 473 474 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 475 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 476 GFP_KERNEL); 477 if (!ha->queue_pair_map) { 478 ql_log(ql_log_fatal, vha, 0x0180, 479 "Unable to allocate memory for queue pair ptrs.\n"); 480 goto fail_qpair_map; 481 } 482 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) { 483 kfree(ha->queue_pair_map); 484 ha->queue_pair_map = NULL; 485 goto fail_qpair_map; 486 } 487 } 488 489 /* 490 * Make sure we record at least the request and response queue zero in 491 * case we need to free them if part of the probe fails. 492 */ 493 ha->rsp_q_map[0] = rsp; 494 ha->req_q_map[0] = req; 495 set_bit(0, ha->rsp_qid_map); 496 set_bit(0, ha->req_qid_map); 497 return 0; 498 499 fail_qpair_map: 500 kfree(ha->base_qpair); 501 ha->base_qpair = NULL; 502 fail_base_qpair: 503 kfree(ha->rsp_q_map); 504 ha->rsp_q_map = NULL; 505 fail_rsp_map: 506 kfree(ha->req_q_map); 507 ha->req_q_map = NULL; 508 fail_req_map: 509 return -ENOMEM; 510 } 511 512 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 513 { 514 if (IS_QLAFX00(ha)) { 515 if (req && req->ring_fx00) 516 dma_free_coherent(&ha->pdev->dev, 517 (req->length_fx00 + 1) * sizeof(request_t), 518 req->ring_fx00, req->dma_fx00); 519 } else if (req && req->ring) 520 dma_free_coherent(&ha->pdev->dev, 521 (req->length + 1) * sizeof(request_t), 522 req->ring, req->dma); 523 524 if (req) 525 kfree(req->outstanding_cmds); 526 527 kfree(req); 528 } 529 530 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 531 { 532 if (IS_QLAFX00(ha)) { 533 if (rsp && rsp->ring_fx00) 534 dma_free_coherent(&ha->pdev->dev, 535 (rsp->length_fx00 + 1) * sizeof(request_t), 536 rsp->ring_fx00, rsp->dma_fx00); 537 } else if (rsp && rsp->ring) { 538 dma_free_coherent(&ha->pdev->dev, 539 (rsp->length + 1) * sizeof(response_t), 540 rsp->ring, rsp->dma); 541 } 542 kfree(rsp); 543 } 544 545 static void qla2x00_free_queues(struct qla_hw_data *ha) 546 { 547 struct req_que *req; 548 struct rsp_que *rsp; 549 int cnt; 550 unsigned long flags; 551 552 if (ha->queue_pair_map) { 553 kfree(ha->queue_pair_map); 554 ha->queue_pair_map = NULL; 555 } 556 if (ha->base_qpair) { 557 kfree(ha->base_qpair); 558 ha->base_qpair = NULL; 559 } 560 561 qla_mapq_free_qp_cpu_map(ha); 562 spin_lock_irqsave(&ha->hardware_lock, flags); 563 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 564 if (!test_bit(cnt, ha->req_qid_map)) 565 continue; 566 567 req = ha->req_q_map[cnt]; 568 clear_bit(cnt, ha->req_qid_map); 569 ha->req_q_map[cnt] = NULL; 570 571 spin_unlock_irqrestore(&ha->hardware_lock, flags); 572 qla2x00_free_req_que(ha, req); 573 spin_lock_irqsave(&ha->hardware_lock, flags); 574 } 575 spin_unlock_irqrestore(&ha->hardware_lock, flags); 576 577 kfree(ha->req_q_map); 578 ha->req_q_map = NULL; 579 580 581 spin_lock_irqsave(&ha->hardware_lock, flags); 582 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 583 if (!test_bit(cnt, ha->rsp_qid_map)) 584 continue; 585 586 rsp = ha->rsp_q_map[cnt]; 587 clear_bit(cnt, ha->rsp_qid_map); 588 ha->rsp_q_map[cnt] = NULL; 589 spin_unlock_irqrestore(&ha->hardware_lock, flags); 590 qla2x00_free_rsp_que(ha, rsp); 591 spin_lock_irqsave(&ha->hardware_lock, flags); 592 } 593 spin_unlock_irqrestore(&ha->hardware_lock, flags); 594 595 kfree(ha->rsp_q_map); 596 ha->rsp_q_map = NULL; 597 } 598 599 static char * 600 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 601 { 602 struct qla_hw_data *ha = vha->hw; 603 static const char *const pci_bus_modes[] = { 604 "33", "66", "100", "133", 605 }; 606 uint16_t pci_bus; 607 608 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 609 if (pci_bus) { 610 snprintf(str, str_len, "PCI-X (%s MHz)", 611 pci_bus_modes[pci_bus]); 612 } else { 613 pci_bus = (ha->pci_attr & BIT_8) >> 8; 614 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 615 } 616 617 return str; 618 } 619 620 static char * 621 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 622 { 623 static const char *const pci_bus_modes[] = { 624 "33", "66", "100", "133", 625 }; 626 struct qla_hw_data *ha = vha->hw; 627 uint32_t pci_bus; 628 629 if (pci_is_pcie(ha->pdev)) { 630 uint32_t lstat, lspeed, lwidth; 631 const char *speed_str; 632 633 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 634 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 635 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 636 637 switch (lspeed) { 638 case 1: 639 speed_str = "2.5GT/s"; 640 break; 641 case 2: 642 speed_str = "5.0GT/s"; 643 break; 644 case 3: 645 speed_str = "8.0GT/s"; 646 break; 647 case 4: 648 speed_str = "16.0GT/s"; 649 break; 650 default: 651 speed_str = "<unknown>"; 652 break; 653 } 654 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 655 656 return str; 657 } 658 659 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 660 if (pci_bus == 0 || pci_bus == 8) 661 snprintf(str, str_len, "PCI (%s MHz)", 662 pci_bus_modes[pci_bus >> 3]); 663 else 664 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 665 pci_bus & 4 ? 2 : 1, 666 pci_bus_modes[pci_bus & 3]); 667 668 return str; 669 } 670 671 static char * 672 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 673 { 674 char un_str[10]; 675 struct qla_hw_data *ha = vha->hw; 676 677 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 678 ha->fw_minor_version, ha->fw_subminor_version); 679 680 if (ha->fw_attributes & BIT_9) { 681 strcat(str, "FLX"); 682 return (str); 683 } 684 685 switch (ha->fw_attributes & 0xFF) { 686 case 0x7: 687 strcat(str, "EF"); 688 break; 689 case 0x17: 690 strcat(str, "TP"); 691 break; 692 case 0x37: 693 strcat(str, "IP"); 694 break; 695 case 0x77: 696 strcat(str, "VI"); 697 break; 698 default: 699 sprintf(un_str, "(%x)", ha->fw_attributes); 700 strcat(str, un_str); 701 break; 702 } 703 if (ha->fw_attributes & 0x100) 704 strcat(str, "X"); 705 706 return (str); 707 } 708 709 static char * 710 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 711 { 712 struct qla_hw_data *ha = vha->hw; 713 714 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 715 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 716 return str; 717 } 718 719 void qla2x00_sp_free_dma(srb_t *sp) 720 { 721 struct qla_hw_data *ha = sp->vha->hw; 722 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 723 724 if (sp->flags & SRB_DMA_VALID) { 725 scsi_dma_unmap(cmd); 726 sp->flags &= ~SRB_DMA_VALID; 727 } 728 729 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 730 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 731 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 732 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 733 } 734 735 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 736 /* List assured to be having elements */ 737 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 738 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 739 } 740 741 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 742 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 743 744 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 745 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 746 } 747 748 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 749 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 750 751 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 752 ctx1->fcp_cmnd_dma); 753 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 754 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 755 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 756 } 757 758 if (sp->flags & SRB_GOT_BUF) 759 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 760 } 761 762 void qla2x00_sp_compl(srb_t *sp, int res) 763 { 764 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 765 struct completion *comp = sp->comp; 766 767 /* kref: INIT */ 768 kref_put(&sp->cmd_kref, qla2x00_sp_release); 769 cmd->result = res; 770 sp->type = 0; 771 scsi_done(cmd); 772 if (comp) 773 complete(comp); 774 } 775 776 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 777 { 778 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 779 struct qla_hw_data *ha = sp->fcport->vha->hw; 780 781 if (sp->flags & SRB_DMA_VALID) { 782 scsi_dma_unmap(cmd); 783 sp->flags &= ~SRB_DMA_VALID; 784 } 785 786 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 787 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 788 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 789 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 790 } 791 792 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 793 /* List assured to be having elements */ 794 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 795 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 796 } 797 798 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 799 struct crc_context *difctx = sp->u.scmd.crc_ctx; 800 struct dsd_dma *dif_dsd, *nxt_dsd; 801 802 list_for_each_entry_safe(dif_dsd, nxt_dsd, 803 &difctx->ldif_dma_hndl_list, list) { 804 list_del(&dif_dsd->list); 805 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 806 dif_dsd->dsd_list_dma); 807 kfree(dif_dsd); 808 difctx->no_dif_bundl--; 809 } 810 811 list_for_each_entry_safe(dif_dsd, nxt_dsd, 812 &difctx->ldif_dsd_list, list) { 813 list_del(&dif_dsd->list); 814 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 815 dif_dsd->dsd_list_dma); 816 kfree(dif_dsd); 817 difctx->no_ldif_dsd--; 818 } 819 820 if (difctx->no_ldif_dsd) { 821 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 822 "%s: difctx->no_ldif_dsd=%x\n", 823 __func__, difctx->no_ldif_dsd); 824 } 825 826 if (difctx->no_dif_bundl) { 827 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 828 "%s: difctx->no_dif_bundl=%x\n", 829 __func__, difctx->no_dif_bundl); 830 } 831 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 832 } 833 834 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 835 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 836 837 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 838 ctx1->fcp_cmnd_dma); 839 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 840 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 841 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 842 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 843 } 844 845 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 846 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 847 848 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 849 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 850 } 851 852 if (sp->flags & SRB_GOT_BUF) 853 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 854 } 855 856 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 857 { 858 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 859 struct completion *comp = sp->comp; 860 861 /* ref: INIT */ 862 kref_put(&sp->cmd_kref, qla2x00_sp_release); 863 cmd->result = res; 864 sp->type = 0; 865 scsi_done(cmd); 866 if (comp) 867 complete(comp); 868 } 869 870 static int 871 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 872 { 873 scsi_qla_host_t *vha = shost_priv(host); 874 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 875 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 876 struct qla_hw_data *ha = vha->hw; 877 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 878 srb_t *sp; 879 int rval; 880 881 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 882 WARN_ON_ONCE(!rport)) { 883 cmd->result = DID_NO_CONNECT << 16; 884 goto qc24_fail_command; 885 } 886 887 if (ha->mqenable) { 888 uint32_t tag; 889 uint16_t hwq; 890 struct qla_qpair *qpair = NULL; 891 892 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 893 hwq = blk_mq_unique_tag_to_hwq(tag); 894 qpair = ha->queue_pair_map[hwq]; 895 896 if (qpair) 897 return qla2xxx_mqueuecommand(host, cmd, qpair); 898 } 899 900 if (ha->flags.eeh_busy) { 901 if (ha->flags.pci_channel_io_perm_failure) { 902 ql_dbg(ql_dbg_aer, vha, 0x9010, 903 "PCI Channel IO permanent failure, exiting " 904 "cmd=%p.\n", cmd); 905 cmd->result = DID_NO_CONNECT << 16; 906 } else { 907 ql_dbg(ql_dbg_aer, vha, 0x9011, 908 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 909 cmd->result = DID_REQUEUE << 16; 910 } 911 goto qc24_fail_command; 912 } 913 914 rval = fc_remote_port_chkready(rport); 915 if (rval) { 916 cmd->result = rval; 917 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 918 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 919 cmd, rval); 920 goto qc24_fail_command; 921 } 922 923 if (!vha->flags.difdix_supported && 924 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 925 ql_dbg(ql_dbg_io, vha, 0x3004, 926 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 927 cmd); 928 cmd->result = DID_NO_CONNECT << 16; 929 goto qc24_fail_command; 930 } 931 932 if (!fcport || fcport->deleted) { 933 cmd->result = DID_IMM_RETRY << 16; 934 goto qc24_fail_command; 935 } 936 937 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 938 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 939 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 940 ql_dbg(ql_dbg_io, vha, 0x3005, 941 "Returning DNC, fcport_state=%d loop_state=%d.\n", 942 atomic_read(&fcport->state), 943 atomic_read(&base_vha->loop_state)); 944 cmd->result = DID_NO_CONNECT << 16; 945 goto qc24_fail_command; 946 } 947 goto qc24_target_busy; 948 } 949 950 /* 951 * Return target busy if we've received a non-zero retry_delay_timer 952 * in a FCP_RSP. 953 */ 954 if (fcport->retry_delay_timestamp == 0) { 955 /* retry delay not set */ 956 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 957 fcport->retry_delay_timestamp = 0; 958 else 959 goto qc24_target_busy; 960 961 sp = scsi_cmd_priv(cmd); 962 /* ref: INIT */ 963 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 964 965 sp->u.scmd.cmd = cmd; 966 sp->type = SRB_SCSI_CMD; 967 sp->free = qla2x00_sp_free_dma; 968 sp->done = qla2x00_sp_compl; 969 970 rval = ha->isp_ops->start_scsi(sp); 971 if (rval != QLA_SUCCESS) { 972 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 973 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 974 goto qc24_host_busy_free_sp; 975 } 976 977 return 0; 978 979 qc24_host_busy_free_sp: 980 /* ref: INIT */ 981 kref_put(&sp->cmd_kref, qla2x00_sp_release); 982 983 qc24_target_busy: 984 return SCSI_MLQUEUE_TARGET_BUSY; 985 986 qc24_fail_command: 987 scsi_done(cmd); 988 989 return 0; 990 } 991 992 /* For MQ supported I/O */ 993 int 994 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 995 struct qla_qpair *qpair) 996 { 997 scsi_qla_host_t *vha = shost_priv(host); 998 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 999 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 1000 struct qla_hw_data *ha = vha->hw; 1001 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1002 srb_t *sp; 1003 int rval; 1004 1005 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 1006 if (rval) { 1007 cmd->result = rval; 1008 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 1009 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 1010 cmd, rval); 1011 goto qc24_fail_command; 1012 } 1013 1014 if (!qpair->online) { 1015 ql_dbg(ql_dbg_io, vha, 0x3077, 1016 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 1017 cmd->result = DID_NO_CONNECT << 16; 1018 goto qc24_fail_command; 1019 } 1020 1021 if (!fcport || fcport->deleted) { 1022 cmd->result = DID_IMM_RETRY << 16; 1023 goto qc24_fail_command; 1024 } 1025 1026 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 1027 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1028 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1029 ql_dbg(ql_dbg_io, vha, 0x3077, 1030 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1031 atomic_read(&fcport->state), 1032 atomic_read(&base_vha->loop_state)); 1033 cmd->result = DID_NO_CONNECT << 16; 1034 goto qc24_fail_command; 1035 } 1036 goto qc24_target_busy; 1037 } 1038 1039 /* 1040 * Return target busy if we've received a non-zero retry_delay_timer 1041 * in a FCP_RSP. 1042 */ 1043 if (fcport->retry_delay_timestamp == 0) { 1044 /* retry delay not set */ 1045 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1046 fcport->retry_delay_timestamp = 0; 1047 else 1048 goto qc24_target_busy; 1049 1050 sp = scsi_cmd_priv(cmd); 1051 /* ref: INIT */ 1052 qla2xxx_init_sp(sp, vha, qpair, fcport); 1053 1054 sp->u.scmd.cmd = cmd; 1055 sp->type = SRB_SCSI_CMD; 1056 sp->free = qla2xxx_qpair_sp_free_dma; 1057 sp->done = qla2xxx_qpair_sp_compl; 1058 1059 rval = ha->isp_ops->start_scsi_mq(sp); 1060 if (rval != QLA_SUCCESS) { 1061 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1062 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1063 goto qc24_host_busy_free_sp; 1064 } 1065 1066 return 0; 1067 1068 qc24_host_busy_free_sp: 1069 /* ref: INIT */ 1070 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1071 1072 qc24_target_busy: 1073 return SCSI_MLQUEUE_TARGET_BUSY; 1074 1075 qc24_fail_command: 1076 scsi_done(cmd); 1077 1078 return 0; 1079 } 1080 1081 /* 1082 * qla2x00_eh_wait_on_command 1083 * Waits for the command to be returned by the Firmware for some 1084 * max time. 1085 * 1086 * Input: 1087 * cmd = Scsi Command to wait on. 1088 * 1089 * Return: 1090 * Completed in time : QLA_SUCCESS 1091 * Did not complete in time : QLA_FUNCTION_FAILED 1092 */ 1093 static int 1094 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1095 { 1096 #define ABORT_POLLING_PERIOD 1000 1097 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1098 unsigned long wait_iter = ABORT_WAIT_ITER; 1099 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1100 struct qla_hw_data *ha = vha->hw; 1101 srb_t *sp = scsi_cmd_priv(cmd); 1102 int ret = QLA_SUCCESS; 1103 1104 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1105 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1106 "Return:eh_wait.\n"); 1107 return ret; 1108 } 1109 1110 while (sp->type && wait_iter--) 1111 msleep(ABORT_POLLING_PERIOD); 1112 if (sp->type) 1113 ret = QLA_FUNCTION_FAILED; 1114 1115 return ret; 1116 } 1117 1118 /* 1119 * qla2x00_wait_for_hba_online 1120 * Wait till the HBA is online after going through 1121 * <= MAX_RETRIES_OF_ISP_ABORT or 1122 * finally HBA is disabled ie marked offline 1123 * 1124 * Input: 1125 * ha - pointer to host adapter structure 1126 * 1127 * Note: 1128 * Does context switching-Release SPIN_LOCK 1129 * (if any) before calling this routine. 1130 * 1131 * Return: 1132 * Success (Adapter is online) : 0 1133 * Failed (Adapter is offline/disabled) : 1 1134 */ 1135 int 1136 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1137 { 1138 int return_status; 1139 unsigned long wait_online; 1140 struct qla_hw_data *ha = vha->hw; 1141 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1142 1143 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1144 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1145 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1146 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1147 ha->dpc_active) && time_before(jiffies, wait_online)) { 1148 1149 msleep(1000); 1150 } 1151 if (base_vha->flags.online) 1152 return_status = QLA_SUCCESS; 1153 else 1154 return_status = QLA_FUNCTION_FAILED; 1155 1156 return (return_status); 1157 } 1158 1159 static inline int test_fcport_count(scsi_qla_host_t *vha) 1160 { 1161 struct qla_hw_data *ha = vha->hw; 1162 unsigned long flags; 1163 int res; 1164 /* Return 0 = sleep, x=wake */ 1165 1166 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1167 ql_dbg(ql_dbg_init, vha, 0x00ec, 1168 "tgt %p, fcport_count=%d\n", 1169 vha, vha->fcport_count); 1170 res = (vha->fcport_count == 0); 1171 if (res) { 1172 struct fc_port *fcport; 1173 1174 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1175 if (fcport->deleted != QLA_SESS_DELETED) { 1176 /* session(s) may not be fully logged in 1177 * (ie fcport_count=0), but session 1178 * deletion thread(s) may be inflight. 1179 */ 1180 1181 res = 0; 1182 break; 1183 } 1184 } 1185 } 1186 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1187 1188 return res; 1189 } 1190 1191 /* 1192 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1193 * it has dependency on UNLOADING flag to stop device discovery 1194 */ 1195 void 1196 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1197 { 1198 u8 i; 1199 1200 qla2x00_mark_all_devices_lost(vha); 1201 1202 for (i = 0; i < 10; i++) { 1203 if (wait_event_timeout(vha->fcport_waitQ, 1204 test_fcport_count(vha), HZ) > 0) 1205 break; 1206 } 1207 1208 flush_workqueue(vha->hw->wq); 1209 } 1210 1211 /* 1212 * qla2x00_wait_for_hba_ready 1213 * Wait till the HBA is ready before doing driver unload 1214 * 1215 * Input: 1216 * ha - pointer to host adapter structure 1217 * 1218 * Note: 1219 * Does context switching-Release SPIN_LOCK 1220 * (if any) before calling this routine. 1221 * 1222 */ 1223 static void 1224 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1225 { 1226 struct qla_hw_data *ha = vha->hw; 1227 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1228 1229 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1230 ha->flags.mbox_busy) || 1231 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1232 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1233 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1234 break; 1235 msleep(1000); 1236 } 1237 } 1238 1239 int 1240 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1241 { 1242 int return_status; 1243 unsigned long wait_reset; 1244 struct qla_hw_data *ha = vha->hw; 1245 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1246 1247 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1248 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1249 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1250 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1251 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1252 1253 msleep(1000); 1254 1255 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1256 ha->flags.chip_reset_done) 1257 break; 1258 } 1259 if (ha->flags.chip_reset_done) 1260 return_status = QLA_SUCCESS; 1261 else 1262 return_status = QLA_FUNCTION_FAILED; 1263 1264 return return_status; 1265 } 1266 1267 /************************************************************************** 1268 * qla2xxx_eh_abort 1269 * 1270 * Description: 1271 * The abort function will abort the specified command. 1272 * 1273 * Input: 1274 * cmd = Linux SCSI command packet to be aborted. 1275 * 1276 * Returns: 1277 * Either SUCCESS or FAILED. 1278 * 1279 * Note: 1280 * Only return FAILED if command not returned by firmware. 1281 **************************************************************************/ 1282 static int 1283 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1284 { 1285 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1286 DECLARE_COMPLETION_ONSTACK(comp); 1287 srb_t *sp; 1288 int ret; 1289 unsigned int id; 1290 uint64_t lun; 1291 int rval; 1292 struct qla_hw_data *ha = vha->hw; 1293 uint32_t ratov_j; 1294 struct qla_qpair *qpair; 1295 unsigned long flags; 1296 int fast_fail_status = SUCCESS; 1297 1298 if (qla2x00_isp_reg_stat(ha)) { 1299 ql_log(ql_log_info, vha, 0x8042, 1300 "PCI/Register disconnect, exiting.\n"); 1301 qla_pci_set_eeh_busy(vha); 1302 return FAILED; 1303 } 1304 1305 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1306 ret = fc_block_scsi_eh(cmd); 1307 if (ret != 0) 1308 fast_fail_status = ret; 1309 1310 sp = scsi_cmd_priv(cmd); 1311 qpair = sp->qpair; 1312 1313 vha->cmd_timeout_cnt++; 1314 1315 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1316 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1317 1318 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1319 sp->comp = ∁ 1320 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1321 1322 1323 id = cmd->device->id; 1324 lun = cmd->device->lun; 1325 1326 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1327 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1328 vha->host_no, id, lun, sp, cmd, sp->handle); 1329 1330 /* 1331 * Abort will release the original Command/sp from FW. Let the 1332 * original command call scsi_done. In return, he will wakeup 1333 * this sleeping thread. 1334 */ 1335 rval = ha->isp_ops->abort_command(sp); 1336 1337 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1338 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1339 1340 /* Wait for the command completion. */ 1341 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1342 ratov_j = msecs_to_jiffies(ratov_j); 1343 switch (rval) { 1344 case QLA_SUCCESS: 1345 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1346 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1347 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1348 __func__, ha->r_a_tov/10); 1349 ret = FAILED; 1350 } else { 1351 ret = fast_fail_status; 1352 } 1353 break; 1354 default: 1355 ret = FAILED; 1356 break; 1357 } 1358 1359 sp->comp = NULL; 1360 1361 ql_log(ql_log_info, vha, 0x801c, 1362 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1363 vha->host_no, id, lun, ret); 1364 1365 return ret; 1366 } 1367 1368 /* 1369 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1370 */ 1371 static int 1372 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t, 1373 uint64_t l, enum nexus_wait_type type) 1374 { 1375 int cnt, match, status; 1376 unsigned long flags; 1377 scsi_qla_host_t *vha = qpair->vha; 1378 struct req_que *req = qpair->req; 1379 srb_t *sp; 1380 struct scsi_cmnd *cmd; 1381 1382 status = QLA_SUCCESS; 1383 1384 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1385 for (cnt = 1; status == QLA_SUCCESS && 1386 cnt < req->num_outstanding_cmds; cnt++) { 1387 sp = req->outstanding_cmds[cnt]; 1388 if (!sp) 1389 continue; 1390 if (sp->type != SRB_SCSI_CMD) 1391 continue; 1392 if (vha->vp_idx != sp->vha->vp_idx) 1393 continue; 1394 match = 0; 1395 cmd = GET_CMD_SP(sp); 1396 switch (type) { 1397 case WAIT_HOST: 1398 match = 1; 1399 break; 1400 case WAIT_TARGET: 1401 match = cmd->device->id == t; 1402 break; 1403 case WAIT_LUN: 1404 match = (cmd->device->id == t && 1405 cmd->device->lun == l); 1406 break; 1407 } 1408 if (!match) 1409 continue; 1410 1411 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1412 status = qla2x00_eh_wait_on_command(cmd); 1413 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1414 } 1415 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1416 1417 return status; 1418 } 1419 1420 int 1421 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1422 uint64_t l, enum nexus_wait_type type) 1423 { 1424 struct qla_qpair *qpair; 1425 struct qla_hw_data *ha = vha->hw; 1426 int i, status = QLA_SUCCESS; 1427 1428 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l, 1429 type); 1430 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) { 1431 qpair = ha->queue_pair_map[i]; 1432 if (!qpair) 1433 continue; 1434 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l, 1435 type); 1436 } 1437 return status; 1438 } 1439 1440 static char *reset_errors[] = { 1441 "HBA not online", 1442 "HBA not ready", 1443 "Task management failed", 1444 "Waiting for command completions", 1445 }; 1446 1447 static int 1448 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1449 { 1450 struct scsi_device *sdev = cmd->device; 1451 scsi_qla_host_t *vha = shost_priv(sdev->host); 1452 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1453 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1454 struct qla_hw_data *ha = vha->hw; 1455 int err; 1456 1457 if (qla2x00_isp_reg_stat(ha)) { 1458 ql_log(ql_log_info, vha, 0x803e, 1459 "PCI/Register disconnect, exiting.\n"); 1460 qla_pci_set_eeh_busy(vha); 1461 return FAILED; 1462 } 1463 1464 if (!fcport) { 1465 return FAILED; 1466 } 1467 1468 err = fc_block_rport(rport); 1469 if (err != 0) 1470 return err; 1471 1472 if (fcport->deleted) 1473 return FAILED; 1474 1475 ql_log(ql_log_info, vha, 0x8009, 1476 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1477 sdev->id, sdev->lun, cmd); 1478 1479 err = 0; 1480 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1481 ql_log(ql_log_warn, vha, 0x800a, 1482 "Wait for hba online failed for cmd=%p.\n", cmd); 1483 goto eh_reset_failed; 1484 } 1485 err = 2; 1486 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1487 != QLA_SUCCESS) { 1488 ql_log(ql_log_warn, vha, 0x800c, 1489 "do_reset failed for cmd=%p.\n", cmd); 1490 goto eh_reset_failed; 1491 } 1492 err = 3; 1493 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1494 sdev->lun, WAIT_LUN) != QLA_SUCCESS) { 1495 ql_log(ql_log_warn, vha, 0x800d, 1496 "wait for pending cmds failed for cmd=%p.\n", cmd); 1497 goto eh_reset_failed; 1498 } 1499 1500 ql_log(ql_log_info, vha, 0x800e, 1501 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1502 vha->host_no, sdev->id, sdev->lun, cmd); 1503 1504 return SUCCESS; 1505 1506 eh_reset_failed: 1507 ql_log(ql_log_info, vha, 0x800f, 1508 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1509 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1510 cmd); 1511 vha->reset_cmd_err_cnt++; 1512 return FAILED; 1513 } 1514 1515 static int 1516 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1517 { 1518 struct scsi_device *sdev = cmd->device; 1519 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1520 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1521 struct qla_hw_data *ha = vha->hw; 1522 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1523 int err; 1524 1525 if (qla2x00_isp_reg_stat(ha)) { 1526 ql_log(ql_log_info, vha, 0x803f, 1527 "PCI/Register disconnect, exiting.\n"); 1528 qla_pci_set_eeh_busy(vha); 1529 return FAILED; 1530 } 1531 1532 if (!fcport) { 1533 return FAILED; 1534 } 1535 1536 err = fc_block_rport(rport); 1537 if (err != 0) 1538 return err; 1539 1540 if (fcport->deleted) 1541 return FAILED; 1542 1543 ql_log(ql_log_info, vha, 0x8009, 1544 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1545 sdev->id, cmd); 1546 1547 err = 0; 1548 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1549 ql_log(ql_log_warn, vha, 0x800a, 1550 "Wait for hba online failed for cmd=%p.\n", cmd); 1551 goto eh_reset_failed; 1552 } 1553 err = 2; 1554 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1555 ql_log(ql_log_warn, vha, 0x800c, 1556 "target_reset failed for cmd=%p.\n", cmd); 1557 goto eh_reset_failed; 1558 } 1559 err = 3; 1560 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1561 0, WAIT_TARGET) != QLA_SUCCESS) { 1562 ql_log(ql_log_warn, vha, 0x800d, 1563 "wait for pending cmds failed for cmd=%p.\n", cmd); 1564 goto eh_reset_failed; 1565 } 1566 1567 ql_log(ql_log_info, vha, 0x800e, 1568 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1569 vha->host_no, sdev->id, cmd); 1570 1571 return SUCCESS; 1572 1573 eh_reset_failed: 1574 ql_log(ql_log_info, vha, 0x800f, 1575 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1576 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1577 cmd); 1578 vha->reset_cmd_err_cnt++; 1579 return FAILED; 1580 } 1581 1582 /************************************************************************** 1583 * qla2xxx_eh_bus_reset 1584 * 1585 * Description: 1586 * The bus reset function will reset the bus and abort any executing 1587 * commands. 1588 * 1589 * Input: 1590 * cmd = Linux SCSI command packet of the command that cause the 1591 * bus reset. 1592 * 1593 * Returns: 1594 * SUCCESS/FAILURE (defined as macro in scsi.h). 1595 * 1596 **************************************************************************/ 1597 static int 1598 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1599 { 1600 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1601 int ret = FAILED; 1602 unsigned int id; 1603 uint64_t lun; 1604 struct qla_hw_data *ha = vha->hw; 1605 1606 if (qla2x00_isp_reg_stat(ha)) { 1607 ql_log(ql_log_info, vha, 0x8040, 1608 "PCI/Register disconnect, exiting.\n"); 1609 qla_pci_set_eeh_busy(vha); 1610 return FAILED; 1611 } 1612 1613 id = cmd->device->id; 1614 lun = cmd->device->lun; 1615 1616 if (qla2x00_chip_is_down(vha)) 1617 return ret; 1618 1619 ql_log(ql_log_info, vha, 0x8012, 1620 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1621 1622 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1623 ql_log(ql_log_fatal, vha, 0x8013, 1624 "Wait for hba online failed board disabled.\n"); 1625 goto eh_bus_reset_done; 1626 } 1627 1628 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1629 ret = SUCCESS; 1630 1631 if (ret == FAILED) 1632 goto eh_bus_reset_done; 1633 1634 /* Flush outstanding commands. */ 1635 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1636 QLA_SUCCESS) { 1637 ql_log(ql_log_warn, vha, 0x8014, 1638 "Wait for pending commands failed.\n"); 1639 ret = FAILED; 1640 } 1641 1642 eh_bus_reset_done: 1643 ql_log(ql_log_warn, vha, 0x802b, 1644 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1645 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1646 1647 return ret; 1648 } 1649 1650 /************************************************************************** 1651 * qla2xxx_eh_host_reset 1652 * 1653 * Description: 1654 * The reset function will reset the Adapter. 1655 * 1656 * Input: 1657 * cmd = Linux SCSI command packet of the command that cause the 1658 * adapter reset. 1659 * 1660 * Returns: 1661 * Either SUCCESS or FAILED. 1662 * 1663 * Note: 1664 **************************************************************************/ 1665 static int 1666 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1667 { 1668 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1669 struct qla_hw_data *ha = vha->hw; 1670 int ret = FAILED; 1671 unsigned int id; 1672 uint64_t lun; 1673 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1674 1675 if (qla2x00_isp_reg_stat(ha)) { 1676 ql_log(ql_log_info, vha, 0x8041, 1677 "PCI/Register disconnect, exiting.\n"); 1678 qla_pci_set_eeh_busy(vha); 1679 return SUCCESS; 1680 } 1681 1682 id = cmd->device->id; 1683 lun = cmd->device->lun; 1684 1685 ql_log(ql_log_info, vha, 0x8018, 1686 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1687 1688 /* 1689 * No point in issuing another reset if one is active. Also do not 1690 * attempt a reset if we are updating flash. 1691 */ 1692 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1693 goto eh_host_reset_lock; 1694 1695 if (vha != base_vha) { 1696 if (qla2x00_vp_abort_isp(vha)) 1697 goto eh_host_reset_lock; 1698 } else { 1699 if (IS_P3P_TYPE(vha->hw)) { 1700 if (!qla82xx_fcoe_ctx_reset(vha)) { 1701 /* Ctx reset success */ 1702 ret = SUCCESS; 1703 goto eh_host_reset_lock; 1704 } 1705 /* fall thru if ctx reset failed */ 1706 } 1707 if (ha->wq) 1708 flush_workqueue(ha->wq); 1709 1710 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1711 if (ha->isp_ops->abort_isp(base_vha)) { 1712 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1713 /* failed. schedule dpc to try */ 1714 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1715 1716 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1717 ql_log(ql_log_warn, vha, 0x802a, 1718 "wait for hba online failed.\n"); 1719 goto eh_host_reset_lock; 1720 } 1721 } 1722 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1723 } 1724 1725 /* Waiting for command to be returned to OS.*/ 1726 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1727 QLA_SUCCESS) 1728 ret = SUCCESS; 1729 1730 eh_host_reset_lock: 1731 ql_log(ql_log_info, vha, 0x8017, 1732 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1733 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1734 1735 return ret; 1736 } 1737 1738 /* 1739 * qla2x00_loop_reset 1740 * Issue loop reset. 1741 * 1742 * Input: 1743 * ha = adapter block pointer. 1744 * 1745 * Returns: 1746 * 0 = success 1747 */ 1748 int 1749 qla2x00_loop_reset(scsi_qla_host_t *vha) 1750 { 1751 int ret; 1752 struct qla_hw_data *ha = vha->hw; 1753 1754 if (IS_QLAFX00(ha)) 1755 return QLA_SUCCESS; 1756 1757 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1758 atomic_set(&vha->loop_state, LOOP_DOWN); 1759 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1760 qla2x00_mark_all_devices_lost(vha); 1761 ret = qla2x00_full_login_lip(vha); 1762 if (ret != QLA_SUCCESS) { 1763 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1764 "full_login_lip=%d.\n", ret); 1765 } 1766 } 1767 1768 if (ha->flags.enable_lip_reset) { 1769 ret = qla2x00_lip_reset(vha); 1770 if (ret != QLA_SUCCESS) 1771 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1772 "lip_reset failed (%d).\n", ret); 1773 } 1774 1775 /* Issue marker command only when we are going to start the I/O */ 1776 vha->marker_needed = 1; 1777 1778 return QLA_SUCCESS; 1779 } 1780 1781 /* 1782 * The caller must ensure that no completion interrupts will happen 1783 * while this function is in progress. 1784 */ 1785 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1786 unsigned long *flags) 1787 __releases(qp->qp_lock_ptr) 1788 __acquires(qp->qp_lock_ptr) 1789 { 1790 DECLARE_COMPLETION_ONSTACK(comp); 1791 scsi_qla_host_t *vha = qp->vha; 1792 struct qla_hw_data *ha = vha->hw; 1793 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1794 int rval; 1795 bool ret_cmd; 1796 uint32_t ratov_j; 1797 1798 lockdep_assert_held(qp->qp_lock_ptr); 1799 1800 if (qla2x00_chip_is_down(vha)) { 1801 sp->done(sp, res); 1802 return; 1803 } 1804 1805 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1806 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1807 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1808 !qla2x00_isp_reg_stat(ha))) { 1809 if (sp->comp) { 1810 sp->done(sp, res); 1811 return; 1812 } 1813 1814 sp->comp = ∁ 1815 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1816 1817 rval = ha->isp_ops->abort_command(sp); 1818 /* Wait for command completion. */ 1819 ret_cmd = false; 1820 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1821 ratov_j = msecs_to_jiffies(ratov_j); 1822 switch (rval) { 1823 case QLA_SUCCESS: 1824 if (wait_for_completion_timeout(&comp, ratov_j)) { 1825 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1826 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1827 __func__, ha->r_a_tov/10); 1828 ret_cmd = true; 1829 } 1830 /* else FW return SP to driver */ 1831 break; 1832 default: 1833 ret_cmd = true; 1834 break; 1835 } 1836 1837 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1838 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1839 sp->done(sp, res); 1840 } else { 1841 sp->done(sp, res); 1842 } 1843 } 1844 1845 /* 1846 * The caller must ensure that no completion interrupts will happen 1847 * while this function is in progress. 1848 */ 1849 static void 1850 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1851 { 1852 int cnt; 1853 unsigned long flags; 1854 srb_t *sp; 1855 scsi_qla_host_t *vha = qp->vha; 1856 struct qla_hw_data *ha = vha->hw; 1857 struct req_que *req; 1858 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1859 struct qla_tgt_cmd *cmd; 1860 1861 if (!ha->req_q_map) 1862 return; 1863 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1864 req = qp->req; 1865 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1866 sp = req->outstanding_cmds[cnt]; 1867 if (sp) { 1868 /* 1869 * perform lockless completion during driver unload 1870 */ 1871 if (qla2x00_chip_is_down(vha)) { 1872 req->outstanding_cmds[cnt] = NULL; 1873 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1874 sp->done(sp, res); 1875 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1876 continue; 1877 } 1878 1879 switch (sp->cmd_type) { 1880 case TYPE_SRB: 1881 qla2x00_abort_srb(qp, sp, res, &flags); 1882 break; 1883 case TYPE_TGT_CMD: 1884 if (!vha->hw->tgt.tgt_ops || !tgt || 1885 qla_ini_mode_enabled(vha)) { 1886 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1887 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1888 vha->dpc_flags); 1889 continue; 1890 } 1891 cmd = (struct qla_tgt_cmd *)sp; 1892 cmd->aborted = 1; 1893 break; 1894 case TYPE_TGT_TMCMD: 1895 /* Skip task management functions. */ 1896 break; 1897 default: 1898 break; 1899 } 1900 req->outstanding_cmds[cnt] = NULL; 1901 } 1902 } 1903 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1904 } 1905 1906 /* 1907 * The caller must ensure that no completion interrupts will happen 1908 * while this function is in progress. 1909 */ 1910 void 1911 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1912 { 1913 int que; 1914 struct qla_hw_data *ha = vha->hw; 1915 1916 /* Continue only if initialization complete. */ 1917 if (!ha->base_qpair) 1918 return; 1919 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1920 1921 if (!ha->queue_pair_map) 1922 return; 1923 for (que = 0; que < ha->max_qpairs; que++) { 1924 if (!ha->queue_pair_map[que]) 1925 continue; 1926 1927 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1928 } 1929 } 1930 1931 static int 1932 qla2xxx_slave_alloc(struct scsi_device *sdev) 1933 { 1934 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1935 1936 if (!rport || fc_remote_port_chkready(rport)) 1937 return -ENXIO; 1938 1939 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1940 1941 return 0; 1942 } 1943 1944 static int 1945 qla2xxx_slave_configure(struct scsi_device *sdev) 1946 { 1947 scsi_qla_host_t *vha = shost_priv(sdev->host); 1948 struct req_que *req = vha->req; 1949 1950 if (IS_T10_PI_CAPABLE(vha->hw)) 1951 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1952 1953 scsi_change_queue_depth(sdev, req->max_q_depth); 1954 return 0; 1955 } 1956 1957 static void 1958 qla2xxx_slave_destroy(struct scsi_device *sdev) 1959 { 1960 sdev->hostdata = NULL; 1961 } 1962 1963 /** 1964 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1965 * @ha: HA context 1966 * 1967 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1968 * supported addressing method. 1969 */ 1970 static void 1971 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1972 { 1973 /* Assume a 32bit DMA mask. */ 1974 ha->flags.enable_64bit_addressing = 0; 1975 1976 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1977 /* Any upper-dword bits set? */ 1978 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1979 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1980 /* Ok, a 64bit DMA mask is applicable. */ 1981 ha->flags.enable_64bit_addressing = 1; 1982 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1983 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1984 return; 1985 } 1986 } 1987 1988 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1989 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1990 } 1991 1992 static void 1993 qla2x00_enable_intrs(struct qla_hw_data *ha) 1994 { 1995 unsigned long flags = 0; 1996 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1997 1998 spin_lock_irqsave(&ha->hardware_lock, flags); 1999 ha->interrupts_on = 1; 2000 /* enable risc and host interrupts */ 2001 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 2002 rd_reg_word(®->ictrl); 2003 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2004 2005 } 2006 2007 static void 2008 qla2x00_disable_intrs(struct qla_hw_data *ha) 2009 { 2010 unsigned long flags = 0; 2011 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2012 2013 spin_lock_irqsave(&ha->hardware_lock, flags); 2014 ha->interrupts_on = 0; 2015 /* disable risc and host interrupts */ 2016 wrt_reg_word(®->ictrl, 0); 2017 rd_reg_word(®->ictrl); 2018 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2019 } 2020 2021 static void 2022 qla24xx_enable_intrs(struct qla_hw_data *ha) 2023 { 2024 unsigned long flags = 0; 2025 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2026 2027 spin_lock_irqsave(&ha->hardware_lock, flags); 2028 ha->interrupts_on = 1; 2029 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 2030 rd_reg_dword(®->ictrl); 2031 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2032 } 2033 2034 static void 2035 qla24xx_disable_intrs(struct qla_hw_data *ha) 2036 { 2037 unsigned long flags = 0; 2038 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2039 2040 if (IS_NOPOLLING_TYPE(ha)) 2041 return; 2042 spin_lock_irqsave(&ha->hardware_lock, flags); 2043 ha->interrupts_on = 0; 2044 wrt_reg_dword(®->ictrl, 0); 2045 rd_reg_dword(®->ictrl); 2046 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2047 } 2048 2049 static int 2050 qla2x00_iospace_config(struct qla_hw_data *ha) 2051 { 2052 resource_size_t pio; 2053 uint16_t msix; 2054 2055 if (pci_request_selected_regions(ha->pdev, ha->bars, 2056 QLA2XXX_DRIVER_NAME)) { 2057 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2058 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2059 pci_name(ha->pdev)); 2060 goto iospace_error_exit; 2061 } 2062 if (!(ha->bars & 1)) 2063 goto skip_pio; 2064 2065 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2066 pio = pci_resource_start(ha->pdev, 0); 2067 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2068 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2069 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2070 "Invalid pci I/O region size (%s).\n", 2071 pci_name(ha->pdev)); 2072 pio = 0; 2073 } 2074 } else { 2075 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2076 "Region #0 no a PIO resource (%s).\n", 2077 pci_name(ha->pdev)); 2078 pio = 0; 2079 } 2080 ha->pio_address = pio; 2081 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2082 "PIO address=%llu.\n", 2083 (unsigned long long)ha->pio_address); 2084 2085 skip_pio: 2086 /* Use MMIO operations for all accesses. */ 2087 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2088 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2089 "Region #1 not an MMIO resource (%s), aborting.\n", 2090 pci_name(ha->pdev)); 2091 goto iospace_error_exit; 2092 } 2093 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2094 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2095 "Invalid PCI mem region size (%s), aborting.\n", 2096 pci_name(ha->pdev)); 2097 goto iospace_error_exit; 2098 } 2099 2100 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2101 if (!ha->iobase) { 2102 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2103 "Cannot remap MMIO (%s), aborting.\n", 2104 pci_name(ha->pdev)); 2105 goto iospace_error_exit; 2106 } 2107 2108 /* Determine queue resources */ 2109 ha->max_req_queues = ha->max_rsp_queues = 1; 2110 ha->msix_count = QLA_BASE_VECTORS; 2111 2112 /* Check if FW supports MQ or not */ 2113 if (!(ha->fw_attributes & BIT_6)) 2114 goto mqiobase_exit; 2115 2116 if (!ql2xmqsupport || !ql2xnvmeenable || 2117 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2118 goto mqiobase_exit; 2119 2120 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2121 pci_resource_len(ha->pdev, 3)); 2122 if (ha->mqiobase) { 2123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2124 "MQIO Base=%p.\n", ha->mqiobase); 2125 /* Read MSIX vector size of the board */ 2126 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2127 ha->msix_count = msix + 1; 2128 /* Max queues are bounded by available msix vectors */ 2129 /* MB interrupt uses 1 vector */ 2130 ha->max_req_queues = ha->msix_count - 1; 2131 ha->max_rsp_queues = ha->max_req_queues; 2132 /* Queue pairs is the max value minus the base queue pair */ 2133 ha->max_qpairs = ha->max_rsp_queues - 1; 2134 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2135 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2136 2137 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2138 "MSI-X vector count: %d.\n", ha->msix_count); 2139 } else 2140 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2141 "BAR 3 not enabled.\n"); 2142 2143 mqiobase_exit: 2144 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2145 "MSIX Count: %d.\n", ha->msix_count); 2146 return (0); 2147 2148 iospace_error_exit: 2149 return (-ENOMEM); 2150 } 2151 2152 2153 static int 2154 qla83xx_iospace_config(struct qla_hw_data *ha) 2155 { 2156 uint16_t msix; 2157 2158 if (pci_request_selected_regions(ha->pdev, ha->bars, 2159 QLA2XXX_DRIVER_NAME)) { 2160 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2161 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2162 pci_name(ha->pdev)); 2163 2164 goto iospace_error_exit; 2165 } 2166 2167 /* Use MMIO operations for all accesses. */ 2168 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2169 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2170 "Invalid pci I/O region size (%s).\n", 2171 pci_name(ha->pdev)); 2172 goto iospace_error_exit; 2173 } 2174 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2175 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2176 "Invalid PCI mem region size (%s), aborting\n", 2177 pci_name(ha->pdev)); 2178 goto iospace_error_exit; 2179 } 2180 2181 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2182 if (!ha->iobase) { 2183 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2184 "Cannot remap MMIO (%s), aborting.\n", 2185 pci_name(ha->pdev)); 2186 goto iospace_error_exit; 2187 } 2188 2189 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2190 /* 83XX 26XX always use MQ type access for queues 2191 * - mbar 2, a.k.a region 4 */ 2192 ha->max_req_queues = ha->max_rsp_queues = 1; 2193 ha->msix_count = QLA_BASE_VECTORS; 2194 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2195 pci_resource_len(ha->pdev, 4)); 2196 2197 if (!ha->mqiobase) { 2198 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2199 "BAR2/region4 not enabled\n"); 2200 goto mqiobase_exit; 2201 } 2202 2203 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2204 pci_resource_len(ha->pdev, 2)); 2205 if (ha->msixbase) { 2206 /* Read MSIX vector size of the board */ 2207 pci_read_config_word(ha->pdev, 2208 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2209 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2210 /* 2211 * By default, driver uses at least two msix vectors 2212 * (default & rspq) 2213 */ 2214 if (ql2xmqsupport || ql2xnvmeenable) { 2215 /* MB interrupt uses 1 vector */ 2216 ha->max_req_queues = ha->msix_count - 1; 2217 2218 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2219 if (QLA_TGT_MODE_ENABLED()) 2220 ha->max_req_queues--; 2221 2222 ha->max_rsp_queues = ha->max_req_queues; 2223 2224 /* Queue pairs is the max value minus 2225 * the base queue pair */ 2226 ha->max_qpairs = ha->max_req_queues - 1; 2227 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2228 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2229 } 2230 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2231 "MSI-X vector count: %d.\n", ha->msix_count); 2232 } else 2233 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2234 "BAR 1 not enabled.\n"); 2235 2236 mqiobase_exit: 2237 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2238 "MSIX Count: %d.\n", ha->msix_count); 2239 return 0; 2240 2241 iospace_error_exit: 2242 return -ENOMEM; 2243 } 2244 2245 static struct isp_operations qla2100_isp_ops = { 2246 .pci_config = qla2100_pci_config, 2247 .reset_chip = qla2x00_reset_chip, 2248 .chip_diag = qla2x00_chip_diag, 2249 .config_rings = qla2x00_config_rings, 2250 .reset_adapter = qla2x00_reset_adapter, 2251 .nvram_config = qla2x00_nvram_config, 2252 .update_fw_options = qla2x00_update_fw_options, 2253 .load_risc = qla2x00_load_risc, 2254 .pci_info_str = qla2x00_pci_info_str, 2255 .fw_version_str = qla2x00_fw_version_str, 2256 .intr_handler = qla2100_intr_handler, 2257 .enable_intrs = qla2x00_enable_intrs, 2258 .disable_intrs = qla2x00_disable_intrs, 2259 .abort_command = qla2x00_abort_command, 2260 .target_reset = qla2x00_abort_target, 2261 .lun_reset = qla2x00_lun_reset, 2262 .fabric_login = qla2x00_login_fabric, 2263 .fabric_logout = qla2x00_fabric_logout, 2264 .calc_req_entries = qla2x00_calc_iocbs_32, 2265 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2266 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2267 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2268 .read_nvram = qla2x00_read_nvram_data, 2269 .write_nvram = qla2x00_write_nvram_data, 2270 .fw_dump = qla2100_fw_dump, 2271 .beacon_on = NULL, 2272 .beacon_off = NULL, 2273 .beacon_blink = NULL, 2274 .read_optrom = qla2x00_read_optrom_data, 2275 .write_optrom = qla2x00_write_optrom_data, 2276 .get_flash_version = qla2x00_get_flash_version, 2277 .start_scsi = qla2x00_start_scsi, 2278 .start_scsi_mq = NULL, 2279 .abort_isp = qla2x00_abort_isp, 2280 .iospace_config = qla2x00_iospace_config, 2281 .initialize_adapter = qla2x00_initialize_adapter, 2282 }; 2283 2284 static struct isp_operations qla2300_isp_ops = { 2285 .pci_config = qla2300_pci_config, 2286 .reset_chip = qla2x00_reset_chip, 2287 .chip_diag = qla2x00_chip_diag, 2288 .config_rings = qla2x00_config_rings, 2289 .reset_adapter = qla2x00_reset_adapter, 2290 .nvram_config = qla2x00_nvram_config, 2291 .update_fw_options = qla2x00_update_fw_options, 2292 .load_risc = qla2x00_load_risc, 2293 .pci_info_str = qla2x00_pci_info_str, 2294 .fw_version_str = qla2x00_fw_version_str, 2295 .intr_handler = qla2300_intr_handler, 2296 .enable_intrs = qla2x00_enable_intrs, 2297 .disable_intrs = qla2x00_disable_intrs, 2298 .abort_command = qla2x00_abort_command, 2299 .target_reset = qla2x00_abort_target, 2300 .lun_reset = qla2x00_lun_reset, 2301 .fabric_login = qla2x00_login_fabric, 2302 .fabric_logout = qla2x00_fabric_logout, 2303 .calc_req_entries = qla2x00_calc_iocbs_32, 2304 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2305 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2306 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2307 .read_nvram = qla2x00_read_nvram_data, 2308 .write_nvram = qla2x00_write_nvram_data, 2309 .fw_dump = qla2300_fw_dump, 2310 .beacon_on = qla2x00_beacon_on, 2311 .beacon_off = qla2x00_beacon_off, 2312 .beacon_blink = qla2x00_beacon_blink, 2313 .read_optrom = qla2x00_read_optrom_data, 2314 .write_optrom = qla2x00_write_optrom_data, 2315 .get_flash_version = qla2x00_get_flash_version, 2316 .start_scsi = qla2x00_start_scsi, 2317 .start_scsi_mq = NULL, 2318 .abort_isp = qla2x00_abort_isp, 2319 .iospace_config = qla2x00_iospace_config, 2320 .initialize_adapter = qla2x00_initialize_adapter, 2321 }; 2322 2323 static struct isp_operations qla24xx_isp_ops = { 2324 .pci_config = qla24xx_pci_config, 2325 .reset_chip = qla24xx_reset_chip, 2326 .chip_diag = qla24xx_chip_diag, 2327 .config_rings = qla24xx_config_rings, 2328 .reset_adapter = qla24xx_reset_adapter, 2329 .nvram_config = qla24xx_nvram_config, 2330 .update_fw_options = qla24xx_update_fw_options, 2331 .load_risc = qla24xx_load_risc, 2332 .pci_info_str = qla24xx_pci_info_str, 2333 .fw_version_str = qla24xx_fw_version_str, 2334 .intr_handler = qla24xx_intr_handler, 2335 .enable_intrs = qla24xx_enable_intrs, 2336 .disable_intrs = qla24xx_disable_intrs, 2337 .abort_command = qla24xx_abort_command, 2338 .target_reset = qla24xx_abort_target, 2339 .lun_reset = qla24xx_lun_reset, 2340 .fabric_login = qla24xx_login_fabric, 2341 .fabric_logout = qla24xx_fabric_logout, 2342 .calc_req_entries = NULL, 2343 .build_iocbs = NULL, 2344 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2345 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2346 .read_nvram = qla24xx_read_nvram_data, 2347 .write_nvram = qla24xx_write_nvram_data, 2348 .fw_dump = qla24xx_fw_dump, 2349 .beacon_on = qla24xx_beacon_on, 2350 .beacon_off = qla24xx_beacon_off, 2351 .beacon_blink = qla24xx_beacon_blink, 2352 .read_optrom = qla24xx_read_optrom_data, 2353 .write_optrom = qla24xx_write_optrom_data, 2354 .get_flash_version = qla24xx_get_flash_version, 2355 .start_scsi = qla24xx_start_scsi, 2356 .start_scsi_mq = NULL, 2357 .abort_isp = qla2x00_abort_isp, 2358 .iospace_config = qla2x00_iospace_config, 2359 .initialize_adapter = qla2x00_initialize_adapter, 2360 }; 2361 2362 static struct isp_operations qla25xx_isp_ops = { 2363 .pci_config = qla25xx_pci_config, 2364 .reset_chip = qla24xx_reset_chip, 2365 .chip_diag = qla24xx_chip_diag, 2366 .config_rings = qla24xx_config_rings, 2367 .reset_adapter = qla24xx_reset_adapter, 2368 .nvram_config = qla24xx_nvram_config, 2369 .update_fw_options = qla24xx_update_fw_options, 2370 .load_risc = qla24xx_load_risc, 2371 .pci_info_str = qla24xx_pci_info_str, 2372 .fw_version_str = qla24xx_fw_version_str, 2373 .intr_handler = qla24xx_intr_handler, 2374 .enable_intrs = qla24xx_enable_intrs, 2375 .disable_intrs = qla24xx_disable_intrs, 2376 .abort_command = qla24xx_abort_command, 2377 .target_reset = qla24xx_abort_target, 2378 .lun_reset = qla24xx_lun_reset, 2379 .fabric_login = qla24xx_login_fabric, 2380 .fabric_logout = qla24xx_fabric_logout, 2381 .calc_req_entries = NULL, 2382 .build_iocbs = NULL, 2383 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2384 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2385 .read_nvram = qla25xx_read_nvram_data, 2386 .write_nvram = qla25xx_write_nvram_data, 2387 .fw_dump = qla25xx_fw_dump, 2388 .beacon_on = qla24xx_beacon_on, 2389 .beacon_off = qla24xx_beacon_off, 2390 .beacon_blink = qla24xx_beacon_blink, 2391 .read_optrom = qla25xx_read_optrom_data, 2392 .write_optrom = qla24xx_write_optrom_data, 2393 .get_flash_version = qla24xx_get_flash_version, 2394 .start_scsi = qla24xx_dif_start_scsi, 2395 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2396 .abort_isp = qla2x00_abort_isp, 2397 .iospace_config = qla2x00_iospace_config, 2398 .initialize_adapter = qla2x00_initialize_adapter, 2399 }; 2400 2401 static struct isp_operations qla81xx_isp_ops = { 2402 .pci_config = qla25xx_pci_config, 2403 .reset_chip = qla24xx_reset_chip, 2404 .chip_diag = qla24xx_chip_diag, 2405 .config_rings = qla24xx_config_rings, 2406 .reset_adapter = qla24xx_reset_adapter, 2407 .nvram_config = qla81xx_nvram_config, 2408 .update_fw_options = qla24xx_update_fw_options, 2409 .load_risc = qla81xx_load_risc, 2410 .pci_info_str = qla24xx_pci_info_str, 2411 .fw_version_str = qla24xx_fw_version_str, 2412 .intr_handler = qla24xx_intr_handler, 2413 .enable_intrs = qla24xx_enable_intrs, 2414 .disable_intrs = qla24xx_disable_intrs, 2415 .abort_command = qla24xx_abort_command, 2416 .target_reset = qla24xx_abort_target, 2417 .lun_reset = qla24xx_lun_reset, 2418 .fabric_login = qla24xx_login_fabric, 2419 .fabric_logout = qla24xx_fabric_logout, 2420 .calc_req_entries = NULL, 2421 .build_iocbs = NULL, 2422 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2423 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2424 .read_nvram = NULL, 2425 .write_nvram = NULL, 2426 .fw_dump = qla81xx_fw_dump, 2427 .beacon_on = qla24xx_beacon_on, 2428 .beacon_off = qla24xx_beacon_off, 2429 .beacon_blink = qla83xx_beacon_blink, 2430 .read_optrom = qla25xx_read_optrom_data, 2431 .write_optrom = qla24xx_write_optrom_data, 2432 .get_flash_version = qla24xx_get_flash_version, 2433 .start_scsi = qla24xx_dif_start_scsi, 2434 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2435 .abort_isp = qla2x00_abort_isp, 2436 .iospace_config = qla2x00_iospace_config, 2437 .initialize_adapter = qla2x00_initialize_adapter, 2438 }; 2439 2440 static struct isp_operations qla82xx_isp_ops = { 2441 .pci_config = qla82xx_pci_config, 2442 .reset_chip = qla82xx_reset_chip, 2443 .chip_diag = qla24xx_chip_diag, 2444 .config_rings = qla82xx_config_rings, 2445 .reset_adapter = qla24xx_reset_adapter, 2446 .nvram_config = qla81xx_nvram_config, 2447 .update_fw_options = qla24xx_update_fw_options, 2448 .load_risc = qla82xx_load_risc, 2449 .pci_info_str = qla24xx_pci_info_str, 2450 .fw_version_str = qla24xx_fw_version_str, 2451 .intr_handler = qla82xx_intr_handler, 2452 .enable_intrs = qla82xx_enable_intrs, 2453 .disable_intrs = qla82xx_disable_intrs, 2454 .abort_command = qla24xx_abort_command, 2455 .target_reset = qla24xx_abort_target, 2456 .lun_reset = qla24xx_lun_reset, 2457 .fabric_login = qla24xx_login_fabric, 2458 .fabric_logout = qla24xx_fabric_logout, 2459 .calc_req_entries = NULL, 2460 .build_iocbs = NULL, 2461 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2462 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2463 .read_nvram = qla24xx_read_nvram_data, 2464 .write_nvram = qla24xx_write_nvram_data, 2465 .fw_dump = qla82xx_fw_dump, 2466 .beacon_on = qla82xx_beacon_on, 2467 .beacon_off = qla82xx_beacon_off, 2468 .beacon_blink = NULL, 2469 .read_optrom = qla82xx_read_optrom_data, 2470 .write_optrom = qla82xx_write_optrom_data, 2471 .get_flash_version = qla82xx_get_flash_version, 2472 .start_scsi = qla82xx_start_scsi, 2473 .start_scsi_mq = NULL, 2474 .abort_isp = qla82xx_abort_isp, 2475 .iospace_config = qla82xx_iospace_config, 2476 .initialize_adapter = qla2x00_initialize_adapter, 2477 }; 2478 2479 static struct isp_operations qla8044_isp_ops = { 2480 .pci_config = qla82xx_pci_config, 2481 .reset_chip = qla82xx_reset_chip, 2482 .chip_diag = qla24xx_chip_diag, 2483 .config_rings = qla82xx_config_rings, 2484 .reset_adapter = qla24xx_reset_adapter, 2485 .nvram_config = qla81xx_nvram_config, 2486 .update_fw_options = qla24xx_update_fw_options, 2487 .load_risc = qla82xx_load_risc, 2488 .pci_info_str = qla24xx_pci_info_str, 2489 .fw_version_str = qla24xx_fw_version_str, 2490 .intr_handler = qla8044_intr_handler, 2491 .enable_intrs = qla82xx_enable_intrs, 2492 .disable_intrs = qla82xx_disable_intrs, 2493 .abort_command = qla24xx_abort_command, 2494 .target_reset = qla24xx_abort_target, 2495 .lun_reset = qla24xx_lun_reset, 2496 .fabric_login = qla24xx_login_fabric, 2497 .fabric_logout = qla24xx_fabric_logout, 2498 .calc_req_entries = NULL, 2499 .build_iocbs = NULL, 2500 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2501 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2502 .read_nvram = NULL, 2503 .write_nvram = NULL, 2504 .fw_dump = qla8044_fw_dump, 2505 .beacon_on = qla82xx_beacon_on, 2506 .beacon_off = qla82xx_beacon_off, 2507 .beacon_blink = NULL, 2508 .read_optrom = qla8044_read_optrom_data, 2509 .write_optrom = qla8044_write_optrom_data, 2510 .get_flash_version = qla82xx_get_flash_version, 2511 .start_scsi = qla82xx_start_scsi, 2512 .start_scsi_mq = NULL, 2513 .abort_isp = qla8044_abort_isp, 2514 .iospace_config = qla82xx_iospace_config, 2515 .initialize_adapter = qla2x00_initialize_adapter, 2516 }; 2517 2518 static struct isp_operations qla83xx_isp_ops = { 2519 .pci_config = qla25xx_pci_config, 2520 .reset_chip = qla24xx_reset_chip, 2521 .chip_diag = qla24xx_chip_diag, 2522 .config_rings = qla24xx_config_rings, 2523 .reset_adapter = qla24xx_reset_adapter, 2524 .nvram_config = qla81xx_nvram_config, 2525 .update_fw_options = qla24xx_update_fw_options, 2526 .load_risc = qla81xx_load_risc, 2527 .pci_info_str = qla24xx_pci_info_str, 2528 .fw_version_str = qla24xx_fw_version_str, 2529 .intr_handler = qla24xx_intr_handler, 2530 .enable_intrs = qla24xx_enable_intrs, 2531 .disable_intrs = qla24xx_disable_intrs, 2532 .abort_command = qla24xx_abort_command, 2533 .target_reset = qla24xx_abort_target, 2534 .lun_reset = qla24xx_lun_reset, 2535 .fabric_login = qla24xx_login_fabric, 2536 .fabric_logout = qla24xx_fabric_logout, 2537 .calc_req_entries = NULL, 2538 .build_iocbs = NULL, 2539 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2540 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2541 .read_nvram = NULL, 2542 .write_nvram = NULL, 2543 .fw_dump = qla83xx_fw_dump, 2544 .beacon_on = qla24xx_beacon_on, 2545 .beacon_off = qla24xx_beacon_off, 2546 .beacon_blink = qla83xx_beacon_blink, 2547 .read_optrom = qla25xx_read_optrom_data, 2548 .write_optrom = qla24xx_write_optrom_data, 2549 .get_flash_version = qla24xx_get_flash_version, 2550 .start_scsi = qla24xx_dif_start_scsi, 2551 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2552 .abort_isp = qla2x00_abort_isp, 2553 .iospace_config = qla83xx_iospace_config, 2554 .initialize_adapter = qla2x00_initialize_adapter, 2555 }; 2556 2557 static struct isp_operations qlafx00_isp_ops = { 2558 .pci_config = qlafx00_pci_config, 2559 .reset_chip = qlafx00_soft_reset, 2560 .chip_diag = qlafx00_chip_diag, 2561 .config_rings = qlafx00_config_rings, 2562 .reset_adapter = qlafx00_soft_reset, 2563 .nvram_config = NULL, 2564 .update_fw_options = NULL, 2565 .load_risc = NULL, 2566 .pci_info_str = qlafx00_pci_info_str, 2567 .fw_version_str = qlafx00_fw_version_str, 2568 .intr_handler = qlafx00_intr_handler, 2569 .enable_intrs = qlafx00_enable_intrs, 2570 .disable_intrs = qlafx00_disable_intrs, 2571 .abort_command = qla24xx_async_abort_command, 2572 .target_reset = qlafx00_abort_target, 2573 .lun_reset = qlafx00_lun_reset, 2574 .fabric_login = NULL, 2575 .fabric_logout = NULL, 2576 .calc_req_entries = NULL, 2577 .build_iocbs = NULL, 2578 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2579 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2580 .read_nvram = qla24xx_read_nvram_data, 2581 .write_nvram = qla24xx_write_nvram_data, 2582 .fw_dump = NULL, 2583 .beacon_on = qla24xx_beacon_on, 2584 .beacon_off = qla24xx_beacon_off, 2585 .beacon_blink = NULL, 2586 .read_optrom = qla24xx_read_optrom_data, 2587 .write_optrom = qla24xx_write_optrom_data, 2588 .get_flash_version = qla24xx_get_flash_version, 2589 .start_scsi = qlafx00_start_scsi, 2590 .start_scsi_mq = NULL, 2591 .abort_isp = qlafx00_abort_isp, 2592 .iospace_config = qlafx00_iospace_config, 2593 .initialize_adapter = qlafx00_initialize_adapter, 2594 }; 2595 2596 static struct isp_operations qla27xx_isp_ops = { 2597 .pci_config = qla25xx_pci_config, 2598 .reset_chip = qla24xx_reset_chip, 2599 .chip_diag = qla24xx_chip_diag, 2600 .config_rings = qla24xx_config_rings, 2601 .reset_adapter = qla24xx_reset_adapter, 2602 .nvram_config = qla81xx_nvram_config, 2603 .update_fw_options = qla24xx_update_fw_options, 2604 .load_risc = qla81xx_load_risc, 2605 .pci_info_str = qla24xx_pci_info_str, 2606 .fw_version_str = qla24xx_fw_version_str, 2607 .intr_handler = qla24xx_intr_handler, 2608 .enable_intrs = qla24xx_enable_intrs, 2609 .disable_intrs = qla24xx_disable_intrs, 2610 .abort_command = qla24xx_abort_command, 2611 .target_reset = qla24xx_abort_target, 2612 .lun_reset = qla24xx_lun_reset, 2613 .fabric_login = qla24xx_login_fabric, 2614 .fabric_logout = qla24xx_fabric_logout, 2615 .calc_req_entries = NULL, 2616 .build_iocbs = NULL, 2617 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2618 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2619 .read_nvram = NULL, 2620 .write_nvram = NULL, 2621 .fw_dump = qla27xx_fwdump, 2622 .mpi_fw_dump = qla27xx_mpi_fwdump, 2623 .beacon_on = qla24xx_beacon_on, 2624 .beacon_off = qla24xx_beacon_off, 2625 .beacon_blink = qla83xx_beacon_blink, 2626 .read_optrom = qla25xx_read_optrom_data, 2627 .write_optrom = qla24xx_write_optrom_data, 2628 .get_flash_version = qla24xx_get_flash_version, 2629 .start_scsi = qla24xx_dif_start_scsi, 2630 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2631 .abort_isp = qla2x00_abort_isp, 2632 .iospace_config = qla83xx_iospace_config, 2633 .initialize_adapter = qla2x00_initialize_adapter, 2634 }; 2635 2636 static inline void 2637 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2638 { 2639 ha->device_type = DT_EXTENDED_IDS; 2640 switch (ha->pdev->device) { 2641 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2642 ha->isp_type |= DT_ISP2100; 2643 ha->device_type &= ~DT_EXTENDED_IDS; 2644 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2645 break; 2646 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2647 ha->isp_type |= DT_ISP2200; 2648 ha->device_type &= ~DT_EXTENDED_IDS; 2649 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2650 break; 2651 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2652 ha->isp_type |= DT_ISP2300; 2653 ha->device_type |= DT_ZIO_SUPPORTED; 2654 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2655 break; 2656 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2657 ha->isp_type |= DT_ISP2312; 2658 ha->device_type |= DT_ZIO_SUPPORTED; 2659 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2660 break; 2661 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2662 ha->isp_type |= DT_ISP2322; 2663 ha->device_type |= DT_ZIO_SUPPORTED; 2664 if (ha->pdev->subsystem_vendor == 0x1028 && 2665 ha->pdev->subsystem_device == 0x0170) 2666 ha->device_type |= DT_OEM_001; 2667 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2668 break; 2669 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2670 ha->isp_type |= DT_ISP6312; 2671 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2672 break; 2673 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2674 ha->isp_type |= DT_ISP6322; 2675 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2676 break; 2677 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2678 ha->isp_type |= DT_ISP2422; 2679 ha->device_type |= DT_ZIO_SUPPORTED; 2680 ha->device_type |= DT_FWI2; 2681 ha->device_type |= DT_IIDMA; 2682 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2683 break; 2684 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2685 ha->isp_type |= DT_ISP2432; 2686 ha->device_type |= DT_ZIO_SUPPORTED; 2687 ha->device_type |= DT_FWI2; 2688 ha->device_type |= DT_IIDMA; 2689 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2690 break; 2691 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2692 ha->isp_type |= DT_ISP8432; 2693 ha->device_type |= DT_ZIO_SUPPORTED; 2694 ha->device_type |= DT_FWI2; 2695 ha->device_type |= DT_IIDMA; 2696 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2697 break; 2698 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2699 ha->isp_type |= DT_ISP5422; 2700 ha->device_type |= DT_FWI2; 2701 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2702 break; 2703 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2704 ha->isp_type |= DT_ISP5432; 2705 ha->device_type |= DT_FWI2; 2706 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2707 break; 2708 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2709 ha->isp_type |= DT_ISP2532; 2710 ha->device_type |= DT_ZIO_SUPPORTED; 2711 ha->device_type |= DT_FWI2; 2712 ha->device_type |= DT_IIDMA; 2713 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2714 break; 2715 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2716 ha->isp_type |= DT_ISP8001; 2717 ha->device_type |= DT_ZIO_SUPPORTED; 2718 ha->device_type |= DT_FWI2; 2719 ha->device_type |= DT_IIDMA; 2720 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2721 break; 2722 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2723 ha->isp_type |= DT_ISP8021; 2724 ha->device_type |= DT_ZIO_SUPPORTED; 2725 ha->device_type |= DT_FWI2; 2726 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2727 /* Initialize 82XX ISP flags */ 2728 qla82xx_init_flags(ha); 2729 break; 2730 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2731 ha->isp_type |= DT_ISP8044; 2732 ha->device_type |= DT_ZIO_SUPPORTED; 2733 ha->device_type |= DT_FWI2; 2734 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2735 /* Initialize 82XX ISP flags */ 2736 qla82xx_init_flags(ha); 2737 break; 2738 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2739 ha->isp_type |= DT_ISP2031; 2740 ha->device_type |= DT_ZIO_SUPPORTED; 2741 ha->device_type |= DT_FWI2; 2742 ha->device_type |= DT_IIDMA; 2743 ha->device_type |= DT_T10_PI; 2744 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2745 break; 2746 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2747 ha->isp_type |= DT_ISP8031; 2748 ha->device_type |= DT_ZIO_SUPPORTED; 2749 ha->device_type |= DT_FWI2; 2750 ha->device_type |= DT_IIDMA; 2751 ha->device_type |= DT_T10_PI; 2752 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2753 break; 2754 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2755 ha->isp_type |= DT_ISPFX00; 2756 break; 2757 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2758 ha->isp_type |= DT_ISP2071; 2759 ha->device_type |= DT_ZIO_SUPPORTED; 2760 ha->device_type |= DT_FWI2; 2761 ha->device_type |= DT_IIDMA; 2762 ha->device_type |= DT_T10_PI; 2763 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2764 break; 2765 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2766 ha->isp_type |= DT_ISP2271; 2767 ha->device_type |= DT_ZIO_SUPPORTED; 2768 ha->device_type |= DT_FWI2; 2769 ha->device_type |= DT_IIDMA; 2770 ha->device_type |= DT_T10_PI; 2771 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2772 break; 2773 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2774 ha->isp_type |= DT_ISP2261; 2775 ha->device_type |= DT_ZIO_SUPPORTED; 2776 ha->device_type |= DT_FWI2; 2777 ha->device_type |= DT_IIDMA; 2778 ha->device_type |= DT_T10_PI; 2779 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2780 break; 2781 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2782 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2783 ha->isp_type |= DT_ISP2081; 2784 ha->device_type |= DT_ZIO_SUPPORTED; 2785 ha->device_type |= DT_FWI2; 2786 ha->device_type |= DT_IIDMA; 2787 ha->device_type |= DT_T10_PI; 2788 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2789 break; 2790 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2791 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2792 ha->isp_type |= DT_ISP2281; 2793 ha->device_type |= DT_ZIO_SUPPORTED; 2794 ha->device_type |= DT_FWI2; 2795 ha->device_type |= DT_IIDMA; 2796 ha->device_type |= DT_T10_PI; 2797 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2798 break; 2799 } 2800 2801 if (IS_QLA82XX(ha)) 2802 ha->port_no = ha->portnum & 1; 2803 else { 2804 /* Get adapter physical port no from interrupt pin register. */ 2805 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2806 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2807 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2808 ha->port_no--; 2809 else 2810 ha->port_no = !(ha->port_no & 1); 2811 } 2812 2813 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2814 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2815 ha->device_type, ha->port_no, ha->fw_srisc_address); 2816 } 2817 2818 static void 2819 qla2xxx_scan_start(struct Scsi_Host *shost) 2820 { 2821 scsi_qla_host_t *vha = shost_priv(shost); 2822 2823 if (vha->hw->flags.running_gold_fw) 2824 return; 2825 2826 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2827 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2828 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2829 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2830 } 2831 2832 static int 2833 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2834 { 2835 scsi_qla_host_t *vha = shost_priv(shost); 2836 2837 if (test_bit(UNLOADING, &vha->dpc_flags)) 2838 return 1; 2839 if (!vha->host) 2840 return 1; 2841 if (time > vha->hw->loop_reset_delay * HZ) 2842 return 1; 2843 2844 return atomic_read(&vha->loop_state) == LOOP_READY; 2845 } 2846 2847 static void qla_heartbeat_work_fn(struct work_struct *work) 2848 { 2849 struct qla_hw_data *ha = container_of(work, 2850 struct qla_hw_data, heartbeat_work); 2851 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2852 2853 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2854 qla_no_op_mb(base_vha); 2855 } 2856 2857 static void qla2x00_iocb_work_fn(struct work_struct *work) 2858 { 2859 struct scsi_qla_host *vha = container_of(work, 2860 struct scsi_qla_host, iocb_work); 2861 struct qla_hw_data *ha = vha->hw; 2862 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2863 int i = 2; 2864 unsigned long flags; 2865 2866 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2867 return; 2868 2869 while (!list_empty(&vha->work_list) && i > 0) { 2870 qla2x00_do_work(vha); 2871 i--; 2872 } 2873 2874 spin_lock_irqsave(&vha->work_lock, flags); 2875 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2876 spin_unlock_irqrestore(&vha->work_lock, flags); 2877 } 2878 2879 static void 2880 qla_trace_init(void) 2881 { 2882 qla_trc_array = trace_array_get_by_name("qla2xxx"); 2883 if (!qla_trc_array) { 2884 ql_log(ql_log_fatal, NULL, 0x0001, 2885 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n"); 2886 return; 2887 } 2888 2889 QLA_TRACE_ENABLE(qla_trc_array); 2890 } 2891 2892 static void 2893 qla_trace_uninit(void) 2894 { 2895 if (!qla_trc_array) 2896 return; 2897 trace_array_put(qla_trc_array); 2898 } 2899 2900 /* 2901 * PCI driver interface 2902 */ 2903 static int 2904 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2905 { 2906 int ret = -ENODEV; 2907 struct Scsi_Host *host; 2908 scsi_qla_host_t *base_vha = NULL; 2909 struct qla_hw_data *ha; 2910 char pci_info[30]; 2911 char fw_str[30], wq_name[30]; 2912 struct scsi_host_template *sht; 2913 int bars, mem_only = 0; 2914 uint16_t req_length = 0, rsp_length = 0; 2915 struct req_que *req = NULL; 2916 struct rsp_que *rsp = NULL; 2917 int i; 2918 2919 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2920 sht = &qla2xxx_driver_template; 2921 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2922 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2929 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2930 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2938 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2939 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2940 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2941 mem_only = 1; 2942 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2943 "Mem only adapter.\n"); 2944 } 2945 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2946 "Bars=%d.\n", bars); 2947 2948 if (mem_only) { 2949 if (pci_enable_device_mem(pdev)) 2950 return ret; 2951 } else { 2952 if (pci_enable_device(pdev)) 2953 return ret; 2954 } 2955 2956 if (is_kdump_kernel()) { 2957 ql2xmqsupport = 0; 2958 ql2xallocfwdump = 0; 2959 } 2960 2961 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2962 if (!ha) { 2963 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2964 "Unable to allocate memory for ha.\n"); 2965 goto disable_device; 2966 } 2967 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2968 "Memory allocated for ha=%p.\n", ha); 2969 ha->pdev = pdev; 2970 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2971 spin_lock_init(&ha->tgt.q_full_lock); 2972 spin_lock_init(&ha->tgt.sess_lock); 2973 spin_lock_init(&ha->tgt.atio_lock); 2974 2975 spin_lock_init(&ha->sadb_lock); 2976 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2977 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2978 2979 spin_lock_init(&ha->sadb_fp_lock); 2980 2981 if (qla_edif_sadb_build_free_pool(ha)) { 2982 kfree(ha); 2983 goto disable_device; 2984 } 2985 2986 atomic_set(&ha->nvme_active_aen_cnt, 0); 2987 2988 /* Clear our data area */ 2989 ha->bars = bars; 2990 ha->mem_only = mem_only; 2991 spin_lock_init(&ha->hardware_lock); 2992 spin_lock_init(&ha->vport_slock); 2993 mutex_init(&ha->selflogin_lock); 2994 mutex_init(&ha->optrom_mutex); 2995 2996 /* Set ISP-type information. */ 2997 qla2x00_set_isp_flags(ha); 2998 2999 /* Set EEH reset type to fundamental if required by hba */ 3000 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 3001 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3002 pdev->needs_freset = 1; 3003 3004 ha->prev_topology = 0; 3005 ha->init_cb_size = sizeof(init_cb_t); 3006 ha->link_data_rate = PORT_SPEED_UNKNOWN; 3007 ha->optrom_size = OPTROM_SIZE_2300; 3008 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 3009 atomic_set(&ha->num_pend_mbx_stage1, 0); 3010 atomic_set(&ha->num_pend_mbx_stage2, 0); 3011 atomic_set(&ha->num_pend_mbx_stage3, 0); 3012 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 3013 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 3014 3015 /* Assign ISP specific operations. */ 3016 if (IS_QLA2100(ha)) { 3017 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3018 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 3019 req_length = REQUEST_ENTRY_CNT_2100; 3020 rsp_length = RESPONSE_ENTRY_CNT_2100; 3021 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3022 ha->gid_list_info_size = 4; 3023 ha->flash_conf_off = ~0; 3024 ha->flash_data_off = ~0; 3025 ha->nvram_conf_off = ~0; 3026 ha->nvram_data_off = ~0; 3027 ha->isp_ops = &qla2100_isp_ops; 3028 } else if (IS_QLA2200(ha)) { 3029 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3030 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 3031 req_length = REQUEST_ENTRY_CNT_2200; 3032 rsp_length = RESPONSE_ENTRY_CNT_2100; 3033 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3034 ha->gid_list_info_size = 4; 3035 ha->flash_conf_off = ~0; 3036 ha->flash_data_off = ~0; 3037 ha->nvram_conf_off = ~0; 3038 ha->nvram_data_off = ~0; 3039 ha->isp_ops = &qla2100_isp_ops; 3040 } else if (IS_QLA23XX(ha)) { 3041 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3042 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3043 req_length = REQUEST_ENTRY_CNT_2200; 3044 rsp_length = RESPONSE_ENTRY_CNT_2300; 3045 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3046 ha->gid_list_info_size = 6; 3047 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3048 ha->optrom_size = OPTROM_SIZE_2322; 3049 ha->flash_conf_off = ~0; 3050 ha->flash_data_off = ~0; 3051 ha->nvram_conf_off = ~0; 3052 ha->nvram_data_off = ~0; 3053 ha->isp_ops = &qla2300_isp_ops; 3054 } else if (IS_QLA24XX_TYPE(ha)) { 3055 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3056 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3057 req_length = REQUEST_ENTRY_CNT_24XX; 3058 rsp_length = RESPONSE_ENTRY_CNT_2300; 3059 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3060 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3061 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3062 ha->gid_list_info_size = 8; 3063 ha->optrom_size = OPTROM_SIZE_24XX; 3064 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 3065 ha->isp_ops = &qla24xx_isp_ops; 3066 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3067 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3068 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3069 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3070 } else if (IS_QLA25XX(ha)) { 3071 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3072 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3073 req_length = REQUEST_ENTRY_CNT_24XX; 3074 rsp_length = RESPONSE_ENTRY_CNT_2300; 3075 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3076 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3077 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3078 ha->gid_list_info_size = 8; 3079 ha->optrom_size = OPTROM_SIZE_25XX; 3080 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3081 ha->isp_ops = &qla25xx_isp_ops; 3082 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3083 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3084 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3085 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3086 } else if (IS_QLA81XX(ha)) { 3087 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3088 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3089 req_length = REQUEST_ENTRY_CNT_24XX; 3090 rsp_length = RESPONSE_ENTRY_CNT_2300; 3091 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3092 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3093 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3094 ha->gid_list_info_size = 8; 3095 ha->optrom_size = OPTROM_SIZE_81XX; 3096 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3097 ha->isp_ops = &qla81xx_isp_ops; 3098 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3099 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3100 ha->nvram_conf_off = ~0; 3101 ha->nvram_data_off = ~0; 3102 } else if (IS_QLA82XX(ha)) { 3103 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3104 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3105 req_length = REQUEST_ENTRY_CNT_82XX; 3106 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3107 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3108 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3109 ha->gid_list_info_size = 8; 3110 ha->optrom_size = OPTROM_SIZE_82XX; 3111 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3112 ha->isp_ops = &qla82xx_isp_ops; 3113 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3114 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3115 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3116 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3117 } else if (IS_QLA8044(ha)) { 3118 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3119 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3120 req_length = REQUEST_ENTRY_CNT_82XX; 3121 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3122 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3123 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3124 ha->gid_list_info_size = 8; 3125 ha->optrom_size = OPTROM_SIZE_83XX; 3126 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3127 ha->isp_ops = &qla8044_isp_ops; 3128 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3129 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3130 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3131 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3132 } else if (IS_QLA83XX(ha)) { 3133 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3134 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3135 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3136 req_length = REQUEST_ENTRY_CNT_83XX; 3137 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3138 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3139 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3140 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3141 ha->gid_list_info_size = 8; 3142 ha->optrom_size = OPTROM_SIZE_83XX; 3143 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3144 ha->isp_ops = &qla83xx_isp_ops; 3145 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3146 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3147 ha->nvram_conf_off = ~0; 3148 ha->nvram_data_off = ~0; 3149 } else if (IS_QLAFX00(ha)) { 3150 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3151 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3152 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3153 req_length = REQUEST_ENTRY_CNT_FX00; 3154 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3155 ha->isp_ops = &qlafx00_isp_ops; 3156 ha->port_down_retry_count = 30; /* default value */ 3157 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3158 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3159 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3160 ha->mr.fw_hbt_en = 1; 3161 ha->mr.host_info_resend = false; 3162 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3163 } else if (IS_QLA27XX(ha)) { 3164 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3165 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3166 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3167 req_length = REQUEST_ENTRY_CNT_83XX; 3168 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3169 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3170 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3171 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3172 ha->gid_list_info_size = 8; 3173 ha->optrom_size = OPTROM_SIZE_83XX; 3174 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3175 ha->isp_ops = &qla27xx_isp_ops; 3176 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3177 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3178 ha->nvram_conf_off = ~0; 3179 ha->nvram_data_off = ~0; 3180 } else if (IS_QLA28XX(ha)) { 3181 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3182 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3183 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3184 req_length = REQUEST_ENTRY_CNT_83XX; 3185 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3186 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3187 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3188 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3189 ha->gid_list_info_size = 8; 3190 ha->optrom_size = OPTROM_SIZE_28XX; 3191 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3192 ha->isp_ops = &qla27xx_isp_ops; 3193 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3194 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3195 ha->nvram_conf_off = ~0; 3196 ha->nvram_data_off = ~0; 3197 } 3198 3199 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3200 "mbx_count=%d, req_length=%d, " 3201 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3202 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3203 "max_fibre_devices=%d.\n", 3204 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3205 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3206 ha->nvram_npiv_size, ha->max_fibre_devices); 3207 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3208 "isp_ops=%p, flash_conf_off=%d, " 3209 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3210 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3211 ha->nvram_conf_off, ha->nvram_data_off); 3212 3213 /* Configure PCI I/O space */ 3214 ret = ha->isp_ops->iospace_config(ha); 3215 if (ret) 3216 goto iospace_config_failed; 3217 3218 ql_log_pci(ql_log_info, pdev, 0x001d, 3219 "Found an ISP%04X irq %d iobase 0x%p.\n", 3220 pdev->device, pdev->irq, ha->iobase); 3221 mutex_init(&ha->vport_lock); 3222 mutex_init(&ha->mq_lock); 3223 init_completion(&ha->mbx_cmd_comp); 3224 complete(&ha->mbx_cmd_comp); 3225 init_completion(&ha->mbx_intr_comp); 3226 init_completion(&ha->dcbx_comp); 3227 init_completion(&ha->lb_portup_comp); 3228 3229 set_bit(0, (unsigned long *) ha->vp_idx_map); 3230 3231 qla2x00_config_dma_addressing(ha); 3232 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3233 "64 Bit addressing is %s.\n", 3234 ha->flags.enable_64bit_addressing ? "enable" : 3235 "disable"); 3236 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3237 if (ret) { 3238 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3239 "Failed to allocate memory for adapter, aborting.\n"); 3240 3241 goto probe_hw_failed; 3242 } 3243 3244 req->max_q_depth = MAX_Q_DEPTH; 3245 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3246 req->max_q_depth = ql2xmaxqdepth; 3247 3248 3249 base_vha = qla2x00_create_host(sht, ha); 3250 if (!base_vha) { 3251 ret = -ENOMEM; 3252 goto probe_hw_failed; 3253 } 3254 3255 pci_set_drvdata(pdev, base_vha); 3256 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3257 3258 host = base_vha->host; 3259 base_vha->req = req; 3260 if (IS_QLA2XXX_MIDTYPE(ha)) 3261 base_vha->mgmt_svr_loop_id = 3262 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3263 else 3264 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3265 base_vha->vp_idx; 3266 3267 /* Setup fcport template structure. */ 3268 ha->mr.fcport.vha = base_vha; 3269 ha->mr.fcport.port_type = FCT_UNKNOWN; 3270 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3271 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3272 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3273 ha->mr.fcport.scan_state = 1; 3274 3275 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3276 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3277 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3278 3279 /* Set the SG table size based on ISP type */ 3280 if (!IS_FWI2_CAPABLE(ha)) { 3281 if (IS_QLA2100(ha)) 3282 host->sg_tablesize = 32; 3283 } else { 3284 if (!IS_QLA82XX(ha)) 3285 host->sg_tablesize = QLA_SG_ALL; 3286 } 3287 host->max_id = ha->max_fibre_devices; 3288 host->cmd_per_lun = 3; 3289 host->unique_id = host->host_no; 3290 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3291 host->max_cmd_len = 32; 3292 else 3293 host->max_cmd_len = MAX_CMDSZ; 3294 host->max_channel = MAX_BUSES - 1; 3295 /* Older HBAs support only 16-bit LUNs */ 3296 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3297 ql2xmaxlun > 0xffff) 3298 host->max_lun = 0xffff; 3299 else 3300 host->max_lun = ql2xmaxlun; 3301 host->transportt = qla2xxx_transport_template; 3302 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3303 3304 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3305 "max_id=%d this_id=%d " 3306 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3307 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3308 host->this_id, host->cmd_per_lun, host->unique_id, 3309 host->max_cmd_len, host->max_channel, host->max_lun, 3310 host->transportt, sht->vendor_id); 3311 3312 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3313 3314 /* Set up the irqs */ 3315 ret = qla2x00_request_irqs(ha, rsp); 3316 if (ret) 3317 goto probe_failed; 3318 3319 /* Alloc arrays of request and response ring ptrs */ 3320 ret = qla2x00_alloc_queues(ha, req, rsp); 3321 if (ret) { 3322 ql_log(ql_log_fatal, base_vha, 0x003d, 3323 "Failed to allocate memory for queue pointers..." 3324 "aborting.\n"); 3325 ret = -ENODEV; 3326 goto probe_failed; 3327 } 3328 3329 if (ha->mqenable) { 3330 /* number of hardware queues supported by blk/scsi-mq*/ 3331 host->nr_hw_queues = ha->max_qpairs; 3332 3333 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3334 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3335 } else { 3336 if (ql2xnvmeenable) { 3337 host->nr_hw_queues = ha->max_qpairs; 3338 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3339 "FC-NVMe support is enabled, HW queues=%d\n", 3340 host->nr_hw_queues); 3341 } else { 3342 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3343 "blk/scsi-mq disabled.\n"); 3344 } 3345 } 3346 3347 qlt_probe_one_stage1(base_vha, ha); 3348 3349 pci_save_state(pdev); 3350 3351 /* Assign back pointers */ 3352 rsp->req = req; 3353 req->rsp = rsp; 3354 3355 if (IS_QLAFX00(ha)) { 3356 ha->rsp_q_map[0] = rsp; 3357 ha->req_q_map[0] = req; 3358 set_bit(0, ha->req_qid_map); 3359 set_bit(0, ha->rsp_qid_map); 3360 } 3361 3362 /* FWI2-capable only. */ 3363 req->req_q_in = &ha->iobase->isp24.req_q_in; 3364 req->req_q_out = &ha->iobase->isp24.req_q_out; 3365 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3366 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3367 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3368 IS_QLA28XX(ha)) { 3369 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3370 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3371 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3372 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3373 } 3374 3375 if (IS_QLAFX00(ha)) { 3376 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3377 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3378 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3379 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3380 } 3381 3382 if (IS_P3P_TYPE(ha)) { 3383 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3384 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3385 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3386 } 3387 3388 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3389 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3390 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3391 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3392 "req->req_q_in=%p req->req_q_out=%p " 3393 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3394 req->req_q_in, req->req_q_out, 3395 rsp->rsp_q_in, rsp->rsp_q_out); 3396 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3397 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3398 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3399 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3400 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3401 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3402 3403 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3404 if (unlikely(!ha->wq)) { 3405 ret = -ENOMEM; 3406 goto probe_failed; 3407 } 3408 3409 if (ha->isp_ops->initialize_adapter(base_vha)) { 3410 ql_log(ql_log_fatal, base_vha, 0x00d6, 3411 "Failed to initialize adapter - Adapter flags %x.\n", 3412 base_vha->device_flags); 3413 3414 if (IS_QLA82XX(ha)) { 3415 qla82xx_idc_lock(ha); 3416 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3417 QLA8XXX_DEV_FAILED); 3418 qla82xx_idc_unlock(ha); 3419 ql_log(ql_log_fatal, base_vha, 0x00d7, 3420 "HW State: FAILED.\n"); 3421 } else if (IS_QLA8044(ha)) { 3422 qla8044_idc_lock(ha); 3423 qla8044_wr_direct(base_vha, 3424 QLA8044_CRB_DEV_STATE_INDEX, 3425 QLA8XXX_DEV_FAILED); 3426 qla8044_idc_unlock(ha); 3427 ql_log(ql_log_fatal, base_vha, 0x0150, 3428 "HW State: FAILED.\n"); 3429 } 3430 3431 ret = -ENODEV; 3432 goto probe_failed; 3433 } 3434 3435 if (IS_QLAFX00(ha)) 3436 host->can_queue = QLAFX00_MAX_CANQUEUE; 3437 else 3438 host->can_queue = req->num_outstanding_cmds - 10; 3439 3440 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3441 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3442 host->can_queue, base_vha->req, 3443 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3444 3445 /* Check if FW supports MQ or not for ISP25xx */ 3446 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3447 ha->mqenable = 0; 3448 3449 if (ha->mqenable) { 3450 bool startit = false; 3451 3452 if (QLA_TGT_MODE_ENABLED()) 3453 startit = false; 3454 3455 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3456 startit = true; 3457 3458 /* Create start of day qpairs for Block MQ */ 3459 for (i = 0; i < ha->max_qpairs; i++) 3460 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3461 } 3462 qla_init_iocb_limit(base_vha); 3463 3464 if (ha->flags.running_gold_fw) 3465 goto skip_dpc; 3466 3467 /* 3468 * Startup the kernel thread for this host adapter 3469 */ 3470 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3471 "%s_dpc", base_vha->host_str); 3472 if (IS_ERR(ha->dpc_thread)) { 3473 ql_log(ql_log_fatal, base_vha, 0x00ed, 3474 "Failed to start DPC thread.\n"); 3475 ret = PTR_ERR(ha->dpc_thread); 3476 ha->dpc_thread = NULL; 3477 goto probe_failed; 3478 } 3479 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3480 "DPC thread started successfully.\n"); 3481 3482 /* 3483 * If we're not coming up in initiator mode, we might sit for 3484 * a while without waking up the dpc thread, which leads to a 3485 * stuck process warning. So just kick the dpc once here and 3486 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3487 */ 3488 qla2xxx_wake_dpc(base_vha); 3489 3490 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3491 3492 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3493 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3494 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3495 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3496 3497 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3498 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3499 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3500 INIT_WORK(&ha->idc_state_handler, 3501 qla83xx_idc_state_handler_work); 3502 INIT_WORK(&ha->nic_core_unrecoverable, 3503 qla83xx_nic_core_unrecoverable_work); 3504 } 3505 3506 skip_dpc: 3507 list_add_tail(&base_vha->list, &ha->vp_list); 3508 base_vha->host->irq = ha->pdev->irq; 3509 3510 /* Initialized the timer */ 3511 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3512 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3513 "Started qla2x00_timer with " 3514 "interval=%d.\n", WATCH_INTERVAL); 3515 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3516 "Detected hba at address=%p.\n", 3517 ha); 3518 3519 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3520 if (ha->fw_attributes & BIT_4) { 3521 int prot = 0, guard; 3522 3523 base_vha->flags.difdix_supported = 1; 3524 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3525 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3526 if (ql2xenabledif == 1) 3527 prot = SHOST_DIX_TYPE0_PROTECTION; 3528 if (ql2xprotmask) 3529 scsi_host_set_prot(host, ql2xprotmask); 3530 else 3531 scsi_host_set_prot(host, 3532 prot | SHOST_DIF_TYPE1_PROTECTION 3533 | SHOST_DIF_TYPE2_PROTECTION 3534 | SHOST_DIF_TYPE3_PROTECTION 3535 | SHOST_DIX_TYPE1_PROTECTION 3536 | SHOST_DIX_TYPE2_PROTECTION 3537 | SHOST_DIX_TYPE3_PROTECTION); 3538 3539 guard = SHOST_DIX_GUARD_CRC; 3540 3541 if (IS_PI_IPGUARD_CAPABLE(ha) && 3542 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3543 guard |= SHOST_DIX_GUARD_IP; 3544 3545 if (ql2xprotguard) 3546 scsi_host_set_guard(host, ql2xprotguard); 3547 else 3548 scsi_host_set_guard(host, guard); 3549 } else 3550 base_vha->flags.difdix_supported = 0; 3551 } 3552 3553 ha->isp_ops->enable_intrs(ha); 3554 3555 if (IS_QLAFX00(ha)) { 3556 ret = qlafx00_fx_disc(base_vha, 3557 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3558 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3559 QLA_SG_ALL : 128; 3560 } 3561 3562 ret = scsi_add_host(host, &pdev->dev); 3563 if (ret) 3564 goto probe_failed; 3565 3566 base_vha->flags.init_done = 1; 3567 base_vha->flags.online = 1; 3568 ha->prev_minidump_failed = 0; 3569 3570 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3571 "Init done and hba is online.\n"); 3572 3573 if (qla_ini_mode_enabled(base_vha) || 3574 qla_dual_mode_enabled(base_vha)) 3575 scsi_scan_host(host); 3576 else 3577 ql_log(ql_log_info, base_vha, 0x0122, 3578 "skipping scsi_scan_host() for non-initiator port\n"); 3579 3580 qla2x00_alloc_sysfs_attr(base_vha); 3581 3582 if (IS_QLAFX00(ha)) { 3583 ret = qlafx00_fx_disc(base_vha, 3584 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3585 3586 /* Register system information */ 3587 ret = qlafx00_fx_disc(base_vha, 3588 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3589 } 3590 3591 qla2x00_init_host_attr(base_vha); 3592 3593 qla2x00_dfs_setup(base_vha); 3594 3595 ql_log(ql_log_info, base_vha, 0x00fb, 3596 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3597 ql_log(ql_log_info, base_vha, 0x00fc, 3598 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3599 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3600 sizeof(pci_info)), 3601 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3602 base_vha->host_no, 3603 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3604 3605 qlt_add_target(ha, base_vha); 3606 3607 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3608 3609 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3610 return -ENODEV; 3611 3612 return 0; 3613 3614 probe_failed: 3615 qla_enode_stop(base_vha); 3616 qla_edb_stop(base_vha); 3617 vfree(base_vha->scan.l); 3618 if (base_vha->gnl.l) { 3619 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3620 base_vha->gnl.l, base_vha->gnl.ldma); 3621 base_vha->gnl.l = NULL; 3622 } 3623 3624 if (base_vha->timer_active) 3625 qla2x00_stop_timer(base_vha); 3626 base_vha->flags.online = 0; 3627 if (ha->dpc_thread) { 3628 struct task_struct *t = ha->dpc_thread; 3629 3630 ha->dpc_thread = NULL; 3631 kthread_stop(t); 3632 } 3633 3634 qla2x00_free_device(base_vha); 3635 scsi_host_put(base_vha->host); 3636 /* 3637 * Need to NULL out local req/rsp after 3638 * qla2x00_free_device => qla2x00_free_queues frees 3639 * what these are pointing to. Or else we'll 3640 * fall over below in qla2x00_free_req/rsp_que. 3641 */ 3642 req = NULL; 3643 rsp = NULL; 3644 3645 probe_hw_failed: 3646 qla2x00_mem_free(ha); 3647 qla2x00_free_req_que(ha, req); 3648 qla2x00_free_rsp_que(ha, rsp); 3649 qla2x00_clear_drv_active(ha); 3650 3651 iospace_config_failed: 3652 if (IS_P3P_TYPE(ha)) { 3653 if (!ha->nx_pcibase) 3654 iounmap((device_reg_t *)ha->nx_pcibase); 3655 if (!ql2xdbwr) 3656 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3657 } else { 3658 if (ha->iobase) 3659 iounmap(ha->iobase); 3660 if (ha->cregbase) 3661 iounmap(ha->cregbase); 3662 } 3663 pci_release_selected_regions(ha->pdev, ha->bars); 3664 kfree(ha); 3665 3666 disable_device: 3667 pci_disable_device(pdev); 3668 return ret; 3669 } 3670 3671 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3672 { 3673 scsi_qla_host_t *vp; 3674 unsigned long flags; 3675 struct qla_hw_data *ha; 3676 3677 if (!base_vha) 3678 return; 3679 3680 ha = base_vha->hw; 3681 3682 spin_lock_irqsave(&ha->vport_slock, flags); 3683 list_for_each_entry(vp, &ha->vp_list, list) 3684 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3685 3686 /* 3687 * Indicate device removal to prevent future board_disable 3688 * and wait until any pending board_disable has completed. 3689 */ 3690 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3691 spin_unlock_irqrestore(&ha->vport_slock, flags); 3692 } 3693 3694 static void 3695 qla2x00_shutdown(struct pci_dev *pdev) 3696 { 3697 scsi_qla_host_t *vha; 3698 struct qla_hw_data *ha; 3699 3700 vha = pci_get_drvdata(pdev); 3701 ha = vha->hw; 3702 3703 ql_log(ql_log_info, vha, 0xfffa, 3704 "Adapter shutdown\n"); 3705 3706 /* 3707 * Prevent future board_disable and wait 3708 * until any pending board_disable has completed. 3709 */ 3710 __qla_set_remove_flag(vha); 3711 cancel_work_sync(&ha->board_disable); 3712 3713 if (!atomic_read(&pdev->enable_cnt)) 3714 return; 3715 3716 /* Notify ISPFX00 firmware */ 3717 if (IS_QLAFX00(ha)) 3718 qlafx00_driver_shutdown(vha, 20); 3719 3720 /* Turn-off FCE trace */ 3721 if (ha->flags.fce_enabled) { 3722 qla2x00_disable_fce_trace(vha, NULL, NULL); 3723 ha->flags.fce_enabled = 0; 3724 } 3725 3726 /* Turn-off EFT trace */ 3727 if (ha->eft) 3728 qla2x00_disable_eft_trace(vha); 3729 3730 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3731 IS_QLA28XX(ha)) { 3732 if (ha->flags.fw_started) 3733 qla2x00_abort_isp_cleanup(vha); 3734 } else { 3735 /* Stop currently executing firmware. */ 3736 qla2x00_try_to_stop_firmware(vha); 3737 } 3738 3739 /* Disable timer */ 3740 if (vha->timer_active) 3741 qla2x00_stop_timer(vha); 3742 3743 /* Turn adapter off line */ 3744 vha->flags.online = 0; 3745 3746 /* turn-off interrupts on the card */ 3747 if (ha->interrupts_on) { 3748 vha->flags.init_done = 0; 3749 ha->isp_ops->disable_intrs(ha); 3750 } 3751 3752 qla2x00_free_irqs(vha); 3753 3754 qla2x00_free_fw_dump(ha); 3755 3756 pci_disable_device(pdev); 3757 ql_log(ql_log_info, vha, 0xfffe, 3758 "Adapter shutdown successfully.\n"); 3759 } 3760 3761 /* Deletes all the virtual ports for a given ha */ 3762 static void 3763 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3764 { 3765 scsi_qla_host_t *vha; 3766 unsigned long flags; 3767 3768 mutex_lock(&ha->vport_lock); 3769 while (ha->cur_vport_count) { 3770 spin_lock_irqsave(&ha->vport_slock, flags); 3771 3772 BUG_ON(base_vha->list.next == &ha->vp_list); 3773 /* This assumes first entry in ha->vp_list is always base vha */ 3774 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3775 scsi_host_get(vha->host); 3776 3777 spin_unlock_irqrestore(&ha->vport_slock, flags); 3778 mutex_unlock(&ha->vport_lock); 3779 3780 qla_nvme_delete(vha); 3781 3782 fc_vport_terminate(vha->fc_vport); 3783 scsi_host_put(vha->host); 3784 3785 mutex_lock(&ha->vport_lock); 3786 } 3787 mutex_unlock(&ha->vport_lock); 3788 } 3789 3790 /* Stops all deferred work threads */ 3791 static void 3792 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3793 { 3794 /* Cancel all work and destroy DPC workqueues */ 3795 if (ha->dpc_lp_wq) { 3796 cancel_work_sync(&ha->idc_aen); 3797 destroy_workqueue(ha->dpc_lp_wq); 3798 ha->dpc_lp_wq = NULL; 3799 } 3800 3801 if (ha->dpc_hp_wq) { 3802 cancel_work_sync(&ha->nic_core_reset); 3803 cancel_work_sync(&ha->idc_state_handler); 3804 cancel_work_sync(&ha->nic_core_unrecoverable); 3805 destroy_workqueue(ha->dpc_hp_wq); 3806 ha->dpc_hp_wq = NULL; 3807 } 3808 3809 /* Kill the kernel thread for this host */ 3810 if (ha->dpc_thread) { 3811 struct task_struct *t = ha->dpc_thread; 3812 3813 /* 3814 * qla2xxx_wake_dpc checks for ->dpc_thread 3815 * so we need to zero it out. 3816 */ 3817 ha->dpc_thread = NULL; 3818 kthread_stop(t); 3819 } 3820 } 3821 3822 static void 3823 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3824 { 3825 if (IS_QLA82XX(ha)) { 3826 3827 iounmap((device_reg_t *)ha->nx_pcibase); 3828 if (!ql2xdbwr) 3829 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3830 } else { 3831 if (ha->iobase) 3832 iounmap(ha->iobase); 3833 3834 if (ha->cregbase) 3835 iounmap(ha->cregbase); 3836 3837 if (ha->mqiobase) 3838 iounmap(ha->mqiobase); 3839 3840 if (ha->msixbase) 3841 iounmap(ha->msixbase); 3842 } 3843 } 3844 3845 static void 3846 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3847 { 3848 if (IS_QLA8044(ha)) { 3849 qla8044_idc_lock(ha); 3850 qla8044_clear_drv_active(ha); 3851 qla8044_idc_unlock(ha); 3852 } else if (IS_QLA82XX(ha)) { 3853 qla82xx_idc_lock(ha); 3854 qla82xx_clear_drv_active(ha); 3855 qla82xx_idc_unlock(ha); 3856 } 3857 } 3858 3859 static void 3860 qla2x00_remove_one(struct pci_dev *pdev) 3861 { 3862 scsi_qla_host_t *base_vha; 3863 struct qla_hw_data *ha; 3864 3865 base_vha = pci_get_drvdata(pdev); 3866 ha = base_vha->hw; 3867 ql_log(ql_log_info, base_vha, 0xb079, 3868 "Removing driver\n"); 3869 __qla_set_remove_flag(base_vha); 3870 cancel_work_sync(&ha->board_disable); 3871 3872 /* 3873 * If the PCI device is disabled then there was a PCI-disconnect and 3874 * qla2x00_disable_board_on_pci_error has taken care of most of the 3875 * resources. 3876 */ 3877 if (!atomic_read(&pdev->enable_cnt)) { 3878 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3879 base_vha->gnl.l, base_vha->gnl.ldma); 3880 base_vha->gnl.l = NULL; 3881 scsi_host_put(base_vha->host); 3882 kfree(ha); 3883 pci_set_drvdata(pdev, NULL); 3884 return; 3885 } 3886 qla2x00_wait_for_hba_ready(base_vha); 3887 3888 /* 3889 * if UNLOADING flag is already set, then continue unload, 3890 * where it was set first. 3891 */ 3892 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3893 return; 3894 3895 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3896 IS_QLA28XX(ha)) { 3897 if (ha->flags.fw_started) 3898 qla2x00_abort_isp_cleanup(base_vha); 3899 } else if (!IS_QLAFX00(ha)) { 3900 if (IS_QLA8031(ha)) { 3901 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3902 "Clearing fcoe driver presence.\n"); 3903 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3904 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3905 "Error while clearing DRV-Presence.\n"); 3906 } 3907 3908 qla2x00_try_to_stop_firmware(base_vha); 3909 } 3910 3911 qla2x00_wait_for_sess_deletion(base_vha); 3912 3913 qla_nvme_delete(base_vha); 3914 3915 dma_free_coherent(&ha->pdev->dev, 3916 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3917 3918 base_vha->gnl.l = NULL; 3919 qla_enode_stop(base_vha); 3920 qla_edb_stop(base_vha); 3921 3922 vfree(base_vha->scan.l); 3923 3924 if (IS_QLAFX00(ha)) 3925 qlafx00_driver_shutdown(base_vha, 20); 3926 3927 qla2x00_delete_all_vps(ha, base_vha); 3928 3929 qla2x00_dfs_remove(base_vha); 3930 3931 qla84xx_put_chip(base_vha); 3932 3933 /* Disable timer */ 3934 if (base_vha->timer_active) 3935 qla2x00_stop_timer(base_vha); 3936 3937 base_vha->flags.online = 0; 3938 3939 /* free DMA memory */ 3940 if (ha->exlogin_buf) 3941 qla2x00_free_exlogin_buffer(ha); 3942 3943 /* free DMA memory */ 3944 if (ha->exchoffld_buf) 3945 qla2x00_free_exchoffld_buffer(ha); 3946 3947 qla2x00_destroy_deferred_work(ha); 3948 3949 qlt_remove_target(ha, base_vha); 3950 3951 qla2x00_free_sysfs_attr(base_vha, true); 3952 3953 fc_remove_host(base_vha->host); 3954 3955 scsi_remove_host(base_vha->host); 3956 3957 qla2x00_free_device(base_vha); 3958 3959 qla2x00_clear_drv_active(ha); 3960 3961 scsi_host_put(base_vha->host); 3962 3963 qla2x00_unmap_iobases(ha); 3964 3965 pci_release_selected_regions(ha->pdev, ha->bars); 3966 kfree(ha); 3967 3968 pci_disable_device(pdev); 3969 } 3970 3971 static inline void 3972 qla24xx_free_purex_list(struct purex_list *list) 3973 { 3974 struct purex_item *item, *next; 3975 ulong flags; 3976 3977 spin_lock_irqsave(&list->lock, flags); 3978 list_for_each_entry_safe(item, next, &list->head, list) { 3979 list_del(&item->list); 3980 if (item == &item->vha->default_item) 3981 continue; 3982 kfree(item); 3983 } 3984 spin_unlock_irqrestore(&list->lock, flags); 3985 } 3986 3987 static void 3988 qla2x00_free_device(scsi_qla_host_t *vha) 3989 { 3990 struct qla_hw_data *ha = vha->hw; 3991 3992 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3993 3994 /* Disable timer */ 3995 if (vha->timer_active) 3996 qla2x00_stop_timer(vha); 3997 3998 qla25xx_delete_queues(vha); 3999 vha->flags.online = 0; 4000 4001 /* turn-off interrupts on the card */ 4002 if (ha->interrupts_on) { 4003 vha->flags.init_done = 0; 4004 ha->isp_ops->disable_intrs(ha); 4005 } 4006 4007 qla2x00_free_fcports(vha); 4008 4009 qla2x00_free_irqs(vha); 4010 4011 /* Flush the work queue and remove it */ 4012 if (ha->wq) { 4013 destroy_workqueue(ha->wq); 4014 ha->wq = NULL; 4015 } 4016 4017 4018 qla24xx_free_purex_list(&vha->purex_list); 4019 4020 qla2x00_mem_free(ha); 4021 4022 qla82xx_md_free(vha); 4023 4024 qla_edif_sadb_release_free_pool(ha); 4025 qla_edif_sadb_release(ha); 4026 4027 qla2x00_free_queues(ha); 4028 } 4029 4030 void qla2x00_free_fcports(struct scsi_qla_host *vha) 4031 { 4032 fc_port_t *fcport, *tfcport; 4033 4034 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 4035 qla2x00_free_fcport(fcport); 4036 } 4037 4038 static inline void 4039 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 4040 { 4041 int now; 4042 4043 if (!fcport->rport) 4044 return; 4045 4046 if (fcport->rport) { 4047 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 4048 "%s %8phN. rport %p roles %x\n", 4049 __func__, fcport->port_name, fcport->rport, 4050 fcport->rport->roles); 4051 fc_remote_port_delete(fcport->rport); 4052 } 4053 qlt_do_generation_tick(vha, &now); 4054 } 4055 4056 /* 4057 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 4058 * 4059 * Input: ha = adapter block pointer. fcport = port structure pointer. 4060 * 4061 * Return: None. 4062 * 4063 * Context: 4064 */ 4065 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 4066 int do_login) 4067 { 4068 if (IS_QLAFX00(vha->hw)) { 4069 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4070 qla2x00_schedule_rport_del(vha, fcport); 4071 return; 4072 } 4073 4074 if (atomic_read(&fcport->state) == FCS_ONLINE && 4075 vha->vp_idx == fcport->vha->vp_idx) { 4076 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4077 qla2x00_schedule_rport_del(vha, fcport); 4078 } 4079 4080 /* 4081 * We may need to retry the login, so don't change the state of the 4082 * port but do the retries. 4083 */ 4084 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4085 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4086 4087 if (!do_login) 4088 return; 4089 4090 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4091 } 4092 4093 void 4094 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4095 { 4096 fc_port_t *fcport; 4097 4098 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4099 "Mark all dev lost\n"); 4100 4101 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4102 if (ql2xfc2target && 4103 fcport->loop_id != FC_NO_LOOP_ID && 4104 (fcport->flags & FCF_FCP2_DEVICE) && 4105 fcport->port_type == FCT_TARGET && 4106 !qla2x00_reset_active(vha)) { 4107 ql_dbg(ql_dbg_disc, vha, 0x211a, 4108 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4109 fcport->flags, fcport->port_type, 4110 fcport->d_id.b24, fcport->port_name); 4111 continue; 4112 } 4113 fcport->scan_state = 0; 4114 qlt_schedule_sess_for_deletion(fcport); 4115 } 4116 } 4117 4118 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4119 { 4120 int i; 4121 4122 if (IS_FWI2_CAPABLE(ha)) 4123 return; 4124 4125 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4126 set_bit(i, ha->loop_id_map); 4127 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4128 set_bit(BROADCAST, ha->loop_id_map); 4129 } 4130 4131 /* 4132 * qla2x00_mem_alloc 4133 * Allocates adapter memory. 4134 * 4135 * Returns: 4136 * 0 = success. 4137 * !0 = failure. 4138 */ 4139 static int 4140 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4141 struct req_que **req, struct rsp_que **rsp) 4142 { 4143 char name[16]; 4144 int rc; 4145 4146 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) { 4147 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL); 4148 if (!ha->vp_map) 4149 goto fail; 4150 } 4151 4152 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4153 &ha->init_cb_dma, GFP_KERNEL); 4154 if (!ha->init_cb) 4155 goto fail_free_vp_map; 4156 4157 rc = btree_init32(&ha->host_map); 4158 if (rc) 4159 goto fail_free_init_cb; 4160 4161 if (qlt_mem_alloc(ha) < 0) 4162 goto fail_free_btree; 4163 4164 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4165 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4166 if (!ha->gid_list) 4167 goto fail_free_tgt_mem; 4168 4169 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4170 if (!ha->srb_mempool) 4171 goto fail_free_gid_list; 4172 4173 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4174 /* Allocate cache for CT6 Ctx. */ 4175 if (!ctx_cachep) { 4176 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4177 sizeof(struct ct6_dsd), 0, 4178 SLAB_HWCACHE_ALIGN, NULL); 4179 if (!ctx_cachep) 4180 goto fail_free_srb_mempool; 4181 } 4182 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4183 ctx_cachep); 4184 if (!ha->ctx_mempool) 4185 goto fail_free_srb_mempool; 4186 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4187 "ctx_cachep=%p ctx_mempool=%p.\n", 4188 ctx_cachep, ha->ctx_mempool); 4189 } 4190 4191 /* Get memory for cached NVRAM */ 4192 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4193 if (!ha->nvram) 4194 goto fail_free_ctx_mempool; 4195 4196 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4197 ha->pdev->device); 4198 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4199 DMA_POOL_SIZE, 8, 0); 4200 if (!ha->s_dma_pool) 4201 goto fail_free_nvram; 4202 4203 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4204 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4205 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4206 4207 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4208 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4209 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4210 if (!ha->dl_dma_pool) { 4211 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4212 "Failed to allocate memory for dl_dma_pool.\n"); 4213 goto fail_s_dma_pool; 4214 } 4215 4216 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4217 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4218 if (!ha->fcp_cmnd_dma_pool) { 4219 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4220 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4221 goto fail_dl_dma_pool; 4222 } 4223 4224 if (ql2xenabledif) { 4225 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4226 struct dsd_dma *dsd, *nxt; 4227 uint i; 4228 /* Creata a DMA pool of buffers for DIF bundling */ 4229 ha->dif_bundl_pool = dma_pool_create(name, 4230 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4231 if (!ha->dif_bundl_pool) { 4232 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4233 "%s: failed create dif_bundl_pool\n", 4234 __func__); 4235 goto fail_dif_bundl_dma_pool; 4236 } 4237 4238 INIT_LIST_HEAD(&ha->pool.good.head); 4239 INIT_LIST_HEAD(&ha->pool.unusable.head); 4240 ha->pool.good.count = 0; 4241 ha->pool.unusable.count = 0; 4242 for (i = 0; i < 128; i++) { 4243 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4244 if (!dsd) { 4245 ql_dbg_pci(ql_dbg_init, ha->pdev, 4246 0xe0ee, "%s: failed alloc dsd\n", 4247 __func__); 4248 return -ENOMEM; 4249 } 4250 ha->dif_bundle_kallocs++; 4251 4252 dsd->dsd_addr = dma_pool_alloc( 4253 ha->dif_bundl_pool, GFP_ATOMIC, 4254 &dsd->dsd_list_dma); 4255 if (!dsd->dsd_addr) { 4256 ql_dbg_pci(ql_dbg_init, ha->pdev, 4257 0xe0ee, 4258 "%s: failed alloc ->dsd_addr\n", 4259 __func__); 4260 kfree(dsd); 4261 ha->dif_bundle_kallocs--; 4262 continue; 4263 } 4264 ha->dif_bundle_dma_allocs++; 4265 4266 /* 4267 * if DMA buffer crosses 4G boundary, 4268 * put it on bad list 4269 */ 4270 if (MSD(dsd->dsd_list_dma) ^ 4271 MSD(dsd->dsd_list_dma + bufsize)) { 4272 list_add_tail(&dsd->list, 4273 &ha->pool.unusable.head); 4274 ha->pool.unusable.count++; 4275 } else { 4276 list_add_tail(&dsd->list, 4277 &ha->pool.good.head); 4278 ha->pool.good.count++; 4279 } 4280 } 4281 4282 /* return the good ones back to the pool */ 4283 list_for_each_entry_safe(dsd, nxt, 4284 &ha->pool.good.head, list) { 4285 list_del(&dsd->list); 4286 dma_pool_free(ha->dif_bundl_pool, 4287 dsd->dsd_addr, dsd->dsd_list_dma); 4288 ha->dif_bundle_dma_allocs--; 4289 kfree(dsd); 4290 ha->dif_bundle_kallocs--; 4291 } 4292 4293 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4294 "%s: dif dma pool (good=%u unusable=%u)\n", 4295 __func__, ha->pool.good.count, 4296 ha->pool.unusable.count); 4297 } 4298 4299 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4300 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4301 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4302 ha->dif_bundl_pool); 4303 } 4304 4305 /* Allocate memory for SNS commands */ 4306 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4307 /* Get consistent memory allocated for SNS commands */ 4308 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4309 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4310 if (!ha->sns_cmd) 4311 goto fail_dma_pool; 4312 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4313 "sns_cmd: %p.\n", ha->sns_cmd); 4314 } else { 4315 /* Get consistent memory allocated for MS IOCB */ 4316 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4317 &ha->ms_iocb_dma); 4318 if (!ha->ms_iocb) 4319 goto fail_dma_pool; 4320 /* Get consistent memory allocated for CT SNS commands */ 4321 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4322 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4323 if (!ha->ct_sns) 4324 goto fail_free_ms_iocb; 4325 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4326 "ms_iocb=%p ct_sns=%p.\n", 4327 ha->ms_iocb, ha->ct_sns); 4328 } 4329 4330 /* Allocate memory for request ring */ 4331 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4332 if (!*req) { 4333 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4334 "Failed to allocate memory for req.\n"); 4335 goto fail_req; 4336 } 4337 (*req)->length = req_len; 4338 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4339 ((*req)->length + 1) * sizeof(request_t), 4340 &(*req)->dma, GFP_KERNEL); 4341 if (!(*req)->ring) { 4342 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4343 "Failed to allocate memory for req_ring.\n"); 4344 goto fail_req_ring; 4345 } 4346 /* Allocate memory for response ring */ 4347 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4348 if (!*rsp) { 4349 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4350 "Failed to allocate memory for rsp.\n"); 4351 goto fail_rsp; 4352 } 4353 (*rsp)->hw = ha; 4354 (*rsp)->length = rsp_len; 4355 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4356 ((*rsp)->length + 1) * sizeof(response_t), 4357 &(*rsp)->dma, GFP_KERNEL); 4358 if (!(*rsp)->ring) { 4359 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4360 "Failed to allocate memory for rsp_ring.\n"); 4361 goto fail_rsp_ring; 4362 } 4363 (*req)->rsp = *rsp; 4364 (*rsp)->req = *req; 4365 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4366 "req=%p req->length=%d req->ring=%p rsp=%p " 4367 "rsp->length=%d rsp->ring=%p.\n", 4368 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4369 (*rsp)->ring); 4370 /* Allocate memory for NVRAM data for vports */ 4371 if (ha->nvram_npiv_size) { 4372 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4373 sizeof(struct qla_npiv_entry), 4374 GFP_KERNEL); 4375 if (!ha->npiv_info) { 4376 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4377 "Failed to allocate memory for npiv_info.\n"); 4378 goto fail_npiv_info; 4379 } 4380 } else 4381 ha->npiv_info = NULL; 4382 4383 /* Get consistent memory allocated for EX-INIT-CB. */ 4384 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4385 IS_QLA28XX(ha)) { 4386 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4387 &ha->ex_init_cb_dma); 4388 if (!ha->ex_init_cb) 4389 goto fail_ex_init_cb; 4390 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4391 "ex_init_cb=%p.\n", ha->ex_init_cb); 4392 } 4393 4394 /* Get consistent memory allocated for Special Features-CB. */ 4395 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4396 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4397 &ha->sf_init_cb_dma); 4398 if (!ha->sf_init_cb) 4399 goto fail_sf_init_cb; 4400 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4401 "sf_init_cb=%p.\n", ha->sf_init_cb); 4402 } 4403 4404 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4405 4406 /* Get consistent memory allocated for Async Port-Database. */ 4407 if (!IS_FWI2_CAPABLE(ha)) { 4408 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4409 &ha->async_pd_dma); 4410 if (!ha->async_pd) 4411 goto fail_async_pd; 4412 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4413 "async_pd=%p.\n", ha->async_pd); 4414 } 4415 4416 INIT_LIST_HEAD(&ha->vp_list); 4417 4418 /* Allocate memory for our loop_id bitmap */ 4419 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4420 sizeof(long), 4421 GFP_KERNEL); 4422 if (!ha->loop_id_map) 4423 goto fail_loop_id_map; 4424 else { 4425 qla2x00_set_reserved_loop_ids(ha); 4426 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4427 "loop_id_map=%p.\n", ha->loop_id_map); 4428 } 4429 4430 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4431 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4432 if (!ha->sfp_data) { 4433 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4434 "Unable to allocate memory for SFP read-data.\n"); 4435 goto fail_sfp_data; 4436 } 4437 4438 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4439 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4440 GFP_KERNEL); 4441 if (!ha->flt) { 4442 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4443 "Unable to allocate memory for FLT.\n"); 4444 goto fail_flt_buffer; 4445 } 4446 4447 /* allocate the purex dma pool */ 4448 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4449 ELS_MAX_PAYLOAD, 8, 0); 4450 4451 if (!ha->purex_dma_pool) { 4452 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4453 "Unable to allocate purex_dma_pool.\n"); 4454 goto fail_flt; 4455 } 4456 4457 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4458 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4459 ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL); 4460 4461 if (!ha->elsrej.c) { 4462 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4463 "Alloc failed for els reject cmd.\n"); 4464 goto fail_elsrej; 4465 } 4466 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4467 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4468 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4469 return 0; 4470 4471 fail_elsrej: 4472 dma_pool_destroy(ha->purex_dma_pool); 4473 fail_flt: 4474 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4475 ha->flt, ha->flt_dma); 4476 4477 fail_flt_buffer: 4478 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4479 ha->sfp_data, ha->sfp_data_dma); 4480 fail_sfp_data: 4481 kfree(ha->loop_id_map); 4482 fail_loop_id_map: 4483 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4484 fail_async_pd: 4485 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4486 fail_sf_init_cb: 4487 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4488 fail_ex_init_cb: 4489 kfree(ha->npiv_info); 4490 fail_npiv_info: 4491 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4492 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4493 (*rsp)->ring = NULL; 4494 (*rsp)->dma = 0; 4495 fail_rsp_ring: 4496 kfree(*rsp); 4497 *rsp = NULL; 4498 fail_rsp: 4499 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4500 sizeof(request_t), (*req)->ring, (*req)->dma); 4501 (*req)->ring = NULL; 4502 (*req)->dma = 0; 4503 fail_req_ring: 4504 kfree(*req); 4505 *req = NULL; 4506 fail_req: 4507 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4508 ha->ct_sns, ha->ct_sns_dma); 4509 ha->ct_sns = NULL; 4510 ha->ct_sns_dma = 0; 4511 fail_free_ms_iocb: 4512 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4513 ha->ms_iocb = NULL; 4514 ha->ms_iocb_dma = 0; 4515 4516 if (ha->sns_cmd) 4517 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4518 ha->sns_cmd, ha->sns_cmd_dma); 4519 fail_dma_pool: 4520 if (ql2xenabledif) { 4521 struct dsd_dma *dsd, *nxt; 4522 4523 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4524 list) { 4525 list_del(&dsd->list); 4526 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4527 dsd->dsd_list_dma); 4528 ha->dif_bundle_dma_allocs--; 4529 kfree(dsd); 4530 ha->dif_bundle_kallocs--; 4531 ha->pool.unusable.count--; 4532 } 4533 dma_pool_destroy(ha->dif_bundl_pool); 4534 ha->dif_bundl_pool = NULL; 4535 } 4536 4537 fail_dif_bundl_dma_pool: 4538 if (IS_QLA82XX(ha) || ql2xenabledif) { 4539 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4540 ha->fcp_cmnd_dma_pool = NULL; 4541 } 4542 fail_dl_dma_pool: 4543 if (IS_QLA82XX(ha) || ql2xenabledif) { 4544 dma_pool_destroy(ha->dl_dma_pool); 4545 ha->dl_dma_pool = NULL; 4546 } 4547 fail_s_dma_pool: 4548 dma_pool_destroy(ha->s_dma_pool); 4549 ha->s_dma_pool = NULL; 4550 fail_free_nvram: 4551 kfree(ha->nvram); 4552 ha->nvram = NULL; 4553 fail_free_ctx_mempool: 4554 mempool_destroy(ha->ctx_mempool); 4555 ha->ctx_mempool = NULL; 4556 fail_free_srb_mempool: 4557 mempool_destroy(ha->srb_mempool); 4558 ha->srb_mempool = NULL; 4559 fail_free_gid_list: 4560 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4561 ha->gid_list, 4562 ha->gid_list_dma); 4563 ha->gid_list = NULL; 4564 ha->gid_list_dma = 0; 4565 fail_free_tgt_mem: 4566 qlt_mem_free(ha); 4567 fail_free_btree: 4568 btree_destroy32(&ha->host_map); 4569 fail_free_init_cb: 4570 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4571 ha->init_cb_dma); 4572 ha->init_cb = NULL; 4573 ha->init_cb_dma = 0; 4574 fail_free_vp_map: 4575 kfree(ha->vp_map); 4576 fail: 4577 ql_log(ql_log_fatal, NULL, 0x0030, 4578 "Memory allocation failure.\n"); 4579 return -ENOMEM; 4580 } 4581 4582 int 4583 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4584 { 4585 int rval; 4586 uint16_t size, max_cnt; 4587 uint32_t temp; 4588 struct qla_hw_data *ha = vha->hw; 4589 4590 /* Return if we don't need to alloacate any extended logins */ 4591 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4592 return QLA_SUCCESS; 4593 4594 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4595 return QLA_SUCCESS; 4596 4597 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4598 max_cnt = 0; 4599 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4600 if (rval != QLA_SUCCESS) { 4601 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4602 "Failed to get exlogin status.\n"); 4603 return rval; 4604 } 4605 4606 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4607 temp *= size; 4608 4609 if (temp != ha->exlogin_size) { 4610 qla2x00_free_exlogin_buffer(ha); 4611 ha->exlogin_size = temp; 4612 4613 ql_log(ql_log_info, vha, 0xd024, 4614 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4615 max_cnt, size, temp); 4616 4617 ql_log(ql_log_info, vha, 0xd025, 4618 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4619 4620 /* Get consistent memory for extended logins */ 4621 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4622 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4623 if (!ha->exlogin_buf) { 4624 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4625 "Failed to allocate memory for exlogin_buf_dma.\n"); 4626 return -ENOMEM; 4627 } 4628 } 4629 4630 /* Now configure the dma buffer */ 4631 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4632 if (rval) { 4633 ql_log(ql_log_fatal, vha, 0xd033, 4634 "Setup extended login buffer ****FAILED****.\n"); 4635 qla2x00_free_exlogin_buffer(ha); 4636 } 4637 4638 return rval; 4639 } 4640 4641 /* 4642 * qla2x00_free_exlogin_buffer 4643 * 4644 * Input: 4645 * ha = adapter block pointer 4646 */ 4647 void 4648 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4649 { 4650 if (ha->exlogin_buf) { 4651 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4652 ha->exlogin_buf, ha->exlogin_buf_dma); 4653 ha->exlogin_buf = NULL; 4654 ha->exlogin_size = 0; 4655 } 4656 } 4657 4658 static void 4659 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4660 { 4661 u32 temp; 4662 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4663 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4664 4665 if (max_cnt > vha->hw->max_exchg) 4666 max_cnt = vha->hw->max_exchg; 4667 4668 if (qla_ini_mode_enabled(vha)) { 4669 if (vha->ql2xiniexchg > max_cnt) 4670 vha->ql2xiniexchg = max_cnt; 4671 4672 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4673 *ret_cnt = vha->ql2xiniexchg; 4674 4675 } else if (qla_tgt_mode_enabled(vha)) { 4676 if (vha->ql2xexchoffld > max_cnt) { 4677 vha->ql2xexchoffld = max_cnt; 4678 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4679 } 4680 4681 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4682 *ret_cnt = vha->ql2xexchoffld; 4683 } else if (qla_dual_mode_enabled(vha)) { 4684 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4685 if (temp > max_cnt) { 4686 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4687 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4688 temp = max_cnt; 4689 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4690 } 4691 4692 if (temp > FW_DEF_EXCHANGES_CNT) 4693 *ret_cnt = temp; 4694 } 4695 } 4696 4697 int 4698 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4699 { 4700 int rval; 4701 u16 size, max_cnt; 4702 u32 actual_cnt, totsz; 4703 struct qla_hw_data *ha = vha->hw; 4704 4705 if (!ha->flags.exchoffld_enabled) 4706 return QLA_SUCCESS; 4707 4708 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4709 return QLA_SUCCESS; 4710 4711 max_cnt = 0; 4712 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4713 if (rval != QLA_SUCCESS) { 4714 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4715 "Failed to get exlogin status.\n"); 4716 return rval; 4717 } 4718 4719 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4720 ql_log(ql_log_info, vha, 0xd014, 4721 "Actual exchange offload count: %d.\n", actual_cnt); 4722 4723 totsz = actual_cnt * size; 4724 4725 if (totsz != ha->exchoffld_size) { 4726 qla2x00_free_exchoffld_buffer(ha); 4727 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4728 ha->exchoffld_size = 0; 4729 ha->flags.exchoffld_enabled = 0; 4730 return QLA_SUCCESS; 4731 } 4732 4733 ha->exchoffld_size = totsz; 4734 4735 ql_log(ql_log_info, vha, 0xd016, 4736 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4737 max_cnt, actual_cnt, size, totsz); 4738 4739 ql_log(ql_log_info, vha, 0xd017, 4740 "Exchange Buffers requested size = 0x%x\n", 4741 ha->exchoffld_size); 4742 4743 /* Get consistent memory for extended logins */ 4744 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4745 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4746 if (!ha->exchoffld_buf) { 4747 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4748 "Failed to allocate memory for Exchange Offload.\n"); 4749 4750 if (ha->max_exchg > 4751 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4752 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4753 } else if (ha->max_exchg > 4754 (FW_DEF_EXCHANGES_CNT + 512)) { 4755 ha->max_exchg -= 512; 4756 } else { 4757 ha->flags.exchoffld_enabled = 0; 4758 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4759 "Disabling Exchange offload due to lack of memory\n"); 4760 } 4761 ha->exchoffld_size = 0; 4762 4763 return -ENOMEM; 4764 } 4765 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4766 /* pathological case */ 4767 qla2x00_free_exchoffld_buffer(ha); 4768 ha->exchoffld_size = 0; 4769 ha->flags.exchoffld_enabled = 0; 4770 ql_log(ql_log_info, vha, 0xd016, 4771 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4772 ha->exchoffld_size, actual_cnt, size, totsz); 4773 return 0; 4774 } 4775 4776 /* Now configure the dma buffer */ 4777 rval = qla_set_exchoffld_mem_cfg(vha); 4778 if (rval) { 4779 ql_log(ql_log_fatal, vha, 0xd02e, 4780 "Setup exchange offload buffer ****FAILED****.\n"); 4781 qla2x00_free_exchoffld_buffer(ha); 4782 } else { 4783 /* re-adjust number of target exchange */ 4784 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4785 4786 if (qla_ini_mode_enabled(vha)) 4787 icb->exchange_count = 0; 4788 else 4789 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4790 } 4791 4792 return rval; 4793 } 4794 4795 /* 4796 * qla2x00_free_exchoffld_buffer 4797 * 4798 * Input: 4799 * ha = adapter block pointer 4800 */ 4801 void 4802 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4803 { 4804 if (ha->exchoffld_buf) { 4805 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4806 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4807 ha->exchoffld_buf = NULL; 4808 ha->exchoffld_size = 0; 4809 } 4810 } 4811 4812 /* 4813 * qla2x00_free_fw_dump 4814 * Frees fw dump stuff. 4815 * 4816 * Input: 4817 * ha = adapter block pointer 4818 */ 4819 static void 4820 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4821 { 4822 struct fwdt *fwdt = ha->fwdt; 4823 uint j; 4824 4825 if (ha->fce) 4826 dma_free_coherent(&ha->pdev->dev, 4827 FCE_SIZE, ha->fce, ha->fce_dma); 4828 4829 if (ha->eft) 4830 dma_free_coherent(&ha->pdev->dev, 4831 EFT_SIZE, ha->eft, ha->eft_dma); 4832 4833 vfree(ha->fw_dump); 4834 4835 ha->fce = NULL; 4836 ha->fce_dma = 0; 4837 ha->flags.fce_enabled = 0; 4838 ha->eft = NULL; 4839 ha->eft_dma = 0; 4840 ha->fw_dumped = false; 4841 ha->fw_dump_cap_flags = 0; 4842 ha->fw_dump_reading = 0; 4843 ha->fw_dump = NULL; 4844 ha->fw_dump_len = 0; 4845 4846 for (j = 0; j < 2; j++, fwdt++) { 4847 vfree(fwdt->template); 4848 fwdt->template = NULL; 4849 fwdt->length = 0; 4850 } 4851 } 4852 4853 /* 4854 * qla2x00_mem_free 4855 * Frees all adapter allocated memory. 4856 * 4857 * Input: 4858 * ha = adapter block pointer. 4859 */ 4860 static void 4861 qla2x00_mem_free(struct qla_hw_data *ha) 4862 { 4863 qla2x00_free_fw_dump(ha); 4864 4865 if (ha->mctp_dump) 4866 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4867 ha->mctp_dump_dma); 4868 ha->mctp_dump = NULL; 4869 4870 mempool_destroy(ha->srb_mempool); 4871 ha->srb_mempool = NULL; 4872 4873 if (ha->dcbx_tlv) 4874 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4875 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4876 ha->dcbx_tlv = NULL; 4877 4878 if (ha->xgmac_data) 4879 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4880 ha->xgmac_data, ha->xgmac_data_dma); 4881 ha->xgmac_data = NULL; 4882 4883 if (ha->sns_cmd) 4884 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4885 ha->sns_cmd, ha->sns_cmd_dma); 4886 ha->sns_cmd = NULL; 4887 ha->sns_cmd_dma = 0; 4888 4889 if (ha->ct_sns) 4890 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4891 ha->ct_sns, ha->ct_sns_dma); 4892 ha->ct_sns = NULL; 4893 ha->ct_sns_dma = 0; 4894 4895 if (ha->sfp_data) 4896 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4897 ha->sfp_data_dma); 4898 ha->sfp_data = NULL; 4899 4900 if (ha->flt) 4901 dma_free_coherent(&ha->pdev->dev, 4902 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4903 ha->flt, ha->flt_dma); 4904 ha->flt = NULL; 4905 ha->flt_dma = 0; 4906 4907 if (ha->ms_iocb) 4908 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4909 ha->ms_iocb = NULL; 4910 ha->ms_iocb_dma = 0; 4911 4912 if (ha->sf_init_cb) 4913 dma_pool_free(ha->s_dma_pool, 4914 ha->sf_init_cb, ha->sf_init_cb_dma); 4915 4916 if (ha->ex_init_cb) 4917 dma_pool_free(ha->s_dma_pool, 4918 ha->ex_init_cb, ha->ex_init_cb_dma); 4919 ha->ex_init_cb = NULL; 4920 ha->ex_init_cb_dma = 0; 4921 4922 if (ha->async_pd) 4923 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4924 ha->async_pd = NULL; 4925 ha->async_pd_dma = 0; 4926 4927 dma_pool_destroy(ha->s_dma_pool); 4928 ha->s_dma_pool = NULL; 4929 4930 if (ha->gid_list) 4931 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4932 ha->gid_list, ha->gid_list_dma); 4933 ha->gid_list = NULL; 4934 ha->gid_list_dma = 0; 4935 4936 if (IS_QLA82XX(ha)) { 4937 if (!list_empty(&ha->gbl_dsd_list)) { 4938 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4939 4940 /* clean up allocated prev pool */ 4941 list_for_each_entry_safe(dsd_ptr, 4942 tdsd_ptr, &ha->gbl_dsd_list, list) { 4943 dma_pool_free(ha->dl_dma_pool, 4944 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4945 list_del(&dsd_ptr->list); 4946 kfree(dsd_ptr); 4947 } 4948 } 4949 } 4950 4951 dma_pool_destroy(ha->dl_dma_pool); 4952 ha->dl_dma_pool = NULL; 4953 4954 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4955 ha->fcp_cmnd_dma_pool = NULL; 4956 4957 mempool_destroy(ha->ctx_mempool); 4958 ha->ctx_mempool = NULL; 4959 4960 if (ql2xenabledif && ha->dif_bundl_pool) { 4961 struct dsd_dma *dsd, *nxt; 4962 4963 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4964 list) { 4965 list_del(&dsd->list); 4966 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4967 dsd->dsd_list_dma); 4968 ha->dif_bundle_dma_allocs--; 4969 kfree(dsd); 4970 ha->dif_bundle_kallocs--; 4971 ha->pool.unusable.count--; 4972 } 4973 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4974 list_del(&dsd->list); 4975 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4976 dsd->dsd_list_dma); 4977 ha->dif_bundle_dma_allocs--; 4978 kfree(dsd); 4979 ha->dif_bundle_kallocs--; 4980 } 4981 } 4982 4983 dma_pool_destroy(ha->dif_bundl_pool); 4984 ha->dif_bundl_pool = NULL; 4985 4986 qlt_mem_free(ha); 4987 qla_remove_hostmap(ha); 4988 4989 if (ha->init_cb) 4990 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4991 ha->init_cb, ha->init_cb_dma); 4992 4993 dma_pool_destroy(ha->purex_dma_pool); 4994 ha->purex_dma_pool = NULL; 4995 4996 if (ha->elsrej.c) { 4997 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4998 ha->elsrej.c, ha->elsrej.cdma); 4999 ha->elsrej.c = NULL; 5000 } 5001 5002 ha->init_cb = NULL; 5003 ha->init_cb_dma = 0; 5004 5005 vfree(ha->optrom_buffer); 5006 ha->optrom_buffer = NULL; 5007 kfree(ha->nvram); 5008 ha->nvram = NULL; 5009 kfree(ha->npiv_info); 5010 ha->npiv_info = NULL; 5011 kfree(ha->swl); 5012 ha->swl = NULL; 5013 kfree(ha->loop_id_map); 5014 ha->sf_init_cb = NULL; 5015 ha->sf_init_cb_dma = 0; 5016 ha->loop_id_map = NULL; 5017 5018 kfree(ha->vp_map); 5019 ha->vp_map = NULL; 5020 } 5021 5022 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht, 5023 struct qla_hw_data *ha) 5024 { 5025 struct Scsi_Host *host; 5026 struct scsi_qla_host *vha = NULL; 5027 5028 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 5029 if (!host) { 5030 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 5031 "Failed to allocate host from the scsi layer, aborting.\n"); 5032 return NULL; 5033 } 5034 5035 /* Clear our data area */ 5036 vha = shost_priv(host); 5037 memset(vha, 0, sizeof(scsi_qla_host_t)); 5038 5039 vha->host = host; 5040 vha->host_no = host->host_no; 5041 vha->hw = ha; 5042 5043 vha->qlini_mode = ql2x_ini_mode; 5044 vha->ql2xexchoffld = ql2xexchoffld; 5045 vha->ql2xiniexchg = ql2xiniexchg; 5046 5047 INIT_LIST_HEAD(&vha->vp_fcports); 5048 INIT_LIST_HEAD(&vha->work_list); 5049 INIT_LIST_HEAD(&vha->list); 5050 INIT_LIST_HEAD(&vha->qla_cmd_list); 5051 INIT_LIST_HEAD(&vha->logo_list); 5052 INIT_LIST_HEAD(&vha->plogi_ack_list); 5053 INIT_LIST_HEAD(&vha->qp_list); 5054 INIT_LIST_HEAD(&vha->gnl.fcports); 5055 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 5056 5057 INIT_LIST_HEAD(&vha->purex_list.head); 5058 spin_lock_init(&vha->purex_list.lock); 5059 5060 spin_lock_init(&vha->work_lock); 5061 spin_lock_init(&vha->cmd_list_lock); 5062 init_waitqueue_head(&vha->fcport_waitQ); 5063 init_waitqueue_head(&vha->vref_waitq); 5064 qla_enode_init(vha); 5065 qla_edb_init(vha); 5066 5067 5068 vha->gnl.size = sizeof(struct get_name_list_extended) * 5069 (ha->max_loop_id + 1); 5070 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 5071 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 5072 if (!vha->gnl.l) { 5073 ql_log(ql_log_fatal, vha, 0xd04a, 5074 "Alloc failed for name list.\n"); 5075 scsi_host_put(vha->host); 5076 return NULL; 5077 } 5078 5079 /* todo: what about ext login? */ 5080 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 5081 vha->scan.l = vmalloc(vha->scan.size); 5082 if (!vha->scan.l) { 5083 ql_log(ql_log_fatal, vha, 0xd04a, 5084 "Alloc failed for scan database.\n"); 5085 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 5086 vha->gnl.l, vha->gnl.ldma); 5087 vha->gnl.l = NULL; 5088 scsi_host_put(vha->host); 5089 return NULL; 5090 } 5091 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5092 5093 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); 5094 ql_dbg(ql_dbg_init, vha, 0x0041, 5095 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5096 vha->host, vha->hw, vha, 5097 dev_name(&(ha->pdev->dev))); 5098 5099 return vha; 5100 } 5101 5102 struct qla_work_evt * 5103 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5104 { 5105 struct qla_work_evt *e; 5106 5107 if (test_bit(UNLOADING, &vha->dpc_flags)) 5108 return NULL; 5109 5110 if (qla_vha_mark_busy(vha)) 5111 return NULL; 5112 5113 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5114 if (!e) { 5115 QLA_VHA_MARK_NOT_BUSY(vha); 5116 return NULL; 5117 } 5118 5119 INIT_LIST_HEAD(&e->list); 5120 e->type = type; 5121 e->flags = QLA_EVT_FLAG_FREE; 5122 return e; 5123 } 5124 5125 int 5126 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5127 { 5128 unsigned long flags; 5129 bool q = false; 5130 5131 spin_lock_irqsave(&vha->work_lock, flags); 5132 list_add_tail(&e->list, &vha->work_list); 5133 5134 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5135 q = true; 5136 5137 spin_unlock_irqrestore(&vha->work_lock, flags); 5138 5139 if (q) 5140 queue_work(vha->hw->wq, &vha->iocb_work); 5141 5142 return QLA_SUCCESS; 5143 } 5144 5145 int 5146 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5147 u32 data) 5148 { 5149 struct qla_work_evt *e; 5150 5151 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5152 if (!e) 5153 return QLA_FUNCTION_FAILED; 5154 5155 e->u.aen.code = code; 5156 e->u.aen.data = data; 5157 return qla2x00_post_work(vha, e); 5158 } 5159 5160 int 5161 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5162 { 5163 struct qla_work_evt *e; 5164 5165 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5166 if (!e) 5167 return QLA_FUNCTION_FAILED; 5168 5169 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5170 return qla2x00_post_work(vha, e); 5171 } 5172 5173 #define qla2x00_post_async_work(name, type) \ 5174 int qla2x00_post_async_##name##_work( \ 5175 struct scsi_qla_host *vha, \ 5176 fc_port_t *fcport, uint16_t *data) \ 5177 { \ 5178 struct qla_work_evt *e; \ 5179 \ 5180 e = qla2x00_alloc_work(vha, type); \ 5181 if (!e) \ 5182 return QLA_FUNCTION_FAILED; \ 5183 \ 5184 e->u.logio.fcport = fcport; \ 5185 if (data) { \ 5186 e->u.logio.data[0] = data[0]; \ 5187 e->u.logio.data[1] = data[1]; \ 5188 } \ 5189 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5190 return qla2x00_post_work(vha, e); \ 5191 } 5192 5193 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5194 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5195 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5196 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5197 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5198 5199 int 5200 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5201 { 5202 struct qla_work_evt *e; 5203 5204 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5205 if (!e) 5206 return QLA_FUNCTION_FAILED; 5207 5208 e->u.uevent.code = code; 5209 return qla2x00_post_work(vha, e); 5210 } 5211 5212 static void 5213 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5214 { 5215 char event_string[40]; 5216 char *envp[] = { event_string, NULL }; 5217 5218 switch (code) { 5219 case QLA_UEVENT_CODE_FW_DUMP: 5220 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5221 vha->host_no); 5222 break; 5223 default: 5224 /* do nothing */ 5225 break; 5226 } 5227 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5228 } 5229 5230 int 5231 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5232 uint32_t *data, int cnt) 5233 { 5234 struct qla_work_evt *e; 5235 5236 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5237 if (!e) 5238 return QLA_FUNCTION_FAILED; 5239 5240 e->u.aenfx.evtcode = evtcode; 5241 e->u.aenfx.count = cnt; 5242 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5243 return qla2x00_post_work(vha, e); 5244 } 5245 5246 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5247 { 5248 unsigned long flags; 5249 5250 if (IS_SW_RESV_ADDR(fcport->d_id)) 5251 return; 5252 5253 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5254 if (fcport->disc_state == DSC_UPD_FCPORT) { 5255 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5256 return; 5257 } 5258 fcport->jiffies_at_registration = jiffies; 5259 fcport->sec_since_registration = 0; 5260 fcport->next_disc_state = DSC_DELETED; 5261 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5262 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5263 5264 queue_work(system_unbound_wq, &fcport->reg_work); 5265 } 5266 5267 static 5268 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5269 { 5270 unsigned long flags; 5271 fc_port_t *fcport = NULL, *tfcp; 5272 struct qlt_plogi_ack_t *pla = 5273 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5274 uint8_t free_fcport = 0; 5275 5276 ql_dbg(ql_dbg_disc, vha, 0xffff, 5277 "%s %d %8phC enter\n", 5278 __func__, __LINE__, e->u.new_sess.port_name); 5279 5280 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5281 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5282 if (fcport) { 5283 fcport->d_id = e->u.new_sess.id; 5284 if (pla) { 5285 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5286 memcpy(fcport->node_name, 5287 pla->iocb.u.isp24.u.plogi.node_name, 5288 WWN_SIZE); 5289 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5290 /* we took an extra ref_count to prevent PLOGI ACK when 5291 * fcport/sess has not been created. 5292 */ 5293 pla->ref_count--; 5294 } 5295 } else { 5296 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5297 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5298 if (fcport) { 5299 fcport->d_id = e->u.new_sess.id; 5300 fcport->flags |= FCF_FABRIC_DEVICE; 5301 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5302 fcport->tgt_short_link_down_cnt = 0; 5303 5304 memcpy(fcport->port_name, e->u.new_sess.port_name, 5305 WWN_SIZE); 5306 5307 fcport->fc4_type = e->u.new_sess.fc4_type; 5308 if (NVME_PRIORITY(vha->hw, fcport)) 5309 fcport->do_prli_nvme = 1; 5310 else 5311 fcport->do_prli_nvme = 0; 5312 5313 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5314 fcport->dm_login_expire = jiffies + 5315 QLA_N2N_WAIT_TIME * HZ; 5316 fcport->fc4_type = FS_FC4TYPE_FCP; 5317 fcport->n2n_flag = 1; 5318 if (vha->flags.nvme_enabled) 5319 fcport->fc4_type |= FS_FC4TYPE_NVME; 5320 } 5321 5322 } else { 5323 ql_dbg(ql_dbg_disc, vha, 0xffff, 5324 "%s %8phC mem alloc fail.\n", 5325 __func__, e->u.new_sess.port_name); 5326 5327 if (pla) { 5328 list_del(&pla->list); 5329 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5330 } 5331 return; 5332 } 5333 5334 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5335 /* search again to make sure no one else got ahead */ 5336 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5337 e->u.new_sess.port_name, 1); 5338 if (tfcp) { 5339 /* should rarily happen */ 5340 ql_dbg(ql_dbg_disc, vha, 0xffff, 5341 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5342 __func__, tfcp->port_name, tfcp->disc_state, 5343 tfcp->fw_login_state); 5344 5345 free_fcport = 1; 5346 } else { 5347 list_add_tail(&fcport->list, &vha->vp_fcports); 5348 5349 } 5350 if (pla) { 5351 qlt_plogi_ack_link(vha, pla, fcport, 5352 QLT_PLOGI_LINK_SAME_WWN); 5353 pla->ref_count--; 5354 } 5355 } 5356 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5357 5358 if (fcport) { 5359 fcport->id_changed = 1; 5360 fcport->scan_state = QLA_FCPORT_FOUND; 5361 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5362 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5363 5364 if (pla) { 5365 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5366 u16 wd3_lo; 5367 5368 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5369 fcport->local = 0; 5370 fcport->loop_id = 5371 le16_to_cpu( 5372 pla->iocb.u.isp24.nport_handle); 5373 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5374 wd3_lo = 5375 le16_to_cpu( 5376 pla->iocb.u.isp24.u.prli.wd3_lo); 5377 5378 if (wd3_lo & BIT_7) 5379 fcport->conf_compl_supported = 1; 5380 5381 if ((wd3_lo & BIT_4) == 0) 5382 fcport->port_type = FCT_INITIATOR; 5383 else 5384 fcport->port_type = FCT_TARGET; 5385 } 5386 qlt_plogi_ack_unref(vha, pla); 5387 } else { 5388 fc_port_t *dfcp = NULL; 5389 5390 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5391 tfcp = qla2x00_find_fcport_by_nportid(vha, 5392 &e->u.new_sess.id, 1); 5393 if (tfcp && (tfcp != fcport)) { 5394 /* 5395 * We have a conflict fcport with same NportID. 5396 */ 5397 ql_dbg(ql_dbg_disc, vha, 0xffff, 5398 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5399 __func__, tfcp->port_name, tfcp->disc_state, 5400 tfcp->fw_login_state); 5401 5402 switch (tfcp->disc_state) { 5403 case DSC_DELETED: 5404 break; 5405 case DSC_DELETE_PEND: 5406 fcport->login_pause = 1; 5407 tfcp->conflict = fcport; 5408 break; 5409 default: 5410 fcport->login_pause = 1; 5411 tfcp->conflict = fcport; 5412 dfcp = tfcp; 5413 break; 5414 } 5415 } 5416 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5417 if (dfcp) 5418 qlt_schedule_sess_for_deletion(tfcp); 5419 5420 if (N2N_TOPO(vha->hw)) { 5421 fcport->flags &= ~FCF_FABRIC_DEVICE; 5422 fcport->keep_nport_handle = 1; 5423 if (vha->flags.nvme_enabled) { 5424 fcport->fc4_type = 5425 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5426 fcport->n2n_flag = 1; 5427 } 5428 fcport->fw_login_state = 0; 5429 5430 schedule_delayed_work(&vha->scan.scan_work, 5); 5431 } else { 5432 qla24xx_fcport_handle_login(vha, fcport); 5433 } 5434 } 5435 } 5436 5437 if (free_fcport) { 5438 qla2x00_free_fcport(fcport); 5439 if (pla) { 5440 list_del(&pla->list); 5441 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5442 } 5443 } 5444 } 5445 5446 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5447 { 5448 struct srb *sp = e->u.iosb.sp; 5449 int rval; 5450 5451 rval = qla2x00_start_sp(sp); 5452 if (rval != QLA_SUCCESS) { 5453 ql_dbg(ql_dbg_disc, vha, 0x2043, 5454 "%s: %s: Re-issue IOCB failed (%d).\n", 5455 __func__, sp->name, rval); 5456 qla24xx_sp_unmap(vha, sp); 5457 } 5458 } 5459 5460 void 5461 qla2x00_do_work(struct scsi_qla_host *vha) 5462 { 5463 struct qla_work_evt *e, *tmp; 5464 unsigned long flags; 5465 LIST_HEAD(work); 5466 int rc; 5467 5468 spin_lock_irqsave(&vha->work_lock, flags); 5469 list_splice_init(&vha->work_list, &work); 5470 spin_unlock_irqrestore(&vha->work_lock, flags); 5471 5472 list_for_each_entry_safe(e, tmp, &work, list) { 5473 rc = QLA_SUCCESS; 5474 switch (e->type) { 5475 case QLA_EVT_AEN: 5476 fc_host_post_event(vha->host, fc_get_event_number(), 5477 e->u.aen.code, e->u.aen.data); 5478 break; 5479 case QLA_EVT_IDC_ACK: 5480 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5481 break; 5482 case QLA_EVT_ASYNC_LOGIN: 5483 qla2x00_async_login(vha, e->u.logio.fcport, 5484 e->u.logio.data); 5485 break; 5486 case QLA_EVT_ASYNC_LOGOUT: 5487 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5488 break; 5489 case QLA_EVT_ASYNC_ADISC: 5490 qla2x00_async_adisc(vha, e->u.logio.fcport, 5491 e->u.logio.data); 5492 break; 5493 case QLA_EVT_UEVENT: 5494 qla2x00_uevent_emit(vha, e->u.uevent.code); 5495 break; 5496 case QLA_EVT_AENFX: 5497 qlafx00_process_aen(vha, e); 5498 break; 5499 case QLA_EVT_UNMAP: 5500 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5501 break; 5502 case QLA_EVT_RELOGIN: 5503 qla2x00_relogin(vha); 5504 break; 5505 case QLA_EVT_NEW_SESS: 5506 qla24xx_create_new_sess(vha, e); 5507 break; 5508 case QLA_EVT_GPDB: 5509 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5510 e->u.fcport.opt); 5511 break; 5512 case QLA_EVT_PRLI: 5513 qla24xx_async_prli(vha, e->u.fcport.fcport); 5514 break; 5515 case QLA_EVT_GPSC: 5516 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5517 break; 5518 case QLA_EVT_GNL: 5519 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5520 break; 5521 case QLA_EVT_NACK: 5522 qla24xx_do_nack_work(vha, e); 5523 break; 5524 case QLA_EVT_ASYNC_PRLO: 5525 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5526 break; 5527 case QLA_EVT_ASYNC_PRLO_DONE: 5528 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5529 e->u.logio.data); 5530 break; 5531 case QLA_EVT_GPNFT: 5532 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5533 e->u.gpnft.sp); 5534 break; 5535 case QLA_EVT_GPNFT_DONE: 5536 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5537 break; 5538 case QLA_EVT_GNNFT_DONE: 5539 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5540 break; 5541 case QLA_EVT_GFPNID: 5542 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5543 break; 5544 case QLA_EVT_SP_RETRY: 5545 qla_sp_retry(vha, e); 5546 break; 5547 case QLA_EVT_IIDMA: 5548 qla_do_iidma_work(vha, e->u.fcport.fcport); 5549 break; 5550 case QLA_EVT_ELS_PLOGI: 5551 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5552 e->u.fcport.fcport, false); 5553 break; 5554 case QLA_EVT_SA_REPLACE: 5555 rc = qla24xx_issue_sa_replace_iocb(vha, e); 5556 break; 5557 } 5558 5559 if (rc == EAGAIN) { 5560 /* put 'work' at head of 'vha->work_list' */ 5561 spin_lock_irqsave(&vha->work_lock, flags); 5562 list_splice(&work, &vha->work_list); 5563 spin_unlock_irqrestore(&vha->work_lock, flags); 5564 break; 5565 } 5566 list_del_init(&e->list); 5567 if (e->flags & QLA_EVT_FLAG_FREE) 5568 kfree(e); 5569 5570 /* For each work completed decrement vha ref count */ 5571 QLA_VHA_MARK_NOT_BUSY(vha); 5572 } 5573 } 5574 5575 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5576 { 5577 struct qla_work_evt *e; 5578 5579 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5580 5581 if (!e) { 5582 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5583 return QLA_FUNCTION_FAILED; 5584 } 5585 5586 return qla2x00_post_work(vha, e); 5587 } 5588 5589 /* Relogins all the fcports of a vport 5590 * Context: dpc thread 5591 */ 5592 void qla2x00_relogin(struct scsi_qla_host *vha) 5593 { 5594 fc_port_t *fcport; 5595 int status, relogin_needed = 0; 5596 struct event_arg ea; 5597 5598 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5599 /* 5600 * If the port is not ONLINE then try to login 5601 * to it if we haven't run out of retries. 5602 */ 5603 if (atomic_read(&fcport->state) != FCS_ONLINE && 5604 fcport->login_retry) { 5605 if (fcport->scan_state != QLA_FCPORT_FOUND || 5606 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5607 fcport->disc_state == DSC_LOGIN_COMPLETE) 5608 continue; 5609 5610 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5611 fcport->disc_state == DSC_DELETE_PEND) { 5612 relogin_needed = 1; 5613 } else { 5614 if (vha->hw->current_topology != ISP_CFG_NL) { 5615 memset(&ea, 0, sizeof(ea)); 5616 ea.fcport = fcport; 5617 qla24xx_handle_relogin_event(vha, &ea); 5618 } else if (vha->hw->current_topology == 5619 ISP_CFG_NL && 5620 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5621 (void)qla24xx_fcport_handle_login(vha, 5622 fcport); 5623 } else if (vha->hw->current_topology == 5624 ISP_CFG_NL) { 5625 fcport->login_retry--; 5626 status = 5627 qla2x00_local_device_login(vha, 5628 fcport); 5629 if (status == QLA_SUCCESS) { 5630 fcport->old_loop_id = 5631 fcport->loop_id; 5632 ql_dbg(ql_dbg_disc, vha, 0x2003, 5633 "Port login OK: logged in ID 0x%x.\n", 5634 fcport->loop_id); 5635 qla2x00_update_fcport 5636 (vha, fcport); 5637 } else if (status == 1) { 5638 set_bit(RELOGIN_NEEDED, 5639 &vha->dpc_flags); 5640 /* retry the login again */ 5641 ql_dbg(ql_dbg_disc, vha, 0x2007, 5642 "Retrying %d login again loop_id 0x%x.\n", 5643 fcport->login_retry, 5644 fcport->loop_id); 5645 } else { 5646 fcport->login_retry = 0; 5647 } 5648 5649 if (fcport->login_retry == 0 && 5650 status != QLA_SUCCESS) 5651 qla2x00_clear_loop_id(fcport); 5652 } 5653 } 5654 } 5655 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5656 break; 5657 } 5658 5659 if (relogin_needed) 5660 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5661 5662 ql_dbg(ql_dbg_disc, vha, 0x400e, 5663 "Relogin end.\n"); 5664 } 5665 5666 /* Schedule work on any of the dpc-workqueues */ 5667 void 5668 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5669 { 5670 struct qla_hw_data *ha = base_vha->hw; 5671 5672 switch (work_code) { 5673 case MBA_IDC_AEN: /* 0x8200 */ 5674 if (ha->dpc_lp_wq) 5675 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5676 break; 5677 5678 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5679 if (!ha->flags.nic_core_reset_hdlr_active) { 5680 if (ha->dpc_hp_wq) 5681 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5682 } else 5683 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5684 "NIC Core reset is already active. Skip " 5685 "scheduling it again.\n"); 5686 break; 5687 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5688 if (ha->dpc_hp_wq) 5689 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5690 break; 5691 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5692 if (ha->dpc_hp_wq) 5693 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5694 break; 5695 default: 5696 ql_log(ql_log_warn, base_vha, 0xb05f, 5697 "Unknown work-code=0x%x.\n", work_code); 5698 } 5699 5700 return; 5701 } 5702 5703 /* Work: Perform NIC Core Unrecoverable state handling */ 5704 void 5705 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5706 { 5707 struct qla_hw_data *ha = 5708 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5709 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5710 uint32_t dev_state = 0; 5711 5712 qla83xx_idc_lock(base_vha, 0); 5713 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5714 qla83xx_reset_ownership(base_vha); 5715 if (ha->flags.nic_core_reset_owner) { 5716 ha->flags.nic_core_reset_owner = 0; 5717 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5718 QLA8XXX_DEV_FAILED); 5719 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5720 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5721 } 5722 qla83xx_idc_unlock(base_vha, 0); 5723 } 5724 5725 /* Work: Execute IDC state handler */ 5726 void 5727 qla83xx_idc_state_handler_work(struct work_struct *work) 5728 { 5729 struct qla_hw_data *ha = 5730 container_of(work, struct qla_hw_data, idc_state_handler); 5731 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5732 uint32_t dev_state = 0; 5733 5734 qla83xx_idc_lock(base_vha, 0); 5735 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5736 if (dev_state == QLA8XXX_DEV_FAILED || 5737 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5738 qla83xx_idc_state_handler(base_vha); 5739 qla83xx_idc_unlock(base_vha, 0); 5740 } 5741 5742 static int 5743 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5744 { 5745 int rval = QLA_SUCCESS; 5746 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5747 uint32_t heart_beat_counter1, heart_beat_counter2; 5748 5749 do { 5750 if (time_after(jiffies, heart_beat_wait)) { 5751 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5752 "Nic Core f/w is not alive.\n"); 5753 rval = QLA_FUNCTION_FAILED; 5754 break; 5755 } 5756 5757 qla83xx_idc_lock(base_vha, 0); 5758 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5759 &heart_beat_counter1); 5760 qla83xx_idc_unlock(base_vha, 0); 5761 msleep(100); 5762 qla83xx_idc_lock(base_vha, 0); 5763 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5764 &heart_beat_counter2); 5765 qla83xx_idc_unlock(base_vha, 0); 5766 } while (heart_beat_counter1 == heart_beat_counter2); 5767 5768 return rval; 5769 } 5770 5771 /* Work: Perform NIC Core Reset handling */ 5772 void 5773 qla83xx_nic_core_reset_work(struct work_struct *work) 5774 { 5775 struct qla_hw_data *ha = 5776 container_of(work, struct qla_hw_data, nic_core_reset); 5777 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5778 uint32_t dev_state = 0; 5779 5780 if (IS_QLA2031(ha)) { 5781 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5782 ql_log(ql_log_warn, base_vha, 0xb081, 5783 "Failed to dump mctp\n"); 5784 return; 5785 } 5786 5787 if (!ha->flags.nic_core_reset_hdlr_active) { 5788 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5789 qla83xx_idc_lock(base_vha, 0); 5790 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5791 &dev_state); 5792 qla83xx_idc_unlock(base_vha, 0); 5793 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5794 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5795 "Nic Core f/w is alive.\n"); 5796 return; 5797 } 5798 } 5799 5800 ha->flags.nic_core_reset_hdlr_active = 1; 5801 if (qla83xx_nic_core_reset(base_vha)) { 5802 /* NIC Core reset failed. */ 5803 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5804 "NIC Core reset failed.\n"); 5805 } 5806 ha->flags.nic_core_reset_hdlr_active = 0; 5807 } 5808 } 5809 5810 /* Work: Handle 8200 IDC aens */ 5811 void 5812 qla83xx_service_idc_aen(struct work_struct *work) 5813 { 5814 struct qla_hw_data *ha = 5815 container_of(work, struct qla_hw_data, idc_aen); 5816 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5817 uint32_t dev_state, idc_control; 5818 5819 qla83xx_idc_lock(base_vha, 0); 5820 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5821 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5822 qla83xx_idc_unlock(base_vha, 0); 5823 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5824 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5825 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5826 "Application requested NIC Core Reset.\n"); 5827 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5828 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5829 QLA_SUCCESS) { 5830 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5831 "Other protocol driver requested NIC Core Reset.\n"); 5832 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5833 } 5834 } else if (dev_state == QLA8XXX_DEV_FAILED || 5835 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5836 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5837 } 5838 } 5839 5840 /* 5841 * Control the frequency of IDC lock retries 5842 */ 5843 #define QLA83XX_WAIT_LOGIC_MS 100 5844 5845 static int 5846 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5847 { 5848 int rval; 5849 uint32_t data; 5850 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5851 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5852 struct qla_hw_data *ha = base_vha->hw; 5853 5854 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5855 "Trying force recovery of the IDC lock.\n"); 5856 5857 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5858 if (rval) 5859 return rval; 5860 5861 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5862 return QLA_SUCCESS; 5863 } else { 5864 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5865 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5866 data); 5867 if (rval) 5868 return rval; 5869 5870 msleep(200); 5871 5872 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5873 &data); 5874 if (rval) 5875 return rval; 5876 5877 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5878 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5879 ~(idc_lck_rcvry_stage_mask)); 5880 rval = qla83xx_wr_reg(base_vha, 5881 QLA83XX_IDC_LOCK_RECOVERY, data); 5882 if (rval) 5883 return rval; 5884 5885 /* Forcefully perform IDC UnLock */ 5886 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5887 &data); 5888 if (rval) 5889 return rval; 5890 /* Clear lock-id by setting 0xff */ 5891 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5892 0xff); 5893 if (rval) 5894 return rval; 5895 /* Clear lock-recovery by setting 0x0 */ 5896 rval = qla83xx_wr_reg(base_vha, 5897 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5898 if (rval) 5899 return rval; 5900 } else 5901 return QLA_SUCCESS; 5902 } 5903 5904 return rval; 5905 } 5906 5907 static int 5908 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5909 { 5910 int rval = QLA_SUCCESS; 5911 uint32_t o_drv_lockid, n_drv_lockid; 5912 unsigned long lock_recovery_timeout; 5913 5914 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5915 retry_lockid: 5916 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5917 if (rval) 5918 goto exit; 5919 5920 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5921 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5922 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5923 return QLA_SUCCESS; 5924 else 5925 return QLA_FUNCTION_FAILED; 5926 } 5927 5928 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5929 if (rval) 5930 goto exit; 5931 5932 if (o_drv_lockid == n_drv_lockid) { 5933 msleep(QLA83XX_WAIT_LOGIC_MS); 5934 goto retry_lockid; 5935 } else 5936 return QLA_SUCCESS; 5937 5938 exit: 5939 return rval; 5940 } 5941 5942 /* 5943 * Context: task, can sleep 5944 */ 5945 void 5946 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5947 { 5948 uint32_t data; 5949 uint32_t lock_owner; 5950 struct qla_hw_data *ha = base_vha->hw; 5951 5952 might_sleep(); 5953 5954 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5955 retry_lock: 5956 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5957 == QLA_SUCCESS) { 5958 if (data) { 5959 /* Setting lock-id to our function-number */ 5960 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5961 ha->portnum); 5962 } else { 5963 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5964 &lock_owner); 5965 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5966 "Failed to acquire IDC lock, acquired by %d, " 5967 "retrying...\n", lock_owner); 5968 5969 /* Retry/Perform IDC-Lock recovery */ 5970 if (qla83xx_idc_lock_recovery(base_vha) 5971 == QLA_SUCCESS) { 5972 msleep(QLA83XX_WAIT_LOGIC_MS); 5973 goto retry_lock; 5974 } else 5975 ql_log(ql_log_warn, base_vha, 0xb075, 5976 "IDC Lock recovery FAILED.\n"); 5977 } 5978 5979 } 5980 5981 return; 5982 } 5983 5984 static bool 5985 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5986 struct purex_entry_24xx *purex) 5987 { 5988 char fwstr[16]; 5989 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5990 struct port_database_24xx *pdb; 5991 5992 /* Domain Controller is always logged-out. */ 5993 /* if RDP request is not from Domain Controller: */ 5994 if (sid != 0xfffc01) 5995 return false; 5996 5997 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5998 5999 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 6000 if (!pdb) { 6001 ql_dbg(ql_dbg_init, vha, 0x0181, 6002 "%s: Failed allocate pdb\n", __func__); 6003 } else if (qla24xx_get_port_database(vha, 6004 le16_to_cpu(purex->nport_handle), pdb)) { 6005 ql_dbg(ql_dbg_init, vha, 0x0181, 6006 "%s: Failed get pdb sid=%x\n", __func__, sid); 6007 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 6008 pdb->current_login_state != PDS_PRLI_COMPLETE) { 6009 ql_dbg(ql_dbg_init, vha, 0x0181, 6010 "%s: Port not logged in sid=%#x\n", __func__, sid); 6011 } else { 6012 /* RDP request is from logged in port */ 6013 kfree(pdb); 6014 return false; 6015 } 6016 kfree(pdb); 6017 6018 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 6019 fwstr[strcspn(fwstr, " ")] = 0; 6020 /* if FW version allows RDP response length upto 2048 bytes: */ 6021 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 6022 return false; 6023 6024 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 6025 6026 /* RDP response length is to be reduced to maximum 256 bytes */ 6027 return true; 6028 } 6029 6030 /* 6031 * Function Name: qla24xx_process_purex_iocb 6032 * 6033 * Description: 6034 * Prepare a RDP response and send to Fabric switch 6035 * 6036 * PARAMETERS: 6037 * vha: SCSI qla host 6038 * purex: RDP request received by HBA 6039 */ 6040 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 6041 struct purex_item *item) 6042 { 6043 struct qla_hw_data *ha = vha->hw; 6044 struct purex_entry_24xx *purex = 6045 (struct purex_entry_24xx *)&item->iocb; 6046 dma_addr_t rsp_els_dma; 6047 dma_addr_t rsp_payload_dma; 6048 dma_addr_t stat_dma; 6049 dma_addr_t sfp_dma; 6050 struct els_entry_24xx *rsp_els = NULL; 6051 struct rdp_rsp_payload *rsp_payload = NULL; 6052 struct link_statistics *stat = NULL; 6053 uint8_t *sfp = NULL; 6054 uint16_t sfp_flags = 0; 6055 uint rsp_payload_length = sizeof(*rsp_payload); 6056 int rval; 6057 6058 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 6059 "%s: Enter\n", __func__); 6060 6061 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 6062 "-------- ELS REQ -------\n"); 6063 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 6064 purex, sizeof(*purex)); 6065 6066 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 6067 rsp_payload_length = 6068 offsetof(typeof(*rsp_payload), optical_elmt_desc); 6069 ql_dbg(ql_dbg_init, vha, 0x0181, 6070 "Reducing RSP payload length to %u bytes...\n", 6071 rsp_payload_length); 6072 } 6073 6074 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6075 &rsp_els_dma, GFP_KERNEL); 6076 if (!rsp_els) { 6077 ql_log(ql_log_warn, vha, 0x0183, 6078 "Failed allocate dma buffer ELS RSP.\n"); 6079 goto dealloc; 6080 } 6081 6082 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6083 &rsp_payload_dma, GFP_KERNEL); 6084 if (!rsp_payload) { 6085 ql_log(ql_log_warn, vha, 0x0184, 6086 "Failed allocate dma buffer ELS RSP payload.\n"); 6087 goto dealloc; 6088 } 6089 6090 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6091 &sfp_dma, GFP_KERNEL); 6092 6093 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6094 &stat_dma, GFP_KERNEL); 6095 6096 /* Prepare Response IOCB */ 6097 rsp_els->entry_type = ELS_IOCB_TYPE; 6098 rsp_els->entry_count = 1; 6099 rsp_els->sys_define = 0; 6100 rsp_els->entry_status = 0; 6101 rsp_els->handle = 0; 6102 rsp_els->nport_handle = purex->nport_handle; 6103 rsp_els->tx_dsd_count = cpu_to_le16(1); 6104 rsp_els->vp_index = purex->vp_idx; 6105 rsp_els->sof_type = EST_SOFI3; 6106 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6107 rsp_els->rx_dsd_count = 0; 6108 rsp_els->opcode = purex->els_frame_payload[0]; 6109 6110 rsp_els->d_id[0] = purex->s_id[0]; 6111 rsp_els->d_id[1] = purex->s_id[1]; 6112 rsp_els->d_id[2] = purex->s_id[2]; 6113 6114 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6115 rsp_els->rx_byte_count = 0; 6116 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6117 6118 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6119 rsp_els->tx_len = rsp_els->tx_byte_count; 6120 6121 rsp_els->rx_address = 0; 6122 rsp_els->rx_len = 0; 6123 6124 /* Prepare Response Payload */ 6125 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6126 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6127 sizeof(rsp_payload->hdr)); 6128 6129 /* Link service Request Info Descriptor */ 6130 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6131 rsp_payload->ls_req_info_desc.desc_len = 6132 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6133 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6134 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6135 6136 /* Link service Request Info Descriptor 2 */ 6137 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6138 rsp_payload->ls_req_info_desc2.desc_len = 6139 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6140 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6141 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6142 6143 6144 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6145 rsp_payload->sfp_diag_desc.desc_len = 6146 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6147 6148 if (sfp) { 6149 /* SFP Flags */ 6150 memset(sfp, 0, SFP_RTDI_LEN); 6151 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6152 if (!rval) { 6153 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6154 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6155 sfp_flags |= BIT_0; /* short wave */ 6156 else if (sfp[0] & BIT_1) 6157 sfp_flags |= BIT_1; /* long wave 1310nm */ 6158 else if (sfp[1] & BIT_4) 6159 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6160 } 6161 6162 /* SFP Type */ 6163 memset(sfp, 0, SFP_RTDI_LEN); 6164 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6165 if (!rval) { 6166 sfp_flags |= BIT_4; /* optical */ 6167 if (sfp[0] == 0x3) 6168 sfp_flags |= BIT_6; /* sfp+ */ 6169 } 6170 6171 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6172 6173 /* SFP Diagnostics */ 6174 memset(sfp, 0, SFP_RTDI_LEN); 6175 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6176 if (!rval) { 6177 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6178 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6179 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6180 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6181 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6182 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6183 } 6184 } 6185 6186 /* Port Speed Descriptor */ 6187 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6188 rsp_payload->port_speed_desc.desc_len = 6189 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6190 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6191 qla25xx_fdmi_port_speed_capability(ha)); 6192 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6193 qla25xx_fdmi_port_speed_currently(ha)); 6194 6195 /* Link Error Status Descriptor */ 6196 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6197 rsp_payload->ls_err_desc.desc_len = 6198 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6199 6200 if (stat) { 6201 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6202 if (!rval) { 6203 rsp_payload->ls_err_desc.link_fail_cnt = 6204 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6205 rsp_payload->ls_err_desc.loss_sync_cnt = 6206 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6207 rsp_payload->ls_err_desc.loss_sig_cnt = 6208 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6209 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6210 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6211 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6212 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6213 rsp_payload->ls_err_desc.inval_crc_cnt = 6214 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6215 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6216 } 6217 } 6218 6219 /* Portname Descriptor */ 6220 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6221 rsp_payload->port_name_diag_desc.desc_len = 6222 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6223 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6224 vha->node_name, 6225 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6226 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6227 vha->port_name, 6228 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6229 6230 /* F-Port Portname Descriptor */ 6231 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6232 rsp_payload->port_name_direct_desc.desc_len = 6233 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6234 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6235 vha->fabric_node_name, 6236 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6237 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6238 vha->fabric_port_name, 6239 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6240 6241 /* Bufer Credit Descriptor */ 6242 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6243 rsp_payload->buffer_credit_desc.desc_len = 6244 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6245 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6246 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6247 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6248 6249 if (ha->flags.plogi_template_valid) { 6250 uint32_t tmp = 6251 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6252 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6253 } 6254 6255 if (rsp_payload_length < sizeof(*rsp_payload)) 6256 goto send; 6257 6258 /* Optical Element Descriptor, Temperature */ 6259 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6260 rsp_payload->optical_elmt_desc[0].desc_len = 6261 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6262 /* Optical Element Descriptor, Voltage */ 6263 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6264 rsp_payload->optical_elmt_desc[1].desc_len = 6265 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6266 /* Optical Element Descriptor, Tx Bias Current */ 6267 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6268 rsp_payload->optical_elmt_desc[2].desc_len = 6269 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6270 /* Optical Element Descriptor, Tx Power */ 6271 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6272 rsp_payload->optical_elmt_desc[3].desc_len = 6273 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6274 /* Optical Element Descriptor, Rx Power */ 6275 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6276 rsp_payload->optical_elmt_desc[4].desc_len = 6277 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6278 6279 if (sfp) { 6280 memset(sfp, 0, SFP_RTDI_LEN); 6281 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6282 if (!rval) { 6283 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6284 6285 /* Optical Element Descriptor, Temperature */ 6286 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6287 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6288 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6289 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6290 rsp_payload->optical_elmt_desc[0].element_flags = 6291 cpu_to_be32(1 << 28); 6292 6293 /* Optical Element Descriptor, Voltage */ 6294 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6295 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6296 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6297 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6298 rsp_payload->optical_elmt_desc[1].element_flags = 6299 cpu_to_be32(2 << 28); 6300 6301 /* Optical Element Descriptor, Tx Bias Current */ 6302 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6303 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6304 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6305 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6306 rsp_payload->optical_elmt_desc[2].element_flags = 6307 cpu_to_be32(3 << 28); 6308 6309 /* Optical Element Descriptor, Tx Power */ 6310 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6311 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6312 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6313 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6314 rsp_payload->optical_elmt_desc[3].element_flags = 6315 cpu_to_be32(4 << 28); 6316 6317 /* Optical Element Descriptor, Rx Power */ 6318 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6319 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6320 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6321 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6322 rsp_payload->optical_elmt_desc[4].element_flags = 6323 cpu_to_be32(5 << 28); 6324 } 6325 6326 memset(sfp, 0, SFP_RTDI_LEN); 6327 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6328 if (!rval) { 6329 /* Temperature high/low alarm/warning */ 6330 rsp_payload->optical_elmt_desc[0].element_flags |= 6331 cpu_to_be32( 6332 (sfp[0] >> 7 & 1) << 3 | 6333 (sfp[0] >> 6 & 1) << 2 | 6334 (sfp[4] >> 7 & 1) << 1 | 6335 (sfp[4] >> 6 & 1) << 0); 6336 6337 /* Voltage high/low alarm/warning */ 6338 rsp_payload->optical_elmt_desc[1].element_flags |= 6339 cpu_to_be32( 6340 (sfp[0] >> 5 & 1) << 3 | 6341 (sfp[0] >> 4 & 1) << 2 | 6342 (sfp[4] >> 5 & 1) << 1 | 6343 (sfp[4] >> 4 & 1) << 0); 6344 6345 /* Tx Bias Current high/low alarm/warning */ 6346 rsp_payload->optical_elmt_desc[2].element_flags |= 6347 cpu_to_be32( 6348 (sfp[0] >> 3 & 1) << 3 | 6349 (sfp[0] >> 2 & 1) << 2 | 6350 (sfp[4] >> 3 & 1) << 1 | 6351 (sfp[4] >> 2 & 1) << 0); 6352 6353 /* Tx Power high/low alarm/warning */ 6354 rsp_payload->optical_elmt_desc[3].element_flags |= 6355 cpu_to_be32( 6356 (sfp[0] >> 1 & 1) << 3 | 6357 (sfp[0] >> 0 & 1) << 2 | 6358 (sfp[4] >> 1 & 1) << 1 | 6359 (sfp[4] >> 0 & 1) << 0); 6360 6361 /* Rx Power high/low alarm/warning */ 6362 rsp_payload->optical_elmt_desc[4].element_flags |= 6363 cpu_to_be32( 6364 (sfp[1] >> 7 & 1) << 3 | 6365 (sfp[1] >> 6 & 1) << 2 | 6366 (sfp[5] >> 7 & 1) << 1 | 6367 (sfp[5] >> 6 & 1) << 0); 6368 } 6369 } 6370 6371 /* Optical Product Data Descriptor */ 6372 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6373 rsp_payload->optical_prod_desc.desc_len = 6374 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6375 6376 if (sfp) { 6377 memset(sfp, 0, SFP_RTDI_LEN); 6378 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6379 if (!rval) { 6380 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6381 sfp + 0, 6382 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6383 memcpy(rsp_payload->optical_prod_desc.part_number, 6384 sfp + 20, 6385 sizeof(rsp_payload->optical_prod_desc.part_number)); 6386 memcpy(rsp_payload->optical_prod_desc.revision, 6387 sfp + 36, 6388 sizeof(rsp_payload->optical_prod_desc.revision)); 6389 memcpy(rsp_payload->optical_prod_desc.serial_number, 6390 sfp + 48, 6391 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6392 } 6393 6394 memset(sfp, 0, SFP_RTDI_LEN); 6395 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6396 if (!rval) { 6397 memcpy(rsp_payload->optical_prod_desc.date, 6398 sfp + 0, 6399 sizeof(rsp_payload->optical_prod_desc.date)); 6400 } 6401 } 6402 6403 send: 6404 ql_dbg(ql_dbg_init, vha, 0x0183, 6405 "Sending ELS Response to RDP Request...\n"); 6406 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6407 "-------- ELS RSP -------\n"); 6408 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6409 rsp_els, sizeof(*rsp_els)); 6410 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6411 "-------- ELS RSP PAYLOAD -------\n"); 6412 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6413 rsp_payload, rsp_payload_length); 6414 6415 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6416 6417 if (rval) { 6418 ql_log(ql_log_warn, vha, 0x0188, 6419 "%s: iocb failed to execute -> %x\n", __func__, rval); 6420 } else if (rsp_els->comp_status) { 6421 ql_log(ql_log_warn, vha, 0x0189, 6422 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6423 __func__, rsp_els->comp_status, 6424 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6425 } else { 6426 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6427 } 6428 6429 dealloc: 6430 if (stat) 6431 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6432 stat, stat_dma); 6433 if (sfp) 6434 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6435 sfp, sfp_dma); 6436 if (rsp_payload) 6437 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6438 rsp_payload, rsp_payload_dma); 6439 if (rsp_els) 6440 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6441 rsp_els, rsp_els_dma); 6442 } 6443 6444 void 6445 qla24xx_free_purex_item(struct purex_item *item) 6446 { 6447 if (item == &item->vha->default_item) 6448 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6449 else 6450 kfree(item); 6451 } 6452 6453 void qla24xx_process_purex_list(struct purex_list *list) 6454 { 6455 struct list_head head = LIST_HEAD_INIT(head); 6456 struct purex_item *item, *next; 6457 ulong flags; 6458 6459 spin_lock_irqsave(&list->lock, flags); 6460 list_splice_init(&list->head, &head); 6461 spin_unlock_irqrestore(&list->lock, flags); 6462 6463 list_for_each_entry_safe(item, next, &head, list) { 6464 list_del(&item->list); 6465 item->process_item(item->vha, item); 6466 qla24xx_free_purex_item(item); 6467 } 6468 } 6469 6470 /* 6471 * Context: task, can sleep 6472 */ 6473 void 6474 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6475 { 6476 #if 0 6477 uint16_t options = (requester_id << 15) | BIT_7; 6478 #endif 6479 uint16_t retry; 6480 uint32_t data; 6481 struct qla_hw_data *ha = base_vha->hw; 6482 6483 might_sleep(); 6484 6485 /* IDC-unlock implementation using driver-unlock/lock-id 6486 * remote registers 6487 */ 6488 retry = 0; 6489 retry_unlock: 6490 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6491 == QLA_SUCCESS) { 6492 if (data == ha->portnum) { 6493 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6494 /* Clearing lock-id by setting 0xff */ 6495 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6496 } else if (retry < 10) { 6497 /* SV: XXX: IDC unlock retrying needed here? */ 6498 6499 /* Retry for IDC-unlock */ 6500 msleep(QLA83XX_WAIT_LOGIC_MS); 6501 retry++; 6502 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6503 "Failed to release IDC lock, retrying=%d\n", retry); 6504 goto retry_unlock; 6505 } 6506 } else if (retry < 10) { 6507 /* Retry for IDC-unlock */ 6508 msleep(QLA83XX_WAIT_LOGIC_MS); 6509 retry++; 6510 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6511 "Failed to read drv-lockid, retrying=%d\n", retry); 6512 goto retry_unlock; 6513 } 6514 6515 return; 6516 6517 #if 0 6518 /* XXX: IDC-unlock implementation using access-control mbx */ 6519 retry = 0; 6520 retry_unlock2: 6521 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6522 if (retry < 10) { 6523 /* Retry for IDC-unlock */ 6524 msleep(QLA83XX_WAIT_LOGIC_MS); 6525 retry++; 6526 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6527 "Failed to release IDC lock, retrying=%d\n", retry); 6528 goto retry_unlock2; 6529 } 6530 } 6531 6532 return; 6533 #endif 6534 } 6535 6536 int 6537 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6538 { 6539 int rval = QLA_SUCCESS; 6540 struct qla_hw_data *ha = vha->hw; 6541 uint32_t drv_presence; 6542 6543 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6544 if (rval == QLA_SUCCESS) { 6545 drv_presence |= (1 << ha->portnum); 6546 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6547 drv_presence); 6548 } 6549 6550 return rval; 6551 } 6552 6553 int 6554 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6555 { 6556 int rval = QLA_SUCCESS; 6557 6558 qla83xx_idc_lock(vha, 0); 6559 rval = __qla83xx_set_drv_presence(vha); 6560 qla83xx_idc_unlock(vha, 0); 6561 6562 return rval; 6563 } 6564 6565 int 6566 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6567 { 6568 int rval = QLA_SUCCESS; 6569 struct qla_hw_data *ha = vha->hw; 6570 uint32_t drv_presence; 6571 6572 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6573 if (rval == QLA_SUCCESS) { 6574 drv_presence &= ~(1 << ha->portnum); 6575 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6576 drv_presence); 6577 } 6578 6579 return rval; 6580 } 6581 6582 int 6583 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6584 { 6585 int rval = QLA_SUCCESS; 6586 6587 qla83xx_idc_lock(vha, 0); 6588 rval = __qla83xx_clear_drv_presence(vha); 6589 qla83xx_idc_unlock(vha, 0); 6590 6591 return rval; 6592 } 6593 6594 static void 6595 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6596 { 6597 struct qla_hw_data *ha = vha->hw; 6598 uint32_t drv_ack, drv_presence; 6599 unsigned long ack_timeout; 6600 6601 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6602 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6603 while (1) { 6604 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6605 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6606 if ((drv_ack & drv_presence) == drv_presence) 6607 break; 6608 6609 if (time_after_eq(jiffies, ack_timeout)) { 6610 ql_log(ql_log_warn, vha, 0xb067, 6611 "RESET ACK TIMEOUT! drv_presence=0x%x " 6612 "drv_ack=0x%x\n", drv_presence, drv_ack); 6613 /* 6614 * The function(s) which did not ack in time are forced 6615 * to withdraw any further participation in the IDC 6616 * reset. 6617 */ 6618 if (drv_ack != drv_presence) 6619 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6620 drv_ack); 6621 break; 6622 } 6623 6624 qla83xx_idc_unlock(vha, 0); 6625 msleep(1000); 6626 qla83xx_idc_lock(vha, 0); 6627 } 6628 6629 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6630 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6631 } 6632 6633 static int 6634 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6635 { 6636 int rval = QLA_SUCCESS; 6637 uint32_t idc_control; 6638 6639 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6640 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6641 6642 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6643 __qla83xx_get_idc_control(vha, &idc_control); 6644 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6645 __qla83xx_set_idc_control(vha, 0); 6646 6647 qla83xx_idc_unlock(vha, 0); 6648 rval = qla83xx_restart_nic_firmware(vha); 6649 qla83xx_idc_lock(vha, 0); 6650 6651 if (rval != QLA_SUCCESS) { 6652 ql_log(ql_log_fatal, vha, 0xb06a, 6653 "Failed to restart NIC f/w.\n"); 6654 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6655 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6656 } else { 6657 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6658 "Success in restarting nic f/w.\n"); 6659 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6660 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6661 } 6662 6663 return rval; 6664 } 6665 6666 /* Assumes idc_lock always held on entry */ 6667 int 6668 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6669 { 6670 struct qla_hw_data *ha = base_vha->hw; 6671 int rval = QLA_SUCCESS; 6672 unsigned long dev_init_timeout; 6673 uint32_t dev_state; 6674 6675 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6676 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6677 6678 while (1) { 6679 6680 if (time_after_eq(jiffies, dev_init_timeout)) { 6681 ql_log(ql_log_warn, base_vha, 0xb06e, 6682 "Initialization TIMEOUT!\n"); 6683 /* Init timeout. Disable further NIC Core 6684 * communication. 6685 */ 6686 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6687 QLA8XXX_DEV_FAILED); 6688 ql_log(ql_log_info, base_vha, 0xb06f, 6689 "HW State: FAILED.\n"); 6690 } 6691 6692 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6693 switch (dev_state) { 6694 case QLA8XXX_DEV_READY: 6695 if (ha->flags.nic_core_reset_owner) 6696 qla83xx_idc_audit(base_vha, 6697 IDC_AUDIT_COMPLETION); 6698 ha->flags.nic_core_reset_owner = 0; 6699 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6700 "Reset_owner reset by 0x%x.\n", 6701 ha->portnum); 6702 goto exit; 6703 case QLA8XXX_DEV_COLD: 6704 if (ha->flags.nic_core_reset_owner) 6705 rval = qla83xx_device_bootstrap(base_vha); 6706 else { 6707 /* Wait for AEN to change device-state */ 6708 qla83xx_idc_unlock(base_vha, 0); 6709 msleep(1000); 6710 qla83xx_idc_lock(base_vha, 0); 6711 } 6712 break; 6713 case QLA8XXX_DEV_INITIALIZING: 6714 /* Wait for AEN to change device-state */ 6715 qla83xx_idc_unlock(base_vha, 0); 6716 msleep(1000); 6717 qla83xx_idc_lock(base_vha, 0); 6718 break; 6719 case QLA8XXX_DEV_NEED_RESET: 6720 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6721 qla83xx_need_reset_handler(base_vha); 6722 else { 6723 /* Wait for AEN to change device-state */ 6724 qla83xx_idc_unlock(base_vha, 0); 6725 msleep(1000); 6726 qla83xx_idc_lock(base_vha, 0); 6727 } 6728 /* reset timeout value after need reset handler */ 6729 dev_init_timeout = jiffies + 6730 (ha->fcoe_dev_init_timeout * HZ); 6731 break; 6732 case QLA8XXX_DEV_NEED_QUIESCENT: 6733 /* XXX: DEBUG for now */ 6734 qla83xx_idc_unlock(base_vha, 0); 6735 msleep(1000); 6736 qla83xx_idc_lock(base_vha, 0); 6737 break; 6738 case QLA8XXX_DEV_QUIESCENT: 6739 /* XXX: DEBUG for now */ 6740 if (ha->flags.quiesce_owner) 6741 goto exit; 6742 6743 qla83xx_idc_unlock(base_vha, 0); 6744 msleep(1000); 6745 qla83xx_idc_lock(base_vha, 0); 6746 dev_init_timeout = jiffies + 6747 (ha->fcoe_dev_init_timeout * HZ); 6748 break; 6749 case QLA8XXX_DEV_FAILED: 6750 if (ha->flags.nic_core_reset_owner) 6751 qla83xx_idc_audit(base_vha, 6752 IDC_AUDIT_COMPLETION); 6753 ha->flags.nic_core_reset_owner = 0; 6754 __qla83xx_clear_drv_presence(base_vha); 6755 qla83xx_idc_unlock(base_vha, 0); 6756 qla8xxx_dev_failed_handler(base_vha); 6757 rval = QLA_FUNCTION_FAILED; 6758 qla83xx_idc_lock(base_vha, 0); 6759 goto exit; 6760 case QLA8XXX_BAD_VALUE: 6761 qla83xx_idc_unlock(base_vha, 0); 6762 msleep(1000); 6763 qla83xx_idc_lock(base_vha, 0); 6764 break; 6765 default: 6766 ql_log(ql_log_warn, base_vha, 0xb071, 6767 "Unknown Device State: %x.\n", dev_state); 6768 qla83xx_idc_unlock(base_vha, 0); 6769 qla8xxx_dev_failed_handler(base_vha); 6770 rval = QLA_FUNCTION_FAILED; 6771 qla83xx_idc_lock(base_vha, 0); 6772 goto exit; 6773 } 6774 } 6775 6776 exit: 6777 return rval; 6778 } 6779 6780 void 6781 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6782 { 6783 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6784 board_disable); 6785 struct pci_dev *pdev = ha->pdev; 6786 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6787 6788 ql_log(ql_log_warn, base_vha, 0x015b, 6789 "Disabling adapter.\n"); 6790 6791 if (!atomic_read(&pdev->enable_cnt)) { 6792 ql_log(ql_log_info, base_vha, 0xfffc, 6793 "PCI device disabled, no action req for PCI error=%lx\n", 6794 base_vha->pci_flags); 6795 return; 6796 } 6797 6798 /* 6799 * if UNLOADING flag is already set, then continue unload, 6800 * where it was set first. 6801 */ 6802 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6803 return; 6804 6805 qla2x00_wait_for_sess_deletion(base_vha); 6806 6807 qla2x00_delete_all_vps(ha, base_vha); 6808 6809 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6810 6811 qla2x00_dfs_remove(base_vha); 6812 6813 qla84xx_put_chip(base_vha); 6814 6815 if (base_vha->timer_active) 6816 qla2x00_stop_timer(base_vha); 6817 6818 base_vha->flags.online = 0; 6819 6820 qla2x00_destroy_deferred_work(ha); 6821 6822 /* 6823 * Do not try to stop beacon blink as it will issue a mailbox 6824 * command. 6825 */ 6826 qla2x00_free_sysfs_attr(base_vha, false); 6827 6828 fc_remove_host(base_vha->host); 6829 6830 scsi_remove_host(base_vha->host); 6831 6832 base_vha->flags.init_done = 0; 6833 qla25xx_delete_queues(base_vha); 6834 qla2x00_free_fcports(base_vha); 6835 qla2x00_free_irqs(base_vha); 6836 qla2x00_mem_free(ha); 6837 qla82xx_md_free(base_vha); 6838 qla2x00_free_queues(ha); 6839 6840 qla2x00_unmap_iobases(ha); 6841 6842 pci_release_selected_regions(ha->pdev, ha->bars); 6843 pci_disable_device(pdev); 6844 6845 /* 6846 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6847 */ 6848 } 6849 6850 /************************************************************************** 6851 * qla2x00_do_dpc 6852 * This kernel thread is a task that is schedule by the interrupt handler 6853 * to perform the background processing for interrupts. 6854 * 6855 * Notes: 6856 * This task always run in the context of a kernel thread. It 6857 * is kick-off by the driver's detect code and starts up 6858 * up one per adapter. It immediately goes to sleep and waits for 6859 * some fibre event. When either the interrupt handler or 6860 * the timer routine detects a event it will one of the task 6861 * bits then wake us up. 6862 **************************************************************************/ 6863 static int 6864 qla2x00_do_dpc(void *data) 6865 { 6866 scsi_qla_host_t *base_vha; 6867 struct qla_hw_data *ha; 6868 uint32_t online; 6869 struct qla_qpair *qpair; 6870 6871 ha = (struct qla_hw_data *)data; 6872 base_vha = pci_get_drvdata(ha->pdev); 6873 6874 set_user_nice(current, MIN_NICE); 6875 6876 set_current_state(TASK_INTERRUPTIBLE); 6877 while (!kthread_should_stop()) { 6878 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6879 "DPC handler sleeping.\n"); 6880 6881 schedule(); 6882 6883 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6884 qla_pci_set_eeh_busy(base_vha); 6885 6886 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6887 goto end_loop; 6888 6889 if (ha->flags.eeh_busy) { 6890 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6891 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6892 goto end_loop; 6893 } 6894 6895 ha->dpc_active = 1; 6896 6897 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6898 "DPC handler waking up, dpc_flags=0x%lx.\n", 6899 base_vha->dpc_flags); 6900 6901 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6902 break; 6903 6904 if (IS_P3P_TYPE(ha)) { 6905 if (IS_QLA8044(ha)) { 6906 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6907 &base_vha->dpc_flags)) { 6908 qla8044_idc_lock(ha); 6909 qla8044_wr_direct(base_vha, 6910 QLA8044_CRB_DEV_STATE_INDEX, 6911 QLA8XXX_DEV_FAILED); 6912 qla8044_idc_unlock(ha); 6913 ql_log(ql_log_info, base_vha, 0x4004, 6914 "HW State: FAILED.\n"); 6915 qla8044_device_state_handler(base_vha); 6916 continue; 6917 } 6918 6919 } else { 6920 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6921 &base_vha->dpc_flags)) { 6922 qla82xx_idc_lock(ha); 6923 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6924 QLA8XXX_DEV_FAILED); 6925 qla82xx_idc_unlock(ha); 6926 ql_log(ql_log_info, base_vha, 0x0151, 6927 "HW State: FAILED.\n"); 6928 qla82xx_device_state_handler(base_vha); 6929 continue; 6930 } 6931 } 6932 6933 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6934 &base_vha->dpc_flags)) { 6935 6936 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6937 "FCoE context reset scheduled.\n"); 6938 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6939 &base_vha->dpc_flags))) { 6940 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6941 /* FCoE-ctx reset failed. 6942 * Escalate to chip-reset 6943 */ 6944 set_bit(ISP_ABORT_NEEDED, 6945 &base_vha->dpc_flags); 6946 } 6947 clear_bit(ABORT_ISP_ACTIVE, 6948 &base_vha->dpc_flags); 6949 } 6950 6951 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6952 "FCoE context reset end.\n"); 6953 } 6954 } else if (IS_QLAFX00(ha)) { 6955 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6956 &base_vha->dpc_flags)) { 6957 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6958 "Firmware Reset Recovery\n"); 6959 if (qlafx00_reset_initialize(base_vha)) { 6960 /* Failed. Abort isp later. */ 6961 if (!test_bit(UNLOADING, 6962 &base_vha->dpc_flags)) { 6963 set_bit(ISP_UNRECOVERABLE, 6964 &base_vha->dpc_flags); 6965 ql_dbg(ql_dbg_dpc, base_vha, 6966 0x4021, 6967 "Reset Recovery Failed\n"); 6968 } 6969 } 6970 } 6971 6972 if (test_and_clear_bit(FX00_TARGET_SCAN, 6973 &base_vha->dpc_flags)) { 6974 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6975 "ISPFx00 Target Scan scheduled\n"); 6976 if (qlafx00_rescan_isp(base_vha)) { 6977 if (!test_bit(UNLOADING, 6978 &base_vha->dpc_flags)) 6979 set_bit(ISP_UNRECOVERABLE, 6980 &base_vha->dpc_flags); 6981 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6982 "ISPFx00 Target Scan Failed\n"); 6983 } 6984 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6985 "ISPFx00 Target Scan End\n"); 6986 } 6987 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6988 &base_vha->dpc_flags)) { 6989 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6990 "ISPFx00 Host Info resend scheduled\n"); 6991 qlafx00_fx_disc(base_vha, 6992 &base_vha->hw->mr.fcport, 6993 FXDISC_REG_HOST_INFO); 6994 } 6995 } 6996 6997 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6998 &base_vha->dpc_flags)) { 6999 /* Semantic: 7000 * - NO-OP -- await next ISP-ABORT. Preferred method 7001 * to minimize disruptions that will occur 7002 * when a forced chip-reset occurs. 7003 * - Force -- ISP-ABORT scheduled. 7004 */ 7005 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 7006 } 7007 7008 if (test_and_clear_bit 7009 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 7010 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 7011 bool do_reset = true; 7012 7013 switch (base_vha->qlini_mode) { 7014 case QLA2XXX_INI_MODE_ENABLED: 7015 break; 7016 case QLA2XXX_INI_MODE_DISABLED: 7017 if (!qla_tgt_mode_enabled(base_vha) && 7018 !ha->flags.fw_started) 7019 do_reset = false; 7020 break; 7021 case QLA2XXX_INI_MODE_DUAL: 7022 if (!qla_dual_mode_enabled(base_vha) && 7023 !ha->flags.fw_started) 7024 do_reset = false; 7025 break; 7026 default: 7027 break; 7028 } 7029 7030 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 7031 &base_vha->dpc_flags))) { 7032 base_vha->flags.online = 1; 7033 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 7034 "ISP abort scheduled.\n"); 7035 if (ha->isp_ops->abort_isp(base_vha)) { 7036 /* failed. retry later */ 7037 set_bit(ISP_ABORT_NEEDED, 7038 &base_vha->dpc_flags); 7039 } 7040 clear_bit(ABORT_ISP_ACTIVE, 7041 &base_vha->dpc_flags); 7042 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 7043 "ISP abort end.\n"); 7044 } 7045 } 7046 7047 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 7048 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 7049 qla24xx_process_purex_list 7050 (&base_vha->purex_list); 7051 clear_bit(PROCESS_PUREX_IOCB, 7052 &base_vha->dpc_flags); 7053 } 7054 } 7055 7056 if (IS_QLAFX00(ha)) 7057 goto loop_resync_check; 7058 7059 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 7060 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 7061 "Quiescence mode scheduled.\n"); 7062 if (IS_P3P_TYPE(ha)) { 7063 if (IS_QLA82XX(ha)) 7064 qla82xx_device_state_handler(base_vha); 7065 if (IS_QLA8044(ha)) 7066 qla8044_device_state_handler(base_vha); 7067 clear_bit(ISP_QUIESCE_NEEDED, 7068 &base_vha->dpc_flags); 7069 if (!ha->flags.quiesce_owner) { 7070 qla2x00_perform_loop_resync(base_vha); 7071 if (IS_QLA82XX(ha)) { 7072 qla82xx_idc_lock(ha); 7073 qla82xx_clear_qsnt_ready( 7074 base_vha); 7075 qla82xx_idc_unlock(ha); 7076 } else if (IS_QLA8044(ha)) { 7077 qla8044_idc_lock(ha); 7078 qla8044_clear_qsnt_ready( 7079 base_vha); 7080 qla8044_idc_unlock(ha); 7081 } 7082 } 7083 } else { 7084 clear_bit(ISP_QUIESCE_NEEDED, 7085 &base_vha->dpc_flags); 7086 qla2x00_quiesce_io(base_vha); 7087 } 7088 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7089 "Quiescence mode end.\n"); 7090 } 7091 7092 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7093 &base_vha->dpc_flags) && 7094 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7095 7096 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7097 "Reset marker scheduled.\n"); 7098 qla2x00_rst_aen(base_vha); 7099 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7100 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7101 "Reset marker end.\n"); 7102 } 7103 7104 /* Retry each device up to login retry count */ 7105 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7106 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7107 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7108 7109 if (!base_vha->relogin_jif || 7110 time_after_eq(jiffies, base_vha->relogin_jif)) { 7111 base_vha->relogin_jif = jiffies + HZ; 7112 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7113 7114 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7115 "Relogin scheduled.\n"); 7116 qla24xx_post_relogin_work(base_vha); 7117 } 7118 } 7119 loop_resync_check: 7120 if (!qla2x00_reset_active(base_vha) && 7121 test_and_clear_bit(LOOP_RESYNC_NEEDED, 7122 &base_vha->dpc_flags)) { 7123 /* 7124 * Allow abort_isp to complete before moving on to scanning. 7125 */ 7126 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7127 "Loop resync scheduled.\n"); 7128 7129 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7130 &base_vha->dpc_flags))) { 7131 7132 qla2x00_loop_resync(base_vha); 7133 7134 clear_bit(LOOP_RESYNC_ACTIVE, 7135 &base_vha->dpc_flags); 7136 } 7137 7138 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7139 "Loop resync end.\n"); 7140 } 7141 7142 if (IS_QLAFX00(ha)) 7143 goto intr_on_check; 7144 7145 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7146 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7147 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7148 qla2xxx_flash_npiv_conf(base_vha); 7149 } 7150 7151 intr_on_check: 7152 if (!ha->interrupts_on) 7153 ha->isp_ops->enable_intrs(ha); 7154 7155 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7156 &base_vha->dpc_flags)) { 7157 if (ha->beacon_blink_led == 1) 7158 ha->isp_ops->beacon_blink(base_vha); 7159 } 7160 7161 /* qpair online check */ 7162 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7163 &base_vha->dpc_flags)) { 7164 if (ha->flags.eeh_busy || 7165 ha->flags.pci_channel_io_perm_failure) 7166 online = 0; 7167 else 7168 online = 1; 7169 7170 mutex_lock(&ha->mq_lock); 7171 list_for_each_entry(qpair, &base_vha->qp_list, 7172 qp_list_elem) 7173 qpair->online = online; 7174 mutex_unlock(&ha->mq_lock); 7175 } 7176 7177 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7178 &base_vha->dpc_flags)) { 7179 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7180 7181 if (threshold > ha->orig_fw_xcb_count) 7182 threshold = ha->orig_fw_xcb_count; 7183 7184 ql_log(ql_log_info, base_vha, 0xffffff, 7185 "SET ZIO Activity exchange threshold to %d.\n", 7186 threshold); 7187 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7188 ql_log(ql_log_info, base_vha, 0xffffff, 7189 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7190 threshold); 7191 } 7192 } 7193 7194 if (!IS_QLAFX00(ha)) 7195 qla2x00_do_dpc_all_vps(base_vha); 7196 7197 if (test_and_clear_bit(N2N_LINK_RESET, 7198 &base_vha->dpc_flags)) { 7199 qla2x00_lip_reset(base_vha); 7200 } 7201 7202 ha->dpc_active = 0; 7203 end_loop: 7204 set_current_state(TASK_INTERRUPTIBLE); 7205 } /* End of while(1) */ 7206 __set_current_state(TASK_RUNNING); 7207 7208 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7209 "DPC handler exiting.\n"); 7210 7211 /* 7212 * Make sure that nobody tries to wake us up again. 7213 */ 7214 ha->dpc_active = 0; 7215 7216 /* Cleanup any residual CTX SRBs. */ 7217 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7218 7219 return 0; 7220 } 7221 7222 void 7223 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7224 { 7225 struct qla_hw_data *ha = vha->hw; 7226 struct task_struct *t = ha->dpc_thread; 7227 7228 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7229 wake_up_process(t); 7230 } 7231 7232 /* 7233 * qla2x00_rst_aen 7234 * Processes asynchronous reset. 7235 * 7236 * Input: 7237 * ha = adapter block pointer. 7238 */ 7239 static void 7240 qla2x00_rst_aen(scsi_qla_host_t *vha) 7241 { 7242 if (vha->flags.online && !vha->flags.reset_active && 7243 !atomic_read(&vha->loop_down_timer) && 7244 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7245 do { 7246 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7247 7248 /* 7249 * Issue marker command only when we are going to start 7250 * the I/O. 7251 */ 7252 vha->marker_needed = 1; 7253 } while (!atomic_read(&vha->loop_down_timer) && 7254 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7255 } 7256 } 7257 7258 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7259 { 7260 struct qla_hw_data *ha = vha->hw; 7261 u32 cmpl_cnt; 7262 u16 i; 7263 bool do_heartbeat = false; 7264 7265 /* 7266 * Allow do_heartbeat only if we don’t have any active interrupts, 7267 * but there are still IOs outstanding with firmware. 7268 */ 7269 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7270 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7271 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7272 do_heartbeat = true; 7273 goto skip; 7274 } 7275 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7276 7277 for (i = 0; i < ha->max_qpairs; i++) { 7278 if (ha->queue_pair_map[i]) { 7279 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7280 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7281 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7282 do_heartbeat = true; 7283 break; 7284 } 7285 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7286 } 7287 } 7288 7289 skip: 7290 return do_heartbeat; 7291 } 7292 7293 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started) 7294 { 7295 struct qla_hw_data *ha = vha->hw; 7296 7297 if (vha->vp_idx) 7298 return; 7299 7300 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7301 return; 7302 7303 /* 7304 * dpc thread cannot run if heartbeat is running at the same time. 7305 * We also do not want to starve heartbeat task. Therefore, do 7306 * heartbeat task at least once every 5 seconds. 7307 */ 7308 if (dpc_started && 7309 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ)) 7310 return; 7311 7312 if (qla_do_heartbeat(vha)) { 7313 ha->last_heartbeat_run_jiffies = jiffies; 7314 queue_work(ha->wq, &ha->heartbeat_work); 7315 } 7316 } 7317 7318 static void qla_wind_down_chip(scsi_qla_host_t *vha) 7319 { 7320 struct qla_hw_data *ha = vha->hw; 7321 7322 if (!ha->flags.eeh_busy) 7323 return; 7324 if (ha->pci_error_state) 7325 /* system is trying to recover */ 7326 return; 7327 7328 /* 7329 * Current system is not handling PCIE error. At this point, this is 7330 * best effort to wind down the adapter. 7331 */ 7332 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) && 7333 !ha->flags.eeh_flush) { 7334 ql_log(ql_log_info, vha, 0x9009, 7335 "PCI Error detected, attempting to reset hardware.\n"); 7336 7337 ha->isp_ops->reset_chip(vha); 7338 ha->isp_ops->disable_intrs(ha); 7339 7340 ha->flags.eeh_flush = EEH_FLUSH_RDY; 7341 ha->eeh_jif = jiffies; 7342 7343 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY && 7344 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) { 7345 pci_clear_master(ha->pdev); 7346 7347 /* flush all command */ 7348 qla2x00_abort_isp_cleanup(vha); 7349 ha->flags.eeh_flush = EEH_FLUSH_DONE; 7350 7351 ql_log(ql_log_info, vha, 0x900a, 7352 "PCI Error handling complete, all IOs aborted.\n"); 7353 } 7354 } 7355 7356 /************************************************************************** 7357 * qla2x00_timer 7358 * 7359 * Description: 7360 * One second timer 7361 * 7362 * Context: Interrupt 7363 ***************************************************************************/ 7364 void 7365 qla2x00_timer(struct timer_list *t) 7366 { 7367 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7368 unsigned long cpu_flags = 0; 7369 int start_dpc = 0; 7370 int index; 7371 srb_t *sp; 7372 uint16_t w; 7373 struct qla_hw_data *ha = vha->hw; 7374 struct req_que *req; 7375 unsigned long flags; 7376 fc_port_t *fcport = NULL; 7377 7378 if (ha->flags.eeh_busy) { 7379 qla_wind_down_chip(vha); 7380 7381 ql_dbg(ql_dbg_timer, vha, 0x6000, 7382 "EEH = %d, restarting timer.\n", 7383 ha->flags.eeh_busy); 7384 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7385 return; 7386 } 7387 7388 /* 7389 * Hardware read to raise pending EEH errors during mailbox waits. If 7390 * the read returns -1 then disable the board. 7391 */ 7392 if (!pci_channel_offline(ha->pdev)) { 7393 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7394 qla2x00_check_reg16_for_disconnect(vha, w); 7395 } 7396 7397 /* Make sure qla82xx_watchdog is run only for physical port */ 7398 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7399 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7400 start_dpc++; 7401 if (IS_QLA82XX(ha)) 7402 qla82xx_watchdog(vha); 7403 else if (IS_QLA8044(ha)) 7404 qla8044_watchdog(vha); 7405 } 7406 7407 if (!vha->vp_idx && IS_QLAFX00(ha)) 7408 qlafx00_timer_routine(vha); 7409 7410 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7411 vha->link_down_time++; 7412 7413 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7414 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7415 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7416 fcport->tgt_link_down_time++; 7417 } 7418 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7419 7420 /* Loop down handler. */ 7421 if (atomic_read(&vha->loop_down_timer) > 0 && 7422 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7423 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7424 && vha->flags.online) { 7425 7426 if (atomic_read(&vha->loop_down_timer) == 7427 vha->loop_down_abort_time) { 7428 7429 ql_log(ql_log_info, vha, 0x6008, 7430 "Loop down - aborting the queues before time expires.\n"); 7431 7432 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7433 atomic_set(&vha->loop_state, LOOP_DEAD); 7434 7435 /* 7436 * Schedule an ISP abort to return any FCP2-device 7437 * commands. 7438 */ 7439 /* NPIV - scan physical port only */ 7440 if (!vha->vp_idx) { 7441 spin_lock_irqsave(&ha->hardware_lock, 7442 cpu_flags); 7443 req = ha->req_q_map[0]; 7444 for (index = 1; 7445 index < req->num_outstanding_cmds; 7446 index++) { 7447 fc_port_t *sfcp; 7448 7449 sp = req->outstanding_cmds[index]; 7450 if (!sp) 7451 continue; 7452 if (sp->cmd_type != TYPE_SRB) 7453 continue; 7454 if (sp->type != SRB_SCSI_CMD) 7455 continue; 7456 sfcp = sp->fcport; 7457 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7458 continue; 7459 7460 if (IS_QLA82XX(ha)) 7461 set_bit(FCOE_CTX_RESET_NEEDED, 7462 &vha->dpc_flags); 7463 else 7464 set_bit(ISP_ABORT_NEEDED, 7465 &vha->dpc_flags); 7466 break; 7467 } 7468 spin_unlock_irqrestore(&ha->hardware_lock, 7469 cpu_flags); 7470 } 7471 start_dpc++; 7472 } 7473 7474 /* if the loop has been down for 4 minutes, reinit adapter */ 7475 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7476 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { 7477 ql_log(ql_log_warn, vha, 0x6009, 7478 "Loop down - aborting ISP.\n"); 7479 7480 if (IS_QLA82XX(ha)) 7481 set_bit(FCOE_CTX_RESET_NEEDED, 7482 &vha->dpc_flags); 7483 else 7484 set_bit(ISP_ABORT_NEEDED, 7485 &vha->dpc_flags); 7486 } 7487 } 7488 ql_dbg(ql_dbg_timer, vha, 0x600a, 7489 "Loop down - seconds remaining %d.\n", 7490 atomic_read(&vha->loop_down_timer)); 7491 } 7492 /* Check if beacon LED needs to be blinked for physical host only */ 7493 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7494 /* There is no beacon_blink function for ISP82xx */ 7495 if (!IS_P3P_TYPE(ha)) { 7496 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7497 start_dpc++; 7498 } 7499 } 7500 7501 /* check if edif running */ 7502 if (vha->hw->flags.edif_enabled) 7503 qla_edif_timer(vha); 7504 7505 /* Process any deferred work. */ 7506 if (!list_empty(&vha->work_list)) { 7507 unsigned long flags; 7508 bool q = false; 7509 7510 spin_lock_irqsave(&vha->work_lock, flags); 7511 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7512 q = true; 7513 spin_unlock_irqrestore(&vha->work_lock, flags); 7514 if (q) 7515 queue_work(vha->hw->wq, &vha->iocb_work); 7516 } 7517 7518 /* 7519 * FC-NVME 7520 * see if the active AEN count has changed from what was last reported. 7521 */ 7522 index = atomic_read(&ha->nvme_active_aen_cnt); 7523 if (!vha->vp_idx && 7524 (index != ha->nvme_last_rptd_aen) && 7525 ha->zio_mode == QLA_ZIO_MODE_6 && 7526 !ha->flags.host_shutting_down) { 7527 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7528 ql_log(ql_log_info, vha, 0x3002, 7529 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7530 ha->nvme_last_rptd_aen); 7531 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7532 start_dpc++; 7533 } 7534 7535 if (!vha->vp_idx && 7536 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7537 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7538 ql_log(ql_log_info, vha, 0x3002, 7539 "Sched: Set ZIO exchange threshold to %d.\n", 7540 ha->last_zio_threshold); 7541 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7542 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7543 start_dpc++; 7544 } 7545 qla_adjust_buf(vha); 7546 7547 /* borrowing w to signify dpc will run */ 7548 w = 0; 7549 /* Schedule the DPC routine if needed */ 7550 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7551 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7552 start_dpc || 7553 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7554 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7555 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7556 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7557 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7558 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7559 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7560 ql_dbg(ql_dbg_timer, vha, 0x600b, 7561 "isp_abort_needed=%d loop_resync_needed=%d " 7562 "start_dpc=%d reset_marker_needed=%d", 7563 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7564 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7565 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7566 ql_dbg(ql_dbg_timer, vha, 0x600c, 7567 "beacon_blink_needed=%d isp_unrecoverable=%d " 7568 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7569 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7570 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7571 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7572 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7573 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7574 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7575 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7576 qla2xxx_wake_dpc(vha); 7577 w = 1; 7578 } 7579 7580 qla_heart_beat(vha, w); 7581 7582 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7583 } 7584 7585 /* Firmware interface routines. */ 7586 7587 #define FW_ISP21XX 0 7588 #define FW_ISP22XX 1 7589 #define FW_ISP2300 2 7590 #define FW_ISP2322 3 7591 #define FW_ISP24XX 4 7592 #define FW_ISP25XX 5 7593 #define FW_ISP81XX 6 7594 #define FW_ISP82XX 7 7595 #define FW_ISP2031 8 7596 #define FW_ISP8031 9 7597 #define FW_ISP27XX 10 7598 #define FW_ISP28XX 11 7599 7600 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7601 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7602 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7603 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7604 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7605 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7606 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7607 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7608 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7609 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7610 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7611 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7612 7613 7614 static DEFINE_MUTEX(qla_fw_lock); 7615 7616 static struct fw_blob qla_fw_blobs[] = { 7617 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7618 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7619 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7620 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7621 { .name = FW_FILE_ISP24XX, }, 7622 { .name = FW_FILE_ISP25XX, }, 7623 { .name = FW_FILE_ISP81XX, }, 7624 { .name = FW_FILE_ISP82XX, }, 7625 { .name = FW_FILE_ISP2031, }, 7626 { .name = FW_FILE_ISP8031, }, 7627 { .name = FW_FILE_ISP27XX, }, 7628 { .name = FW_FILE_ISP28XX, }, 7629 { .name = NULL, }, 7630 }; 7631 7632 struct fw_blob * 7633 qla2x00_request_firmware(scsi_qla_host_t *vha) 7634 { 7635 struct qla_hw_data *ha = vha->hw; 7636 struct fw_blob *blob; 7637 7638 if (IS_QLA2100(ha)) { 7639 blob = &qla_fw_blobs[FW_ISP21XX]; 7640 } else if (IS_QLA2200(ha)) { 7641 blob = &qla_fw_blobs[FW_ISP22XX]; 7642 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7643 blob = &qla_fw_blobs[FW_ISP2300]; 7644 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7645 blob = &qla_fw_blobs[FW_ISP2322]; 7646 } else if (IS_QLA24XX_TYPE(ha)) { 7647 blob = &qla_fw_blobs[FW_ISP24XX]; 7648 } else if (IS_QLA25XX(ha)) { 7649 blob = &qla_fw_blobs[FW_ISP25XX]; 7650 } else if (IS_QLA81XX(ha)) { 7651 blob = &qla_fw_blobs[FW_ISP81XX]; 7652 } else if (IS_QLA82XX(ha)) { 7653 blob = &qla_fw_blobs[FW_ISP82XX]; 7654 } else if (IS_QLA2031(ha)) { 7655 blob = &qla_fw_blobs[FW_ISP2031]; 7656 } else if (IS_QLA8031(ha)) { 7657 blob = &qla_fw_blobs[FW_ISP8031]; 7658 } else if (IS_QLA27XX(ha)) { 7659 blob = &qla_fw_blobs[FW_ISP27XX]; 7660 } else if (IS_QLA28XX(ha)) { 7661 blob = &qla_fw_blobs[FW_ISP28XX]; 7662 } else { 7663 return NULL; 7664 } 7665 7666 if (!blob->name) 7667 return NULL; 7668 7669 mutex_lock(&qla_fw_lock); 7670 if (blob->fw) 7671 goto out; 7672 7673 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7674 ql_log(ql_log_warn, vha, 0x0063, 7675 "Failed to load firmware image (%s).\n", blob->name); 7676 blob->fw = NULL; 7677 blob = NULL; 7678 } 7679 7680 out: 7681 mutex_unlock(&qla_fw_lock); 7682 return blob; 7683 } 7684 7685 static void 7686 qla2x00_release_firmware(void) 7687 { 7688 struct fw_blob *blob; 7689 7690 mutex_lock(&qla_fw_lock); 7691 for (blob = qla_fw_blobs; blob->name; blob++) 7692 release_firmware(blob->fw); 7693 mutex_unlock(&qla_fw_lock); 7694 } 7695 7696 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7697 { 7698 struct qla_hw_data *ha = vha->hw; 7699 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7700 struct qla_qpair *qpair = NULL; 7701 struct scsi_qla_host *vp, *tvp; 7702 fc_port_t *fcport; 7703 int i; 7704 unsigned long flags; 7705 7706 ql_dbg(ql_dbg_aer, vha, 0x9000, 7707 "%s\n", __func__); 7708 ha->chip_reset++; 7709 7710 ha->base_qpair->chip_reset = ha->chip_reset; 7711 for (i = 0; i < ha->max_qpairs; i++) { 7712 if (ha->queue_pair_map[i]) 7713 ha->queue_pair_map[i]->chip_reset = 7714 ha->base_qpair->chip_reset; 7715 } 7716 7717 /* 7718 * purge mailbox might take a while. Slot Reset/chip reset 7719 * will take care of the purge 7720 */ 7721 7722 mutex_lock(&ha->mq_lock); 7723 ha->base_qpair->online = 0; 7724 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7725 qpair->online = 0; 7726 wmb(); 7727 mutex_unlock(&ha->mq_lock); 7728 7729 qla2x00_mark_all_devices_lost(vha); 7730 7731 spin_lock_irqsave(&ha->vport_slock, flags); 7732 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7733 atomic_inc(&vp->vref_count); 7734 spin_unlock_irqrestore(&ha->vport_slock, flags); 7735 qla2x00_mark_all_devices_lost(vp); 7736 spin_lock_irqsave(&ha->vport_slock, flags); 7737 atomic_dec(&vp->vref_count); 7738 } 7739 spin_unlock_irqrestore(&ha->vport_slock, flags); 7740 7741 /* Clear all async request states across all VPs. */ 7742 list_for_each_entry(fcport, &vha->vp_fcports, list) 7743 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7744 7745 spin_lock_irqsave(&ha->vport_slock, flags); 7746 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7747 atomic_inc(&vp->vref_count); 7748 spin_unlock_irqrestore(&ha->vport_slock, flags); 7749 list_for_each_entry(fcport, &vp->vp_fcports, list) 7750 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7751 spin_lock_irqsave(&ha->vport_slock, flags); 7752 atomic_dec(&vp->vref_count); 7753 } 7754 spin_unlock_irqrestore(&ha->vport_slock, flags); 7755 } 7756 7757 7758 static pci_ers_result_t 7759 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7760 { 7761 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7762 struct qla_hw_data *ha = vha->hw; 7763 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7764 7765 ql_log(ql_log_warn, vha, 0x9000, 7766 "PCI error detected, state %x.\n", state); 7767 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7768 7769 if (!atomic_read(&pdev->enable_cnt)) { 7770 ql_log(ql_log_info, vha, 0xffff, 7771 "PCI device is disabled,state %x\n", state); 7772 ret = PCI_ERS_RESULT_NEED_RESET; 7773 goto out; 7774 } 7775 7776 switch (state) { 7777 case pci_channel_io_normal: 7778 qla_pci_set_eeh_busy(vha); 7779 if (ql2xmqsupport || ql2xnvmeenable) { 7780 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7781 qla2xxx_wake_dpc(vha); 7782 } 7783 ret = PCI_ERS_RESULT_CAN_RECOVER; 7784 break; 7785 case pci_channel_io_frozen: 7786 qla_pci_set_eeh_busy(vha); 7787 ret = PCI_ERS_RESULT_NEED_RESET; 7788 break; 7789 case pci_channel_io_perm_failure: 7790 ha->flags.pci_channel_io_perm_failure = 1; 7791 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7792 if (ql2xmqsupport || ql2xnvmeenable) { 7793 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7794 qla2xxx_wake_dpc(vha); 7795 } 7796 ret = PCI_ERS_RESULT_DISCONNECT; 7797 } 7798 out: 7799 ql_dbg(ql_dbg_aer, vha, 0x600d, 7800 "PCI error detected returning [%x].\n", ret); 7801 return ret; 7802 } 7803 7804 static pci_ers_result_t 7805 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7806 { 7807 int risc_paused = 0; 7808 uint32_t stat; 7809 unsigned long flags; 7810 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7811 struct qla_hw_data *ha = base_vha->hw; 7812 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7813 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7814 7815 ql_log(ql_log_warn, base_vha, 0x9000, 7816 "mmio enabled\n"); 7817 7818 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7819 7820 if (IS_QLA82XX(ha)) 7821 return PCI_ERS_RESULT_RECOVERED; 7822 7823 if (qla2x00_isp_reg_stat(ha)) { 7824 ql_log(ql_log_info, base_vha, 0x803f, 7825 "During mmio enabled, PCI/Register disconnect still detected.\n"); 7826 goto out; 7827 } 7828 7829 spin_lock_irqsave(&ha->hardware_lock, flags); 7830 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7831 stat = rd_reg_word(®->hccr); 7832 if (stat & HCCR_RISC_PAUSE) 7833 risc_paused = 1; 7834 } else if (IS_QLA23XX(ha)) { 7835 stat = rd_reg_dword(®->u.isp2300.host_status); 7836 if (stat & HSR_RISC_PAUSED) 7837 risc_paused = 1; 7838 } else if (IS_FWI2_CAPABLE(ha)) { 7839 stat = rd_reg_dword(®24->host_status); 7840 if (stat & HSRX_RISC_PAUSED) 7841 risc_paused = 1; 7842 } 7843 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7844 7845 if (risc_paused) { 7846 ql_log(ql_log_info, base_vha, 0x9003, 7847 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7848 qla2xxx_dump_fw(base_vha); 7849 } 7850 out: 7851 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7852 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7853 "mmio enabled returning.\n"); 7854 return PCI_ERS_RESULT_NEED_RESET; 7855 } 7856 7857 static pci_ers_result_t 7858 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7859 { 7860 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7861 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7862 struct qla_hw_data *ha = base_vha->hw; 7863 int rc; 7864 struct qla_qpair *qpair = NULL; 7865 7866 ql_log(ql_log_warn, base_vha, 0x9004, 7867 "Slot Reset.\n"); 7868 7869 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7870 /* Workaround: qla2xxx driver which access hardware earlier 7871 * needs error state to be pci_channel_io_online. 7872 * Otherwise mailbox command timesout. 7873 */ 7874 pdev->error_state = pci_channel_io_normal; 7875 7876 pci_restore_state(pdev); 7877 7878 /* pci_restore_state() clears the saved_state flag of the device 7879 * save restored state which resets saved_state flag 7880 */ 7881 pci_save_state(pdev); 7882 7883 if (ha->mem_only) 7884 rc = pci_enable_device_mem(pdev); 7885 else 7886 rc = pci_enable_device(pdev); 7887 7888 if (rc) { 7889 ql_log(ql_log_warn, base_vha, 0x9005, 7890 "Can't re-enable PCI device after reset.\n"); 7891 goto exit_slot_reset; 7892 } 7893 7894 7895 if (ha->isp_ops->pci_config(base_vha)) 7896 goto exit_slot_reset; 7897 7898 mutex_lock(&ha->mq_lock); 7899 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7900 qpair->online = 1; 7901 mutex_unlock(&ha->mq_lock); 7902 7903 ha->flags.eeh_busy = 0; 7904 base_vha->flags.online = 1; 7905 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7906 ha->isp_ops->abort_isp(base_vha); 7907 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7908 7909 if (qla2x00_isp_reg_stat(ha)) { 7910 ha->flags.eeh_busy = 1; 7911 qla_pci_error_cleanup(base_vha); 7912 ql_log(ql_log_warn, base_vha, 0x9005, 7913 "Device unable to recover from PCI error.\n"); 7914 } else { 7915 ret = PCI_ERS_RESULT_RECOVERED; 7916 } 7917 7918 exit_slot_reset: 7919 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7920 "Slot Reset returning %x.\n", ret); 7921 7922 return ret; 7923 } 7924 7925 static void 7926 qla2xxx_pci_resume(struct pci_dev *pdev) 7927 { 7928 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7929 struct qla_hw_data *ha = base_vha->hw; 7930 int ret; 7931 7932 ql_log(ql_log_warn, base_vha, 0x900f, 7933 "Pci Resume.\n"); 7934 7935 7936 ret = qla2x00_wait_for_hba_online(base_vha); 7937 if (ret != QLA_SUCCESS) { 7938 ql_log(ql_log_fatal, base_vha, 0x9002, 7939 "The device failed to resume I/O from slot/link_reset.\n"); 7940 } 7941 ha->pci_error_state = QLA_PCI_RESUME; 7942 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7943 "Pci Resume returning.\n"); 7944 } 7945 7946 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7947 { 7948 struct qla_hw_data *ha = vha->hw; 7949 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7950 bool do_cleanup = false; 7951 unsigned long flags; 7952 7953 if (ha->flags.eeh_busy) 7954 return; 7955 7956 spin_lock_irqsave(&base_vha->work_lock, flags); 7957 if (!ha->flags.eeh_busy) { 7958 ha->eeh_jif = jiffies; 7959 ha->flags.eeh_flush = 0; 7960 7961 ha->flags.eeh_busy = 1; 7962 do_cleanup = true; 7963 } 7964 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7965 7966 if (do_cleanup) 7967 qla_pci_error_cleanup(base_vha); 7968 } 7969 7970 /* 7971 * this routine will schedule a task to pause IO from interrupt context 7972 * if caller sees a PCIE error event (register read = 0xf's) 7973 */ 7974 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7975 { 7976 struct qla_hw_data *ha = vha->hw; 7977 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7978 7979 if (ha->flags.eeh_busy) 7980 return; 7981 7982 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7983 qla2xxx_wake_dpc(base_vha); 7984 } 7985 7986 static void 7987 qla_pci_reset_prepare(struct pci_dev *pdev) 7988 { 7989 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7990 struct qla_hw_data *ha = base_vha->hw; 7991 struct qla_qpair *qpair; 7992 7993 ql_log(ql_log_warn, base_vha, 0xffff, 7994 "%s.\n", __func__); 7995 7996 /* 7997 * PCI FLR/function reset is about to reset the 7998 * slot. Stop the chip to stop all DMA access. 7999 * It is assumed that pci_reset_done will be called 8000 * after FLR to resume Chip operation. 8001 */ 8002 ha->flags.eeh_busy = 1; 8003 mutex_lock(&ha->mq_lock); 8004 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8005 qpair->online = 0; 8006 mutex_unlock(&ha->mq_lock); 8007 8008 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8009 qla2x00_abort_isp_cleanup(base_vha); 8010 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 8011 } 8012 8013 static void 8014 qla_pci_reset_done(struct pci_dev *pdev) 8015 { 8016 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8017 struct qla_hw_data *ha = base_vha->hw; 8018 struct qla_qpair *qpair; 8019 8020 ql_log(ql_log_warn, base_vha, 0xffff, 8021 "%s.\n", __func__); 8022 8023 /* 8024 * FLR just completed by PCI layer. Resume adapter 8025 */ 8026 ha->flags.eeh_busy = 0; 8027 mutex_lock(&ha->mq_lock); 8028 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8029 qpair->online = 1; 8030 mutex_unlock(&ha->mq_lock); 8031 8032 base_vha->flags.online = 1; 8033 ha->isp_ops->abort_isp(base_vha); 8034 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8035 } 8036 8037 static void qla2xxx_map_queues(struct Scsi_Host *shost) 8038 { 8039 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 8040 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 8041 8042 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 8043 blk_mq_map_queues(qmap); 8044 else 8045 blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 8046 } 8047 8048 struct scsi_host_template qla2xxx_driver_template = { 8049 .module = THIS_MODULE, 8050 .name = QLA2XXX_DRIVER_NAME, 8051 .queuecommand = qla2xxx_queuecommand, 8052 8053 .eh_timed_out = fc_eh_timed_out, 8054 .eh_abort_handler = qla2xxx_eh_abort, 8055 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 8056 .eh_device_reset_handler = qla2xxx_eh_device_reset, 8057 .eh_target_reset_handler = qla2xxx_eh_target_reset, 8058 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 8059 .eh_host_reset_handler = qla2xxx_eh_host_reset, 8060 8061 .slave_configure = qla2xxx_slave_configure, 8062 8063 .slave_alloc = qla2xxx_slave_alloc, 8064 .slave_destroy = qla2xxx_slave_destroy, 8065 .scan_finished = qla2xxx_scan_finished, 8066 .scan_start = qla2xxx_scan_start, 8067 .change_queue_depth = scsi_change_queue_depth, 8068 .map_queues = qla2xxx_map_queues, 8069 .this_id = -1, 8070 .cmd_per_lun = 3, 8071 .sg_tablesize = SG_ALL, 8072 8073 .max_sectors = 0xFFFF, 8074 .shost_groups = qla2x00_host_groups, 8075 8076 .supported_mode = MODE_INITIATOR, 8077 .track_queue_depth = 1, 8078 .cmd_size = sizeof(srb_t), 8079 }; 8080 8081 static const struct pci_error_handlers qla2xxx_err_handler = { 8082 .error_detected = qla2xxx_pci_error_detected, 8083 .mmio_enabled = qla2xxx_pci_mmio_enabled, 8084 .slot_reset = qla2xxx_pci_slot_reset, 8085 .resume = qla2xxx_pci_resume, 8086 .reset_prepare = qla_pci_reset_prepare, 8087 .reset_done = qla_pci_reset_done, 8088 }; 8089 8090 static struct pci_device_id qla2xxx_pci_tbl[] = { 8091 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 8092 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 8093 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 8094 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 8095 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 8096 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 8097 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 8098 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 8099 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 8100 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 8101 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 8102 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 8103 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 8104 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 8105 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 8106 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 8107 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 8108 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 8109 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 8110 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 8111 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 8112 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 8113 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 8114 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 8115 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 8116 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 8117 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 8118 { 0 }, 8119 }; 8120 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 8121 8122 static struct pci_driver qla2xxx_pci_driver = { 8123 .name = QLA2XXX_DRIVER_NAME, 8124 .driver = { 8125 .owner = THIS_MODULE, 8126 }, 8127 .id_table = qla2xxx_pci_tbl, 8128 .probe = qla2x00_probe_one, 8129 .remove = qla2x00_remove_one, 8130 .shutdown = qla2x00_shutdown, 8131 .err_handler = &qla2xxx_err_handler, 8132 }; 8133 8134 static const struct file_operations apidev_fops = { 8135 .owner = THIS_MODULE, 8136 .llseek = noop_llseek, 8137 }; 8138 8139 /** 8140 * qla2x00_module_init - Module initialization. 8141 **/ 8142 static int __init 8143 qla2x00_module_init(void) 8144 { 8145 int ret = 0; 8146 8147 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8148 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8149 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8150 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8151 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8152 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8153 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8154 BUILD_BUG_ON(sizeof(request_t) != 64); 8155 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8156 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8157 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8158 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8159 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8160 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8161 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8162 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8163 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8164 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8165 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8166 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8167 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8168 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8169 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8170 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8171 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8172 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8173 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8174 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8175 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8176 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8177 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8178 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8179 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8180 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8181 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8182 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8183 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8184 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8185 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8186 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8187 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8188 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8189 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8190 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8191 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8192 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8193 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8194 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8195 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8196 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8197 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8198 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8199 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8200 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8201 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8202 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8203 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8204 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8205 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8206 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8207 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8208 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8209 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8210 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8211 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8212 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8213 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8214 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8215 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8216 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8217 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8218 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8219 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8220 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8221 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8222 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8223 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8224 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8225 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8226 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8227 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8228 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8229 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8230 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8231 8232 qla_trace_init(); 8233 8234 /* Allocate cache for SRBs. */ 8235 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8236 SLAB_HWCACHE_ALIGN, NULL); 8237 if (srb_cachep == NULL) { 8238 ql_log(ql_log_fatal, NULL, 0x0001, 8239 "Unable to allocate SRB cache...Failing load!.\n"); 8240 return -ENOMEM; 8241 } 8242 8243 /* Initialize target kmem_cache and mem_pools */ 8244 ret = qlt_init(); 8245 if (ret < 0) { 8246 goto destroy_cache; 8247 } else if (ret > 0) { 8248 /* 8249 * If initiator mode is explictly disabled by qlt_init(), 8250 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8251 * performing scsi_scan_target() during LOOP UP event. 8252 */ 8253 qla2xxx_transport_functions.disable_target_scan = 1; 8254 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8255 } 8256 8257 /* Derive version string. */ 8258 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8259 if (ql2xextended_error_logging) 8260 strcat(qla2x00_version_str, "-debug"); 8261 if (ql2xextended_error_logging == 1) 8262 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8263 8264 qla2xxx_transport_template = 8265 fc_attach_transport(&qla2xxx_transport_functions); 8266 if (!qla2xxx_transport_template) { 8267 ql_log(ql_log_fatal, NULL, 0x0002, 8268 "fc_attach_transport failed...Failing load!.\n"); 8269 ret = -ENODEV; 8270 goto qlt_exit; 8271 } 8272 8273 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8274 if (apidev_major < 0) { 8275 ql_log(ql_log_fatal, NULL, 0x0003, 8276 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8277 } 8278 8279 qla2xxx_transport_vport_template = 8280 fc_attach_transport(&qla2xxx_transport_vport_functions); 8281 if (!qla2xxx_transport_vport_template) { 8282 ql_log(ql_log_fatal, NULL, 0x0004, 8283 "fc_attach_transport vport failed...Failing load!.\n"); 8284 ret = -ENODEV; 8285 goto unreg_chrdev; 8286 } 8287 ql_log(ql_log_info, NULL, 0x0005, 8288 "QLogic Fibre Channel HBA Driver: %s.\n", 8289 qla2x00_version_str); 8290 ret = pci_register_driver(&qla2xxx_pci_driver); 8291 if (ret) { 8292 ql_log(ql_log_fatal, NULL, 0x0006, 8293 "pci_register_driver failed...ret=%d Failing load!.\n", 8294 ret); 8295 goto release_vport_transport; 8296 } 8297 return ret; 8298 8299 release_vport_transport: 8300 fc_release_transport(qla2xxx_transport_vport_template); 8301 8302 unreg_chrdev: 8303 if (apidev_major >= 0) 8304 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8305 fc_release_transport(qla2xxx_transport_template); 8306 8307 qlt_exit: 8308 qlt_exit(); 8309 8310 destroy_cache: 8311 kmem_cache_destroy(srb_cachep); 8312 8313 qla_trace_uninit(); 8314 return ret; 8315 } 8316 8317 /** 8318 * qla2x00_module_exit - Module cleanup. 8319 **/ 8320 static void __exit 8321 qla2x00_module_exit(void) 8322 { 8323 pci_unregister_driver(&qla2xxx_pci_driver); 8324 qla2x00_release_firmware(); 8325 kmem_cache_destroy(ctx_cachep); 8326 fc_release_transport(qla2xxx_transport_vport_template); 8327 if (apidev_major >= 0) 8328 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8329 fc_release_transport(qla2xxx_transport_template); 8330 qlt_exit(); 8331 kmem_cache_destroy(srb_cachep); 8332 qla_trace_uninit(); 8333 } 8334 8335 module_init(qla2x00_module_init); 8336 module_exit(qla2x00_module_exit); 8337 8338 MODULE_AUTHOR("QLogic Corporation"); 8339 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8340 MODULE_LICENSE("GPL"); 8341 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8342 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8343 MODULE_FIRMWARE(FW_FILE_ISP2300); 8344 MODULE_FIRMWARE(FW_FILE_ISP2322); 8345 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8346 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8347