1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <scsi/scsi_tcq.h> 18 #include <scsi/scsicam.h> 19 #include <scsi/scsi_transport.h> 20 #include <scsi/scsi_transport_fc.h> 21 22 #include "qla_target.h" 23 24 /* 25 * Driver version 26 */ 27 char qla2x00_version_str[40]; 28 29 static int apidev_major; 30 31 /* 32 * SRB allocation cache 33 */ 34 struct kmem_cache *srb_cachep; 35 36 /* 37 * CT6 CTX allocation cache 38 */ 39 static struct kmem_cache *ctx_cachep; 40 /* 41 * error level for logging 42 */ 43 int ql_errlev = ql_log_all; 44 45 static int ql2xenableclass2; 46 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 47 MODULE_PARM_DESC(ql2xenableclass2, 48 "Specify if Class 2 operations are supported from the very " 49 "beginning. Default is 0 - class 2 not supported."); 50 51 52 int ql2xlogintimeout = 20; 53 module_param(ql2xlogintimeout, int, S_IRUGO); 54 MODULE_PARM_DESC(ql2xlogintimeout, 55 "Login timeout value in seconds."); 56 57 int qlport_down_retry; 58 module_param(qlport_down_retry, int, S_IRUGO); 59 MODULE_PARM_DESC(qlport_down_retry, 60 "Maximum number of command retries to a port that returns " 61 "a PORT-DOWN status."); 62 63 int ql2xplogiabsentdevice; 64 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 65 MODULE_PARM_DESC(ql2xplogiabsentdevice, 66 "Option to enable PLOGI to devices that are not present after " 67 "a Fabric scan. This is needed for several broken switches. " 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI."); 69 70 int ql2xloginretrycount = 0; 71 module_param(ql2xloginretrycount, int, S_IRUGO); 72 MODULE_PARM_DESC(ql2xloginretrycount, 73 "Specify an alternate value for the NVRAM login retry count."); 74 75 int ql2xallocfwdump = 1; 76 module_param(ql2xallocfwdump, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xallocfwdump, 78 "Option to enable allocation of memory for a firmware dump " 79 "during HBA initialization. Memory allocation requirements " 80 "vary by ISP type. Default is 1 - allocate memory."); 81 82 int ql2xextended_error_logging; 83 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 84 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 85 MODULE_PARM_DESC(ql2xextended_error_logging, 86 "Option to enable extended error logging,\n" 87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 98 "\t\t0x1e400000 - Preferred value for capturing essential " 99 "debug information (equivalent to old " 100 "ql2xextended_error_logging=1).\n" 101 "\t\tDo LOGICAL OR of the value to enable more than one level"); 102 103 int ql2xshiftctondsd = 6; 104 module_param(ql2xshiftctondsd, int, S_IRUGO); 105 MODULE_PARM_DESC(ql2xshiftctondsd, 106 "Set to control shifting of command type processing " 107 "based on total number of SG elements."); 108 109 int ql2xfdmienable=1; 110 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 111 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 112 MODULE_PARM_DESC(ql2xfdmienable, 113 "Enables FDMI registrations. " 114 "0 - no FDMI. Default is 1 - perform FDMI."); 115 116 #define MAX_Q_DEPTH 64 117 static int ql2xmaxqdepth = MAX_Q_DEPTH; 118 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 119 MODULE_PARM_DESC(ql2xmaxqdepth, 120 "Maximum queue depth to set for each LUN. " 121 "Default is 64."); 122 123 #if (IS_ENABLED(CONFIG_NVME_FC)) 124 int ql2xenabledif; 125 #else 126 int ql2xenabledif = 2; 127 #endif 128 module_param(ql2xenabledif, int, S_IRUGO); 129 MODULE_PARM_DESC(ql2xenabledif, 130 " Enable T10-CRC-DIF:\n" 131 " Default is 2.\n" 132 " 0 -- No DIF Support\n" 133 " 1 -- Enable DIF for all types\n" 134 " 2 -- Enable DIF for all types, except Type 0.\n"); 135 136 #if (IS_ENABLED(CONFIG_NVME_FC)) 137 int ql2xnvmeenable = 1; 138 #else 139 int ql2xnvmeenable; 140 #endif 141 module_param(ql2xnvmeenable, int, 0644); 142 MODULE_PARM_DESC(ql2xnvmeenable, 143 "Enables NVME support. " 144 "0 - no NVMe. Default is Y"); 145 146 int ql2xenablehba_err_chk = 2; 147 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 148 MODULE_PARM_DESC(ql2xenablehba_err_chk, 149 " Enable T10-CRC-DIF Error isolation by HBA:\n" 150 " Default is 2.\n" 151 " 0 -- Error isolation disabled\n" 152 " 1 -- Error isolation enabled only for DIX Type 0\n" 153 " 2 -- Error isolation enabled for all Types\n"); 154 155 int ql2xiidmaenable=1; 156 module_param(ql2xiidmaenable, int, S_IRUGO); 157 MODULE_PARM_DESC(ql2xiidmaenable, 158 "Enables iIDMA settings " 159 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 160 161 int ql2xmqsupport = 1; 162 module_param(ql2xmqsupport, int, S_IRUGO); 163 MODULE_PARM_DESC(ql2xmqsupport, 164 "Enable on demand multiple queue pairs support " 165 "Default is 1 for supported. " 166 "Set it to 0 to turn off mq qpair support."); 167 168 int ql2xfwloadbin; 169 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 170 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xfwloadbin, 172 "Option to specify location from which to load ISP firmware:.\n" 173 " 2 -- load firmware via the request_firmware() (hotplug).\n" 174 " interface.\n" 175 " 1 -- load firmware from flash.\n" 176 " 0 -- use default semantics.\n"); 177 178 int ql2xetsenable; 179 module_param(ql2xetsenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xetsenable, 181 "Enables firmware ETS burst." 182 "Default is 0 - skip ETS enablement."); 183 184 int ql2xdbwr = 1; 185 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 186 MODULE_PARM_DESC(ql2xdbwr, 187 "Option to specify scheme for request queue posting.\n" 188 " 0 -- Regular doorbell.\n" 189 " 1 -- CAMRAM doorbell (faster).\n"); 190 191 int ql2xtargetreset = 1; 192 module_param(ql2xtargetreset, int, S_IRUGO); 193 MODULE_PARM_DESC(ql2xtargetreset, 194 "Enable target reset." 195 "Default is 1 - use hw defaults."); 196 197 int ql2xgffidenable; 198 module_param(ql2xgffidenable, int, S_IRUGO); 199 MODULE_PARM_DESC(ql2xgffidenable, 200 "Enables GFF_ID checks of port type. " 201 "Default is 0 - Do not use GFF_ID information."); 202 203 int ql2xasynctmfenable = 1; 204 module_param(ql2xasynctmfenable, int, S_IRUGO); 205 MODULE_PARM_DESC(ql2xasynctmfenable, 206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 207 "Default is 0 - Issue TM IOCBs via mailbox mechanism."); 208 209 int ql2xdontresethba; 210 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 211 MODULE_PARM_DESC(ql2xdontresethba, 212 "Option to specify reset behaviour.\n" 213 " 0 (Default) -- Reset on failure.\n" 214 " 1 -- Do not reset on failure.\n"); 215 216 uint64_t ql2xmaxlun = MAX_LUNS; 217 module_param(ql2xmaxlun, ullong, S_IRUGO); 218 MODULE_PARM_DESC(ql2xmaxlun, 219 "Defines the maximum LU number to register with the SCSI " 220 "midlayer. Default is 65535."); 221 222 int ql2xmdcapmask = 0x1F; 223 module_param(ql2xmdcapmask, int, S_IRUGO); 224 MODULE_PARM_DESC(ql2xmdcapmask, 225 "Set the Minidump driver capture mask level. " 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 227 228 int ql2xmdenable = 1; 229 module_param(ql2xmdenable, int, S_IRUGO); 230 MODULE_PARM_DESC(ql2xmdenable, 231 "Enable/disable MiniDump. " 232 "0 - MiniDump disabled. " 233 "1 (Default) - MiniDump enabled."); 234 235 int ql2xexlogins = 0; 236 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 237 MODULE_PARM_DESC(ql2xexlogins, 238 "Number of extended Logins. " 239 "0 (Default)- Disabled."); 240 241 int ql2xexchoffld = 1024; 242 module_param(ql2xexchoffld, uint, 0644); 243 MODULE_PARM_DESC(ql2xexchoffld, 244 "Number of target exchanges."); 245 246 int ql2xiniexchg = 1024; 247 module_param(ql2xiniexchg, uint, 0644); 248 MODULE_PARM_DESC(ql2xiniexchg, 249 "Number of initiator exchanges."); 250 251 int ql2xfwholdabts = 0; 252 module_param(ql2xfwholdabts, int, S_IRUGO); 253 MODULE_PARM_DESC(ql2xfwholdabts, 254 "Allow FW to hold status IOCB until ABTS rsp received. " 255 "0 (Default) Do not set fw option. " 256 "1 - Set fw option to hold ABTS."); 257 258 int ql2xmvasynctoatio = 1; 259 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 260 MODULE_PARM_DESC(ql2xmvasynctoatio, 261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 262 "0 (Default). Do not move IOCBs" 263 "1 - Move IOCBs."); 264 265 int ql2xautodetectsfp = 1; 266 module_param(ql2xautodetectsfp, int, 0444); 267 MODULE_PARM_DESC(ql2xautodetectsfp, 268 "Detect SFP range and set appropriate distance.\n" 269 "1 (Default): Enable\n"); 270 271 int ql2xenablemsix = 1; 272 module_param(ql2xenablemsix, int, 0444); 273 MODULE_PARM_DESC(ql2xenablemsix, 274 "Set to enable MSI or MSI-X interrupt mechanism.\n" 275 " Default is 1, enable MSI-X interrupt mechanism.\n" 276 " 0 -- enable traditional pin-based mechanism.\n" 277 " 1 -- enable MSI-X interrupt mechanism.\n" 278 " 2 -- enable MSI interrupt mechanism.\n"); 279 280 int qla2xuseresexchforels; 281 module_param(qla2xuseresexchforels, int, 0444); 282 MODULE_PARM_DESC(qla2xuseresexchforels, 283 "Reserve 1/2 of emergency exchanges for ELS.\n" 284 " 0 (default): disabled"); 285 286 /* 287 * SCSI host template entry points 288 */ 289 static int qla2xxx_slave_configure(struct scsi_device * device); 290 static int qla2xxx_slave_alloc(struct scsi_device *); 291 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); 292 static void qla2xxx_scan_start(struct Scsi_Host *); 293 static void qla2xxx_slave_destroy(struct scsi_device *); 294 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); 295 static int qla2xxx_eh_abort(struct scsi_cmnd *); 296 static int qla2xxx_eh_device_reset(struct scsi_cmnd *); 297 static int qla2xxx_eh_target_reset(struct scsi_cmnd *); 298 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); 299 static int qla2xxx_eh_host_reset(struct scsi_cmnd *); 300 301 static void qla2x00_clear_drv_active(struct qla_hw_data *); 302 static void qla2x00_free_device(scsi_qla_host_t *); 303 static int qla2xxx_map_queues(struct Scsi_Host *shost); 304 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 305 306 struct scsi_host_template qla2xxx_driver_template = { 307 .module = THIS_MODULE, 308 .name = QLA2XXX_DRIVER_NAME, 309 .queuecommand = qla2xxx_queuecommand, 310 311 .eh_timed_out = fc_eh_timed_out, 312 .eh_abort_handler = qla2xxx_eh_abort, 313 .eh_device_reset_handler = qla2xxx_eh_device_reset, 314 .eh_target_reset_handler = qla2xxx_eh_target_reset, 315 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 316 .eh_host_reset_handler = qla2xxx_eh_host_reset, 317 318 .slave_configure = qla2xxx_slave_configure, 319 320 .slave_alloc = qla2xxx_slave_alloc, 321 .slave_destroy = qla2xxx_slave_destroy, 322 .scan_finished = qla2xxx_scan_finished, 323 .scan_start = qla2xxx_scan_start, 324 .change_queue_depth = scsi_change_queue_depth, 325 .map_queues = qla2xxx_map_queues, 326 .this_id = -1, 327 .cmd_per_lun = 3, 328 .use_clustering = ENABLE_CLUSTERING, 329 .sg_tablesize = SG_ALL, 330 331 .max_sectors = 0xFFFF, 332 .shost_attrs = qla2x00_host_attrs, 333 334 .supported_mode = MODE_INITIATOR, 335 .track_queue_depth = 1, 336 }; 337 338 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 339 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 340 341 /* TODO Convert to inlines 342 * 343 * Timer routines 344 */ 345 346 __inline__ void 347 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 348 { 349 timer_setup(&vha->timer, qla2x00_timer, 0); 350 vha->timer.expires = jiffies + interval * HZ; 351 add_timer(&vha->timer); 352 vha->timer_active = 1; 353 } 354 355 static inline void 356 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 357 { 358 /* Currently used for 82XX only. */ 359 if (vha->device_flags & DFLG_DEV_FAILED) { 360 ql_dbg(ql_dbg_timer, vha, 0x600d, 361 "Device in a failed state, returning.\n"); 362 return; 363 } 364 365 mod_timer(&vha->timer, jiffies + interval * HZ); 366 } 367 368 static __inline__ void 369 qla2x00_stop_timer(scsi_qla_host_t *vha) 370 { 371 del_timer_sync(&vha->timer); 372 vha->timer_active = 0; 373 } 374 375 static int qla2x00_do_dpc(void *data); 376 377 static void qla2x00_rst_aen(scsi_qla_host_t *); 378 379 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 380 struct req_que **, struct rsp_que **); 381 static void qla2x00_free_fw_dump(struct qla_hw_data *); 382 static void qla2x00_mem_free(struct qla_hw_data *); 383 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 384 struct qla_qpair *qpair); 385 386 /* -------------------------------------------------------------------------- */ 387 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 388 struct rsp_que *rsp) 389 { 390 struct qla_hw_data *ha = vha->hw; 391 rsp->qpair = ha->base_qpair; 392 rsp->req = req; 393 ha->base_qpair->req = req; 394 ha->base_qpair->rsp = rsp; 395 ha->base_qpair->vha = vha; 396 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 397 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 398 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 399 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 400 ha->base_qpair->enable_class_2 = ql2xenableclass2; 401 /* init qpair to this cpu. Will adjust at run time. */ 402 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 403 ha->base_qpair->pdev = ha->pdev; 404 405 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) 406 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 407 } 408 409 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 410 struct rsp_que *rsp) 411 { 412 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 413 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, 414 GFP_KERNEL); 415 if (!ha->req_q_map) { 416 ql_log(ql_log_fatal, vha, 0x003b, 417 "Unable to allocate memory for request queue ptrs.\n"); 418 goto fail_req_map; 419 } 420 421 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, 422 GFP_KERNEL); 423 if (!ha->rsp_q_map) { 424 ql_log(ql_log_fatal, vha, 0x003c, 425 "Unable to allocate memory for response queue ptrs.\n"); 426 goto fail_rsp_map; 427 } 428 429 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 430 if (ha->base_qpair == NULL) { 431 ql_log(ql_log_warn, vha, 0x00e0, 432 "Failed to allocate base queue pair memory.\n"); 433 goto fail_base_qpair; 434 } 435 436 qla_init_base_qpair(vha, req, rsp); 437 438 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 439 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 440 GFP_KERNEL); 441 if (!ha->queue_pair_map) { 442 ql_log(ql_log_fatal, vha, 0x0180, 443 "Unable to allocate memory for queue pair ptrs.\n"); 444 goto fail_qpair_map; 445 } 446 } 447 448 /* 449 * Make sure we record at least the request and response queue zero in 450 * case we need to free them if part of the probe fails. 451 */ 452 ha->rsp_q_map[0] = rsp; 453 ha->req_q_map[0] = req; 454 set_bit(0, ha->rsp_qid_map); 455 set_bit(0, ha->req_qid_map); 456 return 0; 457 458 fail_qpair_map: 459 kfree(ha->base_qpair); 460 ha->base_qpair = NULL; 461 fail_base_qpair: 462 kfree(ha->rsp_q_map); 463 ha->rsp_q_map = NULL; 464 fail_rsp_map: 465 kfree(ha->req_q_map); 466 ha->req_q_map = NULL; 467 fail_req_map: 468 return -ENOMEM; 469 } 470 471 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 472 { 473 if (IS_QLAFX00(ha)) { 474 if (req && req->ring_fx00) 475 dma_free_coherent(&ha->pdev->dev, 476 (req->length_fx00 + 1) * sizeof(request_t), 477 req->ring_fx00, req->dma_fx00); 478 } else if (req && req->ring) 479 dma_free_coherent(&ha->pdev->dev, 480 (req->length + 1) * sizeof(request_t), 481 req->ring, req->dma); 482 483 if (req) 484 kfree(req->outstanding_cmds); 485 486 kfree(req); 487 } 488 489 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 490 { 491 if (IS_QLAFX00(ha)) { 492 if (rsp && rsp->ring_fx00) 493 dma_free_coherent(&ha->pdev->dev, 494 (rsp->length_fx00 + 1) * sizeof(request_t), 495 rsp->ring_fx00, rsp->dma_fx00); 496 } else if (rsp && rsp->ring) { 497 dma_free_coherent(&ha->pdev->dev, 498 (rsp->length + 1) * sizeof(response_t), 499 rsp->ring, rsp->dma); 500 } 501 kfree(rsp); 502 } 503 504 static void qla2x00_free_queues(struct qla_hw_data *ha) 505 { 506 struct req_que *req; 507 struct rsp_que *rsp; 508 int cnt; 509 unsigned long flags; 510 511 if (ha->queue_pair_map) { 512 kfree(ha->queue_pair_map); 513 ha->queue_pair_map = NULL; 514 } 515 if (ha->base_qpair) { 516 kfree(ha->base_qpair); 517 ha->base_qpair = NULL; 518 } 519 520 spin_lock_irqsave(&ha->hardware_lock, flags); 521 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 522 if (!test_bit(cnt, ha->req_qid_map)) 523 continue; 524 525 req = ha->req_q_map[cnt]; 526 clear_bit(cnt, ha->req_qid_map); 527 ha->req_q_map[cnt] = NULL; 528 529 spin_unlock_irqrestore(&ha->hardware_lock, flags); 530 qla2x00_free_req_que(ha, req); 531 spin_lock_irqsave(&ha->hardware_lock, flags); 532 } 533 spin_unlock_irqrestore(&ha->hardware_lock, flags); 534 535 kfree(ha->req_q_map); 536 ha->req_q_map = NULL; 537 538 539 spin_lock_irqsave(&ha->hardware_lock, flags); 540 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 541 if (!test_bit(cnt, ha->rsp_qid_map)) 542 continue; 543 544 rsp = ha->rsp_q_map[cnt]; 545 clear_bit(cnt, ha->rsp_qid_map); 546 ha->rsp_q_map[cnt] = NULL; 547 spin_unlock_irqrestore(&ha->hardware_lock, flags); 548 qla2x00_free_rsp_que(ha, rsp); 549 spin_lock_irqsave(&ha->hardware_lock, flags); 550 } 551 spin_unlock_irqrestore(&ha->hardware_lock, flags); 552 553 kfree(ha->rsp_q_map); 554 ha->rsp_q_map = NULL; 555 } 556 557 static char * 558 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 559 { 560 struct qla_hw_data *ha = vha->hw; 561 static char *pci_bus_modes[] = { 562 "33", "66", "100", "133", 563 }; 564 uint16_t pci_bus; 565 566 strcpy(str, "PCI"); 567 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 568 if (pci_bus) { 569 strcat(str, "-X ("); 570 strcat(str, pci_bus_modes[pci_bus]); 571 } else { 572 pci_bus = (ha->pci_attr & BIT_8) >> 8; 573 strcat(str, " ("); 574 strcat(str, pci_bus_modes[pci_bus]); 575 } 576 strcat(str, " MHz)"); 577 578 return (str); 579 } 580 581 static char * 582 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 583 { 584 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 585 struct qla_hw_data *ha = vha->hw; 586 uint32_t pci_bus; 587 588 if (pci_is_pcie(ha->pdev)) { 589 char lwstr[6]; 590 uint32_t lstat, lspeed, lwidth; 591 592 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 593 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 594 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 595 596 strcpy(str, "PCIe ("); 597 switch (lspeed) { 598 case 1: 599 strcat(str, "2.5GT/s "); 600 break; 601 case 2: 602 strcat(str, "5.0GT/s "); 603 break; 604 case 3: 605 strcat(str, "8.0GT/s "); 606 break; 607 default: 608 strcat(str, "<unknown> "); 609 break; 610 } 611 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 612 strcat(str, lwstr); 613 614 return str; 615 } 616 617 strcpy(str, "PCI"); 618 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 619 if (pci_bus == 0 || pci_bus == 8) { 620 strcat(str, " ("); 621 strcat(str, pci_bus_modes[pci_bus >> 3]); 622 } else { 623 strcat(str, "-X "); 624 if (pci_bus & BIT_2) 625 strcat(str, "Mode 2"); 626 else 627 strcat(str, "Mode 1"); 628 strcat(str, " ("); 629 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 630 } 631 strcat(str, " MHz)"); 632 633 return str; 634 } 635 636 static char * 637 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 638 { 639 char un_str[10]; 640 struct qla_hw_data *ha = vha->hw; 641 642 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 643 ha->fw_minor_version, ha->fw_subminor_version); 644 645 if (ha->fw_attributes & BIT_9) { 646 strcat(str, "FLX"); 647 return (str); 648 } 649 650 switch (ha->fw_attributes & 0xFF) { 651 case 0x7: 652 strcat(str, "EF"); 653 break; 654 case 0x17: 655 strcat(str, "TP"); 656 break; 657 case 0x37: 658 strcat(str, "IP"); 659 break; 660 case 0x77: 661 strcat(str, "VI"); 662 break; 663 default: 664 sprintf(un_str, "(%x)", ha->fw_attributes); 665 strcat(str, un_str); 666 break; 667 } 668 if (ha->fw_attributes & 0x100) 669 strcat(str, "X"); 670 671 return (str); 672 } 673 674 static char * 675 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 676 { 677 struct qla_hw_data *ha = vha->hw; 678 679 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 680 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 681 return str; 682 } 683 684 void 685 qla2x00_sp_free_dma(void *ptr) 686 { 687 srb_t *sp = ptr; 688 struct qla_hw_data *ha = sp->vha->hw; 689 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 690 void *ctx = GET_CMD_CTX_SP(sp); 691 692 if (sp->flags & SRB_DMA_VALID) { 693 scsi_dma_unmap(cmd); 694 sp->flags &= ~SRB_DMA_VALID; 695 } 696 697 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 698 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 699 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 700 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 701 } 702 703 if (!ctx) 704 goto end; 705 706 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 707 /* List assured to be having elements */ 708 qla2x00_clean_dsd_pool(ha, ctx); 709 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 710 } 711 712 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 713 struct crc_context *ctx0 = ctx; 714 715 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 716 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 717 } 718 719 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 720 struct ct6_dsd *ctx1 = ctx; 721 722 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 723 ctx1->fcp_cmnd_dma); 724 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 725 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 726 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 727 mempool_free(ctx1, ha->ctx_mempool); 728 } 729 730 end: 731 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) { 732 CMD_SP(cmd) = NULL; 733 qla2x00_rel_sp(sp); 734 } 735 } 736 737 void 738 qla2x00_sp_compl(void *ptr, int res) 739 { 740 srb_t *sp = ptr; 741 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 742 743 cmd->result = res; 744 745 if (atomic_read(&sp->ref_count) == 0) { 746 ql_dbg(ql_dbg_io, sp->vha, 0x3015, 747 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 748 sp, GET_CMD_SP(sp)); 749 if (ql2xextended_error_logging & ql_dbg_io) 750 WARN_ON(atomic_read(&sp->ref_count) == 0); 751 return; 752 } 753 if (!atomic_dec_and_test(&sp->ref_count)) 754 return; 755 756 sp->free(sp); 757 cmd->scsi_done(cmd); 758 } 759 760 void 761 qla2xxx_qpair_sp_free_dma(void *ptr) 762 { 763 srb_t *sp = (srb_t *)ptr; 764 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 765 struct qla_hw_data *ha = sp->fcport->vha->hw; 766 void *ctx = GET_CMD_CTX_SP(sp); 767 768 if (sp->flags & SRB_DMA_VALID) { 769 scsi_dma_unmap(cmd); 770 sp->flags &= ~SRB_DMA_VALID; 771 } 772 773 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 774 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 775 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 776 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 777 } 778 779 if (!ctx) 780 goto end; 781 782 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 783 /* List assured to be having elements */ 784 qla2x00_clean_dsd_pool(ha, ctx); 785 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 786 } 787 788 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 789 struct crc_context *ctx0 = ctx; 790 791 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma); 792 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 793 } 794 795 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 796 struct ct6_dsd *ctx1 = ctx; 797 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 798 ctx1->fcp_cmnd_dma); 799 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 800 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 801 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 802 mempool_free(ctx1, ha->ctx_mempool); 803 } 804 end: 805 CMD_SP(cmd) = NULL; 806 qla2xxx_rel_qpair_sp(sp->qpair, sp); 807 } 808 809 void 810 qla2xxx_qpair_sp_compl(void *ptr, int res) 811 { 812 srb_t *sp = ptr; 813 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 814 815 cmd->result = res; 816 817 if (atomic_read(&sp->ref_count) == 0) { 818 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079, 819 "SP reference-count to ZERO -- sp=%p cmd=%p.\n", 820 sp, GET_CMD_SP(sp)); 821 if (ql2xextended_error_logging & ql_dbg_io) 822 WARN_ON(atomic_read(&sp->ref_count) == 0); 823 return; 824 } 825 if (!atomic_dec_and_test(&sp->ref_count)) 826 return; 827 828 sp->free(sp); 829 cmd->scsi_done(cmd); 830 } 831 832 /* If we are SP1 here, we need to still take and release the host_lock as SP1 833 * does not have the changes necessary to avoid taking host->host_lock. 834 */ 835 static int 836 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 837 { 838 scsi_qla_host_t *vha = shost_priv(host); 839 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 840 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 841 struct qla_hw_data *ha = vha->hw; 842 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 843 srb_t *sp; 844 int rval; 845 struct qla_qpair *qpair = NULL; 846 uint32_t tag; 847 uint16_t hwq; 848 849 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) { 850 cmd->result = DID_NO_CONNECT << 16; 851 goto qc24_fail_command; 852 } 853 854 if (ha->mqenable) { 855 if (shost_use_blk_mq(vha->host)) { 856 tag = blk_mq_unique_tag(cmd->request); 857 hwq = blk_mq_unique_tag_to_hwq(tag); 858 qpair = ha->queue_pair_map[hwq]; 859 } else if (vha->vp_idx && vha->qpair) { 860 qpair = vha->qpair; 861 } 862 863 if (qpair) 864 return qla2xxx_mqueuecommand(host, cmd, qpair); 865 } 866 867 if (ha->flags.eeh_busy) { 868 if (ha->flags.pci_channel_io_perm_failure) { 869 ql_dbg(ql_dbg_aer, vha, 0x9010, 870 "PCI Channel IO permanent failure, exiting " 871 "cmd=%p.\n", cmd); 872 cmd->result = DID_NO_CONNECT << 16; 873 } else { 874 ql_dbg(ql_dbg_aer, vha, 0x9011, 875 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 876 cmd->result = DID_REQUEUE << 16; 877 } 878 goto qc24_fail_command; 879 } 880 881 rval = fc_remote_port_chkready(rport); 882 if (rval) { 883 cmd->result = rval; 884 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 885 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 886 cmd, rval); 887 goto qc24_fail_command; 888 } 889 890 if (!vha->flags.difdix_supported && 891 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 892 ql_dbg(ql_dbg_io, vha, 0x3004, 893 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 894 cmd); 895 cmd->result = DID_NO_CONNECT << 16; 896 goto qc24_fail_command; 897 } 898 899 if (!fcport) { 900 cmd->result = DID_NO_CONNECT << 16; 901 goto qc24_fail_command; 902 } 903 904 if (atomic_read(&fcport->state) != FCS_ONLINE) { 905 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 906 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 907 ql_dbg(ql_dbg_io, vha, 0x3005, 908 "Returning DNC, fcport_state=%d loop_state=%d.\n", 909 atomic_read(&fcport->state), 910 atomic_read(&base_vha->loop_state)); 911 cmd->result = DID_NO_CONNECT << 16; 912 goto qc24_fail_command; 913 } 914 goto qc24_target_busy; 915 } 916 917 /* 918 * Return target busy if we've received a non-zero retry_delay_timer 919 * in a FCP_RSP. 920 */ 921 if (fcport->retry_delay_timestamp == 0) { 922 /* retry delay not set */ 923 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 924 fcport->retry_delay_timestamp = 0; 925 else 926 goto qc24_target_busy; 927 928 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 929 if (!sp) 930 goto qc24_host_busy; 931 932 sp->u.scmd.cmd = cmd; 933 sp->type = SRB_SCSI_CMD; 934 atomic_set(&sp->ref_count, 1); 935 CMD_SP(cmd) = (void *)sp; 936 sp->free = qla2x00_sp_free_dma; 937 sp->done = qla2x00_sp_compl; 938 939 rval = ha->isp_ops->start_scsi(sp); 940 if (rval != QLA_SUCCESS) { 941 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 942 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 943 goto qc24_host_busy_free_sp; 944 } 945 946 return 0; 947 948 qc24_host_busy_free_sp: 949 sp->free(sp); 950 951 qc24_host_busy: 952 return SCSI_MLQUEUE_HOST_BUSY; 953 954 qc24_target_busy: 955 return SCSI_MLQUEUE_TARGET_BUSY; 956 957 qc24_fail_command: 958 cmd->scsi_done(cmd); 959 960 return 0; 961 } 962 963 /* For MQ supported I/O */ 964 int 965 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 966 struct qla_qpair *qpair) 967 { 968 scsi_qla_host_t *vha = shost_priv(host); 969 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 970 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 971 struct qla_hw_data *ha = vha->hw; 972 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 973 srb_t *sp; 974 int rval; 975 976 rval = fc_remote_port_chkready(rport); 977 if (rval) { 978 cmd->result = rval; 979 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 980 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 981 cmd, rval); 982 goto qc24_fail_command; 983 } 984 985 if (!fcport) { 986 cmd->result = DID_NO_CONNECT << 16; 987 goto qc24_fail_command; 988 } 989 990 if (atomic_read(&fcport->state) != FCS_ONLINE) { 991 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 992 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 993 ql_dbg(ql_dbg_io, vha, 0x3077, 994 "Returning DNC, fcport_state=%d loop_state=%d.\n", 995 atomic_read(&fcport->state), 996 atomic_read(&base_vha->loop_state)); 997 cmd->result = DID_NO_CONNECT << 16; 998 goto qc24_fail_command; 999 } 1000 goto qc24_target_busy; 1001 } 1002 1003 /* 1004 * Return target busy if we've received a non-zero retry_delay_timer 1005 * in a FCP_RSP. 1006 */ 1007 if (fcport->retry_delay_timestamp == 0) { 1008 /* retry delay not set */ 1009 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1010 fcport->retry_delay_timestamp = 0; 1011 else 1012 goto qc24_target_busy; 1013 1014 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC); 1015 if (!sp) 1016 goto qc24_host_busy; 1017 1018 sp->u.scmd.cmd = cmd; 1019 sp->type = SRB_SCSI_CMD; 1020 atomic_set(&sp->ref_count, 1); 1021 CMD_SP(cmd) = (void *)sp; 1022 sp->free = qla2xxx_qpair_sp_free_dma; 1023 sp->done = qla2xxx_qpair_sp_compl; 1024 sp->qpair = qpair; 1025 1026 rval = ha->isp_ops->start_scsi_mq(sp); 1027 if (rval != QLA_SUCCESS) { 1028 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1029 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1030 if (rval == QLA_INTERFACE_ERROR) 1031 goto qc24_fail_command; 1032 goto qc24_host_busy_free_sp; 1033 } 1034 1035 return 0; 1036 1037 qc24_host_busy_free_sp: 1038 sp->free(sp); 1039 1040 qc24_host_busy: 1041 return SCSI_MLQUEUE_HOST_BUSY; 1042 1043 qc24_target_busy: 1044 return SCSI_MLQUEUE_TARGET_BUSY; 1045 1046 qc24_fail_command: 1047 cmd->scsi_done(cmd); 1048 1049 return 0; 1050 } 1051 1052 /* 1053 * qla2x00_eh_wait_on_command 1054 * Waits for the command to be returned by the Firmware for some 1055 * max time. 1056 * 1057 * Input: 1058 * cmd = Scsi Command to wait on. 1059 * 1060 * Return: 1061 * Not Found : 0 1062 * Found : 1 1063 */ 1064 static int 1065 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1066 { 1067 #define ABORT_POLLING_PERIOD 1000 1068 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1069 unsigned long wait_iter = ABORT_WAIT_ITER; 1070 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1071 struct qla_hw_data *ha = vha->hw; 1072 int ret = QLA_SUCCESS; 1073 1074 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1075 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1076 "Return:eh_wait.\n"); 1077 return ret; 1078 } 1079 1080 while (CMD_SP(cmd) && wait_iter--) { 1081 msleep(ABORT_POLLING_PERIOD); 1082 } 1083 if (CMD_SP(cmd)) 1084 ret = QLA_FUNCTION_FAILED; 1085 1086 return ret; 1087 } 1088 1089 /* 1090 * qla2x00_wait_for_hba_online 1091 * Wait till the HBA is online after going through 1092 * <= MAX_RETRIES_OF_ISP_ABORT or 1093 * finally HBA is disabled ie marked offline 1094 * 1095 * Input: 1096 * ha - pointer to host adapter structure 1097 * 1098 * Note: 1099 * Does context switching-Release SPIN_LOCK 1100 * (if any) before calling this routine. 1101 * 1102 * Return: 1103 * Success (Adapter is online) : 0 1104 * Failed (Adapter is offline/disabled) : 1 1105 */ 1106 int 1107 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1108 { 1109 int return_status; 1110 unsigned long wait_online; 1111 struct qla_hw_data *ha = vha->hw; 1112 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1113 1114 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1115 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1116 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1117 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1118 ha->dpc_active) && time_before(jiffies, wait_online)) { 1119 1120 msleep(1000); 1121 } 1122 if (base_vha->flags.online) 1123 return_status = QLA_SUCCESS; 1124 else 1125 return_status = QLA_FUNCTION_FAILED; 1126 1127 return (return_status); 1128 } 1129 1130 static inline int test_fcport_count(scsi_qla_host_t *vha) 1131 { 1132 struct qla_hw_data *ha = vha->hw; 1133 unsigned long flags; 1134 int res; 1135 1136 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1137 ql_dbg(ql_dbg_init, vha, 0x00ec, 1138 "tgt %p, fcport_count=%d\n", 1139 vha, vha->fcport_count); 1140 res = (vha->fcport_count == 0); 1141 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1142 1143 return res; 1144 } 1145 1146 /* 1147 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1148 * it has dependency on UNLOADING flag to stop device discovery 1149 */ 1150 static void 1151 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1152 { 1153 qla2x00_mark_all_devices_lost(vha, 0); 1154 1155 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ); 1156 } 1157 1158 /* 1159 * qla2x00_wait_for_hba_ready 1160 * Wait till the HBA is ready before doing driver unload 1161 * 1162 * Input: 1163 * ha - pointer to host adapter structure 1164 * 1165 * Note: 1166 * Does context switching-Release SPIN_LOCK 1167 * (if any) before calling this routine. 1168 * 1169 */ 1170 static void 1171 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1172 { 1173 struct qla_hw_data *ha = vha->hw; 1174 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1175 1176 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1177 ha->flags.mbox_busy) || 1178 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1179 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1180 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1181 break; 1182 msleep(1000); 1183 } 1184 } 1185 1186 int 1187 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1188 { 1189 int return_status; 1190 unsigned long wait_reset; 1191 struct qla_hw_data *ha = vha->hw; 1192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1193 1194 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1195 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1196 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1197 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1198 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1199 1200 msleep(1000); 1201 1202 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1203 ha->flags.chip_reset_done) 1204 break; 1205 } 1206 if (ha->flags.chip_reset_done) 1207 return_status = QLA_SUCCESS; 1208 else 1209 return_status = QLA_FUNCTION_FAILED; 1210 1211 return return_status; 1212 } 1213 1214 static void 1215 sp_get(struct srb *sp) 1216 { 1217 atomic_inc(&sp->ref_count); 1218 } 1219 1220 #define ISP_REG_DISCONNECT 0xffffffffU 1221 /************************************************************************** 1222 * qla2x00_isp_reg_stat 1223 * 1224 * Description: 1225 * Read the host status register of ISP before aborting the command. 1226 * 1227 * Input: 1228 * ha = pointer to host adapter structure. 1229 * 1230 * 1231 * Returns: 1232 * Either true or false. 1233 * 1234 * Note: Return true if there is register disconnect. 1235 **************************************************************************/ 1236 static inline 1237 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1238 { 1239 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1240 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1241 1242 if (IS_P3P_TYPE(ha)) 1243 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1244 else 1245 return ((RD_REG_DWORD(®->host_status)) == 1246 ISP_REG_DISCONNECT); 1247 } 1248 1249 /************************************************************************** 1250 * qla2xxx_eh_abort 1251 * 1252 * Description: 1253 * The abort function will abort the specified command. 1254 * 1255 * Input: 1256 * cmd = Linux SCSI command packet to be aborted. 1257 * 1258 * Returns: 1259 * Either SUCCESS or FAILED. 1260 * 1261 * Note: 1262 * Only return FAILED if command not returned by firmware. 1263 **************************************************************************/ 1264 static int 1265 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1266 { 1267 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1268 srb_t *sp; 1269 int ret; 1270 unsigned int id; 1271 uint64_t lun; 1272 unsigned long flags; 1273 int rval, wait = 0; 1274 struct qla_hw_data *ha = vha->hw; 1275 1276 if (qla2x00_isp_reg_stat(ha)) { 1277 ql_log(ql_log_info, vha, 0x8042, 1278 "PCI/Register disconnect, exiting.\n"); 1279 return FAILED; 1280 } 1281 if (!CMD_SP(cmd)) 1282 return SUCCESS; 1283 1284 ret = fc_block_scsi_eh(cmd); 1285 if (ret != 0) 1286 return ret; 1287 ret = SUCCESS; 1288 1289 id = cmd->device->id; 1290 lun = cmd->device->lun; 1291 1292 spin_lock_irqsave(&ha->hardware_lock, flags); 1293 sp = (srb_t *) CMD_SP(cmd); 1294 if (!sp) { 1295 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1296 return SUCCESS; 1297 } 1298 1299 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1300 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1301 vha->host_no, id, lun, sp, cmd, sp->handle); 1302 1303 /* Get a reference to the sp and drop the lock.*/ 1304 sp_get(sp); 1305 1306 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1307 rval = ha->isp_ops->abort_command(sp); 1308 if (rval) { 1309 if (rval == QLA_FUNCTION_PARAMETER_ERROR) 1310 ret = SUCCESS; 1311 else 1312 ret = FAILED; 1313 1314 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1315 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); 1316 } else { 1317 ql_dbg(ql_dbg_taskm, vha, 0x8004, 1318 "Abort command mbx success cmd=%p.\n", cmd); 1319 wait = 1; 1320 } 1321 1322 spin_lock_irqsave(&ha->hardware_lock, flags); 1323 sp->done(sp, 0); 1324 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1325 1326 /* Did the command return during mailbox execution? */ 1327 if (ret == FAILED && !CMD_SP(cmd)) 1328 ret = SUCCESS; 1329 1330 /* Wait for the command to be returned. */ 1331 if (wait) { 1332 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { 1333 ql_log(ql_log_warn, vha, 0x8006, 1334 "Abort handler timed out cmd=%p.\n", cmd); 1335 ret = FAILED; 1336 } 1337 } 1338 1339 ql_log(ql_log_info, vha, 0x801c, 1340 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", 1341 vha->host_no, id, lun, wait, ret); 1342 1343 return ret; 1344 } 1345 1346 int 1347 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1348 uint64_t l, enum nexus_wait_type type) 1349 { 1350 int cnt, match, status; 1351 unsigned long flags; 1352 struct qla_hw_data *ha = vha->hw; 1353 struct req_que *req; 1354 srb_t *sp; 1355 struct scsi_cmnd *cmd; 1356 1357 status = QLA_SUCCESS; 1358 1359 spin_lock_irqsave(&ha->hardware_lock, flags); 1360 req = vha->req; 1361 for (cnt = 1; status == QLA_SUCCESS && 1362 cnt < req->num_outstanding_cmds; cnt++) { 1363 sp = req->outstanding_cmds[cnt]; 1364 if (!sp) 1365 continue; 1366 if (sp->type != SRB_SCSI_CMD) 1367 continue; 1368 if (vha->vp_idx != sp->vha->vp_idx) 1369 continue; 1370 match = 0; 1371 cmd = GET_CMD_SP(sp); 1372 switch (type) { 1373 case WAIT_HOST: 1374 match = 1; 1375 break; 1376 case WAIT_TARGET: 1377 match = cmd->device->id == t; 1378 break; 1379 case WAIT_LUN: 1380 match = (cmd->device->id == t && 1381 cmd->device->lun == l); 1382 break; 1383 } 1384 if (!match) 1385 continue; 1386 1387 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1388 status = qla2x00_eh_wait_on_command(cmd); 1389 spin_lock_irqsave(&ha->hardware_lock, flags); 1390 } 1391 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1392 1393 return status; 1394 } 1395 1396 static char *reset_errors[] = { 1397 "HBA not online", 1398 "HBA not ready", 1399 "Task management failed", 1400 "Waiting for command completions", 1401 }; 1402 1403 static int 1404 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1405 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1406 { 1407 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1408 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1409 int err; 1410 1411 if (!fcport) { 1412 return FAILED; 1413 } 1414 1415 err = fc_block_scsi_eh(cmd); 1416 if (err != 0) 1417 return err; 1418 1419 ql_log(ql_log_info, vha, 0x8009, 1420 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1421 cmd->device->id, cmd->device->lun, cmd); 1422 1423 err = 0; 1424 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1425 ql_log(ql_log_warn, vha, 0x800a, 1426 "Wait for hba online failed for cmd=%p.\n", cmd); 1427 goto eh_reset_failed; 1428 } 1429 err = 2; 1430 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) 1431 != QLA_SUCCESS) { 1432 ql_log(ql_log_warn, vha, 0x800c, 1433 "do_reset failed for cmd=%p.\n", cmd); 1434 goto eh_reset_failed; 1435 } 1436 err = 3; 1437 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1438 cmd->device->lun, type) != QLA_SUCCESS) { 1439 ql_log(ql_log_warn, vha, 0x800d, 1440 "wait for pending cmds failed for cmd=%p.\n", cmd); 1441 goto eh_reset_failed; 1442 } 1443 1444 ql_log(ql_log_info, vha, 0x800e, 1445 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1446 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1447 1448 return SUCCESS; 1449 1450 eh_reset_failed: 1451 ql_log(ql_log_info, vha, 0x800f, 1452 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1453 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1454 cmd); 1455 return FAILED; 1456 } 1457 1458 static int 1459 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1460 { 1461 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1462 struct qla_hw_data *ha = vha->hw; 1463 1464 if (qla2x00_isp_reg_stat(ha)) { 1465 ql_log(ql_log_info, vha, 0x803e, 1466 "PCI/Register disconnect, exiting.\n"); 1467 return FAILED; 1468 } 1469 1470 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1471 ha->isp_ops->lun_reset); 1472 } 1473 1474 static int 1475 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1476 { 1477 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1478 struct qla_hw_data *ha = vha->hw; 1479 1480 if (qla2x00_isp_reg_stat(ha)) { 1481 ql_log(ql_log_info, vha, 0x803f, 1482 "PCI/Register disconnect, exiting.\n"); 1483 return FAILED; 1484 } 1485 1486 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1487 ha->isp_ops->target_reset); 1488 } 1489 1490 /************************************************************************** 1491 * qla2xxx_eh_bus_reset 1492 * 1493 * Description: 1494 * The bus reset function will reset the bus and abort any executing 1495 * commands. 1496 * 1497 * Input: 1498 * cmd = Linux SCSI command packet of the command that cause the 1499 * bus reset. 1500 * 1501 * Returns: 1502 * SUCCESS/FAILURE (defined as macro in scsi.h). 1503 * 1504 **************************************************************************/ 1505 static int 1506 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1507 { 1508 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1509 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1510 int ret = FAILED; 1511 unsigned int id; 1512 uint64_t lun; 1513 struct qla_hw_data *ha = vha->hw; 1514 1515 if (qla2x00_isp_reg_stat(ha)) { 1516 ql_log(ql_log_info, vha, 0x8040, 1517 "PCI/Register disconnect, exiting.\n"); 1518 return FAILED; 1519 } 1520 1521 id = cmd->device->id; 1522 lun = cmd->device->lun; 1523 1524 if (!fcport) { 1525 return ret; 1526 } 1527 1528 ret = fc_block_scsi_eh(cmd); 1529 if (ret != 0) 1530 return ret; 1531 ret = FAILED; 1532 1533 ql_log(ql_log_info, vha, 0x8012, 1534 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1535 1536 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1537 ql_log(ql_log_fatal, vha, 0x8013, 1538 "Wait for hba online failed board disabled.\n"); 1539 goto eh_bus_reset_done; 1540 } 1541 1542 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1543 ret = SUCCESS; 1544 1545 if (ret == FAILED) 1546 goto eh_bus_reset_done; 1547 1548 /* Flush outstanding commands. */ 1549 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1550 QLA_SUCCESS) { 1551 ql_log(ql_log_warn, vha, 0x8014, 1552 "Wait for pending commands failed.\n"); 1553 ret = FAILED; 1554 } 1555 1556 eh_bus_reset_done: 1557 ql_log(ql_log_warn, vha, 0x802b, 1558 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1559 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1560 1561 return ret; 1562 } 1563 1564 /************************************************************************** 1565 * qla2xxx_eh_host_reset 1566 * 1567 * Description: 1568 * The reset function will reset the Adapter. 1569 * 1570 * Input: 1571 * cmd = Linux SCSI command packet of the command that cause the 1572 * adapter reset. 1573 * 1574 * Returns: 1575 * Either SUCCESS or FAILED. 1576 * 1577 * Note: 1578 **************************************************************************/ 1579 static int 1580 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1581 { 1582 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1583 struct qla_hw_data *ha = vha->hw; 1584 int ret = FAILED; 1585 unsigned int id; 1586 uint64_t lun; 1587 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1588 1589 if (qla2x00_isp_reg_stat(ha)) { 1590 ql_log(ql_log_info, vha, 0x8041, 1591 "PCI/Register disconnect, exiting.\n"); 1592 schedule_work(&ha->board_disable); 1593 return SUCCESS; 1594 } 1595 1596 id = cmd->device->id; 1597 lun = cmd->device->lun; 1598 1599 ql_log(ql_log_info, vha, 0x8018, 1600 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1601 1602 /* 1603 * No point in issuing another reset if one is active. Also do not 1604 * attempt a reset if we are updating flash. 1605 */ 1606 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1607 goto eh_host_reset_lock; 1608 1609 if (vha != base_vha) { 1610 if (qla2x00_vp_abort_isp(vha)) 1611 goto eh_host_reset_lock; 1612 } else { 1613 if (IS_P3P_TYPE(vha->hw)) { 1614 if (!qla82xx_fcoe_ctx_reset(vha)) { 1615 /* Ctx reset success */ 1616 ret = SUCCESS; 1617 goto eh_host_reset_lock; 1618 } 1619 /* fall thru if ctx reset failed */ 1620 } 1621 if (ha->wq) 1622 flush_workqueue(ha->wq); 1623 1624 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1625 if (ha->isp_ops->abort_isp(base_vha)) { 1626 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1627 /* failed. schedule dpc to try */ 1628 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1629 1630 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1631 ql_log(ql_log_warn, vha, 0x802a, 1632 "wait for hba online failed.\n"); 1633 goto eh_host_reset_lock; 1634 } 1635 } 1636 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1637 } 1638 1639 /* Waiting for command to be returned to OS.*/ 1640 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1641 QLA_SUCCESS) 1642 ret = SUCCESS; 1643 1644 eh_host_reset_lock: 1645 ql_log(ql_log_info, vha, 0x8017, 1646 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1647 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1648 1649 return ret; 1650 } 1651 1652 /* 1653 * qla2x00_loop_reset 1654 * Issue loop reset. 1655 * 1656 * Input: 1657 * ha = adapter block pointer. 1658 * 1659 * Returns: 1660 * 0 = success 1661 */ 1662 int 1663 qla2x00_loop_reset(scsi_qla_host_t *vha) 1664 { 1665 int ret; 1666 struct fc_port *fcport; 1667 struct qla_hw_data *ha = vha->hw; 1668 1669 if (IS_QLAFX00(ha)) { 1670 return qlafx00_loop_reset(vha); 1671 } 1672 1673 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1674 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1675 if (fcport->port_type != FCT_TARGET) 1676 continue; 1677 1678 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1679 if (ret != QLA_SUCCESS) { 1680 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1681 "Bus Reset failed: Reset=%d " 1682 "d_id=%x.\n", ret, fcport->d_id.b24); 1683 } 1684 } 1685 } 1686 1687 1688 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1689 atomic_set(&vha->loop_state, LOOP_DOWN); 1690 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1691 qla2x00_mark_all_devices_lost(vha, 0); 1692 ret = qla2x00_full_login_lip(vha); 1693 if (ret != QLA_SUCCESS) { 1694 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1695 "full_login_lip=%d.\n", ret); 1696 } 1697 } 1698 1699 if (ha->flags.enable_lip_reset) { 1700 ret = qla2x00_lip_reset(vha); 1701 if (ret != QLA_SUCCESS) 1702 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1703 "lip_reset failed (%d).\n", ret); 1704 } 1705 1706 /* Issue marker command only when we are going to start the I/O */ 1707 vha->marker_needed = 1; 1708 1709 return QLA_SUCCESS; 1710 } 1711 1712 static void 1713 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1714 { 1715 int cnt, status; 1716 unsigned long flags; 1717 srb_t *sp; 1718 scsi_qla_host_t *vha = qp->vha; 1719 struct qla_hw_data *ha = vha->hw; 1720 struct req_que *req; 1721 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1722 struct qla_tgt_cmd *cmd; 1723 uint8_t trace = 0; 1724 1725 if (!ha->req_q_map) 1726 return; 1727 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1728 req = qp->req; 1729 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1730 sp = req->outstanding_cmds[cnt]; 1731 if (sp) { 1732 req->outstanding_cmds[cnt] = NULL; 1733 if (sp->cmd_type == TYPE_SRB) { 1734 if (sp->type == SRB_NVME_CMD || 1735 sp->type == SRB_NVME_LS) { 1736 sp_get(sp); 1737 spin_unlock_irqrestore(qp->qp_lock_ptr, 1738 flags); 1739 qla_nvme_abort(ha, sp, res); 1740 spin_lock_irqsave(qp->qp_lock_ptr, 1741 flags); 1742 } else if (GET_CMD_SP(sp) && 1743 !ha->flags.eeh_busy && 1744 (!test_bit(ABORT_ISP_ACTIVE, 1745 &vha->dpc_flags)) && 1746 (sp->type == SRB_SCSI_CMD)) { 1747 /* 1748 * Don't abort commands in 1749 * adapter during EEH 1750 * recovery as it's not 1751 * accessible/responding. 1752 * 1753 * Get a reference to the sp 1754 * and drop the lock. The 1755 * reference ensures this 1756 * sp->done() call and not the 1757 * call in qla2xxx_eh_abort() 1758 * ends the SCSI command (with 1759 * result 'res'). 1760 */ 1761 sp_get(sp); 1762 spin_unlock_irqrestore(qp->qp_lock_ptr, 1763 flags); 1764 status = qla2xxx_eh_abort( 1765 GET_CMD_SP(sp)); 1766 spin_lock_irqsave(qp->qp_lock_ptr, 1767 flags); 1768 /* 1769 * Get rid of extra reference 1770 * if immediate exit from 1771 * ql2xxx_eh_abort 1772 */ 1773 if (status == FAILED && 1774 (qla2x00_isp_reg_stat(ha))) 1775 atomic_dec( 1776 &sp->ref_count); 1777 } 1778 sp->done(sp, res); 1779 } else { 1780 if (!vha->hw->tgt.tgt_ops || !tgt || 1781 qla_ini_mode_enabled(vha)) { 1782 if (!trace) 1783 ql_dbg(ql_dbg_tgt_mgt, 1784 vha, 0xf003, 1785 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1786 vha->dpc_flags); 1787 continue; 1788 } 1789 cmd = (struct qla_tgt_cmd *)sp; 1790 qlt_abort_cmd_on_host_reset(cmd->vha, cmd); 1791 } 1792 } 1793 } 1794 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1795 } 1796 1797 void 1798 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1799 { 1800 int que; 1801 struct qla_hw_data *ha = vha->hw; 1802 1803 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1804 1805 for (que = 0; que < ha->max_qpairs; que++) { 1806 if (!ha->queue_pair_map[que]) 1807 continue; 1808 1809 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1810 } 1811 } 1812 1813 static int 1814 qla2xxx_slave_alloc(struct scsi_device *sdev) 1815 { 1816 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1817 1818 if (!rport || fc_remote_port_chkready(rport)) 1819 return -ENXIO; 1820 1821 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1822 1823 return 0; 1824 } 1825 1826 static int 1827 qla2xxx_slave_configure(struct scsi_device *sdev) 1828 { 1829 scsi_qla_host_t *vha = shost_priv(sdev->host); 1830 struct req_que *req = vha->req; 1831 1832 if (IS_T10_PI_CAPABLE(vha->hw)) 1833 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1834 1835 scsi_change_queue_depth(sdev, req->max_q_depth); 1836 return 0; 1837 } 1838 1839 static void 1840 qla2xxx_slave_destroy(struct scsi_device *sdev) 1841 { 1842 sdev->hostdata = NULL; 1843 } 1844 1845 /** 1846 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1847 * @ha: HA context 1848 * 1849 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1850 * supported addressing method. 1851 */ 1852 static void 1853 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1854 { 1855 /* Assume a 32bit DMA mask. */ 1856 ha->flags.enable_64bit_addressing = 0; 1857 1858 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1859 /* Any upper-dword bits set? */ 1860 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1861 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1862 /* Ok, a 64bit DMA mask is applicable. */ 1863 ha->flags.enable_64bit_addressing = 1; 1864 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1865 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1866 return; 1867 } 1868 } 1869 1870 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1871 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1872 } 1873 1874 static void 1875 qla2x00_enable_intrs(struct qla_hw_data *ha) 1876 { 1877 unsigned long flags = 0; 1878 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1879 1880 spin_lock_irqsave(&ha->hardware_lock, flags); 1881 ha->interrupts_on = 1; 1882 /* enable risc and host interrupts */ 1883 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1884 RD_REG_WORD(®->ictrl); 1885 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1886 1887 } 1888 1889 static void 1890 qla2x00_disable_intrs(struct qla_hw_data *ha) 1891 { 1892 unsigned long flags = 0; 1893 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1894 1895 spin_lock_irqsave(&ha->hardware_lock, flags); 1896 ha->interrupts_on = 0; 1897 /* disable risc and host interrupts */ 1898 WRT_REG_WORD(®->ictrl, 0); 1899 RD_REG_WORD(®->ictrl); 1900 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1901 } 1902 1903 static void 1904 qla24xx_enable_intrs(struct qla_hw_data *ha) 1905 { 1906 unsigned long flags = 0; 1907 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1908 1909 spin_lock_irqsave(&ha->hardware_lock, flags); 1910 ha->interrupts_on = 1; 1911 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1912 RD_REG_DWORD(®->ictrl); 1913 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1914 } 1915 1916 static void 1917 qla24xx_disable_intrs(struct qla_hw_data *ha) 1918 { 1919 unsigned long flags = 0; 1920 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1921 1922 if (IS_NOPOLLING_TYPE(ha)) 1923 return; 1924 spin_lock_irqsave(&ha->hardware_lock, flags); 1925 ha->interrupts_on = 0; 1926 WRT_REG_DWORD(®->ictrl, 0); 1927 RD_REG_DWORD(®->ictrl); 1928 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1929 } 1930 1931 static int 1932 qla2x00_iospace_config(struct qla_hw_data *ha) 1933 { 1934 resource_size_t pio; 1935 uint16_t msix; 1936 1937 if (pci_request_selected_regions(ha->pdev, ha->bars, 1938 QLA2XXX_DRIVER_NAME)) { 1939 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1940 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1941 pci_name(ha->pdev)); 1942 goto iospace_error_exit; 1943 } 1944 if (!(ha->bars & 1)) 1945 goto skip_pio; 1946 1947 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1948 pio = pci_resource_start(ha->pdev, 0); 1949 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1950 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1951 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1952 "Invalid pci I/O region size (%s).\n", 1953 pci_name(ha->pdev)); 1954 pio = 0; 1955 } 1956 } else { 1957 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1958 "Region #0 no a PIO resource (%s).\n", 1959 pci_name(ha->pdev)); 1960 pio = 0; 1961 } 1962 ha->pio_address = pio; 1963 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1964 "PIO address=%llu.\n", 1965 (unsigned long long)ha->pio_address); 1966 1967 skip_pio: 1968 /* Use MMIO operations for all accesses. */ 1969 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1970 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1971 "Region #1 not an MMIO resource (%s), aborting.\n", 1972 pci_name(ha->pdev)); 1973 goto iospace_error_exit; 1974 } 1975 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1976 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1977 "Invalid PCI mem region size (%s), aborting.\n", 1978 pci_name(ha->pdev)); 1979 goto iospace_error_exit; 1980 } 1981 1982 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1983 if (!ha->iobase) { 1984 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1985 "Cannot remap MMIO (%s), aborting.\n", 1986 pci_name(ha->pdev)); 1987 goto iospace_error_exit; 1988 } 1989 1990 /* Determine queue resources */ 1991 ha->max_req_queues = ha->max_rsp_queues = 1; 1992 ha->msix_count = QLA_BASE_VECTORS; 1993 if (!ql2xmqsupport || !ql2xnvmeenable || 1994 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1995 goto mqiobase_exit; 1996 1997 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1998 pci_resource_len(ha->pdev, 3)); 1999 if (ha->mqiobase) { 2000 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2001 "MQIO Base=%p.\n", ha->mqiobase); 2002 /* Read MSIX vector size of the board */ 2003 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2004 ha->msix_count = msix + 1; 2005 /* Max queues are bounded by available msix vectors */ 2006 /* MB interrupt uses 1 vector */ 2007 ha->max_req_queues = ha->msix_count - 1; 2008 ha->max_rsp_queues = ha->max_req_queues; 2009 /* Queue pairs is the max value minus the base queue pair */ 2010 ha->max_qpairs = ha->max_rsp_queues - 1; 2011 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2012 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2013 2014 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2015 "MSI-X vector count: %d.\n", ha->msix_count); 2016 } else 2017 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2018 "BAR 3 not enabled.\n"); 2019 2020 mqiobase_exit: 2021 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2022 "MSIX Count: %d.\n", ha->msix_count); 2023 return (0); 2024 2025 iospace_error_exit: 2026 return (-ENOMEM); 2027 } 2028 2029 2030 static int 2031 qla83xx_iospace_config(struct qla_hw_data *ha) 2032 { 2033 uint16_t msix; 2034 2035 if (pci_request_selected_regions(ha->pdev, ha->bars, 2036 QLA2XXX_DRIVER_NAME)) { 2037 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2038 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2039 pci_name(ha->pdev)); 2040 2041 goto iospace_error_exit; 2042 } 2043 2044 /* Use MMIO operations for all accesses. */ 2045 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2046 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2047 "Invalid pci I/O region size (%s).\n", 2048 pci_name(ha->pdev)); 2049 goto iospace_error_exit; 2050 } 2051 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2052 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2053 "Invalid PCI mem region size (%s), aborting\n", 2054 pci_name(ha->pdev)); 2055 goto iospace_error_exit; 2056 } 2057 2058 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2059 if (!ha->iobase) { 2060 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2061 "Cannot remap MMIO (%s), aborting.\n", 2062 pci_name(ha->pdev)); 2063 goto iospace_error_exit; 2064 } 2065 2066 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2067 /* 83XX 26XX always use MQ type access for queues 2068 * - mbar 2, a.k.a region 4 */ 2069 ha->max_req_queues = ha->max_rsp_queues = 1; 2070 ha->msix_count = QLA_BASE_VECTORS; 2071 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2072 pci_resource_len(ha->pdev, 4)); 2073 2074 if (!ha->mqiobase) { 2075 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2076 "BAR2/region4 not enabled\n"); 2077 goto mqiobase_exit; 2078 } 2079 2080 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2081 pci_resource_len(ha->pdev, 2)); 2082 if (ha->msixbase) { 2083 /* Read MSIX vector size of the board */ 2084 pci_read_config_word(ha->pdev, 2085 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2086 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2087 /* 2088 * By default, driver uses at least two msix vectors 2089 * (default & rspq) 2090 */ 2091 if (ql2xmqsupport || ql2xnvmeenable) { 2092 /* MB interrupt uses 1 vector */ 2093 ha->max_req_queues = ha->msix_count - 1; 2094 2095 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2096 if (QLA_TGT_MODE_ENABLED()) 2097 ha->max_req_queues--; 2098 2099 ha->max_rsp_queues = ha->max_req_queues; 2100 2101 /* Queue pairs is the max value minus 2102 * the base queue pair */ 2103 ha->max_qpairs = ha->max_req_queues - 1; 2104 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2105 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2106 } 2107 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2108 "MSI-X vector count: %d.\n", ha->msix_count); 2109 } else 2110 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2111 "BAR 1 not enabled.\n"); 2112 2113 mqiobase_exit: 2114 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2115 "MSIX Count: %d.\n", ha->msix_count); 2116 return 0; 2117 2118 iospace_error_exit: 2119 return -ENOMEM; 2120 } 2121 2122 static struct isp_operations qla2100_isp_ops = { 2123 .pci_config = qla2100_pci_config, 2124 .reset_chip = qla2x00_reset_chip, 2125 .chip_diag = qla2x00_chip_diag, 2126 .config_rings = qla2x00_config_rings, 2127 .reset_adapter = qla2x00_reset_adapter, 2128 .nvram_config = qla2x00_nvram_config, 2129 .update_fw_options = qla2x00_update_fw_options, 2130 .load_risc = qla2x00_load_risc, 2131 .pci_info_str = qla2x00_pci_info_str, 2132 .fw_version_str = qla2x00_fw_version_str, 2133 .intr_handler = qla2100_intr_handler, 2134 .enable_intrs = qla2x00_enable_intrs, 2135 .disable_intrs = qla2x00_disable_intrs, 2136 .abort_command = qla2x00_abort_command, 2137 .target_reset = qla2x00_abort_target, 2138 .lun_reset = qla2x00_lun_reset, 2139 .fabric_login = qla2x00_login_fabric, 2140 .fabric_logout = qla2x00_fabric_logout, 2141 .calc_req_entries = qla2x00_calc_iocbs_32, 2142 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2143 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2144 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2145 .read_nvram = qla2x00_read_nvram_data, 2146 .write_nvram = qla2x00_write_nvram_data, 2147 .fw_dump = qla2100_fw_dump, 2148 .beacon_on = NULL, 2149 .beacon_off = NULL, 2150 .beacon_blink = NULL, 2151 .read_optrom = qla2x00_read_optrom_data, 2152 .write_optrom = qla2x00_write_optrom_data, 2153 .get_flash_version = qla2x00_get_flash_version, 2154 .start_scsi = qla2x00_start_scsi, 2155 .start_scsi_mq = NULL, 2156 .abort_isp = qla2x00_abort_isp, 2157 .iospace_config = qla2x00_iospace_config, 2158 .initialize_adapter = qla2x00_initialize_adapter, 2159 }; 2160 2161 static struct isp_operations qla2300_isp_ops = { 2162 .pci_config = qla2300_pci_config, 2163 .reset_chip = qla2x00_reset_chip, 2164 .chip_diag = qla2x00_chip_diag, 2165 .config_rings = qla2x00_config_rings, 2166 .reset_adapter = qla2x00_reset_adapter, 2167 .nvram_config = qla2x00_nvram_config, 2168 .update_fw_options = qla2x00_update_fw_options, 2169 .load_risc = qla2x00_load_risc, 2170 .pci_info_str = qla2x00_pci_info_str, 2171 .fw_version_str = qla2x00_fw_version_str, 2172 .intr_handler = qla2300_intr_handler, 2173 .enable_intrs = qla2x00_enable_intrs, 2174 .disable_intrs = qla2x00_disable_intrs, 2175 .abort_command = qla2x00_abort_command, 2176 .target_reset = qla2x00_abort_target, 2177 .lun_reset = qla2x00_lun_reset, 2178 .fabric_login = qla2x00_login_fabric, 2179 .fabric_logout = qla2x00_fabric_logout, 2180 .calc_req_entries = qla2x00_calc_iocbs_32, 2181 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2182 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2183 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2184 .read_nvram = qla2x00_read_nvram_data, 2185 .write_nvram = qla2x00_write_nvram_data, 2186 .fw_dump = qla2300_fw_dump, 2187 .beacon_on = qla2x00_beacon_on, 2188 .beacon_off = qla2x00_beacon_off, 2189 .beacon_blink = qla2x00_beacon_blink, 2190 .read_optrom = qla2x00_read_optrom_data, 2191 .write_optrom = qla2x00_write_optrom_data, 2192 .get_flash_version = qla2x00_get_flash_version, 2193 .start_scsi = qla2x00_start_scsi, 2194 .start_scsi_mq = NULL, 2195 .abort_isp = qla2x00_abort_isp, 2196 .iospace_config = qla2x00_iospace_config, 2197 .initialize_adapter = qla2x00_initialize_adapter, 2198 }; 2199 2200 static struct isp_operations qla24xx_isp_ops = { 2201 .pci_config = qla24xx_pci_config, 2202 .reset_chip = qla24xx_reset_chip, 2203 .chip_diag = qla24xx_chip_diag, 2204 .config_rings = qla24xx_config_rings, 2205 .reset_adapter = qla24xx_reset_adapter, 2206 .nvram_config = qla24xx_nvram_config, 2207 .update_fw_options = qla24xx_update_fw_options, 2208 .load_risc = qla24xx_load_risc, 2209 .pci_info_str = qla24xx_pci_info_str, 2210 .fw_version_str = qla24xx_fw_version_str, 2211 .intr_handler = qla24xx_intr_handler, 2212 .enable_intrs = qla24xx_enable_intrs, 2213 .disable_intrs = qla24xx_disable_intrs, 2214 .abort_command = qla24xx_abort_command, 2215 .target_reset = qla24xx_abort_target, 2216 .lun_reset = qla24xx_lun_reset, 2217 .fabric_login = qla24xx_login_fabric, 2218 .fabric_logout = qla24xx_fabric_logout, 2219 .calc_req_entries = NULL, 2220 .build_iocbs = NULL, 2221 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2222 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2223 .read_nvram = qla24xx_read_nvram_data, 2224 .write_nvram = qla24xx_write_nvram_data, 2225 .fw_dump = qla24xx_fw_dump, 2226 .beacon_on = qla24xx_beacon_on, 2227 .beacon_off = qla24xx_beacon_off, 2228 .beacon_blink = qla24xx_beacon_blink, 2229 .read_optrom = qla24xx_read_optrom_data, 2230 .write_optrom = qla24xx_write_optrom_data, 2231 .get_flash_version = qla24xx_get_flash_version, 2232 .start_scsi = qla24xx_start_scsi, 2233 .start_scsi_mq = NULL, 2234 .abort_isp = qla2x00_abort_isp, 2235 .iospace_config = qla2x00_iospace_config, 2236 .initialize_adapter = qla2x00_initialize_adapter, 2237 }; 2238 2239 static struct isp_operations qla25xx_isp_ops = { 2240 .pci_config = qla25xx_pci_config, 2241 .reset_chip = qla24xx_reset_chip, 2242 .chip_diag = qla24xx_chip_diag, 2243 .config_rings = qla24xx_config_rings, 2244 .reset_adapter = qla24xx_reset_adapter, 2245 .nvram_config = qla24xx_nvram_config, 2246 .update_fw_options = qla24xx_update_fw_options, 2247 .load_risc = qla24xx_load_risc, 2248 .pci_info_str = qla24xx_pci_info_str, 2249 .fw_version_str = qla24xx_fw_version_str, 2250 .intr_handler = qla24xx_intr_handler, 2251 .enable_intrs = qla24xx_enable_intrs, 2252 .disable_intrs = qla24xx_disable_intrs, 2253 .abort_command = qla24xx_abort_command, 2254 .target_reset = qla24xx_abort_target, 2255 .lun_reset = qla24xx_lun_reset, 2256 .fabric_login = qla24xx_login_fabric, 2257 .fabric_logout = qla24xx_fabric_logout, 2258 .calc_req_entries = NULL, 2259 .build_iocbs = NULL, 2260 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2261 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2262 .read_nvram = qla25xx_read_nvram_data, 2263 .write_nvram = qla25xx_write_nvram_data, 2264 .fw_dump = qla25xx_fw_dump, 2265 .beacon_on = qla24xx_beacon_on, 2266 .beacon_off = qla24xx_beacon_off, 2267 .beacon_blink = qla24xx_beacon_blink, 2268 .read_optrom = qla25xx_read_optrom_data, 2269 .write_optrom = qla24xx_write_optrom_data, 2270 .get_flash_version = qla24xx_get_flash_version, 2271 .start_scsi = qla24xx_dif_start_scsi, 2272 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2273 .abort_isp = qla2x00_abort_isp, 2274 .iospace_config = qla2x00_iospace_config, 2275 .initialize_adapter = qla2x00_initialize_adapter, 2276 }; 2277 2278 static struct isp_operations qla81xx_isp_ops = { 2279 .pci_config = qla25xx_pci_config, 2280 .reset_chip = qla24xx_reset_chip, 2281 .chip_diag = qla24xx_chip_diag, 2282 .config_rings = qla24xx_config_rings, 2283 .reset_adapter = qla24xx_reset_adapter, 2284 .nvram_config = qla81xx_nvram_config, 2285 .update_fw_options = qla81xx_update_fw_options, 2286 .load_risc = qla81xx_load_risc, 2287 .pci_info_str = qla24xx_pci_info_str, 2288 .fw_version_str = qla24xx_fw_version_str, 2289 .intr_handler = qla24xx_intr_handler, 2290 .enable_intrs = qla24xx_enable_intrs, 2291 .disable_intrs = qla24xx_disable_intrs, 2292 .abort_command = qla24xx_abort_command, 2293 .target_reset = qla24xx_abort_target, 2294 .lun_reset = qla24xx_lun_reset, 2295 .fabric_login = qla24xx_login_fabric, 2296 .fabric_logout = qla24xx_fabric_logout, 2297 .calc_req_entries = NULL, 2298 .build_iocbs = NULL, 2299 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2300 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2301 .read_nvram = NULL, 2302 .write_nvram = NULL, 2303 .fw_dump = qla81xx_fw_dump, 2304 .beacon_on = qla24xx_beacon_on, 2305 .beacon_off = qla24xx_beacon_off, 2306 .beacon_blink = qla83xx_beacon_blink, 2307 .read_optrom = qla25xx_read_optrom_data, 2308 .write_optrom = qla24xx_write_optrom_data, 2309 .get_flash_version = qla24xx_get_flash_version, 2310 .start_scsi = qla24xx_dif_start_scsi, 2311 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2312 .abort_isp = qla2x00_abort_isp, 2313 .iospace_config = qla2x00_iospace_config, 2314 .initialize_adapter = qla2x00_initialize_adapter, 2315 }; 2316 2317 static struct isp_operations qla82xx_isp_ops = { 2318 .pci_config = qla82xx_pci_config, 2319 .reset_chip = qla82xx_reset_chip, 2320 .chip_diag = qla24xx_chip_diag, 2321 .config_rings = qla82xx_config_rings, 2322 .reset_adapter = qla24xx_reset_adapter, 2323 .nvram_config = qla81xx_nvram_config, 2324 .update_fw_options = qla24xx_update_fw_options, 2325 .load_risc = qla82xx_load_risc, 2326 .pci_info_str = qla24xx_pci_info_str, 2327 .fw_version_str = qla24xx_fw_version_str, 2328 .intr_handler = qla82xx_intr_handler, 2329 .enable_intrs = qla82xx_enable_intrs, 2330 .disable_intrs = qla82xx_disable_intrs, 2331 .abort_command = qla24xx_abort_command, 2332 .target_reset = qla24xx_abort_target, 2333 .lun_reset = qla24xx_lun_reset, 2334 .fabric_login = qla24xx_login_fabric, 2335 .fabric_logout = qla24xx_fabric_logout, 2336 .calc_req_entries = NULL, 2337 .build_iocbs = NULL, 2338 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2339 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2340 .read_nvram = qla24xx_read_nvram_data, 2341 .write_nvram = qla24xx_write_nvram_data, 2342 .fw_dump = qla82xx_fw_dump, 2343 .beacon_on = qla82xx_beacon_on, 2344 .beacon_off = qla82xx_beacon_off, 2345 .beacon_blink = NULL, 2346 .read_optrom = qla82xx_read_optrom_data, 2347 .write_optrom = qla82xx_write_optrom_data, 2348 .get_flash_version = qla82xx_get_flash_version, 2349 .start_scsi = qla82xx_start_scsi, 2350 .start_scsi_mq = NULL, 2351 .abort_isp = qla82xx_abort_isp, 2352 .iospace_config = qla82xx_iospace_config, 2353 .initialize_adapter = qla2x00_initialize_adapter, 2354 }; 2355 2356 static struct isp_operations qla8044_isp_ops = { 2357 .pci_config = qla82xx_pci_config, 2358 .reset_chip = qla82xx_reset_chip, 2359 .chip_diag = qla24xx_chip_diag, 2360 .config_rings = qla82xx_config_rings, 2361 .reset_adapter = qla24xx_reset_adapter, 2362 .nvram_config = qla81xx_nvram_config, 2363 .update_fw_options = qla24xx_update_fw_options, 2364 .load_risc = qla82xx_load_risc, 2365 .pci_info_str = qla24xx_pci_info_str, 2366 .fw_version_str = qla24xx_fw_version_str, 2367 .intr_handler = qla8044_intr_handler, 2368 .enable_intrs = qla82xx_enable_intrs, 2369 .disable_intrs = qla82xx_disable_intrs, 2370 .abort_command = qla24xx_abort_command, 2371 .target_reset = qla24xx_abort_target, 2372 .lun_reset = qla24xx_lun_reset, 2373 .fabric_login = qla24xx_login_fabric, 2374 .fabric_logout = qla24xx_fabric_logout, 2375 .calc_req_entries = NULL, 2376 .build_iocbs = NULL, 2377 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2378 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2379 .read_nvram = NULL, 2380 .write_nvram = NULL, 2381 .fw_dump = qla8044_fw_dump, 2382 .beacon_on = qla82xx_beacon_on, 2383 .beacon_off = qla82xx_beacon_off, 2384 .beacon_blink = NULL, 2385 .read_optrom = qla8044_read_optrom_data, 2386 .write_optrom = qla8044_write_optrom_data, 2387 .get_flash_version = qla82xx_get_flash_version, 2388 .start_scsi = qla82xx_start_scsi, 2389 .start_scsi_mq = NULL, 2390 .abort_isp = qla8044_abort_isp, 2391 .iospace_config = qla82xx_iospace_config, 2392 .initialize_adapter = qla2x00_initialize_adapter, 2393 }; 2394 2395 static struct isp_operations qla83xx_isp_ops = { 2396 .pci_config = qla25xx_pci_config, 2397 .reset_chip = qla24xx_reset_chip, 2398 .chip_diag = qla24xx_chip_diag, 2399 .config_rings = qla24xx_config_rings, 2400 .reset_adapter = qla24xx_reset_adapter, 2401 .nvram_config = qla81xx_nvram_config, 2402 .update_fw_options = qla81xx_update_fw_options, 2403 .load_risc = qla81xx_load_risc, 2404 .pci_info_str = qla24xx_pci_info_str, 2405 .fw_version_str = qla24xx_fw_version_str, 2406 .intr_handler = qla24xx_intr_handler, 2407 .enable_intrs = qla24xx_enable_intrs, 2408 .disable_intrs = qla24xx_disable_intrs, 2409 .abort_command = qla24xx_abort_command, 2410 .target_reset = qla24xx_abort_target, 2411 .lun_reset = qla24xx_lun_reset, 2412 .fabric_login = qla24xx_login_fabric, 2413 .fabric_logout = qla24xx_fabric_logout, 2414 .calc_req_entries = NULL, 2415 .build_iocbs = NULL, 2416 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2417 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2418 .read_nvram = NULL, 2419 .write_nvram = NULL, 2420 .fw_dump = qla83xx_fw_dump, 2421 .beacon_on = qla24xx_beacon_on, 2422 .beacon_off = qla24xx_beacon_off, 2423 .beacon_blink = qla83xx_beacon_blink, 2424 .read_optrom = qla25xx_read_optrom_data, 2425 .write_optrom = qla24xx_write_optrom_data, 2426 .get_flash_version = qla24xx_get_flash_version, 2427 .start_scsi = qla24xx_dif_start_scsi, 2428 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2429 .abort_isp = qla2x00_abort_isp, 2430 .iospace_config = qla83xx_iospace_config, 2431 .initialize_adapter = qla2x00_initialize_adapter, 2432 }; 2433 2434 static struct isp_operations qlafx00_isp_ops = { 2435 .pci_config = qlafx00_pci_config, 2436 .reset_chip = qlafx00_soft_reset, 2437 .chip_diag = qlafx00_chip_diag, 2438 .config_rings = qlafx00_config_rings, 2439 .reset_adapter = qlafx00_soft_reset, 2440 .nvram_config = NULL, 2441 .update_fw_options = NULL, 2442 .load_risc = NULL, 2443 .pci_info_str = qlafx00_pci_info_str, 2444 .fw_version_str = qlafx00_fw_version_str, 2445 .intr_handler = qlafx00_intr_handler, 2446 .enable_intrs = qlafx00_enable_intrs, 2447 .disable_intrs = qlafx00_disable_intrs, 2448 .abort_command = qla24xx_async_abort_command, 2449 .target_reset = qlafx00_abort_target, 2450 .lun_reset = qlafx00_lun_reset, 2451 .fabric_login = NULL, 2452 .fabric_logout = NULL, 2453 .calc_req_entries = NULL, 2454 .build_iocbs = NULL, 2455 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2456 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2457 .read_nvram = qla24xx_read_nvram_data, 2458 .write_nvram = qla24xx_write_nvram_data, 2459 .fw_dump = NULL, 2460 .beacon_on = qla24xx_beacon_on, 2461 .beacon_off = qla24xx_beacon_off, 2462 .beacon_blink = NULL, 2463 .read_optrom = qla24xx_read_optrom_data, 2464 .write_optrom = qla24xx_write_optrom_data, 2465 .get_flash_version = qla24xx_get_flash_version, 2466 .start_scsi = qlafx00_start_scsi, 2467 .start_scsi_mq = NULL, 2468 .abort_isp = qlafx00_abort_isp, 2469 .iospace_config = qlafx00_iospace_config, 2470 .initialize_adapter = qlafx00_initialize_adapter, 2471 }; 2472 2473 static struct isp_operations qla27xx_isp_ops = { 2474 .pci_config = qla25xx_pci_config, 2475 .reset_chip = qla24xx_reset_chip, 2476 .chip_diag = qla24xx_chip_diag, 2477 .config_rings = qla24xx_config_rings, 2478 .reset_adapter = qla24xx_reset_adapter, 2479 .nvram_config = qla81xx_nvram_config, 2480 .update_fw_options = qla81xx_update_fw_options, 2481 .load_risc = qla81xx_load_risc, 2482 .pci_info_str = qla24xx_pci_info_str, 2483 .fw_version_str = qla24xx_fw_version_str, 2484 .intr_handler = qla24xx_intr_handler, 2485 .enable_intrs = qla24xx_enable_intrs, 2486 .disable_intrs = qla24xx_disable_intrs, 2487 .abort_command = qla24xx_abort_command, 2488 .target_reset = qla24xx_abort_target, 2489 .lun_reset = qla24xx_lun_reset, 2490 .fabric_login = qla24xx_login_fabric, 2491 .fabric_logout = qla24xx_fabric_logout, 2492 .calc_req_entries = NULL, 2493 .build_iocbs = NULL, 2494 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2495 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2496 .read_nvram = NULL, 2497 .write_nvram = NULL, 2498 .fw_dump = qla27xx_fwdump, 2499 .beacon_on = qla24xx_beacon_on, 2500 .beacon_off = qla24xx_beacon_off, 2501 .beacon_blink = qla83xx_beacon_blink, 2502 .read_optrom = qla25xx_read_optrom_data, 2503 .write_optrom = qla24xx_write_optrom_data, 2504 .get_flash_version = qla24xx_get_flash_version, 2505 .start_scsi = qla24xx_dif_start_scsi, 2506 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2507 .abort_isp = qla2x00_abort_isp, 2508 .iospace_config = qla83xx_iospace_config, 2509 .initialize_adapter = qla2x00_initialize_adapter, 2510 }; 2511 2512 static inline void 2513 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2514 { 2515 ha->device_type = DT_EXTENDED_IDS; 2516 switch (ha->pdev->device) { 2517 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2518 ha->isp_type |= DT_ISP2100; 2519 ha->device_type &= ~DT_EXTENDED_IDS; 2520 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2521 break; 2522 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2523 ha->isp_type |= DT_ISP2200; 2524 ha->device_type &= ~DT_EXTENDED_IDS; 2525 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2526 break; 2527 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2528 ha->isp_type |= DT_ISP2300; 2529 ha->device_type |= DT_ZIO_SUPPORTED; 2530 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2531 break; 2532 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2533 ha->isp_type |= DT_ISP2312; 2534 ha->device_type |= DT_ZIO_SUPPORTED; 2535 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2536 break; 2537 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2538 ha->isp_type |= DT_ISP2322; 2539 ha->device_type |= DT_ZIO_SUPPORTED; 2540 if (ha->pdev->subsystem_vendor == 0x1028 && 2541 ha->pdev->subsystem_device == 0x0170) 2542 ha->device_type |= DT_OEM_001; 2543 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2544 break; 2545 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2546 ha->isp_type |= DT_ISP6312; 2547 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2548 break; 2549 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2550 ha->isp_type |= DT_ISP6322; 2551 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2552 break; 2553 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2554 ha->isp_type |= DT_ISP2422; 2555 ha->device_type |= DT_ZIO_SUPPORTED; 2556 ha->device_type |= DT_FWI2; 2557 ha->device_type |= DT_IIDMA; 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2559 break; 2560 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2561 ha->isp_type |= DT_ISP2432; 2562 ha->device_type |= DT_ZIO_SUPPORTED; 2563 ha->device_type |= DT_FWI2; 2564 ha->device_type |= DT_IIDMA; 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2566 break; 2567 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2568 ha->isp_type |= DT_ISP8432; 2569 ha->device_type |= DT_ZIO_SUPPORTED; 2570 ha->device_type |= DT_FWI2; 2571 ha->device_type |= DT_IIDMA; 2572 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2573 break; 2574 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2575 ha->isp_type |= DT_ISP5422; 2576 ha->device_type |= DT_FWI2; 2577 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2578 break; 2579 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2580 ha->isp_type |= DT_ISP5432; 2581 ha->device_type |= DT_FWI2; 2582 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2583 break; 2584 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2585 ha->isp_type |= DT_ISP2532; 2586 ha->device_type |= DT_ZIO_SUPPORTED; 2587 ha->device_type |= DT_FWI2; 2588 ha->device_type |= DT_IIDMA; 2589 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2590 break; 2591 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2592 ha->isp_type |= DT_ISP8001; 2593 ha->device_type |= DT_ZIO_SUPPORTED; 2594 ha->device_type |= DT_FWI2; 2595 ha->device_type |= DT_IIDMA; 2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2597 break; 2598 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2599 ha->isp_type |= DT_ISP8021; 2600 ha->device_type |= DT_ZIO_SUPPORTED; 2601 ha->device_type |= DT_FWI2; 2602 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2603 /* Initialize 82XX ISP flags */ 2604 qla82xx_init_flags(ha); 2605 break; 2606 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2607 ha->isp_type |= DT_ISP8044; 2608 ha->device_type |= DT_ZIO_SUPPORTED; 2609 ha->device_type |= DT_FWI2; 2610 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2611 /* Initialize 82XX ISP flags */ 2612 qla82xx_init_flags(ha); 2613 break; 2614 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2615 ha->isp_type |= DT_ISP2031; 2616 ha->device_type |= DT_ZIO_SUPPORTED; 2617 ha->device_type |= DT_FWI2; 2618 ha->device_type |= DT_IIDMA; 2619 ha->device_type |= DT_T10_PI; 2620 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2621 break; 2622 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2623 ha->isp_type |= DT_ISP8031; 2624 ha->device_type |= DT_ZIO_SUPPORTED; 2625 ha->device_type |= DT_FWI2; 2626 ha->device_type |= DT_IIDMA; 2627 ha->device_type |= DT_T10_PI; 2628 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2629 break; 2630 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2631 ha->isp_type |= DT_ISPFX00; 2632 break; 2633 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2634 ha->isp_type |= DT_ISP2071; 2635 ha->device_type |= DT_ZIO_SUPPORTED; 2636 ha->device_type |= DT_FWI2; 2637 ha->device_type |= DT_IIDMA; 2638 ha->device_type |= DT_T10_PI; 2639 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2640 break; 2641 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2642 ha->isp_type |= DT_ISP2271; 2643 ha->device_type |= DT_ZIO_SUPPORTED; 2644 ha->device_type |= DT_FWI2; 2645 ha->device_type |= DT_IIDMA; 2646 ha->device_type |= DT_T10_PI; 2647 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2648 break; 2649 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2650 ha->isp_type |= DT_ISP2261; 2651 ha->device_type |= DT_ZIO_SUPPORTED; 2652 ha->device_type |= DT_FWI2; 2653 ha->device_type |= DT_IIDMA; 2654 ha->device_type |= DT_T10_PI; 2655 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2656 break; 2657 } 2658 2659 if (IS_QLA82XX(ha)) 2660 ha->port_no = ha->portnum & 1; 2661 else { 2662 /* Get adapter physical port no from interrupt pin register. */ 2663 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2664 if (IS_QLA27XX(ha)) 2665 ha->port_no--; 2666 else 2667 ha->port_no = !(ha->port_no & 1); 2668 } 2669 2670 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2671 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2672 ha->device_type, ha->port_no, ha->fw_srisc_address); 2673 } 2674 2675 static void 2676 qla2xxx_scan_start(struct Scsi_Host *shost) 2677 { 2678 scsi_qla_host_t *vha = shost_priv(shost); 2679 2680 if (vha->hw->flags.running_gold_fw) 2681 return; 2682 2683 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2684 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2685 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2686 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2687 } 2688 2689 static int 2690 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2691 { 2692 scsi_qla_host_t *vha = shost_priv(shost); 2693 2694 if (test_bit(UNLOADING, &vha->dpc_flags)) 2695 return 1; 2696 if (!vha->host) 2697 return 1; 2698 if (time > vha->hw->loop_reset_delay * HZ) 2699 return 1; 2700 2701 return atomic_read(&vha->loop_state) == LOOP_READY; 2702 } 2703 2704 static void qla2x00_iocb_work_fn(struct work_struct *work) 2705 { 2706 struct scsi_qla_host *vha = container_of(work, 2707 struct scsi_qla_host, iocb_work); 2708 struct qla_hw_data *ha = vha->hw; 2709 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2710 int i = 20; 2711 unsigned long flags; 2712 2713 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2714 return; 2715 2716 while (!list_empty(&vha->work_list) && i > 0) { 2717 qla2x00_do_work(vha); 2718 i--; 2719 } 2720 2721 spin_lock_irqsave(&vha->work_lock, flags); 2722 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2723 spin_unlock_irqrestore(&vha->work_lock, flags); 2724 } 2725 2726 /* 2727 * PCI driver interface 2728 */ 2729 static int 2730 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2731 { 2732 int ret = -ENODEV; 2733 struct Scsi_Host *host; 2734 scsi_qla_host_t *base_vha = NULL; 2735 struct qla_hw_data *ha; 2736 char pci_info[30]; 2737 char fw_str[30], wq_name[30]; 2738 struct scsi_host_template *sht; 2739 int bars, mem_only = 0; 2740 uint16_t req_length = 0, rsp_length = 0; 2741 struct req_que *req = NULL; 2742 struct rsp_que *rsp = NULL; 2743 int i; 2744 2745 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2746 sht = &qla2xxx_driver_template; 2747 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2748 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2749 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2750 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2751 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2752 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2753 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2754 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2755 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2756 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2757 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) { 2762 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2763 mem_only = 1; 2764 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2765 "Mem only adapter.\n"); 2766 } 2767 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2768 "Bars=%d.\n", bars); 2769 2770 if (mem_only) { 2771 if (pci_enable_device_mem(pdev)) 2772 return ret; 2773 } else { 2774 if (pci_enable_device(pdev)) 2775 return ret; 2776 } 2777 2778 /* This may fail but that's ok */ 2779 pci_enable_pcie_error_reporting(pdev); 2780 2781 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2782 if (!ha) { 2783 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2784 "Unable to allocate memory for ha.\n"); 2785 goto disable_device; 2786 } 2787 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2788 "Memory allocated for ha=%p.\n", ha); 2789 ha->pdev = pdev; 2790 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2791 spin_lock_init(&ha->tgt.q_full_lock); 2792 spin_lock_init(&ha->tgt.sess_lock); 2793 spin_lock_init(&ha->tgt.atio_lock); 2794 2795 atomic_set(&ha->nvme_active_aen_cnt, 0); 2796 2797 /* Clear our data area */ 2798 ha->bars = bars; 2799 ha->mem_only = mem_only; 2800 spin_lock_init(&ha->hardware_lock); 2801 spin_lock_init(&ha->vport_slock); 2802 mutex_init(&ha->selflogin_lock); 2803 mutex_init(&ha->optrom_mutex); 2804 2805 /* Set ISP-type information. */ 2806 qla2x00_set_isp_flags(ha); 2807 2808 /* Set EEH reset type to fundamental if required by hba */ 2809 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2810 IS_QLA83XX(ha) || IS_QLA27XX(ha)) 2811 pdev->needs_freset = 1; 2812 2813 ha->prev_topology = 0; 2814 ha->init_cb_size = sizeof(init_cb_t); 2815 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2816 ha->optrom_size = OPTROM_SIZE_2300; 2817 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2818 2819 /* Assign ISP specific operations. */ 2820 if (IS_QLA2100(ha)) { 2821 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2822 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2823 req_length = REQUEST_ENTRY_CNT_2100; 2824 rsp_length = RESPONSE_ENTRY_CNT_2100; 2825 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2826 ha->gid_list_info_size = 4; 2827 ha->flash_conf_off = ~0; 2828 ha->flash_data_off = ~0; 2829 ha->nvram_conf_off = ~0; 2830 ha->nvram_data_off = ~0; 2831 ha->isp_ops = &qla2100_isp_ops; 2832 } else if (IS_QLA2200(ha)) { 2833 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2834 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2835 req_length = REQUEST_ENTRY_CNT_2200; 2836 rsp_length = RESPONSE_ENTRY_CNT_2100; 2837 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2838 ha->gid_list_info_size = 4; 2839 ha->flash_conf_off = ~0; 2840 ha->flash_data_off = ~0; 2841 ha->nvram_conf_off = ~0; 2842 ha->nvram_data_off = ~0; 2843 ha->isp_ops = &qla2100_isp_ops; 2844 } else if (IS_QLA23XX(ha)) { 2845 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2846 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2847 req_length = REQUEST_ENTRY_CNT_2200; 2848 rsp_length = RESPONSE_ENTRY_CNT_2300; 2849 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2850 ha->gid_list_info_size = 6; 2851 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2852 ha->optrom_size = OPTROM_SIZE_2322; 2853 ha->flash_conf_off = ~0; 2854 ha->flash_data_off = ~0; 2855 ha->nvram_conf_off = ~0; 2856 ha->nvram_data_off = ~0; 2857 ha->isp_ops = &qla2300_isp_ops; 2858 } else if (IS_QLA24XX_TYPE(ha)) { 2859 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2860 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2861 req_length = REQUEST_ENTRY_CNT_24XX; 2862 rsp_length = RESPONSE_ENTRY_CNT_2300; 2863 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2864 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2865 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2866 ha->gid_list_info_size = 8; 2867 ha->optrom_size = OPTROM_SIZE_24XX; 2868 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2869 ha->isp_ops = &qla24xx_isp_ops; 2870 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2871 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2872 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2873 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2874 } else if (IS_QLA25XX(ha)) { 2875 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2876 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2877 req_length = REQUEST_ENTRY_CNT_24XX; 2878 rsp_length = RESPONSE_ENTRY_CNT_2300; 2879 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2880 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2881 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2882 ha->gid_list_info_size = 8; 2883 ha->optrom_size = OPTROM_SIZE_25XX; 2884 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2885 ha->isp_ops = &qla25xx_isp_ops; 2886 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2887 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2888 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2889 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2890 } else if (IS_QLA81XX(ha)) { 2891 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2892 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2893 req_length = REQUEST_ENTRY_CNT_24XX; 2894 rsp_length = RESPONSE_ENTRY_CNT_2300; 2895 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2896 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2897 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2898 ha->gid_list_info_size = 8; 2899 ha->optrom_size = OPTROM_SIZE_81XX; 2900 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2901 ha->isp_ops = &qla81xx_isp_ops; 2902 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2903 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2904 ha->nvram_conf_off = ~0; 2905 ha->nvram_data_off = ~0; 2906 } else if (IS_QLA82XX(ha)) { 2907 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2908 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2909 req_length = REQUEST_ENTRY_CNT_82XX; 2910 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2911 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2912 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2913 ha->gid_list_info_size = 8; 2914 ha->optrom_size = OPTROM_SIZE_82XX; 2915 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2916 ha->isp_ops = &qla82xx_isp_ops; 2917 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2918 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2919 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2920 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2921 } else if (IS_QLA8044(ha)) { 2922 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2923 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2924 req_length = REQUEST_ENTRY_CNT_82XX; 2925 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2926 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2927 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2928 ha->gid_list_info_size = 8; 2929 ha->optrom_size = OPTROM_SIZE_83XX; 2930 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2931 ha->isp_ops = &qla8044_isp_ops; 2932 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2933 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2934 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2935 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2936 } else if (IS_QLA83XX(ha)) { 2937 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2938 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2939 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2940 req_length = REQUEST_ENTRY_CNT_83XX; 2941 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2942 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2943 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2944 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2945 ha->gid_list_info_size = 8; 2946 ha->optrom_size = OPTROM_SIZE_83XX; 2947 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2948 ha->isp_ops = &qla83xx_isp_ops; 2949 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2950 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2951 ha->nvram_conf_off = ~0; 2952 ha->nvram_data_off = ~0; 2953 } else if (IS_QLAFX00(ha)) { 2954 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2955 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2956 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2957 req_length = REQUEST_ENTRY_CNT_FX00; 2958 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2959 ha->isp_ops = &qlafx00_isp_ops; 2960 ha->port_down_retry_count = 30; /* default value */ 2961 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2962 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2963 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2964 ha->mr.fw_hbt_en = 1; 2965 ha->mr.host_info_resend = false; 2966 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2967 } else if (IS_QLA27XX(ha)) { 2968 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2969 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2970 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2971 req_length = REQUEST_ENTRY_CNT_83XX; 2972 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2973 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2974 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2975 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2976 ha->gid_list_info_size = 8; 2977 ha->optrom_size = OPTROM_SIZE_83XX; 2978 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2979 ha->isp_ops = &qla27xx_isp_ops; 2980 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2981 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2982 ha->nvram_conf_off = ~0; 2983 ha->nvram_data_off = ~0; 2984 } 2985 2986 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 2987 "mbx_count=%d, req_length=%d, " 2988 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 2989 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 2990 "max_fibre_devices=%d.\n", 2991 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 2992 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 2993 ha->nvram_npiv_size, ha->max_fibre_devices); 2994 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 2995 "isp_ops=%p, flash_conf_off=%d, " 2996 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 2997 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 2998 ha->nvram_conf_off, ha->nvram_data_off); 2999 3000 /* Configure PCI I/O space */ 3001 ret = ha->isp_ops->iospace_config(ha); 3002 if (ret) 3003 goto iospace_config_failed; 3004 3005 ql_log_pci(ql_log_info, pdev, 0x001d, 3006 "Found an ISP%04X irq %d iobase 0x%p.\n", 3007 pdev->device, pdev->irq, ha->iobase); 3008 mutex_init(&ha->vport_lock); 3009 mutex_init(&ha->mq_lock); 3010 init_completion(&ha->mbx_cmd_comp); 3011 complete(&ha->mbx_cmd_comp); 3012 init_completion(&ha->mbx_intr_comp); 3013 init_completion(&ha->dcbx_comp); 3014 init_completion(&ha->lb_portup_comp); 3015 3016 set_bit(0, (unsigned long *) ha->vp_idx_map); 3017 3018 qla2x00_config_dma_addressing(ha); 3019 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3020 "64 Bit addressing is %s.\n", 3021 ha->flags.enable_64bit_addressing ? "enable" : 3022 "disable"); 3023 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3024 if (ret) { 3025 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3026 "Failed to allocate memory for adapter, aborting.\n"); 3027 3028 goto probe_hw_failed; 3029 } 3030 3031 req->max_q_depth = MAX_Q_DEPTH; 3032 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3033 req->max_q_depth = ql2xmaxqdepth; 3034 3035 3036 base_vha = qla2x00_create_host(sht, ha); 3037 if (!base_vha) { 3038 ret = -ENOMEM; 3039 goto probe_hw_failed; 3040 } 3041 3042 pci_set_drvdata(pdev, base_vha); 3043 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3044 3045 host = base_vha->host; 3046 base_vha->req = req; 3047 if (IS_QLA2XXX_MIDTYPE(ha)) 3048 base_vha->mgmt_svr_loop_id = NPH_MGMT_SERVER; 3049 else 3050 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3051 base_vha->vp_idx; 3052 3053 /* Setup fcport template structure. */ 3054 ha->mr.fcport.vha = base_vha; 3055 ha->mr.fcport.port_type = FCT_UNKNOWN; 3056 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3057 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3058 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3059 ha->mr.fcport.scan_state = 1; 3060 3061 /* Set the SG table size based on ISP type */ 3062 if (!IS_FWI2_CAPABLE(ha)) { 3063 if (IS_QLA2100(ha)) 3064 host->sg_tablesize = 32; 3065 } else { 3066 if (!IS_QLA82XX(ha)) 3067 host->sg_tablesize = QLA_SG_ALL; 3068 } 3069 host->max_id = ha->max_fibre_devices; 3070 host->cmd_per_lun = 3; 3071 host->unique_id = host->host_no; 3072 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3073 host->max_cmd_len = 32; 3074 else 3075 host->max_cmd_len = MAX_CMDSZ; 3076 host->max_channel = MAX_BUSES - 1; 3077 /* Older HBAs support only 16-bit LUNs */ 3078 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3079 ql2xmaxlun > 0xffff) 3080 host->max_lun = 0xffff; 3081 else 3082 host->max_lun = ql2xmaxlun; 3083 host->transportt = qla2xxx_transport_template; 3084 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3085 3086 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3087 "max_id=%d this_id=%d " 3088 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3089 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3090 host->this_id, host->cmd_per_lun, host->unique_id, 3091 host->max_cmd_len, host->max_channel, host->max_lun, 3092 host->transportt, sht->vendor_id); 3093 3094 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3095 3096 /* Set up the irqs */ 3097 ret = qla2x00_request_irqs(ha, rsp); 3098 if (ret) 3099 goto probe_failed; 3100 3101 /* Alloc arrays of request and response ring ptrs */ 3102 ret = qla2x00_alloc_queues(ha, req, rsp); 3103 if (ret) { 3104 ql_log(ql_log_fatal, base_vha, 0x003d, 3105 "Failed to allocate memory for queue pointers..." 3106 "aborting.\n"); 3107 goto probe_failed; 3108 } 3109 3110 if (ha->mqenable && shost_use_blk_mq(host)) { 3111 /* number of hardware queues supported by blk/scsi-mq*/ 3112 host->nr_hw_queues = ha->max_qpairs; 3113 3114 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3115 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3116 } else { 3117 if (ql2xnvmeenable) { 3118 host->nr_hw_queues = ha->max_qpairs; 3119 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3120 "FC-NVMe support is enabled, HW queues=%d\n", 3121 host->nr_hw_queues); 3122 } else { 3123 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3124 "blk/scsi-mq disabled.\n"); 3125 } 3126 } 3127 3128 qlt_probe_one_stage1(base_vha, ha); 3129 3130 pci_save_state(pdev); 3131 3132 /* Assign back pointers */ 3133 rsp->req = req; 3134 req->rsp = rsp; 3135 3136 if (IS_QLAFX00(ha)) { 3137 ha->rsp_q_map[0] = rsp; 3138 ha->req_q_map[0] = req; 3139 set_bit(0, ha->req_qid_map); 3140 set_bit(0, ha->rsp_qid_map); 3141 } 3142 3143 /* FWI2-capable only. */ 3144 req->req_q_in = &ha->iobase->isp24.req_q_in; 3145 req->req_q_out = &ha->iobase->isp24.req_q_out; 3146 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3147 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3148 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 3149 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3150 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3151 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3152 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3153 } 3154 3155 if (IS_QLAFX00(ha)) { 3156 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3157 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3158 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3159 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3160 } 3161 3162 if (IS_P3P_TYPE(ha)) { 3163 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3164 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3165 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3166 } 3167 3168 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3169 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3170 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3171 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3172 "req->req_q_in=%p req->req_q_out=%p " 3173 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3174 req->req_q_in, req->req_q_out, 3175 rsp->rsp_q_in, rsp->rsp_q_out); 3176 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3177 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3178 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3179 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3180 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3181 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3182 3183 if (ha->isp_ops->initialize_adapter(base_vha)) { 3184 ql_log(ql_log_fatal, base_vha, 0x00d6, 3185 "Failed to initialize adapter - Adapter flags %x.\n", 3186 base_vha->device_flags); 3187 3188 if (IS_QLA82XX(ha)) { 3189 qla82xx_idc_lock(ha); 3190 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3191 QLA8XXX_DEV_FAILED); 3192 qla82xx_idc_unlock(ha); 3193 ql_log(ql_log_fatal, base_vha, 0x00d7, 3194 "HW State: FAILED.\n"); 3195 } else if (IS_QLA8044(ha)) { 3196 qla8044_idc_lock(ha); 3197 qla8044_wr_direct(base_vha, 3198 QLA8044_CRB_DEV_STATE_INDEX, 3199 QLA8XXX_DEV_FAILED); 3200 qla8044_idc_unlock(ha); 3201 ql_log(ql_log_fatal, base_vha, 0x0150, 3202 "HW State: FAILED.\n"); 3203 } 3204 3205 ret = -ENODEV; 3206 goto probe_failed; 3207 } 3208 3209 if (IS_QLAFX00(ha)) 3210 host->can_queue = QLAFX00_MAX_CANQUEUE; 3211 else 3212 host->can_queue = req->num_outstanding_cmds - 10; 3213 3214 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3215 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3216 host->can_queue, base_vha->req, 3217 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3218 3219 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3220 3221 if (ha->mqenable) { 3222 bool mq = false; 3223 bool startit = false; 3224 3225 if (QLA_TGT_MODE_ENABLED()) { 3226 mq = true; 3227 startit = false; 3228 } 3229 3230 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) && 3231 shost_use_blk_mq(host)) { 3232 mq = true; 3233 startit = true; 3234 } 3235 3236 if (mq) { 3237 /* Create start of day qpairs for Block MQ */ 3238 for (i = 0; i < ha->max_qpairs; i++) 3239 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3240 } 3241 } 3242 3243 if (ha->flags.running_gold_fw) 3244 goto skip_dpc; 3245 3246 /* 3247 * Startup the kernel thread for this host adapter 3248 */ 3249 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3250 "%s_dpc", base_vha->host_str); 3251 if (IS_ERR(ha->dpc_thread)) { 3252 ql_log(ql_log_fatal, base_vha, 0x00ed, 3253 "Failed to start DPC thread.\n"); 3254 ret = PTR_ERR(ha->dpc_thread); 3255 ha->dpc_thread = NULL; 3256 goto probe_failed; 3257 } 3258 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3259 "DPC thread started successfully.\n"); 3260 3261 /* 3262 * If we're not coming up in initiator mode, we might sit for 3263 * a while without waking up the dpc thread, which leads to a 3264 * stuck process warning. So just kick the dpc once here and 3265 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3266 */ 3267 qla2xxx_wake_dpc(base_vha); 3268 3269 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3270 3271 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3272 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3273 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3274 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3275 3276 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3277 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3278 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3279 INIT_WORK(&ha->idc_state_handler, 3280 qla83xx_idc_state_handler_work); 3281 INIT_WORK(&ha->nic_core_unrecoverable, 3282 qla83xx_nic_core_unrecoverable_work); 3283 } 3284 3285 skip_dpc: 3286 list_add_tail(&base_vha->list, &ha->vp_list); 3287 base_vha->host->irq = ha->pdev->irq; 3288 3289 /* Initialized the timer */ 3290 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3291 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3292 "Started qla2x00_timer with " 3293 "interval=%d.\n", WATCH_INTERVAL); 3294 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3295 "Detected hba at address=%p.\n", 3296 ha); 3297 3298 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3299 if (ha->fw_attributes & BIT_4) { 3300 int prot = 0, guard; 3301 base_vha->flags.difdix_supported = 1; 3302 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3303 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3304 if (ql2xenabledif == 1) 3305 prot = SHOST_DIX_TYPE0_PROTECTION; 3306 scsi_host_set_prot(host, 3307 prot | SHOST_DIF_TYPE1_PROTECTION 3308 | SHOST_DIF_TYPE2_PROTECTION 3309 | SHOST_DIF_TYPE3_PROTECTION 3310 | SHOST_DIX_TYPE1_PROTECTION 3311 | SHOST_DIX_TYPE2_PROTECTION 3312 | SHOST_DIX_TYPE3_PROTECTION); 3313 3314 guard = SHOST_DIX_GUARD_CRC; 3315 3316 if (IS_PI_IPGUARD_CAPABLE(ha) && 3317 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3318 guard |= SHOST_DIX_GUARD_IP; 3319 3320 scsi_host_set_guard(host, guard); 3321 } else 3322 base_vha->flags.difdix_supported = 0; 3323 } 3324 3325 ha->isp_ops->enable_intrs(ha); 3326 3327 if (IS_QLAFX00(ha)) { 3328 ret = qlafx00_fx_disc(base_vha, 3329 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3330 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3331 QLA_SG_ALL : 128; 3332 } 3333 3334 ret = scsi_add_host(host, &pdev->dev); 3335 if (ret) 3336 goto probe_failed; 3337 3338 base_vha->flags.init_done = 1; 3339 base_vha->flags.online = 1; 3340 ha->prev_minidump_failed = 0; 3341 3342 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3343 "Init done and hba is online.\n"); 3344 3345 if (qla_ini_mode_enabled(base_vha) || 3346 qla_dual_mode_enabled(base_vha)) 3347 scsi_scan_host(host); 3348 else 3349 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3350 "skipping scsi_scan_host() for non-initiator port\n"); 3351 3352 qla2x00_alloc_sysfs_attr(base_vha); 3353 3354 if (IS_QLAFX00(ha)) { 3355 ret = qlafx00_fx_disc(base_vha, 3356 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3357 3358 /* Register system information */ 3359 ret = qlafx00_fx_disc(base_vha, 3360 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3361 } 3362 3363 qla2x00_init_host_attr(base_vha); 3364 3365 qla2x00_dfs_setup(base_vha); 3366 3367 ql_log(ql_log_info, base_vha, 0x00fb, 3368 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3369 ql_log(ql_log_info, base_vha, 0x00fc, 3370 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3371 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3372 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3373 base_vha->host_no, 3374 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3375 3376 qlt_add_target(ha, base_vha); 3377 3378 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3379 3380 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3381 return -ENODEV; 3382 3383 if (ha->flags.detected_lr_sfp) { 3384 ql_log(ql_log_info, base_vha, 0xffff, 3385 "Reset chip to pick up LR SFP setting\n"); 3386 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3387 qla2xxx_wake_dpc(base_vha); 3388 } 3389 3390 return 0; 3391 3392 probe_failed: 3393 if (base_vha->timer_active) 3394 qla2x00_stop_timer(base_vha); 3395 base_vha->flags.online = 0; 3396 if (ha->dpc_thread) { 3397 struct task_struct *t = ha->dpc_thread; 3398 3399 ha->dpc_thread = NULL; 3400 kthread_stop(t); 3401 } 3402 3403 qla2x00_free_device(base_vha); 3404 scsi_host_put(base_vha->host); 3405 /* 3406 * Need to NULL out local req/rsp after 3407 * qla2x00_free_device => qla2x00_free_queues frees 3408 * what these are pointing to. Or else we'll 3409 * fall over below in qla2x00_free_req/rsp_que. 3410 */ 3411 req = NULL; 3412 rsp = NULL; 3413 3414 probe_hw_failed: 3415 qla2x00_mem_free(ha); 3416 qla2x00_free_req_que(ha, req); 3417 qla2x00_free_rsp_que(ha, rsp); 3418 qla2x00_clear_drv_active(ha); 3419 3420 iospace_config_failed: 3421 if (IS_P3P_TYPE(ha)) { 3422 if (!ha->nx_pcibase) 3423 iounmap((device_reg_t *)ha->nx_pcibase); 3424 if (!ql2xdbwr) 3425 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3426 } else { 3427 if (ha->iobase) 3428 iounmap(ha->iobase); 3429 if (ha->cregbase) 3430 iounmap(ha->cregbase); 3431 } 3432 pci_release_selected_regions(ha->pdev, ha->bars); 3433 kfree(ha); 3434 3435 disable_device: 3436 pci_disable_device(pdev); 3437 return ret; 3438 } 3439 3440 static void 3441 qla2x00_shutdown(struct pci_dev *pdev) 3442 { 3443 scsi_qla_host_t *vha; 3444 struct qla_hw_data *ha; 3445 3446 vha = pci_get_drvdata(pdev); 3447 ha = vha->hw; 3448 3449 ql_log(ql_log_info, vha, 0xfffa, 3450 "Adapter shutdown\n"); 3451 3452 /* 3453 * Prevent future board_disable and wait 3454 * until any pending board_disable has completed. 3455 */ 3456 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3457 cancel_work_sync(&ha->board_disable); 3458 3459 if (!atomic_read(&pdev->enable_cnt)) 3460 return; 3461 3462 /* Notify ISPFX00 firmware */ 3463 if (IS_QLAFX00(ha)) 3464 qlafx00_driver_shutdown(vha, 20); 3465 3466 /* Turn-off FCE trace */ 3467 if (ha->flags.fce_enabled) { 3468 qla2x00_disable_fce_trace(vha, NULL, NULL); 3469 ha->flags.fce_enabled = 0; 3470 } 3471 3472 /* Turn-off EFT trace */ 3473 if (ha->eft) 3474 qla2x00_disable_eft_trace(vha); 3475 3476 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3477 if (ha->flags.fw_started) 3478 qla2x00_abort_isp_cleanup(vha); 3479 } else { 3480 /* Stop currently executing firmware. */ 3481 qla2x00_try_to_stop_firmware(vha); 3482 } 3483 3484 /* Turn adapter off line */ 3485 vha->flags.online = 0; 3486 3487 /* turn-off interrupts on the card */ 3488 if (ha->interrupts_on) { 3489 vha->flags.init_done = 0; 3490 ha->isp_ops->disable_intrs(ha); 3491 } 3492 3493 qla2x00_free_irqs(vha); 3494 3495 qla2x00_free_fw_dump(ha); 3496 3497 pci_disable_device(pdev); 3498 ql_log(ql_log_info, vha, 0xfffe, 3499 "Adapter shutdown successfully.\n"); 3500 } 3501 3502 /* Deletes all the virtual ports for a given ha */ 3503 static void 3504 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3505 { 3506 scsi_qla_host_t *vha; 3507 unsigned long flags; 3508 3509 mutex_lock(&ha->vport_lock); 3510 while (ha->cur_vport_count) { 3511 spin_lock_irqsave(&ha->vport_slock, flags); 3512 3513 BUG_ON(base_vha->list.next == &ha->vp_list); 3514 /* This assumes first entry in ha->vp_list is always base vha */ 3515 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3516 scsi_host_get(vha->host); 3517 3518 spin_unlock_irqrestore(&ha->vport_slock, flags); 3519 mutex_unlock(&ha->vport_lock); 3520 3521 fc_vport_terminate(vha->fc_vport); 3522 scsi_host_put(vha->host); 3523 3524 mutex_lock(&ha->vport_lock); 3525 } 3526 mutex_unlock(&ha->vport_lock); 3527 } 3528 3529 /* Stops all deferred work threads */ 3530 static void 3531 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3532 { 3533 /* Cancel all work and destroy DPC workqueues */ 3534 if (ha->dpc_lp_wq) { 3535 cancel_work_sync(&ha->idc_aen); 3536 destroy_workqueue(ha->dpc_lp_wq); 3537 ha->dpc_lp_wq = NULL; 3538 } 3539 3540 if (ha->dpc_hp_wq) { 3541 cancel_work_sync(&ha->nic_core_reset); 3542 cancel_work_sync(&ha->idc_state_handler); 3543 cancel_work_sync(&ha->nic_core_unrecoverable); 3544 destroy_workqueue(ha->dpc_hp_wq); 3545 ha->dpc_hp_wq = NULL; 3546 } 3547 3548 /* Kill the kernel thread for this host */ 3549 if (ha->dpc_thread) { 3550 struct task_struct *t = ha->dpc_thread; 3551 3552 /* 3553 * qla2xxx_wake_dpc checks for ->dpc_thread 3554 * so we need to zero it out. 3555 */ 3556 ha->dpc_thread = NULL; 3557 kthread_stop(t); 3558 } 3559 } 3560 3561 static void 3562 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3563 { 3564 if (IS_QLA82XX(ha)) { 3565 3566 iounmap((device_reg_t *)ha->nx_pcibase); 3567 if (!ql2xdbwr) 3568 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3569 } else { 3570 if (ha->iobase) 3571 iounmap(ha->iobase); 3572 3573 if (ha->cregbase) 3574 iounmap(ha->cregbase); 3575 3576 if (ha->mqiobase) 3577 iounmap(ha->mqiobase); 3578 3579 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) 3580 iounmap(ha->msixbase); 3581 } 3582 } 3583 3584 static void 3585 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3586 { 3587 if (IS_QLA8044(ha)) { 3588 qla8044_idc_lock(ha); 3589 qla8044_clear_drv_active(ha); 3590 qla8044_idc_unlock(ha); 3591 } else if (IS_QLA82XX(ha)) { 3592 qla82xx_idc_lock(ha); 3593 qla82xx_clear_drv_active(ha); 3594 qla82xx_idc_unlock(ha); 3595 } 3596 } 3597 3598 static void 3599 qla2x00_remove_one(struct pci_dev *pdev) 3600 { 3601 scsi_qla_host_t *base_vha; 3602 struct qla_hw_data *ha; 3603 3604 base_vha = pci_get_drvdata(pdev); 3605 ha = base_vha->hw; 3606 3607 /* Indicate device removal to prevent future board_disable and wait 3608 * until any pending board_disable has completed. */ 3609 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3610 cancel_work_sync(&ha->board_disable); 3611 3612 /* 3613 * If the PCI device is disabled then there was a PCI-disconnect and 3614 * qla2x00_disable_board_on_pci_error has taken care of most of the 3615 * resources. 3616 */ 3617 if (!atomic_read(&pdev->enable_cnt)) { 3618 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3619 base_vha->gnl.l, base_vha->gnl.ldma); 3620 3621 scsi_host_put(base_vha->host); 3622 kfree(ha); 3623 pci_set_drvdata(pdev, NULL); 3624 return; 3625 } 3626 qla2x00_wait_for_hba_ready(base_vha); 3627 3628 qla2x00_wait_for_sess_deletion(base_vha); 3629 3630 /* 3631 * if UNLOAD flag is already set, then continue unload, 3632 * where it was set first. 3633 */ 3634 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3635 return; 3636 3637 set_bit(UNLOADING, &base_vha->dpc_flags); 3638 3639 qla_nvme_delete(base_vha); 3640 3641 dma_free_coherent(&ha->pdev->dev, 3642 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3643 3644 vfree(base_vha->scan.l); 3645 3646 if (IS_QLAFX00(ha)) 3647 qlafx00_driver_shutdown(base_vha, 20); 3648 3649 qla2x00_delete_all_vps(ha, base_vha); 3650 3651 if (IS_QLA8031(ha)) { 3652 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3653 "Clearing fcoe driver presence.\n"); 3654 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3655 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3656 "Error while clearing DRV-Presence.\n"); 3657 } 3658 3659 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 3660 3661 qla2x00_dfs_remove(base_vha); 3662 3663 qla84xx_put_chip(base_vha); 3664 3665 /* Disable timer */ 3666 if (base_vha->timer_active) 3667 qla2x00_stop_timer(base_vha); 3668 3669 base_vha->flags.online = 0; 3670 3671 /* free DMA memory */ 3672 if (ha->exlogin_buf) 3673 qla2x00_free_exlogin_buffer(ha); 3674 3675 /* free DMA memory */ 3676 if (ha->exchoffld_buf) 3677 qla2x00_free_exchoffld_buffer(ha); 3678 3679 qla2x00_destroy_deferred_work(ha); 3680 3681 qlt_remove_target(ha, base_vha); 3682 3683 qla2x00_free_sysfs_attr(base_vha, true); 3684 3685 fc_remove_host(base_vha->host); 3686 qlt_remove_target_resources(ha); 3687 3688 scsi_remove_host(base_vha->host); 3689 3690 qla2x00_free_device(base_vha); 3691 3692 qla2x00_clear_drv_active(ha); 3693 3694 scsi_host_put(base_vha->host); 3695 3696 qla2x00_unmap_iobases(ha); 3697 3698 pci_release_selected_regions(ha->pdev, ha->bars); 3699 kfree(ha); 3700 3701 pci_disable_pcie_error_reporting(pdev); 3702 3703 pci_disable_device(pdev); 3704 } 3705 3706 static void 3707 qla2x00_free_device(scsi_qla_host_t *vha) 3708 { 3709 struct qla_hw_data *ha = vha->hw; 3710 3711 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3712 3713 /* Disable timer */ 3714 if (vha->timer_active) 3715 qla2x00_stop_timer(vha); 3716 3717 qla25xx_delete_queues(vha); 3718 3719 if (ha->flags.fce_enabled) 3720 qla2x00_disable_fce_trace(vha, NULL, NULL); 3721 3722 if (ha->eft) 3723 qla2x00_disable_eft_trace(vha); 3724 3725 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 3726 if (ha->flags.fw_started) 3727 qla2x00_abort_isp_cleanup(vha); 3728 } else { 3729 if (ha->flags.fw_started) { 3730 /* Stop currently executing firmware. */ 3731 qla2x00_try_to_stop_firmware(vha); 3732 ha->flags.fw_started = 0; 3733 } 3734 } 3735 3736 vha->flags.online = 0; 3737 3738 /* turn-off interrupts on the card */ 3739 if (ha->interrupts_on) { 3740 vha->flags.init_done = 0; 3741 ha->isp_ops->disable_intrs(ha); 3742 } 3743 3744 qla2x00_free_fcports(vha); 3745 3746 qla2x00_free_irqs(vha); 3747 3748 /* Flush the work queue and remove it */ 3749 if (ha->wq) { 3750 flush_workqueue(ha->wq); 3751 destroy_workqueue(ha->wq); 3752 ha->wq = NULL; 3753 } 3754 3755 3756 qla2x00_mem_free(ha); 3757 3758 qla82xx_md_free(vha); 3759 3760 qla2x00_free_queues(ha); 3761 } 3762 3763 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3764 { 3765 fc_port_t *fcport, *tfcport; 3766 3767 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { 3768 list_del(&fcport->list); 3769 qla2x00_clear_loop_id(fcport); 3770 kfree(fcport); 3771 } 3772 } 3773 3774 static inline void 3775 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3776 int defer) 3777 { 3778 struct fc_rport *rport; 3779 scsi_qla_host_t *base_vha; 3780 unsigned long flags; 3781 3782 if (!fcport->rport) 3783 return; 3784 3785 rport = fcport->rport; 3786 if (defer) { 3787 base_vha = pci_get_drvdata(vha->hw->pdev); 3788 spin_lock_irqsave(vha->host->host_lock, flags); 3789 fcport->drport = rport; 3790 spin_unlock_irqrestore(vha->host->host_lock, flags); 3791 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3792 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3793 qla2xxx_wake_dpc(base_vha); 3794 } else { 3795 int now; 3796 if (rport) { 3797 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3798 "%s %8phN. rport %p roles %x\n", 3799 __func__, fcport->port_name, rport, 3800 rport->roles); 3801 fc_remote_port_delete(rport); 3802 } 3803 qlt_do_generation_tick(vha, &now); 3804 } 3805 } 3806 3807 /* 3808 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3809 * 3810 * Input: ha = adapter block pointer. fcport = port structure pointer. 3811 * 3812 * Return: None. 3813 * 3814 * Context: 3815 */ 3816 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3817 int do_login, int defer) 3818 { 3819 if (IS_QLAFX00(vha->hw)) { 3820 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3821 qla2x00_schedule_rport_del(vha, fcport, defer); 3822 return; 3823 } 3824 3825 if (atomic_read(&fcport->state) == FCS_ONLINE && 3826 vha->vp_idx == fcport->vha->vp_idx) { 3827 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3828 qla2x00_schedule_rport_del(vha, fcport, defer); 3829 } 3830 /* 3831 * We may need to retry the login, so don't change the state of the 3832 * port but do the retries. 3833 */ 3834 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3835 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3836 3837 if (!do_login) 3838 return; 3839 3840 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3841 3842 if (fcport->login_retry == 0) { 3843 fcport->login_retry = vha->hw->login_retry_count; 3844 3845 ql_dbg(ql_dbg_disc, vha, 0x20a3, 3846 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n", 3847 fcport->port_name, fcport->loop_id, fcport->login_retry); 3848 } 3849 } 3850 3851 /* 3852 * qla2x00_mark_all_devices_lost 3853 * Updates fcport state when device goes offline. 3854 * 3855 * Input: 3856 * ha = adapter block pointer. 3857 * fcport = port structure pointer. 3858 * 3859 * Return: 3860 * None. 3861 * 3862 * Context: 3863 */ 3864 void 3865 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3866 { 3867 fc_port_t *fcport; 3868 3869 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3870 "Mark all dev lost\n"); 3871 3872 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3873 fcport->scan_state = 0; 3874 qlt_schedule_sess_for_deletion(fcport); 3875 3876 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3877 continue; 3878 3879 /* 3880 * No point in marking the device as lost, if the device is 3881 * already DEAD. 3882 */ 3883 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3884 continue; 3885 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3886 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3887 if (defer) 3888 qla2x00_schedule_rport_del(vha, fcport, defer); 3889 else if (vha->vp_idx == fcport->vha->vp_idx) 3890 qla2x00_schedule_rport_del(vha, fcport, defer); 3891 } 3892 } 3893 } 3894 3895 /* 3896 * qla2x00_mem_alloc 3897 * Allocates adapter memory. 3898 * 3899 * Returns: 3900 * 0 = success. 3901 * !0 = failure. 3902 */ 3903 static int 3904 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3905 struct req_que **req, struct rsp_que **rsp) 3906 { 3907 char name[16]; 3908 3909 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3910 &ha->init_cb_dma, GFP_KERNEL); 3911 if (!ha->init_cb) 3912 goto fail; 3913 3914 if (qlt_mem_alloc(ha) < 0) 3915 goto fail_free_init_cb; 3916 3917 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3918 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3919 if (!ha->gid_list) 3920 goto fail_free_tgt_mem; 3921 3922 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3923 if (!ha->srb_mempool) 3924 goto fail_free_gid_list; 3925 3926 if (IS_P3P_TYPE(ha)) { 3927 /* Allocate cache for CT6 Ctx. */ 3928 if (!ctx_cachep) { 3929 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3930 sizeof(struct ct6_dsd), 0, 3931 SLAB_HWCACHE_ALIGN, NULL); 3932 if (!ctx_cachep) 3933 goto fail_free_srb_mempool; 3934 } 3935 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3936 ctx_cachep); 3937 if (!ha->ctx_mempool) 3938 goto fail_free_srb_mempool; 3939 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3940 "ctx_cachep=%p ctx_mempool=%p.\n", 3941 ctx_cachep, ha->ctx_mempool); 3942 } 3943 3944 /* Get memory for cached NVRAM */ 3945 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3946 if (!ha->nvram) 3947 goto fail_free_ctx_mempool; 3948 3949 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3950 ha->pdev->device); 3951 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3952 DMA_POOL_SIZE, 8, 0); 3953 if (!ha->s_dma_pool) 3954 goto fail_free_nvram; 3955 3956 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 3957 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 3958 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 3959 3960 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 3961 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3962 DSD_LIST_DMA_POOL_SIZE, 8, 0); 3963 if (!ha->dl_dma_pool) { 3964 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 3965 "Failed to allocate memory for dl_dma_pool.\n"); 3966 goto fail_s_dma_pool; 3967 } 3968 3969 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3970 FCP_CMND_DMA_POOL_SIZE, 8, 0); 3971 if (!ha->fcp_cmnd_dma_pool) { 3972 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 3973 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 3974 goto fail_dl_dma_pool; 3975 } 3976 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 3977 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", 3978 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); 3979 } 3980 3981 /* Allocate memory for SNS commands */ 3982 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3983 /* Get consistent memory allocated for SNS commands */ 3984 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 3985 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 3986 if (!ha->sns_cmd) 3987 goto fail_dma_pool; 3988 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 3989 "sns_cmd: %p.\n", ha->sns_cmd); 3990 } else { 3991 /* Get consistent memory allocated for MS IOCB */ 3992 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 3993 &ha->ms_iocb_dma); 3994 if (!ha->ms_iocb) 3995 goto fail_dma_pool; 3996 /* Get consistent memory allocated for CT SNS commands */ 3997 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 3998 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 3999 if (!ha->ct_sns) 4000 goto fail_free_ms_iocb; 4001 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4002 "ms_iocb=%p ct_sns=%p.\n", 4003 ha->ms_iocb, ha->ct_sns); 4004 } 4005 4006 /* Allocate memory for request ring */ 4007 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4008 if (!*req) { 4009 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4010 "Failed to allocate memory for req.\n"); 4011 goto fail_req; 4012 } 4013 (*req)->length = req_len; 4014 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4015 ((*req)->length + 1) * sizeof(request_t), 4016 &(*req)->dma, GFP_KERNEL); 4017 if (!(*req)->ring) { 4018 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4019 "Failed to allocate memory for req_ring.\n"); 4020 goto fail_req_ring; 4021 } 4022 /* Allocate memory for response ring */ 4023 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4024 if (!*rsp) { 4025 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4026 "Failed to allocate memory for rsp.\n"); 4027 goto fail_rsp; 4028 } 4029 (*rsp)->hw = ha; 4030 (*rsp)->length = rsp_len; 4031 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4032 ((*rsp)->length + 1) * sizeof(response_t), 4033 &(*rsp)->dma, GFP_KERNEL); 4034 if (!(*rsp)->ring) { 4035 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4036 "Failed to allocate memory for rsp_ring.\n"); 4037 goto fail_rsp_ring; 4038 } 4039 (*req)->rsp = *rsp; 4040 (*rsp)->req = *req; 4041 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4042 "req=%p req->length=%d req->ring=%p rsp=%p " 4043 "rsp->length=%d rsp->ring=%p.\n", 4044 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4045 (*rsp)->ring); 4046 /* Allocate memory for NVRAM data for vports */ 4047 if (ha->nvram_npiv_size) { 4048 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * 4049 ha->nvram_npiv_size, GFP_KERNEL); 4050 if (!ha->npiv_info) { 4051 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4052 "Failed to allocate memory for npiv_info.\n"); 4053 goto fail_npiv_info; 4054 } 4055 } else 4056 ha->npiv_info = NULL; 4057 4058 /* Get consistent memory allocated for EX-INIT-CB. */ 4059 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { 4060 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4061 &ha->ex_init_cb_dma); 4062 if (!ha->ex_init_cb) 4063 goto fail_ex_init_cb; 4064 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4065 "ex_init_cb=%p.\n", ha->ex_init_cb); 4066 } 4067 4068 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4069 4070 /* Get consistent memory allocated for Async Port-Database. */ 4071 if (!IS_FWI2_CAPABLE(ha)) { 4072 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4073 &ha->async_pd_dma); 4074 if (!ha->async_pd) 4075 goto fail_async_pd; 4076 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4077 "async_pd=%p.\n", ha->async_pd); 4078 } 4079 4080 INIT_LIST_HEAD(&ha->vp_list); 4081 4082 /* Allocate memory for our loop_id bitmap */ 4083 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), 4084 GFP_KERNEL); 4085 if (!ha->loop_id_map) 4086 goto fail_loop_id_map; 4087 else { 4088 qla2x00_set_reserved_loop_ids(ha); 4089 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4090 "loop_id_map=%p.\n", ha->loop_id_map); 4091 } 4092 4093 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4094 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4095 if (!ha->sfp_data) { 4096 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4097 "Unable to allocate memory for SFP read-data.\n"); 4098 goto fail_sfp_data; 4099 } 4100 4101 return 0; 4102 4103 fail_sfp_data: 4104 kfree(ha->loop_id_map); 4105 fail_loop_id_map: 4106 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4107 fail_async_pd: 4108 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4109 fail_ex_init_cb: 4110 kfree(ha->npiv_info); 4111 fail_npiv_info: 4112 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4113 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4114 (*rsp)->ring = NULL; 4115 (*rsp)->dma = 0; 4116 fail_rsp_ring: 4117 kfree(*rsp); 4118 *rsp = NULL; 4119 fail_rsp: 4120 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4121 sizeof(request_t), (*req)->ring, (*req)->dma); 4122 (*req)->ring = NULL; 4123 (*req)->dma = 0; 4124 fail_req_ring: 4125 kfree(*req); 4126 *req = NULL; 4127 fail_req: 4128 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4129 ha->ct_sns, ha->ct_sns_dma); 4130 ha->ct_sns = NULL; 4131 ha->ct_sns_dma = 0; 4132 fail_free_ms_iocb: 4133 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4134 ha->ms_iocb = NULL; 4135 ha->ms_iocb_dma = 0; 4136 4137 if (ha->sns_cmd) 4138 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4139 ha->sns_cmd, ha->sns_cmd_dma); 4140 fail_dma_pool: 4141 if (IS_QLA82XX(ha) || ql2xenabledif) { 4142 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4143 ha->fcp_cmnd_dma_pool = NULL; 4144 } 4145 fail_dl_dma_pool: 4146 if (IS_QLA82XX(ha) || ql2xenabledif) { 4147 dma_pool_destroy(ha->dl_dma_pool); 4148 ha->dl_dma_pool = NULL; 4149 } 4150 fail_s_dma_pool: 4151 dma_pool_destroy(ha->s_dma_pool); 4152 ha->s_dma_pool = NULL; 4153 fail_free_nvram: 4154 kfree(ha->nvram); 4155 ha->nvram = NULL; 4156 fail_free_ctx_mempool: 4157 if (ha->ctx_mempool) 4158 mempool_destroy(ha->ctx_mempool); 4159 ha->ctx_mempool = NULL; 4160 fail_free_srb_mempool: 4161 if (ha->srb_mempool) 4162 mempool_destroy(ha->srb_mempool); 4163 ha->srb_mempool = NULL; 4164 fail_free_gid_list: 4165 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4166 ha->gid_list, 4167 ha->gid_list_dma); 4168 ha->gid_list = NULL; 4169 ha->gid_list_dma = 0; 4170 fail_free_tgt_mem: 4171 qlt_mem_free(ha); 4172 fail_free_init_cb: 4173 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4174 ha->init_cb_dma); 4175 ha->init_cb = NULL; 4176 ha->init_cb_dma = 0; 4177 fail: 4178 ql_log(ql_log_fatal, NULL, 0x0030, 4179 "Memory allocation failure.\n"); 4180 return -ENOMEM; 4181 } 4182 4183 int 4184 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4185 { 4186 int rval; 4187 uint16_t size, max_cnt, temp; 4188 struct qla_hw_data *ha = vha->hw; 4189 4190 /* Return if we don't need to alloacate any extended logins */ 4191 if (!ql2xexlogins) 4192 return QLA_SUCCESS; 4193 4194 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4195 return QLA_SUCCESS; 4196 4197 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4198 max_cnt = 0; 4199 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4200 if (rval != QLA_SUCCESS) { 4201 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4202 "Failed to get exlogin status.\n"); 4203 return rval; 4204 } 4205 4206 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4207 temp *= size; 4208 4209 if (temp != ha->exlogin_size) { 4210 qla2x00_free_exlogin_buffer(ha); 4211 ha->exlogin_size = temp; 4212 4213 ql_log(ql_log_info, vha, 0xd024, 4214 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4215 max_cnt, size, temp); 4216 4217 ql_log(ql_log_info, vha, 0xd025, 4218 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4219 4220 /* Get consistent memory for extended logins */ 4221 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4222 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4223 if (!ha->exlogin_buf) { 4224 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4225 "Failed to allocate memory for exlogin_buf_dma.\n"); 4226 return -ENOMEM; 4227 } 4228 } 4229 4230 /* Now configure the dma buffer */ 4231 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4232 if (rval) { 4233 ql_log(ql_log_fatal, vha, 0xd033, 4234 "Setup extended login buffer ****FAILED****.\n"); 4235 qla2x00_free_exlogin_buffer(ha); 4236 } 4237 4238 return rval; 4239 } 4240 4241 /* 4242 * qla2x00_free_exlogin_buffer 4243 * 4244 * Input: 4245 * ha = adapter block pointer 4246 */ 4247 void 4248 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4249 { 4250 if (ha->exlogin_buf) { 4251 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4252 ha->exlogin_buf, ha->exlogin_buf_dma); 4253 ha->exlogin_buf = NULL; 4254 ha->exlogin_size = 0; 4255 } 4256 } 4257 4258 static void 4259 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4260 { 4261 u32 temp; 4262 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4263 4264 if (max_cnt > vha->hw->max_exchg) 4265 max_cnt = vha->hw->max_exchg; 4266 4267 if (qla_ini_mode_enabled(vha)) { 4268 if (ql2xiniexchg > max_cnt) 4269 ql2xiniexchg = max_cnt; 4270 4271 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4272 *ret_cnt = ql2xiniexchg; 4273 } else if (qla_tgt_mode_enabled(vha)) { 4274 if (ql2xexchoffld > max_cnt) 4275 ql2xexchoffld = max_cnt; 4276 4277 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4278 *ret_cnt = ql2xexchoffld; 4279 } else if (qla_dual_mode_enabled(vha)) { 4280 temp = ql2xiniexchg + ql2xexchoffld; 4281 if (temp > max_cnt) { 4282 ql2xiniexchg -= (temp - max_cnt)/2; 4283 ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4284 temp = max_cnt; 4285 } 4286 4287 if (temp > FW_DEF_EXCHANGES_CNT) 4288 *ret_cnt = temp; 4289 } 4290 } 4291 4292 int 4293 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4294 { 4295 int rval; 4296 u16 size, max_cnt; 4297 u32 actual_cnt, totsz; 4298 struct qla_hw_data *ha = vha->hw; 4299 4300 if (!ha->flags.exchoffld_enabled) 4301 return QLA_SUCCESS; 4302 4303 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4304 return QLA_SUCCESS; 4305 4306 max_cnt = 0; 4307 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4308 if (rval != QLA_SUCCESS) { 4309 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4310 "Failed to get exlogin status.\n"); 4311 return rval; 4312 } 4313 4314 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4315 ql_log(ql_log_info, vha, 0xd014, 4316 "Actual exchange offload count: %d.\n", actual_cnt); 4317 4318 totsz = actual_cnt * size; 4319 4320 if (totsz != ha->exchoffld_size) { 4321 qla2x00_free_exchoffld_buffer(ha); 4322 ha->exchoffld_size = totsz; 4323 4324 ql_log(ql_log_info, vha, 0xd016, 4325 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4326 max_cnt, actual_cnt, size, totsz); 4327 4328 ql_log(ql_log_info, vha, 0xd017, 4329 "Exchange Buffers requested size = 0x%x\n", 4330 ha->exchoffld_size); 4331 4332 /* Get consistent memory for extended logins */ 4333 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4334 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4335 if (!ha->exchoffld_buf) { 4336 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4337 "Failed to allocate memory for Exchange Offload.\n"); 4338 4339 if (ha->max_exchg > 4340 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4341 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4342 } else if (ha->max_exchg > 4343 (FW_DEF_EXCHANGES_CNT + 512)) { 4344 ha->max_exchg -= 512; 4345 } else { 4346 ha->flags.exchoffld_enabled = 0; 4347 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4348 "Disabling Exchange offload due to lack of memory\n"); 4349 } 4350 ha->exchoffld_size = 0; 4351 4352 return -ENOMEM; 4353 } 4354 } 4355 4356 /* Now configure the dma buffer */ 4357 rval = qla_set_exchoffld_mem_cfg(vha); 4358 if (rval) { 4359 ql_log(ql_log_fatal, vha, 0xd02e, 4360 "Setup exchange offload buffer ****FAILED****.\n"); 4361 qla2x00_free_exchoffld_buffer(ha); 4362 } else { 4363 /* re-adjust number of target exchange */ 4364 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4365 4366 if (qla_ini_mode_enabled(vha)) 4367 icb->exchange_count = 0; 4368 else 4369 icb->exchange_count = cpu_to_le16(ql2xexchoffld); 4370 } 4371 4372 return rval; 4373 } 4374 4375 /* 4376 * qla2x00_free_exchoffld_buffer 4377 * 4378 * Input: 4379 * ha = adapter block pointer 4380 */ 4381 void 4382 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4383 { 4384 if (ha->exchoffld_buf) { 4385 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4386 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4387 ha->exchoffld_buf = NULL; 4388 ha->exchoffld_size = 0; 4389 } 4390 } 4391 4392 /* 4393 * qla2x00_free_fw_dump 4394 * Frees fw dump stuff. 4395 * 4396 * Input: 4397 * ha = adapter block pointer 4398 */ 4399 static void 4400 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4401 { 4402 if (ha->fce) 4403 dma_free_coherent(&ha->pdev->dev, 4404 FCE_SIZE, ha->fce, ha->fce_dma); 4405 4406 if (ha->eft) 4407 dma_free_coherent(&ha->pdev->dev, 4408 EFT_SIZE, ha->eft, ha->eft_dma); 4409 4410 if (ha->fw_dump) 4411 vfree(ha->fw_dump); 4412 if (ha->fw_dump_template) 4413 vfree(ha->fw_dump_template); 4414 4415 ha->fce = NULL; 4416 ha->fce_dma = 0; 4417 ha->eft = NULL; 4418 ha->eft_dma = 0; 4419 ha->fw_dumped = 0; 4420 ha->fw_dump_cap_flags = 0; 4421 ha->fw_dump_reading = 0; 4422 ha->fw_dump = NULL; 4423 ha->fw_dump_len = 0; 4424 ha->fw_dump_template = NULL; 4425 ha->fw_dump_template_len = 0; 4426 } 4427 4428 /* 4429 * qla2x00_mem_free 4430 * Frees all adapter allocated memory. 4431 * 4432 * Input: 4433 * ha = adapter block pointer. 4434 */ 4435 static void 4436 qla2x00_mem_free(struct qla_hw_data *ha) 4437 { 4438 qla2x00_free_fw_dump(ha); 4439 4440 if (ha->mctp_dump) 4441 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4442 ha->mctp_dump_dma); 4443 4444 if (ha->srb_mempool) 4445 mempool_destroy(ha->srb_mempool); 4446 4447 if (ha->dcbx_tlv) 4448 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4449 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4450 4451 if (ha->xgmac_data) 4452 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4453 ha->xgmac_data, ha->xgmac_data_dma); 4454 4455 if (ha->sns_cmd) 4456 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4457 ha->sns_cmd, ha->sns_cmd_dma); 4458 4459 if (ha->ct_sns) 4460 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4461 ha->ct_sns, ha->ct_sns_dma); 4462 4463 if (ha->sfp_data) 4464 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4465 ha->sfp_data_dma); 4466 4467 if (ha->ms_iocb) 4468 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4469 4470 if (ha->ex_init_cb) 4471 dma_pool_free(ha->s_dma_pool, 4472 ha->ex_init_cb, ha->ex_init_cb_dma); 4473 4474 if (ha->async_pd) 4475 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4476 4477 if (ha->s_dma_pool) 4478 dma_pool_destroy(ha->s_dma_pool); 4479 4480 if (ha->gid_list) 4481 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4482 ha->gid_list, ha->gid_list_dma); 4483 4484 if (IS_QLA82XX(ha)) { 4485 if (!list_empty(&ha->gbl_dsd_list)) { 4486 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4487 4488 /* clean up allocated prev pool */ 4489 list_for_each_entry_safe(dsd_ptr, 4490 tdsd_ptr, &ha->gbl_dsd_list, list) { 4491 dma_pool_free(ha->dl_dma_pool, 4492 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4493 list_del(&dsd_ptr->list); 4494 kfree(dsd_ptr); 4495 } 4496 } 4497 } 4498 4499 if (ha->dl_dma_pool) 4500 dma_pool_destroy(ha->dl_dma_pool); 4501 4502 if (ha->fcp_cmnd_dma_pool) 4503 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4504 4505 if (ha->ctx_mempool) 4506 mempool_destroy(ha->ctx_mempool); 4507 4508 qlt_mem_free(ha); 4509 4510 if (ha->init_cb) 4511 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4512 ha->init_cb, ha->init_cb_dma); 4513 4514 vfree(ha->optrom_buffer); 4515 kfree(ha->nvram); 4516 kfree(ha->npiv_info); 4517 kfree(ha->swl); 4518 kfree(ha->loop_id_map); 4519 4520 ha->srb_mempool = NULL; 4521 ha->ctx_mempool = NULL; 4522 ha->sns_cmd = NULL; 4523 ha->sns_cmd_dma = 0; 4524 ha->ct_sns = NULL; 4525 ha->ct_sns_dma = 0; 4526 ha->ms_iocb = NULL; 4527 ha->ms_iocb_dma = 0; 4528 ha->init_cb = NULL; 4529 ha->init_cb_dma = 0; 4530 ha->ex_init_cb = NULL; 4531 ha->ex_init_cb_dma = 0; 4532 ha->async_pd = NULL; 4533 ha->async_pd_dma = 0; 4534 ha->loop_id_map = NULL; 4535 ha->npiv_info = NULL; 4536 ha->optrom_buffer = NULL; 4537 ha->swl = NULL; 4538 ha->nvram = NULL; 4539 ha->mctp_dump = NULL; 4540 ha->dcbx_tlv = NULL; 4541 ha->xgmac_data = NULL; 4542 ha->sfp_data = NULL; 4543 4544 ha->s_dma_pool = NULL; 4545 ha->dl_dma_pool = NULL; 4546 ha->fcp_cmnd_dma_pool = NULL; 4547 4548 ha->gid_list = NULL; 4549 ha->gid_list_dma = 0; 4550 4551 ha->tgt.atio_ring = NULL; 4552 ha->tgt.atio_dma = 0; 4553 ha->tgt.tgt_vp_map = NULL; 4554 } 4555 4556 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4557 struct qla_hw_data *ha) 4558 { 4559 struct Scsi_Host *host; 4560 struct scsi_qla_host *vha = NULL; 4561 4562 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4563 if (!host) { 4564 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4565 "Failed to allocate host from the scsi layer, aborting.\n"); 4566 return NULL; 4567 } 4568 4569 /* Clear our data area */ 4570 vha = shost_priv(host); 4571 memset(vha, 0, sizeof(scsi_qla_host_t)); 4572 4573 vha->host = host; 4574 vha->host_no = host->host_no; 4575 vha->hw = ha; 4576 4577 INIT_LIST_HEAD(&vha->vp_fcports); 4578 INIT_LIST_HEAD(&vha->work_list); 4579 INIT_LIST_HEAD(&vha->list); 4580 INIT_LIST_HEAD(&vha->qla_cmd_list); 4581 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4582 INIT_LIST_HEAD(&vha->logo_list); 4583 INIT_LIST_HEAD(&vha->plogi_ack_list); 4584 INIT_LIST_HEAD(&vha->qp_list); 4585 INIT_LIST_HEAD(&vha->gnl.fcports); 4586 INIT_LIST_HEAD(&vha->nvme_rport_list); 4587 INIT_LIST_HEAD(&vha->gpnid_list); 4588 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4589 4590 spin_lock_init(&vha->work_lock); 4591 spin_lock_init(&vha->cmd_list_lock); 4592 spin_lock_init(&vha->gnl.fcports_lock); 4593 init_waitqueue_head(&vha->fcport_waitQ); 4594 init_waitqueue_head(&vha->vref_waitq); 4595 4596 vha->gnl.size = sizeof(struct get_name_list_extended) * 4597 (ha->max_loop_id + 1); 4598 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4599 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4600 if (!vha->gnl.l) { 4601 ql_log(ql_log_fatal, vha, 0xd04a, 4602 "Alloc failed for name list.\n"); 4603 scsi_remove_host(vha->host); 4604 return NULL; 4605 } 4606 4607 /* todo: what about ext login? */ 4608 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4609 vha->scan.l = vmalloc(vha->scan.size); 4610 if (!vha->scan.l) { 4611 ql_log(ql_log_fatal, vha, 0xd04a, 4612 "Alloc failed for scan database.\n"); 4613 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4614 vha->gnl.l, vha->gnl.ldma); 4615 scsi_remove_host(vha->host); 4616 return NULL; 4617 } 4618 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4619 4620 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4621 ql_dbg(ql_dbg_init, vha, 0x0041, 4622 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4623 vha->host, vha->hw, vha, 4624 dev_name(&(ha->pdev->dev))); 4625 4626 return vha; 4627 } 4628 4629 struct qla_work_evt * 4630 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4631 { 4632 struct qla_work_evt *e; 4633 uint8_t bail; 4634 4635 QLA_VHA_MARK_BUSY(vha, bail); 4636 if (bail) 4637 return NULL; 4638 4639 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4640 if (!e) { 4641 QLA_VHA_MARK_NOT_BUSY(vha); 4642 return NULL; 4643 } 4644 4645 INIT_LIST_HEAD(&e->list); 4646 e->type = type; 4647 e->flags = QLA_EVT_FLAG_FREE; 4648 return e; 4649 } 4650 4651 int 4652 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4653 { 4654 unsigned long flags; 4655 bool q = false; 4656 4657 spin_lock_irqsave(&vha->work_lock, flags); 4658 list_add_tail(&e->list, &vha->work_list); 4659 4660 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4661 q = true; 4662 4663 spin_unlock_irqrestore(&vha->work_lock, flags); 4664 4665 if (q) 4666 queue_work(vha->hw->wq, &vha->iocb_work); 4667 4668 return QLA_SUCCESS; 4669 } 4670 4671 int 4672 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4673 u32 data) 4674 { 4675 struct qla_work_evt *e; 4676 4677 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4678 if (!e) 4679 return QLA_FUNCTION_FAILED; 4680 4681 e->u.aen.code = code; 4682 e->u.aen.data = data; 4683 return qla2x00_post_work(vha, e); 4684 } 4685 4686 int 4687 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4688 { 4689 struct qla_work_evt *e; 4690 4691 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4692 if (!e) 4693 return QLA_FUNCTION_FAILED; 4694 4695 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4696 return qla2x00_post_work(vha, e); 4697 } 4698 4699 #define qla2x00_post_async_work(name, type) \ 4700 int qla2x00_post_async_##name##_work( \ 4701 struct scsi_qla_host *vha, \ 4702 fc_port_t *fcport, uint16_t *data) \ 4703 { \ 4704 struct qla_work_evt *e; \ 4705 \ 4706 e = qla2x00_alloc_work(vha, type); \ 4707 if (!e) \ 4708 return QLA_FUNCTION_FAILED; \ 4709 \ 4710 e->u.logio.fcport = fcport; \ 4711 if (data) { \ 4712 e->u.logio.data[0] = data[0]; \ 4713 e->u.logio.data[1] = data[1]; \ 4714 } \ 4715 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4716 return qla2x00_post_work(vha, e); \ 4717 } 4718 4719 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4720 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4721 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4722 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4723 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); 4724 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4725 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4726 4727 int 4728 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4729 { 4730 struct qla_work_evt *e; 4731 4732 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4733 if (!e) 4734 return QLA_FUNCTION_FAILED; 4735 4736 e->u.uevent.code = code; 4737 return qla2x00_post_work(vha, e); 4738 } 4739 4740 static void 4741 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4742 { 4743 char event_string[40]; 4744 char *envp[] = { event_string, NULL }; 4745 4746 switch (code) { 4747 case QLA_UEVENT_CODE_FW_DUMP: 4748 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4749 vha->host_no); 4750 break; 4751 default: 4752 /* do nothing */ 4753 break; 4754 } 4755 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4756 } 4757 4758 int 4759 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4760 uint32_t *data, int cnt) 4761 { 4762 struct qla_work_evt *e; 4763 4764 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4765 if (!e) 4766 return QLA_FUNCTION_FAILED; 4767 4768 e->u.aenfx.evtcode = evtcode; 4769 e->u.aenfx.count = cnt; 4770 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4771 return qla2x00_post_work(vha, e); 4772 } 4773 4774 int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport) 4775 { 4776 struct qla_work_evt *e; 4777 4778 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT); 4779 if (!e) 4780 return QLA_FUNCTION_FAILED; 4781 4782 e->u.fcport.fcport = fcport; 4783 return qla2x00_post_work(vha, e); 4784 } 4785 4786 static 4787 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 4788 { 4789 unsigned long flags; 4790 fc_port_t *fcport = NULL, *tfcp; 4791 struct qlt_plogi_ack_t *pla = 4792 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 4793 uint8_t free_fcport = 0; 4794 u64 wwn; 4795 4796 ql_dbg(ql_dbg_disc, vha, 0xffff, 4797 "%s %d %8phC enter\n", 4798 __func__, __LINE__, e->u.new_sess.port_name); 4799 4800 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4801 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 4802 if (fcport) { 4803 fcport->d_id = e->u.new_sess.id; 4804 if (pla) { 4805 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4806 memcpy(fcport->node_name, 4807 pla->iocb.u.isp24.u.plogi.node_name, 4808 WWN_SIZE); 4809 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 4810 /* we took an extra ref_count to prevent PLOGI ACK when 4811 * fcport/sess has not been created. 4812 */ 4813 pla->ref_count--; 4814 } 4815 } else { 4816 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4817 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 4818 if (fcport) { 4819 fcport->d_id = e->u.new_sess.id; 4820 fcport->flags |= FCF_FABRIC_DEVICE; 4821 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 4822 if (e->u.new_sess.fc4_type & FS_FC4TYPE_FCP) 4823 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 4824 4825 if (e->u.new_sess.fc4_type & FS_FC4TYPE_NVME) { 4826 fcport->fc4_type = FC4_TYPE_OTHER; 4827 fcport->fc4f_nvme = FC4_TYPE_NVME; 4828 } 4829 4830 memcpy(fcport->port_name, e->u.new_sess.port_name, 4831 WWN_SIZE); 4832 } else { 4833 ql_dbg(ql_dbg_disc, vha, 0xffff, 4834 "%s %8phC mem alloc fail.\n", 4835 __func__, e->u.new_sess.port_name); 4836 4837 if (pla) 4838 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4839 return; 4840 } 4841 4842 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4843 /* search again to make sure no one else got ahead */ 4844 tfcp = qla2x00_find_fcport_by_wwpn(vha, 4845 e->u.new_sess.port_name, 1); 4846 if (tfcp) { 4847 /* should rarily happen */ 4848 ql_dbg(ql_dbg_disc, vha, 0xffff, 4849 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 4850 __func__, tfcp->port_name, tfcp->disc_state, 4851 tfcp->fw_login_state); 4852 4853 free_fcport = 1; 4854 } else { 4855 list_add_tail(&fcport->list, &vha->vp_fcports); 4856 4857 } 4858 if (pla) { 4859 qlt_plogi_ack_link(vha, pla, fcport, 4860 QLT_PLOGI_LINK_SAME_WWN); 4861 pla->ref_count--; 4862 } 4863 } 4864 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4865 4866 if (fcport) { 4867 if (N2N_TOPO(vha->hw)) 4868 fcport->flags &= ~FCF_FABRIC_DEVICE; 4869 4870 fcport->id_changed = 1; 4871 fcport->scan_state = QLA_FCPORT_FOUND; 4872 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 4873 4874 if (pla) { 4875 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 4876 u16 wd3_lo; 4877 4878 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4879 fcport->local = 0; 4880 fcport->loop_id = 4881 le16_to_cpu( 4882 pla->iocb.u.isp24.nport_handle); 4883 fcport->fw_login_state = DSC_LS_PRLI_PEND; 4884 wd3_lo = 4885 le16_to_cpu( 4886 pla->iocb.u.isp24.u.prli.wd3_lo); 4887 4888 if (wd3_lo & BIT_7) 4889 fcport->conf_compl_supported = 1; 4890 4891 if ((wd3_lo & BIT_4) == 0) 4892 fcport->port_type = FCT_INITIATOR; 4893 else 4894 fcport->port_type = FCT_TARGET; 4895 } 4896 qlt_plogi_ack_unref(vha, pla); 4897 } else { 4898 fc_port_t *dfcp = NULL; 4899 4900 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 4901 tfcp = qla2x00_find_fcport_by_nportid(vha, 4902 &e->u.new_sess.id, 1); 4903 if (tfcp && (tfcp != fcport)) { 4904 /* 4905 * We have a conflict fcport with same NportID. 4906 */ 4907 ql_dbg(ql_dbg_disc, vha, 0xffff, 4908 "%s %8phC found conflict b4 add. DS %d LS %d\n", 4909 __func__, tfcp->port_name, tfcp->disc_state, 4910 tfcp->fw_login_state); 4911 4912 switch (tfcp->disc_state) { 4913 case DSC_DELETED: 4914 break; 4915 case DSC_DELETE_PEND: 4916 fcport->login_pause = 1; 4917 tfcp->conflict = fcport; 4918 break; 4919 default: 4920 fcport->login_pause = 1; 4921 tfcp->conflict = fcport; 4922 dfcp = tfcp; 4923 break; 4924 } 4925 } 4926 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 4927 if (dfcp) 4928 qlt_schedule_sess_for_deletion(tfcp); 4929 4930 wwn = wwn_to_u64(fcport->node_name); 4931 4932 if (!wwn) 4933 qla24xx_async_gnnid(vha, fcport); 4934 else 4935 qla24xx_async_gnl(vha, fcport); 4936 } 4937 } 4938 4939 if (free_fcport) { 4940 qla2x00_free_fcport(fcport); 4941 if (pla) 4942 kmem_cache_free(qla_tgt_plogi_cachep, pla); 4943 } 4944 } 4945 4946 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 4947 { 4948 struct srb *sp = e->u.iosb.sp; 4949 int rval; 4950 4951 rval = qla2x00_start_sp(sp); 4952 if (rval != QLA_SUCCESS) { 4953 ql_dbg(ql_dbg_disc, vha, 0x2043, 4954 "%s: %s: Re-issue IOCB failed (%d).\n", 4955 __func__, sp->name, rval); 4956 qla24xx_sp_unmap(vha, sp); 4957 } 4958 } 4959 4960 void 4961 qla2x00_do_work(struct scsi_qla_host *vha) 4962 { 4963 struct qla_work_evt *e, *tmp; 4964 unsigned long flags; 4965 LIST_HEAD(work); 4966 4967 spin_lock_irqsave(&vha->work_lock, flags); 4968 list_splice_init(&vha->work_list, &work); 4969 spin_unlock_irqrestore(&vha->work_lock, flags); 4970 4971 list_for_each_entry_safe(e, tmp, &work, list) { 4972 list_del_init(&e->list); 4973 4974 switch (e->type) { 4975 case QLA_EVT_AEN: 4976 fc_host_post_event(vha->host, fc_get_event_number(), 4977 e->u.aen.code, e->u.aen.data); 4978 break; 4979 case QLA_EVT_IDC_ACK: 4980 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 4981 break; 4982 case QLA_EVT_ASYNC_LOGIN: 4983 qla2x00_async_login(vha, e->u.logio.fcport, 4984 e->u.logio.data); 4985 break; 4986 case QLA_EVT_ASYNC_LOGOUT: 4987 qla2x00_async_logout(vha, e->u.logio.fcport); 4988 break; 4989 case QLA_EVT_ASYNC_LOGOUT_DONE: 4990 qla2x00_async_logout_done(vha, e->u.logio.fcport, 4991 e->u.logio.data); 4992 break; 4993 case QLA_EVT_ASYNC_ADISC: 4994 qla2x00_async_adisc(vha, e->u.logio.fcport, 4995 e->u.logio.data); 4996 break; 4997 case QLA_EVT_ASYNC_ADISC_DONE: 4998 qla2x00_async_adisc_done(vha, e->u.logio.fcport, 4999 e->u.logio.data); 5000 break; 5001 case QLA_EVT_UEVENT: 5002 qla2x00_uevent_emit(vha, e->u.uevent.code); 5003 break; 5004 case QLA_EVT_AENFX: 5005 qlafx00_process_aen(vha, e); 5006 break; 5007 case QLA_EVT_GIDPN: 5008 qla24xx_async_gidpn(vha, e->u.fcport.fcport); 5009 break; 5010 case QLA_EVT_GPNID: 5011 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5012 break; 5013 case QLA_EVT_UNMAP: 5014 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5015 break; 5016 case QLA_EVT_RELOGIN: 5017 qla2x00_relogin(vha); 5018 break; 5019 case QLA_EVT_NEW_SESS: 5020 qla24xx_create_new_sess(vha, e); 5021 break; 5022 case QLA_EVT_GPDB: 5023 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5024 e->u.fcport.opt); 5025 break; 5026 case QLA_EVT_PRLI: 5027 qla24xx_async_prli(vha, e->u.fcport.fcport); 5028 break; 5029 case QLA_EVT_GPSC: 5030 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5031 break; 5032 case QLA_EVT_UPD_FCPORT: 5033 qla2x00_update_fcport(vha, e->u.fcport.fcport); 5034 break; 5035 case QLA_EVT_GNL: 5036 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5037 break; 5038 case QLA_EVT_NACK: 5039 qla24xx_do_nack_work(vha, e); 5040 break; 5041 case QLA_EVT_ASYNC_PRLO: 5042 qla2x00_async_prlo(vha, e->u.logio.fcport); 5043 break; 5044 case QLA_EVT_ASYNC_PRLO_DONE: 5045 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5046 e->u.logio.data); 5047 break; 5048 case QLA_EVT_GPNFT: 5049 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5050 e->u.gpnft.sp); 5051 break; 5052 case QLA_EVT_GPNFT_DONE: 5053 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5054 break; 5055 case QLA_EVT_GNNFT_DONE: 5056 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5057 break; 5058 case QLA_EVT_GNNID: 5059 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5060 break; 5061 case QLA_EVT_GFPNID: 5062 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5063 break; 5064 case QLA_EVT_SP_RETRY: 5065 qla_sp_retry(vha, e); 5066 } 5067 if (e->flags & QLA_EVT_FLAG_FREE) 5068 kfree(e); 5069 5070 /* For each work completed decrement vha ref count */ 5071 QLA_VHA_MARK_NOT_BUSY(vha); 5072 } 5073 } 5074 5075 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5076 { 5077 struct qla_work_evt *e; 5078 5079 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5080 5081 if (!e) { 5082 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5083 return QLA_FUNCTION_FAILED; 5084 } 5085 5086 return qla2x00_post_work(vha, e); 5087 } 5088 5089 /* Relogins all the fcports of a vport 5090 * Context: dpc thread 5091 */ 5092 void qla2x00_relogin(struct scsi_qla_host *vha) 5093 { 5094 fc_port_t *fcport; 5095 int status; 5096 struct event_arg ea; 5097 5098 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5099 /* 5100 * If the port is not ONLINE then try to login 5101 * to it if we haven't run out of retries. 5102 */ 5103 if (atomic_read(&fcport->state) != FCS_ONLINE && 5104 fcport->login_retry && 5105 !(fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE))) { 5106 if (vha->hw->current_topology != ISP_CFG_NL) { 5107 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108, 5108 "%s %8phC DS %d LS %d\n", __func__, 5109 fcport->port_name, fcport->disc_state, 5110 fcport->fw_login_state); 5111 memset(&ea, 0, sizeof(ea)); 5112 ea.event = FCME_RELOGIN; 5113 ea.fcport = fcport; 5114 qla2x00_fcport_event_handler(vha, &ea); 5115 } else if (vha->hw->current_topology == ISP_CFG_NL) { 5116 fcport->login_retry--; 5117 status = qla2x00_local_device_login(vha, 5118 fcport); 5119 if (status == QLA_SUCCESS) { 5120 fcport->old_loop_id = fcport->loop_id; 5121 ql_dbg(ql_dbg_disc, vha, 0x2003, 5122 "Port login OK: logged in ID 0x%x.\n", 5123 fcport->loop_id); 5124 qla2x00_update_fcport(vha, fcport); 5125 } else if (status == 1) { 5126 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5127 /* retry the login again */ 5128 ql_dbg(ql_dbg_disc, vha, 0x2007, 5129 "Retrying %d login again loop_id 0x%x.\n", 5130 fcport->login_retry, 5131 fcport->loop_id); 5132 } else { 5133 fcport->login_retry = 0; 5134 } 5135 5136 if (fcport->login_retry == 0 && 5137 status != QLA_SUCCESS) 5138 qla2x00_clear_loop_id(fcport); 5139 } 5140 } 5141 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5142 break; 5143 } 5144 5145 ql_dbg(ql_dbg_disc, vha, 0x400e, 5146 "Relogin end.\n"); 5147 } 5148 5149 /* Schedule work on any of the dpc-workqueues */ 5150 void 5151 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5152 { 5153 struct qla_hw_data *ha = base_vha->hw; 5154 5155 switch (work_code) { 5156 case MBA_IDC_AEN: /* 0x8200 */ 5157 if (ha->dpc_lp_wq) 5158 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5159 break; 5160 5161 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5162 if (!ha->flags.nic_core_reset_hdlr_active) { 5163 if (ha->dpc_hp_wq) 5164 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5165 } else 5166 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5167 "NIC Core reset is already active. Skip " 5168 "scheduling it again.\n"); 5169 break; 5170 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5171 if (ha->dpc_hp_wq) 5172 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5173 break; 5174 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5175 if (ha->dpc_hp_wq) 5176 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5177 break; 5178 default: 5179 ql_log(ql_log_warn, base_vha, 0xb05f, 5180 "Unknown work-code=0x%x.\n", work_code); 5181 } 5182 5183 return; 5184 } 5185 5186 /* Work: Perform NIC Core Unrecoverable state handling */ 5187 void 5188 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5189 { 5190 struct qla_hw_data *ha = 5191 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5193 uint32_t dev_state = 0; 5194 5195 qla83xx_idc_lock(base_vha, 0); 5196 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5197 qla83xx_reset_ownership(base_vha); 5198 if (ha->flags.nic_core_reset_owner) { 5199 ha->flags.nic_core_reset_owner = 0; 5200 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5201 QLA8XXX_DEV_FAILED); 5202 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5203 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5204 } 5205 qla83xx_idc_unlock(base_vha, 0); 5206 } 5207 5208 /* Work: Execute IDC state handler */ 5209 void 5210 qla83xx_idc_state_handler_work(struct work_struct *work) 5211 { 5212 struct qla_hw_data *ha = 5213 container_of(work, struct qla_hw_data, idc_state_handler); 5214 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5215 uint32_t dev_state = 0; 5216 5217 qla83xx_idc_lock(base_vha, 0); 5218 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5219 if (dev_state == QLA8XXX_DEV_FAILED || 5220 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5221 qla83xx_idc_state_handler(base_vha); 5222 qla83xx_idc_unlock(base_vha, 0); 5223 } 5224 5225 static int 5226 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5227 { 5228 int rval = QLA_SUCCESS; 5229 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5230 uint32_t heart_beat_counter1, heart_beat_counter2; 5231 5232 do { 5233 if (time_after(jiffies, heart_beat_wait)) { 5234 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5235 "Nic Core f/w is not alive.\n"); 5236 rval = QLA_FUNCTION_FAILED; 5237 break; 5238 } 5239 5240 qla83xx_idc_lock(base_vha, 0); 5241 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5242 &heart_beat_counter1); 5243 qla83xx_idc_unlock(base_vha, 0); 5244 msleep(100); 5245 qla83xx_idc_lock(base_vha, 0); 5246 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5247 &heart_beat_counter2); 5248 qla83xx_idc_unlock(base_vha, 0); 5249 } while (heart_beat_counter1 == heart_beat_counter2); 5250 5251 return rval; 5252 } 5253 5254 /* Work: Perform NIC Core Reset handling */ 5255 void 5256 qla83xx_nic_core_reset_work(struct work_struct *work) 5257 { 5258 struct qla_hw_data *ha = 5259 container_of(work, struct qla_hw_data, nic_core_reset); 5260 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5261 uint32_t dev_state = 0; 5262 5263 if (IS_QLA2031(ha)) { 5264 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5265 ql_log(ql_log_warn, base_vha, 0xb081, 5266 "Failed to dump mctp\n"); 5267 return; 5268 } 5269 5270 if (!ha->flags.nic_core_reset_hdlr_active) { 5271 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5272 qla83xx_idc_lock(base_vha, 0); 5273 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5274 &dev_state); 5275 qla83xx_idc_unlock(base_vha, 0); 5276 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5277 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5278 "Nic Core f/w is alive.\n"); 5279 return; 5280 } 5281 } 5282 5283 ha->flags.nic_core_reset_hdlr_active = 1; 5284 if (qla83xx_nic_core_reset(base_vha)) { 5285 /* NIC Core reset failed. */ 5286 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5287 "NIC Core reset failed.\n"); 5288 } 5289 ha->flags.nic_core_reset_hdlr_active = 0; 5290 } 5291 } 5292 5293 /* Work: Handle 8200 IDC aens */ 5294 void 5295 qla83xx_service_idc_aen(struct work_struct *work) 5296 { 5297 struct qla_hw_data *ha = 5298 container_of(work, struct qla_hw_data, idc_aen); 5299 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5300 uint32_t dev_state, idc_control; 5301 5302 qla83xx_idc_lock(base_vha, 0); 5303 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5304 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5305 qla83xx_idc_unlock(base_vha, 0); 5306 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5307 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5308 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5309 "Application requested NIC Core Reset.\n"); 5310 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5311 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5312 QLA_SUCCESS) { 5313 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5314 "Other protocol driver requested NIC Core Reset.\n"); 5315 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5316 } 5317 } else if (dev_state == QLA8XXX_DEV_FAILED || 5318 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5319 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5320 } 5321 } 5322 5323 static void 5324 qla83xx_wait_logic(void) 5325 { 5326 int i; 5327 5328 /* Yield CPU */ 5329 if (!in_interrupt()) { 5330 /* 5331 * Wait about 200ms before retrying again. 5332 * This controls the number of retries for single 5333 * lock operation. 5334 */ 5335 msleep(100); 5336 schedule(); 5337 } else { 5338 for (i = 0; i < 20; i++) 5339 cpu_relax(); /* This a nop instr on i386 */ 5340 } 5341 } 5342 5343 static int 5344 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5345 { 5346 int rval; 5347 uint32_t data; 5348 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5349 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5350 struct qla_hw_data *ha = base_vha->hw; 5351 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5352 "Trying force recovery of the IDC lock.\n"); 5353 5354 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5355 if (rval) 5356 return rval; 5357 5358 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5359 return QLA_SUCCESS; 5360 } else { 5361 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5362 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5363 data); 5364 if (rval) 5365 return rval; 5366 5367 msleep(200); 5368 5369 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5370 &data); 5371 if (rval) 5372 return rval; 5373 5374 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5375 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5376 ~(idc_lck_rcvry_stage_mask)); 5377 rval = qla83xx_wr_reg(base_vha, 5378 QLA83XX_IDC_LOCK_RECOVERY, data); 5379 if (rval) 5380 return rval; 5381 5382 /* Forcefully perform IDC UnLock */ 5383 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5384 &data); 5385 if (rval) 5386 return rval; 5387 /* Clear lock-id by setting 0xff */ 5388 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5389 0xff); 5390 if (rval) 5391 return rval; 5392 /* Clear lock-recovery by setting 0x0 */ 5393 rval = qla83xx_wr_reg(base_vha, 5394 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5395 if (rval) 5396 return rval; 5397 } else 5398 return QLA_SUCCESS; 5399 } 5400 5401 return rval; 5402 } 5403 5404 static int 5405 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5406 { 5407 int rval = QLA_SUCCESS; 5408 uint32_t o_drv_lockid, n_drv_lockid; 5409 unsigned long lock_recovery_timeout; 5410 5411 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5412 retry_lockid: 5413 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5414 if (rval) 5415 goto exit; 5416 5417 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5418 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5419 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5420 return QLA_SUCCESS; 5421 else 5422 return QLA_FUNCTION_FAILED; 5423 } 5424 5425 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5426 if (rval) 5427 goto exit; 5428 5429 if (o_drv_lockid == n_drv_lockid) { 5430 qla83xx_wait_logic(); 5431 goto retry_lockid; 5432 } else 5433 return QLA_SUCCESS; 5434 5435 exit: 5436 return rval; 5437 } 5438 5439 void 5440 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5441 { 5442 uint16_t options = (requester_id << 15) | BIT_6; 5443 uint32_t data; 5444 uint32_t lock_owner; 5445 struct qla_hw_data *ha = base_vha->hw; 5446 5447 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5448 retry_lock: 5449 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5450 == QLA_SUCCESS) { 5451 if (data) { 5452 /* Setting lock-id to our function-number */ 5453 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5454 ha->portnum); 5455 } else { 5456 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5457 &lock_owner); 5458 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5459 "Failed to acquire IDC lock, acquired by %d, " 5460 "retrying...\n", lock_owner); 5461 5462 /* Retry/Perform IDC-Lock recovery */ 5463 if (qla83xx_idc_lock_recovery(base_vha) 5464 == QLA_SUCCESS) { 5465 qla83xx_wait_logic(); 5466 goto retry_lock; 5467 } else 5468 ql_log(ql_log_warn, base_vha, 0xb075, 5469 "IDC Lock recovery FAILED.\n"); 5470 } 5471 5472 } 5473 5474 return; 5475 5476 /* XXX: IDC-lock implementation using access-control mbx */ 5477 retry_lock2: 5478 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5479 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 5480 "Failed to acquire IDC lock. retrying...\n"); 5481 /* Retry/Perform IDC-Lock recovery */ 5482 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 5483 qla83xx_wait_logic(); 5484 goto retry_lock2; 5485 } else 5486 ql_log(ql_log_warn, base_vha, 0xb076, 5487 "IDC Lock recovery FAILED.\n"); 5488 } 5489 5490 return; 5491 } 5492 5493 void 5494 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5495 { 5496 #if 0 5497 uint16_t options = (requester_id << 15) | BIT_7; 5498 #endif 5499 uint16_t retry; 5500 uint32_t data; 5501 struct qla_hw_data *ha = base_vha->hw; 5502 5503 /* IDC-unlock implementation using driver-unlock/lock-id 5504 * remote registers 5505 */ 5506 retry = 0; 5507 retry_unlock: 5508 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5509 == QLA_SUCCESS) { 5510 if (data == ha->portnum) { 5511 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5512 /* Clearing lock-id by setting 0xff */ 5513 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5514 } else if (retry < 10) { 5515 /* SV: XXX: IDC unlock retrying needed here? */ 5516 5517 /* Retry for IDC-unlock */ 5518 qla83xx_wait_logic(); 5519 retry++; 5520 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5521 "Failed to release IDC lock, retrying=%d\n", retry); 5522 goto retry_unlock; 5523 } 5524 } else if (retry < 10) { 5525 /* Retry for IDC-unlock */ 5526 qla83xx_wait_logic(); 5527 retry++; 5528 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5529 "Failed to read drv-lockid, retrying=%d\n", retry); 5530 goto retry_unlock; 5531 } 5532 5533 return; 5534 5535 #if 0 5536 /* XXX: IDC-unlock implementation using access-control mbx */ 5537 retry = 0; 5538 retry_unlock2: 5539 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5540 if (retry < 10) { 5541 /* Retry for IDC-unlock */ 5542 qla83xx_wait_logic(); 5543 retry++; 5544 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5545 "Failed to release IDC lock, retrying=%d\n", retry); 5546 goto retry_unlock2; 5547 } 5548 } 5549 5550 return; 5551 #endif 5552 } 5553 5554 int 5555 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5556 { 5557 int rval = QLA_SUCCESS; 5558 struct qla_hw_data *ha = vha->hw; 5559 uint32_t drv_presence; 5560 5561 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5562 if (rval == QLA_SUCCESS) { 5563 drv_presence |= (1 << ha->portnum); 5564 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5565 drv_presence); 5566 } 5567 5568 return rval; 5569 } 5570 5571 int 5572 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5573 { 5574 int rval = QLA_SUCCESS; 5575 5576 qla83xx_idc_lock(vha, 0); 5577 rval = __qla83xx_set_drv_presence(vha); 5578 qla83xx_idc_unlock(vha, 0); 5579 5580 return rval; 5581 } 5582 5583 int 5584 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5585 { 5586 int rval = QLA_SUCCESS; 5587 struct qla_hw_data *ha = vha->hw; 5588 uint32_t drv_presence; 5589 5590 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5591 if (rval == QLA_SUCCESS) { 5592 drv_presence &= ~(1 << ha->portnum); 5593 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5594 drv_presence); 5595 } 5596 5597 return rval; 5598 } 5599 5600 int 5601 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5602 { 5603 int rval = QLA_SUCCESS; 5604 5605 qla83xx_idc_lock(vha, 0); 5606 rval = __qla83xx_clear_drv_presence(vha); 5607 qla83xx_idc_unlock(vha, 0); 5608 5609 return rval; 5610 } 5611 5612 static void 5613 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5614 { 5615 struct qla_hw_data *ha = vha->hw; 5616 uint32_t drv_ack, drv_presence; 5617 unsigned long ack_timeout; 5618 5619 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5620 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5621 while (1) { 5622 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5623 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5624 if ((drv_ack & drv_presence) == drv_presence) 5625 break; 5626 5627 if (time_after_eq(jiffies, ack_timeout)) { 5628 ql_log(ql_log_warn, vha, 0xb067, 5629 "RESET ACK TIMEOUT! drv_presence=0x%x " 5630 "drv_ack=0x%x\n", drv_presence, drv_ack); 5631 /* 5632 * The function(s) which did not ack in time are forced 5633 * to withdraw any further participation in the IDC 5634 * reset. 5635 */ 5636 if (drv_ack != drv_presence) 5637 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5638 drv_ack); 5639 break; 5640 } 5641 5642 qla83xx_idc_unlock(vha, 0); 5643 msleep(1000); 5644 qla83xx_idc_lock(vha, 0); 5645 } 5646 5647 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5648 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5649 } 5650 5651 static int 5652 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5653 { 5654 int rval = QLA_SUCCESS; 5655 uint32_t idc_control; 5656 5657 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5658 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5659 5660 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5661 __qla83xx_get_idc_control(vha, &idc_control); 5662 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5663 __qla83xx_set_idc_control(vha, 0); 5664 5665 qla83xx_idc_unlock(vha, 0); 5666 rval = qla83xx_restart_nic_firmware(vha); 5667 qla83xx_idc_lock(vha, 0); 5668 5669 if (rval != QLA_SUCCESS) { 5670 ql_log(ql_log_fatal, vha, 0xb06a, 5671 "Failed to restart NIC f/w.\n"); 5672 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5673 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5674 } else { 5675 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5676 "Success in restarting nic f/w.\n"); 5677 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5678 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5679 } 5680 5681 return rval; 5682 } 5683 5684 /* Assumes idc_lock always held on entry */ 5685 int 5686 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5687 { 5688 struct qla_hw_data *ha = base_vha->hw; 5689 int rval = QLA_SUCCESS; 5690 unsigned long dev_init_timeout; 5691 uint32_t dev_state; 5692 5693 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5694 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5695 5696 while (1) { 5697 5698 if (time_after_eq(jiffies, dev_init_timeout)) { 5699 ql_log(ql_log_warn, base_vha, 0xb06e, 5700 "Initialization TIMEOUT!\n"); 5701 /* Init timeout. Disable further NIC Core 5702 * communication. 5703 */ 5704 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5705 QLA8XXX_DEV_FAILED); 5706 ql_log(ql_log_info, base_vha, 0xb06f, 5707 "HW State: FAILED.\n"); 5708 } 5709 5710 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5711 switch (dev_state) { 5712 case QLA8XXX_DEV_READY: 5713 if (ha->flags.nic_core_reset_owner) 5714 qla83xx_idc_audit(base_vha, 5715 IDC_AUDIT_COMPLETION); 5716 ha->flags.nic_core_reset_owner = 0; 5717 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5718 "Reset_owner reset by 0x%x.\n", 5719 ha->portnum); 5720 goto exit; 5721 case QLA8XXX_DEV_COLD: 5722 if (ha->flags.nic_core_reset_owner) 5723 rval = qla83xx_device_bootstrap(base_vha); 5724 else { 5725 /* Wait for AEN to change device-state */ 5726 qla83xx_idc_unlock(base_vha, 0); 5727 msleep(1000); 5728 qla83xx_idc_lock(base_vha, 0); 5729 } 5730 break; 5731 case QLA8XXX_DEV_INITIALIZING: 5732 /* Wait for AEN to change device-state */ 5733 qla83xx_idc_unlock(base_vha, 0); 5734 msleep(1000); 5735 qla83xx_idc_lock(base_vha, 0); 5736 break; 5737 case QLA8XXX_DEV_NEED_RESET: 5738 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5739 qla83xx_need_reset_handler(base_vha); 5740 else { 5741 /* Wait for AEN to change device-state */ 5742 qla83xx_idc_unlock(base_vha, 0); 5743 msleep(1000); 5744 qla83xx_idc_lock(base_vha, 0); 5745 } 5746 /* reset timeout value after need reset handler */ 5747 dev_init_timeout = jiffies + 5748 (ha->fcoe_dev_init_timeout * HZ); 5749 break; 5750 case QLA8XXX_DEV_NEED_QUIESCENT: 5751 /* XXX: DEBUG for now */ 5752 qla83xx_idc_unlock(base_vha, 0); 5753 msleep(1000); 5754 qla83xx_idc_lock(base_vha, 0); 5755 break; 5756 case QLA8XXX_DEV_QUIESCENT: 5757 /* XXX: DEBUG for now */ 5758 if (ha->flags.quiesce_owner) 5759 goto exit; 5760 5761 qla83xx_idc_unlock(base_vha, 0); 5762 msleep(1000); 5763 qla83xx_idc_lock(base_vha, 0); 5764 dev_init_timeout = jiffies + 5765 (ha->fcoe_dev_init_timeout * HZ); 5766 break; 5767 case QLA8XXX_DEV_FAILED: 5768 if (ha->flags.nic_core_reset_owner) 5769 qla83xx_idc_audit(base_vha, 5770 IDC_AUDIT_COMPLETION); 5771 ha->flags.nic_core_reset_owner = 0; 5772 __qla83xx_clear_drv_presence(base_vha); 5773 qla83xx_idc_unlock(base_vha, 0); 5774 qla8xxx_dev_failed_handler(base_vha); 5775 rval = QLA_FUNCTION_FAILED; 5776 qla83xx_idc_lock(base_vha, 0); 5777 goto exit; 5778 case QLA8XXX_BAD_VALUE: 5779 qla83xx_idc_unlock(base_vha, 0); 5780 msleep(1000); 5781 qla83xx_idc_lock(base_vha, 0); 5782 break; 5783 default: 5784 ql_log(ql_log_warn, base_vha, 0xb071, 5785 "Unknown Device State: %x.\n", dev_state); 5786 qla83xx_idc_unlock(base_vha, 0); 5787 qla8xxx_dev_failed_handler(base_vha); 5788 rval = QLA_FUNCTION_FAILED; 5789 qla83xx_idc_lock(base_vha, 0); 5790 goto exit; 5791 } 5792 } 5793 5794 exit: 5795 return rval; 5796 } 5797 5798 void 5799 qla2x00_disable_board_on_pci_error(struct work_struct *work) 5800 { 5801 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 5802 board_disable); 5803 struct pci_dev *pdev = ha->pdev; 5804 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5805 5806 /* 5807 * if UNLOAD flag is already set, then continue unload, 5808 * where it was set first. 5809 */ 5810 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5811 return; 5812 5813 ql_log(ql_log_warn, base_vha, 0x015b, 5814 "Disabling adapter.\n"); 5815 5816 if (!atomic_read(&pdev->enable_cnt)) { 5817 ql_log(ql_log_info, base_vha, 0xfffc, 5818 "PCI device disabled, no action req for PCI error=%lx\n", 5819 base_vha->pci_flags); 5820 return; 5821 } 5822 5823 qla2x00_wait_for_sess_deletion(base_vha); 5824 5825 set_bit(UNLOADING, &base_vha->dpc_flags); 5826 5827 qla2x00_delete_all_vps(ha, base_vha); 5828 5829 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 5830 5831 qla2x00_dfs_remove(base_vha); 5832 5833 qla84xx_put_chip(base_vha); 5834 5835 if (base_vha->timer_active) 5836 qla2x00_stop_timer(base_vha); 5837 5838 base_vha->flags.online = 0; 5839 5840 qla2x00_destroy_deferred_work(ha); 5841 5842 /* 5843 * Do not try to stop beacon blink as it will issue a mailbox 5844 * command. 5845 */ 5846 qla2x00_free_sysfs_attr(base_vha, false); 5847 5848 fc_remove_host(base_vha->host); 5849 5850 scsi_remove_host(base_vha->host); 5851 5852 base_vha->flags.init_done = 0; 5853 qla25xx_delete_queues(base_vha); 5854 qla2x00_free_fcports(base_vha); 5855 qla2x00_free_irqs(base_vha); 5856 qla2x00_mem_free(ha); 5857 qla82xx_md_free(base_vha); 5858 qla2x00_free_queues(ha); 5859 5860 qla2x00_unmap_iobases(ha); 5861 5862 pci_release_selected_regions(ha->pdev, ha->bars); 5863 pci_disable_pcie_error_reporting(pdev); 5864 pci_disable_device(pdev); 5865 5866 /* 5867 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 5868 */ 5869 } 5870 5871 /************************************************************************** 5872 * qla2x00_do_dpc 5873 * This kernel thread is a task that is schedule by the interrupt handler 5874 * to perform the background processing for interrupts. 5875 * 5876 * Notes: 5877 * This task always run in the context of a kernel thread. It 5878 * is kick-off by the driver's detect code and starts up 5879 * up one per adapter. It immediately goes to sleep and waits for 5880 * some fibre event. When either the interrupt handler or 5881 * the timer routine detects a event it will one of the task 5882 * bits then wake us up. 5883 **************************************************************************/ 5884 static int 5885 qla2x00_do_dpc(void *data) 5886 { 5887 scsi_qla_host_t *base_vha; 5888 struct qla_hw_data *ha; 5889 uint32_t online; 5890 struct qla_qpair *qpair; 5891 5892 ha = (struct qla_hw_data *)data; 5893 base_vha = pci_get_drvdata(ha->pdev); 5894 5895 set_user_nice(current, MIN_NICE); 5896 5897 set_current_state(TASK_INTERRUPTIBLE); 5898 while (!kthread_should_stop()) { 5899 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 5900 "DPC handler sleeping.\n"); 5901 5902 schedule(); 5903 5904 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 5905 goto end_loop; 5906 5907 if (ha->flags.eeh_busy) { 5908 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 5909 "eeh_busy=%d.\n", ha->flags.eeh_busy); 5910 goto end_loop; 5911 } 5912 5913 ha->dpc_active = 1; 5914 5915 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 5916 "DPC handler waking up, dpc_flags=0x%lx.\n", 5917 base_vha->dpc_flags); 5918 5919 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 5920 break; 5921 5922 if (IS_P3P_TYPE(ha)) { 5923 if (IS_QLA8044(ha)) { 5924 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5925 &base_vha->dpc_flags)) { 5926 qla8044_idc_lock(ha); 5927 qla8044_wr_direct(base_vha, 5928 QLA8044_CRB_DEV_STATE_INDEX, 5929 QLA8XXX_DEV_FAILED); 5930 qla8044_idc_unlock(ha); 5931 ql_log(ql_log_info, base_vha, 0x4004, 5932 "HW State: FAILED.\n"); 5933 qla8044_device_state_handler(base_vha); 5934 continue; 5935 } 5936 5937 } else { 5938 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5939 &base_vha->dpc_flags)) { 5940 qla82xx_idc_lock(ha); 5941 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 5942 QLA8XXX_DEV_FAILED); 5943 qla82xx_idc_unlock(ha); 5944 ql_log(ql_log_info, base_vha, 0x0151, 5945 "HW State: FAILED.\n"); 5946 qla82xx_device_state_handler(base_vha); 5947 continue; 5948 } 5949 } 5950 5951 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 5952 &base_vha->dpc_flags)) { 5953 5954 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 5955 "FCoE context reset scheduled.\n"); 5956 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 5957 &base_vha->dpc_flags))) { 5958 if (qla82xx_fcoe_ctx_reset(base_vha)) { 5959 /* FCoE-ctx reset failed. 5960 * Escalate to chip-reset 5961 */ 5962 set_bit(ISP_ABORT_NEEDED, 5963 &base_vha->dpc_flags); 5964 } 5965 clear_bit(ABORT_ISP_ACTIVE, 5966 &base_vha->dpc_flags); 5967 } 5968 5969 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 5970 "FCoE context reset end.\n"); 5971 } 5972 } else if (IS_QLAFX00(ha)) { 5973 if (test_and_clear_bit(ISP_UNRECOVERABLE, 5974 &base_vha->dpc_flags)) { 5975 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 5976 "Firmware Reset Recovery\n"); 5977 if (qlafx00_reset_initialize(base_vha)) { 5978 /* Failed. Abort isp later. */ 5979 if (!test_bit(UNLOADING, 5980 &base_vha->dpc_flags)) { 5981 set_bit(ISP_UNRECOVERABLE, 5982 &base_vha->dpc_flags); 5983 ql_dbg(ql_dbg_dpc, base_vha, 5984 0x4021, 5985 "Reset Recovery Failed\n"); 5986 } 5987 } 5988 } 5989 5990 if (test_and_clear_bit(FX00_TARGET_SCAN, 5991 &base_vha->dpc_flags)) { 5992 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 5993 "ISPFx00 Target Scan scheduled\n"); 5994 if (qlafx00_rescan_isp(base_vha)) { 5995 if (!test_bit(UNLOADING, 5996 &base_vha->dpc_flags)) 5997 set_bit(ISP_UNRECOVERABLE, 5998 &base_vha->dpc_flags); 5999 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6000 "ISPFx00 Target Scan Failed\n"); 6001 } 6002 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6003 "ISPFx00 Target Scan End\n"); 6004 } 6005 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6006 &base_vha->dpc_flags)) { 6007 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6008 "ISPFx00 Host Info resend scheduled\n"); 6009 qlafx00_fx_disc(base_vha, 6010 &base_vha->hw->mr.fcport, 6011 FXDISC_REG_HOST_INFO); 6012 } 6013 } 6014 6015 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6016 &base_vha->dpc_flags) && 6017 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 6018 qla24xx_detect_sfp(base_vha); 6019 6020 if (ha->flags.detected_lr_sfp != 6021 ha->flags.using_lr_setting) 6022 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6023 } 6024 6025 if (test_and_clear_bit(ISP_ABORT_NEEDED, 6026 &base_vha->dpc_flags)) { 6027 6028 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6029 "ISP abort scheduled.\n"); 6030 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6031 &base_vha->dpc_flags))) { 6032 6033 if (ha->isp_ops->abort_isp(base_vha)) { 6034 /* failed. retry later */ 6035 set_bit(ISP_ABORT_NEEDED, 6036 &base_vha->dpc_flags); 6037 } 6038 clear_bit(ABORT_ISP_ACTIVE, 6039 &base_vha->dpc_flags); 6040 } 6041 6042 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6043 "ISP abort end.\n"); 6044 } 6045 6046 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6047 &base_vha->dpc_flags)) { 6048 qla2x00_update_fcports(base_vha); 6049 } 6050 6051 if (IS_QLAFX00(ha)) 6052 goto loop_resync_check; 6053 6054 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6055 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6056 "Quiescence mode scheduled.\n"); 6057 if (IS_P3P_TYPE(ha)) { 6058 if (IS_QLA82XX(ha)) 6059 qla82xx_device_state_handler(base_vha); 6060 if (IS_QLA8044(ha)) 6061 qla8044_device_state_handler(base_vha); 6062 clear_bit(ISP_QUIESCE_NEEDED, 6063 &base_vha->dpc_flags); 6064 if (!ha->flags.quiesce_owner) { 6065 qla2x00_perform_loop_resync(base_vha); 6066 if (IS_QLA82XX(ha)) { 6067 qla82xx_idc_lock(ha); 6068 qla82xx_clear_qsnt_ready( 6069 base_vha); 6070 qla82xx_idc_unlock(ha); 6071 } else if (IS_QLA8044(ha)) { 6072 qla8044_idc_lock(ha); 6073 qla8044_clear_qsnt_ready( 6074 base_vha); 6075 qla8044_idc_unlock(ha); 6076 } 6077 } 6078 } else { 6079 clear_bit(ISP_QUIESCE_NEEDED, 6080 &base_vha->dpc_flags); 6081 qla2x00_quiesce_io(base_vha); 6082 } 6083 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6084 "Quiescence mode end.\n"); 6085 } 6086 6087 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6088 &base_vha->dpc_flags) && 6089 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6090 6091 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6092 "Reset marker scheduled.\n"); 6093 qla2x00_rst_aen(base_vha); 6094 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6095 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6096 "Reset marker end.\n"); 6097 } 6098 6099 /* Retry each device up to login retry count */ 6100 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6101 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6102 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6103 6104 if (!base_vha->relogin_jif || 6105 time_after_eq(jiffies, base_vha->relogin_jif)) { 6106 base_vha->relogin_jif = jiffies + HZ; 6107 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6108 6109 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6110 "Relogin scheduled.\n"); 6111 qla24xx_post_relogin_work(base_vha); 6112 } 6113 } 6114 loop_resync_check: 6115 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6116 &base_vha->dpc_flags)) { 6117 6118 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6119 "Loop resync scheduled.\n"); 6120 6121 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6122 &base_vha->dpc_flags))) { 6123 6124 qla2x00_loop_resync(base_vha); 6125 6126 clear_bit(LOOP_RESYNC_ACTIVE, 6127 &base_vha->dpc_flags); 6128 } 6129 6130 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6131 "Loop resync end.\n"); 6132 } 6133 6134 if (IS_QLAFX00(ha)) 6135 goto intr_on_check; 6136 6137 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6138 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6139 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6140 qla2xxx_flash_npiv_conf(base_vha); 6141 } 6142 6143 intr_on_check: 6144 if (!ha->interrupts_on) 6145 ha->isp_ops->enable_intrs(ha); 6146 6147 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6148 &base_vha->dpc_flags)) { 6149 if (ha->beacon_blink_led == 1) 6150 ha->isp_ops->beacon_blink(base_vha); 6151 } 6152 6153 /* qpair online check */ 6154 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6155 &base_vha->dpc_flags)) { 6156 if (ha->flags.eeh_busy || 6157 ha->flags.pci_channel_io_perm_failure) 6158 online = 0; 6159 else 6160 online = 1; 6161 6162 mutex_lock(&ha->mq_lock); 6163 list_for_each_entry(qpair, &base_vha->qp_list, 6164 qp_list_elem) 6165 qpair->online = online; 6166 mutex_unlock(&ha->mq_lock); 6167 } 6168 6169 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) { 6170 ql_log(ql_log_info, base_vha, 0xffffff, 6171 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6172 ha->nvme_last_rptd_aen); 6173 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) { 6174 ql_log(ql_log_info, base_vha, 0xffffff, 6175 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6176 ha->nvme_last_rptd_aen); 6177 } 6178 } 6179 6180 if (!IS_QLAFX00(ha)) 6181 qla2x00_do_dpc_all_vps(base_vha); 6182 6183 ha->dpc_active = 0; 6184 end_loop: 6185 set_current_state(TASK_INTERRUPTIBLE); 6186 } /* End of while(1) */ 6187 __set_current_state(TASK_RUNNING); 6188 6189 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6190 "DPC handler exiting.\n"); 6191 6192 /* 6193 * Make sure that nobody tries to wake us up again. 6194 */ 6195 ha->dpc_active = 0; 6196 6197 /* Cleanup any residual CTX SRBs. */ 6198 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6199 6200 return 0; 6201 } 6202 6203 void 6204 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6205 { 6206 struct qla_hw_data *ha = vha->hw; 6207 struct task_struct *t = ha->dpc_thread; 6208 6209 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6210 wake_up_process(t); 6211 } 6212 6213 /* 6214 * qla2x00_rst_aen 6215 * Processes asynchronous reset. 6216 * 6217 * Input: 6218 * ha = adapter block pointer. 6219 */ 6220 static void 6221 qla2x00_rst_aen(scsi_qla_host_t *vha) 6222 { 6223 if (vha->flags.online && !vha->flags.reset_active && 6224 !atomic_read(&vha->loop_down_timer) && 6225 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6226 do { 6227 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6228 6229 /* 6230 * Issue marker command only when we are going to start 6231 * the I/O. 6232 */ 6233 vha->marker_needed = 1; 6234 } while (!atomic_read(&vha->loop_down_timer) && 6235 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6236 } 6237 } 6238 6239 /************************************************************************** 6240 * qla2x00_timer 6241 * 6242 * Description: 6243 * One second timer 6244 * 6245 * Context: Interrupt 6246 ***************************************************************************/ 6247 void 6248 qla2x00_timer(struct timer_list *t) 6249 { 6250 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6251 unsigned long cpu_flags = 0; 6252 int start_dpc = 0; 6253 int index; 6254 srb_t *sp; 6255 uint16_t w; 6256 struct qla_hw_data *ha = vha->hw; 6257 struct req_que *req; 6258 6259 if (ha->flags.eeh_busy) { 6260 ql_dbg(ql_dbg_timer, vha, 0x6000, 6261 "EEH = %d, restarting timer.\n", 6262 ha->flags.eeh_busy); 6263 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6264 return; 6265 } 6266 6267 /* 6268 * Hardware read to raise pending EEH errors during mailbox waits. If 6269 * the read returns -1 then disable the board. 6270 */ 6271 if (!pci_channel_offline(ha->pdev)) { 6272 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6273 qla2x00_check_reg16_for_disconnect(vha, w); 6274 } 6275 6276 /* Make sure qla82xx_watchdog is run only for physical port */ 6277 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6278 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6279 start_dpc++; 6280 if (IS_QLA82XX(ha)) 6281 qla82xx_watchdog(vha); 6282 else if (IS_QLA8044(ha)) 6283 qla8044_watchdog(vha); 6284 } 6285 6286 if (!vha->vp_idx && IS_QLAFX00(ha)) 6287 qlafx00_timer_routine(vha); 6288 6289 /* Loop down handler. */ 6290 if (atomic_read(&vha->loop_down_timer) > 0 && 6291 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6292 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6293 && vha->flags.online) { 6294 6295 if (atomic_read(&vha->loop_down_timer) == 6296 vha->loop_down_abort_time) { 6297 6298 ql_log(ql_log_info, vha, 0x6008, 6299 "Loop down - aborting the queues before time expires.\n"); 6300 6301 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6302 atomic_set(&vha->loop_state, LOOP_DEAD); 6303 6304 /* 6305 * Schedule an ISP abort to return any FCP2-device 6306 * commands. 6307 */ 6308 /* NPIV - scan physical port only */ 6309 if (!vha->vp_idx) { 6310 spin_lock_irqsave(&ha->hardware_lock, 6311 cpu_flags); 6312 req = ha->req_q_map[0]; 6313 for (index = 1; 6314 index < req->num_outstanding_cmds; 6315 index++) { 6316 fc_port_t *sfcp; 6317 6318 sp = req->outstanding_cmds[index]; 6319 if (!sp) 6320 continue; 6321 if (sp->cmd_type != TYPE_SRB) 6322 continue; 6323 if (sp->type != SRB_SCSI_CMD) 6324 continue; 6325 sfcp = sp->fcport; 6326 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6327 continue; 6328 6329 if (IS_QLA82XX(ha)) 6330 set_bit(FCOE_CTX_RESET_NEEDED, 6331 &vha->dpc_flags); 6332 else 6333 set_bit(ISP_ABORT_NEEDED, 6334 &vha->dpc_flags); 6335 break; 6336 } 6337 spin_unlock_irqrestore(&ha->hardware_lock, 6338 cpu_flags); 6339 } 6340 start_dpc++; 6341 } 6342 6343 /* if the loop has been down for 4 minutes, reinit adapter */ 6344 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6345 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6346 ql_log(ql_log_warn, vha, 0x6009, 6347 "Loop down - aborting ISP.\n"); 6348 6349 if (IS_QLA82XX(ha)) 6350 set_bit(FCOE_CTX_RESET_NEEDED, 6351 &vha->dpc_flags); 6352 else 6353 set_bit(ISP_ABORT_NEEDED, 6354 &vha->dpc_flags); 6355 } 6356 } 6357 ql_dbg(ql_dbg_timer, vha, 0x600a, 6358 "Loop down - seconds remaining %d.\n", 6359 atomic_read(&vha->loop_down_timer)); 6360 } 6361 /* Check if beacon LED needs to be blinked for physical host only */ 6362 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6363 /* There is no beacon_blink function for ISP82xx */ 6364 if (!IS_P3P_TYPE(ha)) { 6365 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6366 start_dpc++; 6367 } 6368 } 6369 6370 /* Process any deferred work. */ 6371 if (!list_empty(&vha->work_list)) { 6372 unsigned long flags; 6373 bool q = false; 6374 6375 spin_lock_irqsave(&vha->work_lock, flags); 6376 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6377 q = true; 6378 spin_unlock_irqrestore(&vha->work_lock, flags); 6379 if (q) 6380 queue_work(vha->hw->wq, &vha->iocb_work); 6381 } 6382 6383 /* 6384 * FC-NVME 6385 * see if the active AEN count has changed from what was last reported. 6386 */ 6387 if (!vha->vp_idx && 6388 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen && 6389 ha->zio_mode == QLA_ZIO_MODE_6) { 6390 ql_log(ql_log_info, vha, 0x3002, 6391 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6392 ha->nvme_last_rptd_aen); 6393 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6394 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6395 start_dpc++; 6396 } 6397 6398 /* Schedule the DPC routine if needed */ 6399 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6400 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6401 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6402 start_dpc || 6403 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6404 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6405 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6406 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6407 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6408 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6409 ql_dbg(ql_dbg_timer, vha, 0x600b, 6410 "isp_abort_needed=%d loop_resync_needed=%d " 6411 "fcport_update_needed=%d start_dpc=%d " 6412 "reset_marker_needed=%d", 6413 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6414 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6415 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6416 start_dpc, 6417 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6418 ql_dbg(ql_dbg_timer, vha, 0x600c, 6419 "beacon_blink_needed=%d isp_unrecoverable=%d " 6420 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6421 "relogin_needed=%d.\n", 6422 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6423 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6424 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6425 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6426 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6427 qla2xxx_wake_dpc(vha); 6428 } 6429 6430 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6431 } 6432 6433 /* Firmware interface routines. */ 6434 6435 #define FW_BLOBS 11 6436 #define FW_ISP21XX 0 6437 #define FW_ISP22XX 1 6438 #define FW_ISP2300 2 6439 #define FW_ISP2322 3 6440 #define FW_ISP24XX 4 6441 #define FW_ISP25XX 5 6442 #define FW_ISP81XX 6 6443 #define FW_ISP82XX 7 6444 #define FW_ISP2031 8 6445 #define FW_ISP8031 9 6446 #define FW_ISP27XX 10 6447 6448 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6449 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6450 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6451 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6452 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6453 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6454 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6455 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6456 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6457 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6458 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6459 6460 6461 static DEFINE_MUTEX(qla_fw_lock); 6462 6463 static struct fw_blob qla_fw_blobs[FW_BLOBS] = { 6464 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6465 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6466 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6467 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6468 { .name = FW_FILE_ISP24XX, }, 6469 { .name = FW_FILE_ISP25XX, }, 6470 { .name = FW_FILE_ISP81XX, }, 6471 { .name = FW_FILE_ISP82XX, }, 6472 { .name = FW_FILE_ISP2031, }, 6473 { .name = FW_FILE_ISP8031, }, 6474 { .name = FW_FILE_ISP27XX, }, 6475 }; 6476 6477 struct fw_blob * 6478 qla2x00_request_firmware(scsi_qla_host_t *vha) 6479 { 6480 struct qla_hw_data *ha = vha->hw; 6481 struct fw_blob *blob; 6482 6483 if (IS_QLA2100(ha)) { 6484 blob = &qla_fw_blobs[FW_ISP21XX]; 6485 } else if (IS_QLA2200(ha)) { 6486 blob = &qla_fw_blobs[FW_ISP22XX]; 6487 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6488 blob = &qla_fw_blobs[FW_ISP2300]; 6489 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6490 blob = &qla_fw_blobs[FW_ISP2322]; 6491 } else if (IS_QLA24XX_TYPE(ha)) { 6492 blob = &qla_fw_blobs[FW_ISP24XX]; 6493 } else if (IS_QLA25XX(ha)) { 6494 blob = &qla_fw_blobs[FW_ISP25XX]; 6495 } else if (IS_QLA81XX(ha)) { 6496 blob = &qla_fw_blobs[FW_ISP81XX]; 6497 } else if (IS_QLA82XX(ha)) { 6498 blob = &qla_fw_blobs[FW_ISP82XX]; 6499 } else if (IS_QLA2031(ha)) { 6500 blob = &qla_fw_blobs[FW_ISP2031]; 6501 } else if (IS_QLA8031(ha)) { 6502 blob = &qla_fw_blobs[FW_ISP8031]; 6503 } else if (IS_QLA27XX(ha)) { 6504 blob = &qla_fw_blobs[FW_ISP27XX]; 6505 } else { 6506 return NULL; 6507 } 6508 6509 mutex_lock(&qla_fw_lock); 6510 if (blob->fw) 6511 goto out; 6512 6513 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6514 ql_log(ql_log_warn, vha, 0x0063, 6515 "Failed to load firmware image (%s).\n", blob->name); 6516 blob->fw = NULL; 6517 blob = NULL; 6518 goto out; 6519 } 6520 6521 out: 6522 mutex_unlock(&qla_fw_lock); 6523 return blob; 6524 } 6525 6526 static void 6527 qla2x00_release_firmware(void) 6528 { 6529 int idx; 6530 6531 mutex_lock(&qla_fw_lock); 6532 for (idx = 0; idx < FW_BLOBS; idx++) 6533 release_firmware(qla_fw_blobs[idx].fw); 6534 mutex_unlock(&qla_fw_lock); 6535 } 6536 6537 static pci_ers_result_t 6538 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6539 { 6540 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6541 struct qla_hw_data *ha = vha->hw; 6542 6543 ql_dbg(ql_dbg_aer, vha, 0x9000, 6544 "PCI error detected, state %x.\n", state); 6545 6546 if (!atomic_read(&pdev->enable_cnt)) { 6547 ql_log(ql_log_info, vha, 0xffff, 6548 "PCI device is disabled,state %x\n", state); 6549 return PCI_ERS_RESULT_NEED_RESET; 6550 } 6551 6552 switch (state) { 6553 case pci_channel_io_normal: 6554 ha->flags.eeh_busy = 0; 6555 if (ql2xmqsupport || ql2xnvmeenable) { 6556 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6557 qla2xxx_wake_dpc(vha); 6558 } 6559 return PCI_ERS_RESULT_CAN_RECOVER; 6560 case pci_channel_io_frozen: 6561 ha->flags.eeh_busy = 1; 6562 /* For ISP82XX complete any pending mailbox cmd */ 6563 if (IS_QLA82XX(ha)) { 6564 ha->flags.isp82xx_fw_hung = 1; 6565 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); 6566 qla82xx_clear_pending_mbx(vha); 6567 } 6568 qla2x00_free_irqs(vha); 6569 pci_disable_device(pdev); 6570 /* Return back all IOs */ 6571 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 6572 if (ql2xmqsupport || ql2xnvmeenable) { 6573 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6574 qla2xxx_wake_dpc(vha); 6575 } 6576 return PCI_ERS_RESULT_NEED_RESET; 6577 case pci_channel_io_perm_failure: 6578 ha->flags.pci_channel_io_perm_failure = 1; 6579 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6580 if (ql2xmqsupport || ql2xnvmeenable) { 6581 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6582 qla2xxx_wake_dpc(vha); 6583 } 6584 return PCI_ERS_RESULT_DISCONNECT; 6585 } 6586 return PCI_ERS_RESULT_NEED_RESET; 6587 } 6588 6589 static pci_ers_result_t 6590 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6591 { 6592 int risc_paused = 0; 6593 uint32_t stat; 6594 unsigned long flags; 6595 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6596 struct qla_hw_data *ha = base_vha->hw; 6597 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6598 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6599 6600 if (IS_QLA82XX(ha)) 6601 return PCI_ERS_RESULT_RECOVERED; 6602 6603 spin_lock_irqsave(&ha->hardware_lock, flags); 6604 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6605 stat = RD_REG_DWORD(®->hccr); 6606 if (stat & HCCR_RISC_PAUSE) 6607 risc_paused = 1; 6608 } else if (IS_QLA23XX(ha)) { 6609 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6610 if (stat & HSR_RISC_PAUSED) 6611 risc_paused = 1; 6612 } else if (IS_FWI2_CAPABLE(ha)) { 6613 stat = RD_REG_DWORD(®24->host_status); 6614 if (stat & HSRX_RISC_PAUSED) 6615 risc_paused = 1; 6616 } 6617 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6618 6619 if (risc_paused) { 6620 ql_log(ql_log_info, base_vha, 0x9003, 6621 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6622 ha->isp_ops->fw_dump(base_vha, 0); 6623 6624 return PCI_ERS_RESULT_NEED_RESET; 6625 } else 6626 return PCI_ERS_RESULT_RECOVERED; 6627 } 6628 6629 static uint32_t 6630 qla82xx_error_recovery(scsi_qla_host_t *base_vha) 6631 { 6632 uint32_t rval = QLA_FUNCTION_FAILED; 6633 uint32_t drv_active = 0; 6634 struct qla_hw_data *ha = base_vha->hw; 6635 int fn; 6636 struct pci_dev *other_pdev = NULL; 6637 6638 ql_dbg(ql_dbg_aer, base_vha, 0x9006, 6639 "Entered %s.\n", __func__); 6640 6641 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6642 6643 if (base_vha->flags.online) { 6644 /* Abort all outstanding commands, 6645 * so as to be requeued later */ 6646 qla2x00_abort_isp_cleanup(base_vha); 6647 } 6648 6649 6650 fn = PCI_FUNC(ha->pdev->devfn); 6651 while (fn > 0) { 6652 fn--; 6653 ql_dbg(ql_dbg_aer, base_vha, 0x9007, 6654 "Finding pci device at function = 0x%x.\n", fn); 6655 other_pdev = 6656 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), 6657 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), 6658 fn)); 6659 6660 if (!other_pdev) 6661 continue; 6662 if (atomic_read(&other_pdev->enable_cnt)) { 6663 ql_dbg(ql_dbg_aer, base_vha, 0x9008, 6664 "Found PCI func available and enable at 0x%x.\n", 6665 fn); 6666 pci_dev_put(other_pdev); 6667 break; 6668 } 6669 pci_dev_put(other_pdev); 6670 } 6671 6672 if (!fn) { 6673 /* Reset owner */ 6674 ql_dbg(ql_dbg_aer, base_vha, 0x9009, 6675 "This devfn is reset owner = 0x%x.\n", 6676 ha->pdev->devfn); 6677 qla82xx_idc_lock(ha); 6678 6679 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6680 QLA8XXX_DEV_INITIALIZING); 6681 6682 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, 6683 QLA82XX_IDC_VERSION); 6684 6685 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 6686 ql_dbg(ql_dbg_aer, base_vha, 0x900a, 6687 "drv_active = 0x%x.\n", drv_active); 6688 6689 qla82xx_idc_unlock(ha); 6690 /* Reset if device is not already reset 6691 * drv_active would be 0 if a reset has already been done 6692 */ 6693 if (drv_active) 6694 rval = qla82xx_start_firmware(base_vha); 6695 else 6696 rval = QLA_SUCCESS; 6697 qla82xx_idc_lock(ha); 6698 6699 if (rval != QLA_SUCCESS) { 6700 ql_log(ql_log_info, base_vha, 0x900b, 6701 "HW State: FAILED.\n"); 6702 qla82xx_clear_drv_active(ha); 6703 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6704 QLA8XXX_DEV_FAILED); 6705 } else { 6706 ql_log(ql_log_info, base_vha, 0x900c, 6707 "HW State: READY.\n"); 6708 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6709 QLA8XXX_DEV_READY); 6710 qla82xx_idc_unlock(ha); 6711 ha->flags.isp82xx_fw_hung = 0; 6712 rval = qla82xx_restart_isp(base_vha); 6713 qla82xx_idc_lock(ha); 6714 /* Clear driver state register */ 6715 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); 6716 qla82xx_set_drv_active(base_vha); 6717 } 6718 qla82xx_idc_unlock(ha); 6719 } else { 6720 ql_dbg(ql_dbg_aer, base_vha, 0x900d, 6721 "This devfn is not reset owner = 0x%x.\n", 6722 ha->pdev->devfn); 6723 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == 6724 QLA8XXX_DEV_READY)) { 6725 ha->flags.isp82xx_fw_hung = 0; 6726 rval = qla82xx_restart_isp(base_vha); 6727 qla82xx_idc_lock(ha); 6728 qla82xx_set_drv_active(base_vha); 6729 qla82xx_idc_unlock(ha); 6730 } 6731 } 6732 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6733 6734 return rval; 6735 } 6736 6737 static pci_ers_result_t 6738 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6739 { 6740 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6741 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6742 struct qla_hw_data *ha = base_vha->hw; 6743 struct rsp_que *rsp; 6744 int rc, retries = 10; 6745 6746 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6747 "Slot Reset.\n"); 6748 6749 /* Workaround: qla2xxx driver which access hardware earlier 6750 * needs error state to be pci_channel_io_online. 6751 * Otherwise mailbox command timesout. 6752 */ 6753 pdev->error_state = pci_channel_io_normal; 6754 6755 pci_restore_state(pdev); 6756 6757 /* pci_restore_state() clears the saved_state flag of the device 6758 * save restored state which resets saved_state flag 6759 */ 6760 pci_save_state(pdev); 6761 6762 if (ha->mem_only) 6763 rc = pci_enable_device_mem(pdev); 6764 else 6765 rc = pci_enable_device(pdev); 6766 6767 if (rc) { 6768 ql_log(ql_log_warn, base_vha, 0x9005, 6769 "Can't re-enable PCI device after reset.\n"); 6770 goto exit_slot_reset; 6771 } 6772 6773 rsp = ha->rsp_q_map[0]; 6774 if (qla2x00_request_irqs(ha, rsp)) 6775 goto exit_slot_reset; 6776 6777 if (ha->isp_ops->pci_config(base_vha)) 6778 goto exit_slot_reset; 6779 6780 if (IS_QLA82XX(ha)) { 6781 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { 6782 ret = PCI_ERS_RESULT_RECOVERED; 6783 goto exit_slot_reset; 6784 } else 6785 goto exit_slot_reset; 6786 } 6787 6788 while (ha->flags.mbox_busy && retries--) 6789 msleep(1000); 6790 6791 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6792 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 6793 ret = PCI_ERS_RESULT_RECOVERED; 6794 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 6795 6796 6797 exit_slot_reset: 6798 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 6799 "slot_reset return %x.\n", ret); 6800 6801 return ret; 6802 } 6803 6804 static void 6805 qla2xxx_pci_resume(struct pci_dev *pdev) 6806 { 6807 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6808 struct qla_hw_data *ha = base_vha->hw; 6809 int ret; 6810 6811 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 6812 "pci_resume.\n"); 6813 6814 ret = qla2x00_wait_for_hba_online(base_vha); 6815 if (ret != QLA_SUCCESS) { 6816 ql_log(ql_log_fatal, base_vha, 0x9002, 6817 "The device failed to resume I/O from slot/link_reset.\n"); 6818 } 6819 6820 pci_cleanup_aer_uncorrect_error_status(pdev); 6821 6822 ha->flags.eeh_busy = 0; 6823 } 6824 6825 static int qla2xxx_map_queues(struct Scsi_Host *shost) 6826 { 6827 int rc; 6828 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 6829 6830 if (USER_CTRL_IRQ(vha->hw)) 6831 rc = blk_mq_map_queues(&shost->tag_set); 6832 else 6833 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0); 6834 return rc; 6835 } 6836 6837 static const struct pci_error_handlers qla2xxx_err_handler = { 6838 .error_detected = qla2xxx_pci_error_detected, 6839 .mmio_enabled = qla2xxx_pci_mmio_enabled, 6840 .slot_reset = qla2xxx_pci_slot_reset, 6841 .resume = qla2xxx_pci_resume, 6842 }; 6843 6844 static struct pci_device_id qla2xxx_pci_tbl[] = { 6845 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 6846 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 6847 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 6848 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 6849 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 6850 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 6851 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 6852 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 6853 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 6854 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 6855 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 6856 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 6857 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 6858 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 6859 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 6860 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 6861 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 6862 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 6863 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 6864 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 6865 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 6866 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 6867 { 0 }, 6868 }; 6869 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 6870 6871 static struct pci_driver qla2xxx_pci_driver = { 6872 .name = QLA2XXX_DRIVER_NAME, 6873 .driver = { 6874 .owner = THIS_MODULE, 6875 }, 6876 .id_table = qla2xxx_pci_tbl, 6877 .probe = qla2x00_probe_one, 6878 .remove = qla2x00_remove_one, 6879 .shutdown = qla2x00_shutdown, 6880 .err_handler = &qla2xxx_err_handler, 6881 }; 6882 6883 static const struct file_operations apidev_fops = { 6884 .owner = THIS_MODULE, 6885 .llseek = noop_llseek, 6886 }; 6887 6888 /** 6889 * qla2x00_module_init - Module initialization. 6890 **/ 6891 static int __init 6892 qla2x00_module_init(void) 6893 { 6894 int ret = 0; 6895 6896 /* Allocate cache for SRBs. */ 6897 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 6898 SLAB_HWCACHE_ALIGN, NULL); 6899 if (srb_cachep == NULL) { 6900 ql_log(ql_log_fatal, NULL, 0x0001, 6901 "Unable to allocate SRB cache...Failing load!.\n"); 6902 return -ENOMEM; 6903 } 6904 6905 /* Initialize target kmem_cache and mem_pools */ 6906 ret = qlt_init(); 6907 if (ret < 0) { 6908 kmem_cache_destroy(srb_cachep); 6909 return ret; 6910 } else if (ret > 0) { 6911 /* 6912 * If initiator mode is explictly disabled by qlt_init(), 6913 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 6914 * performing scsi_scan_target() during LOOP UP event. 6915 */ 6916 qla2xxx_transport_functions.disable_target_scan = 1; 6917 qla2xxx_transport_vport_functions.disable_target_scan = 1; 6918 } 6919 6920 /* Derive version string. */ 6921 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 6922 if (ql2xextended_error_logging) 6923 strcat(qla2x00_version_str, "-debug"); 6924 if (ql2xextended_error_logging == 1) 6925 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 6926 6927 qla2xxx_transport_template = 6928 fc_attach_transport(&qla2xxx_transport_functions); 6929 if (!qla2xxx_transport_template) { 6930 kmem_cache_destroy(srb_cachep); 6931 ql_log(ql_log_fatal, NULL, 0x0002, 6932 "fc_attach_transport failed...Failing load!.\n"); 6933 qlt_exit(); 6934 return -ENODEV; 6935 } 6936 6937 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 6938 if (apidev_major < 0) { 6939 ql_log(ql_log_fatal, NULL, 0x0003, 6940 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 6941 } 6942 6943 qla2xxx_transport_vport_template = 6944 fc_attach_transport(&qla2xxx_transport_vport_functions); 6945 if (!qla2xxx_transport_vport_template) { 6946 kmem_cache_destroy(srb_cachep); 6947 qlt_exit(); 6948 fc_release_transport(qla2xxx_transport_template); 6949 ql_log(ql_log_fatal, NULL, 0x0004, 6950 "fc_attach_transport vport failed...Failing load!.\n"); 6951 return -ENODEV; 6952 } 6953 ql_log(ql_log_info, NULL, 0x0005, 6954 "QLogic Fibre Channel HBA Driver: %s.\n", 6955 qla2x00_version_str); 6956 ret = pci_register_driver(&qla2xxx_pci_driver); 6957 if (ret) { 6958 kmem_cache_destroy(srb_cachep); 6959 qlt_exit(); 6960 fc_release_transport(qla2xxx_transport_template); 6961 fc_release_transport(qla2xxx_transport_vport_template); 6962 ql_log(ql_log_fatal, NULL, 0x0006, 6963 "pci_register_driver failed...ret=%d Failing load!.\n", 6964 ret); 6965 } 6966 return ret; 6967 } 6968 6969 /** 6970 * qla2x00_module_exit - Module cleanup. 6971 **/ 6972 static void __exit 6973 qla2x00_module_exit(void) 6974 { 6975 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 6976 pci_unregister_driver(&qla2xxx_pci_driver); 6977 qla2x00_release_firmware(); 6978 kmem_cache_destroy(srb_cachep); 6979 qlt_exit(); 6980 if (ctx_cachep) 6981 kmem_cache_destroy(ctx_cachep); 6982 fc_release_transport(qla2xxx_transport_template); 6983 fc_release_transport(qla2xxx_transport_vport_template); 6984 } 6985 6986 module_init(qla2x00_module_init); 6987 module_exit(qla2x00_module_exit); 6988 6989 MODULE_AUTHOR("QLogic Corporation"); 6990 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 6991 MODULE_LICENSE("GPL"); 6992 MODULE_VERSION(QLA2XXX_VERSION); 6993 MODULE_FIRMWARE(FW_FILE_ISP21XX); 6994 MODULE_FIRMWARE(FW_FILE_ISP22XX); 6995 MODULE_FIRMWARE(FW_FILE_ISP2300); 6996 MODULE_FIRMWARE(FW_FILE_ISP2322); 6997 MODULE_FIRMWARE(FW_FILE_ISP24XX); 6998 MODULE_FIRMWARE(FW_FILE_ISP25XX); 6999