1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 #include <linux/trace_events.h> 19 #include <linux/trace.h> 20 21 #include <scsi/scsi_tcq.h> 22 #include <scsi/scsicam.h> 23 #include <scsi/scsi_transport.h> 24 #include <scsi/scsi_transport_fc.h> 25 26 #include "qla_target.h" 27 28 /* 29 * Driver version 30 */ 31 char qla2x00_version_str[40]; 32 33 static int apidev_major; 34 35 /* 36 * SRB allocation cache 37 */ 38 struct kmem_cache *srb_cachep; 39 40 static struct trace_array *qla_trc_array; 41 42 int ql2xfulldump_on_mpifail; 43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 45 "Set this to take full dump on MPI hang."); 46 47 int ql2xenforce_iocb_limit = 1; 48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 49 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 50 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 51 52 /* 53 * CT6 CTX allocation cache 54 */ 55 static struct kmem_cache *ctx_cachep; 56 /* 57 * error level for logging 58 */ 59 uint ql_errlev = 0x8001; 60 61 int ql2xsecenable; 62 module_param(ql2xsecenable, int, S_IRUGO); 63 MODULE_PARM_DESC(ql2xsecenable, 64 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 65 66 static int ql2xenableclass2; 67 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 68 MODULE_PARM_DESC(ql2xenableclass2, 69 "Specify if Class 2 operations are supported from the very " 70 "beginning. Default is 0 - class 2 not supported."); 71 72 73 int ql2xlogintimeout = 20; 74 module_param(ql2xlogintimeout, int, S_IRUGO); 75 MODULE_PARM_DESC(ql2xlogintimeout, 76 "Login timeout value in seconds."); 77 78 int qlport_down_retry; 79 module_param(qlport_down_retry, int, S_IRUGO); 80 MODULE_PARM_DESC(qlport_down_retry, 81 "Maximum number of command retries to a port that returns " 82 "a PORT-DOWN status."); 83 84 int ql2xplogiabsentdevice; 85 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 86 MODULE_PARM_DESC(ql2xplogiabsentdevice, 87 "Option to enable PLOGI to devices that are not present after " 88 "a Fabric scan. This is needed for several broken switches. " 89 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 90 91 int ql2xloginretrycount; 92 module_param(ql2xloginretrycount, int, S_IRUGO); 93 MODULE_PARM_DESC(ql2xloginretrycount, 94 "Specify an alternate value for the NVRAM login retry count."); 95 96 int ql2xallocfwdump = 1; 97 module_param(ql2xallocfwdump, int, S_IRUGO); 98 MODULE_PARM_DESC(ql2xallocfwdump, 99 "Option to enable allocation of memory for a firmware dump " 100 "during HBA initialization. Memory allocation requirements " 101 "vary by ISP type. Default is 1 - allocate memory."); 102 103 int ql2xextended_error_logging; 104 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 105 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 106 MODULE_PARM_DESC(ql2xextended_error_logging, 107 "Option to enable extended error logging,\n" 108 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 109 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 110 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 111 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 112 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 113 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 114 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 115 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 116 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 117 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 118 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 119 "\t\t0x1e400000 - Preferred value for capturing essential " 120 "debug information (equivalent to old " 121 "ql2xextended_error_logging=1).\n" 122 "\t\tDo LOGICAL OR of the value to enable more than one level"); 123 124 int ql2xextended_error_logging_ktrace = 1; 125 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR); 126 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace, 127 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n"); 128 129 int ql2xshiftctondsd = 6; 130 module_param(ql2xshiftctondsd, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xshiftctondsd, 132 "Set to control shifting of command type processing " 133 "based on total number of SG elements."); 134 135 int ql2xfdmienable = 1; 136 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 137 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 138 MODULE_PARM_DESC(ql2xfdmienable, 139 "Enables FDMI registrations. " 140 "0 - no FDMI registrations. " 141 "1 - provide FDMI registrations (default)."); 142 143 #define MAX_Q_DEPTH 64 144 static int ql2xmaxqdepth = MAX_Q_DEPTH; 145 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 146 MODULE_PARM_DESC(ql2xmaxqdepth, 147 "Maximum queue depth to set for each LUN. " 148 "Default is 64."); 149 150 int ql2xenabledif = 2; 151 module_param(ql2xenabledif, int, S_IRUGO); 152 MODULE_PARM_DESC(ql2xenabledif, 153 " Enable T10-CRC-DIF:\n" 154 " Default is 2.\n" 155 " 0 -- No DIF Support\n" 156 " 1 -- Enable DIF for all types\n" 157 " 2 -- Enable DIF for all types, except Type 0.\n"); 158 159 #if (IS_ENABLED(CONFIG_NVME_FC)) 160 int ql2xnvmeenable = 1; 161 #else 162 int ql2xnvmeenable; 163 #endif 164 module_param(ql2xnvmeenable, int, 0644); 165 MODULE_PARM_DESC(ql2xnvmeenable, 166 "Enables NVME support. " 167 "0 - no NVMe. Default is Y"); 168 169 int ql2xenablehba_err_chk = 2; 170 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 171 MODULE_PARM_DESC(ql2xenablehba_err_chk, 172 " Enable T10-CRC-DIF Error isolation by HBA:\n" 173 " Default is 2.\n" 174 " 0 -- Error isolation disabled\n" 175 " 1 -- Error isolation enabled only for DIX Type 0\n" 176 " 2 -- Error isolation enabled for all Types\n"); 177 178 int ql2xiidmaenable = 1; 179 module_param(ql2xiidmaenable, int, S_IRUGO); 180 MODULE_PARM_DESC(ql2xiidmaenable, 181 "Enables iIDMA settings " 182 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 183 184 int ql2xmqsupport = 1; 185 module_param(ql2xmqsupport, int, S_IRUGO); 186 MODULE_PARM_DESC(ql2xmqsupport, 187 "Enable on demand multiple queue pairs support " 188 "Default is 1 for supported. " 189 "Set it to 0 to turn off mq qpair support."); 190 191 int ql2xfwloadbin; 192 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 193 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 194 MODULE_PARM_DESC(ql2xfwloadbin, 195 "Option to specify location from which to load ISP firmware:.\n" 196 " 2 -- load firmware via the request_firmware() (hotplug).\n" 197 " interface.\n" 198 " 1 -- load firmware from flash.\n" 199 " 0 -- use default semantics.\n"); 200 201 int ql2xetsenable; 202 module_param(ql2xetsenable, int, S_IRUGO); 203 MODULE_PARM_DESC(ql2xetsenable, 204 "Enables firmware ETS burst." 205 "Default is 0 - skip ETS enablement."); 206 207 int ql2xdbwr = 1; 208 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 209 MODULE_PARM_DESC(ql2xdbwr, 210 "Option to specify scheme for request queue posting.\n" 211 " 0 -- Regular doorbell.\n" 212 " 1 -- CAMRAM doorbell (faster).\n"); 213 214 int ql2xgffidenable; 215 module_param(ql2xgffidenable, int, S_IRUGO); 216 MODULE_PARM_DESC(ql2xgffidenable, 217 "Enables GFF_ID checks of port type. " 218 "Default is 0 - Do not use GFF_ID information."); 219 220 int ql2xasynctmfenable = 1; 221 module_param(ql2xasynctmfenable, int, S_IRUGO); 222 MODULE_PARM_DESC(ql2xasynctmfenable, 223 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 224 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 225 226 int ql2xdontresethba; 227 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 228 MODULE_PARM_DESC(ql2xdontresethba, 229 "Option to specify reset behaviour.\n" 230 " 0 (Default) -- Reset on failure.\n" 231 " 1 -- Do not reset on failure.\n"); 232 233 uint64_t ql2xmaxlun = MAX_LUNS; 234 module_param(ql2xmaxlun, ullong, S_IRUGO); 235 MODULE_PARM_DESC(ql2xmaxlun, 236 "Defines the maximum LU number to register with the SCSI " 237 "midlayer. Default is 65535."); 238 239 int ql2xmdcapmask = 0x1F; 240 module_param(ql2xmdcapmask, int, S_IRUGO); 241 MODULE_PARM_DESC(ql2xmdcapmask, 242 "Set the Minidump driver capture mask level. " 243 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 244 245 int ql2xmdenable = 1; 246 module_param(ql2xmdenable, int, S_IRUGO); 247 MODULE_PARM_DESC(ql2xmdenable, 248 "Enable/disable MiniDump. " 249 "0 - MiniDump disabled. " 250 "1 (Default) - MiniDump enabled."); 251 252 int ql2xexlogins; 253 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 254 MODULE_PARM_DESC(ql2xexlogins, 255 "Number of extended Logins. " 256 "0 (Default)- Disabled."); 257 258 int ql2xexchoffld = 1024; 259 module_param(ql2xexchoffld, uint, 0644); 260 MODULE_PARM_DESC(ql2xexchoffld, 261 "Number of target exchanges."); 262 263 int ql2xiniexchg = 1024; 264 module_param(ql2xiniexchg, uint, 0644); 265 MODULE_PARM_DESC(ql2xiniexchg, 266 "Number of initiator exchanges."); 267 268 int ql2xfwholdabts; 269 module_param(ql2xfwholdabts, int, S_IRUGO); 270 MODULE_PARM_DESC(ql2xfwholdabts, 271 "Allow FW to hold status IOCB until ABTS rsp received. " 272 "0 (Default) Do not set fw option. " 273 "1 - Set fw option to hold ABTS."); 274 275 int ql2xmvasynctoatio = 1; 276 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 277 MODULE_PARM_DESC(ql2xmvasynctoatio, 278 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 279 "0 (Default). Do not move IOCBs" 280 "1 - Move IOCBs."); 281 282 int ql2xautodetectsfp = 1; 283 module_param(ql2xautodetectsfp, int, 0444); 284 MODULE_PARM_DESC(ql2xautodetectsfp, 285 "Detect SFP range and set appropriate distance.\n" 286 "1 (Default): Enable\n"); 287 288 int ql2xenablemsix = 1; 289 module_param(ql2xenablemsix, int, 0444); 290 MODULE_PARM_DESC(ql2xenablemsix, 291 "Set to enable MSI or MSI-X interrupt mechanism.\n" 292 " Default is 1, enable MSI-X interrupt mechanism.\n" 293 " 0 -- enable traditional pin-based mechanism.\n" 294 " 1 -- enable MSI-X interrupt mechanism.\n" 295 " 2 -- enable MSI interrupt mechanism.\n"); 296 297 int qla2xuseresexchforels; 298 module_param(qla2xuseresexchforels, int, 0444); 299 MODULE_PARM_DESC(qla2xuseresexchforels, 300 "Reserve 1/2 of emergency exchanges for ELS.\n" 301 " 0 (default): disabled"); 302 303 static int ql2xprotmask; 304 module_param(ql2xprotmask, int, 0644); 305 MODULE_PARM_DESC(ql2xprotmask, 306 "Override DIF/DIX protection capabilities mask\n" 307 "Default is 0 which sets protection mask based on " 308 "capabilities reported by HBA firmware.\n"); 309 310 static int ql2xprotguard; 311 module_param(ql2xprotguard, int, 0644); 312 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 313 " 0 -- Let HBA firmware decide\n" 314 " 1 -- Force T10 CRC\n" 315 " 2 -- Force IP checksum\n"); 316 317 int ql2xdifbundlinginternalbuffers; 318 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 319 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 320 "Force using internal buffers for DIF information\n" 321 "0 (Default). Based on check.\n" 322 "1 Force using internal buffers\n"); 323 324 int ql2xsmartsan; 325 module_param(ql2xsmartsan, int, 0444); 326 module_param_named(smartsan, ql2xsmartsan, int, 0444); 327 MODULE_PARM_DESC(ql2xsmartsan, 328 "Send SmartSAN Management Attributes for FDMI Registration." 329 " Default is 0 - No SmartSAN registration," 330 " 1 - Register SmartSAN Management Attributes."); 331 332 int ql2xrdpenable; 333 module_param(ql2xrdpenable, int, 0444); 334 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 335 MODULE_PARM_DESC(ql2xrdpenable, 336 "Enables RDP responses. " 337 "0 - no RDP responses (default). " 338 "1 - provide RDP responses."); 339 int ql2xabts_wait_nvme = 1; 340 module_param(ql2xabts_wait_nvme, int, 0444); 341 MODULE_PARM_DESC(ql2xabts_wait_nvme, 342 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 343 344 345 static u32 ql2xdelay_before_pci_error_handling = 5; 346 module_param(ql2xdelay_before_pci_error_handling, uint, 0644); 347 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling, 348 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n"); 349 350 static void qla2x00_clear_drv_active(struct qla_hw_data *); 351 static void qla2x00_free_device(scsi_qla_host_t *); 352 static void qla2xxx_map_queues(struct Scsi_Host *shost); 353 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 354 355 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES; 356 module_param(ql2xnvme_queues, uint, S_IRUGO); 357 MODULE_PARM_DESC(ql2xnvme_queues, 358 "Number of NVMe Queues that can be configured.\n" 359 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n" 360 "1 - Minimum number of queues supported\n" 361 "8 - Default value"); 362 363 int ql2xfc2target = 1; 364 module_param(ql2xfc2target, int, 0444); 365 MODULE_PARM_DESC(qla2xfc2target, 366 "Enables FC2 Target support. " 367 "0 - FC2 Target support is disabled. " 368 "1 - FC2 Target support is enabled (default)."); 369 370 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 371 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 372 373 /* TODO Convert to inlines 374 * 375 * Timer routines 376 */ 377 378 __inline__ void 379 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 380 { 381 timer_setup(&vha->timer, qla2x00_timer, 0); 382 vha->timer.expires = jiffies + interval * HZ; 383 add_timer(&vha->timer); 384 vha->timer_active = 1; 385 } 386 387 static inline void 388 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 389 { 390 /* Currently used for 82XX only. */ 391 if (vha->device_flags & DFLG_DEV_FAILED) { 392 ql_dbg(ql_dbg_timer, vha, 0x600d, 393 "Device in a failed state, returning.\n"); 394 return; 395 } 396 397 mod_timer(&vha->timer, jiffies + interval * HZ); 398 } 399 400 static __inline__ void 401 qla2x00_stop_timer(scsi_qla_host_t *vha) 402 { 403 del_timer_sync(&vha->timer); 404 vha->timer_active = 0; 405 } 406 407 static int qla2x00_do_dpc(void *data); 408 409 static void qla2x00_rst_aen(scsi_qla_host_t *); 410 411 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 412 struct req_que **, struct rsp_que **); 413 static void qla2x00_free_fw_dump(struct qla_hw_data *); 414 static void qla2x00_mem_free(struct qla_hw_data *); 415 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 416 struct qla_qpair *qpair); 417 418 /* -------------------------------------------------------------------------- */ 419 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 420 struct rsp_que *rsp) 421 { 422 struct qla_hw_data *ha = vha->hw; 423 424 rsp->qpair = ha->base_qpair; 425 rsp->req = req; 426 ha->base_qpair->hw = ha; 427 ha->base_qpair->req = req; 428 ha->base_qpair->rsp = rsp; 429 ha->base_qpair->vha = vha; 430 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 431 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 432 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 433 ha->base_qpair->srb_mempool = ha->srb_mempool; 434 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 435 ha->base_qpair->enable_class_2 = ql2xenableclass2; 436 /* init qpair to this cpu. Will adjust at run time. */ 437 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 438 ha->base_qpair->pdev = ha->pdev; 439 440 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 441 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 442 } 443 444 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 445 struct rsp_que *rsp) 446 { 447 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 448 449 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 450 GFP_KERNEL); 451 if (!ha->req_q_map) { 452 ql_log(ql_log_fatal, vha, 0x003b, 453 "Unable to allocate memory for request queue ptrs.\n"); 454 goto fail_req_map; 455 } 456 457 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 458 GFP_KERNEL); 459 if (!ha->rsp_q_map) { 460 ql_log(ql_log_fatal, vha, 0x003c, 461 "Unable to allocate memory for response queue ptrs.\n"); 462 goto fail_rsp_map; 463 } 464 465 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 466 if (ha->base_qpair == NULL) { 467 ql_log(ql_log_warn, vha, 0x00e0, 468 "Failed to allocate base queue pair memory.\n"); 469 goto fail_base_qpair; 470 } 471 472 qla_init_base_qpair(vha, req, rsp); 473 474 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 475 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 476 GFP_KERNEL); 477 if (!ha->queue_pair_map) { 478 ql_log(ql_log_fatal, vha, 0x0180, 479 "Unable to allocate memory for queue pair ptrs.\n"); 480 goto fail_qpair_map; 481 } 482 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) { 483 kfree(ha->queue_pair_map); 484 ha->queue_pair_map = NULL; 485 goto fail_qpair_map; 486 } 487 } 488 489 /* 490 * Make sure we record at least the request and response queue zero in 491 * case we need to free them if part of the probe fails. 492 */ 493 ha->rsp_q_map[0] = rsp; 494 ha->req_q_map[0] = req; 495 set_bit(0, ha->rsp_qid_map); 496 set_bit(0, ha->req_qid_map); 497 return 0; 498 499 fail_qpair_map: 500 kfree(ha->base_qpair); 501 ha->base_qpair = NULL; 502 fail_base_qpair: 503 kfree(ha->rsp_q_map); 504 ha->rsp_q_map = NULL; 505 fail_rsp_map: 506 kfree(ha->req_q_map); 507 ha->req_q_map = NULL; 508 fail_req_map: 509 return -ENOMEM; 510 } 511 512 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 513 { 514 if (IS_QLAFX00(ha)) { 515 if (req && req->ring_fx00) 516 dma_free_coherent(&ha->pdev->dev, 517 (req->length_fx00 + 1) * sizeof(request_t), 518 req->ring_fx00, req->dma_fx00); 519 } else if (req && req->ring) 520 dma_free_coherent(&ha->pdev->dev, 521 (req->length + 1) * sizeof(request_t), 522 req->ring, req->dma); 523 524 if (req) 525 kfree(req->outstanding_cmds); 526 527 kfree(req); 528 } 529 530 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 531 { 532 if (IS_QLAFX00(ha)) { 533 if (rsp && rsp->ring_fx00) 534 dma_free_coherent(&ha->pdev->dev, 535 (rsp->length_fx00 + 1) * sizeof(request_t), 536 rsp->ring_fx00, rsp->dma_fx00); 537 } else if (rsp && rsp->ring) { 538 dma_free_coherent(&ha->pdev->dev, 539 (rsp->length + 1) * sizeof(response_t), 540 rsp->ring, rsp->dma); 541 } 542 kfree(rsp); 543 } 544 545 static void qla2x00_free_queues(struct qla_hw_data *ha) 546 { 547 struct req_que *req; 548 struct rsp_que *rsp; 549 int cnt; 550 unsigned long flags; 551 552 if (ha->queue_pair_map) { 553 kfree(ha->queue_pair_map); 554 ha->queue_pair_map = NULL; 555 } 556 if (ha->base_qpair) { 557 kfree(ha->base_qpair); 558 ha->base_qpair = NULL; 559 } 560 561 qla_mapq_free_qp_cpu_map(ha); 562 spin_lock_irqsave(&ha->hardware_lock, flags); 563 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 564 if (!test_bit(cnt, ha->req_qid_map)) 565 continue; 566 567 req = ha->req_q_map[cnt]; 568 clear_bit(cnt, ha->req_qid_map); 569 ha->req_q_map[cnt] = NULL; 570 571 spin_unlock_irqrestore(&ha->hardware_lock, flags); 572 qla2x00_free_req_que(ha, req); 573 spin_lock_irqsave(&ha->hardware_lock, flags); 574 } 575 spin_unlock_irqrestore(&ha->hardware_lock, flags); 576 577 kfree(ha->req_q_map); 578 ha->req_q_map = NULL; 579 580 581 spin_lock_irqsave(&ha->hardware_lock, flags); 582 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 583 if (!test_bit(cnt, ha->rsp_qid_map)) 584 continue; 585 586 rsp = ha->rsp_q_map[cnt]; 587 clear_bit(cnt, ha->rsp_qid_map); 588 ha->rsp_q_map[cnt] = NULL; 589 spin_unlock_irqrestore(&ha->hardware_lock, flags); 590 qla2x00_free_rsp_que(ha, rsp); 591 spin_lock_irqsave(&ha->hardware_lock, flags); 592 } 593 spin_unlock_irqrestore(&ha->hardware_lock, flags); 594 595 kfree(ha->rsp_q_map); 596 ha->rsp_q_map = NULL; 597 } 598 599 static char * 600 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 601 { 602 struct qla_hw_data *ha = vha->hw; 603 static const char *const pci_bus_modes[] = { 604 "33", "66", "100", "133", 605 }; 606 uint16_t pci_bus; 607 608 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 609 if (pci_bus) { 610 snprintf(str, str_len, "PCI-X (%s MHz)", 611 pci_bus_modes[pci_bus]); 612 } else { 613 pci_bus = (ha->pci_attr & BIT_8) >> 8; 614 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 615 } 616 617 return str; 618 } 619 620 static char * 621 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 622 { 623 static const char *const pci_bus_modes[] = { 624 "33", "66", "100", "133", 625 }; 626 struct qla_hw_data *ha = vha->hw; 627 uint32_t pci_bus; 628 629 if (pci_is_pcie(ha->pdev)) { 630 uint32_t lstat, lspeed, lwidth; 631 const char *speed_str; 632 633 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 634 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 635 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 636 637 switch (lspeed) { 638 case 1: 639 speed_str = "2.5GT/s"; 640 break; 641 case 2: 642 speed_str = "5.0GT/s"; 643 break; 644 case 3: 645 speed_str = "8.0GT/s"; 646 break; 647 case 4: 648 speed_str = "16.0GT/s"; 649 break; 650 default: 651 speed_str = "<unknown>"; 652 break; 653 } 654 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 655 656 return str; 657 } 658 659 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 660 if (pci_bus == 0 || pci_bus == 8) 661 snprintf(str, str_len, "PCI (%s MHz)", 662 pci_bus_modes[pci_bus >> 3]); 663 else 664 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 665 pci_bus & 4 ? 2 : 1, 666 pci_bus_modes[pci_bus & 3]); 667 668 return str; 669 } 670 671 static char * 672 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 673 { 674 char un_str[10]; 675 struct qla_hw_data *ha = vha->hw; 676 677 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 678 ha->fw_minor_version, ha->fw_subminor_version); 679 680 if (ha->fw_attributes & BIT_9) { 681 strcat(str, "FLX"); 682 return (str); 683 } 684 685 switch (ha->fw_attributes & 0xFF) { 686 case 0x7: 687 strcat(str, "EF"); 688 break; 689 case 0x17: 690 strcat(str, "TP"); 691 break; 692 case 0x37: 693 strcat(str, "IP"); 694 break; 695 case 0x77: 696 strcat(str, "VI"); 697 break; 698 default: 699 sprintf(un_str, "(%x)", ha->fw_attributes); 700 strcat(str, un_str); 701 break; 702 } 703 if (ha->fw_attributes & 0x100) 704 strcat(str, "X"); 705 706 return (str); 707 } 708 709 static char * 710 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 711 { 712 struct qla_hw_data *ha = vha->hw; 713 714 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 715 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 716 return str; 717 } 718 719 void qla2x00_sp_free_dma(srb_t *sp) 720 { 721 struct qla_hw_data *ha = sp->vha->hw; 722 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 723 724 if (sp->flags & SRB_DMA_VALID) { 725 scsi_dma_unmap(cmd); 726 sp->flags &= ~SRB_DMA_VALID; 727 } 728 729 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 730 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 731 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 732 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 733 } 734 735 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 736 /* List assured to be having elements */ 737 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 738 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 739 } 740 741 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 742 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 743 744 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 745 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 746 } 747 748 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 749 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 750 751 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 752 ctx1->fcp_cmnd_dma); 753 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 754 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 755 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 756 } 757 758 if (sp->flags & SRB_GOT_BUF) 759 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 760 } 761 762 void qla2x00_sp_compl(srb_t *sp, int res) 763 { 764 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 765 struct completion *comp = sp->comp; 766 767 /* kref: INIT */ 768 kref_put(&sp->cmd_kref, qla2x00_sp_release); 769 cmd->result = res; 770 sp->type = 0; 771 scsi_done(cmd); 772 if (comp) 773 complete(comp); 774 } 775 776 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 777 { 778 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 779 struct qla_hw_data *ha = sp->fcport->vha->hw; 780 781 if (sp->flags & SRB_DMA_VALID) { 782 scsi_dma_unmap(cmd); 783 sp->flags &= ~SRB_DMA_VALID; 784 } 785 786 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 787 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 788 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 789 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 790 } 791 792 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 793 /* List assured to be having elements */ 794 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 795 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 796 } 797 798 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 799 struct crc_context *difctx = sp->u.scmd.crc_ctx; 800 struct dsd_dma *dif_dsd, *nxt_dsd; 801 802 list_for_each_entry_safe(dif_dsd, nxt_dsd, 803 &difctx->ldif_dma_hndl_list, list) { 804 list_del(&dif_dsd->list); 805 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 806 dif_dsd->dsd_list_dma); 807 kfree(dif_dsd); 808 difctx->no_dif_bundl--; 809 } 810 811 list_for_each_entry_safe(dif_dsd, nxt_dsd, 812 &difctx->ldif_dsd_list, list) { 813 list_del(&dif_dsd->list); 814 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 815 dif_dsd->dsd_list_dma); 816 kfree(dif_dsd); 817 difctx->no_ldif_dsd--; 818 } 819 820 if (difctx->no_ldif_dsd) { 821 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 822 "%s: difctx->no_ldif_dsd=%x\n", 823 __func__, difctx->no_ldif_dsd); 824 } 825 826 if (difctx->no_dif_bundl) { 827 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 828 "%s: difctx->no_dif_bundl=%x\n", 829 __func__, difctx->no_dif_bundl); 830 } 831 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 832 } 833 834 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 835 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 836 837 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 838 ctx1->fcp_cmnd_dma); 839 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 840 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 841 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 842 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 843 } 844 845 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 846 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 847 848 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 849 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 850 } 851 852 if (sp->flags & SRB_GOT_BUF) 853 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 854 } 855 856 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 857 { 858 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 859 struct completion *comp = sp->comp; 860 861 /* ref: INIT */ 862 kref_put(&sp->cmd_kref, qla2x00_sp_release); 863 cmd->result = res; 864 sp->type = 0; 865 scsi_done(cmd); 866 if (comp) 867 complete(comp); 868 } 869 870 static int 871 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 872 { 873 scsi_qla_host_t *vha = shost_priv(host); 874 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 875 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 876 struct qla_hw_data *ha = vha->hw; 877 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 878 srb_t *sp; 879 int rval; 880 881 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 882 WARN_ON_ONCE(!rport)) { 883 cmd->result = DID_NO_CONNECT << 16; 884 goto qc24_fail_command; 885 } 886 887 if (ha->mqenable) { 888 uint32_t tag; 889 uint16_t hwq; 890 struct qla_qpair *qpair = NULL; 891 892 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 893 hwq = blk_mq_unique_tag_to_hwq(tag); 894 qpair = ha->queue_pair_map[hwq]; 895 896 if (qpair) 897 return qla2xxx_mqueuecommand(host, cmd, qpair); 898 } 899 900 if (ha->flags.eeh_busy) { 901 if (ha->flags.pci_channel_io_perm_failure) { 902 ql_dbg(ql_dbg_aer, vha, 0x9010, 903 "PCI Channel IO permanent failure, exiting " 904 "cmd=%p.\n", cmd); 905 cmd->result = DID_NO_CONNECT << 16; 906 } else { 907 ql_dbg(ql_dbg_aer, vha, 0x9011, 908 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 909 cmd->result = DID_REQUEUE << 16; 910 } 911 goto qc24_fail_command; 912 } 913 914 rval = fc_remote_port_chkready(rport); 915 if (rval) { 916 cmd->result = rval; 917 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 918 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 919 cmd, rval); 920 goto qc24_fail_command; 921 } 922 923 if (!vha->flags.difdix_supported && 924 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 925 ql_dbg(ql_dbg_io, vha, 0x3004, 926 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 927 cmd); 928 cmd->result = DID_NO_CONNECT << 16; 929 goto qc24_fail_command; 930 } 931 932 if (!fcport || fcport->deleted) { 933 cmd->result = DID_IMM_RETRY << 16; 934 goto qc24_fail_command; 935 } 936 937 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 938 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 939 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 940 ql_dbg(ql_dbg_io, vha, 0x3005, 941 "Returning DNC, fcport_state=%d loop_state=%d.\n", 942 atomic_read(&fcport->state), 943 atomic_read(&base_vha->loop_state)); 944 cmd->result = DID_NO_CONNECT << 16; 945 goto qc24_fail_command; 946 } 947 goto qc24_target_busy; 948 } 949 950 /* 951 * Return target busy if we've received a non-zero retry_delay_timer 952 * in a FCP_RSP. 953 */ 954 if (fcport->retry_delay_timestamp == 0) { 955 /* retry delay not set */ 956 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 957 fcport->retry_delay_timestamp = 0; 958 else 959 goto qc24_target_busy; 960 961 sp = scsi_cmd_priv(cmd); 962 /* ref: INIT */ 963 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 964 965 sp->u.scmd.cmd = cmd; 966 sp->type = SRB_SCSI_CMD; 967 sp->free = qla2x00_sp_free_dma; 968 sp->done = qla2x00_sp_compl; 969 970 rval = ha->isp_ops->start_scsi(sp); 971 if (rval != QLA_SUCCESS) { 972 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 973 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 974 goto qc24_host_busy_free_sp; 975 } 976 977 return 0; 978 979 qc24_host_busy_free_sp: 980 /* ref: INIT */ 981 kref_put(&sp->cmd_kref, qla2x00_sp_release); 982 983 qc24_target_busy: 984 return SCSI_MLQUEUE_TARGET_BUSY; 985 986 qc24_fail_command: 987 scsi_done(cmd); 988 989 return 0; 990 } 991 992 /* For MQ supported I/O */ 993 int 994 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 995 struct qla_qpair *qpair) 996 { 997 scsi_qla_host_t *vha = shost_priv(host); 998 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 999 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 1000 struct qla_hw_data *ha = vha->hw; 1001 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1002 srb_t *sp; 1003 int rval; 1004 1005 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 1006 if (rval) { 1007 cmd->result = rval; 1008 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 1009 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 1010 cmd, rval); 1011 goto qc24_fail_command; 1012 } 1013 1014 if (!qpair->online) { 1015 ql_dbg(ql_dbg_io, vha, 0x3077, 1016 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 1017 cmd->result = DID_NO_CONNECT << 16; 1018 goto qc24_fail_command; 1019 } 1020 1021 if (!fcport || fcport->deleted) { 1022 cmd->result = DID_IMM_RETRY << 16; 1023 goto qc24_fail_command; 1024 } 1025 1026 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 1027 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1028 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1029 ql_dbg(ql_dbg_io, vha, 0x3077, 1030 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1031 atomic_read(&fcport->state), 1032 atomic_read(&base_vha->loop_state)); 1033 cmd->result = DID_NO_CONNECT << 16; 1034 goto qc24_fail_command; 1035 } 1036 goto qc24_target_busy; 1037 } 1038 1039 /* 1040 * Return target busy if we've received a non-zero retry_delay_timer 1041 * in a FCP_RSP. 1042 */ 1043 if (fcport->retry_delay_timestamp == 0) { 1044 /* retry delay not set */ 1045 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1046 fcport->retry_delay_timestamp = 0; 1047 else 1048 goto qc24_target_busy; 1049 1050 sp = scsi_cmd_priv(cmd); 1051 /* ref: INIT */ 1052 qla2xxx_init_sp(sp, vha, qpair, fcport); 1053 1054 sp->u.scmd.cmd = cmd; 1055 sp->type = SRB_SCSI_CMD; 1056 sp->free = qla2xxx_qpair_sp_free_dma; 1057 sp->done = qla2xxx_qpair_sp_compl; 1058 1059 rval = ha->isp_ops->start_scsi_mq(sp); 1060 if (rval != QLA_SUCCESS) { 1061 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1062 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1063 goto qc24_host_busy_free_sp; 1064 } 1065 1066 return 0; 1067 1068 qc24_host_busy_free_sp: 1069 /* ref: INIT */ 1070 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1071 1072 qc24_target_busy: 1073 return SCSI_MLQUEUE_TARGET_BUSY; 1074 1075 qc24_fail_command: 1076 scsi_done(cmd); 1077 1078 return 0; 1079 } 1080 1081 /* 1082 * qla2x00_wait_for_hba_online 1083 * Wait till the HBA is online after going through 1084 * <= MAX_RETRIES_OF_ISP_ABORT or 1085 * finally HBA is disabled ie marked offline 1086 * 1087 * Input: 1088 * ha - pointer to host adapter structure 1089 * 1090 * Note: 1091 * Does context switching-Release SPIN_LOCK 1092 * (if any) before calling this routine. 1093 * 1094 * Return: 1095 * Success (Adapter is online) : 0 1096 * Failed (Adapter is offline/disabled) : 1 1097 */ 1098 int 1099 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1100 { 1101 int return_status; 1102 unsigned long wait_online; 1103 struct qla_hw_data *ha = vha->hw; 1104 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1105 1106 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1107 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1108 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1109 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1110 ha->dpc_active) && time_before(jiffies, wait_online)) { 1111 1112 msleep(1000); 1113 } 1114 if (base_vha->flags.online) 1115 return_status = QLA_SUCCESS; 1116 else 1117 return_status = QLA_FUNCTION_FAILED; 1118 1119 return (return_status); 1120 } 1121 1122 static inline int test_fcport_count(scsi_qla_host_t *vha) 1123 { 1124 struct qla_hw_data *ha = vha->hw; 1125 unsigned long flags; 1126 int res; 1127 /* Return 0 = sleep, x=wake */ 1128 1129 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1130 ql_dbg(ql_dbg_init, vha, 0x00ec, 1131 "tgt %p, fcport_count=%d\n", 1132 vha, vha->fcport_count); 1133 res = (vha->fcport_count == 0); 1134 if (res) { 1135 struct fc_port *fcport; 1136 1137 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1138 if (fcport->deleted != QLA_SESS_DELETED) { 1139 /* session(s) may not be fully logged in 1140 * (ie fcport_count=0), but session 1141 * deletion thread(s) may be inflight. 1142 */ 1143 1144 res = 0; 1145 break; 1146 } 1147 } 1148 } 1149 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1150 1151 return res; 1152 } 1153 1154 /* 1155 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1156 * it has dependency on UNLOADING flag to stop device discovery 1157 */ 1158 void 1159 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1160 { 1161 u8 i; 1162 1163 qla2x00_mark_all_devices_lost(vha); 1164 1165 for (i = 0; i < 10; i++) { 1166 if (wait_event_timeout(vha->fcport_waitQ, 1167 test_fcport_count(vha), HZ) > 0) 1168 break; 1169 } 1170 1171 flush_workqueue(vha->hw->wq); 1172 } 1173 1174 /* 1175 * qla2x00_wait_for_hba_ready 1176 * Wait till the HBA is ready before doing driver unload 1177 * 1178 * Input: 1179 * ha - pointer to host adapter structure 1180 * 1181 * Note: 1182 * Does context switching-Release SPIN_LOCK 1183 * (if any) before calling this routine. 1184 * 1185 */ 1186 static void 1187 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1188 { 1189 struct qla_hw_data *ha = vha->hw; 1190 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1191 1192 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1193 ha->flags.mbox_busy) || 1194 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1195 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1196 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1197 break; 1198 msleep(1000); 1199 } 1200 } 1201 1202 int 1203 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1204 { 1205 int return_status; 1206 unsigned long wait_reset; 1207 struct qla_hw_data *ha = vha->hw; 1208 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1209 1210 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1211 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1212 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1213 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1214 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1215 1216 msleep(1000); 1217 1218 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1219 ha->flags.chip_reset_done) 1220 break; 1221 } 1222 if (ha->flags.chip_reset_done) 1223 return_status = QLA_SUCCESS; 1224 else 1225 return_status = QLA_FUNCTION_FAILED; 1226 1227 return return_status; 1228 } 1229 1230 /************************************************************************** 1231 * qla2xxx_eh_abort 1232 * 1233 * Description: 1234 * The abort function will abort the specified command. 1235 * 1236 * Input: 1237 * cmd = Linux SCSI command packet to be aborted. 1238 * 1239 * Returns: 1240 * Either SUCCESS or FAILED. 1241 * 1242 * Note: 1243 * Only return FAILED if command not returned by firmware. 1244 **************************************************************************/ 1245 static int 1246 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1247 { 1248 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1249 DECLARE_COMPLETION_ONSTACK(comp); 1250 srb_t *sp; 1251 int ret; 1252 unsigned int id; 1253 uint64_t lun; 1254 int rval; 1255 struct qla_hw_data *ha = vha->hw; 1256 uint32_t ratov_j; 1257 struct qla_qpair *qpair; 1258 unsigned long flags; 1259 int fast_fail_status = SUCCESS; 1260 1261 if (qla2x00_isp_reg_stat(ha)) { 1262 ql_log(ql_log_info, vha, 0x8042, 1263 "PCI/Register disconnect, exiting.\n"); 1264 qla_pci_set_eeh_busy(vha); 1265 return FAILED; 1266 } 1267 1268 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1269 ret = fc_block_scsi_eh(cmd); 1270 if (ret != 0) 1271 fast_fail_status = ret; 1272 1273 sp = scsi_cmd_priv(cmd); 1274 qpair = sp->qpair; 1275 1276 vha->cmd_timeout_cnt++; 1277 1278 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1279 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1280 1281 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1282 sp->comp = ∁ 1283 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1284 1285 1286 id = cmd->device->id; 1287 lun = cmd->device->lun; 1288 1289 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1290 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1291 vha->host_no, id, lun, sp, cmd, sp->handle); 1292 1293 /* 1294 * Abort will release the original Command/sp from FW. Let the 1295 * original command call scsi_done. In return, he will wakeup 1296 * this sleeping thread. 1297 */ 1298 rval = ha->isp_ops->abort_command(sp); 1299 1300 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1301 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1302 1303 /* Wait for the command completion. */ 1304 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1305 ratov_j = msecs_to_jiffies(ratov_j); 1306 switch (rval) { 1307 case QLA_SUCCESS: 1308 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1309 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1310 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1311 __func__, ha->r_a_tov/10); 1312 ret = FAILED; 1313 } else { 1314 ret = fast_fail_status; 1315 } 1316 break; 1317 default: 1318 ret = FAILED; 1319 break; 1320 } 1321 1322 sp->comp = NULL; 1323 1324 ql_log(ql_log_info, vha, 0x801c, 1325 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1326 vha->host_no, id, lun, ret); 1327 1328 return ret; 1329 } 1330 1331 #define ABORT_POLLING_PERIOD 1000 1332 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1333 1334 /* 1335 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1336 */ 1337 static int 1338 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t, 1339 uint64_t l, enum nexus_wait_type type) 1340 { 1341 int cnt, match, status; 1342 unsigned long flags; 1343 scsi_qla_host_t *vha = qpair->vha; 1344 struct req_que *req = qpair->req; 1345 srb_t *sp; 1346 struct scsi_cmnd *cmd; 1347 unsigned long wait_iter = ABORT_WAIT_ITER; 1348 bool found; 1349 struct qla_hw_data *ha = vha->hw; 1350 1351 status = QLA_SUCCESS; 1352 1353 while (wait_iter--) { 1354 found = false; 1355 1356 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1357 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1358 sp = req->outstanding_cmds[cnt]; 1359 if (!sp) 1360 continue; 1361 if (sp->type != SRB_SCSI_CMD) 1362 continue; 1363 if (vha->vp_idx != sp->vha->vp_idx) 1364 continue; 1365 match = 0; 1366 cmd = GET_CMD_SP(sp); 1367 switch (type) { 1368 case WAIT_HOST: 1369 match = 1; 1370 break; 1371 case WAIT_TARGET: 1372 if (sp->fcport) 1373 match = sp->fcport->d_id.b24 == t; 1374 else 1375 match = 0; 1376 break; 1377 case WAIT_LUN: 1378 if (sp->fcport) 1379 match = (sp->fcport->d_id.b24 == t && 1380 cmd->device->lun == l); 1381 else 1382 match = 0; 1383 break; 1384 } 1385 if (!match) 1386 continue; 1387 1388 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1389 1390 if (unlikely(pci_channel_offline(ha->pdev)) || 1391 ha->flags.eeh_busy) { 1392 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1393 "Return:eh_wait.\n"); 1394 return status; 1395 } 1396 1397 /* 1398 * SRB_SCSI_CMD is still in the outstanding_cmds array. 1399 * it means scsi_done has not called. Wait for it to 1400 * clear from outstanding_cmds. 1401 */ 1402 msleep(ABORT_POLLING_PERIOD); 1403 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1404 found = true; 1405 } 1406 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1407 1408 if (!found) 1409 break; 1410 } 1411 1412 if (wait_iter == -1) 1413 status = QLA_FUNCTION_FAILED; 1414 1415 return status; 1416 } 1417 1418 int 1419 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1420 uint64_t l, enum nexus_wait_type type) 1421 { 1422 struct qla_qpair *qpair; 1423 struct qla_hw_data *ha = vha->hw; 1424 int i, status = QLA_SUCCESS; 1425 1426 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l, 1427 type); 1428 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) { 1429 qpair = ha->queue_pair_map[i]; 1430 if (!qpair) 1431 continue; 1432 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l, 1433 type); 1434 } 1435 return status; 1436 } 1437 1438 static char *reset_errors[] = { 1439 "HBA not online", 1440 "HBA not ready", 1441 "Task management failed", 1442 "Waiting for command completions", 1443 }; 1444 1445 static int 1446 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1447 { 1448 struct scsi_device *sdev = cmd->device; 1449 scsi_qla_host_t *vha = shost_priv(sdev->host); 1450 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1451 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1452 struct qla_hw_data *ha = vha->hw; 1453 int err; 1454 1455 if (qla2x00_isp_reg_stat(ha)) { 1456 ql_log(ql_log_info, vha, 0x803e, 1457 "PCI/Register disconnect, exiting.\n"); 1458 qla_pci_set_eeh_busy(vha); 1459 return FAILED; 1460 } 1461 1462 if (!fcport) { 1463 return FAILED; 1464 } 1465 1466 err = fc_block_rport(rport); 1467 if (err != 0) 1468 return err; 1469 1470 if (fcport->deleted) 1471 return FAILED; 1472 1473 ql_log(ql_log_info, vha, 0x8009, 1474 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1475 sdev->id, sdev->lun, cmd); 1476 1477 err = 0; 1478 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1479 ql_log(ql_log_warn, vha, 0x800a, 1480 "Wait for hba online failed for cmd=%p.\n", cmd); 1481 goto eh_reset_failed; 1482 } 1483 err = 2; 1484 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1485 != QLA_SUCCESS) { 1486 ql_log(ql_log_warn, vha, 0x800c, 1487 "do_reset failed for cmd=%p.\n", cmd); 1488 goto eh_reset_failed; 1489 } 1490 err = 3; 1491 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1492 sdev->lun, WAIT_LUN) != QLA_SUCCESS) { 1493 ql_log(ql_log_warn, vha, 0x800d, 1494 "wait for pending cmds failed for cmd=%p.\n", cmd); 1495 goto eh_reset_failed; 1496 } 1497 1498 ql_log(ql_log_info, vha, 0x800e, 1499 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1500 vha->host_no, sdev->id, sdev->lun, cmd); 1501 1502 return SUCCESS; 1503 1504 eh_reset_failed: 1505 ql_log(ql_log_info, vha, 0x800f, 1506 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1507 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1508 cmd); 1509 vha->reset_cmd_err_cnt++; 1510 return FAILED; 1511 } 1512 1513 static int 1514 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1515 { 1516 struct scsi_device *sdev = cmd->device; 1517 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1518 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1519 struct qla_hw_data *ha = vha->hw; 1520 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1521 int err; 1522 1523 if (qla2x00_isp_reg_stat(ha)) { 1524 ql_log(ql_log_info, vha, 0x803f, 1525 "PCI/Register disconnect, exiting.\n"); 1526 qla_pci_set_eeh_busy(vha); 1527 return FAILED; 1528 } 1529 1530 if (!fcport) { 1531 return FAILED; 1532 } 1533 1534 err = fc_block_rport(rport); 1535 if (err != 0) 1536 return err; 1537 1538 if (fcport->deleted) 1539 return FAILED; 1540 1541 ql_log(ql_log_info, vha, 0x8009, 1542 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1543 sdev->id, cmd); 1544 1545 err = 0; 1546 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1547 ql_log(ql_log_warn, vha, 0x800a, 1548 "Wait for hba online failed for cmd=%p.\n", cmd); 1549 goto eh_reset_failed; 1550 } 1551 err = 2; 1552 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1553 ql_log(ql_log_warn, vha, 0x800c, 1554 "target_reset failed for cmd=%p.\n", cmd); 1555 goto eh_reset_failed; 1556 } 1557 err = 3; 1558 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id, 1559 0, WAIT_TARGET) != QLA_SUCCESS) { 1560 ql_log(ql_log_warn, vha, 0x800d, 1561 "wait for pending cmds failed for cmd=%p.\n", cmd); 1562 goto eh_reset_failed; 1563 } 1564 1565 ql_log(ql_log_info, vha, 0x800e, 1566 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1567 vha->host_no, sdev->id, cmd); 1568 1569 return SUCCESS; 1570 1571 eh_reset_failed: 1572 ql_log(ql_log_info, vha, 0x800f, 1573 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1574 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1575 cmd); 1576 vha->reset_cmd_err_cnt++; 1577 return FAILED; 1578 } 1579 1580 /************************************************************************** 1581 * qla2xxx_eh_bus_reset 1582 * 1583 * Description: 1584 * The bus reset function will reset the bus and abort any executing 1585 * commands. 1586 * 1587 * Input: 1588 * cmd = Linux SCSI command packet of the command that cause the 1589 * bus reset. 1590 * 1591 * Returns: 1592 * SUCCESS/FAILURE (defined as macro in scsi.h). 1593 * 1594 **************************************************************************/ 1595 static int 1596 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1597 { 1598 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1599 int ret = FAILED; 1600 unsigned int id; 1601 uint64_t lun; 1602 struct qla_hw_data *ha = vha->hw; 1603 1604 if (qla2x00_isp_reg_stat(ha)) { 1605 ql_log(ql_log_info, vha, 0x8040, 1606 "PCI/Register disconnect, exiting.\n"); 1607 qla_pci_set_eeh_busy(vha); 1608 return FAILED; 1609 } 1610 1611 id = cmd->device->id; 1612 lun = cmd->device->lun; 1613 1614 if (qla2x00_chip_is_down(vha)) 1615 return ret; 1616 1617 ql_log(ql_log_info, vha, 0x8012, 1618 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1619 1620 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1621 ql_log(ql_log_fatal, vha, 0x8013, 1622 "Wait for hba online failed board disabled.\n"); 1623 goto eh_bus_reset_done; 1624 } 1625 1626 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1627 ret = SUCCESS; 1628 1629 if (ret == FAILED) 1630 goto eh_bus_reset_done; 1631 1632 /* Flush outstanding commands. */ 1633 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1634 QLA_SUCCESS) { 1635 ql_log(ql_log_warn, vha, 0x8014, 1636 "Wait for pending commands failed.\n"); 1637 ret = FAILED; 1638 } 1639 1640 eh_bus_reset_done: 1641 ql_log(ql_log_warn, vha, 0x802b, 1642 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1643 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1644 1645 return ret; 1646 } 1647 1648 /************************************************************************** 1649 * qla2xxx_eh_host_reset 1650 * 1651 * Description: 1652 * The reset function will reset the Adapter. 1653 * 1654 * Input: 1655 * cmd = Linux SCSI command packet of the command that cause the 1656 * adapter reset. 1657 * 1658 * Returns: 1659 * Either SUCCESS or FAILED. 1660 * 1661 * Note: 1662 **************************************************************************/ 1663 static int 1664 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1665 { 1666 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1667 struct qla_hw_data *ha = vha->hw; 1668 int ret = FAILED; 1669 unsigned int id; 1670 uint64_t lun; 1671 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1672 1673 if (qla2x00_isp_reg_stat(ha)) { 1674 ql_log(ql_log_info, vha, 0x8041, 1675 "PCI/Register disconnect, exiting.\n"); 1676 qla_pci_set_eeh_busy(vha); 1677 return SUCCESS; 1678 } 1679 1680 id = cmd->device->id; 1681 lun = cmd->device->lun; 1682 1683 ql_log(ql_log_info, vha, 0x8018, 1684 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1685 1686 /* 1687 * No point in issuing another reset if one is active. Also do not 1688 * attempt a reset if we are updating flash. 1689 */ 1690 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1691 goto eh_host_reset_lock; 1692 1693 if (vha != base_vha) { 1694 if (qla2x00_vp_abort_isp(vha)) 1695 goto eh_host_reset_lock; 1696 } else { 1697 if (IS_P3P_TYPE(vha->hw)) { 1698 if (!qla82xx_fcoe_ctx_reset(vha)) { 1699 /* Ctx reset success */ 1700 ret = SUCCESS; 1701 goto eh_host_reset_lock; 1702 } 1703 /* fall thru if ctx reset failed */ 1704 } 1705 if (ha->wq) 1706 flush_workqueue(ha->wq); 1707 1708 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1709 if (ha->isp_ops->abort_isp(base_vha)) { 1710 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1711 /* failed. schedule dpc to try */ 1712 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1713 1714 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1715 ql_log(ql_log_warn, vha, 0x802a, 1716 "wait for hba online failed.\n"); 1717 goto eh_host_reset_lock; 1718 } 1719 } 1720 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1721 } 1722 1723 /* Waiting for command to be returned to OS.*/ 1724 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1725 QLA_SUCCESS) 1726 ret = SUCCESS; 1727 1728 eh_host_reset_lock: 1729 ql_log(ql_log_info, vha, 0x8017, 1730 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1731 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1732 1733 return ret; 1734 } 1735 1736 /* 1737 * qla2x00_loop_reset 1738 * Issue loop reset. 1739 * 1740 * Input: 1741 * ha = adapter block pointer. 1742 * 1743 * Returns: 1744 * 0 = success 1745 */ 1746 int 1747 qla2x00_loop_reset(scsi_qla_host_t *vha) 1748 { 1749 int ret; 1750 struct qla_hw_data *ha = vha->hw; 1751 1752 if (IS_QLAFX00(ha)) 1753 return QLA_SUCCESS; 1754 1755 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1756 atomic_set(&vha->loop_state, LOOP_DOWN); 1757 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1758 qla2x00_mark_all_devices_lost(vha); 1759 ret = qla2x00_full_login_lip(vha); 1760 if (ret != QLA_SUCCESS) { 1761 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1762 "full_login_lip=%d.\n", ret); 1763 } 1764 } 1765 1766 if (ha->flags.enable_lip_reset) { 1767 ret = qla2x00_lip_reset(vha); 1768 if (ret != QLA_SUCCESS) 1769 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1770 "lip_reset failed (%d).\n", ret); 1771 } 1772 1773 /* Issue marker command only when we are going to start the I/O */ 1774 vha->marker_needed = 1; 1775 1776 return QLA_SUCCESS; 1777 } 1778 1779 /* 1780 * The caller must ensure that no completion interrupts will happen 1781 * while this function is in progress. 1782 */ 1783 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1784 unsigned long *flags) 1785 __releases(qp->qp_lock_ptr) 1786 __acquires(qp->qp_lock_ptr) 1787 { 1788 DECLARE_COMPLETION_ONSTACK(comp); 1789 scsi_qla_host_t *vha = qp->vha; 1790 struct qla_hw_data *ha = vha->hw; 1791 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1792 int rval; 1793 bool ret_cmd; 1794 uint32_t ratov_j; 1795 1796 lockdep_assert_held(qp->qp_lock_ptr); 1797 1798 if (qla2x00_chip_is_down(vha)) { 1799 sp->done(sp, res); 1800 return; 1801 } 1802 1803 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1804 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1805 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1806 !qla2x00_isp_reg_stat(ha))) { 1807 if (sp->comp) { 1808 sp->done(sp, res); 1809 return; 1810 } 1811 1812 sp->comp = ∁ 1813 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1814 1815 rval = ha->isp_ops->abort_command(sp); 1816 /* Wait for command completion. */ 1817 ret_cmd = false; 1818 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1819 ratov_j = msecs_to_jiffies(ratov_j); 1820 switch (rval) { 1821 case QLA_SUCCESS: 1822 if (wait_for_completion_timeout(&comp, ratov_j)) { 1823 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1824 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1825 __func__, ha->r_a_tov/10); 1826 ret_cmd = true; 1827 } 1828 /* else FW return SP to driver */ 1829 break; 1830 default: 1831 ret_cmd = true; 1832 break; 1833 } 1834 1835 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1836 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1837 sp->done(sp, res); 1838 } else { 1839 sp->done(sp, res); 1840 } 1841 } 1842 1843 /* 1844 * The caller must ensure that no completion interrupts will happen 1845 * while this function is in progress. 1846 */ 1847 static void 1848 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1849 { 1850 int cnt; 1851 unsigned long flags; 1852 srb_t *sp; 1853 scsi_qla_host_t *vha = qp->vha; 1854 struct qla_hw_data *ha = vha->hw; 1855 struct req_que *req; 1856 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1857 struct qla_tgt_cmd *cmd; 1858 1859 if (!ha->req_q_map) 1860 return; 1861 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1862 req = qp->req; 1863 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1864 sp = req->outstanding_cmds[cnt]; 1865 if (sp) { 1866 /* 1867 * perform lockless completion during driver unload 1868 */ 1869 if (qla2x00_chip_is_down(vha)) { 1870 req->outstanding_cmds[cnt] = NULL; 1871 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1872 sp->done(sp, res); 1873 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1874 continue; 1875 } 1876 1877 switch (sp->cmd_type) { 1878 case TYPE_SRB: 1879 qla2x00_abort_srb(qp, sp, res, &flags); 1880 break; 1881 case TYPE_TGT_CMD: 1882 if (!vha->hw->tgt.tgt_ops || !tgt || 1883 qla_ini_mode_enabled(vha)) { 1884 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1885 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1886 vha->dpc_flags); 1887 continue; 1888 } 1889 cmd = (struct qla_tgt_cmd *)sp; 1890 cmd->aborted = 1; 1891 break; 1892 case TYPE_TGT_TMCMD: 1893 /* Skip task management functions. */ 1894 break; 1895 default: 1896 break; 1897 } 1898 req->outstanding_cmds[cnt] = NULL; 1899 } 1900 } 1901 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1902 } 1903 1904 /* 1905 * The caller must ensure that no completion interrupts will happen 1906 * while this function is in progress. 1907 */ 1908 void 1909 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1910 { 1911 int que; 1912 struct qla_hw_data *ha = vha->hw; 1913 1914 /* Continue only if initialization complete. */ 1915 if (!ha->base_qpair) 1916 return; 1917 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1918 1919 if (!ha->queue_pair_map) 1920 return; 1921 for (que = 0; que < ha->max_qpairs; que++) { 1922 if (!ha->queue_pair_map[que]) 1923 continue; 1924 1925 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1926 } 1927 } 1928 1929 static int 1930 qla2xxx_slave_alloc(struct scsi_device *sdev) 1931 { 1932 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1933 1934 if (!rport || fc_remote_port_chkready(rport)) 1935 return -ENXIO; 1936 1937 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1938 1939 return 0; 1940 } 1941 1942 static int 1943 qla2xxx_slave_configure(struct scsi_device *sdev) 1944 { 1945 scsi_qla_host_t *vha = shost_priv(sdev->host); 1946 struct req_que *req = vha->req; 1947 1948 if (IS_T10_PI_CAPABLE(vha->hw)) 1949 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1950 1951 scsi_change_queue_depth(sdev, req->max_q_depth); 1952 return 0; 1953 } 1954 1955 static void 1956 qla2xxx_slave_destroy(struct scsi_device *sdev) 1957 { 1958 sdev->hostdata = NULL; 1959 } 1960 1961 /** 1962 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1963 * @ha: HA context 1964 * 1965 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1966 * supported addressing method. 1967 */ 1968 static void 1969 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1970 { 1971 /* Assume a 32bit DMA mask. */ 1972 ha->flags.enable_64bit_addressing = 0; 1973 1974 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1975 /* Any upper-dword bits set? */ 1976 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1977 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1978 /* Ok, a 64bit DMA mask is applicable. */ 1979 ha->flags.enable_64bit_addressing = 1; 1980 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1981 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1982 return; 1983 } 1984 } 1985 1986 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1987 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1988 } 1989 1990 static void 1991 qla2x00_enable_intrs(struct qla_hw_data *ha) 1992 { 1993 unsigned long flags = 0; 1994 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1995 1996 spin_lock_irqsave(&ha->hardware_lock, flags); 1997 ha->interrupts_on = 1; 1998 /* enable risc and host interrupts */ 1999 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 2000 rd_reg_word(®->ictrl); 2001 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2002 2003 } 2004 2005 static void 2006 qla2x00_disable_intrs(struct qla_hw_data *ha) 2007 { 2008 unsigned long flags = 0; 2009 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2010 2011 spin_lock_irqsave(&ha->hardware_lock, flags); 2012 ha->interrupts_on = 0; 2013 /* disable risc and host interrupts */ 2014 wrt_reg_word(®->ictrl, 0); 2015 rd_reg_word(®->ictrl); 2016 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2017 } 2018 2019 static void 2020 qla24xx_enable_intrs(struct qla_hw_data *ha) 2021 { 2022 unsigned long flags = 0; 2023 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2024 2025 spin_lock_irqsave(&ha->hardware_lock, flags); 2026 ha->interrupts_on = 1; 2027 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 2028 rd_reg_dword(®->ictrl); 2029 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2030 } 2031 2032 static void 2033 qla24xx_disable_intrs(struct qla_hw_data *ha) 2034 { 2035 unsigned long flags = 0; 2036 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2037 2038 if (IS_NOPOLLING_TYPE(ha)) 2039 return; 2040 spin_lock_irqsave(&ha->hardware_lock, flags); 2041 ha->interrupts_on = 0; 2042 wrt_reg_dword(®->ictrl, 0); 2043 rd_reg_dword(®->ictrl); 2044 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2045 } 2046 2047 static int 2048 qla2x00_iospace_config(struct qla_hw_data *ha) 2049 { 2050 resource_size_t pio; 2051 uint16_t msix; 2052 2053 if (pci_request_selected_regions(ha->pdev, ha->bars, 2054 QLA2XXX_DRIVER_NAME)) { 2055 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2056 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2057 pci_name(ha->pdev)); 2058 goto iospace_error_exit; 2059 } 2060 if (!(ha->bars & 1)) 2061 goto skip_pio; 2062 2063 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2064 pio = pci_resource_start(ha->pdev, 0); 2065 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2066 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2067 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2068 "Invalid pci I/O region size (%s).\n", 2069 pci_name(ha->pdev)); 2070 pio = 0; 2071 } 2072 } else { 2073 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2074 "Region #0 no a PIO resource (%s).\n", 2075 pci_name(ha->pdev)); 2076 pio = 0; 2077 } 2078 ha->pio_address = pio; 2079 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2080 "PIO address=%llu.\n", 2081 (unsigned long long)ha->pio_address); 2082 2083 skip_pio: 2084 /* Use MMIO operations for all accesses. */ 2085 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2086 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2087 "Region #1 not an MMIO resource (%s), aborting.\n", 2088 pci_name(ha->pdev)); 2089 goto iospace_error_exit; 2090 } 2091 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2092 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2093 "Invalid PCI mem region size (%s), aborting.\n", 2094 pci_name(ha->pdev)); 2095 goto iospace_error_exit; 2096 } 2097 2098 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2099 if (!ha->iobase) { 2100 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2101 "Cannot remap MMIO (%s), aborting.\n", 2102 pci_name(ha->pdev)); 2103 goto iospace_error_exit; 2104 } 2105 2106 /* Determine queue resources */ 2107 ha->max_req_queues = ha->max_rsp_queues = 1; 2108 ha->msix_count = QLA_BASE_VECTORS; 2109 2110 /* Check if FW supports MQ or not */ 2111 if (!(ha->fw_attributes & BIT_6)) 2112 goto mqiobase_exit; 2113 2114 if (!ql2xmqsupport || !ql2xnvmeenable || 2115 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2116 goto mqiobase_exit; 2117 2118 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2119 pci_resource_len(ha->pdev, 3)); 2120 if (ha->mqiobase) { 2121 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2122 "MQIO Base=%p.\n", ha->mqiobase); 2123 /* Read MSIX vector size of the board */ 2124 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2125 ha->msix_count = msix + 1; 2126 /* Max queues are bounded by available msix vectors */ 2127 /* MB interrupt uses 1 vector */ 2128 ha->max_req_queues = ha->msix_count - 1; 2129 ha->max_rsp_queues = ha->max_req_queues; 2130 /* Queue pairs is the max value minus the base queue pair */ 2131 ha->max_qpairs = ha->max_rsp_queues - 1; 2132 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2133 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2134 2135 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2136 "MSI-X vector count: %d.\n", ha->msix_count); 2137 } else 2138 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2139 "BAR 3 not enabled.\n"); 2140 2141 mqiobase_exit: 2142 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2143 "MSIX Count: %d.\n", ha->msix_count); 2144 return (0); 2145 2146 iospace_error_exit: 2147 return (-ENOMEM); 2148 } 2149 2150 2151 static int 2152 qla83xx_iospace_config(struct qla_hw_data *ha) 2153 { 2154 uint16_t msix; 2155 2156 if (pci_request_selected_regions(ha->pdev, ha->bars, 2157 QLA2XXX_DRIVER_NAME)) { 2158 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2159 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2160 pci_name(ha->pdev)); 2161 2162 goto iospace_error_exit; 2163 } 2164 2165 /* Use MMIO operations for all accesses. */ 2166 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2167 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2168 "Invalid pci I/O region size (%s).\n", 2169 pci_name(ha->pdev)); 2170 goto iospace_error_exit; 2171 } 2172 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2173 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2174 "Invalid PCI mem region size (%s), aborting\n", 2175 pci_name(ha->pdev)); 2176 goto iospace_error_exit; 2177 } 2178 2179 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2180 if (!ha->iobase) { 2181 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2182 "Cannot remap MMIO (%s), aborting.\n", 2183 pci_name(ha->pdev)); 2184 goto iospace_error_exit; 2185 } 2186 2187 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2188 /* 83XX 26XX always use MQ type access for queues 2189 * - mbar 2, a.k.a region 4 */ 2190 ha->max_req_queues = ha->max_rsp_queues = 1; 2191 ha->msix_count = QLA_BASE_VECTORS; 2192 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2193 pci_resource_len(ha->pdev, 4)); 2194 2195 if (!ha->mqiobase) { 2196 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2197 "BAR2/region4 not enabled\n"); 2198 goto mqiobase_exit; 2199 } 2200 2201 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2202 pci_resource_len(ha->pdev, 2)); 2203 if (ha->msixbase) { 2204 /* Read MSIX vector size of the board */ 2205 pci_read_config_word(ha->pdev, 2206 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2207 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2208 /* 2209 * By default, driver uses at least two msix vectors 2210 * (default & rspq) 2211 */ 2212 if (ql2xmqsupport || ql2xnvmeenable) { 2213 /* MB interrupt uses 1 vector */ 2214 ha->max_req_queues = ha->msix_count - 1; 2215 2216 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2217 if (QLA_TGT_MODE_ENABLED()) 2218 ha->max_req_queues--; 2219 2220 ha->max_rsp_queues = ha->max_req_queues; 2221 2222 /* Queue pairs is the max value minus 2223 * the base queue pair */ 2224 ha->max_qpairs = ha->max_req_queues - 1; 2225 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2226 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2227 } 2228 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2229 "MSI-X vector count: %d.\n", ha->msix_count); 2230 } else 2231 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2232 "BAR 1 not enabled.\n"); 2233 2234 mqiobase_exit: 2235 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2236 "MSIX Count: %d.\n", ha->msix_count); 2237 return 0; 2238 2239 iospace_error_exit: 2240 return -ENOMEM; 2241 } 2242 2243 static struct isp_operations qla2100_isp_ops = { 2244 .pci_config = qla2100_pci_config, 2245 .reset_chip = qla2x00_reset_chip, 2246 .chip_diag = qla2x00_chip_diag, 2247 .config_rings = qla2x00_config_rings, 2248 .reset_adapter = qla2x00_reset_adapter, 2249 .nvram_config = qla2x00_nvram_config, 2250 .update_fw_options = qla2x00_update_fw_options, 2251 .load_risc = qla2x00_load_risc, 2252 .pci_info_str = qla2x00_pci_info_str, 2253 .fw_version_str = qla2x00_fw_version_str, 2254 .intr_handler = qla2100_intr_handler, 2255 .enable_intrs = qla2x00_enable_intrs, 2256 .disable_intrs = qla2x00_disable_intrs, 2257 .abort_command = qla2x00_abort_command, 2258 .target_reset = qla2x00_abort_target, 2259 .lun_reset = qla2x00_lun_reset, 2260 .fabric_login = qla2x00_login_fabric, 2261 .fabric_logout = qla2x00_fabric_logout, 2262 .calc_req_entries = qla2x00_calc_iocbs_32, 2263 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2264 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2265 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2266 .read_nvram = qla2x00_read_nvram_data, 2267 .write_nvram = qla2x00_write_nvram_data, 2268 .fw_dump = qla2100_fw_dump, 2269 .beacon_on = NULL, 2270 .beacon_off = NULL, 2271 .beacon_blink = NULL, 2272 .read_optrom = qla2x00_read_optrom_data, 2273 .write_optrom = qla2x00_write_optrom_data, 2274 .get_flash_version = qla2x00_get_flash_version, 2275 .start_scsi = qla2x00_start_scsi, 2276 .start_scsi_mq = NULL, 2277 .abort_isp = qla2x00_abort_isp, 2278 .iospace_config = qla2x00_iospace_config, 2279 .initialize_adapter = qla2x00_initialize_adapter, 2280 }; 2281 2282 static struct isp_operations qla2300_isp_ops = { 2283 .pci_config = qla2300_pci_config, 2284 .reset_chip = qla2x00_reset_chip, 2285 .chip_diag = qla2x00_chip_diag, 2286 .config_rings = qla2x00_config_rings, 2287 .reset_adapter = qla2x00_reset_adapter, 2288 .nvram_config = qla2x00_nvram_config, 2289 .update_fw_options = qla2x00_update_fw_options, 2290 .load_risc = qla2x00_load_risc, 2291 .pci_info_str = qla2x00_pci_info_str, 2292 .fw_version_str = qla2x00_fw_version_str, 2293 .intr_handler = qla2300_intr_handler, 2294 .enable_intrs = qla2x00_enable_intrs, 2295 .disable_intrs = qla2x00_disable_intrs, 2296 .abort_command = qla2x00_abort_command, 2297 .target_reset = qla2x00_abort_target, 2298 .lun_reset = qla2x00_lun_reset, 2299 .fabric_login = qla2x00_login_fabric, 2300 .fabric_logout = qla2x00_fabric_logout, 2301 .calc_req_entries = qla2x00_calc_iocbs_32, 2302 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2303 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2304 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2305 .read_nvram = qla2x00_read_nvram_data, 2306 .write_nvram = qla2x00_write_nvram_data, 2307 .fw_dump = qla2300_fw_dump, 2308 .beacon_on = qla2x00_beacon_on, 2309 .beacon_off = qla2x00_beacon_off, 2310 .beacon_blink = qla2x00_beacon_blink, 2311 .read_optrom = qla2x00_read_optrom_data, 2312 .write_optrom = qla2x00_write_optrom_data, 2313 .get_flash_version = qla2x00_get_flash_version, 2314 .start_scsi = qla2x00_start_scsi, 2315 .start_scsi_mq = NULL, 2316 .abort_isp = qla2x00_abort_isp, 2317 .iospace_config = qla2x00_iospace_config, 2318 .initialize_adapter = qla2x00_initialize_adapter, 2319 }; 2320 2321 static struct isp_operations qla24xx_isp_ops = { 2322 .pci_config = qla24xx_pci_config, 2323 .reset_chip = qla24xx_reset_chip, 2324 .chip_diag = qla24xx_chip_diag, 2325 .config_rings = qla24xx_config_rings, 2326 .reset_adapter = qla24xx_reset_adapter, 2327 .nvram_config = qla24xx_nvram_config, 2328 .update_fw_options = qla24xx_update_fw_options, 2329 .load_risc = qla24xx_load_risc, 2330 .pci_info_str = qla24xx_pci_info_str, 2331 .fw_version_str = qla24xx_fw_version_str, 2332 .intr_handler = qla24xx_intr_handler, 2333 .enable_intrs = qla24xx_enable_intrs, 2334 .disable_intrs = qla24xx_disable_intrs, 2335 .abort_command = qla24xx_abort_command, 2336 .target_reset = qla24xx_abort_target, 2337 .lun_reset = qla24xx_lun_reset, 2338 .fabric_login = qla24xx_login_fabric, 2339 .fabric_logout = qla24xx_fabric_logout, 2340 .calc_req_entries = NULL, 2341 .build_iocbs = NULL, 2342 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2343 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2344 .read_nvram = qla24xx_read_nvram_data, 2345 .write_nvram = qla24xx_write_nvram_data, 2346 .fw_dump = qla24xx_fw_dump, 2347 .beacon_on = qla24xx_beacon_on, 2348 .beacon_off = qla24xx_beacon_off, 2349 .beacon_blink = qla24xx_beacon_blink, 2350 .read_optrom = qla24xx_read_optrom_data, 2351 .write_optrom = qla24xx_write_optrom_data, 2352 .get_flash_version = qla24xx_get_flash_version, 2353 .start_scsi = qla24xx_start_scsi, 2354 .start_scsi_mq = NULL, 2355 .abort_isp = qla2x00_abort_isp, 2356 .iospace_config = qla2x00_iospace_config, 2357 .initialize_adapter = qla2x00_initialize_adapter, 2358 }; 2359 2360 static struct isp_operations qla25xx_isp_ops = { 2361 .pci_config = qla25xx_pci_config, 2362 .reset_chip = qla24xx_reset_chip, 2363 .chip_diag = qla24xx_chip_diag, 2364 .config_rings = qla24xx_config_rings, 2365 .reset_adapter = qla24xx_reset_adapter, 2366 .nvram_config = qla24xx_nvram_config, 2367 .update_fw_options = qla24xx_update_fw_options, 2368 .load_risc = qla24xx_load_risc, 2369 .pci_info_str = qla24xx_pci_info_str, 2370 .fw_version_str = qla24xx_fw_version_str, 2371 .intr_handler = qla24xx_intr_handler, 2372 .enable_intrs = qla24xx_enable_intrs, 2373 .disable_intrs = qla24xx_disable_intrs, 2374 .abort_command = qla24xx_abort_command, 2375 .target_reset = qla24xx_abort_target, 2376 .lun_reset = qla24xx_lun_reset, 2377 .fabric_login = qla24xx_login_fabric, 2378 .fabric_logout = qla24xx_fabric_logout, 2379 .calc_req_entries = NULL, 2380 .build_iocbs = NULL, 2381 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2382 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2383 .read_nvram = qla25xx_read_nvram_data, 2384 .write_nvram = qla25xx_write_nvram_data, 2385 .fw_dump = qla25xx_fw_dump, 2386 .beacon_on = qla24xx_beacon_on, 2387 .beacon_off = qla24xx_beacon_off, 2388 .beacon_blink = qla24xx_beacon_blink, 2389 .read_optrom = qla25xx_read_optrom_data, 2390 .write_optrom = qla24xx_write_optrom_data, 2391 .get_flash_version = qla24xx_get_flash_version, 2392 .start_scsi = qla24xx_dif_start_scsi, 2393 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2394 .abort_isp = qla2x00_abort_isp, 2395 .iospace_config = qla2x00_iospace_config, 2396 .initialize_adapter = qla2x00_initialize_adapter, 2397 }; 2398 2399 static struct isp_operations qla81xx_isp_ops = { 2400 .pci_config = qla25xx_pci_config, 2401 .reset_chip = qla24xx_reset_chip, 2402 .chip_diag = qla24xx_chip_diag, 2403 .config_rings = qla24xx_config_rings, 2404 .reset_adapter = qla24xx_reset_adapter, 2405 .nvram_config = qla81xx_nvram_config, 2406 .update_fw_options = qla24xx_update_fw_options, 2407 .load_risc = qla81xx_load_risc, 2408 .pci_info_str = qla24xx_pci_info_str, 2409 .fw_version_str = qla24xx_fw_version_str, 2410 .intr_handler = qla24xx_intr_handler, 2411 .enable_intrs = qla24xx_enable_intrs, 2412 .disable_intrs = qla24xx_disable_intrs, 2413 .abort_command = qla24xx_abort_command, 2414 .target_reset = qla24xx_abort_target, 2415 .lun_reset = qla24xx_lun_reset, 2416 .fabric_login = qla24xx_login_fabric, 2417 .fabric_logout = qla24xx_fabric_logout, 2418 .calc_req_entries = NULL, 2419 .build_iocbs = NULL, 2420 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2421 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2422 .read_nvram = NULL, 2423 .write_nvram = NULL, 2424 .fw_dump = qla81xx_fw_dump, 2425 .beacon_on = qla24xx_beacon_on, 2426 .beacon_off = qla24xx_beacon_off, 2427 .beacon_blink = qla83xx_beacon_blink, 2428 .read_optrom = qla25xx_read_optrom_data, 2429 .write_optrom = qla24xx_write_optrom_data, 2430 .get_flash_version = qla24xx_get_flash_version, 2431 .start_scsi = qla24xx_dif_start_scsi, 2432 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2433 .abort_isp = qla2x00_abort_isp, 2434 .iospace_config = qla2x00_iospace_config, 2435 .initialize_adapter = qla2x00_initialize_adapter, 2436 }; 2437 2438 static struct isp_operations qla82xx_isp_ops = { 2439 .pci_config = qla82xx_pci_config, 2440 .reset_chip = qla82xx_reset_chip, 2441 .chip_diag = qla24xx_chip_diag, 2442 .config_rings = qla82xx_config_rings, 2443 .reset_adapter = qla24xx_reset_adapter, 2444 .nvram_config = qla81xx_nvram_config, 2445 .update_fw_options = qla24xx_update_fw_options, 2446 .load_risc = qla82xx_load_risc, 2447 .pci_info_str = qla24xx_pci_info_str, 2448 .fw_version_str = qla24xx_fw_version_str, 2449 .intr_handler = qla82xx_intr_handler, 2450 .enable_intrs = qla82xx_enable_intrs, 2451 .disable_intrs = qla82xx_disable_intrs, 2452 .abort_command = qla24xx_abort_command, 2453 .target_reset = qla24xx_abort_target, 2454 .lun_reset = qla24xx_lun_reset, 2455 .fabric_login = qla24xx_login_fabric, 2456 .fabric_logout = qla24xx_fabric_logout, 2457 .calc_req_entries = NULL, 2458 .build_iocbs = NULL, 2459 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2460 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2461 .read_nvram = qla24xx_read_nvram_data, 2462 .write_nvram = qla24xx_write_nvram_data, 2463 .fw_dump = qla82xx_fw_dump, 2464 .beacon_on = qla82xx_beacon_on, 2465 .beacon_off = qla82xx_beacon_off, 2466 .beacon_blink = NULL, 2467 .read_optrom = qla82xx_read_optrom_data, 2468 .write_optrom = qla82xx_write_optrom_data, 2469 .get_flash_version = qla82xx_get_flash_version, 2470 .start_scsi = qla82xx_start_scsi, 2471 .start_scsi_mq = NULL, 2472 .abort_isp = qla82xx_abort_isp, 2473 .iospace_config = qla82xx_iospace_config, 2474 .initialize_adapter = qla2x00_initialize_adapter, 2475 }; 2476 2477 static struct isp_operations qla8044_isp_ops = { 2478 .pci_config = qla82xx_pci_config, 2479 .reset_chip = qla82xx_reset_chip, 2480 .chip_diag = qla24xx_chip_diag, 2481 .config_rings = qla82xx_config_rings, 2482 .reset_adapter = qla24xx_reset_adapter, 2483 .nvram_config = qla81xx_nvram_config, 2484 .update_fw_options = qla24xx_update_fw_options, 2485 .load_risc = qla82xx_load_risc, 2486 .pci_info_str = qla24xx_pci_info_str, 2487 .fw_version_str = qla24xx_fw_version_str, 2488 .intr_handler = qla8044_intr_handler, 2489 .enable_intrs = qla82xx_enable_intrs, 2490 .disable_intrs = qla82xx_disable_intrs, 2491 .abort_command = qla24xx_abort_command, 2492 .target_reset = qla24xx_abort_target, 2493 .lun_reset = qla24xx_lun_reset, 2494 .fabric_login = qla24xx_login_fabric, 2495 .fabric_logout = qla24xx_fabric_logout, 2496 .calc_req_entries = NULL, 2497 .build_iocbs = NULL, 2498 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2499 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2500 .read_nvram = NULL, 2501 .write_nvram = NULL, 2502 .fw_dump = qla8044_fw_dump, 2503 .beacon_on = qla82xx_beacon_on, 2504 .beacon_off = qla82xx_beacon_off, 2505 .beacon_blink = NULL, 2506 .read_optrom = qla8044_read_optrom_data, 2507 .write_optrom = qla8044_write_optrom_data, 2508 .get_flash_version = qla82xx_get_flash_version, 2509 .start_scsi = qla82xx_start_scsi, 2510 .start_scsi_mq = NULL, 2511 .abort_isp = qla8044_abort_isp, 2512 .iospace_config = qla82xx_iospace_config, 2513 .initialize_adapter = qla2x00_initialize_adapter, 2514 }; 2515 2516 static struct isp_operations qla83xx_isp_ops = { 2517 .pci_config = qla25xx_pci_config, 2518 .reset_chip = qla24xx_reset_chip, 2519 .chip_diag = qla24xx_chip_diag, 2520 .config_rings = qla24xx_config_rings, 2521 .reset_adapter = qla24xx_reset_adapter, 2522 .nvram_config = qla81xx_nvram_config, 2523 .update_fw_options = qla24xx_update_fw_options, 2524 .load_risc = qla81xx_load_risc, 2525 .pci_info_str = qla24xx_pci_info_str, 2526 .fw_version_str = qla24xx_fw_version_str, 2527 .intr_handler = qla24xx_intr_handler, 2528 .enable_intrs = qla24xx_enable_intrs, 2529 .disable_intrs = qla24xx_disable_intrs, 2530 .abort_command = qla24xx_abort_command, 2531 .target_reset = qla24xx_abort_target, 2532 .lun_reset = qla24xx_lun_reset, 2533 .fabric_login = qla24xx_login_fabric, 2534 .fabric_logout = qla24xx_fabric_logout, 2535 .calc_req_entries = NULL, 2536 .build_iocbs = NULL, 2537 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2538 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2539 .read_nvram = NULL, 2540 .write_nvram = NULL, 2541 .fw_dump = qla83xx_fw_dump, 2542 .beacon_on = qla24xx_beacon_on, 2543 .beacon_off = qla24xx_beacon_off, 2544 .beacon_blink = qla83xx_beacon_blink, 2545 .read_optrom = qla25xx_read_optrom_data, 2546 .write_optrom = qla24xx_write_optrom_data, 2547 .get_flash_version = qla24xx_get_flash_version, 2548 .start_scsi = qla24xx_dif_start_scsi, 2549 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2550 .abort_isp = qla2x00_abort_isp, 2551 .iospace_config = qla83xx_iospace_config, 2552 .initialize_adapter = qla2x00_initialize_adapter, 2553 }; 2554 2555 static struct isp_operations qlafx00_isp_ops = { 2556 .pci_config = qlafx00_pci_config, 2557 .reset_chip = qlafx00_soft_reset, 2558 .chip_diag = qlafx00_chip_diag, 2559 .config_rings = qlafx00_config_rings, 2560 .reset_adapter = qlafx00_soft_reset, 2561 .nvram_config = NULL, 2562 .update_fw_options = NULL, 2563 .load_risc = NULL, 2564 .pci_info_str = qlafx00_pci_info_str, 2565 .fw_version_str = qlafx00_fw_version_str, 2566 .intr_handler = qlafx00_intr_handler, 2567 .enable_intrs = qlafx00_enable_intrs, 2568 .disable_intrs = qlafx00_disable_intrs, 2569 .abort_command = qla24xx_async_abort_command, 2570 .target_reset = qlafx00_abort_target, 2571 .lun_reset = qlafx00_lun_reset, 2572 .fabric_login = NULL, 2573 .fabric_logout = NULL, 2574 .calc_req_entries = NULL, 2575 .build_iocbs = NULL, 2576 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2577 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2578 .read_nvram = qla24xx_read_nvram_data, 2579 .write_nvram = qla24xx_write_nvram_data, 2580 .fw_dump = NULL, 2581 .beacon_on = qla24xx_beacon_on, 2582 .beacon_off = qla24xx_beacon_off, 2583 .beacon_blink = NULL, 2584 .read_optrom = qla24xx_read_optrom_data, 2585 .write_optrom = qla24xx_write_optrom_data, 2586 .get_flash_version = qla24xx_get_flash_version, 2587 .start_scsi = qlafx00_start_scsi, 2588 .start_scsi_mq = NULL, 2589 .abort_isp = qlafx00_abort_isp, 2590 .iospace_config = qlafx00_iospace_config, 2591 .initialize_adapter = qlafx00_initialize_adapter, 2592 }; 2593 2594 static struct isp_operations qla27xx_isp_ops = { 2595 .pci_config = qla25xx_pci_config, 2596 .reset_chip = qla24xx_reset_chip, 2597 .chip_diag = qla24xx_chip_diag, 2598 .config_rings = qla24xx_config_rings, 2599 .reset_adapter = qla24xx_reset_adapter, 2600 .nvram_config = qla81xx_nvram_config, 2601 .update_fw_options = qla24xx_update_fw_options, 2602 .load_risc = qla81xx_load_risc, 2603 .pci_info_str = qla24xx_pci_info_str, 2604 .fw_version_str = qla24xx_fw_version_str, 2605 .intr_handler = qla24xx_intr_handler, 2606 .enable_intrs = qla24xx_enable_intrs, 2607 .disable_intrs = qla24xx_disable_intrs, 2608 .abort_command = qla24xx_abort_command, 2609 .target_reset = qla24xx_abort_target, 2610 .lun_reset = qla24xx_lun_reset, 2611 .fabric_login = qla24xx_login_fabric, 2612 .fabric_logout = qla24xx_fabric_logout, 2613 .calc_req_entries = NULL, 2614 .build_iocbs = NULL, 2615 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2616 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2617 .read_nvram = NULL, 2618 .write_nvram = NULL, 2619 .fw_dump = qla27xx_fwdump, 2620 .mpi_fw_dump = qla27xx_mpi_fwdump, 2621 .beacon_on = qla24xx_beacon_on, 2622 .beacon_off = qla24xx_beacon_off, 2623 .beacon_blink = qla83xx_beacon_blink, 2624 .read_optrom = qla25xx_read_optrom_data, 2625 .write_optrom = qla24xx_write_optrom_data, 2626 .get_flash_version = qla24xx_get_flash_version, 2627 .start_scsi = qla24xx_dif_start_scsi, 2628 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2629 .abort_isp = qla2x00_abort_isp, 2630 .iospace_config = qla83xx_iospace_config, 2631 .initialize_adapter = qla2x00_initialize_adapter, 2632 }; 2633 2634 static inline void 2635 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2636 { 2637 ha->device_type = DT_EXTENDED_IDS; 2638 switch (ha->pdev->device) { 2639 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2640 ha->isp_type |= DT_ISP2100; 2641 ha->device_type &= ~DT_EXTENDED_IDS; 2642 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2643 break; 2644 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2645 ha->isp_type |= DT_ISP2200; 2646 ha->device_type &= ~DT_EXTENDED_IDS; 2647 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2648 break; 2649 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2650 ha->isp_type |= DT_ISP2300; 2651 ha->device_type |= DT_ZIO_SUPPORTED; 2652 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2653 break; 2654 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2655 ha->isp_type |= DT_ISP2312; 2656 ha->device_type |= DT_ZIO_SUPPORTED; 2657 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2658 break; 2659 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2660 ha->isp_type |= DT_ISP2322; 2661 ha->device_type |= DT_ZIO_SUPPORTED; 2662 if (ha->pdev->subsystem_vendor == 0x1028 && 2663 ha->pdev->subsystem_device == 0x0170) 2664 ha->device_type |= DT_OEM_001; 2665 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2666 break; 2667 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2668 ha->isp_type |= DT_ISP6312; 2669 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2670 break; 2671 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2672 ha->isp_type |= DT_ISP6322; 2673 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2674 break; 2675 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2676 ha->isp_type |= DT_ISP2422; 2677 ha->device_type |= DT_ZIO_SUPPORTED; 2678 ha->device_type |= DT_FWI2; 2679 ha->device_type |= DT_IIDMA; 2680 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2681 break; 2682 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2683 ha->isp_type |= DT_ISP2432; 2684 ha->device_type |= DT_ZIO_SUPPORTED; 2685 ha->device_type |= DT_FWI2; 2686 ha->device_type |= DT_IIDMA; 2687 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2688 break; 2689 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2690 ha->isp_type |= DT_ISP8432; 2691 ha->device_type |= DT_ZIO_SUPPORTED; 2692 ha->device_type |= DT_FWI2; 2693 ha->device_type |= DT_IIDMA; 2694 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2695 break; 2696 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2697 ha->isp_type |= DT_ISP5422; 2698 ha->device_type |= DT_FWI2; 2699 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2700 break; 2701 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2702 ha->isp_type |= DT_ISP5432; 2703 ha->device_type |= DT_FWI2; 2704 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2705 break; 2706 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2707 ha->isp_type |= DT_ISP2532; 2708 ha->device_type |= DT_ZIO_SUPPORTED; 2709 ha->device_type |= DT_FWI2; 2710 ha->device_type |= DT_IIDMA; 2711 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2712 break; 2713 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2714 ha->isp_type |= DT_ISP8001; 2715 ha->device_type |= DT_ZIO_SUPPORTED; 2716 ha->device_type |= DT_FWI2; 2717 ha->device_type |= DT_IIDMA; 2718 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2719 break; 2720 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2721 ha->isp_type |= DT_ISP8021; 2722 ha->device_type |= DT_ZIO_SUPPORTED; 2723 ha->device_type |= DT_FWI2; 2724 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2725 /* Initialize 82XX ISP flags */ 2726 qla82xx_init_flags(ha); 2727 break; 2728 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2729 ha->isp_type |= DT_ISP8044; 2730 ha->device_type |= DT_ZIO_SUPPORTED; 2731 ha->device_type |= DT_FWI2; 2732 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2733 /* Initialize 82XX ISP flags */ 2734 qla82xx_init_flags(ha); 2735 break; 2736 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2737 ha->isp_type |= DT_ISP2031; 2738 ha->device_type |= DT_ZIO_SUPPORTED; 2739 ha->device_type |= DT_FWI2; 2740 ha->device_type |= DT_IIDMA; 2741 ha->device_type |= DT_T10_PI; 2742 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2743 break; 2744 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2745 ha->isp_type |= DT_ISP8031; 2746 ha->device_type |= DT_ZIO_SUPPORTED; 2747 ha->device_type |= DT_FWI2; 2748 ha->device_type |= DT_IIDMA; 2749 ha->device_type |= DT_T10_PI; 2750 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2751 break; 2752 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2753 ha->isp_type |= DT_ISPFX00; 2754 break; 2755 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2756 ha->isp_type |= DT_ISP2071; 2757 ha->device_type |= DT_ZIO_SUPPORTED; 2758 ha->device_type |= DT_FWI2; 2759 ha->device_type |= DT_IIDMA; 2760 ha->device_type |= DT_T10_PI; 2761 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2762 break; 2763 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2764 ha->isp_type |= DT_ISP2271; 2765 ha->device_type |= DT_ZIO_SUPPORTED; 2766 ha->device_type |= DT_FWI2; 2767 ha->device_type |= DT_IIDMA; 2768 ha->device_type |= DT_T10_PI; 2769 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2770 break; 2771 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2772 ha->isp_type |= DT_ISP2261; 2773 ha->device_type |= DT_ZIO_SUPPORTED; 2774 ha->device_type |= DT_FWI2; 2775 ha->device_type |= DT_IIDMA; 2776 ha->device_type |= DT_T10_PI; 2777 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2778 break; 2779 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2780 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2781 ha->isp_type |= DT_ISP2081; 2782 ha->device_type |= DT_ZIO_SUPPORTED; 2783 ha->device_type |= DT_FWI2; 2784 ha->device_type |= DT_IIDMA; 2785 ha->device_type |= DT_T10_PI; 2786 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2787 break; 2788 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2789 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2790 ha->isp_type |= DT_ISP2281; 2791 ha->device_type |= DT_ZIO_SUPPORTED; 2792 ha->device_type |= DT_FWI2; 2793 ha->device_type |= DT_IIDMA; 2794 ha->device_type |= DT_T10_PI; 2795 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2796 break; 2797 } 2798 2799 if (IS_QLA82XX(ha)) 2800 ha->port_no = ha->portnum & 1; 2801 else { 2802 /* Get adapter physical port no from interrupt pin register. */ 2803 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2804 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2805 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2806 ha->port_no--; 2807 else 2808 ha->port_no = !(ha->port_no & 1); 2809 } 2810 2811 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2812 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2813 ha->device_type, ha->port_no, ha->fw_srisc_address); 2814 } 2815 2816 static void 2817 qla2xxx_scan_start(struct Scsi_Host *shost) 2818 { 2819 scsi_qla_host_t *vha = shost_priv(shost); 2820 2821 if (vha->hw->flags.running_gold_fw) 2822 return; 2823 2824 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2825 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2826 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2827 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2828 } 2829 2830 static int 2831 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2832 { 2833 scsi_qla_host_t *vha = shost_priv(shost); 2834 2835 if (test_bit(UNLOADING, &vha->dpc_flags)) 2836 return 1; 2837 if (!vha->host) 2838 return 1; 2839 if (time > vha->hw->loop_reset_delay * HZ) 2840 return 1; 2841 2842 return atomic_read(&vha->loop_state) == LOOP_READY; 2843 } 2844 2845 static void qla_heartbeat_work_fn(struct work_struct *work) 2846 { 2847 struct qla_hw_data *ha = container_of(work, 2848 struct qla_hw_data, heartbeat_work); 2849 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2850 2851 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2852 qla_no_op_mb(base_vha); 2853 } 2854 2855 static void qla2x00_iocb_work_fn(struct work_struct *work) 2856 { 2857 struct scsi_qla_host *vha = container_of(work, 2858 struct scsi_qla_host, iocb_work); 2859 struct qla_hw_data *ha = vha->hw; 2860 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2861 int i = 2; 2862 unsigned long flags; 2863 2864 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2865 return; 2866 2867 while (!list_empty(&vha->work_list) && i > 0) { 2868 qla2x00_do_work(vha); 2869 i--; 2870 } 2871 2872 spin_lock_irqsave(&vha->work_lock, flags); 2873 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2874 spin_unlock_irqrestore(&vha->work_lock, flags); 2875 } 2876 2877 static void 2878 qla_trace_init(void) 2879 { 2880 qla_trc_array = trace_array_get_by_name("qla2xxx"); 2881 if (!qla_trc_array) { 2882 ql_log(ql_log_fatal, NULL, 0x0001, 2883 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n"); 2884 return; 2885 } 2886 2887 QLA_TRACE_ENABLE(qla_trc_array); 2888 } 2889 2890 static void 2891 qla_trace_uninit(void) 2892 { 2893 if (!qla_trc_array) 2894 return; 2895 trace_array_put(qla_trc_array); 2896 } 2897 2898 /* 2899 * PCI driver interface 2900 */ 2901 static int 2902 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2903 { 2904 int ret = -ENODEV; 2905 struct Scsi_Host *host; 2906 scsi_qla_host_t *base_vha = NULL; 2907 struct qla_hw_data *ha; 2908 char pci_info[30]; 2909 char fw_str[30], wq_name[30]; 2910 struct scsi_host_template *sht; 2911 int bars, mem_only = 0; 2912 uint16_t req_length = 0, rsp_length = 0; 2913 struct req_que *req = NULL; 2914 struct rsp_que *rsp = NULL; 2915 int i; 2916 2917 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2918 sht = &qla2xxx_driver_template; 2919 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2920 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2921 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2922 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2923 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2929 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2930 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2938 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2939 mem_only = 1; 2940 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2941 "Mem only adapter.\n"); 2942 } 2943 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2944 "Bars=%d.\n", bars); 2945 2946 if (mem_only) { 2947 if (pci_enable_device_mem(pdev)) 2948 return ret; 2949 } else { 2950 if (pci_enable_device(pdev)) 2951 return ret; 2952 } 2953 2954 if (is_kdump_kernel()) { 2955 ql2xmqsupport = 0; 2956 ql2xallocfwdump = 0; 2957 } 2958 2959 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2960 if (!ha) { 2961 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2962 "Unable to allocate memory for ha.\n"); 2963 goto disable_device; 2964 } 2965 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2966 "Memory allocated for ha=%p.\n", ha); 2967 ha->pdev = pdev; 2968 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2969 spin_lock_init(&ha->tgt.q_full_lock); 2970 spin_lock_init(&ha->tgt.sess_lock); 2971 spin_lock_init(&ha->tgt.atio_lock); 2972 2973 spin_lock_init(&ha->sadb_lock); 2974 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2975 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2976 2977 spin_lock_init(&ha->sadb_fp_lock); 2978 2979 if (qla_edif_sadb_build_free_pool(ha)) { 2980 kfree(ha); 2981 goto disable_device; 2982 } 2983 2984 atomic_set(&ha->nvme_active_aen_cnt, 0); 2985 2986 /* Clear our data area */ 2987 ha->bars = bars; 2988 ha->mem_only = mem_only; 2989 spin_lock_init(&ha->hardware_lock); 2990 spin_lock_init(&ha->vport_slock); 2991 mutex_init(&ha->selflogin_lock); 2992 mutex_init(&ha->optrom_mutex); 2993 2994 /* Set ISP-type information. */ 2995 qla2x00_set_isp_flags(ha); 2996 2997 /* Set EEH reset type to fundamental if required by hba */ 2998 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2999 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3000 pdev->needs_freset = 1; 3001 3002 ha->prev_topology = 0; 3003 ha->init_cb_size = sizeof(init_cb_t); 3004 ha->link_data_rate = PORT_SPEED_UNKNOWN; 3005 ha->optrom_size = OPTROM_SIZE_2300; 3006 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 3007 atomic_set(&ha->num_pend_mbx_stage1, 0); 3008 atomic_set(&ha->num_pend_mbx_stage2, 0); 3009 atomic_set(&ha->num_pend_mbx_stage3, 0); 3010 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 3011 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 3012 3013 /* Assign ISP specific operations. */ 3014 if (IS_QLA2100(ha)) { 3015 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3016 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 3017 req_length = REQUEST_ENTRY_CNT_2100; 3018 rsp_length = RESPONSE_ENTRY_CNT_2100; 3019 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3020 ha->gid_list_info_size = 4; 3021 ha->flash_conf_off = ~0; 3022 ha->flash_data_off = ~0; 3023 ha->nvram_conf_off = ~0; 3024 ha->nvram_data_off = ~0; 3025 ha->isp_ops = &qla2100_isp_ops; 3026 } else if (IS_QLA2200(ha)) { 3027 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3028 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 3029 req_length = REQUEST_ENTRY_CNT_2200; 3030 rsp_length = RESPONSE_ENTRY_CNT_2100; 3031 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3032 ha->gid_list_info_size = 4; 3033 ha->flash_conf_off = ~0; 3034 ha->flash_data_off = ~0; 3035 ha->nvram_conf_off = ~0; 3036 ha->nvram_data_off = ~0; 3037 ha->isp_ops = &qla2100_isp_ops; 3038 } else if (IS_QLA23XX(ha)) { 3039 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3040 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3041 req_length = REQUEST_ENTRY_CNT_2200; 3042 rsp_length = RESPONSE_ENTRY_CNT_2300; 3043 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3044 ha->gid_list_info_size = 6; 3045 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3046 ha->optrom_size = OPTROM_SIZE_2322; 3047 ha->flash_conf_off = ~0; 3048 ha->flash_data_off = ~0; 3049 ha->nvram_conf_off = ~0; 3050 ha->nvram_data_off = ~0; 3051 ha->isp_ops = &qla2300_isp_ops; 3052 } else if (IS_QLA24XX_TYPE(ha)) { 3053 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3054 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3055 req_length = REQUEST_ENTRY_CNT_24XX; 3056 rsp_length = RESPONSE_ENTRY_CNT_2300; 3057 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3058 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3059 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3060 ha->gid_list_info_size = 8; 3061 ha->optrom_size = OPTROM_SIZE_24XX; 3062 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 3063 ha->isp_ops = &qla24xx_isp_ops; 3064 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3065 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3066 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3067 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3068 } else if (IS_QLA25XX(ha)) { 3069 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3070 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3071 req_length = REQUEST_ENTRY_CNT_24XX; 3072 rsp_length = RESPONSE_ENTRY_CNT_2300; 3073 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3074 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3075 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3076 ha->gid_list_info_size = 8; 3077 ha->optrom_size = OPTROM_SIZE_25XX; 3078 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3079 ha->isp_ops = &qla25xx_isp_ops; 3080 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3081 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3082 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3083 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3084 } else if (IS_QLA81XX(ha)) { 3085 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3086 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3087 req_length = REQUEST_ENTRY_CNT_24XX; 3088 rsp_length = RESPONSE_ENTRY_CNT_2300; 3089 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3090 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3091 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3092 ha->gid_list_info_size = 8; 3093 ha->optrom_size = OPTROM_SIZE_81XX; 3094 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3095 ha->isp_ops = &qla81xx_isp_ops; 3096 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3097 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3098 ha->nvram_conf_off = ~0; 3099 ha->nvram_data_off = ~0; 3100 } else if (IS_QLA82XX(ha)) { 3101 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3102 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3103 req_length = REQUEST_ENTRY_CNT_82XX; 3104 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3105 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3106 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3107 ha->gid_list_info_size = 8; 3108 ha->optrom_size = OPTROM_SIZE_82XX; 3109 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3110 ha->isp_ops = &qla82xx_isp_ops; 3111 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3112 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3113 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3114 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3115 } else if (IS_QLA8044(ha)) { 3116 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3117 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3118 req_length = REQUEST_ENTRY_CNT_82XX; 3119 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3120 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3121 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3122 ha->gid_list_info_size = 8; 3123 ha->optrom_size = OPTROM_SIZE_83XX; 3124 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3125 ha->isp_ops = &qla8044_isp_ops; 3126 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3127 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3128 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3129 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3130 } else if (IS_QLA83XX(ha)) { 3131 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3132 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3133 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3134 req_length = REQUEST_ENTRY_CNT_83XX; 3135 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3136 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3137 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3138 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3139 ha->gid_list_info_size = 8; 3140 ha->optrom_size = OPTROM_SIZE_83XX; 3141 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3142 ha->isp_ops = &qla83xx_isp_ops; 3143 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3144 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3145 ha->nvram_conf_off = ~0; 3146 ha->nvram_data_off = ~0; 3147 } else if (IS_QLAFX00(ha)) { 3148 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3149 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3150 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3151 req_length = REQUEST_ENTRY_CNT_FX00; 3152 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3153 ha->isp_ops = &qlafx00_isp_ops; 3154 ha->port_down_retry_count = 30; /* default value */ 3155 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3156 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3157 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3158 ha->mr.fw_hbt_en = 1; 3159 ha->mr.host_info_resend = false; 3160 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3161 } else if (IS_QLA27XX(ha)) { 3162 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3163 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3164 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3165 req_length = REQUEST_ENTRY_CNT_83XX; 3166 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3167 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3168 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3169 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3170 ha->gid_list_info_size = 8; 3171 ha->optrom_size = OPTROM_SIZE_83XX; 3172 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3173 ha->isp_ops = &qla27xx_isp_ops; 3174 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3175 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3176 ha->nvram_conf_off = ~0; 3177 ha->nvram_data_off = ~0; 3178 } else if (IS_QLA28XX(ha)) { 3179 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3180 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3181 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3182 req_length = REQUEST_ENTRY_CNT_83XX; 3183 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3184 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3185 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3186 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3187 ha->gid_list_info_size = 8; 3188 ha->optrom_size = OPTROM_SIZE_28XX; 3189 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3190 ha->isp_ops = &qla27xx_isp_ops; 3191 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3192 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3193 ha->nvram_conf_off = ~0; 3194 ha->nvram_data_off = ~0; 3195 } 3196 3197 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3198 "mbx_count=%d, req_length=%d, " 3199 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3200 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3201 "max_fibre_devices=%d.\n", 3202 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3203 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3204 ha->nvram_npiv_size, ha->max_fibre_devices); 3205 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3206 "isp_ops=%p, flash_conf_off=%d, " 3207 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3208 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3209 ha->nvram_conf_off, ha->nvram_data_off); 3210 3211 /* Configure PCI I/O space */ 3212 ret = ha->isp_ops->iospace_config(ha); 3213 if (ret) 3214 goto iospace_config_failed; 3215 3216 ql_log_pci(ql_log_info, pdev, 0x001d, 3217 "Found an ISP%04X irq %d iobase 0x%p.\n", 3218 pdev->device, pdev->irq, ha->iobase); 3219 mutex_init(&ha->vport_lock); 3220 mutex_init(&ha->mq_lock); 3221 init_completion(&ha->mbx_cmd_comp); 3222 complete(&ha->mbx_cmd_comp); 3223 init_completion(&ha->mbx_intr_comp); 3224 init_completion(&ha->dcbx_comp); 3225 init_completion(&ha->lb_portup_comp); 3226 3227 set_bit(0, (unsigned long *) ha->vp_idx_map); 3228 3229 qla2x00_config_dma_addressing(ha); 3230 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3231 "64 Bit addressing is %s.\n", 3232 ha->flags.enable_64bit_addressing ? "enable" : 3233 "disable"); 3234 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3235 if (ret) { 3236 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3237 "Failed to allocate memory for adapter, aborting.\n"); 3238 3239 goto probe_hw_failed; 3240 } 3241 3242 req->max_q_depth = MAX_Q_DEPTH; 3243 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3244 req->max_q_depth = ql2xmaxqdepth; 3245 3246 3247 base_vha = qla2x00_create_host(sht, ha); 3248 if (!base_vha) { 3249 ret = -ENOMEM; 3250 goto probe_hw_failed; 3251 } 3252 3253 pci_set_drvdata(pdev, base_vha); 3254 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3255 3256 host = base_vha->host; 3257 base_vha->req = req; 3258 if (IS_QLA2XXX_MIDTYPE(ha)) 3259 base_vha->mgmt_svr_loop_id = 3260 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3261 else 3262 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3263 base_vha->vp_idx; 3264 3265 /* Setup fcport template structure. */ 3266 ha->mr.fcport.vha = base_vha; 3267 ha->mr.fcport.port_type = FCT_UNKNOWN; 3268 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3269 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3270 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3271 ha->mr.fcport.scan_state = 1; 3272 3273 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3274 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3275 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3276 3277 /* Set the SG table size based on ISP type */ 3278 if (!IS_FWI2_CAPABLE(ha)) { 3279 if (IS_QLA2100(ha)) 3280 host->sg_tablesize = 32; 3281 } else { 3282 if (!IS_QLA82XX(ha)) 3283 host->sg_tablesize = QLA_SG_ALL; 3284 } 3285 host->max_id = ha->max_fibre_devices; 3286 host->cmd_per_lun = 3; 3287 host->unique_id = host->host_no; 3288 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3289 host->max_cmd_len = 32; 3290 else 3291 host->max_cmd_len = MAX_CMDSZ; 3292 host->max_channel = MAX_BUSES - 1; 3293 /* Older HBAs support only 16-bit LUNs */ 3294 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3295 ql2xmaxlun > 0xffff) 3296 host->max_lun = 0xffff; 3297 else 3298 host->max_lun = ql2xmaxlun; 3299 host->transportt = qla2xxx_transport_template; 3300 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3301 3302 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3303 "max_id=%d this_id=%d " 3304 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3305 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3306 host->this_id, host->cmd_per_lun, host->unique_id, 3307 host->max_cmd_len, host->max_channel, host->max_lun, 3308 host->transportt, sht->vendor_id); 3309 3310 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3311 3312 /* Set up the irqs */ 3313 ret = qla2x00_request_irqs(ha, rsp); 3314 if (ret) 3315 goto probe_failed; 3316 3317 /* Alloc arrays of request and response ring ptrs */ 3318 ret = qla2x00_alloc_queues(ha, req, rsp); 3319 if (ret) { 3320 ql_log(ql_log_fatal, base_vha, 0x003d, 3321 "Failed to allocate memory for queue pointers..." 3322 "aborting.\n"); 3323 ret = -ENODEV; 3324 goto probe_failed; 3325 } 3326 3327 if (ha->mqenable) { 3328 /* number of hardware queues supported by blk/scsi-mq*/ 3329 host->nr_hw_queues = ha->max_qpairs; 3330 3331 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3332 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3333 } else { 3334 if (ql2xnvmeenable) { 3335 host->nr_hw_queues = ha->max_qpairs; 3336 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3337 "FC-NVMe support is enabled, HW queues=%d\n", 3338 host->nr_hw_queues); 3339 } else { 3340 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3341 "blk/scsi-mq disabled.\n"); 3342 } 3343 } 3344 3345 qlt_probe_one_stage1(base_vha, ha); 3346 3347 pci_save_state(pdev); 3348 3349 /* Assign back pointers */ 3350 rsp->req = req; 3351 req->rsp = rsp; 3352 3353 if (IS_QLAFX00(ha)) { 3354 ha->rsp_q_map[0] = rsp; 3355 ha->req_q_map[0] = req; 3356 set_bit(0, ha->req_qid_map); 3357 set_bit(0, ha->rsp_qid_map); 3358 } 3359 3360 /* FWI2-capable only. */ 3361 req->req_q_in = &ha->iobase->isp24.req_q_in; 3362 req->req_q_out = &ha->iobase->isp24.req_q_out; 3363 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3364 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3365 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3366 IS_QLA28XX(ha)) { 3367 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3368 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3369 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3370 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3371 } 3372 3373 if (IS_QLAFX00(ha)) { 3374 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3375 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3376 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3377 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3378 } 3379 3380 if (IS_P3P_TYPE(ha)) { 3381 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3382 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3383 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3384 } 3385 3386 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3387 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3388 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3389 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3390 "req->req_q_in=%p req->req_q_out=%p " 3391 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3392 req->req_q_in, req->req_q_out, 3393 rsp->rsp_q_in, rsp->rsp_q_out); 3394 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3395 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3396 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3397 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3398 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3399 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3400 3401 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3402 if (unlikely(!ha->wq)) { 3403 ret = -ENOMEM; 3404 goto probe_failed; 3405 } 3406 3407 if (ha->isp_ops->initialize_adapter(base_vha)) { 3408 ql_log(ql_log_fatal, base_vha, 0x00d6, 3409 "Failed to initialize adapter - Adapter flags %x.\n", 3410 base_vha->device_flags); 3411 3412 if (IS_QLA82XX(ha)) { 3413 qla82xx_idc_lock(ha); 3414 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3415 QLA8XXX_DEV_FAILED); 3416 qla82xx_idc_unlock(ha); 3417 ql_log(ql_log_fatal, base_vha, 0x00d7, 3418 "HW State: FAILED.\n"); 3419 } else if (IS_QLA8044(ha)) { 3420 qla8044_idc_lock(ha); 3421 qla8044_wr_direct(base_vha, 3422 QLA8044_CRB_DEV_STATE_INDEX, 3423 QLA8XXX_DEV_FAILED); 3424 qla8044_idc_unlock(ha); 3425 ql_log(ql_log_fatal, base_vha, 0x0150, 3426 "HW State: FAILED.\n"); 3427 } 3428 3429 ret = -ENODEV; 3430 goto probe_failed; 3431 } 3432 3433 if (IS_QLAFX00(ha)) 3434 host->can_queue = QLAFX00_MAX_CANQUEUE; 3435 else 3436 host->can_queue = req->num_outstanding_cmds - 10; 3437 3438 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3439 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3440 host->can_queue, base_vha->req, 3441 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3442 3443 /* Check if FW supports MQ or not for ISP25xx */ 3444 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3445 ha->mqenable = 0; 3446 3447 if (ha->mqenable) { 3448 bool startit = false; 3449 3450 if (QLA_TGT_MODE_ENABLED()) 3451 startit = false; 3452 3453 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3454 startit = true; 3455 3456 /* Create start of day qpairs for Block MQ */ 3457 for (i = 0; i < ha->max_qpairs; i++) 3458 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3459 } 3460 qla_init_iocb_limit(base_vha); 3461 3462 if (ha->flags.running_gold_fw) 3463 goto skip_dpc; 3464 3465 /* 3466 * Startup the kernel thread for this host adapter 3467 */ 3468 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3469 "%s_dpc", base_vha->host_str); 3470 if (IS_ERR(ha->dpc_thread)) { 3471 ql_log(ql_log_fatal, base_vha, 0x00ed, 3472 "Failed to start DPC thread.\n"); 3473 ret = PTR_ERR(ha->dpc_thread); 3474 ha->dpc_thread = NULL; 3475 goto probe_failed; 3476 } 3477 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3478 "DPC thread started successfully.\n"); 3479 3480 /* 3481 * If we're not coming up in initiator mode, we might sit for 3482 * a while without waking up the dpc thread, which leads to a 3483 * stuck process warning. So just kick the dpc once here and 3484 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3485 */ 3486 qla2xxx_wake_dpc(base_vha); 3487 3488 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3489 3490 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3491 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3492 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3493 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3494 3495 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3496 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3497 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3498 INIT_WORK(&ha->idc_state_handler, 3499 qla83xx_idc_state_handler_work); 3500 INIT_WORK(&ha->nic_core_unrecoverable, 3501 qla83xx_nic_core_unrecoverable_work); 3502 } 3503 3504 skip_dpc: 3505 list_add_tail(&base_vha->list, &ha->vp_list); 3506 base_vha->host->irq = ha->pdev->irq; 3507 3508 /* Initialized the timer */ 3509 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3510 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3511 "Started qla2x00_timer with " 3512 "interval=%d.\n", WATCH_INTERVAL); 3513 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3514 "Detected hba at address=%p.\n", 3515 ha); 3516 3517 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3518 if (ha->fw_attributes & BIT_4) { 3519 int prot = 0, guard; 3520 3521 base_vha->flags.difdix_supported = 1; 3522 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3523 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3524 if (ql2xenabledif == 1) 3525 prot = SHOST_DIX_TYPE0_PROTECTION; 3526 if (ql2xprotmask) 3527 scsi_host_set_prot(host, ql2xprotmask); 3528 else 3529 scsi_host_set_prot(host, 3530 prot | SHOST_DIF_TYPE1_PROTECTION 3531 | SHOST_DIF_TYPE2_PROTECTION 3532 | SHOST_DIF_TYPE3_PROTECTION 3533 | SHOST_DIX_TYPE1_PROTECTION 3534 | SHOST_DIX_TYPE2_PROTECTION 3535 | SHOST_DIX_TYPE3_PROTECTION); 3536 3537 guard = SHOST_DIX_GUARD_CRC; 3538 3539 if (IS_PI_IPGUARD_CAPABLE(ha) && 3540 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3541 guard |= SHOST_DIX_GUARD_IP; 3542 3543 if (ql2xprotguard) 3544 scsi_host_set_guard(host, ql2xprotguard); 3545 else 3546 scsi_host_set_guard(host, guard); 3547 } else 3548 base_vha->flags.difdix_supported = 0; 3549 } 3550 3551 ha->isp_ops->enable_intrs(ha); 3552 3553 if (IS_QLAFX00(ha)) { 3554 ret = qlafx00_fx_disc(base_vha, 3555 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3556 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3557 QLA_SG_ALL : 128; 3558 } 3559 3560 ret = scsi_add_host(host, &pdev->dev); 3561 if (ret) 3562 goto probe_failed; 3563 3564 base_vha->flags.init_done = 1; 3565 base_vha->flags.online = 1; 3566 ha->prev_minidump_failed = 0; 3567 3568 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3569 "Init done and hba is online.\n"); 3570 3571 if (qla_ini_mode_enabled(base_vha) || 3572 qla_dual_mode_enabled(base_vha)) 3573 scsi_scan_host(host); 3574 else 3575 ql_log(ql_log_info, base_vha, 0x0122, 3576 "skipping scsi_scan_host() for non-initiator port\n"); 3577 3578 qla2x00_alloc_sysfs_attr(base_vha); 3579 3580 if (IS_QLAFX00(ha)) { 3581 ret = qlafx00_fx_disc(base_vha, 3582 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3583 3584 /* Register system information */ 3585 ret = qlafx00_fx_disc(base_vha, 3586 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3587 } 3588 3589 qla2x00_init_host_attr(base_vha); 3590 3591 qla2x00_dfs_setup(base_vha); 3592 3593 ql_log(ql_log_info, base_vha, 0x00fb, 3594 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3595 ql_log(ql_log_info, base_vha, 0x00fc, 3596 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3597 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3598 sizeof(pci_info)), 3599 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3600 base_vha->host_no, 3601 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3602 3603 qlt_add_target(ha, base_vha); 3604 3605 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3606 3607 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3608 return -ENODEV; 3609 3610 return 0; 3611 3612 probe_failed: 3613 qla_enode_stop(base_vha); 3614 qla_edb_stop(base_vha); 3615 vfree(base_vha->scan.l); 3616 if (base_vha->gnl.l) { 3617 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3618 base_vha->gnl.l, base_vha->gnl.ldma); 3619 base_vha->gnl.l = NULL; 3620 } 3621 3622 if (base_vha->timer_active) 3623 qla2x00_stop_timer(base_vha); 3624 base_vha->flags.online = 0; 3625 if (ha->dpc_thread) { 3626 struct task_struct *t = ha->dpc_thread; 3627 3628 ha->dpc_thread = NULL; 3629 kthread_stop(t); 3630 } 3631 3632 qla2x00_free_device(base_vha); 3633 scsi_host_put(base_vha->host); 3634 /* 3635 * Need to NULL out local req/rsp after 3636 * qla2x00_free_device => qla2x00_free_queues frees 3637 * what these are pointing to. Or else we'll 3638 * fall over below in qla2x00_free_req/rsp_que. 3639 */ 3640 req = NULL; 3641 rsp = NULL; 3642 3643 probe_hw_failed: 3644 qla2x00_mem_free(ha); 3645 qla2x00_free_req_que(ha, req); 3646 qla2x00_free_rsp_que(ha, rsp); 3647 qla2x00_clear_drv_active(ha); 3648 3649 iospace_config_failed: 3650 if (IS_P3P_TYPE(ha)) { 3651 if (!ha->nx_pcibase) 3652 iounmap((device_reg_t *)ha->nx_pcibase); 3653 if (!ql2xdbwr) 3654 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3655 } else { 3656 if (ha->iobase) 3657 iounmap(ha->iobase); 3658 if (ha->cregbase) 3659 iounmap(ha->cregbase); 3660 } 3661 pci_release_selected_regions(ha->pdev, ha->bars); 3662 kfree(ha); 3663 3664 disable_device: 3665 pci_disable_device(pdev); 3666 return ret; 3667 } 3668 3669 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3670 { 3671 scsi_qla_host_t *vp; 3672 unsigned long flags; 3673 struct qla_hw_data *ha; 3674 3675 if (!base_vha) 3676 return; 3677 3678 ha = base_vha->hw; 3679 3680 spin_lock_irqsave(&ha->vport_slock, flags); 3681 list_for_each_entry(vp, &ha->vp_list, list) 3682 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3683 3684 /* 3685 * Indicate device removal to prevent future board_disable 3686 * and wait until any pending board_disable has completed. 3687 */ 3688 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3689 spin_unlock_irqrestore(&ha->vport_slock, flags); 3690 } 3691 3692 static void 3693 qla2x00_shutdown(struct pci_dev *pdev) 3694 { 3695 scsi_qla_host_t *vha; 3696 struct qla_hw_data *ha; 3697 3698 vha = pci_get_drvdata(pdev); 3699 ha = vha->hw; 3700 3701 ql_log(ql_log_info, vha, 0xfffa, 3702 "Adapter shutdown\n"); 3703 3704 /* 3705 * Prevent future board_disable and wait 3706 * until any pending board_disable has completed. 3707 */ 3708 __qla_set_remove_flag(vha); 3709 cancel_work_sync(&ha->board_disable); 3710 3711 if (!atomic_read(&pdev->enable_cnt)) 3712 return; 3713 3714 /* Notify ISPFX00 firmware */ 3715 if (IS_QLAFX00(ha)) 3716 qlafx00_driver_shutdown(vha, 20); 3717 3718 /* Turn-off FCE trace */ 3719 if (ha->flags.fce_enabled) { 3720 qla2x00_disable_fce_trace(vha, NULL, NULL); 3721 ha->flags.fce_enabled = 0; 3722 } 3723 3724 /* Turn-off EFT trace */ 3725 if (ha->eft) 3726 qla2x00_disable_eft_trace(vha); 3727 3728 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3729 IS_QLA28XX(ha)) { 3730 if (ha->flags.fw_started) 3731 qla2x00_abort_isp_cleanup(vha); 3732 } else { 3733 /* Stop currently executing firmware. */ 3734 qla2x00_try_to_stop_firmware(vha); 3735 } 3736 3737 /* Disable timer */ 3738 if (vha->timer_active) 3739 qla2x00_stop_timer(vha); 3740 3741 /* Turn adapter off line */ 3742 vha->flags.online = 0; 3743 3744 /* turn-off interrupts on the card */ 3745 if (ha->interrupts_on) { 3746 vha->flags.init_done = 0; 3747 ha->isp_ops->disable_intrs(ha); 3748 } 3749 3750 qla2x00_free_irqs(vha); 3751 3752 qla2x00_free_fw_dump(ha); 3753 3754 pci_disable_device(pdev); 3755 ql_log(ql_log_info, vha, 0xfffe, 3756 "Adapter shutdown successfully.\n"); 3757 } 3758 3759 /* Deletes all the virtual ports for a given ha */ 3760 static void 3761 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3762 { 3763 scsi_qla_host_t *vha; 3764 unsigned long flags; 3765 3766 mutex_lock(&ha->vport_lock); 3767 while (ha->cur_vport_count) { 3768 spin_lock_irqsave(&ha->vport_slock, flags); 3769 3770 BUG_ON(base_vha->list.next == &ha->vp_list); 3771 /* This assumes first entry in ha->vp_list is always base vha */ 3772 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3773 scsi_host_get(vha->host); 3774 3775 spin_unlock_irqrestore(&ha->vport_slock, flags); 3776 mutex_unlock(&ha->vport_lock); 3777 3778 qla_nvme_delete(vha); 3779 3780 fc_vport_terminate(vha->fc_vport); 3781 scsi_host_put(vha->host); 3782 3783 mutex_lock(&ha->vport_lock); 3784 } 3785 mutex_unlock(&ha->vport_lock); 3786 } 3787 3788 /* Stops all deferred work threads */ 3789 static void 3790 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3791 { 3792 /* Cancel all work and destroy DPC workqueues */ 3793 if (ha->dpc_lp_wq) { 3794 cancel_work_sync(&ha->idc_aen); 3795 destroy_workqueue(ha->dpc_lp_wq); 3796 ha->dpc_lp_wq = NULL; 3797 } 3798 3799 if (ha->dpc_hp_wq) { 3800 cancel_work_sync(&ha->nic_core_reset); 3801 cancel_work_sync(&ha->idc_state_handler); 3802 cancel_work_sync(&ha->nic_core_unrecoverable); 3803 destroy_workqueue(ha->dpc_hp_wq); 3804 ha->dpc_hp_wq = NULL; 3805 } 3806 3807 /* Kill the kernel thread for this host */ 3808 if (ha->dpc_thread) { 3809 struct task_struct *t = ha->dpc_thread; 3810 3811 /* 3812 * qla2xxx_wake_dpc checks for ->dpc_thread 3813 * so we need to zero it out. 3814 */ 3815 ha->dpc_thread = NULL; 3816 kthread_stop(t); 3817 } 3818 } 3819 3820 static void 3821 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3822 { 3823 if (IS_QLA82XX(ha)) { 3824 3825 iounmap((device_reg_t *)ha->nx_pcibase); 3826 if (!ql2xdbwr) 3827 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3828 } else { 3829 if (ha->iobase) 3830 iounmap(ha->iobase); 3831 3832 if (ha->cregbase) 3833 iounmap(ha->cregbase); 3834 3835 if (ha->mqiobase) 3836 iounmap(ha->mqiobase); 3837 3838 if (ha->msixbase) 3839 iounmap(ha->msixbase); 3840 } 3841 } 3842 3843 static void 3844 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3845 { 3846 if (IS_QLA8044(ha)) { 3847 qla8044_idc_lock(ha); 3848 qla8044_clear_drv_active(ha); 3849 qla8044_idc_unlock(ha); 3850 } else if (IS_QLA82XX(ha)) { 3851 qla82xx_idc_lock(ha); 3852 qla82xx_clear_drv_active(ha); 3853 qla82xx_idc_unlock(ha); 3854 } 3855 } 3856 3857 static void 3858 qla2x00_remove_one(struct pci_dev *pdev) 3859 { 3860 scsi_qla_host_t *base_vha; 3861 struct qla_hw_data *ha; 3862 3863 base_vha = pci_get_drvdata(pdev); 3864 ha = base_vha->hw; 3865 ql_log(ql_log_info, base_vha, 0xb079, 3866 "Removing driver\n"); 3867 __qla_set_remove_flag(base_vha); 3868 cancel_work_sync(&ha->board_disable); 3869 3870 /* 3871 * If the PCI device is disabled then there was a PCI-disconnect and 3872 * qla2x00_disable_board_on_pci_error has taken care of most of the 3873 * resources. 3874 */ 3875 if (!atomic_read(&pdev->enable_cnt)) { 3876 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3877 base_vha->gnl.l, base_vha->gnl.ldma); 3878 base_vha->gnl.l = NULL; 3879 scsi_host_put(base_vha->host); 3880 kfree(ha); 3881 pci_set_drvdata(pdev, NULL); 3882 return; 3883 } 3884 qla2x00_wait_for_hba_ready(base_vha); 3885 3886 /* 3887 * if UNLOADING flag is already set, then continue unload, 3888 * where it was set first. 3889 */ 3890 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3891 return; 3892 3893 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3894 IS_QLA28XX(ha)) { 3895 if (ha->flags.fw_started) 3896 qla2x00_abort_isp_cleanup(base_vha); 3897 } else if (!IS_QLAFX00(ha)) { 3898 if (IS_QLA8031(ha)) { 3899 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3900 "Clearing fcoe driver presence.\n"); 3901 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3902 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3903 "Error while clearing DRV-Presence.\n"); 3904 } 3905 3906 qla2x00_try_to_stop_firmware(base_vha); 3907 } 3908 3909 qla2x00_wait_for_sess_deletion(base_vha); 3910 3911 qla_nvme_delete(base_vha); 3912 3913 dma_free_coherent(&ha->pdev->dev, 3914 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3915 3916 base_vha->gnl.l = NULL; 3917 qla_enode_stop(base_vha); 3918 qla_edb_stop(base_vha); 3919 3920 vfree(base_vha->scan.l); 3921 3922 if (IS_QLAFX00(ha)) 3923 qlafx00_driver_shutdown(base_vha, 20); 3924 3925 qla2x00_delete_all_vps(ha, base_vha); 3926 3927 qla2x00_dfs_remove(base_vha); 3928 3929 qla84xx_put_chip(base_vha); 3930 3931 /* Disable timer */ 3932 if (base_vha->timer_active) 3933 qla2x00_stop_timer(base_vha); 3934 3935 base_vha->flags.online = 0; 3936 3937 /* free DMA memory */ 3938 if (ha->exlogin_buf) 3939 qla2x00_free_exlogin_buffer(ha); 3940 3941 /* free DMA memory */ 3942 if (ha->exchoffld_buf) 3943 qla2x00_free_exchoffld_buffer(ha); 3944 3945 qla2x00_destroy_deferred_work(ha); 3946 3947 qlt_remove_target(ha, base_vha); 3948 3949 qla2x00_free_sysfs_attr(base_vha, true); 3950 3951 fc_remove_host(base_vha->host); 3952 3953 scsi_remove_host(base_vha->host); 3954 3955 qla2x00_free_device(base_vha); 3956 3957 qla2x00_clear_drv_active(ha); 3958 3959 scsi_host_put(base_vha->host); 3960 3961 qla2x00_unmap_iobases(ha); 3962 3963 pci_release_selected_regions(ha->pdev, ha->bars); 3964 kfree(ha); 3965 3966 pci_disable_device(pdev); 3967 } 3968 3969 static inline void 3970 qla24xx_free_purex_list(struct purex_list *list) 3971 { 3972 struct purex_item *item, *next; 3973 ulong flags; 3974 3975 spin_lock_irqsave(&list->lock, flags); 3976 list_for_each_entry_safe(item, next, &list->head, list) { 3977 list_del(&item->list); 3978 if (item == &item->vha->default_item) 3979 continue; 3980 kfree(item); 3981 } 3982 spin_unlock_irqrestore(&list->lock, flags); 3983 } 3984 3985 static void 3986 qla2x00_free_device(scsi_qla_host_t *vha) 3987 { 3988 struct qla_hw_data *ha = vha->hw; 3989 3990 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3991 3992 /* Disable timer */ 3993 if (vha->timer_active) 3994 qla2x00_stop_timer(vha); 3995 3996 qla25xx_delete_queues(vha); 3997 vha->flags.online = 0; 3998 3999 /* turn-off interrupts on the card */ 4000 if (ha->interrupts_on) { 4001 vha->flags.init_done = 0; 4002 ha->isp_ops->disable_intrs(ha); 4003 } 4004 4005 qla2x00_free_fcports(vha); 4006 4007 qla2x00_free_irqs(vha); 4008 4009 /* Flush the work queue and remove it */ 4010 if (ha->wq) { 4011 destroy_workqueue(ha->wq); 4012 ha->wq = NULL; 4013 } 4014 4015 4016 qla24xx_free_purex_list(&vha->purex_list); 4017 4018 qla2x00_mem_free(ha); 4019 4020 qla82xx_md_free(vha); 4021 4022 qla_edif_sadb_release_free_pool(ha); 4023 qla_edif_sadb_release(ha); 4024 4025 qla2x00_free_queues(ha); 4026 } 4027 4028 void qla2x00_free_fcports(struct scsi_qla_host *vha) 4029 { 4030 fc_port_t *fcport, *tfcport; 4031 4032 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 4033 qla2x00_free_fcport(fcport); 4034 } 4035 4036 static inline void 4037 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 4038 { 4039 int now; 4040 4041 if (!fcport->rport) 4042 return; 4043 4044 if (fcport->rport) { 4045 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 4046 "%s %8phN. rport %p roles %x\n", 4047 __func__, fcport->port_name, fcport->rport, 4048 fcport->rport->roles); 4049 fc_remote_port_delete(fcport->rport); 4050 } 4051 qlt_do_generation_tick(vha, &now); 4052 } 4053 4054 /* 4055 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 4056 * 4057 * Input: ha = adapter block pointer. fcport = port structure pointer. 4058 * 4059 * Return: None. 4060 * 4061 * Context: 4062 */ 4063 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 4064 int do_login) 4065 { 4066 if (IS_QLAFX00(vha->hw)) { 4067 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4068 qla2x00_schedule_rport_del(vha, fcport); 4069 return; 4070 } 4071 4072 if (atomic_read(&fcport->state) == FCS_ONLINE && 4073 vha->vp_idx == fcport->vha->vp_idx) { 4074 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4075 qla2x00_schedule_rport_del(vha, fcport); 4076 } 4077 4078 /* 4079 * We may need to retry the login, so don't change the state of the 4080 * port but do the retries. 4081 */ 4082 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4083 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4084 4085 if (!do_login) 4086 return; 4087 4088 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4089 } 4090 4091 void 4092 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4093 { 4094 fc_port_t *fcport; 4095 4096 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4097 "Mark all dev lost\n"); 4098 4099 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4100 if (ql2xfc2target && 4101 fcport->loop_id != FC_NO_LOOP_ID && 4102 (fcport->flags & FCF_FCP2_DEVICE) && 4103 fcport->port_type == FCT_TARGET && 4104 !qla2x00_reset_active(vha)) { 4105 ql_dbg(ql_dbg_disc, vha, 0x211a, 4106 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4107 fcport->flags, fcport->port_type, 4108 fcport->d_id.b24, fcport->port_name); 4109 continue; 4110 } 4111 fcport->scan_state = 0; 4112 qlt_schedule_sess_for_deletion(fcport); 4113 } 4114 } 4115 4116 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4117 { 4118 int i; 4119 4120 if (IS_FWI2_CAPABLE(ha)) 4121 return; 4122 4123 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4124 set_bit(i, ha->loop_id_map); 4125 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4126 set_bit(BROADCAST, ha->loop_id_map); 4127 } 4128 4129 /* 4130 * qla2x00_mem_alloc 4131 * Allocates adapter memory. 4132 * 4133 * Returns: 4134 * 0 = success. 4135 * !0 = failure. 4136 */ 4137 static int 4138 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4139 struct req_que **req, struct rsp_que **rsp) 4140 { 4141 char name[16]; 4142 int rc; 4143 4144 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) { 4145 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL); 4146 if (!ha->vp_map) 4147 goto fail; 4148 } 4149 4150 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4151 &ha->init_cb_dma, GFP_KERNEL); 4152 if (!ha->init_cb) 4153 goto fail_free_vp_map; 4154 4155 rc = btree_init32(&ha->host_map); 4156 if (rc) 4157 goto fail_free_init_cb; 4158 4159 if (qlt_mem_alloc(ha) < 0) 4160 goto fail_free_btree; 4161 4162 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4163 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4164 if (!ha->gid_list) 4165 goto fail_free_tgt_mem; 4166 4167 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4168 if (!ha->srb_mempool) 4169 goto fail_free_gid_list; 4170 4171 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4172 /* Allocate cache for CT6 Ctx. */ 4173 if (!ctx_cachep) { 4174 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4175 sizeof(struct ct6_dsd), 0, 4176 SLAB_HWCACHE_ALIGN, NULL); 4177 if (!ctx_cachep) 4178 goto fail_free_srb_mempool; 4179 } 4180 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4181 ctx_cachep); 4182 if (!ha->ctx_mempool) 4183 goto fail_free_srb_mempool; 4184 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4185 "ctx_cachep=%p ctx_mempool=%p.\n", 4186 ctx_cachep, ha->ctx_mempool); 4187 } 4188 4189 /* Get memory for cached NVRAM */ 4190 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4191 if (!ha->nvram) 4192 goto fail_free_ctx_mempool; 4193 4194 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4195 ha->pdev->device); 4196 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4197 DMA_POOL_SIZE, 8, 0); 4198 if (!ha->s_dma_pool) 4199 goto fail_free_nvram; 4200 4201 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4202 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4203 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4204 4205 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4206 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4207 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4208 if (!ha->dl_dma_pool) { 4209 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4210 "Failed to allocate memory for dl_dma_pool.\n"); 4211 goto fail_s_dma_pool; 4212 } 4213 4214 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4215 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4216 if (!ha->fcp_cmnd_dma_pool) { 4217 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4218 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4219 goto fail_dl_dma_pool; 4220 } 4221 4222 if (ql2xenabledif) { 4223 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4224 struct dsd_dma *dsd, *nxt; 4225 uint i; 4226 /* Creata a DMA pool of buffers for DIF bundling */ 4227 ha->dif_bundl_pool = dma_pool_create(name, 4228 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4229 if (!ha->dif_bundl_pool) { 4230 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4231 "%s: failed create dif_bundl_pool\n", 4232 __func__); 4233 goto fail_dif_bundl_dma_pool; 4234 } 4235 4236 INIT_LIST_HEAD(&ha->pool.good.head); 4237 INIT_LIST_HEAD(&ha->pool.unusable.head); 4238 ha->pool.good.count = 0; 4239 ha->pool.unusable.count = 0; 4240 for (i = 0; i < 128; i++) { 4241 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4242 if (!dsd) { 4243 ql_dbg_pci(ql_dbg_init, ha->pdev, 4244 0xe0ee, "%s: failed alloc dsd\n", 4245 __func__); 4246 return -ENOMEM; 4247 } 4248 ha->dif_bundle_kallocs++; 4249 4250 dsd->dsd_addr = dma_pool_alloc( 4251 ha->dif_bundl_pool, GFP_ATOMIC, 4252 &dsd->dsd_list_dma); 4253 if (!dsd->dsd_addr) { 4254 ql_dbg_pci(ql_dbg_init, ha->pdev, 4255 0xe0ee, 4256 "%s: failed alloc ->dsd_addr\n", 4257 __func__); 4258 kfree(dsd); 4259 ha->dif_bundle_kallocs--; 4260 continue; 4261 } 4262 ha->dif_bundle_dma_allocs++; 4263 4264 /* 4265 * if DMA buffer crosses 4G boundary, 4266 * put it on bad list 4267 */ 4268 if (MSD(dsd->dsd_list_dma) ^ 4269 MSD(dsd->dsd_list_dma + bufsize)) { 4270 list_add_tail(&dsd->list, 4271 &ha->pool.unusable.head); 4272 ha->pool.unusable.count++; 4273 } else { 4274 list_add_tail(&dsd->list, 4275 &ha->pool.good.head); 4276 ha->pool.good.count++; 4277 } 4278 } 4279 4280 /* return the good ones back to the pool */ 4281 list_for_each_entry_safe(dsd, nxt, 4282 &ha->pool.good.head, list) { 4283 list_del(&dsd->list); 4284 dma_pool_free(ha->dif_bundl_pool, 4285 dsd->dsd_addr, dsd->dsd_list_dma); 4286 ha->dif_bundle_dma_allocs--; 4287 kfree(dsd); 4288 ha->dif_bundle_kallocs--; 4289 } 4290 4291 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4292 "%s: dif dma pool (good=%u unusable=%u)\n", 4293 __func__, ha->pool.good.count, 4294 ha->pool.unusable.count); 4295 } 4296 4297 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4298 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4299 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4300 ha->dif_bundl_pool); 4301 } 4302 4303 /* Allocate memory for SNS commands */ 4304 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4305 /* Get consistent memory allocated for SNS commands */ 4306 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4307 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4308 if (!ha->sns_cmd) 4309 goto fail_dma_pool; 4310 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4311 "sns_cmd: %p.\n", ha->sns_cmd); 4312 } else { 4313 /* Get consistent memory allocated for MS IOCB */ 4314 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4315 &ha->ms_iocb_dma); 4316 if (!ha->ms_iocb) 4317 goto fail_dma_pool; 4318 /* Get consistent memory allocated for CT SNS commands */ 4319 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4320 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4321 if (!ha->ct_sns) 4322 goto fail_free_ms_iocb; 4323 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4324 "ms_iocb=%p ct_sns=%p.\n", 4325 ha->ms_iocb, ha->ct_sns); 4326 } 4327 4328 /* Allocate memory for request ring */ 4329 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4330 if (!*req) { 4331 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4332 "Failed to allocate memory for req.\n"); 4333 goto fail_req; 4334 } 4335 (*req)->length = req_len; 4336 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4337 ((*req)->length + 1) * sizeof(request_t), 4338 &(*req)->dma, GFP_KERNEL); 4339 if (!(*req)->ring) { 4340 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4341 "Failed to allocate memory for req_ring.\n"); 4342 goto fail_req_ring; 4343 } 4344 /* Allocate memory for response ring */ 4345 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4346 if (!*rsp) { 4347 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4348 "Failed to allocate memory for rsp.\n"); 4349 goto fail_rsp; 4350 } 4351 (*rsp)->hw = ha; 4352 (*rsp)->length = rsp_len; 4353 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4354 ((*rsp)->length + 1) * sizeof(response_t), 4355 &(*rsp)->dma, GFP_KERNEL); 4356 if (!(*rsp)->ring) { 4357 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4358 "Failed to allocate memory for rsp_ring.\n"); 4359 goto fail_rsp_ring; 4360 } 4361 (*req)->rsp = *rsp; 4362 (*rsp)->req = *req; 4363 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4364 "req=%p req->length=%d req->ring=%p rsp=%p " 4365 "rsp->length=%d rsp->ring=%p.\n", 4366 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4367 (*rsp)->ring); 4368 /* Allocate memory for NVRAM data for vports */ 4369 if (ha->nvram_npiv_size) { 4370 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4371 sizeof(struct qla_npiv_entry), 4372 GFP_KERNEL); 4373 if (!ha->npiv_info) { 4374 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4375 "Failed to allocate memory for npiv_info.\n"); 4376 goto fail_npiv_info; 4377 } 4378 } else 4379 ha->npiv_info = NULL; 4380 4381 /* Get consistent memory allocated for EX-INIT-CB. */ 4382 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4383 IS_QLA28XX(ha)) { 4384 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4385 &ha->ex_init_cb_dma); 4386 if (!ha->ex_init_cb) 4387 goto fail_ex_init_cb; 4388 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4389 "ex_init_cb=%p.\n", ha->ex_init_cb); 4390 } 4391 4392 /* Get consistent memory allocated for Special Features-CB. */ 4393 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4394 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4395 &ha->sf_init_cb_dma); 4396 if (!ha->sf_init_cb) 4397 goto fail_sf_init_cb; 4398 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4399 "sf_init_cb=%p.\n", ha->sf_init_cb); 4400 } 4401 4402 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4403 4404 /* Get consistent memory allocated for Async Port-Database. */ 4405 if (!IS_FWI2_CAPABLE(ha)) { 4406 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4407 &ha->async_pd_dma); 4408 if (!ha->async_pd) 4409 goto fail_async_pd; 4410 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4411 "async_pd=%p.\n", ha->async_pd); 4412 } 4413 4414 INIT_LIST_HEAD(&ha->vp_list); 4415 4416 /* Allocate memory for our loop_id bitmap */ 4417 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4418 sizeof(long), 4419 GFP_KERNEL); 4420 if (!ha->loop_id_map) 4421 goto fail_loop_id_map; 4422 else { 4423 qla2x00_set_reserved_loop_ids(ha); 4424 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4425 "loop_id_map=%p.\n", ha->loop_id_map); 4426 } 4427 4428 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4429 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4430 if (!ha->sfp_data) { 4431 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4432 "Unable to allocate memory for SFP read-data.\n"); 4433 goto fail_sfp_data; 4434 } 4435 4436 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4437 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4438 GFP_KERNEL); 4439 if (!ha->flt) { 4440 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4441 "Unable to allocate memory for FLT.\n"); 4442 goto fail_flt_buffer; 4443 } 4444 4445 /* allocate the purex dma pool */ 4446 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4447 ELS_MAX_PAYLOAD, 8, 0); 4448 4449 if (!ha->purex_dma_pool) { 4450 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4451 "Unable to allocate purex_dma_pool.\n"); 4452 goto fail_flt; 4453 } 4454 4455 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4456 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4457 ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL); 4458 4459 if (!ha->elsrej.c) { 4460 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4461 "Alloc failed for els reject cmd.\n"); 4462 goto fail_elsrej; 4463 } 4464 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4465 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4466 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4467 return 0; 4468 4469 fail_elsrej: 4470 dma_pool_destroy(ha->purex_dma_pool); 4471 fail_flt: 4472 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4473 ha->flt, ha->flt_dma); 4474 4475 fail_flt_buffer: 4476 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4477 ha->sfp_data, ha->sfp_data_dma); 4478 fail_sfp_data: 4479 kfree(ha->loop_id_map); 4480 fail_loop_id_map: 4481 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4482 fail_async_pd: 4483 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4484 fail_sf_init_cb: 4485 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4486 fail_ex_init_cb: 4487 kfree(ha->npiv_info); 4488 fail_npiv_info: 4489 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4490 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4491 (*rsp)->ring = NULL; 4492 (*rsp)->dma = 0; 4493 fail_rsp_ring: 4494 kfree(*rsp); 4495 *rsp = NULL; 4496 fail_rsp: 4497 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4498 sizeof(request_t), (*req)->ring, (*req)->dma); 4499 (*req)->ring = NULL; 4500 (*req)->dma = 0; 4501 fail_req_ring: 4502 kfree(*req); 4503 *req = NULL; 4504 fail_req: 4505 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4506 ha->ct_sns, ha->ct_sns_dma); 4507 ha->ct_sns = NULL; 4508 ha->ct_sns_dma = 0; 4509 fail_free_ms_iocb: 4510 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4511 ha->ms_iocb = NULL; 4512 ha->ms_iocb_dma = 0; 4513 4514 if (ha->sns_cmd) 4515 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4516 ha->sns_cmd, ha->sns_cmd_dma); 4517 fail_dma_pool: 4518 if (ql2xenabledif) { 4519 struct dsd_dma *dsd, *nxt; 4520 4521 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4522 list) { 4523 list_del(&dsd->list); 4524 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4525 dsd->dsd_list_dma); 4526 ha->dif_bundle_dma_allocs--; 4527 kfree(dsd); 4528 ha->dif_bundle_kallocs--; 4529 ha->pool.unusable.count--; 4530 } 4531 dma_pool_destroy(ha->dif_bundl_pool); 4532 ha->dif_bundl_pool = NULL; 4533 } 4534 4535 fail_dif_bundl_dma_pool: 4536 if (IS_QLA82XX(ha) || ql2xenabledif) { 4537 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4538 ha->fcp_cmnd_dma_pool = NULL; 4539 } 4540 fail_dl_dma_pool: 4541 if (IS_QLA82XX(ha) || ql2xenabledif) { 4542 dma_pool_destroy(ha->dl_dma_pool); 4543 ha->dl_dma_pool = NULL; 4544 } 4545 fail_s_dma_pool: 4546 dma_pool_destroy(ha->s_dma_pool); 4547 ha->s_dma_pool = NULL; 4548 fail_free_nvram: 4549 kfree(ha->nvram); 4550 ha->nvram = NULL; 4551 fail_free_ctx_mempool: 4552 mempool_destroy(ha->ctx_mempool); 4553 ha->ctx_mempool = NULL; 4554 fail_free_srb_mempool: 4555 mempool_destroy(ha->srb_mempool); 4556 ha->srb_mempool = NULL; 4557 fail_free_gid_list: 4558 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4559 ha->gid_list, 4560 ha->gid_list_dma); 4561 ha->gid_list = NULL; 4562 ha->gid_list_dma = 0; 4563 fail_free_tgt_mem: 4564 qlt_mem_free(ha); 4565 fail_free_btree: 4566 btree_destroy32(&ha->host_map); 4567 fail_free_init_cb: 4568 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4569 ha->init_cb_dma); 4570 ha->init_cb = NULL; 4571 ha->init_cb_dma = 0; 4572 fail_free_vp_map: 4573 kfree(ha->vp_map); 4574 fail: 4575 ql_log(ql_log_fatal, NULL, 0x0030, 4576 "Memory allocation failure.\n"); 4577 return -ENOMEM; 4578 } 4579 4580 int 4581 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4582 { 4583 int rval; 4584 uint16_t size, max_cnt; 4585 uint32_t temp; 4586 struct qla_hw_data *ha = vha->hw; 4587 4588 /* Return if we don't need to alloacate any extended logins */ 4589 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4590 return QLA_SUCCESS; 4591 4592 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4593 return QLA_SUCCESS; 4594 4595 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4596 max_cnt = 0; 4597 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4598 if (rval != QLA_SUCCESS) { 4599 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4600 "Failed to get exlogin status.\n"); 4601 return rval; 4602 } 4603 4604 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4605 temp *= size; 4606 4607 if (temp != ha->exlogin_size) { 4608 qla2x00_free_exlogin_buffer(ha); 4609 ha->exlogin_size = temp; 4610 4611 ql_log(ql_log_info, vha, 0xd024, 4612 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4613 max_cnt, size, temp); 4614 4615 ql_log(ql_log_info, vha, 0xd025, 4616 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4617 4618 /* Get consistent memory for extended logins */ 4619 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4620 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4621 if (!ha->exlogin_buf) { 4622 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4623 "Failed to allocate memory for exlogin_buf_dma.\n"); 4624 return -ENOMEM; 4625 } 4626 } 4627 4628 /* Now configure the dma buffer */ 4629 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4630 if (rval) { 4631 ql_log(ql_log_fatal, vha, 0xd033, 4632 "Setup extended login buffer ****FAILED****.\n"); 4633 qla2x00_free_exlogin_buffer(ha); 4634 } 4635 4636 return rval; 4637 } 4638 4639 /* 4640 * qla2x00_free_exlogin_buffer 4641 * 4642 * Input: 4643 * ha = adapter block pointer 4644 */ 4645 void 4646 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4647 { 4648 if (ha->exlogin_buf) { 4649 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4650 ha->exlogin_buf, ha->exlogin_buf_dma); 4651 ha->exlogin_buf = NULL; 4652 ha->exlogin_size = 0; 4653 } 4654 } 4655 4656 static void 4657 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4658 { 4659 u32 temp; 4660 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4661 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4662 4663 if (max_cnt > vha->hw->max_exchg) 4664 max_cnt = vha->hw->max_exchg; 4665 4666 if (qla_ini_mode_enabled(vha)) { 4667 if (vha->ql2xiniexchg > max_cnt) 4668 vha->ql2xiniexchg = max_cnt; 4669 4670 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4671 *ret_cnt = vha->ql2xiniexchg; 4672 4673 } else if (qla_tgt_mode_enabled(vha)) { 4674 if (vha->ql2xexchoffld > max_cnt) { 4675 vha->ql2xexchoffld = max_cnt; 4676 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4677 } 4678 4679 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4680 *ret_cnt = vha->ql2xexchoffld; 4681 } else if (qla_dual_mode_enabled(vha)) { 4682 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4683 if (temp > max_cnt) { 4684 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4685 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4686 temp = max_cnt; 4687 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4688 } 4689 4690 if (temp > FW_DEF_EXCHANGES_CNT) 4691 *ret_cnt = temp; 4692 } 4693 } 4694 4695 int 4696 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4697 { 4698 int rval; 4699 u16 size, max_cnt; 4700 u32 actual_cnt, totsz; 4701 struct qla_hw_data *ha = vha->hw; 4702 4703 if (!ha->flags.exchoffld_enabled) 4704 return QLA_SUCCESS; 4705 4706 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4707 return QLA_SUCCESS; 4708 4709 max_cnt = 0; 4710 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4711 if (rval != QLA_SUCCESS) { 4712 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4713 "Failed to get exlogin status.\n"); 4714 return rval; 4715 } 4716 4717 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4718 ql_log(ql_log_info, vha, 0xd014, 4719 "Actual exchange offload count: %d.\n", actual_cnt); 4720 4721 totsz = actual_cnt * size; 4722 4723 if (totsz != ha->exchoffld_size) { 4724 qla2x00_free_exchoffld_buffer(ha); 4725 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4726 ha->exchoffld_size = 0; 4727 ha->flags.exchoffld_enabled = 0; 4728 return QLA_SUCCESS; 4729 } 4730 4731 ha->exchoffld_size = totsz; 4732 4733 ql_log(ql_log_info, vha, 0xd016, 4734 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4735 max_cnt, actual_cnt, size, totsz); 4736 4737 ql_log(ql_log_info, vha, 0xd017, 4738 "Exchange Buffers requested size = 0x%x\n", 4739 ha->exchoffld_size); 4740 4741 /* Get consistent memory for extended logins */ 4742 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4743 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4744 if (!ha->exchoffld_buf) { 4745 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4746 "Failed to allocate memory for Exchange Offload.\n"); 4747 4748 if (ha->max_exchg > 4749 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4750 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4751 } else if (ha->max_exchg > 4752 (FW_DEF_EXCHANGES_CNT + 512)) { 4753 ha->max_exchg -= 512; 4754 } else { 4755 ha->flags.exchoffld_enabled = 0; 4756 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4757 "Disabling Exchange offload due to lack of memory\n"); 4758 } 4759 ha->exchoffld_size = 0; 4760 4761 return -ENOMEM; 4762 } 4763 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4764 /* pathological case */ 4765 qla2x00_free_exchoffld_buffer(ha); 4766 ha->exchoffld_size = 0; 4767 ha->flags.exchoffld_enabled = 0; 4768 ql_log(ql_log_info, vha, 0xd016, 4769 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4770 ha->exchoffld_size, actual_cnt, size, totsz); 4771 return 0; 4772 } 4773 4774 /* Now configure the dma buffer */ 4775 rval = qla_set_exchoffld_mem_cfg(vha); 4776 if (rval) { 4777 ql_log(ql_log_fatal, vha, 0xd02e, 4778 "Setup exchange offload buffer ****FAILED****.\n"); 4779 qla2x00_free_exchoffld_buffer(ha); 4780 } else { 4781 /* re-adjust number of target exchange */ 4782 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4783 4784 if (qla_ini_mode_enabled(vha)) 4785 icb->exchange_count = 0; 4786 else 4787 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4788 } 4789 4790 return rval; 4791 } 4792 4793 /* 4794 * qla2x00_free_exchoffld_buffer 4795 * 4796 * Input: 4797 * ha = adapter block pointer 4798 */ 4799 void 4800 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4801 { 4802 if (ha->exchoffld_buf) { 4803 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4804 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4805 ha->exchoffld_buf = NULL; 4806 ha->exchoffld_size = 0; 4807 } 4808 } 4809 4810 /* 4811 * qla2x00_free_fw_dump 4812 * Frees fw dump stuff. 4813 * 4814 * Input: 4815 * ha = adapter block pointer 4816 */ 4817 static void 4818 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4819 { 4820 struct fwdt *fwdt = ha->fwdt; 4821 uint j; 4822 4823 if (ha->fce) 4824 dma_free_coherent(&ha->pdev->dev, 4825 FCE_SIZE, ha->fce, ha->fce_dma); 4826 4827 if (ha->eft) 4828 dma_free_coherent(&ha->pdev->dev, 4829 EFT_SIZE, ha->eft, ha->eft_dma); 4830 4831 vfree(ha->fw_dump); 4832 4833 ha->fce = NULL; 4834 ha->fce_dma = 0; 4835 ha->flags.fce_enabled = 0; 4836 ha->eft = NULL; 4837 ha->eft_dma = 0; 4838 ha->fw_dumped = false; 4839 ha->fw_dump_cap_flags = 0; 4840 ha->fw_dump_reading = 0; 4841 ha->fw_dump = NULL; 4842 ha->fw_dump_len = 0; 4843 4844 for (j = 0; j < 2; j++, fwdt++) { 4845 vfree(fwdt->template); 4846 fwdt->template = NULL; 4847 fwdt->length = 0; 4848 } 4849 } 4850 4851 /* 4852 * qla2x00_mem_free 4853 * Frees all adapter allocated memory. 4854 * 4855 * Input: 4856 * ha = adapter block pointer. 4857 */ 4858 static void 4859 qla2x00_mem_free(struct qla_hw_data *ha) 4860 { 4861 qla2x00_free_fw_dump(ha); 4862 4863 if (ha->mctp_dump) 4864 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4865 ha->mctp_dump_dma); 4866 ha->mctp_dump = NULL; 4867 4868 mempool_destroy(ha->srb_mempool); 4869 ha->srb_mempool = NULL; 4870 4871 if (ha->dcbx_tlv) 4872 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4873 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4874 ha->dcbx_tlv = NULL; 4875 4876 if (ha->xgmac_data) 4877 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4878 ha->xgmac_data, ha->xgmac_data_dma); 4879 ha->xgmac_data = NULL; 4880 4881 if (ha->sns_cmd) 4882 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4883 ha->sns_cmd, ha->sns_cmd_dma); 4884 ha->sns_cmd = NULL; 4885 ha->sns_cmd_dma = 0; 4886 4887 if (ha->ct_sns) 4888 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4889 ha->ct_sns, ha->ct_sns_dma); 4890 ha->ct_sns = NULL; 4891 ha->ct_sns_dma = 0; 4892 4893 if (ha->sfp_data) 4894 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4895 ha->sfp_data_dma); 4896 ha->sfp_data = NULL; 4897 4898 if (ha->flt) 4899 dma_free_coherent(&ha->pdev->dev, 4900 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4901 ha->flt, ha->flt_dma); 4902 ha->flt = NULL; 4903 ha->flt_dma = 0; 4904 4905 if (ha->ms_iocb) 4906 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4907 ha->ms_iocb = NULL; 4908 ha->ms_iocb_dma = 0; 4909 4910 if (ha->sf_init_cb) 4911 dma_pool_free(ha->s_dma_pool, 4912 ha->sf_init_cb, ha->sf_init_cb_dma); 4913 4914 if (ha->ex_init_cb) 4915 dma_pool_free(ha->s_dma_pool, 4916 ha->ex_init_cb, ha->ex_init_cb_dma); 4917 ha->ex_init_cb = NULL; 4918 ha->ex_init_cb_dma = 0; 4919 4920 if (ha->async_pd) 4921 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4922 ha->async_pd = NULL; 4923 ha->async_pd_dma = 0; 4924 4925 dma_pool_destroy(ha->s_dma_pool); 4926 ha->s_dma_pool = NULL; 4927 4928 if (ha->gid_list) 4929 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4930 ha->gid_list, ha->gid_list_dma); 4931 ha->gid_list = NULL; 4932 ha->gid_list_dma = 0; 4933 4934 if (IS_QLA82XX(ha)) { 4935 if (!list_empty(&ha->gbl_dsd_list)) { 4936 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4937 4938 /* clean up allocated prev pool */ 4939 list_for_each_entry_safe(dsd_ptr, 4940 tdsd_ptr, &ha->gbl_dsd_list, list) { 4941 dma_pool_free(ha->dl_dma_pool, 4942 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4943 list_del(&dsd_ptr->list); 4944 kfree(dsd_ptr); 4945 } 4946 } 4947 } 4948 4949 dma_pool_destroy(ha->dl_dma_pool); 4950 ha->dl_dma_pool = NULL; 4951 4952 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4953 ha->fcp_cmnd_dma_pool = NULL; 4954 4955 mempool_destroy(ha->ctx_mempool); 4956 ha->ctx_mempool = NULL; 4957 4958 if (ql2xenabledif && ha->dif_bundl_pool) { 4959 struct dsd_dma *dsd, *nxt; 4960 4961 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4962 list) { 4963 list_del(&dsd->list); 4964 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4965 dsd->dsd_list_dma); 4966 ha->dif_bundle_dma_allocs--; 4967 kfree(dsd); 4968 ha->dif_bundle_kallocs--; 4969 ha->pool.unusable.count--; 4970 } 4971 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4972 list_del(&dsd->list); 4973 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4974 dsd->dsd_list_dma); 4975 ha->dif_bundle_dma_allocs--; 4976 kfree(dsd); 4977 ha->dif_bundle_kallocs--; 4978 } 4979 } 4980 4981 dma_pool_destroy(ha->dif_bundl_pool); 4982 ha->dif_bundl_pool = NULL; 4983 4984 qlt_mem_free(ha); 4985 qla_remove_hostmap(ha); 4986 4987 if (ha->init_cb) 4988 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4989 ha->init_cb, ha->init_cb_dma); 4990 4991 dma_pool_destroy(ha->purex_dma_pool); 4992 ha->purex_dma_pool = NULL; 4993 4994 if (ha->elsrej.c) { 4995 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4996 ha->elsrej.c, ha->elsrej.cdma); 4997 ha->elsrej.c = NULL; 4998 } 4999 5000 ha->init_cb = NULL; 5001 ha->init_cb_dma = 0; 5002 5003 vfree(ha->optrom_buffer); 5004 ha->optrom_buffer = NULL; 5005 kfree(ha->nvram); 5006 ha->nvram = NULL; 5007 kfree(ha->npiv_info); 5008 ha->npiv_info = NULL; 5009 kfree(ha->swl); 5010 ha->swl = NULL; 5011 kfree(ha->loop_id_map); 5012 ha->sf_init_cb = NULL; 5013 ha->sf_init_cb_dma = 0; 5014 ha->loop_id_map = NULL; 5015 5016 kfree(ha->vp_map); 5017 ha->vp_map = NULL; 5018 } 5019 5020 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht, 5021 struct qla_hw_data *ha) 5022 { 5023 struct Scsi_Host *host; 5024 struct scsi_qla_host *vha = NULL; 5025 5026 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 5027 if (!host) { 5028 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 5029 "Failed to allocate host from the scsi layer, aborting.\n"); 5030 return NULL; 5031 } 5032 5033 /* Clear our data area */ 5034 vha = shost_priv(host); 5035 memset(vha, 0, sizeof(scsi_qla_host_t)); 5036 5037 vha->host = host; 5038 vha->host_no = host->host_no; 5039 vha->hw = ha; 5040 5041 vha->qlini_mode = ql2x_ini_mode; 5042 vha->ql2xexchoffld = ql2xexchoffld; 5043 vha->ql2xiniexchg = ql2xiniexchg; 5044 5045 INIT_LIST_HEAD(&vha->vp_fcports); 5046 INIT_LIST_HEAD(&vha->work_list); 5047 INIT_LIST_HEAD(&vha->list); 5048 INIT_LIST_HEAD(&vha->qla_cmd_list); 5049 INIT_LIST_HEAD(&vha->logo_list); 5050 INIT_LIST_HEAD(&vha->plogi_ack_list); 5051 INIT_LIST_HEAD(&vha->qp_list); 5052 INIT_LIST_HEAD(&vha->gnl.fcports); 5053 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 5054 5055 INIT_LIST_HEAD(&vha->purex_list.head); 5056 spin_lock_init(&vha->purex_list.lock); 5057 5058 spin_lock_init(&vha->work_lock); 5059 spin_lock_init(&vha->cmd_list_lock); 5060 init_waitqueue_head(&vha->fcport_waitQ); 5061 init_waitqueue_head(&vha->vref_waitq); 5062 qla_enode_init(vha); 5063 qla_edb_init(vha); 5064 5065 5066 vha->gnl.size = sizeof(struct get_name_list_extended) * 5067 (ha->max_loop_id + 1); 5068 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 5069 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 5070 if (!vha->gnl.l) { 5071 ql_log(ql_log_fatal, vha, 0xd04a, 5072 "Alloc failed for name list.\n"); 5073 scsi_host_put(vha->host); 5074 return NULL; 5075 } 5076 5077 /* todo: what about ext login? */ 5078 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 5079 vha->scan.l = vmalloc(vha->scan.size); 5080 if (!vha->scan.l) { 5081 ql_log(ql_log_fatal, vha, 0xd04a, 5082 "Alloc failed for scan database.\n"); 5083 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 5084 vha->gnl.l, vha->gnl.ldma); 5085 vha->gnl.l = NULL; 5086 scsi_host_put(vha->host); 5087 return NULL; 5088 } 5089 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5090 5091 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); 5092 ql_dbg(ql_dbg_init, vha, 0x0041, 5093 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5094 vha->host, vha->hw, vha, 5095 dev_name(&(ha->pdev->dev))); 5096 5097 return vha; 5098 } 5099 5100 struct qla_work_evt * 5101 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5102 { 5103 struct qla_work_evt *e; 5104 5105 if (test_bit(UNLOADING, &vha->dpc_flags)) 5106 return NULL; 5107 5108 if (qla_vha_mark_busy(vha)) 5109 return NULL; 5110 5111 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5112 if (!e) { 5113 QLA_VHA_MARK_NOT_BUSY(vha); 5114 return NULL; 5115 } 5116 5117 INIT_LIST_HEAD(&e->list); 5118 e->type = type; 5119 e->flags = QLA_EVT_FLAG_FREE; 5120 return e; 5121 } 5122 5123 int 5124 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5125 { 5126 unsigned long flags; 5127 bool q = false; 5128 5129 spin_lock_irqsave(&vha->work_lock, flags); 5130 list_add_tail(&e->list, &vha->work_list); 5131 5132 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5133 q = true; 5134 5135 spin_unlock_irqrestore(&vha->work_lock, flags); 5136 5137 if (q) 5138 queue_work(vha->hw->wq, &vha->iocb_work); 5139 5140 return QLA_SUCCESS; 5141 } 5142 5143 int 5144 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5145 u32 data) 5146 { 5147 struct qla_work_evt *e; 5148 5149 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5150 if (!e) 5151 return QLA_FUNCTION_FAILED; 5152 5153 e->u.aen.code = code; 5154 e->u.aen.data = data; 5155 return qla2x00_post_work(vha, e); 5156 } 5157 5158 int 5159 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5160 { 5161 struct qla_work_evt *e; 5162 5163 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5164 if (!e) 5165 return QLA_FUNCTION_FAILED; 5166 5167 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5168 return qla2x00_post_work(vha, e); 5169 } 5170 5171 #define qla2x00_post_async_work(name, type) \ 5172 int qla2x00_post_async_##name##_work( \ 5173 struct scsi_qla_host *vha, \ 5174 fc_port_t *fcport, uint16_t *data) \ 5175 { \ 5176 struct qla_work_evt *e; \ 5177 \ 5178 e = qla2x00_alloc_work(vha, type); \ 5179 if (!e) \ 5180 return QLA_FUNCTION_FAILED; \ 5181 \ 5182 e->u.logio.fcport = fcport; \ 5183 if (data) { \ 5184 e->u.logio.data[0] = data[0]; \ 5185 e->u.logio.data[1] = data[1]; \ 5186 } \ 5187 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5188 return qla2x00_post_work(vha, e); \ 5189 } 5190 5191 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5192 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5193 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5194 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5195 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5196 5197 int 5198 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5199 { 5200 struct qla_work_evt *e; 5201 5202 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5203 if (!e) 5204 return QLA_FUNCTION_FAILED; 5205 5206 e->u.uevent.code = code; 5207 return qla2x00_post_work(vha, e); 5208 } 5209 5210 static void 5211 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5212 { 5213 char event_string[40]; 5214 char *envp[] = { event_string, NULL }; 5215 5216 switch (code) { 5217 case QLA_UEVENT_CODE_FW_DUMP: 5218 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5219 vha->host_no); 5220 break; 5221 default: 5222 /* do nothing */ 5223 break; 5224 } 5225 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5226 } 5227 5228 int 5229 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5230 uint32_t *data, int cnt) 5231 { 5232 struct qla_work_evt *e; 5233 5234 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5235 if (!e) 5236 return QLA_FUNCTION_FAILED; 5237 5238 e->u.aenfx.evtcode = evtcode; 5239 e->u.aenfx.count = cnt; 5240 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5241 return qla2x00_post_work(vha, e); 5242 } 5243 5244 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5245 { 5246 unsigned long flags; 5247 5248 if (IS_SW_RESV_ADDR(fcport->d_id)) 5249 return; 5250 5251 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5252 if (fcport->disc_state == DSC_UPD_FCPORT) { 5253 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5254 return; 5255 } 5256 fcport->jiffies_at_registration = jiffies; 5257 fcport->sec_since_registration = 0; 5258 fcport->next_disc_state = DSC_DELETED; 5259 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5260 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5261 5262 queue_work(system_unbound_wq, &fcport->reg_work); 5263 } 5264 5265 static 5266 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5267 { 5268 unsigned long flags; 5269 fc_port_t *fcport = NULL, *tfcp; 5270 struct qlt_plogi_ack_t *pla = 5271 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5272 uint8_t free_fcport = 0; 5273 5274 ql_dbg(ql_dbg_disc, vha, 0xffff, 5275 "%s %d %8phC enter\n", 5276 __func__, __LINE__, e->u.new_sess.port_name); 5277 5278 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5279 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5280 if (fcport) { 5281 fcport->d_id = e->u.new_sess.id; 5282 if (pla) { 5283 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5284 memcpy(fcport->node_name, 5285 pla->iocb.u.isp24.u.plogi.node_name, 5286 WWN_SIZE); 5287 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5288 /* we took an extra ref_count to prevent PLOGI ACK when 5289 * fcport/sess has not been created. 5290 */ 5291 pla->ref_count--; 5292 } 5293 } else { 5294 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5295 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5296 if (fcport) { 5297 fcport->d_id = e->u.new_sess.id; 5298 fcport->flags |= FCF_FABRIC_DEVICE; 5299 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5300 fcport->tgt_short_link_down_cnt = 0; 5301 5302 memcpy(fcport->port_name, e->u.new_sess.port_name, 5303 WWN_SIZE); 5304 5305 fcport->fc4_type = e->u.new_sess.fc4_type; 5306 if (NVME_PRIORITY(vha->hw, fcport)) 5307 fcport->do_prli_nvme = 1; 5308 else 5309 fcport->do_prli_nvme = 0; 5310 5311 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5312 fcport->dm_login_expire = jiffies + 5313 QLA_N2N_WAIT_TIME * HZ; 5314 fcport->fc4_type = FS_FC4TYPE_FCP; 5315 fcport->n2n_flag = 1; 5316 if (vha->flags.nvme_enabled) 5317 fcport->fc4_type |= FS_FC4TYPE_NVME; 5318 } 5319 5320 } else { 5321 ql_dbg(ql_dbg_disc, vha, 0xffff, 5322 "%s %8phC mem alloc fail.\n", 5323 __func__, e->u.new_sess.port_name); 5324 5325 if (pla) { 5326 list_del(&pla->list); 5327 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5328 } 5329 return; 5330 } 5331 5332 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5333 /* search again to make sure no one else got ahead */ 5334 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5335 e->u.new_sess.port_name, 1); 5336 if (tfcp) { 5337 /* should rarily happen */ 5338 ql_dbg(ql_dbg_disc, vha, 0xffff, 5339 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5340 __func__, tfcp->port_name, tfcp->disc_state, 5341 tfcp->fw_login_state); 5342 5343 free_fcport = 1; 5344 } else { 5345 list_add_tail(&fcport->list, &vha->vp_fcports); 5346 5347 } 5348 if (pla) { 5349 qlt_plogi_ack_link(vha, pla, fcport, 5350 QLT_PLOGI_LINK_SAME_WWN); 5351 pla->ref_count--; 5352 } 5353 } 5354 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5355 5356 if (fcport) { 5357 fcport->id_changed = 1; 5358 fcport->scan_state = QLA_FCPORT_FOUND; 5359 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5360 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5361 5362 if (pla) { 5363 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5364 u16 wd3_lo; 5365 5366 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5367 fcport->local = 0; 5368 fcport->loop_id = 5369 le16_to_cpu( 5370 pla->iocb.u.isp24.nport_handle); 5371 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5372 wd3_lo = 5373 le16_to_cpu( 5374 pla->iocb.u.isp24.u.prli.wd3_lo); 5375 5376 if (wd3_lo & BIT_7) 5377 fcport->conf_compl_supported = 1; 5378 5379 if ((wd3_lo & BIT_4) == 0) 5380 fcport->port_type = FCT_INITIATOR; 5381 else 5382 fcport->port_type = FCT_TARGET; 5383 } 5384 qlt_plogi_ack_unref(vha, pla); 5385 } else { 5386 fc_port_t *dfcp = NULL; 5387 5388 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5389 tfcp = qla2x00_find_fcport_by_nportid(vha, 5390 &e->u.new_sess.id, 1); 5391 if (tfcp && (tfcp != fcport)) { 5392 /* 5393 * We have a conflict fcport with same NportID. 5394 */ 5395 ql_dbg(ql_dbg_disc, vha, 0xffff, 5396 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5397 __func__, tfcp->port_name, tfcp->disc_state, 5398 tfcp->fw_login_state); 5399 5400 switch (tfcp->disc_state) { 5401 case DSC_DELETED: 5402 break; 5403 case DSC_DELETE_PEND: 5404 fcport->login_pause = 1; 5405 tfcp->conflict = fcport; 5406 break; 5407 default: 5408 fcport->login_pause = 1; 5409 tfcp->conflict = fcport; 5410 dfcp = tfcp; 5411 break; 5412 } 5413 } 5414 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5415 if (dfcp) 5416 qlt_schedule_sess_for_deletion(tfcp); 5417 5418 if (N2N_TOPO(vha->hw)) { 5419 fcport->flags &= ~FCF_FABRIC_DEVICE; 5420 fcport->keep_nport_handle = 1; 5421 if (vha->flags.nvme_enabled) { 5422 fcport->fc4_type = 5423 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5424 fcport->n2n_flag = 1; 5425 } 5426 fcport->fw_login_state = 0; 5427 5428 schedule_delayed_work(&vha->scan.scan_work, 5); 5429 } else { 5430 qla24xx_fcport_handle_login(vha, fcport); 5431 } 5432 } 5433 } 5434 5435 if (free_fcport) { 5436 qla2x00_free_fcport(fcport); 5437 if (pla) { 5438 list_del(&pla->list); 5439 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5440 } 5441 } 5442 } 5443 5444 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5445 { 5446 struct srb *sp = e->u.iosb.sp; 5447 int rval; 5448 5449 rval = qla2x00_start_sp(sp); 5450 if (rval != QLA_SUCCESS) { 5451 ql_dbg(ql_dbg_disc, vha, 0x2043, 5452 "%s: %s: Re-issue IOCB failed (%d).\n", 5453 __func__, sp->name, rval); 5454 qla24xx_sp_unmap(vha, sp); 5455 } 5456 } 5457 5458 void 5459 qla2x00_do_work(struct scsi_qla_host *vha) 5460 { 5461 struct qla_work_evt *e, *tmp; 5462 unsigned long flags; 5463 LIST_HEAD(work); 5464 int rc; 5465 5466 spin_lock_irqsave(&vha->work_lock, flags); 5467 list_splice_init(&vha->work_list, &work); 5468 spin_unlock_irqrestore(&vha->work_lock, flags); 5469 5470 list_for_each_entry_safe(e, tmp, &work, list) { 5471 rc = QLA_SUCCESS; 5472 switch (e->type) { 5473 case QLA_EVT_AEN: 5474 fc_host_post_event(vha->host, fc_get_event_number(), 5475 e->u.aen.code, e->u.aen.data); 5476 break; 5477 case QLA_EVT_IDC_ACK: 5478 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5479 break; 5480 case QLA_EVT_ASYNC_LOGIN: 5481 qla2x00_async_login(vha, e->u.logio.fcport, 5482 e->u.logio.data); 5483 break; 5484 case QLA_EVT_ASYNC_LOGOUT: 5485 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5486 break; 5487 case QLA_EVT_ASYNC_ADISC: 5488 qla2x00_async_adisc(vha, e->u.logio.fcport, 5489 e->u.logio.data); 5490 break; 5491 case QLA_EVT_UEVENT: 5492 qla2x00_uevent_emit(vha, e->u.uevent.code); 5493 break; 5494 case QLA_EVT_AENFX: 5495 qlafx00_process_aen(vha, e); 5496 break; 5497 case QLA_EVT_UNMAP: 5498 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5499 break; 5500 case QLA_EVT_RELOGIN: 5501 qla2x00_relogin(vha); 5502 break; 5503 case QLA_EVT_NEW_SESS: 5504 qla24xx_create_new_sess(vha, e); 5505 break; 5506 case QLA_EVT_GPDB: 5507 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5508 e->u.fcport.opt); 5509 break; 5510 case QLA_EVT_PRLI: 5511 qla24xx_async_prli(vha, e->u.fcport.fcport); 5512 break; 5513 case QLA_EVT_GPSC: 5514 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5515 break; 5516 case QLA_EVT_GNL: 5517 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5518 break; 5519 case QLA_EVT_NACK: 5520 qla24xx_do_nack_work(vha, e); 5521 break; 5522 case QLA_EVT_ASYNC_PRLO: 5523 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5524 break; 5525 case QLA_EVT_ASYNC_PRLO_DONE: 5526 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5527 e->u.logio.data); 5528 break; 5529 case QLA_EVT_GPNFT: 5530 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5531 e->u.gpnft.sp); 5532 break; 5533 case QLA_EVT_GPNFT_DONE: 5534 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5535 break; 5536 case QLA_EVT_GNNFT_DONE: 5537 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5538 break; 5539 case QLA_EVT_GFPNID: 5540 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5541 break; 5542 case QLA_EVT_SP_RETRY: 5543 qla_sp_retry(vha, e); 5544 break; 5545 case QLA_EVT_IIDMA: 5546 qla_do_iidma_work(vha, e->u.fcport.fcport); 5547 break; 5548 case QLA_EVT_ELS_PLOGI: 5549 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5550 e->u.fcport.fcport, false); 5551 break; 5552 case QLA_EVT_SA_REPLACE: 5553 rc = qla24xx_issue_sa_replace_iocb(vha, e); 5554 break; 5555 } 5556 5557 if (rc == EAGAIN) { 5558 /* put 'work' at head of 'vha->work_list' */ 5559 spin_lock_irqsave(&vha->work_lock, flags); 5560 list_splice(&work, &vha->work_list); 5561 spin_unlock_irqrestore(&vha->work_lock, flags); 5562 break; 5563 } 5564 list_del_init(&e->list); 5565 if (e->flags & QLA_EVT_FLAG_FREE) 5566 kfree(e); 5567 5568 /* For each work completed decrement vha ref count */ 5569 QLA_VHA_MARK_NOT_BUSY(vha); 5570 } 5571 } 5572 5573 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5574 { 5575 struct qla_work_evt *e; 5576 5577 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5578 5579 if (!e) { 5580 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5581 return QLA_FUNCTION_FAILED; 5582 } 5583 5584 return qla2x00_post_work(vha, e); 5585 } 5586 5587 /* Relogins all the fcports of a vport 5588 * Context: dpc thread 5589 */ 5590 void qla2x00_relogin(struct scsi_qla_host *vha) 5591 { 5592 fc_port_t *fcport; 5593 int status, relogin_needed = 0; 5594 struct event_arg ea; 5595 5596 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5597 /* 5598 * If the port is not ONLINE then try to login 5599 * to it if we haven't run out of retries. 5600 */ 5601 if (atomic_read(&fcport->state) != FCS_ONLINE && 5602 fcport->login_retry) { 5603 if (fcport->scan_state != QLA_FCPORT_FOUND || 5604 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5605 fcport->disc_state == DSC_LOGIN_COMPLETE) 5606 continue; 5607 5608 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5609 fcport->disc_state == DSC_DELETE_PEND) { 5610 relogin_needed = 1; 5611 } else { 5612 if (vha->hw->current_topology != ISP_CFG_NL) { 5613 memset(&ea, 0, sizeof(ea)); 5614 ea.fcport = fcport; 5615 qla24xx_handle_relogin_event(vha, &ea); 5616 } else if (vha->hw->current_topology == 5617 ISP_CFG_NL && 5618 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5619 (void)qla24xx_fcport_handle_login(vha, 5620 fcport); 5621 } else if (vha->hw->current_topology == 5622 ISP_CFG_NL) { 5623 fcport->login_retry--; 5624 status = 5625 qla2x00_local_device_login(vha, 5626 fcport); 5627 if (status == QLA_SUCCESS) { 5628 fcport->old_loop_id = 5629 fcport->loop_id; 5630 ql_dbg(ql_dbg_disc, vha, 0x2003, 5631 "Port login OK: logged in ID 0x%x.\n", 5632 fcport->loop_id); 5633 qla2x00_update_fcport 5634 (vha, fcport); 5635 } else if (status == 1) { 5636 set_bit(RELOGIN_NEEDED, 5637 &vha->dpc_flags); 5638 /* retry the login again */ 5639 ql_dbg(ql_dbg_disc, vha, 0x2007, 5640 "Retrying %d login again loop_id 0x%x.\n", 5641 fcport->login_retry, 5642 fcport->loop_id); 5643 } else { 5644 fcport->login_retry = 0; 5645 } 5646 5647 if (fcport->login_retry == 0 && 5648 status != QLA_SUCCESS) 5649 qla2x00_clear_loop_id(fcport); 5650 } 5651 } 5652 } 5653 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5654 break; 5655 } 5656 5657 if (relogin_needed) 5658 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5659 5660 ql_dbg(ql_dbg_disc, vha, 0x400e, 5661 "Relogin end.\n"); 5662 } 5663 5664 /* Schedule work on any of the dpc-workqueues */ 5665 void 5666 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5667 { 5668 struct qla_hw_data *ha = base_vha->hw; 5669 5670 switch (work_code) { 5671 case MBA_IDC_AEN: /* 0x8200 */ 5672 if (ha->dpc_lp_wq) 5673 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5674 break; 5675 5676 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5677 if (!ha->flags.nic_core_reset_hdlr_active) { 5678 if (ha->dpc_hp_wq) 5679 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5680 } else 5681 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5682 "NIC Core reset is already active. Skip " 5683 "scheduling it again.\n"); 5684 break; 5685 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5686 if (ha->dpc_hp_wq) 5687 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5688 break; 5689 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5690 if (ha->dpc_hp_wq) 5691 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5692 break; 5693 default: 5694 ql_log(ql_log_warn, base_vha, 0xb05f, 5695 "Unknown work-code=0x%x.\n", work_code); 5696 } 5697 5698 return; 5699 } 5700 5701 /* Work: Perform NIC Core Unrecoverable state handling */ 5702 void 5703 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5704 { 5705 struct qla_hw_data *ha = 5706 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5707 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5708 uint32_t dev_state = 0; 5709 5710 qla83xx_idc_lock(base_vha, 0); 5711 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5712 qla83xx_reset_ownership(base_vha); 5713 if (ha->flags.nic_core_reset_owner) { 5714 ha->flags.nic_core_reset_owner = 0; 5715 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5716 QLA8XXX_DEV_FAILED); 5717 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5718 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5719 } 5720 qla83xx_idc_unlock(base_vha, 0); 5721 } 5722 5723 /* Work: Execute IDC state handler */ 5724 void 5725 qla83xx_idc_state_handler_work(struct work_struct *work) 5726 { 5727 struct qla_hw_data *ha = 5728 container_of(work, struct qla_hw_data, idc_state_handler); 5729 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5730 uint32_t dev_state = 0; 5731 5732 qla83xx_idc_lock(base_vha, 0); 5733 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5734 if (dev_state == QLA8XXX_DEV_FAILED || 5735 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5736 qla83xx_idc_state_handler(base_vha); 5737 qla83xx_idc_unlock(base_vha, 0); 5738 } 5739 5740 static int 5741 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5742 { 5743 int rval = QLA_SUCCESS; 5744 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5745 uint32_t heart_beat_counter1, heart_beat_counter2; 5746 5747 do { 5748 if (time_after(jiffies, heart_beat_wait)) { 5749 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5750 "Nic Core f/w is not alive.\n"); 5751 rval = QLA_FUNCTION_FAILED; 5752 break; 5753 } 5754 5755 qla83xx_idc_lock(base_vha, 0); 5756 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5757 &heart_beat_counter1); 5758 qla83xx_idc_unlock(base_vha, 0); 5759 msleep(100); 5760 qla83xx_idc_lock(base_vha, 0); 5761 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5762 &heart_beat_counter2); 5763 qla83xx_idc_unlock(base_vha, 0); 5764 } while (heart_beat_counter1 == heart_beat_counter2); 5765 5766 return rval; 5767 } 5768 5769 /* Work: Perform NIC Core Reset handling */ 5770 void 5771 qla83xx_nic_core_reset_work(struct work_struct *work) 5772 { 5773 struct qla_hw_data *ha = 5774 container_of(work, struct qla_hw_data, nic_core_reset); 5775 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5776 uint32_t dev_state = 0; 5777 5778 if (IS_QLA2031(ha)) { 5779 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5780 ql_log(ql_log_warn, base_vha, 0xb081, 5781 "Failed to dump mctp\n"); 5782 return; 5783 } 5784 5785 if (!ha->flags.nic_core_reset_hdlr_active) { 5786 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5787 qla83xx_idc_lock(base_vha, 0); 5788 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5789 &dev_state); 5790 qla83xx_idc_unlock(base_vha, 0); 5791 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5792 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5793 "Nic Core f/w is alive.\n"); 5794 return; 5795 } 5796 } 5797 5798 ha->flags.nic_core_reset_hdlr_active = 1; 5799 if (qla83xx_nic_core_reset(base_vha)) { 5800 /* NIC Core reset failed. */ 5801 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5802 "NIC Core reset failed.\n"); 5803 } 5804 ha->flags.nic_core_reset_hdlr_active = 0; 5805 } 5806 } 5807 5808 /* Work: Handle 8200 IDC aens */ 5809 void 5810 qla83xx_service_idc_aen(struct work_struct *work) 5811 { 5812 struct qla_hw_data *ha = 5813 container_of(work, struct qla_hw_data, idc_aen); 5814 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5815 uint32_t dev_state, idc_control; 5816 5817 qla83xx_idc_lock(base_vha, 0); 5818 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5819 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5820 qla83xx_idc_unlock(base_vha, 0); 5821 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5822 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5823 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5824 "Application requested NIC Core Reset.\n"); 5825 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5826 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5827 QLA_SUCCESS) { 5828 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5829 "Other protocol driver requested NIC Core Reset.\n"); 5830 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5831 } 5832 } else if (dev_state == QLA8XXX_DEV_FAILED || 5833 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5834 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5835 } 5836 } 5837 5838 /* 5839 * Control the frequency of IDC lock retries 5840 */ 5841 #define QLA83XX_WAIT_LOGIC_MS 100 5842 5843 static int 5844 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5845 { 5846 int rval; 5847 uint32_t data; 5848 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5849 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5850 struct qla_hw_data *ha = base_vha->hw; 5851 5852 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5853 "Trying force recovery of the IDC lock.\n"); 5854 5855 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5856 if (rval) 5857 return rval; 5858 5859 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5860 return QLA_SUCCESS; 5861 } else { 5862 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5863 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5864 data); 5865 if (rval) 5866 return rval; 5867 5868 msleep(200); 5869 5870 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5871 &data); 5872 if (rval) 5873 return rval; 5874 5875 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5876 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5877 ~(idc_lck_rcvry_stage_mask)); 5878 rval = qla83xx_wr_reg(base_vha, 5879 QLA83XX_IDC_LOCK_RECOVERY, data); 5880 if (rval) 5881 return rval; 5882 5883 /* Forcefully perform IDC UnLock */ 5884 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5885 &data); 5886 if (rval) 5887 return rval; 5888 /* Clear lock-id by setting 0xff */ 5889 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5890 0xff); 5891 if (rval) 5892 return rval; 5893 /* Clear lock-recovery by setting 0x0 */ 5894 rval = qla83xx_wr_reg(base_vha, 5895 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5896 if (rval) 5897 return rval; 5898 } else 5899 return QLA_SUCCESS; 5900 } 5901 5902 return rval; 5903 } 5904 5905 static int 5906 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5907 { 5908 int rval = QLA_SUCCESS; 5909 uint32_t o_drv_lockid, n_drv_lockid; 5910 unsigned long lock_recovery_timeout; 5911 5912 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5913 retry_lockid: 5914 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5915 if (rval) 5916 goto exit; 5917 5918 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5919 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5920 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5921 return QLA_SUCCESS; 5922 else 5923 return QLA_FUNCTION_FAILED; 5924 } 5925 5926 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5927 if (rval) 5928 goto exit; 5929 5930 if (o_drv_lockid == n_drv_lockid) { 5931 msleep(QLA83XX_WAIT_LOGIC_MS); 5932 goto retry_lockid; 5933 } else 5934 return QLA_SUCCESS; 5935 5936 exit: 5937 return rval; 5938 } 5939 5940 /* 5941 * Context: task, can sleep 5942 */ 5943 void 5944 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5945 { 5946 uint32_t data; 5947 uint32_t lock_owner; 5948 struct qla_hw_data *ha = base_vha->hw; 5949 5950 might_sleep(); 5951 5952 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5953 retry_lock: 5954 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5955 == QLA_SUCCESS) { 5956 if (data) { 5957 /* Setting lock-id to our function-number */ 5958 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5959 ha->portnum); 5960 } else { 5961 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5962 &lock_owner); 5963 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5964 "Failed to acquire IDC lock, acquired by %d, " 5965 "retrying...\n", lock_owner); 5966 5967 /* Retry/Perform IDC-Lock recovery */ 5968 if (qla83xx_idc_lock_recovery(base_vha) 5969 == QLA_SUCCESS) { 5970 msleep(QLA83XX_WAIT_LOGIC_MS); 5971 goto retry_lock; 5972 } else 5973 ql_log(ql_log_warn, base_vha, 0xb075, 5974 "IDC Lock recovery FAILED.\n"); 5975 } 5976 5977 } 5978 5979 return; 5980 } 5981 5982 static bool 5983 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5984 struct purex_entry_24xx *purex) 5985 { 5986 char fwstr[16]; 5987 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5988 struct port_database_24xx *pdb; 5989 5990 /* Domain Controller is always logged-out. */ 5991 /* if RDP request is not from Domain Controller: */ 5992 if (sid != 0xfffc01) 5993 return false; 5994 5995 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5996 5997 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5998 if (!pdb) { 5999 ql_dbg(ql_dbg_init, vha, 0x0181, 6000 "%s: Failed allocate pdb\n", __func__); 6001 } else if (qla24xx_get_port_database(vha, 6002 le16_to_cpu(purex->nport_handle), pdb)) { 6003 ql_dbg(ql_dbg_init, vha, 0x0181, 6004 "%s: Failed get pdb sid=%x\n", __func__, sid); 6005 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 6006 pdb->current_login_state != PDS_PRLI_COMPLETE) { 6007 ql_dbg(ql_dbg_init, vha, 0x0181, 6008 "%s: Port not logged in sid=%#x\n", __func__, sid); 6009 } else { 6010 /* RDP request is from logged in port */ 6011 kfree(pdb); 6012 return false; 6013 } 6014 kfree(pdb); 6015 6016 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 6017 fwstr[strcspn(fwstr, " ")] = 0; 6018 /* if FW version allows RDP response length upto 2048 bytes: */ 6019 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 6020 return false; 6021 6022 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 6023 6024 /* RDP response length is to be reduced to maximum 256 bytes */ 6025 return true; 6026 } 6027 6028 /* 6029 * Function Name: qla24xx_process_purex_iocb 6030 * 6031 * Description: 6032 * Prepare a RDP response and send to Fabric switch 6033 * 6034 * PARAMETERS: 6035 * vha: SCSI qla host 6036 * purex: RDP request received by HBA 6037 */ 6038 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 6039 struct purex_item *item) 6040 { 6041 struct qla_hw_data *ha = vha->hw; 6042 struct purex_entry_24xx *purex = 6043 (struct purex_entry_24xx *)&item->iocb; 6044 dma_addr_t rsp_els_dma; 6045 dma_addr_t rsp_payload_dma; 6046 dma_addr_t stat_dma; 6047 dma_addr_t sfp_dma; 6048 struct els_entry_24xx *rsp_els = NULL; 6049 struct rdp_rsp_payload *rsp_payload = NULL; 6050 struct link_statistics *stat = NULL; 6051 uint8_t *sfp = NULL; 6052 uint16_t sfp_flags = 0; 6053 uint rsp_payload_length = sizeof(*rsp_payload); 6054 int rval; 6055 6056 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 6057 "%s: Enter\n", __func__); 6058 6059 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 6060 "-------- ELS REQ -------\n"); 6061 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 6062 purex, sizeof(*purex)); 6063 6064 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 6065 rsp_payload_length = 6066 offsetof(typeof(*rsp_payload), optical_elmt_desc); 6067 ql_dbg(ql_dbg_init, vha, 0x0181, 6068 "Reducing RSP payload length to %u bytes...\n", 6069 rsp_payload_length); 6070 } 6071 6072 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6073 &rsp_els_dma, GFP_KERNEL); 6074 if (!rsp_els) { 6075 ql_log(ql_log_warn, vha, 0x0183, 6076 "Failed allocate dma buffer ELS RSP.\n"); 6077 goto dealloc; 6078 } 6079 6080 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6081 &rsp_payload_dma, GFP_KERNEL); 6082 if (!rsp_payload) { 6083 ql_log(ql_log_warn, vha, 0x0184, 6084 "Failed allocate dma buffer ELS RSP payload.\n"); 6085 goto dealloc; 6086 } 6087 6088 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6089 &sfp_dma, GFP_KERNEL); 6090 6091 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6092 &stat_dma, GFP_KERNEL); 6093 6094 /* Prepare Response IOCB */ 6095 rsp_els->entry_type = ELS_IOCB_TYPE; 6096 rsp_els->entry_count = 1; 6097 rsp_els->sys_define = 0; 6098 rsp_els->entry_status = 0; 6099 rsp_els->handle = 0; 6100 rsp_els->nport_handle = purex->nport_handle; 6101 rsp_els->tx_dsd_count = cpu_to_le16(1); 6102 rsp_els->vp_index = purex->vp_idx; 6103 rsp_els->sof_type = EST_SOFI3; 6104 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6105 rsp_els->rx_dsd_count = 0; 6106 rsp_els->opcode = purex->els_frame_payload[0]; 6107 6108 rsp_els->d_id[0] = purex->s_id[0]; 6109 rsp_els->d_id[1] = purex->s_id[1]; 6110 rsp_els->d_id[2] = purex->s_id[2]; 6111 6112 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6113 rsp_els->rx_byte_count = 0; 6114 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6115 6116 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6117 rsp_els->tx_len = rsp_els->tx_byte_count; 6118 6119 rsp_els->rx_address = 0; 6120 rsp_els->rx_len = 0; 6121 6122 /* Prepare Response Payload */ 6123 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6124 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6125 sizeof(rsp_payload->hdr)); 6126 6127 /* Link service Request Info Descriptor */ 6128 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6129 rsp_payload->ls_req_info_desc.desc_len = 6130 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6131 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6132 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6133 6134 /* Link service Request Info Descriptor 2 */ 6135 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6136 rsp_payload->ls_req_info_desc2.desc_len = 6137 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6138 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6139 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6140 6141 6142 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6143 rsp_payload->sfp_diag_desc.desc_len = 6144 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6145 6146 if (sfp) { 6147 /* SFP Flags */ 6148 memset(sfp, 0, SFP_RTDI_LEN); 6149 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6150 if (!rval) { 6151 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6152 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6153 sfp_flags |= BIT_0; /* short wave */ 6154 else if (sfp[0] & BIT_1) 6155 sfp_flags |= BIT_1; /* long wave 1310nm */ 6156 else if (sfp[1] & BIT_4) 6157 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6158 } 6159 6160 /* SFP Type */ 6161 memset(sfp, 0, SFP_RTDI_LEN); 6162 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6163 if (!rval) { 6164 sfp_flags |= BIT_4; /* optical */ 6165 if (sfp[0] == 0x3) 6166 sfp_flags |= BIT_6; /* sfp+ */ 6167 } 6168 6169 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6170 6171 /* SFP Diagnostics */ 6172 memset(sfp, 0, SFP_RTDI_LEN); 6173 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6174 if (!rval) { 6175 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6176 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6177 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6178 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6179 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6180 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6181 } 6182 } 6183 6184 /* Port Speed Descriptor */ 6185 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6186 rsp_payload->port_speed_desc.desc_len = 6187 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6188 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6189 qla25xx_fdmi_port_speed_capability(ha)); 6190 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6191 qla25xx_fdmi_port_speed_currently(ha)); 6192 6193 /* Link Error Status Descriptor */ 6194 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6195 rsp_payload->ls_err_desc.desc_len = 6196 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6197 6198 if (stat) { 6199 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6200 if (!rval) { 6201 rsp_payload->ls_err_desc.link_fail_cnt = 6202 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6203 rsp_payload->ls_err_desc.loss_sync_cnt = 6204 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6205 rsp_payload->ls_err_desc.loss_sig_cnt = 6206 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6207 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6208 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6209 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6210 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6211 rsp_payload->ls_err_desc.inval_crc_cnt = 6212 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6213 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6214 } 6215 } 6216 6217 /* Portname Descriptor */ 6218 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6219 rsp_payload->port_name_diag_desc.desc_len = 6220 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6221 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6222 vha->node_name, 6223 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6224 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6225 vha->port_name, 6226 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6227 6228 /* F-Port Portname Descriptor */ 6229 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6230 rsp_payload->port_name_direct_desc.desc_len = 6231 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6232 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6233 vha->fabric_node_name, 6234 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6235 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6236 vha->fabric_port_name, 6237 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6238 6239 /* Bufer Credit Descriptor */ 6240 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6241 rsp_payload->buffer_credit_desc.desc_len = 6242 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6243 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6244 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6245 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6246 6247 if (ha->flags.plogi_template_valid) { 6248 uint32_t tmp = 6249 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6250 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6251 } 6252 6253 if (rsp_payload_length < sizeof(*rsp_payload)) 6254 goto send; 6255 6256 /* Optical Element Descriptor, Temperature */ 6257 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6258 rsp_payload->optical_elmt_desc[0].desc_len = 6259 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6260 /* Optical Element Descriptor, Voltage */ 6261 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6262 rsp_payload->optical_elmt_desc[1].desc_len = 6263 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6264 /* Optical Element Descriptor, Tx Bias Current */ 6265 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6266 rsp_payload->optical_elmt_desc[2].desc_len = 6267 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6268 /* Optical Element Descriptor, Tx Power */ 6269 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6270 rsp_payload->optical_elmt_desc[3].desc_len = 6271 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6272 /* Optical Element Descriptor, Rx Power */ 6273 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6274 rsp_payload->optical_elmt_desc[4].desc_len = 6275 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6276 6277 if (sfp) { 6278 memset(sfp, 0, SFP_RTDI_LEN); 6279 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6280 if (!rval) { 6281 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6282 6283 /* Optical Element Descriptor, Temperature */ 6284 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6285 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6286 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6287 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6288 rsp_payload->optical_elmt_desc[0].element_flags = 6289 cpu_to_be32(1 << 28); 6290 6291 /* Optical Element Descriptor, Voltage */ 6292 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6293 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6294 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6295 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6296 rsp_payload->optical_elmt_desc[1].element_flags = 6297 cpu_to_be32(2 << 28); 6298 6299 /* Optical Element Descriptor, Tx Bias Current */ 6300 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6301 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6302 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6303 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6304 rsp_payload->optical_elmt_desc[2].element_flags = 6305 cpu_to_be32(3 << 28); 6306 6307 /* Optical Element Descriptor, Tx Power */ 6308 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6309 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6310 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6311 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6312 rsp_payload->optical_elmt_desc[3].element_flags = 6313 cpu_to_be32(4 << 28); 6314 6315 /* Optical Element Descriptor, Rx Power */ 6316 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6317 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6318 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6319 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6320 rsp_payload->optical_elmt_desc[4].element_flags = 6321 cpu_to_be32(5 << 28); 6322 } 6323 6324 memset(sfp, 0, SFP_RTDI_LEN); 6325 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6326 if (!rval) { 6327 /* Temperature high/low alarm/warning */ 6328 rsp_payload->optical_elmt_desc[0].element_flags |= 6329 cpu_to_be32( 6330 (sfp[0] >> 7 & 1) << 3 | 6331 (sfp[0] >> 6 & 1) << 2 | 6332 (sfp[4] >> 7 & 1) << 1 | 6333 (sfp[4] >> 6 & 1) << 0); 6334 6335 /* Voltage high/low alarm/warning */ 6336 rsp_payload->optical_elmt_desc[1].element_flags |= 6337 cpu_to_be32( 6338 (sfp[0] >> 5 & 1) << 3 | 6339 (sfp[0] >> 4 & 1) << 2 | 6340 (sfp[4] >> 5 & 1) << 1 | 6341 (sfp[4] >> 4 & 1) << 0); 6342 6343 /* Tx Bias Current high/low alarm/warning */ 6344 rsp_payload->optical_elmt_desc[2].element_flags |= 6345 cpu_to_be32( 6346 (sfp[0] >> 3 & 1) << 3 | 6347 (sfp[0] >> 2 & 1) << 2 | 6348 (sfp[4] >> 3 & 1) << 1 | 6349 (sfp[4] >> 2 & 1) << 0); 6350 6351 /* Tx Power high/low alarm/warning */ 6352 rsp_payload->optical_elmt_desc[3].element_flags |= 6353 cpu_to_be32( 6354 (sfp[0] >> 1 & 1) << 3 | 6355 (sfp[0] >> 0 & 1) << 2 | 6356 (sfp[4] >> 1 & 1) << 1 | 6357 (sfp[4] >> 0 & 1) << 0); 6358 6359 /* Rx Power high/low alarm/warning */ 6360 rsp_payload->optical_elmt_desc[4].element_flags |= 6361 cpu_to_be32( 6362 (sfp[1] >> 7 & 1) << 3 | 6363 (sfp[1] >> 6 & 1) << 2 | 6364 (sfp[5] >> 7 & 1) << 1 | 6365 (sfp[5] >> 6 & 1) << 0); 6366 } 6367 } 6368 6369 /* Optical Product Data Descriptor */ 6370 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6371 rsp_payload->optical_prod_desc.desc_len = 6372 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6373 6374 if (sfp) { 6375 memset(sfp, 0, SFP_RTDI_LEN); 6376 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6377 if (!rval) { 6378 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6379 sfp + 0, 6380 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6381 memcpy(rsp_payload->optical_prod_desc.part_number, 6382 sfp + 20, 6383 sizeof(rsp_payload->optical_prod_desc.part_number)); 6384 memcpy(rsp_payload->optical_prod_desc.revision, 6385 sfp + 36, 6386 sizeof(rsp_payload->optical_prod_desc.revision)); 6387 memcpy(rsp_payload->optical_prod_desc.serial_number, 6388 sfp + 48, 6389 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6390 } 6391 6392 memset(sfp, 0, SFP_RTDI_LEN); 6393 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6394 if (!rval) { 6395 memcpy(rsp_payload->optical_prod_desc.date, 6396 sfp + 0, 6397 sizeof(rsp_payload->optical_prod_desc.date)); 6398 } 6399 } 6400 6401 send: 6402 ql_dbg(ql_dbg_init, vha, 0x0183, 6403 "Sending ELS Response to RDP Request...\n"); 6404 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6405 "-------- ELS RSP -------\n"); 6406 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6407 rsp_els, sizeof(*rsp_els)); 6408 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6409 "-------- ELS RSP PAYLOAD -------\n"); 6410 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6411 rsp_payload, rsp_payload_length); 6412 6413 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6414 6415 if (rval) { 6416 ql_log(ql_log_warn, vha, 0x0188, 6417 "%s: iocb failed to execute -> %x\n", __func__, rval); 6418 } else if (rsp_els->comp_status) { 6419 ql_log(ql_log_warn, vha, 0x0189, 6420 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6421 __func__, rsp_els->comp_status, 6422 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6423 } else { 6424 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6425 } 6426 6427 dealloc: 6428 if (stat) 6429 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6430 stat, stat_dma); 6431 if (sfp) 6432 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6433 sfp, sfp_dma); 6434 if (rsp_payload) 6435 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6436 rsp_payload, rsp_payload_dma); 6437 if (rsp_els) 6438 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6439 rsp_els, rsp_els_dma); 6440 } 6441 6442 void 6443 qla24xx_free_purex_item(struct purex_item *item) 6444 { 6445 if (item == &item->vha->default_item) 6446 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6447 else 6448 kfree(item); 6449 } 6450 6451 void qla24xx_process_purex_list(struct purex_list *list) 6452 { 6453 struct list_head head = LIST_HEAD_INIT(head); 6454 struct purex_item *item, *next; 6455 ulong flags; 6456 6457 spin_lock_irqsave(&list->lock, flags); 6458 list_splice_init(&list->head, &head); 6459 spin_unlock_irqrestore(&list->lock, flags); 6460 6461 list_for_each_entry_safe(item, next, &head, list) { 6462 list_del(&item->list); 6463 item->process_item(item->vha, item); 6464 qla24xx_free_purex_item(item); 6465 } 6466 } 6467 6468 /* 6469 * Context: task, can sleep 6470 */ 6471 void 6472 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6473 { 6474 #if 0 6475 uint16_t options = (requester_id << 15) | BIT_7; 6476 #endif 6477 uint16_t retry; 6478 uint32_t data; 6479 struct qla_hw_data *ha = base_vha->hw; 6480 6481 might_sleep(); 6482 6483 /* IDC-unlock implementation using driver-unlock/lock-id 6484 * remote registers 6485 */ 6486 retry = 0; 6487 retry_unlock: 6488 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6489 == QLA_SUCCESS) { 6490 if (data == ha->portnum) { 6491 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6492 /* Clearing lock-id by setting 0xff */ 6493 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6494 } else if (retry < 10) { 6495 /* SV: XXX: IDC unlock retrying needed here? */ 6496 6497 /* Retry for IDC-unlock */ 6498 msleep(QLA83XX_WAIT_LOGIC_MS); 6499 retry++; 6500 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6501 "Failed to release IDC lock, retrying=%d\n", retry); 6502 goto retry_unlock; 6503 } 6504 } else if (retry < 10) { 6505 /* Retry for IDC-unlock */ 6506 msleep(QLA83XX_WAIT_LOGIC_MS); 6507 retry++; 6508 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6509 "Failed to read drv-lockid, retrying=%d\n", retry); 6510 goto retry_unlock; 6511 } 6512 6513 return; 6514 6515 #if 0 6516 /* XXX: IDC-unlock implementation using access-control mbx */ 6517 retry = 0; 6518 retry_unlock2: 6519 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6520 if (retry < 10) { 6521 /* Retry for IDC-unlock */ 6522 msleep(QLA83XX_WAIT_LOGIC_MS); 6523 retry++; 6524 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6525 "Failed to release IDC lock, retrying=%d\n", retry); 6526 goto retry_unlock2; 6527 } 6528 } 6529 6530 return; 6531 #endif 6532 } 6533 6534 int 6535 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6536 { 6537 int rval = QLA_SUCCESS; 6538 struct qla_hw_data *ha = vha->hw; 6539 uint32_t drv_presence; 6540 6541 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6542 if (rval == QLA_SUCCESS) { 6543 drv_presence |= (1 << ha->portnum); 6544 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6545 drv_presence); 6546 } 6547 6548 return rval; 6549 } 6550 6551 int 6552 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6553 { 6554 int rval = QLA_SUCCESS; 6555 6556 qla83xx_idc_lock(vha, 0); 6557 rval = __qla83xx_set_drv_presence(vha); 6558 qla83xx_idc_unlock(vha, 0); 6559 6560 return rval; 6561 } 6562 6563 int 6564 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6565 { 6566 int rval = QLA_SUCCESS; 6567 struct qla_hw_data *ha = vha->hw; 6568 uint32_t drv_presence; 6569 6570 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6571 if (rval == QLA_SUCCESS) { 6572 drv_presence &= ~(1 << ha->portnum); 6573 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6574 drv_presence); 6575 } 6576 6577 return rval; 6578 } 6579 6580 int 6581 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6582 { 6583 int rval = QLA_SUCCESS; 6584 6585 qla83xx_idc_lock(vha, 0); 6586 rval = __qla83xx_clear_drv_presence(vha); 6587 qla83xx_idc_unlock(vha, 0); 6588 6589 return rval; 6590 } 6591 6592 static void 6593 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6594 { 6595 struct qla_hw_data *ha = vha->hw; 6596 uint32_t drv_ack, drv_presence; 6597 unsigned long ack_timeout; 6598 6599 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6600 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6601 while (1) { 6602 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6603 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6604 if ((drv_ack & drv_presence) == drv_presence) 6605 break; 6606 6607 if (time_after_eq(jiffies, ack_timeout)) { 6608 ql_log(ql_log_warn, vha, 0xb067, 6609 "RESET ACK TIMEOUT! drv_presence=0x%x " 6610 "drv_ack=0x%x\n", drv_presence, drv_ack); 6611 /* 6612 * The function(s) which did not ack in time are forced 6613 * to withdraw any further participation in the IDC 6614 * reset. 6615 */ 6616 if (drv_ack != drv_presence) 6617 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6618 drv_ack); 6619 break; 6620 } 6621 6622 qla83xx_idc_unlock(vha, 0); 6623 msleep(1000); 6624 qla83xx_idc_lock(vha, 0); 6625 } 6626 6627 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6628 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6629 } 6630 6631 static int 6632 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6633 { 6634 int rval = QLA_SUCCESS; 6635 uint32_t idc_control; 6636 6637 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6638 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6639 6640 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6641 __qla83xx_get_idc_control(vha, &idc_control); 6642 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6643 __qla83xx_set_idc_control(vha, 0); 6644 6645 qla83xx_idc_unlock(vha, 0); 6646 rval = qla83xx_restart_nic_firmware(vha); 6647 qla83xx_idc_lock(vha, 0); 6648 6649 if (rval != QLA_SUCCESS) { 6650 ql_log(ql_log_fatal, vha, 0xb06a, 6651 "Failed to restart NIC f/w.\n"); 6652 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6653 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6654 } else { 6655 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6656 "Success in restarting nic f/w.\n"); 6657 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6658 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6659 } 6660 6661 return rval; 6662 } 6663 6664 /* Assumes idc_lock always held on entry */ 6665 int 6666 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6667 { 6668 struct qla_hw_data *ha = base_vha->hw; 6669 int rval = QLA_SUCCESS; 6670 unsigned long dev_init_timeout; 6671 uint32_t dev_state; 6672 6673 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6674 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6675 6676 while (1) { 6677 6678 if (time_after_eq(jiffies, dev_init_timeout)) { 6679 ql_log(ql_log_warn, base_vha, 0xb06e, 6680 "Initialization TIMEOUT!\n"); 6681 /* Init timeout. Disable further NIC Core 6682 * communication. 6683 */ 6684 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6685 QLA8XXX_DEV_FAILED); 6686 ql_log(ql_log_info, base_vha, 0xb06f, 6687 "HW State: FAILED.\n"); 6688 } 6689 6690 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6691 switch (dev_state) { 6692 case QLA8XXX_DEV_READY: 6693 if (ha->flags.nic_core_reset_owner) 6694 qla83xx_idc_audit(base_vha, 6695 IDC_AUDIT_COMPLETION); 6696 ha->flags.nic_core_reset_owner = 0; 6697 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6698 "Reset_owner reset by 0x%x.\n", 6699 ha->portnum); 6700 goto exit; 6701 case QLA8XXX_DEV_COLD: 6702 if (ha->flags.nic_core_reset_owner) 6703 rval = qla83xx_device_bootstrap(base_vha); 6704 else { 6705 /* Wait for AEN to change device-state */ 6706 qla83xx_idc_unlock(base_vha, 0); 6707 msleep(1000); 6708 qla83xx_idc_lock(base_vha, 0); 6709 } 6710 break; 6711 case QLA8XXX_DEV_INITIALIZING: 6712 /* Wait for AEN to change device-state */ 6713 qla83xx_idc_unlock(base_vha, 0); 6714 msleep(1000); 6715 qla83xx_idc_lock(base_vha, 0); 6716 break; 6717 case QLA8XXX_DEV_NEED_RESET: 6718 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6719 qla83xx_need_reset_handler(base_vha); 6720 else { 6721 /* Wait for AEN to change device-state */ 6722 qla83xx_idc_unlock(base_vha, 0); 6723 msleep(1000); 6724 qla83xx_idc_lock(base_vha, 0); 6725 } 6726 /* reset timeout value after need reset handler */ 6727 dev_init_timeout = jiffies + 6728 (ha->fcoe_dev_init_timeout * HZ); 6729 break; 6730 case QLA8XXX_DEV_NEED_QUIESCENT: 6731 /* XXX: DEBUG for now */ 6732 qla83xx_idc_unlock(base_vha, 0); 6733 msleep(1000); 6734 qla83xx_idc_lock(base_vha, 0); 6735 break; 6736 case QLA8XXX_DEV_QUIESCENT: 6737 /* XXX: DEBUG for now */ 6738 if (ha->flags.quiesce_owner) 6739 goto exit; 6740 6741 qla83xx_idc_unlock(base_vha, 0); 6742 msleep(1000); 6743 qla83xx_idc_lock(base_vha, 0); 6744 dev_init_timeout = jiffies + 6745 (ha->fcoe_dev_init_timeout * HZ); 6746 break; 6747 case QLA8XXX_DEV_FAILED: 6748 if (ha->flags.nic_core_reset_owner) 6749 qla83xx_idc_audit(base_vha, 6750 IDC_AUDIT_COMPLETION); 6751 ha->flags.nic_core_reset_owner = 0; 6752 __qla83xx_clear_drv_presence(base_vha); 6753 qla83xx_idc_unlock(base_vha, 0); 6754 qla8xxx_dev_failed_handler(base_vha); 6755 rval = QLA_FUNCTION_FAILED; 6756 qla83xx_idc_lock(base_vha, 0); 6757 goto exit; 6758 case QLA8XXX_BAD_VALUE: 6759 qla83xx_idc_unlock(base_vha, 0); 6760 msleep(1000); 6761 qla83xx_idc_lock(base_vha, 0); 6762 break; 6763 default: 6764 ql_log(ql_log_warn, base_vha, 0xb071, 6765 "Unknown Device State: %x.\n", dev_state); 6766 qla83xx_idc_unlock(base_vha, 0); 6767 qla8xxx_dev_failed_handler(base_vha); 6768 rval = QLA_FUNCTION_FAILED; 6769 qla83xx_idc_lock(base_vha, 0); 6770 goto exit; 6771 } 6772 } 6773 6774 exit: 6775 return rval; 6776 } 6777 6778 void 6779 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6780 { 6781 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6782 board_disable); 6783 struct pci_dev *pdev = ha->pdev; 6784 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6785 6786 ql_log(ql_log_warn, base_vha, 0x015b, 6787 "Disabling adapter.\n"); 6788 6789 if (!atomic_read(&pdev->enable_cnt)) { 6790 ql_log(ql_log_info, base_vha, 0xfffc, 6791 "PCI device disabled, no action req for PCI error=%lx\n", 6792 base_vha->pci_flags); 6793 return; 6794 } 6795 6796 /* 6797 * if UNLOADING flag is already set, then continue unload, 6798 * where it was set first. 6799 */ 6800 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6801 return; 6802 6803 qla2x00_wait_for_sess_deletion(base_vha); 6804 6805 qla2x00_delete_all_vps(ha, base_vha); 6806 6807 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6808 6809 qla2x00_dfs_remove(base_vha); 6810 6811 qla84xx_put_chip(base_vha); 6812 6813 if (base_vha->timer_active) 6814 qla2x00_stop_timer(base_vha); 6815 6816 base_vha->flags.online = 0; 6817 6818 qla2x00_destroy_deferred_work(ha); 6819 6820 /* 6821 * Do not try to stop beacon blink as it will issue a mailbox 6822 * command. 6823 */ 6824 qla2x00_free_sysfs_attr(base_vha, false); 6825 6826 fc_remove_host(base_vha->host); 6827 6828 scsi_remove_host(base_vha->host); 6829 6830 base_vha->flags.init_done = 0; 6831 qla25xx_delete_queues(base_vha); 6832 qla2x00_free_fcports(base_vha); 6833 qla2x00_free_irqs(base_vha); 6834 qla2x00_mem_free(ha); 6835 qla82xx_md_free(base_vha); 6836 qla2x00_free_queues(ha); 6837 6838 qla2x00_unmap_iobases(ha); 6839 6840 pci_release_selected_regions(ha->pdev, ha->bars); 6841 pci_disable_device(pdev); 6842 6843 /* 6844 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6845 */ 6846 } 6847 6848 /************************************************************************** 6849 * qla2x00_do_dpc 6850 * This kernel thread is a task that is schedule by the interrupt handler 6851 * to perform the background processing for interrupts. 6852 * 6853 * Notes: 6854 * This task always run in the context of a kernel thread. It 6855 * is kick-off by the driver's detect code and starts up 6856 * up one per adapter. It immediately goes to sleep and waits for 6857 * some fibre event. When either the interrupt handler or 6858 * the timer routine detects a event it will one of the task 6859 * bits then wake us up. 6860 **************************************************************************/ 6861 static int 6862 qla2x00_do_dpc(void *data) 6863 { 6864 scsi_qla_host_t *base_vha; 6865 struct qla_hw_data *ha; 6866 uint32_t online; 6867 struct qla_qpair *qpair; 6868 6869 ha = (struct qla_hw_data *)data; 6870 base_vha = pci_get_drvdata(ha->pdev); 6871 6872 set_user_nice(current, MIN_NICE); 6873 6874 set_current_state(TASK_INTERRUPTIBLE); 6875 while (!kthread_should_stop()) { 6876 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6877 "DPC handler sleeping.\n"); 6878 6879 schedule(); 6880 6881 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6882 qla_pci_set_eeh_busy(base_vha); 6883 6884 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6885 goto end_loop; 6886 6887 if (ha->flags.eeh_busy) { 6888 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6889 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6890 goto end_loop; 6891 } 6892 6893 ha->dpc_active = 1; 6894 6895 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6896 "DPC handler waking up, dpc_flags=0x%lx.\n", 6897 base_vha->dpc_flags); 6898 6899 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6900 break; 6901 6902 if (IS_P3P_TYPE(ha)) { 6903 if (IS_QLA8044(ha)) { 6904 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6905 &base_vha->dpc_flags)) { 6906 qla8044_idc_lock(ha); 6907 qla8044_wr_direct(base_vha, 6908 QLA8044_CRB_DEV_STATE_INDEX, 6909 QLA8XXX_DEV_FAILED); 6910 qla8044_idc_unlock(ha); 6911 ql_log(ql_log_info, base_vha, 0x4004, 6912 "HW State: FAILED.\n"); 6913 qla8044_device_state_handler(base_vha); 6914 continue; 6915 } 6916 6917 } else { 6918 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6919 &base_vha->dpc_flags)) { 6920 qla82xx_idc_lock(ha); 6921 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6922 QLA8XXX_DEV_FAILED); 6923 qla82xx_idc_unlock(ha); 6924 ql_log(ql_log_info, base_vha, 0x0151, 6925 "HW State: FAILED.\n"); 6926 qla82xx_device_state_handler(base_vha); 6927 continue; 6928 } 6929 } 6930 6931 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6932 &base_vha->dpc_flags)) { 6933 6934 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6935 "FCoE context reset scheduled.\n"); 6936 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6937 &base_vha->dpc_flags))) { 6938 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6939 /* FCoE-ctx reset failed. 6940 * Escalate to chip-reset 6941 */ 6942 set_bit(ISP_ABORT_NEEDED, 6943 &base_vha->dpc_flags); 6944 } 6945 clear_bit(ABORT_ISP_ACTIVE, 6946 &base_vha->dpc_flags); 6947 } 6948 6949 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6950 "FCoE context reset end.\n"); 6951 } 6952 } else if (IS_QLAFX00(ha)) { 6953 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6954 &base_vha->dpc_flags)) { 6955 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6956 "Firmware Reset Recovery\n"); 6957 if (qlafx00_reset_initialize(base_vha)) { 6958 /* Failed. Abort isp later. */ 6959 if (!test_bit(UNLOADING, 6960 &base_vha->dpc_flags)) { 6961 set_bit(ISP_UNRECOVERABLE, 6962 &base_vha->dpc_flags); 6963 ql_dbg(ql_dbg_dpc, base_vha, 6964 0x4021, 6965 "Reset Recovery Failed\n"); 6966 } 6967 } 6968 } 6969 6970 if (test_and_clear_bit(FX00_TARGET_SCAN, 6971 &base_vha->dpc_flags)) { 6972 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6973 "ISPFx00 Target Scan scheduled\n"); 6974 if (qlafx00_rescan_isp(base_vha)) { 6975 if (!test_bit(UNLOADING, 6976 &base_vha->dpc_flags)) 6977 set_bit(ISP_UNRECOVERABLE, 6978 &base_vha->dpc_flags); 6979 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6980 "ISPFx00 Target Scan Failed\n"); 6981 } 6982 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6983 "ISPFx00 Target Scan End\n"); 6984 } 6985 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6986 &base_vha->dpc_flags)) { 6987 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6988 "ISPFx00 Host Info resend scheduled\n"); 6989 qlafx00_fx_disc(base_vha, 6990 &base_vha->hw->mr.fcport, 6991 FXDISC_REG_HOST_INFO); 6992 } 6993 } 6994 6995 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6996 &base_vha->dpc_flags)) { 6997 /* Semantic: 6998 * - NO-OP -- await next ISP-ABORT. Preferred method 6999 * to minimize disruptions that will occur 7000 * when a forced chip-reset occurs. 7001 * - Force -- ISP-ABORT scheduled. 7002 */ 7003 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 7004 } 7005 7006 if (test_and_clear_bit 7007 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 7008 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 7009 bool do_reset = true; 7010 7011 switch (base_vha->qlini_mode) { 7012 case QLA2XXX_INI_MODE_ENABLED: 7013 break; 7014 case QLA2XXX_INI_MODE_DISABLED: 7015 if (!qla_tgt_mode_enabled(base_vha) && 7016 !ha->flags.fw_started) 7017 do_reset = false; 7018 break; 7019 case QLA2XXX_INI_MODE_DUAL: 7020 if (!qla_dual_mode_enabled(base_vha) && 7021 !ha->flags.fw_started) 7022 do_reset = false; 7023 break; 7024 default: 7025 break; 7026 } 7027 7028 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 7029 &base_vha->dpc_flags))) { 7030 base_vha->flags.online = 1; 7031 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 7032 "ISP abort scheduled.\n"); 7033 if (ha->isp_ops->abort_isp(base_vha)) { 7034 /* failed. retry later */ 7035 set_bit(ISP_ABORT_NEEDED, 7036 &base_vha->dpc_flags); 7037 } 7038 clear_bit(ABORT_ISP_ACTIVE, 7039 &base_vha->dpc_flags); 7040 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 7041 "ISP abort end.\n"); 7042 } 7043 } 7044 7045 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 7046 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 7047 qla24xx_process_purex_list 7048 (&base_vha->purex_list); 7049 clear_bit(PROCESS_PUREX_IOCB, 7050 &base_vha->dpc_flags); 7051 } 7052 } 7053 7054 if (IS_QLAFX00(ha)) 7055 goto loop_resync_check; 7056 7057 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 7058 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 7059 "Quiescence mode scheduled.\n"); 7060 if (IS_P3P_TYPE(ha)) { 7061 if (IS_QLA82XX(ha)) 7062 qla82xx_device_state_handler(base_vha); 7063 if (IS_QLA8044(ha)) 7064 qla8044_device_state_handler(base_vha); 7065 clear_bit(ISP_QUIESCE_NEEDED, 7066 &base_vha->dpc_flags); 7067 if (!ha->flags.quiesce_owner) { 7068 qla2x00_perform_loop_resync(base_vha); 7069 if (IS_QLA82XX(ha)) { 7070 qla82xx_idc_lock(ha); 7071 qla82xx_clear_qsnt_ready( 7072 base_vha); 7073 qla82xx_idc_unlock(ha); 7074 } else if (IS_QLA8044(ha)) { 7075 qla8044_idc_lock(ha); 7076 qla8044_clear_qsnt_ready( 7077 base_vha); 7078 qla8044_idc_unlock(ha); 7079 } 7080 } 7081 } else { 7082 clear_bit(ISP_QUIESCE_NEEDED, 7083 &base_vha->dpc_flags); 7084 qla2x00_quiesce_io(base_vha); 7085 } 7086 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7087 "Quiescence mode end.\n"); 7088 } 7089 7090 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7091 &base_vha->dpc_flags) && 7092 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7093 7094 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7095 "Reset marker scheduled.\n"); 7096 qla2x00_rst_aen(base_vha); 7097 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7098 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7099 "Reset marker end.\n"); 7100 } 7101 7102 /* Retry each device up to login retry count */ 7103 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7104 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7105 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7106 7107 if (!base_vha->relogin_jif || 7108 time_after_eq(jiffies, base_vha->relogin_jif)) { 7109 base_vha->relogin_jif = jiffies + HZ; 7110 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7111 7112 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7113 "Relogin scheduled.\n"); 7114 qla24xx_post_relogin_work(base_vha); 7115 } 7116 } 7117 loop_resync_check: 7118 if (!qla2x00_reset_active(base_vha) && 7119 test_and_clear_bit(LOOP_RESYNC_NEEDED, 7120 &base_vha->dpc_flags)) { 7121 /* 7122 * Allow abort_isp to complete before moving on to scanning. 7123 */ 7124 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7125 "Loop resync scheduled.\n"); 7126 7127 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7128 &base_vha->dpc_flags))) { 7129 7130 qla2x00_loop_resync(base_vha); 7131 7132 clear_bit(LOOP_RESYNC_ACTIVE, 7133 &base_vha->dpc_flags); 7134 } 7135 7136 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7137 "Loop resync end.\n"); 7138 } 7139 7140 if (IS_QLAFX00(ha)) 7141 goto intr_on_check; 7142 7143 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7144 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7145 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7146 qla2xxx_flash_npiv_conf(base_vha); 7147 } 7148 7149 intr_on_check: 7150 if (!ha->interrupts_on) 7151 ha->isp_ops->enable_intrs(ha); 7152 7153 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7154 &base_vha->dpc_flags)) { 7155 if (ha->beacon_blink_led == 1) 7156 ha->isp_ops->beacon_blink(base_vha); 7157 } 7158 7159 /* qpair online check */ 7160 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7161 &base_vha->dpc_flags)) { 7162 if (ha->flags.eeh_busy || 7163 ha->flags.pci_channel_io_perm_failure) 7164 online = 0; 7165 else 7166 online = 1; 7167 7168 mutex_lock(&ha->mq_lock); 7169 list_for_each_entry(qpair, &base_vha->qp_list, 7170 qp_list_elem) 7171 qpair->online = online; 7172 mutex_unlock(&ha->mq_lock); 7173 } 7174 7175 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7176 &base_vha->dpc_flags)) { 7177 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7178 7179 if (threshold > ha->orig_fw_xcb_count) 7180 threshold = ha->orig_fw_xcb_count; 7181 7182 ql_log(ql_log_info, base_vha, 0xffffff, 7183 "SET ZIO Activity exchange threshold to %d.\n", 7184 threshold); 7185 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7186 ql_log(ql_log_info, base_vha, 0xffffff, 7187 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7188 threshold); 7189 } 7190 } 7191 7192 if (!IS_QLAFX00(ha)) 7193 qla2x00_do_dpc_all_vps(base_vha); 7194 7195 if (test_and_clear_bit(N2N_LINK_RESET, 7196 &base_vha->dpc_flags)) { 7197 qla2x00_lip_reset(base_vha); 7198 } 7199 7200 ha->dpc_active = 0; 7201 end_loop: 7202 set_current_state(TASK_INTERRUPTIBLE); 7203 } /* End of while(1) */ 7204 __set_current_state(TASK_RUNNING); 7205 7206 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7207 "DPC handler exiting.\n"); 7208 7209 /* 7210 * Make sure that nobody tries to wake us up again. 7211 */ 7212 ha->dpc_active = 0; 7213 7214 /* Cleanup any residual CTX SRBs. */ 7215 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7216 7217 return 0; 7218 } 7219 7220 void 7221 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7222 { 7223 struct qla_hw_data *ha = vha->hw; 7224 struct task_struct *t = ha->dpc_thread; 7225 7226 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7227 wake_up_process(t); 7228 } 7229 7230 /* 7231 * qla2x00_rst_aen 7232 * Processes asynchronous reset. 7233 * 7234 * Input: 7235 * ha = adapter block pointer. 7236 */ 7237 static void 7238 qla2x00_rst_aen(scsi_qla_host_t *vha) 7239 { 7240 if (vha->flags.online && !vha->flags.reset_active && 7241 !atomic_read(&vha->loop_down_timer) && 7242 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7243 do { 7244 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7245 7246 /* 7247 * Issue marker command only when we are going to start 7248 * the I/O. 7249 */ 7250 vha->marker_needed = 1; 7251 } while (!atomic_read(&vha->loop_down_timer) && 7252 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7253 } 7254 } 7255 7256 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7257 { 7258 struct qla_hw_data *ha = vha->hw; 7259 u32 cmpl_cnt; 7260 u16 i; 7261 bool do_heartbeat = false; 7262 7263 /* 7264 * Allow do_heartbeat only if we don’t have any active interrupts, 7265 * but there are still IOs outstanding with firmware. 7266 */ 7267 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7268 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7269 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7270 do_heartbeat = true; 7271 goto skip; 7272 } 7273 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7274 7275 for (i = 0; i < ha->max_qpairs; i++) { 7276 if (ha->queue_pair_map[i]) { 7277 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7278 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7279 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7280 do_heartbeat = true; 7281 break; 7282 } 7283 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7284 } 7285 } 7286 7287 skip: 7288 return do_heartbeat; 7289 } 7290 7291 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started) 7292 { 7293 struct qla_hw_data *ha = vha->hw; 7294 7295 if (vha->vp_idx) 7296 return; 7297 7298 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7299 return; 7300 7301 /* 7302 * dpc thread cannot run if heartbeat is running at the same time. 7303 * We also do not want to starve heartbeat task. Therefore, do 7304 * heartbeat task at least once every 5 seconds. 7305 */ 7306 if (dpc_started && 7307 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ)) 7308 return; 7309 7310 if (qla_do_heartbeat(vha)) { 7311 ha->last_heartbeat_run_jiffies = jiffies; 7312 queue_work(ha->wq, &ha->heartbeat_work); 7313 } 7314 } 7315 7316 static void qla_wind_down_chip(scsi_qla_host_t *vha) 7317 { 7318 struct qla_hw_data *ha = vha->hw; 7319 7320 if (!ha->flags.eeh_busy) 7321 return; 7322 if (ha->pci_error_state) 7323 /* system is trying to recover */ 7324 return; 7325 7326 /* 7327 * Current system is not handling PCIE error. At this point, this is 7328 * best effort to wind down the adapter. 7329 */ 7330 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) && 7331 !ha->flags.eeh_flush) { 7332 ql_log(ql_log_info, vha, 0x9009, 7333 "PCI Error detected, attempting to reset hardware.\n"); 7334 7335 ha->isp_ops->reset_chip(vha); 7336 ha->isp_ops->disable_intrs(ha); 7337 7338 ha->flags.eeh_flush = EEH_FLUSH_RDY; 7339 ha->eeh_jif = jiffies; 7340 7341 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY && 7342 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) { 7343 pci_clear_master(ha->pdev); 7344 7345 /* flush all command */ 7346 qla2x00_abort_isp_cleanup(vha); 7347 ha->flags.eeh_flush = EEH_FLUSH_DONE; 7348 7349 ql_log(ql_log_info, vha, 0x900a, 7350 "PCI Error handling complete, all IOs aborted.\n"); 7351 } 7352 } 7353 7354 /************************************************************************** 7355 * qla2x00_timer 7356 * 7357 * Description: 7358 * One second timer 7359 * 7360 * Context: Interrupt 7361 ***************************************************************************/ 7362 void 7363 qla2x00_timer(struct timer_list *t) 7364 { 7365 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7366 unsigned long cpu_flags = 0; 7367 int start_dpc = 0; 7368 int index; 7369 srb_t *sp; 7370 uint16_t w; 7371 struct qla_hw_data *ha = vha->hw; 7372 struct req_que *req; 7373 unsigned long flags; 7374 fc_port_t *fcport = NULL; 7375 7376 if (ha->flags.eeh_busy) { 7377 qla_wind_down_chip(vha); 7378 7379 ql_dbg(ql_dbg_timer, vha, 0x6000, 7380 "EEH = %d, restarting timer.\n", 7381 ha->flags.eeh_busy); 7382 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7383 return; 7384 } 7385 7386 /* 7387 * Hardware read to raise pending EEH errors during mailbox waits. If 7388 * the read returns -1 then disable the board. 7389 */ 7390 if (!pci_channel_offline(ha->pdev)) { 7391 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7392 qla2x00_check_reg16_for_disconnect(vha, w); 7393 } 7394 7395 /* Make sure qla82xx_watchdog is run only for physical port */ 7396 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7397 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7398 start_dpc++; 7399 if (IS_QLA82XX(ha)) 7400 qla82xx_watchdog(vha); 7401 else if (IS_QLA8044(ha)) 7402 qla8044_watchdog(vha); 7403 } 7404 7405 if (!vha->vp_idx && IS_QLAFX00(ha)) 7406 qlafx00_timer_routine(vha); 7407 7408 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7409 vha->link_down_time++; 7410 7411 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7412 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7413 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7414 fcport->tgt_link_down_time++; 7415 } 7416 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7417 7418 /* Loop down handler. */ 7419 if (atomic_read(&vha->loop_down_timer) > 0 && 7420 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7421 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7422 && vha->flags.online) { 7423 7424 if (atomic_read(&vha->loop_down_timer) == 7425 vha->loop_down_abort_time) { 7426 7427 ql_log(ql_log_info, vha, 0x6008, 7428 "Loop down - aborting the queues before time expires.\n"); 7429 7430 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7431 atomic_set(&vha->loop_state, LOOP_DEAD); 7432 7433 /* 7434 * Schedule an ISP abort to return any FCP2-device 7435 * commands. 7436 */ 7437 /* NPIV - scan physical port only */ 7438 if (!vha->vp_idx) { 7439 spin_lock_irqsave(&ha->hardware_lock, 7440 cpu_flags); 7441 req = ha->req_q_map[0]; 7442 for (index = 1; 7443 index < req->num_outstanding_cmds; 7444 index++) { 7445 fc_port_t *sfcp; 7446 7447 sp = req->outstanding_cmds[index]; 7448 if (!sp) 7449 continue; 7450 if (sp->cmd_type != TYPE_SRB) 7451 continue; 7452 if (sp->type != SRB_SCSI_CMD) 7453 continue; 7454 sfcp = sp->fcport; 7455 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7456 continue; 7457 7458 if (IS_QLA82XX(ha)) 7459 set_bit(FCOE_CTX_RESET_NEEDED, 7460 &vha->dpc_flags); 7461 else 7462 set_bit(ISP_ABORT_NEEDED, 7463 &vha->dpc_flags); 7464 break; 7465 } 7466 spin_unlock_irqrestore(&ha->hardware_lock, 7467 cpu_flags); 7468 } 7469 start_dpc++; 7470 } 7471 7472 /* if the loop has been down for 4 minutes, reinit adapter */ 7473 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7474 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { 7475 ql_log(ql_log_warn, vha, 0x6009, 7476 "Loop down - aborting ISP.\n"); 7477 7478 if (IS_QLA82XX(ha)) 7479 set_bit(FCOE_CTX_RESET_NEEDED, 7480 &vha->dpc_flags); 7481 else 7482 set_bit(ISP_ABORT_NEEDED, 7483 &vha->dpc_flags); 7484 } 7485 } 7486 ql_dbg(ql_dbg_timer, vha, 0x600a, 7487 "Loop down - seconds remaining %d.\n", 7488 atomic_read(&vha->loop_down_timer)); 7489 } 7490 /* Check if beacon LED needs to be blinked for physical host only */ 7491 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7492 /* There is no beacon_blink function for ISP82xx */ 7493 if (!IS_P3P_TYPE(ha)) { 7494 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7495 start_dpc++; 7496 } 7497 } 7498 7499 /* check if edif running */ 7500 if (vha->hw->flags.edif_enabled) 7501 qla_edif_timer(vha); 7502 7503 /* Process any deferred work. */ 7504 if (!list_empty(&vha->work_list)) { 7505 unsigned long flags; 7506 bool q = false; 7507 7508 spin_lock_irqsave(&vha->work_lock, flags); 7509 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7510 q = true; 7511 spin_unlock_irqrestore(&vha->work_lock, flags); 7512 if (q) 7513 queue_work(vha->hw->wq, &vha->iocb_work); 7514 } 7515 7516 /* 7517 * FC-NVME 7518 * see if the active AEN count has changed from what was last reported. 7519 */ 7520 index = atomic_read(&ha->nvme_active_aen_cnt); 7521 if (!vha->vp_idx && 7522 (index != ha->nvme_last_rptd_aen) && 7523 ha->zio_mode == QLA_ZIO_MODE_6 && 7524 !ha->flags.host_shutting_down) { 7525 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7526 ql_log(ql_log_info, vha, 0x3002, 7527 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7528 ha->nvme_last_rptd_aen); 7529 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7530 start_dpc++; 7531 } 7532 7533 if (!vha->vp_idx && 7534 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7535 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7536 ql_log(ql_log_info, vha, 0x3002, 7537 "Sched: Set ZIO exchange threshold to %d.\n", 7538 ha->last_zio_threshold); 7539 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7540 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7541 start_dpc++; 7542 } 7543 qla_adjust_buf(vha); 7544 7545 /* borrowing w to signify dpc will run */ 7546 w = 0; 7547 /* Schedule the DPC routine if needed */ 7548 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7549 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7550 start_dpc || 7551 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7552 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7553 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7554 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7555 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7556 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7557 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7558 ql_dbg(ql_dbg_timer, vha, 0x600b, 7559 "isp_abort_needed=%d loop_resync_needed=%d " 7560 "start_dpc=%d reset_marker_needed=%d", 7561 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7562 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7563 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7564 ql_dbg(ql_dbg_timer, vha, 0x600c, 7565 "beacon_blink_needed=%d isp_unrecoverable=%d " 7566 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7567 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7568 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7569 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7570 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7571 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7572 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7573 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7574 qla2xxx_wake_dpc(vha); 7575 w = 1; 7576 } 7577 7578 qla_heart_beat(vha, w); 7579 7580 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7581 } 7582 7583 /* Firmware interface routines. */ 7584 7585 #define FW_ISP21XX 0 7586 #define FW_ISP22XX 1 7587 #define FW_ISP2300 2 7588 #define FW_ISP2322 3 7589 #define FW_ISP24XX 4 7590 #define FW_ISP25XX 5 7591 #define FW_ISP81XX 6 7592 #define FW_ISP82XX 7 7593 #define FW_ISP2031 8 7594 #define FW_ISP8031 9 7595 #define FW_ISP27XX 10 7596 #define FW_ISP28XX 11 7597 7598 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7599 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7600 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7601 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7602 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7603 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7604 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7605 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7606 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7607 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7608 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7609 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7610 7611 7612 static DEFINE_MUTEX(qla_fw_lock); 7613 7614 static struct fw_blob qla_fw_blobs[] = { 7615 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7616 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7617 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7618 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7619 { .name = FW_FILE_ISP24XX, }, 7620 { .name = FW_FILE_ISP25XX, }, 7621 { .name = FW_FILE_ISP81XX, }, 7622 { .name = FW_FILE_ISP82XX, }, 7623 { .name = FW_FILE_ISP2031, }, 7624 { .name = FW_FILE_ISP8031, }, 7625 { .name = FW_FILE_ISP27XX, }, 7626 { .name = FW_FILE_ISP28XX, }, 7627 { .name = NULL, }, 7628 }; 7629 7630 struct fw_blob * 7631 qla2x00_request_firmware(scsi_qla_host_t *vha) 7632 { 7633 struct qla_hw_data *ha = vha->hw; 7634 struct fw_blob *blob; 7635 7636 if (IS_QLA2100(ha)) { 7637 blob = &qla_fw_blobs[FW_ISP21XX]; 7638 } else if (IS_QLA2200(ha)) { 7639 blob = &qla_fw_blobs[FW_ISP22XX]; 7640 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7641 blob = &qla_fw_blobs[FW_ISP2300]; 7642 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7643 blob = &qla_fw_blobs[FW_ISP2322]; 7644 } else if (IS_QLA24XX_TYPE(ha)) { 7645 blob = &qla_fw_blobs[FW_ISP24XX]; 7646 } else if (IS_QLA25XX(ha)) { 7647 blob = &qla_fw_blobs[FW_ISP25XX]; 7648 } else if (IS_QLA81XX(ha)) { 7649 blob = &qla_fw_blobs[FW_ISP81XX]; 7650 } else if (IS_QLA82XX(ha)) { 7651 blob = &qla_fw_blobs[FW_ISP82XX]; 7652 } else if (IS_QLA2031(ha)) { 7653 blob = &qla_fw_blobs[FW_ISP2031]; 7654 } else if (IS_QLA8031(ha)) { 7655 blob = &qla_fw_blobs[FW_ISP8031]; 7656 } else if (IS_QLA27XX(ha)) { 7657 blob = &qla_fw_blobs[FW_ISP27XX]; 7658 } else if (IS_QLA28XX(ha)) { 7659 blob = &qla_fw_blobs[FW_ISP28XX]; 7660 } else { 7661 return NULL; 7662 } 7663 7664 if (!blob->name) 7665 return NULL; 7666 7667 mutex_lock(&qla_fw_lock); 7668 if (blob->fw) 7669 goto out; 7670 7671 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7672 ql_log(ql_log_warn, vha, 0x0063, 7673 "Failed to load firmware image (%s).\n", blob->name); 7674 blob->fw = NULL; 7675 blob = NULL; 7676 } 7677 7678 out: 7679 mutex_unlock(&qla_fw_lock); 7680 return blob; 7681 } 7682 7683 static void 7684 qla2x00_release_firmware(void) 7685 { 7686 struct fw_blob *blob; 7687 7688 mutex_lock(&qla_fw_lock); 7689 for (blob = qla_fw_blobs; blob->name; blob++) 7690 release_firmware(blob->fw); 7691 mutex_unlock(&qla_fw_lock); 7692 } 7693 7694 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7695 { 7696 struct qla_hw_data *ha = vha->hw; 7697 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7698 struct qla_qpair *qpair = NULL; 7699 struct scsi_qla_host *vp, *tvp; 7700 fc_port_t *fcport; 7701 int i; 7702 unsigned long flags; 7703 7704 ql_dbg(ql_dbg_aer, vha, 0x9000, 7705 "%s\n", __func__); 7706 ha->chip_reset++; 7707 7708 ha->base_qpair->chip_reset = ha->chip_reset; 7709 for (i = 0; i < ha->max_qpairs; i++) { 7710 if (ha->queue_pair_map[i]) 7711 ha->queue_pair_map[i]->chip_reset = 7712 ha->base_qpair->chip_reset; 7713 } 7714 7715 /* 7716 * purge mailbox might take a while. Slot Reset/chip reset 7717 * will take care of the purge 7718 */ 7719 7720 mutex_lock(&ha->mq_lock); 7721 ha->base_qpair->online = 0; 7722 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7723 qpair->online = 0; 7724 wmb(); 7725 mutex_unlock(&ha->mq_lock); 7726 7727 qla2x00_mark_all_devices_lost(vha); 7728 7729 spin_lock_irqsave(&ha->vport_slock, flags); 7730 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7731 atomic_inc(&vp->vref_count); 7732 spin_unlock_irqrestore(&ha->vport_slock, flags); 7733 qla2x00_mark_all_devices_lost(vp); 7734 spin_lock_irqsave(&ha->vport_slock, flags); 7735 atomic_dec(&vp->vref_count); 7736 } 7737 spin_unlock_irqrestore(&ha->vport_slock, flags); 7738 7739 /* Clear all async request states across all VPs. */ 7740 list_for_each_entry(fcport, &vha->vp_fcports, list) 7741 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7742 7743 spin_lock_irqsave(&ha->vport_slock, flags); 7744 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7745 atomic_inc(&vp->vref_count); 7746 spin_unlock_irqrestore(&ha->vport_slock, flags); 7747 list_for_each_entry(fcport, &vp->vp_fcports, list) 7748 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7749 spin_lock_irqsave(&ha->vport_slock, flags); 7750 atomic_dec(&vp->vref_count); 7751 } 7752 spin_unlock_irqrestore(&ha->vport_slock, flags); 7753 } 7754 7755 7756 static pci_ers_result_t 7757 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7758 { 7759 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7760 struct qla_hw_data *ha = vha->hw; 7761 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7762 7763 ql_log(ql_log_warn, vha, 0x9000, 7764 "PCI error detected, state %x.\n", state); 7765 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7766 7767 if (!atomic_read(&pdev->enable_cnt)) { 7768 ql_log(ql_log_info, vha, 0xffff, 7769 "PCI device is disabled,state %x\n", state); 7770 ret = PCI_ERS_RESULT_NEED_RESET; 7771 goto out; 7772 } 7773 7774 switch (state) { 7775 case pci_channel_io_normal: 7776 qla_pci_set_eeh_busy(vha); 7777 if (ql2xmqsupport || ql2xnvmeenable) { 7778 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7779 qla2xxx_wake_dpc(vha); 7780 } 7781 ret = PCI_ERS_RESULT_CAN_RECOVER; 7782 break; 7783 case pci_channel_io_frozen: 7784 qla_pci_set_eeh_busy(vha); 7785 ret = PCI_ERS_RESULT_NEED_RESET; 7786 break; 7787 case pci_channel_io_perm_failure: 7788 ha->flags.pci_channel_io_perm_failure = 1; 7789 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7790 if (ql2xmqsupport || ql2xnvmeenable) { 7791 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7792 qla2xxx_wake_dpc(vha); 7793 } 7794 ret = PCI_ERS_RESULT_DISCONNECT; 7795 } 7796 out: 7797 ql_dbg(ql_dbg_aer, vha, 0x600d, 7798 "PCI error detected returning [%x].\n", ret); 7799 return ret; 7800 } 7801 7802 static pci_ers_result_t 7803 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7804 { 7805 int risc_paused = 0; 7806 uint32_t stat; 7807 unsigned long flags; 7808 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7809 struct qla_hw_data *ha = base_vha->hw; 7810 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7811 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7812 7813 ql_log(ql_log_warn, base_vha, 0x9000, 7814 "mmio enabled\n"); 7815 7816 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7817 7818 if (IS_QLA82XX(ha)) 7819 return PCI_ERS_RESULT_RECOVERED; 7820 7821 if (qla2x00_isp_reg_stat(ha)) { 7822 ql_log(ql_log_info, base_vha, 0x803f, 7823 "During mmio enabled, PCI/Register disconnect still detected.\n"); 7824 goto out; 7825 } 7826 7827 spin_lock_irqsave(&ha->hardware_lock, flags); 7828 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7829 stat = rd_reg_word(®->hccr); 7830 if (stat & HCCR_RISC_PAUSE) 7831 risc_paused = 1; 7832 } else if (IS_QLA23XX(ha)) { 7833 stat = rd_reg_dword(®->u.isp2300.host_status); 7834 if (stat & HSR_RISC_PAUSED) 7835 risc_paused = 1; 7836 } else if (IS_FWI2_CAPABLE(ha)) { 7837 stat = rd_reg_dword(®24->host_status); 7838 if (stat & HSRX_RISC_PAUSED) 7839 risc_paused = 1; 7840 } 7841 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7842 7843 if (risc_paused) { 7844 ql_log(ql_log_info, base_vha, 0x9003, 7845 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7846 qla2xxx_dump_fw(base_vha); 7847 } 7848 out: 7849 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7850 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7851 "mmio enabled returning.\n"); 7852 return PCI_ERS_RESULT_NEED_RESET; 7853 } 7854 7855 static pci_ers_result_t 7856 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7857 { 7858 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7859 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7860 struct qla_hw_data *ha = base_vha->hw; 7861 int rc; 7862 struct qla_qpair *qpair = NULL; 7863 7864 ql_log(ql_log_warn, base_vha, 0x9004, 7865 "Slot Reset.\n"); 7866 7867 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7868 /* Workaround: qla2xxx driver which access hardware earlier 7869 * needs error state to be pci_channel_io_online. 7870 * Otherwise mailbox command timesout. 7871 */ 7872 pdev->error_state = pci_channel_io_normal; 7873 7874 pci_restore_state(pdev); 7875 7876 /* pci_restore_state() clears the saved_state flag of the device 7877 * save restored state which resets saved_state flag 7878 */ 7879 pci_save_state(pdev); 7880 7881 if (ha->mem_only) 7882 rc = pci_enable_device_mem(pdev); 7883 else 7884 rc = pci_enable_device(pdev); 7885 7886 if (rc) { 7887 ql_log(ql_log_warn, base_vha, 0x9005, 7888 "Can't re-enable PCI device after reset.\n"); 7889 goto exit_slot_reset; 7890 } 7891 7892 7893 if (ha->isp_ops->pci_config(base_vha)) 7894 goto exit_slot_reset; 7895 7896 mutex_lock(&ha->mq_lock); 7897 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7898 qpair->online = 1; 7899 mutex_unlock(&ha->mq_lock); 7900 7901 ha->flags.eeh_busy = 0; 7902 base_vha->flags.online = 1; 7903 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7904 ha->isp_ops->abort_isp(base_vha); 7905 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7906 7907 if (qla2x00_isp_reg_stat(ha)) { 7908 ha->flags.eeh_busy = 1; 7909 qla_pci_error_cleanup(base_vha); 7910 ql_log(ql_log_warn, base_vha, 0x9005, 7911 "Device unable to recover from PCI error.\n"); 7912 } else { 7913 ret = PCI_ERS_RESULT_RECOVERED; 7914 } 7915 7916 exit_slot_reset: 7917 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7918 "Slot Reset returning %x.\n", ret); 7919 7920 return ret; 7921 } 7922 7923 static void 7924 qla2xxx_pci_resume(struct pci_dev *pdev) 7925 { 7926 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7927 struct qla_hw_data *ha = base_vha->hw; 7928 int ret; 7929 7930 ql_log(ql_log_warn, base_vha, 0x900f, 7931 "Pci Resume.\n"); 7932 7933 7934 ret = qla2x00_wait_for_hba_online(base_vha); 7935 if (ret != QLA_SUCCESS) { 7936 ql_log(ql_log_fatal, base_vha, 0x9002, 7937 "The device failed to resume I/O from slot/link_reset.\n"); 7938 } 7939 ha->pci_error_state = QLA_PCI_RESUME; 7940 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7941 "Pci Resume returning.\n"); 7942 } 7943 7944 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7945 { 7946 struct qla_hw_data *ha = vha->hw; 7947 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7948 bool do_cleanup = false; 7949 unsigned long flags; 7950 7951 if (ha->flags.eeh_busy) 7952 return; 7953 7954 spin_lock_irqsave(&base_vha->work_lock, flags); 7955 if (!ha->flags.eeh_busy) { 7956 ha->eeh_jif = jiffies; 7957 ha->flags.eeh_flush = 0; 7958 7959 ha->flags.eeh_busy = 1; 7960 do_cleanup = true; 7961 } 7962 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7963 7964 if (do_cleanup) 7965 qla_pci_error_cleanup(base_vha); 7966 } 7967 7968 /* 7969 * this routine will schedule a task to pause IO from interrupt context 7970 * if caller sees a PCIE error event (register read = 0xf's) 7971 */ 7972 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7973 { 7974 struct qla_hw_data *ha = vha->hw; 7975 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7976 7977 if (ha->flags.eeh_busy) 7978 return; 7979 7980 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7981 qla2xxx_wake_dpc(base_vha); 7982 } 7983 7984 static void 7985 qla_pci_reset_prepare(struct pci_dev *pdev) 7986 { 7987 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7988 struct qla_hw_data *ha = base_vha->hw; 7989 struct qla_qpair *qpair; 7990 7991 ql_log(ql_log_warn, base_vha, 0xffff, 7992 "%s.\n", __func__); 7993 7994 /* 7995 * PCI FLR/function reset is about to reset the 7996 * slot. Stop the chip to stop all DMA access. 7997 * It is assumed that pci_reset_done will be called 7998 * after FLR to resume Chip operation. 7999 */ 8000 ha->flags.eeh_busy = 1; 8001 mutex_lock(&ha->mq_lock); 8002 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8003 qpair->online = 0; 8004 mutex_unlock(&ha->mq_lock); 8005 8006 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8007 qla2x00_abort_isp_cleanup(base_vha); 8008 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 8009 } 8010 8011 static void 8012 qla_pci_reset_done(struct pci_dev *pdev) 8013 { 8014 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8015 struct qla_hw_data *ha = base_vha->hw; 8016 struct qla_qpair *qpair; 8017 8018 ql_log(ql_log_warn, base_vha, 0xffff, 8019 "%s.\n", __func__); 8020 8021 /* 8022 * FLR just completed by PCI layer. Resume adapter 8023 */ 8024 ha->flags.eeh_busy = 0; 8025 mutex_lock(&ha->mq_lock); 8026 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8027 qpair->online = 1; 8028 mutex_unlock(&ha->mq_lock); 8029 8030 base_vha->flags.online = 1; 8031 ha->isp_ops->abort_isp(base_vha); 8032 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8033 } 8034 8035 static void qla2xxx_map_queues(struct Scsi_Host *shost) 8036 { 8037 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 8038 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 8039 8040 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 8041 blk_mq_map_queues(qmap); 8042 else 8043 blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 8044 } 8045 8046 struct scsi_host_template qla2xxx_driver_template = { 8047 .module = THIS_MODULE, 8048 .name = QLA2XXX_DRIVER_NAME, 8049 .queuecommand = qla2xxx_queuecommand, 8050 8051 .eh_timed_out = fc_eh_timed_out, 8052 .eh_abort_handler = qla2xxx_eh_abort, 8053 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 8054 .eh_device_reset_handler = qla2xxx_eh_device_reset, 8055 .eh_target_reset_handler = qla2xxx_eh_target_reset, 8056 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 8057 .eh_host_reset_handler = qla2xxx_eh_host_reset, 8058 8059 .slave_configure = qla2xxx_slave_configure, 8060 8061 .slave_alloc = qla2xxx_slave_alloc, 8062 .slave_destroy = qla2xxx_slave_destroy, 8063 .scan_finished = qla2xxx_scan_finished, 8064 .scan_start = qla2xxx_scan_start, 8065 .change_queue_depth = scsi_change_queue_depth, 8066 .map_queues = qla2xxx_map_queues, 8067 .this_id = -1, 8068 .cmd_per_lun = 3, 8069 .sg_tablesize = SG_ALL, 8070 8071 .max_sectors = 0xFFFF, 8072 .shost_groups = qla2x00_host_groups, 8073 8074 .supported_mode = MODE_INITIATOR, 8075 .track_queue_depth = 1, 8076 .cmd_size = sizeof(srb_t), 8077 }; 8078 8079 static const struct pci_error_handlers qla2xxx_err_handler = { 8080 .error_detected = qla2xxx_pci_error_detected, 8081 .mmio_enabled = qla2xxx_pci_mmio_enabled, 8082 .slot_reset = qla2xxx_pci_slot_reset, 8083 .resume = qla2xxx_pci_resume, 8084 .reset_prepare = qla_pci_reset_prepare, 8085 .reset_done = qla_pci_reset_done, 8086 }; 8087 8088 static struct pci_device_id qla2xxx_pci_tbl[] = { 8089 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 8090 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 8091 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 8092 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 8093 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 8094 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 8095 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 8096 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 8097 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 8098 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 8099 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 8100 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 8101 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 8102 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 8103 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 8104 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 8105 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 8106 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 8107 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 8108 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 8109 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 8110 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 8111 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 8112 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 8113 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 8114 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 8115 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 8116 { 0 }, 8117 }; 8118 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 8119 8120 static struct pci_driver qla2xxx_pci_driver = { 8121 .name = QLA2XXX_DRIVER_NAME, 8122 .driver = { 8123 .owner = THIS_MODULE, 8124 }, 8125 .id_table = qla2xxx_pci_tbl, 8126 .probe = qla2x00_probe_one, 8127 .remove = qla2x00_remove_one, 8128 .shutdown = qla2x00_shutdown, 8129 .err_handler = &qla2xxx_err_handler, 8130 }; 8131 8132 static const struct file_operations apidev_fops = { 8133 .owner = THIS_MODULE, 8134 .llseek = noop_llseek, 8135 }; 8136 8137 /** 8138 * qla2x00_module_init - Module initialization. 8139 **/ 8140 static int __init 8141 qla2x00_module_init(void) 8142 { 8143 int ret = 0; 8144 8145 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8146 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8147 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8148 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8149 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8150 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8151 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8152 BUILD_BUG_ON(sizeof(request_t) != 64); 8153 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8154 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8155 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8156 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8157 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8158 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8159 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8160 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8161 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8162 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8163 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8164 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8165 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8166 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8167 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8168 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8169 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8170 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8171 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8172 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8173 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8174 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8175 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8176 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8177 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8178 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8179 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8180 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8181 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8182 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8183 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8184 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8185 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8186 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8187 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8188 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8189 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8190 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8191 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8192 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8193 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8194 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8195 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8196 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8197 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8198 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8199 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8200 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8201 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8202 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8203 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8204 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8205 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8206 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8207 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8208 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8209 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8210 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8211 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8212 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8213 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8214 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8215 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8216 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8217 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8218 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8219 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8220 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8221 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8222 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8223 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8224 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8225 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8226 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8227 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8228 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8229 8230 qla_trace_init(); 8231 8232 /* Allocate cache for SRBs. */ 8233 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8234 SLAB_HWCACHE_ALIGN, NULL); 8235 if (srb_cachep == NULL) { 8236 ql_log(ql_log_fatal, NULL, 0x0001, 8237 "Unable to allocate SRB cache...Failing load!.\n"); 8238 return -ENOMEM; 8239 } 8240 8241 /* Initialize target kmem_cache and mem_pools */ 8242 ret = qlt_init(); 8243 if (ret < 0) { 8244 goto destroy_cache; 8245 } else if (ret > 0) { 8246 /* 8247 * If initiator mode is explictly disabled by qlt_init(), 8248 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8249 * performing scsi_scan_target() during LOOP UP event. 8250 */ 8251 qla2xxx_transport_functions.disable_target_scan = 1; 8252 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8253 } 8254 8255 /* Derive version string. */ 8256 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8257 if (ql2xextended_error_logging) 8258 strcat(qla2x00_version_str, "-debug"); 8259 if (ql2xextended_error_logging == 1) 8260 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8261 8262 qla2xxx_transport_template = 8263 fc_attach_transport(&qla2xxx_transport_functions); 8264 if (!qla2xxx_transport_template) { 8265 ql_log(ql_log_fatal, NULL, 0x0002, 8266 "fc_attach_transport failed...Failing load!.\n"); 8267 ret = -ENODEV; 8268 goto qlt_exit; 8269 } 8270 8271 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8272 if (apidev_major < 0) { 8273 ql_log(ql_log_fatal, NULL, 0x0003, 8274 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8275 } 8276 8277 qla2xxx_transport_vport_template = 8278 fc_attach_transport(&qla2xxx_transport_vport_functions); 8279 if (!qla2xxx_transport_vport_template) { 8280 ql_log(ql_log_fatal, NULL, 0x0004, 8281 "fc_attach_transport vport failed...Failing load!.\n"); 8282 ret = -ENODEV; 8283 goto unreg_chrdev; 8284 } 8285 ql_log(ql_log_info, NULL, 0x0005, 8286 "QLogic Fibre Channel HBA Driver: %s.\n", 8287 qla2x00_version_str); 8288 ret = pci_register_driver(&qla2xxx_pci_driver); 8289 if (ret) { 8290 ql_log(ql_log_fatal, NULL, 0x0006, 8291 "pci_register_driver failed...ret=%d Failing load!.\n", 8292 ret); 8293 goto release_vport_transport; 8294 } 8295 return ret; 8296 8297 release_vport_transport: 8298 fc_release_transport(qla2xxx_transport_vport_template); 8299 8300 unreg_chrdev: 8301 if (apidev_major >= 0) 8302 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8303 fc_release_transport(qla2xxx_transport_template); 8304 8305 qlt_exit: 8306 qlt_exit(); 8307 8308 destroy_cache: 8309 kmem_cache_destroy(srb_cachep); 8310 8311 qla_trace_uninit(); 8312 return ret; 8313 } 8314 8315 /** 8316 * qla2x00_module_exit - Module cleanup. 8317 **/ 8318 static void __exit 8319 qla2x00_module_exit(void) 8320 { 8321 pci_unregister_driver(&qla2xxx_pci_driver); 8322 qla2x00_release_firmware(); 8323 kmem_cache_destroy(ctx_cachep); 8324 fc_release_transport(qla2xxx_transport_vport_template); 8325 if (apidev_major >= 0) 8326 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8327 fc_release_transport(qla2xxx_transport_template); 8328 qlt_exit(); 8329 kmem_cache_destroy(srb_cachep); 8330 qla_trace_uninit(); 8331 } 8332 8333 module_init(qla2x00_module_init); 8334 module_exit(qla2x00_module_exit); 8335 8336 MODULE_AUTHOR("QLogic Corporation"); 8337 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8338 MODULE_LICENSE("GPL"); 8339 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8340 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8341 MODULE_FIRMWARE(FW_FILE_ISP2300); 8342 MODULE_FIRMWARE(FW_FILE_ISP2322); 8343 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8344 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8345