1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <linux/refcount.h> 18 19 #include <scsi/scsi_tcq.h> 20 #include <scsi/scsicam.h> 21 #include <scsi/scsi_transport.h> 22 #include <scsi/scsi_transport_fc.h> 23 24 #include "qla_target.h" 25 26 /* 27 * Driver version 28 */ 29 char qla2x00_version_str[40]; 30 31 static int apidev_major; 32 33 /* 34 * SRB allocation cache 35 */ 36 struct kmem_cache *srb_cachep; 37 38 /* 39 * CT6 CTX allocation cache 40 */ 41 static struct kmem_cache *ctx_cachep; 42 /* 43 * error level for logging 44 */ 45 uint ql_errlev = 0x8001; 46 47 static int ql2xenableclass2; 48 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 49 MODULE_PARM_DESC(ql2xenableclass2, 50 "Specify if Class 2 operations are supported from the very " 51 "beginning. Default is 0 - class 2 not supported."); 52 53 54 int ql2xlogintimeout = 20; 55 module_param(ql2xlogintimeout, int, S_IRUGO); 56 MODULE_PARM_DESC(ql2xlogintimeout, 57 "Login timeout value in seconds."); 58 59 int qlport_down_retry; 60 module_param(qlport_down_retry, int, S_IRUGO); 61 MODULE_PARM_DESC(qlport_down_retry, 62 "Maximum number of command retries to a port that returns " 63 "a PORT-DOWN status."); 64 65 int ql2xplogiabsentdevice; 66 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 67 MODULE_PARM_DESC(ql2xplogiabsentdevice, 68 "Option to enable PLOGI to devices that are not present after " 69 "a Fabric scan. This is needed for several broken switches. " 70 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 71 72 int ql2xloginretrycount; 73 module_param(ql2xloginretrycount, int, S_IRUGO); 74 MODULE_PARM_DESC(ql2xloginretrycount, 75 "Specify an alternate value for the NVRAM login retry count."); 76 77 int ql2xallocfwdump = 1; 78 module_param(ql2xallocfwdump, int, S_IRUGO); 79 MODULE_PARM_DESC(ql2xallocfwdump, 80 "Option to enable allocation of memory for a firmware dump " 81 "during HBA initialization. Memory allocation requirements " 82 "vary by ISP type. Default is 1 - allocate memory."); 83 84 int ql2xextended_error_logging; 85 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 86 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 87 MODULE_PARM_DESC(ql2xextended_error_logging, 88 "Option to enable extended error logging,\n" 89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 100 "\t\t0x1e400000 - Preferred value for capturing essential " 101 "debug information (equivalent to old " 102 "ql2xextended_error_logging=1).\n" 103 "\t\tDo LOGICAL OR of the value to enable more than one level"); 104 105 int ql2xshiftctondsd = 6; 106 module_param(ql2xshiftctondsd, int, S_IRUGO); 107 MODULE_PARM_DESC(ql2xshiftctondsd, 108 "Set to control shifting of command type processing " 109 "based on total number of SG elements."); 110 111 int ql2xfdmienable = 1; 112 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 113 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 114 MODULE_PARM_DESC(ql2xfdmienable, 115 "Enables FDMI registrations. " 116 "0 - no FDMI registrations. " 117 "1 - provide FDMI registrations (default)."); 118 119 #define MAX_Q_DEPTH 64 120 static int ql2xmaxqdepth = MAX_Q_DEPTH; 121 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 122 MODULE_PARM_DESC(ql2xmaxqdepth, 123 "Maximum queue depth to set for each LUN. " 124 "Default is 64."); 125 126 int ql2xenabledif = 2; 127 module_param(ql2xenabledif, int, S_IRUGO); 128 MODULE_PARM_DESC(ql2xenabledif, 129 " Enable T10-CRC-DIF:\n" 130 " Default is 2.\n" 131 " 0 -- No DIF Support\n" 132 " 1 -- Enable DIF for all types\n" 133 " 2 -- Enable DIF for all types, except Type 0.\n"); 134 135 #if (IS_ENABLED(CONFIG_NVME_FC)) 136 int ql2xnvmeenable = 1; 137 #else 138 int ql2xnvmeenable; 139 #endif 140 module_param(ql2xnvmeenable, int, 0644); 141 MODULE_PARM_DESC(ql2xnvmeenable, 142 "Enables NVME support. " 143 "0 - no NVMe. Default is Y"); 144 145 int ql2xenablehba_err_chk = 2; 146 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 147 MODULE_PARM_DESC(ql2xenablehba_err_chk, 148 " Enable T10-CRC-DIF Error isolation by HBA:\n" 149 " Default is 2.\n" 150 " 0 -- Error isolation disabled\n" 151 " 1 -- Error isolation enabled only for DIX Type 0\n" 152 " 2 -- Error isolation enabled for all Types\n"); 153 154 int ql2xiidmaenable = 1; 155 module_param(ql2xiidmaenable, int, S_IRUGO); 156 MODULE_PARM_DESC(ql2xiidmaenable, 157 "Enables iIDMA settings " 158 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 159 160 int ql2xmqsupport = 1; 161 module_param(ql2xmqsupport, int, S_IRUGO); 162 MODULE_PARM_DESC(ql2xmqsupport, 163 "Enable on demand multiple queue pairs support " 164 "Default is 1 for supported. " 165 "Set it to 0 to turn off mq qpair support."); 166 167 int ql2xfwloadbin; 168 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 169 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 170 MODULE_PARM_DESC(ql2xfwloadbin, 171 "Option to specify location from which to load ISP firmware:.\n" 172 " 2 -- load firmware via the request_firmware() (hotplug).\n" 173 " interface.\n" 174 " 1 -- load firmware from flash.\n" 175 " 0 -- use default semantics.\n"); 176 177 int ql2xetsenable; 178 module_param(ql2xetsenable, int, S_IRUGO); 179 MODULE_PARM_DESC(ql2xetsenable, 180 "Enables firmware ETS burst." 181 "Default is 0 - skip ETS enablement."); 182 183 int ql2xdbwr = 1; 184 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 185 MODULE_PARM_DESC(ql2xdbwr, 186 "Option to specify scheme for request queue posting.\n" 187 " 0 -- Regular doorbell.\n" 188 " 1 -- CAMRAM doorbell (faster).\n"); 189 190 int ql2xtargetreset = 1; 191 module_param(ql2xtargetreset, int, S_IRUGO); 192 MODULE_PARM_DESC(ql2xtargetreset, 193 "Enable target reset." 194 "Default is 1 - use hw defaults."); 195 196 int ql2xgffidenable; 197 module_param(ql2xgffidenable, int, S_IRUGO); 198 MODULE_PARM_DESC(ql2xgffidenable, 199 "Enables GFF_ID checks of port type. " 200 "Default is 0 - Do not use GFF_ID information."); 201 202 int ql2xasynctmfenable = 1; 203 module_param(ql2xasynctmfenable, int, S_IRUGO); 204 MODULE_PARM_DESC(ql2xasynctmfenable, 205 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 206 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 207 208 int ql2xdontresethba; 209 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 210 MODULE_PARM_DESC(ql2xdontresethba, 211 "Option to specify reset behaviour.\n" 212 " 0 (Default) -- Reset on failure.\n" 213 " 1 -- Do not reset on failure.\n"); 214 215 uint64_t ql2xmaxlun = MAX_LUNS; 216 module_param(ql2xmaxlun, ullong, S_IRUGO); 217 MODULE_PARM_DESC(ql2xmaxlun, 218 "Defines the maximum LU number to register with the SCSI " 219 "midlayer. Default is 65535."); 220 221 int ql2xmdcapmask = 0x1F; 222 module_param(ql2xmdcapmask, int, S_IRUGO); 223 MODULE_PARM_DESC(ql2xmdcapmask, 224 "Set the Minidump driver capture mask level. " 225 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 226 227 int ql2xmdenable = 1; 228 module_param(ql2xmdenable, int, S_IRUGO); 229 MODULE_PARM_DESC(ql2xmdenable, 230 "Enable/disable MiniDump. " 231 "0 - MiniDump disabled. " 232 "1 (Default) - MiniDump enabled."); 233 234 int ql2xexlogins; 235 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 236 MODULE_PARM_DESC(ql2xexlogins, 237 "Number of extended Logins. " 238 "0 (Default)- Disabled."); 239 240 int ql2xexchoffld = 1024; 241 module_param(ql2xexchoffld, uint, 0644); 242 MODULE_PARM_DESC(ql2xexchoffld, 243 "Number of target exchanges."); 244 245 int ql2xiniexchg = 1024; 246 module_param(ql2xiniexchg, uint, 0644); 247 MODULE_PARM_DESC(ql2xiniexchg, 248 "Number of initiator exchanges."); 249 250 int ql2xfwholdabts; 251 module_param(ql2xfwholdabts, int, S_IRUGO); 252 MODULE_PARM_DESC(ql2xfwholdabts, 253 "Allow FW to hold status IOCB until ABTS rsp received. " 254 "0 (Default) Do not set fw option. " 255 "1 - Set fw option to hold ABTS."); 256 257 int ql2xmvasynctoatio = 1; 258 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 259 MODULE_PARM_DESC(ql2xmvasynctoatio, 260 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 261 "0 (Default). Do not move IOCBs" 262 "1 - Move IOCBs."); 263 264 int ql2xautodetectsfp = 1; 265 module_param(ql2xautodetectsfp, int, 0444); 266 MODULE_PARM_DESC(ql2xautodetectsfp, 267 "Detect SFP range and set appropriate distance.\n" 268 "1 (Default): Enable\n"); 269 270 int ql2xenablemsix = 1; 271 module_param(ql2xenablemsix, int, 0444); 272 MODULE_PARM_DESC(ql2xenablemsix, 273 "Set to enable MSI or MSI-X interrupt mechanism.\n" 274 " Default is 1, enable MSI-X interrupt mechanism.\n" 275 " 0 -- enable traditional pin-based mechanism.\n" 276 " 1 -- enable MSI-X interrupt mechanism.\n" 277 " 2 -- enable MSI interrupt mechanism.\n"); 278 279 int qla2xuseresexchforels; 280 module_param(qla2xuseresexchforels, int, 0444); 281 MODULE_PARM_DESC(qla2xuseresexchforels, 282 "Reserve 1/2 of emergency exchanges for ELS.\n" 283 " 0 (default): disabled"); 284 285 static int ql2xprotmask; 286 module_param(ql2xprotmask, int, 0644); 287 MODULE_PARM_DESC(ql2xprotmask, 288 "Override DIF/DIX protection capabilities mask\n" 289 "Default is 0 which sets protection mask based on " 290 "capabilities reported by HBA firmware.\n"); 291 292 static int ql2xprotguard; 293 module_param(ql2xprotguard, int, 0644); 294 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 295 " 0 -- Let HBA firmware decide\n" 296 " 1 -- Force T10 CRC\n" 297 " 2 -- Force IP checksum\n"); 298 299 int ql2xdifbundlinginternalbuffers; 300 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 301 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 302 "Force using internal buffers for DIF information\n" 303 "0 (Default). Based on check.\n" 304 "1 Force using internal buffers\n"); 305 306 int ql2xsmartsan; 307 module_param(ql2xsmartsan, int, 0444); 308 module_param_named(smartsan, ql2xsmartsan, int, 0444); 309 MODULE_PARM_DESC(ql2xsmartsan, 310 "Send SmartSAN Management Attributes for FDMI Registration." 311 " Default is 0 - No SmartSAN registration," 312 " 1 - Register SmartSAN Management Attributes."); 313 314 int ql2xrdpenable; 315 module_param(ql2xrdpenable, int, 0444); 316 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 317 MODULE_PARM_DESC(ql2xrdpenable, 318 "Enables RDP responses. " 319 "0 - no RDP responses (default). " 320 "1 - provide RDP responses."); 321 322 static void qla2x00_clear_drv_active(struct qla_hw_data *); 323 static void qla2x00_free_device(scsi_qla_host_t *); 324 static int qla2xxx_map_queues(struct Scsi_Host *shost); 325 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 326 327 328 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 329 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 330 331 /* TODO Convert to inlines 332 * 333 * Timer routines 334 */ 335 336 __inline__ void 337 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 338 { 339 timer_setup(&vha->timer, qla2x00_timer, 0); 340 vha->timer.expires = jiffies + interval * HZ; 341 add_timer(&vha->timer); 342 vha->timer_active = 1; 343 } 344 345 static inline void 346 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 347 { 348 /* Currently used for 82XX only. */ 349 if (vha->device_flags & DFLG_DEV_FAILED) { 350 ql_dbg(ql_dbg_timer, vha, 0x600d, 351 "Device in a failed state, returning.\n"); 352 return; 353 } 354 355 mod_timer(&vha->timer, jiffies + interval * HZ); 356 } 357 358 static __inline__ void 359 qla2x00_stop_timer(scsi_qla_host_t *vha) 360 { 361 del_timer_sync(&vha->timer); 362 vha->timer_active = 0; 363 } 364 365 static int qla2x00_do_dpc(void *data); 366 367 static void qla2x00_rst_aen(scsi_qla_host_t *); 368 369 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 370 struct req_que **, struct rsp_que **); 371 static void qla2x00_free_fw_dump(struct qla_hw_data *); 372 static void qla2x00_mem_free(struct qla_hw_data *); 373 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 374 struct qla_qpair *qpair); 375 376 /* -------------------------------------------------------------------------- */ 377 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 378 struct rsp_que *rsp) 379 { 380 struct qla_hw_data *ha = vha->hw; 381 382 rsp->qpair = ha->base_qpair; 383 rsp->req = req; 384 ha->base_qpair->hw = ha; 385 ha->base_qpair->req = req; 386 ha->base_qpair->rsp = rsp; 387 ha->base_qpair->vha = vha; 388 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 389 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 390 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 391 ha->base_qpair->srb_mempool = ha->srb_mempool; 392 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 393 ha->base_qpair->enable_class_2 = ql2xenableclass2; 394 /* init qpair to this cpu. Will adjust at run time. */ 395 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 396 ha->base_qpair->pdev = ha->pdev; 397 398 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 399 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 400 } 401 402 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 403 struct rsp_que *rsp) 404 { 405 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 406 407 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 408 GFP_KERNEL); 409 if (!ha->req_q_map) { 410 ql_log(ql_log_fatal, vha, 0x003b, 411 "Unable to allocate memory for request queue ptrs.\n"); 412 goto fail_req_map; 413 } 414 415 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 416 GFP_KERNEL); 417 if (!ha->rsp_q_map) { 418 ql_log(ql_log_fatal, vha, 0x003c, 419 "Unable to allocate memory for response queue ptrs.\n"); 420 goto fail_rsp_map; 421 } 422 423 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 424 if (ha->base_qpair == NULL) { 425 ql_log(ql_log_warn, vha, 0x00e0, 426 "Failed to allocate base queue pair memory.\n"); 427 goto fail_base_qpair; 428 } 429 430 qla_init_base_qpair(vha, req, rsp); 431 432 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 433 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 434 GFP_KERNEL); 435 if (!ha->queue_pair_map) { 436 ql_log(ql_log_fatal, vha, 0x0180, 437 "Unable to allocate memory for queue pair ptrs.\n"); 438 goto fail_qpair_map; 439 } 440 } 441 442 /* 443 * Make sure we record at least the request and response queue zero in 444 * case we need to free them if part of the probe fails. 445 */ 446 ha->rsp_q_map[0] = rsp; 447 ha->req_q_map[0] = req; 448 set_bit(0, ha->rsp_qid_map); 449 set_bit(0, ha->req_qid_map); 450 return 0; 451 452 fail_qpair_map: 453 kfree(ha->base_qpair); 454 ha->base_qpair = NULL; 455 fail_base_qpair: 456 kfree(ha->rsp_q_map); 457 ha->rsp_q_map = NULL; 458 fail_rsp_map: 459 kfree(ha->req_q_map); 460 ha->req_q_map = NULL; 461 fail_req_map: 462 return -ENOMEM; 463 } 464 465 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 466 { 467 if (IS_QLAFX00(ha)) { 468 if (req && req->ring_fx00) 469 dma_free_coherent(&ha->pdev->dev, 470 (req->length_fx00 + 1) * sizeof(request_t), 471 req->ring_fx00, req->dma_fx00); 472 } else if (req && req->ring) 473 dma_free_coherent(&ha->pdev->dev, 474 (req->length + 1) * sizeof(request_t), 475 req->ring, req->dma); 476 477 if (req) 478 kfree(req->outstanding_cmds); 479 480 kfree(req); 481 } 482 483 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 484 { 485 if (IS_QLAFX00(ha)) { 486 if (rsp && rsp->ring_fx00) 487 dma_free_coherent(&ha->pdev->dev, 488 (rsp->length_fx00 + 1) * sizeof(request_t), 489 rsp->ring_fx00, rsp->dma_fx00); 490 } else if (rsp && rsp->ring) { 491 dma_free_coherent(&ha->pdev->dev, 492 (rsp->length + 1) * sizeof(response_t), 493 rsp->ring, rsp->dma); 494 } 495 kfree(rsp); 496 } 497 498 static void qla2x00_free_queues(struct qla_hw_data *ha) 499 { 500 struct req_que *req; 501 struct rsp_que *rsp; 502 int cnt; 503 unsigned long flags; 504 505 if (ha->queue_pair_map) { 506 kfree(ha->queue_pair_map); 507 ha->queue_pair_map = NULL; 508 } 509 if (ha->base_qpair) { 510 kfree(ha->base_qpair); 511 ha->base_qpair = NULL; 512 } 513 514 spin_lock_irqsave(&ha->hardware_lock, flags); 515 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 516 if (!test_bit(cnt, ha->req_qid_map)) 517 continue; 518 519 req = ha->req_q_map[cnt]; 520 clear_bit(cnt, ha->req_qid_map); 521 ha->req_q_map[cnt] = NULL; 522 523 spin_unlock_irqrestore(&ha->hardware_lock, flags); 524 qla2x00_free_req_que(ha, req); 525 spin_lock_irqsave(&ha->hardware_lock, flags); 526 } 527 spin_unlock_irqrestore(&ha->hardware_lock, flags); 528 529 kfree(ha->req_q_map); 530 ha->req_q_map = NULL; 531 532 533 spin_lock_irqsave(&ha->hardware_lock, flags); 534 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 535 if (!test_bit(cnt, ha->rsp_qid_map)) 536 continue; 537 538 rsp = ha->rsp_q_map[cnt]; 539 clear_bit(cnt, ha->rsp_qid_map); 540 ha->rsp_q_map[cnt] = NULL; 541 spin_unlock_irqrestore(&ha->hardware_lock, flags); 542 qla2x00_free_rsp_que(ha, rsp); 543 spin_lock_irqsave(&ha->hardware_lock, flags); 544 } 545 spin_unlock_irqrestore(&ha->hardware_lock, flags); 546 547 kfree(ha->rsp_q_map); 548 ha->rsp_q_map = NULL; 549 } 550 551 static char * 552 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 553 { 554 struct qla_hw_data *ha = vha->hw; 555 static const char *const pci_bus_modes[] = { 556 "33", "66", "100", "133", 557 }; 558 uint16_t pci_bus; 559 560 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 561 if (pci_bus) { 562 snprintf(str, str_len, "PCI-X (%s MHz)", 563 pci_bus_modes[pci_bus]); 564 } else { 565 pci_bus = (ha->pci_attr & BIT_8) >> 8; 566 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 567 } 568 569 return str; 570 } 571 572 static char * 573 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 574 { 575 static const char *const pci_bus_modes[] = { 576 "33", "66", "100", "133", 577 }; 578 struct qla_hw_data *ha = vha->hw; 579 uint32_t pci_bus; 580 581 if (pci_is_pcie(ha->pdev)) { 582 uint32_t lstat, lspeed, lwidth; 583 const char *speed_str; 584 585 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 586 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 587 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 588 589 switch (lspeed) { 590 case 1: 591 speed_str = "2.5GT/s"; 592 break; 593 case 2: 594 speed_str = "5.0GT/s"; 595 break; 596 case 3: 597 speed_str = "8.0GT/s"; 598 break; 599 case 4: 600 speed_str = "16.0GT/s"; 601 break; 602 default: 603 speed_str = "<unknown>"; 604 break; 605 } 606 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 607 608 return str; 609 } 610 611 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 612 if (pci_bus == 0 || pci_bus == 8) 613 snprintf(str, str_len, "PCI (%s MHz)", 614 pci_bus_modes[pci_bus >> 3]); 615 else 616 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 617 pci_bus & 4 ? 2 : 1, 618 pci_bus_modes[pci_bus & 3]); 619 620 return str; 621 } 622 623 static char * 624 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 625 { 626 char un_str[10]; 627 struct qla_hw_data *ha = vha->hw; 628 629 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 630 ha->fw_minor_version, ha->fw_subminor_version); 631 632 if (ha->fw_attributes & BIT_9) { 633 strcat(str, "FLX"); 634 return (str); 635 } 636 637 switch (ha->fw_attributes & 0xFF) { 638 case 0x7: 639 strcat(str, "EF"); 640 break; 641 case 0x17: 642 strcat(str, "TP"); 643 break; 644 case 0x37: 645 strcat(str, "IP"); 646 break; 647 case 0x77: 648 strcat(str, "VI"); 649 break; 650 default: 651 sprintf(un_str, "(%x)", ha->fw_attributes); 652 strcat(str, un_str); 653 break; 654 } 655 if (ha->fw_attributes & 0x100) 656 strcat(str, "X"); 657 658 return (str); 659 } 660 661 static char * 662 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 663 { 664 struct qla_hw_data *ha = vha->hw; 665 666 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 667 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 668 return str; 669 } 670 671 void qla2x00_sp_free_dma(srb_t *sp) 672 { 673 struct qla_hw_data *ha = sp->vha->hw; 674 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 675 676 if (sp->flags & SRB_DMA_VALID) { 677 scsi_dma_unmap(cmd); 678 sp->flags &= ~SRB_DMA_VALID; 679 } 680 681 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 682 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 683 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 684 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 685 } 686 687 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 688 /* List assured to be having elements */ 689 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 690 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 691 } 692 693 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 694 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 695 696 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 697 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 698 } 699 700 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 701 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 702 703 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 704 ctx1->fcp_cmnd_dma); 705 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 706 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 707 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 708 mempool_free(ctx1, ha->ctx_mempool); 709 } 710 } 711 712 void qla2x00_sp_compl(srb_t *sp, int res) 713 { 714 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 715 struct completion *comp = sp->comp; 716 717 sp->free(sp); 718 cmd->result = res; 719 CMD_SP(cmd) = NULL; 720 cmd->scsi_done(cmd); 721 if (comp) 722 complete(comp); 723 } 724 725 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 726 { 727 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 728 struct qla_hw_data *ha = sp->fcport->vha->hw; 729 730 if (sp->flags & SRB_DMA_VALID) { 731 scsi_dma_unmap(cmd); 732 sp->flags &= ~SRB_DMA_VALID; 733 } 734 735 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 736 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 737 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 738 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 739 } 740 741 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 742 /* List assured to be having elements */ 743 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 744 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 745 } 746 747 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 748 struct crc_context *difctx = sp->u.scmd.crc_ctx; 749 struct dsd_dma *dif_dsd, *nxt_dsd; 750 751 list_for_each_entry_safe(dif_dsd, nxt_dsd, 752 &difctx->ldif_dma_hndl_list, list) { 753 list_del(&dif_dsd->list); 754 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 755 dif_dsd->dsd_list_dma); 756 kfree(dif_dsd); 757 difctx->no_dif_bundl--; 758 } 759 760 list_for_each_entry_safe(dif_dsd, nxt_dsd, 761 &difctx->ldif_dsd_list, list) { 762 list_del(&dif_dsd->list); 763 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 764 dif_dsd->dsd_list_dma); 765 kfree(dif_dsd); 766 difctx->no_ldif_dsd--; 767 } 768 769 if (difctx->no_ldif_dsd) { 770 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 771 "%s: difctx->no_ldif_dsd=%x\n", 772 __func__, difctx->no_ldif_dsd); 773 } 774 775 if (difctx->no_dif_bundl) { 776 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 777 "%s: difctx->no_dif_bundl=%x\n", 778 __func__, difctx->no_dif_bundl); 779 } 780 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 781 } 782 783 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 784 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 785 786 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 787 ctx1->fcp_cmnd_dma); 788 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 789 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 790 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 791 mempool_free(ctx1, ha->ctx_mempool); 792 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 793 } 794 795 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 796 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 797 798 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 799 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 800 } 801 } 802 803 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 804 { 805 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 806 struct completion *comp = sp->comp; 807 808 sp->free(sp); 809 cmd->result = res; 810 CMD_SP(cmd) = NULL; 811 cmd->scsi_done(cmd); 812 if (comp) 813 complete(comp); 814 } 815 816 static int 817 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 818 { 819 scsi_qla_host_t *vha = shost_priv(host); 820 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 821 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 822 struct qla_hw_data *ha = vha->hw; 823 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 824 srb_t *sp; 825 int rval; 826 827 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 828 WARN_ON_ONCE(!rport)) { 829 cmd->result = DID_NO_CONNECT << 16; 830 goto qc24_fail_command; 831 } 832 833 if (ha->mqenable) { 834 uint32_t tag; 835 uint16_t hwq; 836 struct qla_qpair *qpair = NULL; 837 838 tag = blk_mq_unique_tag(cmd->request); 839 hwq = blk_mq_unique_tag_to_hwq(tag); 840 qpair = ha->queue_pair_map[hwq]; 841 842 if (qpair) 843 return qla2xxx_mqueuecommand(host, cmd, qpair); 844 } 845 846 if (ha->flags.eeh_busy) { 847 if (ha->flags.pci_channel_io_perm_failure) { 848 ql_dbg(ql_dbg_aer, vha, 0x9010, 849 "PCI Channel IO permanent failure, exiting " 850 "cmd=%p.\n", cmd); 851 cmd->result = DID_NO_CONNECT << 16; 852 } else { 853 ql_dbg(ql_dbg_aer, vha, 0x9011, 854 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 855 cmd->result = DID_REQUEUE << 16; 856 } 857 goto qc24_fail_command; 858 } 859 860 rval = fc_remote_port_chkready(rport); 861 if (rval) { 862 cmd->result = rval; 863 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 864 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 865 cmd, rval); 866 goto qc24_fail_command; 867 } 868 869 if (!vha->flags.difdix_supported && 870 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 871 ql_dbg(ql_dbg_io, vha, 0x3004, 872 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 873 cmd); 874 cmd->result = DID_NO_CONNECT << 16; 875 goto qc24_fail_command; 876 } 877 878 if (!fcport) { 879 cmd->result = DID_NO_CONNECT << 16; 880 goto qc24_fail_command; 881 } 882 883 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 884 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 885 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 886 ql_dbg(ql_dbg_io, vha, 0x3005, 887 "Returning DNC, fcport_state=%d loop_state=%d.\n", 888 atomic_read(&fcport->state), 889 atomic_read(&base_vha->loop_state)); 890 cmd->result = DID_NO_CONNECT << 16; 891 goto qc24_fail_command; 892 } 893 goto qc24_target_busy; 894 } 895 896 /* 897 * Return target busy if we've received a non-zero retry_delay_timer 898 * in a FCP_RSP. 899 */ 900 if (fcport->retry_delay_timestamp == 0) { 901 /* retry delay not set */ 902 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 903 fcport->retry_delay_timestamp = 0; 904 else 905 goto qc24_target_busy; 906 907 sp = scsi_cmd_priv(cmd); 908 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 909 910 sp->u.scmd.cmd = cmd; 911 sp->type = SRB_SCSI_CMD; 912 913 CMD_SP(cmd) = (void *)sp; 914 sp->free = qla2x00_sp_free_dma; 915 sp->done = qla2x00_sp_compl; 916 917 rval = ha->isp_ops->start_scsi(sp); 918 if (rval != QLA_SUCCESS) { 919 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 920 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 921 goto qc24_host_busy_free_sp; 922 } 923 924 return 0; 925 926 qc24_host_busy_free_sp: 927 sp->free(sp); 928 929 qc24_target_busy: 930 return SCSI_MLQUEUE_TARGET_BUSY; 931 932 qc24_fail_command: 933 cmd->scsi_done(cmd); 934 935 return 0; 936 } 937 938 /* For MQ supported I/O */ 939 int 940 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 941 struct qla_qpair *qpair) 942 { 943 scsi_qla_host_t *vha = shost_priv(host); 944 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 945 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 946 struct qla_hw_data *ha = vha->hw; 947 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 948 srb_t *sp; 949 int rval; 950 951 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE; 952 if (rval) { 953 cmd->result = rval; 954 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 955 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 956 cmd, rval); 957 goto qc24_fail_command; 958 } 959 960 if (!fcport) { 961 cmd->result = DID_NO_CONNECT << 16; 962 goto qc24_fail_command; 963 } 964 965 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 966 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 967 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 968 ql_dbg(ql_dbg_io, vha, 0x3077, 969 "Returning DNC, fcport_state=%d loop_state=%d.\n", 970 atomic_read(&fcport->state), 971 atomic_read(&base_vha->loop_state)); 972 cmd->result = DID_NO_CONNECT << 16; 973 goto qc24_fail_command; 974 } 975 goto qc24_target_busy; 976 } 977 978 /* 979 * Return target busy if we've received a non-zero retry_delay_timer 980 * in a FCP_RSP. 981 */ 982 if (fcport->retry_delay_timestamp == 0) { 983 /* retry delay not set */ 984 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 985 fcport->retry_delay_timestamp = 0; 986 else 987 goto qc24_target_busy; 988 989 sp = scsi_cmd_priv(cmd); 990 qla2xxx_init_sp(sp, vha, qpair, fcport); 991 992 sp->u.scmd.cmd = cmd; 993 sp->type = SRB_SCSI_CMD; 994 CMD_SP(cmd) = (void *)sp; 995 sp->free = qla2xxx_qpair_sp_free_dma; 996 sp->done = qla2xxx_qpair_sp_compl; 997 998 rval = ha->isp_ops->start_scsi_mq(sp); 999 if (rval != QLA_SUCCESS) { 1000 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1001 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1002 if (rval == QLA_INTERFACE_ERROR) 1003 goto qc24_free_sp_fail_command; 1004 goto qc24_host_busy_free_sp; 1005 } 1006 1007 return 0; 1008 1009 qc24_host_busy_free_sp: 1010 sp->free(sp); 1011 1012 qc24_target_busy: 1013 return SCSI_MLQUEUE_TARGET_BUSY; 1014 1015 qc24_free_sp_fail_command: 1016 sp->free(sp); 1017 CMD_SP(cmd) = NULL; 1018 qla2xxx_rel_qpair_sp(sp->qpair, sp); 1019 1020 qc24_fail_command: 1021 cmd->scsi_done(cmd); 1022 1023 return 0; 1024 } 1025 1026 /* 1027 * qla2x00_eh_wait_on_command 1028 * Waits for the command to be returned by the Firmware for some 1029 * max time. 1030 * 1031 * Input: 1032 * cmd = Scsi Command to wait on. 1033 * 1034 * Return: 1035 * Completed in time : QLA_SUCCESS 1036 * Did not complete in time : QLA_FUNCTION_FAILED 1037 */ 1038 static int 1039 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1040 { 1041 #define ABORT_POLLING_PERIOD 1000 1042 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1043 unsigned long wait_iter = ABORT_WAIT_ITER; 1044 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1045 struct qla_hw_data *ha = vha->hw; 1046 int ret = QLA_SUCCESS; 1047 1048 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1049 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1050 "Return:eh_wait.\n"); 1051 return ret; 1052 } 1053 1054 while (CMD_SP(cmd) && wait_iter--) { 1055 msleep(ABORT_POLLING_PERIOD); 1056 } 1057 if (CMD_SP(cmd)) 1058 ret = QLA_FUNCTION_FAILED; 1059 1060 return ret; 1061 } 1062 1063 /* 1064 * qla2x00_wait_for_hba_online 1065 * Wait till the HBA is online after going through 1066 * <= MAX_RETRIES_OF_ISP_ABORT or 1067 * finally HBA is disabled ie marked offline 1068 * 1069 * Input: 1070 * ha - pointer to host adapter structure 1071 * 1072 * Note: 1073 * Does context switching-Release SPIN_LOCK 1074 * (if any) before calling this routine. 1075 * 1076 * Return: 1077 * Success (Adapter is online) : 0 1078 * Failed (Adapter is offline/disabled) : 1 1079 */ 1080 int 1081 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1082 { 1083 int return_status; 1084 unsigned long wait_online; 1085 struct qla_hw_data *ha = vha->hw; 1086 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1087 1088 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1089 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1090 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1091 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1092 ha->dpc_active) && time_before(jiffies, wait_online)) { 1093 1094 msleep(1000); 1095 } 1096 if (base_vha->flags.online) 1097 return_status = QLA_SUCCESS; 1098 else 1099 return_status = QLA_FUNCTION_FAILED; 1100 1101 return (return_status); 1102 } 1103 1104 static inline int test_fcport_count(scsi_qla_host_t *vha) 1105 { 1106 struct qla_hw_data *ha = vha->hw; 1107 unsigned long flags; 1108 int res; 1109 1110 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1111 ql_dbg(ql_dbg_init, vha, 0x00ec, 1112 "tgt %p, fcport_count=%d\n", 1113 vha, vha->fcport_count); 1114 res = (vha->fcport_count == 0); 1115 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1116 1117 return res; 1118 } 1119 1120 /* 1121 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1122 * it has dependency on UNLOADING flag to stop device discovery 1123 */ 1124 void 1125 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1126 { 1127 u8 i; 1128 1129 qla2x00_mark_all_devices_lost(vha); 1130 1131 for (i = 0; i < 10; i++) { 1132 if (wait_event_timeout(vha->fcport_waitQ, 1133 test_fcport_count(vha), HZ) > 0) 1134 break; 1135 } 1136 1137 flush_workqueue(vha->hw->wq); 1138 } 1139 1140 /* 1141 * qla2x00_wait_for_hba_ready 1142 * Wait till the HBA is ready before doing driver unload 1143 * 1144 * Input: 1145 * ha - pointer to host adapter structure 1146 * 1147 * Note: 1148 * Does context switching-Release SPIN_LOCK 1149 * (if any) before calling this routine. 1150 * 1151 */ 1152 static void 1153 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1154 { 1155 struct qla_hw_data *ha = vha->hw; 1156 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1157 1158 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1159 ha->flags.mbox_busy) || 1160 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1161 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1162 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1163 break; 1164 msleep(1000); 1165 } 1166 } 1167 1168 int 1169 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1170 { 1171 int return_status; 1172 unsigned long wait_reset; 1173 struct qla_hw_data *ha = vha->hw; 1174 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1175 1176 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1177 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1178 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1179 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1180 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1181 1182 msleep(1000); 1183 1184 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1185 ha->flags.chip_reset_done) 1186 break; 1187 } 1188 if (ha->flags.chip_reset_done) 1189 return_status = QLA_SUCCESS; 1190 else 1191 return_status = QLA_FUNCTION_FAILED; 1192 1193 return return_status; 1194 } 1195 1196 #define ISP_REG_DISCONNECT 0xffffffffU 1197 /************************************************************************** 1198 * qla2x00_isp_reg_stat 1199 * 1200 * Description: 1201 * Read the host status register of ISP before aborting the command. 1202 * 1203 * Input: 1204 * ha = pointer to host adapter structure. 1205 * 1206 * 1207 * Returns: 1208 * Either true or false. 1209 * 1210 * Note: Return true if there is register disconnect. 1211 **************************************************************************/ 1212 static inline 1213 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1214 { 1215 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1216 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1217 1218 if (IS_P3P_TYPE(ha)) 1219 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1220 else 1221 return ((RD_REG_DWORD(®->host_status)) == 1222 ISP_REG_DISCONNECT); 1223 } 1224 1225 /************************************************************************** 1226 * qla2xxx_eh_abort 1227 * 1228 * Description: 1229 * The abort function will abort the specified command. 1230 * 1231 * Input: 1232 * cmd = Linux SCSI command packet to be aborted. 1233 * 1234 * Returns: 1235 * Either SUCCESS or FAILED. 1236 * 1237 * Note: 1238 * Only return FAILED if command not returned by firmware. 1239 **************************************************************************/ 1240 static int 1241 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1242 { 1243 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1244 DECLARE_COMPLETION_ONSTACK(comp); 1245 srb_t *sp; 1246 int ret; 1247 unsigned int id; 1248 uint64_t lun; 1249 int rval; 1250 struct qla_hw_data *ha = vha->hw; 1251 uint32_t ratov_j; 1252 struct qla_qpair *qpair; 1253 unsigned long flags; 1254 1255 if (qla2x00_isp_reg_stat(ha)) { 1256 ql_log(ql_log_info, vha, 0x8042, 1257 "PCI/Register disconnect, exiting.\n"); 1258 return FAILED; 1259 } 1260 1261 ret = fc_block_scsi_eh(cmd); 1262 if (ret != 0) 1263 return ret; 1264 1265 sp = scsi_cmd_priv(cmd); 1266 qpair = sp->qpair; 1267 1268 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1269 return SUCCESS; 1270 1271 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1272 sp->comp = ∁ 1273 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1274 1275 1276 id = cmd->device->id; 1277 lun = cmd->device->lun; 1278 1279 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1280 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1281 vha->host_no, id, lun, sp, cmd, sp->handle); 1282 1283 /* 1284 * Abort will release the original Command/sp from FW. Let the 1285 * original command call scsi_done. In return, he will wakeup 1286 * this sleeping thread. 1287 */ 1288 rval = ha->isp_ops->abort_command(sp); 1289 1290 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1291 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1292 1293 /* Wait for the command completion. */ 1294 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1295 ratov_j = msecs_to_jiffies(ratov_j); 1296 switch (rval) { 1297 case QLA_SUCCESS: 1298 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1299 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1300 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1301 __func__, ha->r_a_tov/10); 1302 ret = FAILED; 1303 } else { 1304 ret = SUCCESS; 1305 } 1306 break; 1307 default: 1308 ret = FAILED; 1309 break; 1310 } 1311 1312 sp->comp = NULL; 1313 1314 ql_log(ql_log_info, vha, 0x801c, 1315 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1316 vha->host_no, id, lun, ret); 1317 1318 return ret; 1319 } 1320 1321 /* 1322 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1323 */ 1324 int 1325 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1326 uint64_t l, enum nexus_wait_type type) 1327 { 1328 int cnt, match, status; 1329 unsigned long flags; 1330 struct qla_hw_data *ha = vha->hw; 1331 struct req_que *req; 1332 srb_t *sp; 1333 struct scsi_cmnd *cmd; 1334 1335 status = QLA_SUCCESS; 1336 1337 spin_lock_irqsave(&ha->hardware_lock, flags); 1338 req = vha->req; 1339 for (cnt = 1; status == QLA_SUCCESS && 1340 cnt < req->num_outstanding_cmds; cnt++) { 1341 sp = req->outstanding_cmds[cnt]; 1342 if (!sp) 1343 continue; 1344 if (sp->type != SRB_SCSI_CMD) 1345 continue; 1346 if (vha->vp_idx != sp->vha->vp_idx) 1347 continue; 1348 match = 0; 1349 cmd = GET_CMD_SP(sp); 1350 switch (type) { 1351 case WAIT_HOST: 1352 match = 1; 1353 break; 1354 case WAIT_TARGET: 1355 match = cmd->device->id == t; 1356 break; 1357 case WAIT_LUN: 1358 match = (cmd->device->id == t && 1359 cmd->device->lun == l); 1360 break; 1361 } 1362 if (!match) 1363 continue; 1364 1365 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1366 status = qla2x00_eh_wait_on_command(cmd); 1367 spin_lock_irqsave(&ha->hardware_lock, flags); 1368 } 1369 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1370 1371 return status; 1372 } 1373 1374 static char *reset_errors[] = { 1375 "HBA not online", 1376 "HBA not ready", 1377 "Task management failed", 1378 "Waiting for command completions", 1379 }; 1380 1381 static int 1382 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1383 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1384 { 1385 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1386 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1387 int err; 1388 1389 if (!fcport) { 1390 return FAILED; 1391 } 1392 1393 err = fc_block_scsi_eh(cmd); 1394 if (err != 0) 1395 return err; 1396 1397 if (fcport->deleted) 1398 return SUCCESS; 1399 1400 ql_log(ql_log_info, vha, 0x8009, 1401 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1402 cmd->device->id, cmd->device->lun, cmd); 1403 1404 err = 0; 1405 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1406 ql_log(ql_log_warn, vha, 0x800a, 1407 "Wait for hba online failed for cmd=%p.\n", cmd); 1408 goto eh_reset_failed; 1409 } 1410 err = 2; 1411 if (do_reset(fcport, cmd->device->lun, 1) 1412 != QLA_SUCCESS) { 1413 ql_log(ql_log_warn, vha, 0x800c, 1414 "do_reset failed for cmd=%p.\n", cmd); 1415 goto eh_reset_failed; 1416 } 1417 err = 3; 1418 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1419 cmd->device->lun, type) != QLA_SUCCESS) { 1420 ql_log(ql_log_warn, vha, 0x800d, 1421 "wait for pending cmds failed for cmd=%p.\n", cmd); 1422 goto eh_reset_failed; 1423 } 1424 1425 ql_log(ql_log_info, vha, 0x800e, 1426 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1427 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1428 1429 return SUCCESS; 1430 1431 eh_reset_failed: 1432 ql_log(ql_log_info, vha, 0x800f, 1433 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1434 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1435 cmd); 1436 return FAILED; 1437 } 1438 1439 static int 1440 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1441 { 1442 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1443 struct qla_hw_data *ha = vha->hw; 1444 1445 if (qla2x00_isp_reg_stat(ha)) { 1446 ql_log(ql_log_info, vha, 0x803e, 1447 "PCI/Register disconnect, exiting.\n"); 1448 return FAILED; 1449 } 1450 1451 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1452 ha->isp_ops->lun_reset); 1453 } 1454 1455 static int 1456 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1457 { 1458 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1459 struct qla_hw_data *ha = vha->hw; 1460 1461 if (qla2x00_isp_reg_stat(ha)) { 1462 ql_log(ql_log_info, vha, 0x803f, 1463 "PCI/Register disconnect, exiting.\n"); 1464 return FAILED; 1465 } 1466 1467 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1468 ha->isp_ops->target_reset); 1469 } 1470 1471 /************************************************************************** 1472 * qla2xxx_eh_bus_reset 1473 * 1474 * Description: 1475 * The bus reset function will reset the bus and abort any executing 1476 * commands. 1477 * 1478 * Input: 1479 * cmd = Linux SCSI command packet of the command that cause the 1480 * bus reset. 1481 * 1482 * Returns: 1483 * SUCCESS/FAILURE (defined as macro in scsi.h). 1484 * 1485 **************************************************************************/ 1486 static int 1487 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1488 { 1489 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1490 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1491 int ret = FAILED; 1492 unsigned int id; 1493 uint64_t lun; 1494 struct qla_hw_data *ha = vha->hw; 1495 1496 if (qla2x00_isp_reg_stat(ha)) { 1497 ql_log(ql_log_info, vha, 0x8040, 1498 "PCI/Register disconnect, exiting.\n"); 1499 return FAILED; 1500 } 1501 1502 id = cmd->device->id; 1503 lun = cmd->device->lun; 1504 1505 if (!fcport) { 1506 return ret; 1507 } 1508 1509 ret = fc_block_scsi_eh(cmd); 1510 if (ret != 0) 1511 return ret; 1512 ret = FAILED; 1513 1514 if (qla2x00_chip_is_down(vha)) 1515 return ret; 1516 1517 ql_log(ql_log_info, vha, 0x8012, 1518 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1519 1520 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1521 ql_log(ql_log_fatal, vha, 0x8013, 1522 "Wait for hba online failed board disabled.\n"); 1523 goto eh_bus_reset_done; 1524 } 1525 1526 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1527 ret = SUCCESS; 1528 1529 if (ret == FAILED) 1530 goto eh_bus_reset_done; 1531 1532 /* Flush outstanding commands. */ 1533 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1534 QLA_SUCCESS) { 1535 ql_log(ql_log_warn, vha, 0x8014, 1536 "Wait for pending commands failed.\n"); 1537 ret = FAILED; 1538 } 1539 1540 eh_bus_reset_done: 1541 ql_log(ql_log_warn, vha, 0x802b, 1542 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1543 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1544 1545 return ret; 1546 } 1547 1548 /************************************************************************** 1549 * qla2xxx_eh_host_reset 1550 * 1551 * Description: 1552 * The reset function will reset the Adapter. 1553 * 1554 * Input: 1555 * cmd = Linux SCSI command packet of the command that cause the 1556 * adapter reset. 1557 * 1558 * Returns: 1559 * Either SUCCESS or FAILED. 1560 * 1561 * Note: 1562 **************************************************************************/ 1563 static int 1564 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1565 { 1566 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1567 struct qla_hw_data *ha = vha->hw; 1568 int ret = FAILED; 1569 unsigned int id; 1570 uint64_t lun; 1571 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1572 1573 if (qla2x00_isp_reg_stat(ha)) { 1574 ql_log(ql_log_info, vha, 0x8041, 1575 "PCI/Register disconnect, exiting.\n"); 1576 schedule_work(&ha->board_disable); 1577 return SUCCESS; 1578 } 1579 1580 id = cmd->device->id; 1581 lun = cmd->device->lun; 1582 1583 ql_log(ql_log_info, vha, 0x8018, 1584 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1585 1586 /* 1587 * No point in issuing another reset if one is active. Also do not 1588 * attempt a reset if we are updating flash. 1589 */ 1590 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1591 goto eh_host_reset_lock; 1592 1593 if (vha != base_vha) { 1594 if (qla2x00_vp_abort_isp(vha)) 1595 goto eh_host_reset_lock; 1596 } else { 1597 if (IS_P3P_TYPE(vha->hw)) { 1598 if (!qla82xx_fcoe_ctx_reset(vha)) { 1599 /* Ctx reset success */ 1600 ret = SUCCESS; 1601 goto eh_host_reset_lock; 1602 } 1603 /* fall thru if ctx reset failed */ 1604 } 1605 if (ha->wq) 1606 flush_workqueue(ha->wq); 1607 1608 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1609 if (ha->isp_ops->abort_isp(base_vha)) { 1610 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1611 /* failed. schedule dpc to try */ 1612 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1613 1614 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1615 ql_log(ql_log_warn, vha, 0x802a, 1616 "wait for hba online failed.\n"); 1617 goto eh_host_reset_lock; 1618 } 1619 } 1620 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1621 } 1622 1623 /* Waiting for command to be returned to OS.*/ 1624 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1625 QLA_SUCCESS) 1626 ret = SUCCESS; 1627 1628 eh_host_reset_lock: 1629 ql_log(ql_log_info, vha, 0x8017, 1630 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1631 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1632 1633 return ret; 1634 } 1635 1636 /* 1637 * qla2x00_loop_reset 1638 * Issue loop reset. 1639 * 1640 * Input: 1641 * ha = adapter block pointer. 1642 * 1643 * Returns: 1644 * 0 = success 1645 */ 1646 int 1647 qla2x00_loop_reset(scsi_qla_host_t *vha) 1648 { 1649 int ret; 1650 struct fc_port *fcport; 1651 struct qla_hw_data *ha = vha->hw; 1652 1653 if (IS_QLAFX00(ha)) { 1654 return qlafx00_loop_reset(vha); 1655 } 1656 1657 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1658 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1659 if (fcport->port_type != FCT_TARGET) 1660 continue; 1661 1662 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1663 if (ret != QLA_SUCCESS) { 1664 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1665 "Bus Reset failed: Reset=%d " 1666 "d_id=%x.\n", ret, fcport->d_id.b24); 1667 } 1668 } 1669 } 1670 1671 1672 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1673 atomic_set(&vha->loop_state, LOOP_DOWN); 1674 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1675 qla2x00_mark_all_devices_lost(vha); 1676 ret = qla2x00_full_login_lip(vha); 1677 if (ret != QLA_SUCCESS) { 1678 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1679 "full_login_lip=%d.\n", ret); 1680 } 1681 } 1682 1683 if (ha->flags.enable_lip_reset) { 1684 ret = qla2x00_lip_reset(vha); 1685 if (ret != QLA_SUCCESS) 1686 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1687 "lip_reset failed (%d).\n", ret); 1688 } 1689 1690 /* Issue marker command only when we are going to start the I/O */ 1691 vha->marker_needed = 1; 1692 1693 return QLA_SUCCESS; 1694 } 1695 1696 /* 1697 * The caller must ensure that no completion interrupts will happen 1698 * while this function is in progress. 1699 */ 1700 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1701 unsigned long *flags) 1702 __releases(qp->qp_lock_ptr) 1703 __acquires(qp->qp_lock_ptr) 1704 { 1705 DECLARE_COMPLETION_ONSTACK(comp); 1706 scsi_qla_host_t *vha = qp->vha; 1707 struct qla_hw_data *ha = vha->hw; 1708 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1709 int rval; 1710 bool ret_cmd; 1711 uint32_t ratov_j; 1712 1713 lockdep_assert_held(qp->qp_lock_ptr); 1714 1715 if (qla2x00_chip_is_down(vha)) { 1716 sp->done(sp, res); 1717 return; 1718 } 1719 1720 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1721 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1722 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1723 !qla2x00_isp_reg_stat(ha))) { 1724 if (sp->comp) { 1725 sp->done(sp, res); 1726 return; 1727 } 1728 1729 sp->comp = ∁ 1730 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1731 1732 rval = ha->isp_ops->abort_command(sp); 1733 /* Wait for command completion. */ 1734 ret_cmd = false; 1735 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1736 ratov_j = msecs_to_jiffies(ratov_j); 1737 switch (rval) { 1738 case QLA_SUCCESS: 1739 if (wait_for_completion_timeout(&comp, ratov_j)) { 1740 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1741 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1742 __func__, ha->r_a_tov/10); 1743 ret_cmd = true; 1744 } 1745 /* else FW return SP to driver */ 1746 break; 1747 default: 1748 ret_cmd = true; 1749 break; 1750 } 1751 1752 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1753 if (ret_cmd && blk_mq_request_started(cmd->request)) 1754 sp->done(sp, res); 1755 } else { 1756 sp->done(sp, res); 1757 } 1758 } 1759 1760 /* 1761 * The caller must ensure that no completion interrupts will happen 1762 * while this function is in progress. 1763 */ 1764 static void 1765 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1766 { 1767 int cnt; 1768 unsigned long flags; 1769 srb_t *sp; 1770 scsi_qla_host_t *vha = qp->vha; 1771 struct qla_hw_data *ha = vha->hw; 1772 struct req_que *req; 1773 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1774 struct qla_tgt_cmd *cmd; 1775 1776 if (!ha->req_q_map) 1777 return; 1778 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1779 req = qp->req; 1780 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1781 sp = req->outstanding_cmds[cnt]; 1782 if (sp) { 1783 switch (sp->cmd_type) { 1784 case TYPE_SRB: 1785 qla2x00_abort_srb(qp, sp, res, &flags); 1786 break; 1787 case TYPE_TGT_CMD: 1788 if (!vha->hw->tgt.tgt_ops || !tgt || 1789 qla_ini_mode_enabled(vha)) { 1790 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1791 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1792 vha->dpc_flags); 1793 continue; 1794 } 1795 cmd = (struct qla_tgt_cmd *)sp; 1796 cmd->aborted = 1; 1797 break; 1798 case TYPE_TGT_TMCMD: 1799 /* Skip task management functions. */ 1800 break; 1801 default: 1802 break; 1803 } 1804 req->outstanding_cmds[cnt] = NULL; 1805 } 1806 } 1807 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1808 } 1809 1810 /* 1811 * The caller must ensure that no completion interrupts will happen 1812 * while this function is in progress. 1813 */ 1814 void 1815 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1816 { 1817 int que; 1818 struct qla_hw_data *ha = vha->hw; 1819 1820 /* Continue only if initialization complete. */ 1821 if (!ha->base_qpair) 1822 return; 1823 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1824 1825 if (!ha->queue_pair_map) 1826 return; 1827 for (que = 0; que < ha->max_qpairs; que++) { 1828 if (!ha->queue_pair_map[que]) 1829 continue; 1830 1831 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1832 } 1833 } 1834 1835 static int 1836 qla2xxx_slave_alloc(struct scsi_device *sdev) 1837 { 1838 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1839 1840 if (!rport || fc_remote_port_chkready(rport)) 1841 return -ENXIO; 1842 1843 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1844 1845 return 0; 1846 } 1847 1848 static int 1849 qla2xxx_slave_configure(struct scsi_device *sdev) 1850 { 1851 scsi_qla_host_t *vha = shost_priv(sdev->host); 1852 struct req_que *req = vha->req; 1853 1854 if (IS_T10_PI_CAPABLE(vha->hw)) 1855 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1856 1857 scsi_change_queue_depth(sdev, req->max_q_depth); 1858 return 0; 1859 } 1860 1861 static void 1862 qla2xxx_slave_destroy(struct scsi_device *sdev) 1863 { 1864 sdev->hostdata = NULL; 1865 } 1866 1867 /** 1868 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1869 * @ha: HA context 1870 * 1871 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1872 * supported addressing method. 1873 */ 1874 static void 1875 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1876 { 1877 /* Assume a 32bit DMA mask. */ 1878 ha->flags.enable_64bit_addressing = 0; 1879 1880 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1881 /* Any upper-dword bits set? */ 1882 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1883 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1884 /* Ok, a 64bit DMA mask is applicable. */ 1885 ha->flags.enable_64bit_addressing = 1; 1886 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1887 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1888 return; 1889 } 1890 } 1891 1892 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1893 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1894 } 1895 1896 static void 1897 qla2x00_enable_intrs(struct qla_hw_data *ha) 1898 { 1899 unsigned long flags = 0; 1900 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1901 1902 spin_lock_irqsave(&ha->hardware_lock, flags); 1903 ha->interrupts_on = 1; 1904 /* enable risc and host interrupts */ 1905 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1906 RD_REG_WORD(®->ictrl); 1907 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1908 1909 } 1910 1911 static void 1912 qla2x00_disable_intrs(struct qla_hw_data *ha) 1913 { 1914 unsigned long flags = 0; 1915 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1916 1917 spin_lock_irqsave(&ha->hardware_lock, flags); 1918 ha->interrupts_on = 0; 1919 /* disable risc and host interrupts */ 1920 WRT_REG_WORD(®->ictrl, 0); 1921 RD_REG_WORD(®->ictrl); 1922 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1923 } 1924 1925 static void 1926 qla24xx_enable_intrs(struct qla_hw_data *ha) 1927 { 1928 unsigned long flags = 0; 1929 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1930 1931 spin_lock_irqsave(&ha->hardware_lock, flags); 1932 ha->interrupts_on = 1; 1933 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1934 RD_REG_DWORD(®->ictrl); 1935 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1936 } 1937 1938 static void 1939 qla24xx_disable_intrs(struct qla_hw_data *ha) 1940 { 1941 unsigned long flags = 0; 1942 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1943 1944 if (IS_NOPOLLING_TYPE(ha)) 1945 return; 1946 spin_lock_irqsave(&ha->hardware_lock, flags); 1947 ha->interrupts_on = 0; 1948 WRT_REG_DWORD(®->ictrl, 0); 1949 RD_REG_DWORD(®->ictrl); 1950 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1951 } 1952 1953 static int 1954 qla2x00_iospace_config(struct qla_hw_data *ha) 1955 { 1956 resource_size_t pio; 1957 uint16_t msix; 1958 1959 if (pci_request_selected_regions(ha->pdev, ha->bars, 1960 QLA2XXX_DRIVER_NAME)) { 1961 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1962 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1963 pci_name(ha->pdev)); 1964 goto iospace_error_exit; 1965 } 1966 if (!(ha->bars & 1)) 1967 goto skip_pio; 1968 1969 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1970 pio = pci_resource_start(ha->pdev, 0); 1971 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1972 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1973 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1974 "Invalid pci I/O region size (%s).\n", 1975 pci_name(ha->pdev)); 1976 pio = 0; 1977 } 1978 } else { 1979 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1980 "Region #0 no a PIO resource (%s).\n", 1981 pci_name(ha->pdev)); 1982 pio = 0; 1983 } 1984 ha->pio_address = pio; 1985 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1986 "PIO address=%llu.\n", 1987 (unsigned long long)ha->pio_address); 1988 1989 skip_pio: 1990 /* Use MMIO operations for all accesses. */ 1991 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1992 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1993 "Region #1 not an MMIO resource (%s), aborting.\n", 1994 pci_name(ha->pdev)); 1995 goto iospace_error_exit; 1996 } 1997 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1998 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1999 "Invalid PCI mem region size (%s), aborting.\n", 2000 pci_name(ha->pdev)); 2001 goto iospace_error_exit; 2002 } 2003 2004 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2005 if (!ha->iobase) { 2006 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2007 "Cannot remap MMIO (%s), aborting.\n", 2008 pci_name(ha->pdev)); 2009 goto iospace_error_exit; 2010 } 2011 2012 /* Determine queue resources */ 2013 ha->max_req_queues = ha->max_rsp_queues = 1; 2014 ha->msix_count = QLA_BASE_VECTORS; 2015 if (!ql2xmqsupport || !ql2xnvmeenable || 2016 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2017 goto mqiobase_exit; 2018 2019 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2020 pci_resource_len(ha->pdev, 3)); 2021 if (ha->mqiobase) { 2022 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2023 "MQIO Base=%p.\n", ha->mqiobase); 2024 /* Read MSIX vector size of the board */ 2025 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2026 ha->msix_count = msix + 1; 2027 /* Max queues are bounded by available msix vectors */ 2028 /* MB interrupt uses 1 vector */ 2029 ha->max_req_queues = ha->msix_count - 1; 2030 ha->max_rsp_queues = ha->max_req_queues; 2031 /* Queue pairs is the max value minus the base queue pair */ 2032 ha->max_qpairs = ha->max_rsp_queues - 1; 2033 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2034 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2035 2036 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2037 "MSI-X vector count: %d.\n", ha->msix_count); 2038 } else 2039 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2040 "BAR 3 not enabled.\n"); 2041 2042 mqiobase_exit: 2043 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2044 "MSIX Count: %d.\n", ha->msix_count); 2045 return (0); 2046 2047 iospace_error_exit: 2048 return (-ENOMEM); 2049 } 2050 2051 2052 static int 2053 qla83xx_iospace_config(struct qla_hw_data *ha) 2054 { 2055 uint16_t msix; 2056 2057 if (pci_request_selected_regions(ha->pdev, ha->bars, 2058 QLA2XXX_DRIVER_NAME)) { 2059 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2060 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2061 pci_name(ha->pdev)); 2062 2063 goto iospace_error_exit; 2064 } 2065 2066 /* Use MMIO operations for all accesses. */ 2067 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2068 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2069 "Invalid pci I/O region size (%s).\n", 2070 pci_name(ha->pdev)); 2071 goto iospace_error_exit; 2072 } 2073 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2074 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2075 "Invalid PCI mem region size (%s), aborting\n", 2076 pci_name(ha->pdev)); 2077 goto iospace_error_exit; 2078 } 2079 2080 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2081 if (!ha->iobase) { 2082 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2083 "Cannot remap MMIO (%s), aborting.\n", 2084 pci_name(ha->pdev)); 2085 goto iospace_error_exit; 2086 } 2087 2088 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2089 /* 83XX 26XX always use MQ type access for queues 2090 * - mbar 2, a.k.a region 4 */ 2091 ha->max_req_queues = ha->max_rsp_queues = 1; 2092 ha->msix_count = QLA_BASE_VECTORS; 2093 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2094 pci_resource_len(ha->pdev, 4)); 2095 2096 if (!ha->mqiobase) { 2097 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2098 "BAR2/region4 not enabled\n"); 2099 goto mqiobase_exit; 2100 } 2101 2102 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2103 pci_resource_len(ha->pdev, 2)); 2104 if (ha->msixbase) { 2105 /* Read MSIX vector size of the board */ 2106 pci_read_config_word(ha->pdev, 2107 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2108 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2109 /* 2110 * By default, driver uses at least two msix vectors 2111 * (default & rspq) 2112 */ 2113 if (ql2xmqsupport || ql2xnvmeenable) { 2114 /* MB interrupt uses 1 vector */ 2115 ha->max_req_queues = ha->msix_count - 1; 2116 2117 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2118 if (QLA_TGT_MODE_ENABLED()) 2119 ha->max_req_queues--; 2120 2121 ha->max_rsp_queues = ha->max_req_queues; 2122 2123 /* Queue pairs is the max value minus 2124 * the base queue pair */ 2125 ha->max_qpairs = ha->max_req_queues - 1; 2126 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2127 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2128 } 2129 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2130 "MSI-X vector count: %d.\n", ha->msix_count); 2131 } else 2132 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2133 "BAR 1 not enabled.\n"); 2134 2135 mqiobase_exit: 2136 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2137 "MSIX Count: %d.\n", ha->msix_count); 2138 return 0; 2139 2140 iospace_error_exit: 2141 return -ENOMEM; 2142 } 2143 2144 static struct isp_operations qla2100_isp_ops = { 2145 .pci_config = qla2100_pci_config, 2146 .reset_chip = qla2x00_reset_chip, 2147 .chip_diag = qla2x00_chip_diag, 2148 .config_rings = qla2x00_config_rings, 2149 .reset_adapter = qla2x00_reset_adapter, 2150 .nvram_config = qla2x00_nvram_config, 2151 .update_fw_options = qla2x00_update_fw_options, 2152 .load_risc = qla2x00_load_risc, 2153 .pci_info_str = qla2x00_pci_info_str, 2154 .fw_version_str = qla2x00_fw_version_str, 2155 .intr_handler = qla2100_intr_handler, 2156 .enable_intrs = qla2x00_enable_intrs, 2157 .disable_intrs = qla2x00_disable_intrs, 2158 .abort_command = qla2x00_abort_command, 2159 .target_reset = qla2x00_abort_target, 2160 .lun_reset = qla2x00_lun_reset, 2161 .fabric_login = qla2x00_login_fabric, 2162 .fabric_logout = qla2x00_fabric_logout, 2163 .calc_req_entries = qla2x00_calc_iocbs_32, 2164 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2165 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2166 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2167 .read_nvram = qla2x00_read_nvram_data, 2168 .write_nvram = qla2x00_write_nvram_data, 2169 .fw_dump = qla2100_fw_dump, 2170 .beacon_on = NULL, 2171 .beacon_off = NULL, 2172 .beacon_blink = NULL, 2173 .read_optrom = qla2x00_read_optrom_data, 2174 .write_optrom = qla2x00_write_optrom_data, 2175 .get_flash_version = qla2x00_get_flash_version, 2176 .start_scsi = qla2x00_start_scsi, 2177 .start_scsi_mq = NULL, 2178 .abort_isp = qla2x00_abort_isp, 2179 .iospace_config = qla2x00_iospace_config, 2180 .initialize_adapter = qla2x00_initialize_adapter, 2181 }; 2182 2183 static struct isp_operations qla2300_isp_ops = { 2184 .pci_config = qla2300_pci_config, 2185 .reset_chip = qla2x00_reset_chip, 2186 .chip_diag = qla2x00_chip_diag, 2187 .config_rings = qla2x00_config_rings, 2188 .reset_adapter = qla2x00_reset_adapter, 2189 .nvram_config = qla2x00_nvram_config, 2190 .update_fw_options = qla2x00_update_fw_options, 2191 .load_risc = qla2x00_load_risc, 2192 .pci_info_str = qla2x00_pci_info_str, 2193 .fw_version_str = qla2x00_fw_version_str, 2194 .intr_handler = qla2300_intr_handler, 2195 .enable_intrs = qla2x00_enable_intrs, 2196 .disable_intrs = qla2x00_disable_intrs, 2197 .abort_command = qla2x00_abort_command, 2198 .target_reset = qla2x00_abort_target, 2199 .lun_reset = qla2x00_lun_reset, 2200 .fabric_login = qla2x00_login_fabric, 2201 .fabric_logout = qla2x00_fabric_logout, 2202 .calc_req_entries = qla2x00_calc_iocbs_32, 2203 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2204 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2205 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2206 .read_nvram = qla2x00_read_nvram_data, 2207 .write_nvram = qla2x00_write_nvram_data, 2208 .fw_dump = qla2300_fw_dump, 2209 .beacon_on = qla2x00_beacon_on, 2210 .beacon_off = qla2x00_beacon_off, 2211 .beacon_blink = qla2x00_beacon_blink, 2212 .read_optrom = qla2x00_read_optrom_data, 2213 .write_optrom = qla2x00_write_optrom_data, 2214 .get_flash_version = qla2x00_get_flash_version, 2215 .start_scsi = qla2x00_start_scsi, 2216 .start_scsi_mq = NULL, 2217 .abort_isp = qla2x00_abort_isp, 2218 .iospace_config = qla2x00_iospace_config, 2219 .initialize_adapter = qla2x00_initialize_adapter, 2220 }; 2221 2222 static struct isp_operations qla24xx_isp_ops = { 2223 .pci_config = qla24xx_pci_config, 2224 .reset_chip = qla24xx_reset_chip, 2225 .chip_diag = qla24xx_chip_diag, 2226 .config_rings = qla24xx_config_rings, 2227 .reset_adapter = qla24xx_reset_adapter, 2228 .nvram_config = qla24xx_nvram_config, 2229 .update_fw_options = qla24xx_update_fw_options, 2230 .load_risc = qla24xx_load_risc, 2231 .pci_info_str = qla24xx_pci_info_str, 2232 .fw_version_str = qla24xx_fw_version_str, 2233 .intr_handler = qla24xx_intr_handler, 2234 .enable_intrs = qla24xx_enable_intrs, 2235 .disable_intrs = qla24xx_disable_intrs, 2236 .abort_command = qla24xx_abort_command, 2237 .target_reset = qla24xx_abort_target, 2238 .lun_reset = qla24xx_lun_reset, 2239 .fabric_login = qla24xx_login_fabric, 2240 .fabric_logout = qla24xx_fabric_logout, 2241 .calc_req_entries = NULL, 2242 .build_iocbs = NULL, 2243 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2244 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2245 .read_nvram = qla24xx_read_nvram_data, 2246 .write_nvram = qla24xx_write_nvram_data, 2247 .fw_dump = qla24xx_fw_dump, 2248 .beacon_on = qla24xx_beacon_on, 2249 .beacon_off = qla24xx_beacon_off, 2250 .beacon_blink = qla24xx_beacon_blink, 2251 .read_optrom = qla24xx_read_optrom_data, 2252 .write_optrom = qla24xx_write_optrom_data, 2253 .get_flash_version = qla24xx_get_flash_version, 2254 .start_scsi = qla24xx_start_scsi, 2255 .start_scsi_mq = NULL, 2256 .abort_isp = qla2x00_abort_isp, 2257 .iospace_config = qla2x00_iospace_config, 2258 .initialize_adapter = qla2x00_initialize_adapter, 2259 }; 2260 2261 static struct isp_operations qla25xx_isp_ops = { 2262 .pci_config = qla25xx_pci_config, 2263 .reset_chip = qla24xx_reset_chip, 2264 .chip_diag = qla24xx_chip_diag, 2265 .config_rings = qla24xx_config_rings, 2266 .reset_adapter = qla24xx_reset_adapter, 2267 .nvram_config = qla24xx_nvram_config, 2268 .update_fw_options = qla24xx_update_fw_options, 2269 .load_risc = qla24xx_load_risc, 2270 .pci_info_str = qla24xx_pci_info_str, 2271 .fw_version_str = qla24xx_fw_version_str, 2272 .intr_handler = qla24xx_intr_handler, 2273 .enable_intrs = qla24xx_enable_intrs, 2274 .disable_intrs = qla24xx_disable_intrs, 2275 .abort_command = qla24xx_abort_command, 2276 .target_reset = qla24xx_abort_target, 2277 .lun_reset = qla24xx_lun_reset, 2278 .fabric_login = qla24xx_login_fabric, 2279 .fabric_logout = qla24xx_fabric_logout, 2280 .calc_req_entries = NULL, 2281 .build_iocbs = NULL, 2282 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2283 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2284 .read_nvram = qla25xx_read_nvram_data, 2285 .write_nvram = qla25xx_write_nvram_data, 2286 .fw_dump = qla25xx_fw_dump, 2287 .beacon_on = qla24xx_beacon_on, 2288 .beacon_off = qla24xx_beacon_off, 2289 .beacon_blink = qla24xx_beacon_blink, 2290 .read_optrom = qla25xx_read_optrom_data, 2291 .write_optrom = qla24xx_write_optrom_data, 2292 .get_flash_version = qla24xx_get_flash_version, 2293 .start_scsi = qla24xx_dif_start_scsi, 2294 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2295 .abort_isp = qla2x00_abort_isp, 2296 .iospace_config = qla2x00_iospace_config, 2297 .initialize_adapter = qla2x00_initialize_adapter, 2298 }; 2299 2300 static struct isp_operations qla81xx_isp_ops = { 2301 .pci_config = qla25xx_pci_config, 2302 .reset_chip = qla24xx_reset_chip, 2303 .chip_diag = qla24xx_chip_diag, 2304 .config_rings = qla24xx_config_rings, 2305 .reset_adapter = qla24xx_reset_adapter, 2306 .nvram_config = qla81xx_nvram_config, 2307 .update_fw_options = qla24xx_update_fw_options, 2308 .load_risc = qla81xx_load_risc, 2309 .pci_info_str = qla24xx_pci_info_str, 2310 .fw_version_str = qla24xx_fw_version_str, 2311 .intr_handler = qla24xx_intr_handler, 2312 .enable_intrs = qla24xx_enable_intrs, 2313 .disable_intrs = qla24xx_disable_intrs, 2314 .abort_command = qla24xx_abort_command, 2315 .target_reset = qla24xx_abort_target, 2316 .lun_reset = qla24xx_lun_reset, 2317 .fabric_login = qla24xx_login_fabric, 2318 .fabric_logout = qla24xx_fabric_logout, 2319 .calc_req_entries = NULL, 2320 .build_iocbs = NULL, 2321 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2322 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2323 .read_nvram = NULL, 2324 .write_nvram = NULL, 2325 .fw_dump = qla81xx_fw_dump, 2326 .beacon_on = qla24xx_beacon_on, 2327 .beacon_off = qla24xx_beacon_off, 2328 .beacon_blink = qla83xx_beacon_blink, 2329 .read_optrom = qla25xx_read_optrom_data, 2330 .write_optrom = qla24xx_write_optrom_data, 2331 .get_flash_version = qla24xx_get_flash_version, 2332 .start_scsi = qla24xx_dif_start_scsi, 2333 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2334 .abort_isp = qla2x00_abort_isp, 2335 .iospace_config = qla2x00_iospace_config, 2336 .initialize_adapter = qla2x00_initialize_adapter, 2337 }; 2338 2339 static struct isp_operations qla82xx_isp_ops = { 2340 .pci_config = qla82xx_pci_config, 2341 .reset_chip = qla82xx_reset_chip, 2342 .chip_diag = qla24xx_chip_diag, 2343 .config_rings = qla82xx_config_rings, 2344 .reset_adapter = qla24xx_reset_adapter, 2345 .nvram_config = qla81xx_nvram_config, 2346 .update_fw_options = qla24xx_update_fw_options, 2347 .load_risc = qla82xx_load_risc, 2348 .pci_info_str = qla24xx_pci_info_str, 2349 .fw_version_str = qla24xx_fw_version_str, 2350 .intr_handler = qla82xx_intr_handler, 2351 .enable_intrs = qla82xx_enable_intrs, 2352 .disable_intrs = qla82xx_disable_intrs, 2353 .abort_command = qla24xx_abort_command, 2354 .target_reset = qla24xx_abort_target, 2355 .lun_reset = qla24xx_lun_reset, 2356 .fabric_login = qla24xx_login_fabric, 2357 .fabric_logout = qla24xx_fabric_logout, 2358 .calc_req_entries = NULL, 2359 .build_iocbs = NULL, 2360 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2361 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2362 .read_nvram = qla24xx_read_nvram_data, 2363 .write_nvram = qla24xx_write_nvram_data, 2364 .fw_dump = qla82xx_fw_dump, 2365 .beacon_on = qla82xx_beacon_on, 2366 .beacon_off = qla82xx_beacon_off, 2367 .beacon_blink = NULL, 2368 .read_optrom = qla82xx_read_optrom_data, 2369 .write_optrom = qla82xx_write_optrom_data, 2370 .get_flash_version = qla82xx_get_flash_version, 2371 .start_scsi = qla82xx_start_scsi, 2372 .start_scsi_mq = NULL, 2373 .abort_isp = qla82xx_abort_isp, 2374 .iospace_config = qla82xx_iospace_config, 2375 .initialize_adapter = qla2x00_initialize_adapter, 2376 }; 2377 2378 static struct isp_operations qla8044_isp_ops = { 2379 .pci_config = qla82xx_pci_config, 2380 .reset_chip = qla82xx_reset_chip, 2381 .chip_diag = qla24xx_chip_diag, 2382 .config_rings = qla82xx_config_rings, 2383 .reset_adapter = qla24xx_reset_adapter, 2384 .nvram_config = qla81xx_nvram_config, 2385 .update_fw_options = qla24xx_update_fw_options, 2386 .load_risc = qla82xx_load_risc, 2387 .pci_info_str = qla24xx_pci_info_str, 2388 .fw_version_str = qla24xx_fw_version_str, 2389 .intr_handler = qla8044_intr_handler, 2390 .enable_intrs = qla82xx_enable_intrs, 2391 .disable_intrs = qla82xx_disable_intrs, 2392 .abort_command = qla24xx_abort_command, 2393 .target_reset = qla24xx_abort_target, 2394 .lun_reset = qla24xx_lun_reset, 2395 .fabric_login = qla24xx_login_fabric, 2396 .fabric_logout = qla24xx_fabric_logout, 2397 .calc_req_entries = NULL, 2398 .build_iocbs = NULL, 2399 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2400 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2401 .read_nvram = NULL, 2402 .write_nvram = NULL, 2403 .fw_dump = qla8044_fw_dump, 2404 .beacon_on = qla82xx_beacon_on, 2405 .beacon_off = qla82xx_beacon_off, 2406 .beacon_blink = NULL, 2407 .read_optrom = qla8044_read_optrom_data, 2408 .write_optrom = qla8044_write_optrom_data, 2409 .get_flash_version = qla82xx_get_flash_version, 2410 .start_scsi = qla82xx_start_scsi, 2411 .start_scsi_mq = NULL, 2412 .abort_isp = qla8044_abort_isp, 2413 .iospace_config = qla82xx_iospace_config, 2414 .initialize_adapter = qla2x00_initialize_adapter, 2415 }; 2416 2417 static struct isp_operations qla83xx_isp_ops = { 2418 .pci_config = qla25xx_pci_config, 2419 .reset_chip = qla24xx_reset_chip, 2420 .chip_diag = qla24xx_chip_diag, 2421 .config_rings = qla24xx_config_rings, 2422 .reset_adapter = qla24xx_reset_adapter, 2423 .nvram_config = qla81xx_nvram_config, 2424 .update_fw_options = qla24xx_update_fw_options, 2425 .load_risc = qla81xx_load_risc, 2426 .pci_info_str = qla24xx_pci_info_str, 2427 .fw_version_str = qla24xx_fw_version_str, 2428 .intr_handler = qla24xx_intr_handler, 2429 .enable_intrs = qla24xx_enable_intrs, 2430 .disable_intrs = qla24xx_disable_intrs, 2431 .abort_command = qla24xx_abort_command, 2432 .target_reset = qla24xx_abort_target, 2433 .lun_reset = qla24xx_lun_reset, 2434 .fabric_login = qla24xx_login_fabric, 2435 .fabric_logout = qla24xx_fabric_logout, 2436 .calc_req_entries = NULL, 2437 .build_iocbs = NULL, 2438 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2439 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2440 .read_nvram = NULL, 2441 .write_nvram = NULL, 2442 .fw_dump = qla83xx_fw_dump, 2443 .beacon_on = qla24xx_beacon_on, 2444 .beacon_off = qla24xx_beacon_off, 2445 .beacon_blink = qla83xx_beacon_blink, 2446 .read_optrom = qla25xx_read_optrom_data, 2447 .write_optrom = qla24xx_write_optrom_data, 2448 .get_flash_version = qla24xx_get_flash_version, 2449 .start_scsi = qla24xx_dif_start_scsi, 2450 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2451 .abort_isp = qla2x00_abort_isp, 2452 .iospace_config = qla83xx_iospace_config, 2453 .initialize_adapter = qla2x00_initialize_adapter, 2454 }; 2455 2456 static struct isp_operations qlafx00_isp_ops = { 2457 .pci_config = qlafx00_pci_config, 2458 .reset_chip = qlafx00_soft_reset, 2459 .chip_diag = qlafx00_chip_diag, 2460 .config_rings = qlafx00_config_rings, 2461 .reset_adapter = qlafx00_soft_reset, 2462 .nvram_config = NULL, 2463 .update_fw_options = NULL, 2464 .load_risc = NULL, 2465 .pci_info_str = qlafx00_pci_info_str, 2466 .fw_version_str = qlafx00_fw_version_str, 2467 .intr_handler = qlafx00_intr_handler, 2468 .enable_intrs = qlafx00_enable_intrs, 2469 .disable_intrs = qlafx00_disable_intrs, 2470 .abort_command = qla24xx_async_abort_command, 2471 .target_reset = qlafx00_abort_target, 2472 .lun_reset = qlafx00_lun_reset, 2473 .fabric_login = NULL, 2474 .fabric_logout = NULL, 2475 .calc_req_entries = NULL, 2476 .build_iocbs = NULL, 2477 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2478 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2479 .read_nvram = qla24xx_read_nvram_data, 2480 .write_nvram = qla24xx_write_nvram_data, 2481 .fw_dump = NULL, 2482 .beacon_on = qla24xx_beacon_on, 2483 .beacon_off = qla24xx_beacon_off, 2484 .beacon_blink = NULL, 2485 .read_optrom = qla24xx_read_optrom_data, 2486 .write_optrom = qla24xx_write_optrom_data, 2487 .get_flash_version = qla24xx_get_flash_version, 2488 .start_scsi = qlafx00_start_scsi, 2489 .start_scsi_mq = NULL, 2490 .abort_isp = qlafx00_abort_isp, 2491 .iospace_config = qlafx00_iospace_config, 2492 .initialize_adapter = qlafx00_initialize_adapter, 2493 }; 2494 2495 static struct isp_operations qla27xx_isp_ops = { 2496 .pci_config = qla25xx_pci_config, 2497 .reset_chip = qla24xx_reset_chip, 2498 .chip_diag = qla24xx_chip_diag, 2499 .config_rings = qla24xx_config_rings, 2500 .reset_adapter = qla24xx_reset_adapter, 2501 .nvram_config = qla81xx_nvram_config, 2502 .update_fw_options = qla24xx_update_fw_options, 2503 .load_risc = qla81xx_load_risc, 2504 .pci_info_str = qla24xx_pci_info_str, 2505 .fw_version_str = qla24xx_fw_version_str, 2506 .intr_handler = qla24xx_intr_handler, 2507 .enable_intrs = qla24xx_enable_intrs, 2508 .disable_intrs = qla24xx_disable_intrs, 2509 .abort_command = qla24xx_abort_command, 2510 .target_reset = qla24xx_abort_target, 2511 .lun_reset = qla24xx_lun_reset, 2512 .fabric_login = qla24xx_login_fabric, 2513 .fabric_logout = qla24xx_fabric_logout, 2514 .calc_req_entries = NULL, 2515 .build_iocbs = NULL, 2516 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2517 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2518 .read_nvram = NULL, 2519 .write_nvram = NULL, 2520 .fw_dump = qla27xx_fwdump, 2521 .beacon_on = qla24xx_beacon_on, 2522 .beacon_off = qla24xx_beacon_off, 2523 .beacon_blink = qla83xx_beacon_blink, 2524 .read_optrom = qla25xx_read_optrom_data, 2525 .write_optrom = qla24xx_write_optrom_data, 2526 .get_flash_version = qla24xx_get_flash_version, 2527 .start_scsi = qla24xx_dif_start_scsi, 2528 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2529 .abort_isp = qla2x00_abort_isp, 2530 .iospace_config = qla83xx_iospace_config, 2531 .initialize_adapter = qla2x00_initialize_adapter, 2532 }; 2533 2534 static inline void 2535 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2536 { 2537 ha->device_type = DT_EXTENDED_IDS; 2538 switch (ha->pdev->device) { 2539 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2540 ha->isp_type |= DT_ISP2100; 2541 ha->device_type &= ~DT_EXTENDED_IDS; 2542 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2543 break; 2544 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2545 ha->isp_type |= DT_ISP2200; 2546 ha->device_type &= ~DT_EXTENDED_IDS; 2547 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2548 break; 2549 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2550 ha->isp_type |= DT_ISP2300; 2551 ha->device_type |= DT_ZIO_SUPPORTED; 2552 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2553 break; 2554 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2555 ha->isp_type |= DT_ISP2312; 2556 ha->device_type |= DT_ZIO_SUPPORTED; 2557 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2558 break; 2559 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2560 ha->isp_type |= DT_ISP2322; 2561 ha->device_type |= DT_ZIO_SUPPORTED; 2562 if (ha->pdev->subsystem_vendor == 0x1028 && 2563 ha->pdev->subsystem_device == 0x0170) 2564 ha->device_type |= DT_OEM_001; 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2566 break; 2567 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2568 ha->isp_type |= DT_ISP6312; 2569 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2570 break; 2571 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2572 ha->isp_type |= DT_ISP6322; 2573 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2574 break; 2575 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2576 ha->isp_type |= DT_ISP2422; 2577 ha->device_type |= DT_ZIO_SUPPORTED; 2578 ha->device_type |= DT_FWI2; 2579 ha->device_type |= DT_IIDMA; 2580 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2581 break; 2582 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2583 ha->isp_type |= DT_ISP2432; 2584 ha->device_type |= DT_ZIO_SUPPORTED; 2585 ha->device_type |= DT_FWI2; 2586 ha->device_type |= DT_IIDMA; 2587 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2588 break; 2589 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2590 ha->isp_type |= DT_ISP8432; 2591 ha->device_type |= DT_ZIO_SUPPORTED; 2592 ha->device_type |= DT_FWI2; 2593 ha->device_type |= DT_IIDMA; 2594 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2595 break; 2596 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2597 ha->isp_type |= DT_ISP5422; 2598 ha->device_type |= DT_FWI2; 2599 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2600 break; 2601 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2602 ha->isp_type |= DT_ISP5432; 2603 ha->device_type |= DT_FWI2; 2604 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2605 break; 2606 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2607 ha->isp_type |= DT_ISP2532; 2608 ha->device_type |= DT_ZIO_SUPPORTED; 2609 ha->device_type |= DT_FWI2; 2610 ha->device_type |= DT_IIDMA; 2611 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2612 break; 2613 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2614 ha->isp_type |= DT_ISP8001; 2615 ha->device_type |= DT_ZIO_SUPPORTED; 2616 ha->device_type |= DT_FWI2; 2617 ha->device_type |= DT_IIDMA; 2618 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2619 break; 2620 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2621 ha->isp_type |= DT_ISP8021; 2622 ha->device_type |= DT_ZIO_SUPPORTED; 2623 ha->device_type |= DT_FWI2; 2624 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2625 /* Initialize 82XX ISP flags */ 2626 qla82xx_init_flags(ha); 2627 break; 2628 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2629 ha->isp_type |= DT_ISP8044; 2630 ha->device_type |= DT_ZIO_SUPPORTED; 2631 ha->device_type |= DT_FWI2; 2632 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2633 /* Initialize 82XX ISP flags */ 2634 qla82xx_init_flags(ha); 2635 break; 2636 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2637 ha->isp_type |= DT_ISP2031; 2638 ha->device_type |= DT_ZIO_SUPPORTED; 2639 ha->device_type |= DT_FWI2; 2640 ha->device_type |= DT_IIDMA; 2641 ha->device_type |= DT_T10_PI; 2642 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2643 break; 2644 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2645 ha->isp_type |= DT_ISP8031; 2646 ha->device_type |= DT_ZIO_SUPPORTED; 2647 ha->device_type |= DT_FWI2; 2648 ha->device_type |= DT_IIDMA; 2649 ha->device_type |= DT_T10_PI; 2650 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2651 break; 2652 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2653 ha->isp_type |= DT_ISPFX00; 2654 break; 2655 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2656 ha->isp_type |= DT_ISP2071; 2657 ha->device_type |= DT_ZIO_SUPPORTED; 2658 ha->device_type |= DT_FWI2; 2659 ha->device_type |= DT_IIDMA; 2660 ha->device_type |= DT_T10_PI; 2661 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2662 break; 2663 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2664 ha->isp_type |= DT_ISP2271; 2665 ha->device_type |= DT_ZIO_SUPPORTED; 2666 ha->device_type |= DT_FWI2; 2667 ha->device_type |= DT_IIDMA; 2668 ha->device_type |= DT_T10_PI; 2669 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2670 break; 2671 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2672 ha->isp_type |= DT_ISP2261; 2673 ha->device_type |= DT_ZIO_SUPPORTED; 2674 ha->device_type |= DT_FWI2; 2675 ha->device_type |= DT_IIDMA; 2676 ha->device_type |= DT_T10_PI; 2677 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2678 break; 2679 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2680 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2681 ha->isp_type |= DT_ISP2081; 2682 ha->device_type |= DT_ZIO_SUPPORTED; 2683 ha->device_type |= DT_FWI2; 2684 ha->device_type |= DT_IIDMA; 2685 ha->device_type |= DT_T10_PI; 2686 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2687 break; 2688 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2689 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2690 ha->isp_type |= DT_ISP2281; 2691 ha->device_type |= DT_ZIO_SUPPORTED; 2692 ha->device_type |= DT_FWI2; 2693 ha->device_type |= DT_IIDMA; 2694 ha->device_type |= DT_T10_PI; 2695 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2696 break; 2697 } 2698 2699 if (IS_QLA82XX(ha)) 2700 ha->port_no = ha->portnum & 1; 2701 else { 2702 /* Get adapter physical port no from interrupt pin register. */ 2703 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2704 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2705 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2706 ha->port_no--; 2707 else 2708 ha->port_no = !(ha->port_no & 1); 2709 } 2710 2711 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2712 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2713 ha->device_type, ha->port_no, ha->fw_srisc_address); 2714 } 2715 2716 static void 2717 qla2xxx_scan_start(struct Scsi_Host *shost) 2718 { 2719 scsi_qla_host_t *vha = shost_priv(shost); 2720 2721 if (vha->hw->flags.running_gold_fw) 2722 return; 2723 2724 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2725 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2726 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2727 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2728 } 2729 2730 static int 2731 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2732 { 2733 scsi_qla_host_t *vha = shost_priv(shost); 2734 2735 if (test_bit(UNLOADING, &vha->dpc_flags)) 2736 return 1; 2737 if (!vha->host) 2738 return 1; 2739 if (time > vha->hw->loop_reset_delay * HZ) 2740 return 1; 2741 2742 return atomic_read(&vha->loop_state) == LOOP_READY; 2743 } 2744 2745 static void qla2x00_iocb_work_fn(struct work_struct *work) 2746 { 2747 struct scsi_qla_host *vha = container_of(work, 2748 struct scsi_qla_host, iocb_work); 2749 struct qla_hw_data *ha = vha->hw; 2750 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2751 int i = 2; 2752 unsigned long flags; 2753 2754 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2755 return; 2756 2757 while (!list_empty(&vha->work_list) && i > 0) { 2758 qla2x00_do_work(vha); 2759 i--; 2760 } 2761 2762 spin_lock_irqsave(&vha->work_lock, flags); 2763 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2764 spin_unlock_irqrestore(&vha->work_lock, flags); 2765 } 2766 2767 /* 2768 * PCI driver interface 2769 */ 2770 static int 2771 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2772 { 2773 int ret = -ENODEV; 2774 struct Scsi_Host *host; 2775 scsi_qla_host_t *base_vha = NULL; 2776 struct qla_hw_data *ha; 2777 char pci_info[30]; 2778 char fw_str[30], wq_name[30]; 2779 struct scsi_host_template *sht; 2780 int bars, mem_only = 0; 2781 uint16_t req_length = 0, rsp_length = 0; 2782 struct req_que *req = NULL; 2783 struct rsp_que *rsp = NULL; 2784 int i; 2785 2786 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2787 sht = &qla2xxx_driver_template; 2788 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2789 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2790 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2791 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2792 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2793 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2794 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2795 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2796 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2797 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2798 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2799 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2800 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2801 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2802 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2803 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2804 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2805 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2806 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2807 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2808 mem_only = 1; 2809 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2810 "Mem only adapter.\n"); 2811 } 2812 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2813 "Bars=%d.\n", bars); 2814 2815 if (mem_only) { 2816 if (pci_enable_device_mem(pdev)) 2817 return ret; 2818 } else { 2819 if (pci_enable_device(pdev)) 2820 return ret; 2821 } 2822 2823 /* This may fail but that's ok */ 2824 pci_enable_pcie_error_reporting(pdev); 2825 2826 /* Turn off T10-DIF when FC-NVMe is enabled */ 2827 if (ql2xnvmeenable) 2828 ql2xenabledif = 0; 2829 2830 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2831 if (!ha) { 2832 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2833 "Unable to allocate memory for ha.\n"); 2834 goto disable_device; 2835 } 2836 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2837 "Memory allocated for ha=%p.\n", ha); 2838 ha->pdev = pdev; 2839 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2840 spin_lock_init(&ha->tgt.q_full_lock); 2841 spin_lock_init(&ha->tgt.sess_lock); 2842 spin_lock_init(&ha->tgt.atio_lock); 2843 2844 atomic_set(&ha->nvme_active_aen_cnt, 0); 2845 2846 /* Clear our data area */ 2847 ha->bars = bars; 2848 ha->mem_only = mem_only; 2849 spin_lock_init(&ha->hardware_lock); 2850 spin_lock_init(&ha->vport_slock); 2851 mutex_init(&ha->selflogin_lock); 2852 mutex_init(&ha->optrom_mutex); 2853 2854 /* Set ISP-type information. */ 2855 qla2x00_set_isp_flags(ha); 2856 2857 /* Set EEH reset type to fundamental if required by hba */ 2858 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2859 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2860 pdev->needs_freset = 1; 2861 2862 ha->prev_topology = 0; 2863 ha->init_cb_size = sizeof(init_cb_t); 2864 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2865 ha->optrom_size = OPTROM_SIZE_2300; 2866 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2867 atomic_set(&ha->num_pend_mbx_stage1, 0); 2868 atomic_set(&ha->num_pend_mbx_stage2, 0); 2869 atomic_set(&ha->num_pend_mbx_stage3, 0); 2870 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2871 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2872 2873 /* Assign ISP specific operations. */ 2874 if (IS_QLA2100(ha)) { 2875 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2876 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2877 req_length = REQUEST_ENTRY_CNT_2100; 2878 rsp_length = RESPONSE_ENTRY_CNT_2100; 2879 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2880 ha->gid_list_info_size = 4; 2881 ha->flash_conf_off = ~0; 2882 ha->flash_data_off = ~0; 2883 ha->nvram_conf_off = ~0; 2884 ha->nvram_data_off = ~0; 2885 ha->isp_ops = &qla2100_isp_ops; 2886 } else if (IS_QLA2200(ha)) { 2887 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2888 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2889 req_length = REQUEST_ENTRY_CNT_2200; 2890 rsp_length = RESPONSE_ENTRY_CNT_2100; 2891 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2892 ha->gid_list_info_size = 4; 2893 ha->flash_conf_off = ~0; 2894 ha->flash_data_off = ~0; 2895 ha->nvram_conf_off = ~0; 2896 ha->nvram_data_off = ~0; 2897 ha->isp_ops = &qla2100_isp_ops; 2898 } else if (IS_QLA23XX(ha)) { 2899 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2900 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2901 req_length = REQUEST_ENTRY_CNT_2200; 2902 rsp_length = RESPONSE_ENTRY_CNT_2300; 2903 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2904 ha->gid_list_info_size = 6; 2905 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2906 ha->optrom_size = OPTROM_SIZE_2322; 2907 ha->flash_conf_off = ~0; 2908 ha->flash_data_off = ~0; 2909 ha->nvram_conf_off = ~0; 2910 ha->nvram_data_off = ~0; 2911 ha->isp_ops = &qla2300_isp_ops; 2912 } else if (IS_QLA24XX_TYPE(ha)) { 2913 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2914 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2915 req_length = REQUEST_ENTRY_CNT_24XX; 2916 rsp_length = RESPONSE_ENTRY_CNT_2300; 2917 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2918 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2919 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2920 ha->gid_list_info_size = 8; 2921 ha->optrom_size = OPTROM_SIZE_24XX; 2922 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2923 ha->isp_ops = &qla24xx_isp_ops; 2924 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2925 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2926 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2927 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2928 } else if (IS_QLA25XX(ha)) { 2929 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2930 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2931 req_length = REQUEST_ENTRY_CNT_24XX; 2932 rsp_length = RESPONSE_ENTRY_CNT_2300; 2933 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2934 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2935 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2936 ha->gid_list_info_size = 8; 2937 ha->optrom_size = OPTROM_SIZE_25XX; 2938 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2939 ha->isp_ops = &qla25xx_isp_ops; 2940 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2941 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2942 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2943 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2944 } else if (IS_QLA81XX(ha)) { 2945 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2946 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2947 req_length = REQUEST_ENTRY_CNT_24XX; 2948 rsp_length = RESPONSE_ENTRY_CNT_2300; 2949 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2950 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2951 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2952 ha->gid_list_info_size = 8; 2953 ha->optrom_size = OPTROM_SIZE_81XX; 2954 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2955 ha->isp_ops = &qla81xx_isp_ops; 2956 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2957 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2958 ha->nvram_conf_off = ~0; 2959 ha->nvram_data_off = ~0; 2960 } else if (IS_QLA82XX(ha)) { 2961 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2962 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2963 req_length = REQUEST_ENTRY_CNT_82XX; 2964 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2965 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2966 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2967 ha->gid_list_info_size = 8; 2968 ha->optrom_size = OPTROM_SIZE_82XX; 2969 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2970 ha->isp_ops = &qla82xx_isp_ops; 2971 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2972 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2973 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2974 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2975 } else if (IS_QLA8044(ha)) { 2976 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2977 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2978 req_length = REQUEST_ENTRY_CNT_82XX; 2979 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2980 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2981 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2982 ha->gid_list_info_size = 8; 2983 ha->optrom_size = OPTROM_SIZE_83XX; 2984 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2985 ha->isp_ops = &qla8044_isp_ops; 2986 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2987 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2988 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2989 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2990 } else if (IS_QLA83XX(ha)) { 2991 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2992 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2993 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2994 req_length = REQUEST_ENTRY_CNT_83XX; 2995 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2996 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2997 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2998 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2999 ha->gid_list_info_size = 8; 3000 ha->optrom_size = OPTROM_SIZE_83XX; 3001 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3002 ha->isp_ops = &qla83xx_isp_ops; 3003 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3004 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3005 ha->nvram_conf_off = ~0; 3006 ha->nvram_data_off = ~0; 3007 } else if (IS_QLAFX00(ha)) { 3008 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3009 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3010 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3011 req_length = REQUEST_ENTRY_CNT_FX00; 3012 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3013 ha->isp_ops = &qlafx00_isp_ops; 3014 ha->port_down_retry_count = 30; /* default value */ 3015 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3016 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3017 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3018 ha->mr.fw_hbt_en = 1; 3019 ha->mr.host_info_resend = false; 3020 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3021 } else if (IS_QLA27XX(ha)) { 3022 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3023 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3024 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3025 req_length = REQUEST_ENTRY_CNT_83XX; 3026 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3027 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3028 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3029 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3030 ha->gid_list_info_size = 8; 3031 ha->optrom_size = OPTROM_SIZE_83XX; 3032 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3033 ha->isp_ops = &qla27xx_isp_ops; 3034 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3035 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3036 ha->nvram_conf_off = ~0; 3037 ha->nvram_data_off = ~0; 3038 } else if (IS_QLA28XX(ha)) { 3039 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3040 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3041 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3042 req_length = REQUEST_ENTRY_CNT_24XX; 3043 rsp_length = RESPONSE_ENTRY_CNT_2300; 3044 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3045 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3046 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3047 ha->gid_list_info_size = 8; 3048 ha->optrom_size = OPTROM_SIZE_28XX; 3049 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3050 ha->isp_ops = &qla27xx_isp_ops; 3051 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3052 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3053 ha->nvram_conf_off = ~0; 3054 ha->nvram_data_off = ~0; 3055 } 3056 3057 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3058 "mbx_count=%d, req_length=%d, " 3059 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3060 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3061 "max_fibre_devices=%d.\n", 3062 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3063 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3064 ha->nvram_npiv_size, ha->max_fibre_devices); 3065 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3066 "isp_ops=%p, flash_conf_off=%d, " 3067 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3068 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3069 ha->nvram_conf_off, ha->nvram_data_off); 3070 3071 /* Configure PCI I/O space */ 3072 ret = ha->isp_ops->iospace_config(ha); 3073 if (ret) 3074 goto iospace_config_failed; 3075 3076 ql_log_pci(ql_log_info, pdev, 0x001d, 3077 "Found an ISP%04X irq %d iobase 0x%p.\n", 3078 pdev->device, pdev->irq, ha->iobase); 3079 mutex_init(&ha->vport_lock); 3080 mutex_init(&ha->mq_lock); 3081 init_completion(&ha->mbx_cmd_comp); 3082 complete(&ha->mbx_cmd_comp); 3083 init_completion(&ha->mbx_intr_comp); 3084 init_completion(&ha->dcbx_comp); 3085 init_completion(&ha->lb_portup_comp); 3086 3087 set_bit(0, (unsigned long *) ha->vp_idx_map); 3088 3089 qla2x00_config_dma_addressing(ha); 3090 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3091 "64 Bit addressing is %s.\n", 3092 ha->flags.enable_64bit_addressing ? "enable" : 3093 "disable"); 3094 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3095 if (ret) { 3096 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3097 "Failed to allocate memory for adapter, aborting.\n"); 3098 3099 goto probe_hw_failed; 3100 } 3101 3102 req->max_q_depth = MAX_Q_DEPTH; 3103 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3104 req->max_q_depth = ql2xmaxqdepth; 3105 3106 3107 base_vha = qla2x00_create_host(sht, ha); 3108 if (!base_vha) { 3109 ret = -ENOMEM; 3110 goto probe_hw_failed; 3111 } 3112 3113 pci_set_drvdata(pdev, base_vha); 3114 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3115 3116 host = base_vha->host; 3117 base_vha->req = req; 3118 if (IS_QLA2XXX_MIDTYPE(ha)) 3119 base_vha->mgmt_svr_loop_id = 3120 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3121 else 3122 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3123 base_vha->vp_idx; 3124 3125 /* Setup fcport template structure. */ 3126 ha->mr.fcport.vha = base_vha; 3127 ha->mr.fcport.port_type = FCT_UNKNOWN; 3128 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3129 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3130 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3131 ha->mr.fcport.scan_state = 1; 3132 3133 /* Set the SG table size based on ISP type */ 3134 if (!IS_FWI2_CAPABLE(ha)) { 3135 if (IS_QLA2100(ha)) 3136 host->sg_tablesize = 32; 3137 } else { 3138 if (!IS_QLA82XX(ha)) 3139 host->sg_tablesize = QLA_SG_ALL; 3140 } 3141 host->max_id = ha->max_fibre_devices; 3142 host->cmd_per_lun = 3; 3143 host->unique_id = host->host_no; 3144 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3145 host->max_cmd_len = 32; 3146 else 3147 host->max_cmd_len = MAX_CMDSZ; 3148 host->max_channel = MAX_BUSES - 1; 3149 /* Older HBAs support only 16-bit LUNs */ 3150 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3151 ql2xmaxlun > 0xffff) 3152 host->max_lun = 0xffff; 3153 else 3154 host->max_lun = ql2xmaxlun; 3155 host->transportt = qla2xxx_transport_template; 3156 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3157 3158 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3159 "max_id=%d this_id=%d " 3160 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3161 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3162 host->this_id, host->cmd_per_lun, host->unique_id, 3163 host->max_cmd_len, host->max_channel, host->max_lun, 3164 host->transportt, sht->vendor_id); 3165 3166 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3167 3168 /* Set up the irqs */ 3169 ret = qla2x00_request_irqs(ha, rsp); 3170 if (ret) 3171 goto probe_failed; 3172 3173 /* Alloc arrays of request and response ring ptrs */ 3174 ret = qla2x00_alloc_queues(ha, req, rsp); 3175 if (ret) { 3176 ql_log(ql_log_fatal, base_vha, 0x003d, 3177 "Failed to allocate memory for queue pointers..." 3178 "aborting.\n"); 3179 ret = -ENODEV; 3180 goto probe_failed; 3181 } 3182 3183 if (ha->mqenable) { 3184 /* number of hardware queues supported by blk/scsi-mq*/ 3185 host->nr_hw_queues = ha->max_qpairs; 3186 3187 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3188 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3189 } else { 3190 if (ql2xnvmeenable) { 3191 host->nr_hw_queues = ha->max_qpairs; 3192 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3193 "FC-NVMe support is enabled, HW queues=%d\n", 3194 host->nr_hw_queues); 3195 } else { 3196 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3197 "blk/scsi-mq disabled.\n"); 3198 } 3199 } 3200 3201 qlt_probe_one_stage1(base_vha, ha); 3202 3203 pci_save_state(pdev); 3204 3205 /* Assign back pointers */ 3206 rsp->req = req; 3207 req->rsp = rsp; 3208 3209 if (IS_QLAFX00(ha)) { 3210 ha->rsp_q_map[0] = rsp; 3211 ha->req_q_map[0] = req; 3212 set_bit(0, ha->req_qid_map); 3213 set_bit(0, ha->rsp_qid_map); 3214 } 3215 3216 /* FWI2-capable only. */ 3217 req->req_q_in = &ha->iobase->isp24.req_q_in; 3218 req->req_q_out = &ha->iobase->isp24.req_q_out; 3219 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3220 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3221 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3222 IS_QLA28XX(ha)) { 3223 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3224 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3225 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3226 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3227 } 3228 3229 if (IS_QLAFX00(ha)) { 3230 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3231 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3232 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3233 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3234 } 3235 3236 if (IS_P3P_TYPE(ha)) { 3237 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3238 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3239 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3240 } 3241 3242 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3243 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3244 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3245 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3246 "req->req_q_in=%p req->req_q_out=%p " 3247 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3248 req->req_q_in, req->req_q_out, 3249 rsp->rsp_q_in, rsp->rsp_q_out); 3250 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3251 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3252 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3253 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3254 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3255 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3256 3257 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3258 if (unlikely(!ha->wq)) { 3259 ret = -ENOMEM; 3260 goto probe_failed; 3261 } 3262 3263 if (ha->isp_ops->initialize_adapter(base_vha)) { 3264 ql_log(ql_log_fatal, base_vha, 0x00d6, 3265 "Failed to initialize adapter - Adapter flags %x.\n", 3266 base_vha->device_flags); 3267 3268 if (IS_QLA82XX(ha)) { 3269 qla82xx_idc_lock(ha); 3270 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3271 QLA8XXX_DEV_FAILED); 3272 qla82xx_idc_unlock(ha); 3273 ql_log(ql_log_fatal, base_vha, 0x00d7, 3274 "HW State: FAILED.\n"); 3275 } else if (IS_QLA8044(ha)) { 3276 qla8044_idc_lock(ha); 3277 qla8044_wr_direct(base_vha, 3278 QLA8044_CRB_DEV_STATE_INDEX, 3279 QLA8XXX_DEV_FAILED); 3280 qla8044_idc_unlock(ha); 3281 ql_log(ql_log_fatal, base_vha, 0x0150, 3282 "HW State: FAILED.\n"); 3283 } 3284 3285 ret = -ENODEV; 3286 goto probe_failed; 3287 } 3288 3289 if (IS_QLAFX00(ha)) 3290 host->can_queue = QLAFX00_MAX_CANQUEUE; 3291 else 3292 host->can_queue = req->num_outstanding_cmds - 10; 3293 3294 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3295 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3296 host->can_queue, base_vha->req, 3297 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3298 3299 if (ha->mqenable) { 3300 bool startit = false; 3301 3302 if (QLA_TGT_MODE_ENABLED()) 3303 startit = false; 3304 3305 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3306 startit = true; 3307 3308 /* Create start of day qpairs for Block MQ */ 3309 for (i = 0; i < ha->max_qpairs; i++) 3310 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3311 } 3312 3313 if (ha->flags.running_gold_fw) 3314 goto skip_dpc; 3315 3316 /* 3317 * Startup the kernel thread for this host adapter 3318 */ 3319 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3320 "%s_dpc", base_vha->host_str); 3321 if (IS_ERR(ha->dpc_thread)) { 3322 ql_log(ql_log_fatal, base_vha, 0x00ed, 3323 "Failed to start DPC thread.\n"); 3324 ret = PTR_ERR(ha->dpc_thread); 3325 ha->dpc_thread = NULL; 3326 goto probe_failed; 3327 } 3328 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3329 "DPC thread started successfully.\n"); 3330 3331 /* 3332 * If we're not coming up in initiator mode, we might sit for 3333 * a while without waking up the dpc thread, which leads to a 3334 * stuck process warning. So just kick the dpc once here and 3335 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3336 */ 3337 qla2xxx_wake_dpc(base_vha); 3338 3339 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3340 3341 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3342 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3343 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3344 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3345 3346 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3347 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3348 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3349 INIT_WORK(&ha->idc_state_handler, 3350 qla83xx_idc_state_handler_work); 3351 INIT_WORK(&ha->nic_core_unrecoverable, 3352 qla83xx_nic_core_unrecoverable_work); 3353 } 3354 3355 skip_dpc: 3356 list_add_tail(&base_vha->list, &ha->vp_list); 3357 base_vha->host->irq = ha->pdev->irq; 3358 3359 /* Initialized the timer */ 3360 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3361 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3362 "Started qla2x00_timer with " 3363 "interval=%d.\n", WATCH_INTERVAL); 3364 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3365 "Detected hba at address=%p.\n", 3366 ha); 3367 3368 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3369 if (ha->fw_attributes & BIT_4) { 3370 int prot = 0, guard; 3371 3372 base_vha->flags.difdix_supported = 1; 3373 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3374 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3375 if (ql2xenabledif == 1) 3376 prot = SHOST_DIX_TYPE0_PROTECTION; 3377 if (ql2xprotmask) 3378 scsi_host_set_prot(host, ql2xprotmask); 3379 else 3380 scsi_host_set_prot(host, 3381 prot | SHOST_DIF_TYPE1_PROTECTION 3382 | SHOST_DIF_TYPE2_PROTECTION 3383 | SHOST_DIF_TYPE3_PROTECTION 3384 | SHOST_DIX_TYPE1_PROTECTION 3385 | SHOST_DIX_TYPE2_PROTECTION 3386 | SHOST_DIX_TYPE3_PROTECTION); 3387 3388 guard = SHOST_DIX_GUARD_CRC; 3389 3390 if (IS_PI_IPGUARD_CAPABLE(ha) && 3391 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3392 guard |= SHOST_DIX_GUARD_IP; 3393 3394 if (ql2xprotguard) 3395 scsi_host_set_guard(host, ql2xprotguard); 3396 else 3397 scsi_host_set_guard(host, guard); 3398 } else 3399 base_vha->flags.difdix_supported = 0; 3400 } 3401 3402 ha->isp_ops->enable_intrs(ha); 3403 3404 if (IS_QLAFX00(ha)) { 3405 ret = qlafx00_fx_disc(base_vha, 3406 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3407 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3408 QLA_SG_ALL : 128; 3409 } 3410 3411 ret = scsi_add_host(host, &pdev->dev); 3412 if (ret) 3413 goto probe_failed; 3414 3415 base_vha->flags.init_done = 1; 3416 base_vha->flags.online = 1; 3417 ha->prev_minidump_failed = 0; 3418 3419 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3420 "Init done and hba is online.\n"); 3421 3422 if (qla_ini_mode_enabled(base_vha) || 3423 qla_dual_mode_enabled(base_vha)) 3424 scsi_scan_host(host); 3425 else 3426 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3427 "skipping scsi_scan_host() for non-initiator port\n"); 3428 3429 qla2x00_alloc_sysfs_attr(base_vha); 3430 3431 if (IS_QLAFX00(ha)) { 3432 ret = qlafx00_fx_disc(base_vha, 3433 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3434 3435 /* Register system information */ 3436 ret = qlafx00_fx_disc(base_vha, 3437 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3438 } 3439 3440 qla2x00_init_host_attr(base_vha); 3441 3442 qla2x00_dfs_setup(base_vha); 3443 3444 ql_log(ql_log_info, base_vha, 0x00fb, 3445 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3446 ql_log(ql_log_info, base_vha, 0x00fc, 3447 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3448 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3449 sizeof(pci_info)), 3450 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3451 base_vha->host_no, 3452 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3453 3454 qlt_add_target(ha, base_vha); 3455 3456 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3457 3458 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3459 return -ENODEV; 3460 3461 return 0; 3462 3463 probe_failed: 3464 if (base_vha->gnl.l) { 3465 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3466 base_vha->gnl.l, base_vha->gnl.ldma); 3467 base_vha->gnl.l = NULL; 3468 } 3469 3470 if (base_vha->timer_active) 3471 qla2x00_stop_timer(base_vha); 3472 base_vha->flags.online = 0; 3473 if (ha->dpc_thread) { 3474 struct task_struct *t = ha->dpc_thread; 3475 3476 ha->dpc_thread = NULL; 3477 kthread_stop(t); 3478 } 3479 3480 qla2x00_free_device(base_vha); 3481 scsi_host_put(base_vha->host); 3482 /* 3483 * Need to NULL out local req/rsp after 3484 * qla2x00_free_device => qla2x00_free_queues frees 3485 * what these are pointing to. Or else we'll 3486 * fall over below in qla2x00_free_req/rsp_que. 3487 */ 3488 req = NULL; 3489 rsp = NULL; 3490 3491 probe_hw_failed: 3492 qla2x00_mem_free(ha); 3493 qla2x00_free_req_que(ha, req); 3494 qla2x00_free_rsp_que(ha, rsp); 3495 qla2x00_clear_drv_active(ha); 3496 3497 iospace_config_failed: 3498 if (IS_P3P_TYPE(ha)) { 3499 if (!ha->nx_pcibase) 3500 iounmap((device_reg_t *)ha->nx_pcibase); 3501 if (!ql2xdbwr) 3502 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3503 } else { 3504 if (ha->iobase) 3505 iounmap(ha->iobase); 3506 if (ha->cregbase) 3507 iounmap(ha->cregbase); 3508 } 3509 pci_release_selected_regions(ha->pdev, ha->bars); 3510 kfree(ha); 3511 3512 disable_device: 3513 pci_disable_device(pdev); 3514 return ret; 3515 } 3516 3517 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3518 { 3519 scsi_qla_host_t *vp; 3520 unsigned long flags; 3521 struct qla_hw_data *ha; 3522 3523 if (!base_vha) 3524 return; 3525 3526 ha = base_vha->hw; 3527 3528 spin_lock_irqsave(&ha->vport_slock, flags); 3529 list_for_each_entry(vp, &ha->vp_list, list) 3530 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3531 3532 /* 3533 * Indicate device removal to prevent future board_disable 3534 * and wait until any pending board_disable has completed. 3535 */ 3536 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3537 spin_unlock_irqrestore(&ha->vport_slock, flags); 3538 } 3539 3540 static void 3541 qla2x00_shutdown(struct pci_dev *pdev) 3542 { 3543 scsi_qla_host_t *vha; 3544 struct qla_hw_data *ha; 3545 3546 vha = pci_get_drvdata(pdev); 3547 ha = vha->hw; 3548 3549 ql_log(ql_log_info, vha, 0xfffa, 3550 "Adapter shutdown\n"); 3551 3552 /* 3553 * Prevent future board_disable and wait 3554 * until any pending board_disable has completed. 3555 */ 3556 __qla_set_remove_flag(vha); 3557 cancel_work_sync(&ha->board_disable); 3558 3559 if (!atomic_read(&pdev->enable_cnt)) 3560 return; 3561 3562 /* Notify ISPFX00 firmware */ 3563 if (IS_QLAFX00(ha)) 3564 qlafx00_driver_shutdown(vha, 20); 3565 3566 /* Turn-off FCE trace */ 3567 if (ha->flags.fce_enabled) { 3568 qla2x00_disable_fce_trace(vha, NULL, NULL); 3569 ha->flags.fce_enabled = 0; 3570 } 3571 3572 /* Turn-off EFT trace */ 3573 if (ha->eft) 3574 qla2x00_disable_eft_trace(vha); 3575 3576 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3577 IS_QLA28XX(ha)) { 3578 if (ha->flags.fw_started) 3579 qla2x00_abort_isp_cleanup(vha); 3580 } else { 3581 /* Stop currently executing firmware. */ 3582 qla2x00_try_to_stop_firmware(vha); 3583 } 3584 3585 /* Disable timer */ 3586 if (vha->timer_active) 3587 qla2x00_stop_timer(vha); 3588 3589 /* Turn adapter off line */ 3590 vha->flags.online = 0; 3591 3592 /* turn-off interrupts on the card */ 3593 if (ha->interrupts_on) { 3594 vha->flags.init_done = 0; 3595 ha->isp_ops->disable_intrs(ha); 3596 } 3597 3598 qla2x00_free_irqs(vha); 3599 3600 qla2x00_free_fw_dump(ha); 3601 3602 pci_disable_device(pdev); 3603 ql_log(ql_log_info, vha, 0xfffe, 3604 "Adapter shutdown successfully.\n"); 3605 } 3606 3607 /* Deletes all the virtual ports for a given ha */ 3608 static void 3609 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3610 { 3611 scsi_qla_host_t *vha; 3612 unsigned long flags; 3613 3614 mutex_lock(&ha->vport_lock); 3615 while (ha->cur_vport_count) { 3616 spin_lock_irqsave(&ha->vport_slock, flags); 3617 3618 BUG_ON(base_vha->list.next == &ha->vp_list); 3619 /* This assumes first entry in ha->vp_list is always base vha */ 3620 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3621 scsi_host_get(vha->host); 3622 3623 spin_unlock_irqrestore(&ha->vport_slock, flags); 3624 mutex_unlock(&ha->vport_lock); 3625 3626 qla_nvme_delete(vha); 3627 3628 fc_vport_terminate(vha->fc_vport); 3629 scsi_host_put(vha->host); 3630 3631 mutex_lock(&ha->vport_lock); 3632 } 3633 mutex_unlock(&ha->vport_lock); 3634 } 3635 3636 /* Stops all deferred work threads */ 3637 static void 3638 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3639 { 3640 /* Cancel all work and destroy DPC workqueues */ 3641 if (ha->dpc_lp_wq) { 3642 cancel_work_sync(&ha->idc_aen); 3643 destroy_workqueue(ha->dpc_lp_wq); 3644 ha->dpc_lp_wq = NULL; 3645 } 3646 3647 if (ha->dpc_hp_wq) { 3648 cancel_work_sync(&ha->nic_core_reset); 3649 cancel_work_sync(&ha->idc_state_handler); 3650 cancel_work_sync(&ha->nic_core_unrecoverable); 3651 destroy_workqueue(ha->dpc_hp_wq); 3652 ha->dpc_hp_wq = NULL; 3653 } 3654 3655 /* Kill the kernel thread for this host */ 3656 if (ha->dpc_thread) { 3657 struct task_struct *t = ha->dpc_thread; 3658 3659 /* 3660 * qla2xxx_wake_dpc checks for ->dpc_thread 3661 * so we need to zero it out. 3662 */ 3663 ha->dpc_thread = NULL; 3664 kthread_stop(t); 3665 } 3666 } 3667 3668 static void 3669 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3670 { 3671 if (IS_QLA82XX(ha)) { 3672 3673 iounmap((device_reg_t *)ha->nx_pcibase); 3674 if (!ql2xdbwr) 3675 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3676 } else { 3677 if (ha->iobase) 3678 iounmap(ha->iobase); 3679 3680 if (ha->cregbase) 3681 iounmap(ha->cregbase); 3682 3683 if (ha->mqiobase) 3684 iounmap(ha->mqiobase); 3685 3686 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3687 ha->msixbase) 3688 iounmap(ha->msixbase); 3689 } 3690 } 3691 3692 static void 3693 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3694 { 3695 if (IS_QLA8044(ha)) { 3696 qla8044_idc_lock(ha); 3697 qla8044_clear_drv_active(ha); 3698 qla8044_idc_unlock(ha); 3699 } else if (IS_QLA82XX(ha)) { 3700 qla82xx_idc_lock(ha); 3701 qla82xx_clear_drv_active(ha); 3702 qla82xx_idc_unlock(ha); 3703 } 3704 } 3705 3706 static void 3707 qla2x00_remove_one(struct pci_dev *pdev) 3708 { 3709 scsi_qla_host_t *base_vha; 3710 struct qla_hw_data *ha; 3711 3712 base_vha = pci_get_drvdata(pdev); 3713 ha = base_vha->hw; 3714 ql_log(ql_log_info, base_vha, 0xb079, 3715 "Removing driver\n"); 3716 __qla_set_remove_flag(base_vha); 3717 cancel_work_sync(&ha->board_disable); 3718 3719 /* 3720 * If the PCI device is disabled then there was a PCI-disconnect and 3721 * qla2x00_disable_board_on_pci_error has taken care of most of the 3722 * resources. 3723 */ 3724 if (!atomic_read(&pdev->enable_cnt)) { 3725 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3726 base_vha->gnl.l, base_vha->gnl.ldma); 3727 base_vha->gnl.l = NULL; 3728 scsi_host_put(base_vha->host); 3729 kfree(ha); 3730 pci_set_drvdata(pdev, NULL); 3731 return; 3732 } 3733 qla2x00_wait_for_hba_ready(base_vha); 3734 3735 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3736 IS_QLA28XX(ha)) { 3737 if (ha->flags.fw_started) 3738 qla2x00_abort_isp_cleanup(base_vha); 3739 } else if (!IS_QLAFX00(ha)) { 3740 if (IS_QLA8031(ha)) { 3741 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3742 "Clearing fcoe driver presence.\n"); 3743 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3744 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3745 "Error while clearing DRV-Presence.\n"); 3746 } 3747 3748 qla2x00_try_to_stop_firmware(base_vha); 3749 } 3750 3751 qla2x00_wait_for_sess_deletion(base_vha); 3752 3753 /* 3754 * if UNLOAD flag is already set, then continue unload, 3755 * where it was set first. 3756 */ 3757 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3758 return; 3759 3760 set_bit(UNLOADING, &base_vha->dpc_flags); 3761 3762 qla_nvme_delete(base_vha); 3763 3764 dma_free_coherent(&ha->pdev->dev, 3765 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3766 3767 base_vha->gnl.l = NULL; 3768 3769 vfree(base_vha->scan.l); 3770 3771 if (IS_QLAFX00(ha)) 3772 qlafx00_driver_shutdown(base_vha, 20); 3773 3774 qla2x00_delete_all_vps(ha, base_vha); 3775 3776 qla2x00_dfs_remove(base_vha); 3777 3778 qla84xx_put_chip(base_vha); 3779 3780 /* Disable timer */ 3781 if (base_vha->timer_active) 3782 qla2x00_stop_timer(base_vha); 3783 3784 base_vha->flags.online = 0; 3785 3786 /* free DMA memory */ 3787 if (ha->exlogin_buf) 3788 qla2x00_free_exlogin_buffer(ha); 3789 3790 /* free DMA memory */ 3791 if (ha->exchoffld_buf) 3792 qla2x00_free_exchoffld_buffer(ha); 3793 3794 qla2x00_destroy_deferred_work(ha); 3795 3796 qlt_remove_target(ha, base_vha); 3797 3798 qla2x00_free_sysfs_attr(base_vha, true); 3799 3800 fc_remove_host(base_vha->host); 3801 qlt_remove_target_resources(ha); 3802 3803 scsi_remove_host(base_vha->host); 3804 3805 qla2x00_free_device(base_vha); 3806 3807 qla2x00_clear_drv_active(ha); 3808 3809 scsi_host_put(base_vha->host); 3810 3811 qla2x00_unmap_iobases(ha); 3812 3813 pci_release_selected_regions(ha->pdev, ha->bars); 3814 kfree(ha); 3815 3816 pci_disable_pcie_error_reporting(pdev); 3817 3818 pci_disable_device(pdev); 3819 } 3820 3821 static inline void 3822 qla24xx_free_purex_list(struct purex_list *list) 3823 { 3824 struct list_head *item, *next; 3825 ulong flags; 3826 3827 spin_lock_irqsave(&list->lock, flags); 3828 list_for_each_safe(item, next, &list->head) { 3829 list_del(item); 3830 kfree(list_entry(item, struct purex_item, list)); 3831 } 3832 spin_unlock_irqrestore(&list->lock, flags); 3833 } 3834 3835 static void 3836 qla2x00_free_device(scsi_qla_host_t *vha) 3837 { 3838 struct qla_hw_data *ha = vha->hw; 3839 3840 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3841 3842 /* Disable timer */ 3843 if (vha->timer_active) 3844 qla2x00_stop_timer(vha); 3845 3846 qla25xx_delete_queues(vha); 3847 vha->flags.online = 0; 3848 3849 /* turn-off interrupts on the card */ 3850 if (ha->interrupts_on) { 3851 vha->flags.init_done = 0; 3852 ha->isp_ops->disable_intrs(ha); 3853 } 3854 3855 qla2x00_free_fcports(vha); 3856 3857 qla2x00_free_irqs(vha); 3858 3859 /* Flush the work queue and remove it */ 3860 if (ha->wq) { 3861 flush_workqueue(ha->wq); 3862 destroy_workqueue(ha->wq); 3863 ha->wq = NULL; 3864 } 3865 3866 3867 qla24xx_free_purex_list(&vha->purex_list); 3868 3869 qla2x00_mem_free(ha); 3870 3871 qla82xx_md_free(vha); 3872 3873 qla2x00_free_queues(ha); 3874 } 3875 3876 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3877 { 3878 fc_port_t *fcport, *tfcport; 3879 3880 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3881 qla2x00_free_fcport(fcport); 3882 } 3883 3884 static inline void 3885 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 3886 { 3887 int now; 3888 3889 if (!fcport->rport) 3890 return; 3891 3892 if (fcport->rport) { 3893 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3894 "%s %8phN. rport %p roles %x\n", 3895 __func__, fcport->port_name, fcport->rport, 3896 fcport->rport->roles); 3897 fc_remote_port_delete(fcport->rport); 3898 } 3899 qlt_do_generation_tick(vha, &now); 3900 } 3901 3902 /* 3903 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3904 * 3905 * Input: ha = adapter block pointer. fcport = port structure pointer. 3906 * 3907 * Return: None. 3908 * 3909 * Context: 3910 */ 3911 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3912 int do_login) 3913 { 3914 if (IS_QLAFX00(vha->hw)) { 3915 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3916 qla2x00_schedule_rport_del(vha, fcport); 3917 return; 3918 } 3919 3920 if (atomic_read(&fcport->state) == FCS_ONLINE && 3921 vha->vp_idx == fcport->vha->vp_idx) { 3922 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3923 qla2x00_schedule_rport_del(vha, fcport); 3924 } 3925 /* 3926 * We may need to retry the login, so don't change the state of the 3927 * port but do the retries. 3928 */ 3929 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3930 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3931 3932 if (!do_login) 3933 return; 3934 3935 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3936 } 3937 3938 void 3939 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 3940 { 3941 fc_port_t *fcport; 3942 3943 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3944 "Mark all dev lost\n"); 3945 3946 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3947 fcport->scan_state = 0; 3948 qlt_schedule_sess_for_deletion(fcport); 3949 } 3950 } 3951 3952 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 3953 { 3954 int i; 3955 3956 if (IS_FWI2_CAPABLE(ha)) 3957 return; 3958 3959 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 3960 set_bit(i, ha->loop_id_map); 3961 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 3962 set_bit(BROADCAST, ha->loop_id_map); 3963 } 3964 3965 /* 3966 * qla2x00_mem_alloc 3967 * Allocates adapter memory. 3968 * 3969 * Returns: 3970 * 0 = success. 3971 * !0 = failure. 3972 */ 3973 static int 3974 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3975 struct req_que **req, struct rsp_que **rsp) 3976 { 3977 char name[16]; 3978 3979 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3980 &ha->init_cb_dma, GFP_KERNEL); 3981 if (!ha->init_cb) 3982 goto fail; 3983 3984 if (qlt_mem_alloc(ha) < 0) 3985 goto fail_free_init_cb; 3986 3987 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3988 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3989 if (!ha->gid_list) 3990 goto fail_free_tgt_mem; 3991 3992 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3993 if (!ha->srb_mempool) 3994 goto fail_free_gid_list; 3995 3996 if (IS_P3P_TYPE(ha)) { 3997 /* Allocate cache for CT6 Ctx. */ 3998 if (!ctx_cachep) { 3999 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4000 sizeof(struct ct6_dsd), 0, 4001 SLAB_HWCACHE_ALIGN, NULL); 4002 if (!ctx_cachep) 4003 goto fail_free_srb_mempool; 4004 } 4005 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4006 ctx_cachep); 4007 if (!ha->ctx_mempool) 4008 goto fail_free_srb_mempool; 4009 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4010 "ctx_cachep=%p ctx_mempool=%p.\n", 4011 ctx_cachep, ha->ctx_mempool); 4012 } 4013 4014 /* Get memory for cached NVRAM */ 4015 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4016 if (!ha->nvram) 4017 goto fail_free_ctx_mempool; 4018 4019 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4020 ha->pdev->device); 4021 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4022 DMA_POOL_SIZE, 8, 0); 4023 if (!ha->s_dma_pool) 4024 goto fail_free_nvram; 4025 4026 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4027 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4028 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4029 4030 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 4031 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4032 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4033 if (!ha->dl_dma_pool) { 4034 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4035 "Failed to allocate memory for dl_dma_pool.\n"); 4036 goto fail_s_dma_pool; 4037 } 4038 4039 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4040 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4041 if (!ha->fcp_cmnd_dma_pool) { 4042 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4043 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4044 goto fail_dl_dma_pool; 4045 } 4046 4047 if (ql2xenabledif) { 4048 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4049 struct dsd_dma *dsd, *nxt; 4050 uint i; 4051 /* Creata a DMA pool of buffers for DIF bundling */ 4052 ha->dif_bundl_pool = dma_pool_create(name, 4053 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4054 if (!ha->dif_bundl_pool) { 4055 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4056 "%s: failed create dif_bundl_pool\n", 4057 __func__); 4058 goto fail_dif_bundl_dma_pool; 4059 } 4060 4061 INIT_LIST_HEAD(&ha->pool.good.head); 4062 INIT_LIST_HEAD(&ha->pool.unusable.head); 4063 ha->pool.good.count = 0; 4064 ha->pool.unusable.count = 0; 4065 for (i = 0; i < 128; i++) { 4066 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4067 if (!dsd) { 4068 ql_dbg_pci(ql_dbg_init, ha->pdev, 4069 0xe0ee, "%s: failed alloc dsd\n", 4070 __func__); 4071 return 1; 4072 } 4073 ha->dif_bundle_kallocs++; 4074 4075 dsd->dsd_addr = dma_pool_alloc( 4076 ha->dif_bundl_pool, GFP_ATOMIC, 4077 &dsd->dsd_list_dma); 4078 if (!dsd->dsd_addr) { 4079 ql_dbg_pci(ql_dbg_init, ha->pdev, 4080 0xe0ee, 4081 "%s: failed alloc ->dsd_addr\n", 4082 __func__); 4083 kfree(dsd); 4084 ha->dif_bundle_kallocs--; 4085 continue; 4086 } 4087 ha->dif_bundle_dma_allocs++; 4088 4089 /* 4090 * if DMA buffer crosses 4G boundary, 4091 * put it on bad list 4092 */ 4093 if (MSD(dsd->dsd_list_dma) ^ 4094 MSD(dsd->dsd_list_dma + bufsize)) { 4095 list_add_tail(&dsd->list, 4096 &ha->pool.unusable.head); 4097 ha->pool.unusable.count++; 4098 } else { 4099 list_add_tail(&dsd->list, 4100 &ha->pool.good.head); 4101 ha->pool.good.count++; 4102 } 4103 } 4104 4105 /* return the good ones back to the pool */ 4106 list_for_each_entry_safe(dsd, nxt, 4107 &ha->pool.good.head, list) { 4108 list_del(&dsd->list); 4109 dma_pool_free(ha->dif_bundl_pool, 4110 dsd->dsd_addr, dsd->dsd_list_dma); 4111 ha->dif_bundle_dma_allocs--; 4112 kfree(dsd); 4113 ha->dif_bundle_kallocs--; 4114 } 4115 4116 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4117 "%s: dif dma pool (good=%u unusable=%u)\n", 4118 __func__, ha->pool.good.count, 4119 ha->pool.unusable.count); 4120 } 4121 4122 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4123 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4124 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4125 ha->dif_bundl_pool); 4126 } 4127 4128 /* Allocate memory for SNS commands */ 4129 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4130 /* Get consistent memory allocated for SNS commands */ 4131 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4132 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4133 if (!ha->sns_cmd) 4134 goto fail_dma_pool; 4135 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4136 "sns_cmd: %p.\n", ha->sns_cmd); 4137 } else { 4138 /* Get consistent memory allocated for MS IOCB */ 4139 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4140 &ha->ms_iocb_dma); 4141 if (!ha->ms_iocb) 4142 goto fail_dma_pool; 4143 /* Get consistent memory allocated for CT SNS commands */ 4144 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4145 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4146 if (!ha->ct_sns) 4147 goto fail_free_ms_iocb; 4148 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4149 "ms_iocb=%p ct_sns=%p.\n", 4150 ha->ms_iocb, ha->ct_sns); 4151 } 4152 4153 /* Allocate memory for request ring */ 4154 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4155 if (!*req) { 4156 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4157 "Failed to allocate memory for req.\n"); 4158 goto fail_req; 4159 } 4160 (*req)->length = req_len; 4161 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4162 ((*req)->length + 1) * sizeof(request_t), 4163 &(*req)->dma, GFP_KERNEL); 4164 if (!(*req)->ring) { 4165 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4166 "Failed to allocate memory for req_ring.\n"); 4167 goto fail_req_ring; 4168 } 4169 /* Allocate memory for response ring */ 4170 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4171 if (!*rsp) { 4172 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4173 "Failed to allocate memory for rsp.\n"); 4174 goto fail_rsp; 4175 } 4176 (*rsp)->hw = ha; 4177 (*rsp)->length = rsp_len; 4178 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4179 ((*rsp)->length + 1) * sizeof(response_t), 4180 &(*rsp)->dma, GFP_KERNEL); 4181 if (!(*rsp)->ring) { 4182 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4183 "Failed to allocate memory for rsp_ring.\n"); 4184 goto fail_rsp_ring; 4185 } 4186 (*req)->rsp = *rsp; 4187 (*rsp)->req = *req; 4188 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4189 "req=%p req->length=%d req->ring=%p rsp=%p " 4190 "rsp->length=%d rsp->ring=%p.\n", 4191 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4192 (*rsp)->ring); 4193 /* Allocate memory for NVRAM data for vports */ 4194 if (ha->nvram_npiv_size) { 4195 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4196 sizeof(struct qla_npiv_entry), 4197 GFP_KERNEL); 4198 if (!ha->npiv_info) { 4199 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4200 "Failed to allocate memory for npiv_info.\n"); 4201 goto fail_npiv_info; 4202 } 4203 } else 4204 ha->npiv_info = NULL; 4205 4206 /* Get consistent memory allocated for EX-INIT-CB. */ 4207 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4208 IS_QLA28XX(ha)) { 4209 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4210 &ha->ex_init_cb_dma); 4211 if (!ha->ex_init_cb) 4212 goto fail_ex_init_cb; 4213 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4214 "ex_init_cb=%p.\n", ha->ex_init_cb); 4215 } 4216 4217 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4218 4219 /* Get consistent memory allocated for Async Port-Database. */ 4220 if (!IS_FWI2_CAPABLE(ha)) { 4221 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4222 &ha->async_pd_dma); 4223 if (!ha->async_pd) 4224 goto fail_async_pd; 4225 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4226 "async_pd=%p.\n", ha->async_pd); 4227 } 4228 4229 INIT_LIST_HEAD(&ha->vp_list); 4230 4231 /* Allocate memory for our loop_id bitmap */ 4232 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4233 sizeof(long), 4234 GFP_KERNEL); 4235 if (!ha->loop_id_map) 4236 goto fail_loop_id_map; 4237 else { 4238 qla2x00_set_reserved_loop_ids(ha); 4239 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4240 "loop_id_map=%p.\n", ha->loop_id_map); 4241 } 4242 4243 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4244 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4245 if (!ha->sfp_data) { 4246 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4247 "Unable to allocate memory for SFP read-data.\n"); 4248 goto fail_sfp_data; 4249 } 4250 4251 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4252 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4253 GFP_KERNEL); 4254 if (!ha->flt) { 4255 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4256 "Unable to allocate memory for FLT.\n"); 4257 goto fail_flt_buffer; 4258 } 4259 4260 return 0; 4261 4262 fail_flt_buffer: 4263 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4264 ha->sfp_data, ha->sfp_data_dma); 4265 fail_sfp_data: 4266 kfree(ha->loop_id_map); 4267 fail_loop_id_map: 4268 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4269 fail_async_pd: 4270 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4271 fail_ex_init_cb: 4272 kfree(ha->npiv_info); 4273 fail_npiv_info: 4274 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4275 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4276 (*rsp)->ring = NULL; 4277 (*rsp)->dma = 0; 4278 fail_rsp_ring: 4279 kfree(*rsp); 4280 *rsp = NULL; 4281 fail_rsp: 4282 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4283 sizeof(request_t), (*req)->ring, (*req)->dma); 4284 (*req)->ring = NULL; 4285 (*req)->dma = 0; 4286 fail_req_ring: 4287 kfree(*req); 4288 *req = NULL; 4289 fail_req: 4290 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4291 ha->ct_sns, ha->ct_sns_dma); 4292 ha->ct_sns = NULL; 4293 ha->ct_sns_dma = 0; 4294 fail_free_ms_iocb: 4295 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4296 ha->ms_iocb = NULL; 4297 ha->ms_iocb_dma = 0; 4298 4299 if (ha->sns_cmd) 4300 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4301 ha->sns_cmd, ha->sns_cmd_dma); 4302 fail_dma_pool: 4303 if (ql2xenabledif) { 4304 struct dsd_dma *dsd, *nxt; 4305 4306 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4307 list) { 4308 list_del(&dsd->list); 4309 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4310 dsd->dsd_list_dma); 4311 ha->dif_bundle_dma_allocs--; 4312 kfree(dsd); 4313 ha->dif_bundle_kallocs--; 4314 ha->pool.unusable.count--; 4315 } 4316 dma_pool_destroy(ha->dif_bundl_pool); 4317 ha->dif_bundl_pool = NULL; 4318 } 4319 4320 fail_dif_bundl_dma_pool: 4321 if (IS_QLA82XX(ha) || ql2xenabledif) { 4322 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4323 ha->fcp_cmnd_dma_pool = NULL; 4324 } 4325 fail_dl_dma_pool: 4326 if (IS_QLA82XX(ha) || ql2xenabledif) { 4327 dma_pool_destroy(ha->dl_dma_pool); 4328 ha->dl_dma_pool = NULL; 4329 } 4330 fail_s_dma_pool: 4331 dma_pool_destroy(ha->s_dma_pool); 4332 ha->s_dma_pool = NULL; 4333 fail_free_nvram: 4334 kfree(ha->nvram); 4335 ha->nvram = NULL; 4336 fail_free_ctx_mempool: 4337 mempool_destroy(ha->ctx_mempool); 4338 ha->ctx_mempool = NULL; 4339 fail_free_srb_mempool: 4340 mempool_destroy(ha->srb_mempool); 4341 ha->srb_mempool = NULL; 4342 fail_free_gid_list: 4343 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4344 ha->gid_list, 4345 ha->gid_list_dma); 4346 ha->gid_list = NULL; 4347 ha->gid_list_dma = 0; 4348 fail_free_tgt_mem: 4349 qlt_mem_free(ha); 4350 fail_free_init_cb: 4351 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4352 ha->init_cb_dma); 4353 ha->init_cb = NULL; 4354 ha->init_cb_dma = 0; 4355 fail: 4356 ql_log(ql_log_fatal, NULL, 0x0030, 4357 "Memory allocation failure.\n"); 4358 return -ENOMEM; 4359 } 4360 4361 int 4362 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4363 { 4364 int rval; 4365 uint16_t size, max_cnt, temp; 4366 struct qla_hw_data *ha = vha->hw; 4367 4368 /* Return if we don't need to alloacate any extended logins */ 4369 if (!ql2xexlogins) 4370 return QLA_SUCCESS; 4371 4372 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4373 return QLA_SUCCESS; 4374 4375 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4376 max_cnt = 0; 4377 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4378 if (rval != QLA_SUCCESS) { 4379 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4380 "Failed to get exlogin status.\n"); 4381 return rval; 4382 } 4383 4384 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4385 temp *= size; 4386 4387 if (temp != ha->exlogin_size) { 4388 qla2x00_free_exlogin_buffer(ha); 4389 ha->exlogin_size = temp; 4390 4391 ql_log(ql_log_info, vha, 0xd024, 4392 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4393 max_cnt, size, temp); 4394 4395 ql_log(ql_log_info, vha, 0xd025, 4396 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4397 4398 /* Get consistent memory for extended logins */ 4399 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4400 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4401 if (!ha->exlogin_buf) { 4402 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4403 "Failed to allocate memory for exlogin_buf_dma.\n"); 4404 return -ENOMEM; 4405 } 4406 } 4407 4408 /* Now configure the dma buffer */ 4409 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4410 if (rval) { 4411 ql_log(ql_log_fatal, vha, 0xd033, 4412 "Setup extended login buffer ****FAILED****.\n"); 4413 qla2x00_free_exlogin_buffer(ha); 4414 } 4415 4416 return rval; 4417 } 4418 4419 /* 4420 * qla2x00_free_exlogin_buffer 4421 * 4422 * Input: 4423 * ha = adapter block pointer 4424 */ 4425 void 4426 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4427 { 4428 if (ha->exlogin_buf) { 4429 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4430 ha->exlogin_buf, ha->exlogin_buf_dma); 4431 ha->exlogin_buf = NULL; 4432 ha->exlogin_size = 0; 4433 } 4434 } 4435 4436 static void 4437 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4438 { 4439 u32 temp; 4440 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4441 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4442 4443 if (max_cnt > vha->hw->max_exchg) 4444 max_cnt = vha->hw->max_exchg; 4445 4446 if (qla_ini_mode_enabled(vha)) { 4447 if (vha->ql2xiniexchg > max_cnt) 4448 vha->ql2xiniexchg = max_cnt; 4449 4450 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4451 *ret_cnt = vha->ql2xiniexchg; 4452 4453 } else if (qla_tgt_mode_enabled(vha)) { 4454 if (vha->ql2xexchoffld > max_cnt) { 4455 vha->ql2xexchoffld = max_cnt; 4456 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4457 } 4458 4459 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4460 *ret_cnt = vha->ql2xexchoffld; 4461 } else if (qla_dual_mode_enabled(vha)) { 4462 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4463 if (temp > max_cnt) { 4464 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4465 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4466 temp = max_cnt; 4467 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4468 } 4469 4470 if (temp > FW_DEF_EXCHANGES_CNT) 4471 *ret_cnt = temp; 4472 } 4473 } 4474 4475 int 4476 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4477 { 4478 int rval; 4479 u16 size, max_cnt; 4480 u32 actual_cnt, totsz; 4481 struct qla_hw_data *ha = vha->hw; 4482 4483 if (!ha->flags.exchoffld_enabled) 4484 return QLA_SUCCESS; 4485 4486 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4487 return QLA_SUCCESS; 4488 4489 max_cnt = 0; 4490 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4491 if (rval != QLA_SUCCESS) { 4492 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4493 "Failed to get exlogin status.\n"); 4494 return rval; 4495 } 4496 4497 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4498 ql_log(ql_log_info, vha, 0xd014, 4499 "Actual exchange offload count: %d.\n", actual_cnt); 4500 4501 totsz = actual_cnt * size; 4502 4503 if (totsz != ha->exchoffld_size) { 4504 qla2x00_free_exchoffld_buffer(ha); 4505 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4506 ha->exchoffld_size = 0; 4507 ha->flags.exchoffld_enabled = 0; 4508 return QLA_SUCCESS; 4509 } 4510 4511 ha->exchoffld_size = totsz; 4512 4513 ql_log(ql_log_info, vha, 0xd016, 4514 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4515 max_cnt, actual_cnt, size, totsz); 4516 4517 ql_log(ql_log_info, vha, 0xd017, 4518 "Exchange Buffers requested size = 0x%x\n", 4519 ha->exchoffld_size); 4520 4521 /* Get consistent memory for extended logins */ 4522 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4523 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4524 if (!ha->exchoffld_buf) { 4525 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4526 "Failed to allocate memory for Exchange Offload.\n"); 4527 4528 if (ha->max_exchg > 4529 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4530 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4531 } else if (ha->max_exchg > 4532 (FW_DEF_EXCHANGES_CNT + 512)) { 4533 ha->max_exchg -= 512; 4534 } else { 4535 ha->flags.exchoffld_enabled = 0; 4536 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4537 "Disabling Exchange offload due to lack of memory\n"); 4538 } 4539 ha->exchoffld_size = 0; 4540 4541 return -ENOMEM; 4542 } 4543 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4544 /* pathological case */ 4545 qla2x00_free_exchoffld_buffer(ha); 4546 ha->exchoffld_size = 0; 4547 ha->flags.exchoffld_enabled = 0; 4548 ql_log(ql_log_info, vha, 0xd016, 4549 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4550 ha->exchoffld_size, actual_cnt, size, totsz); 4551 return 0; 4552 } 4553 4554 /* Now configure the dma buffer */ 4555 rval = qla_set_exchoffld_mem_cfg(vha); 4556 if (rval) { 4557 ql_log(ql_log_fatal, vha, 0xd02e, 4558 "Setup exchange offload buffer ****FAILED****.\n"); 4559 qla2x00_free_exchoffld_buffer(ha); 4560 } else { 4561 /* re-adjust number of target exchange */ 4562 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4563 4564 if (qla_ini_mode_enabled(vha)) 4565 icb->exchange_count = 0; 4566 else 4567 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4568 } 4569 4570 return rval; 4571 } 4572 4573 /* 4574 * qla2x00_free_exchoffld_buffer 4575 * 4576 * Input: 4577 * ha = adapter block pointer 4578 */ 4579 void 4580 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4581 { 4582 if (ha->exchoffld_buf) { 4583 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4584 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4585 ha->exchoffld_buf = NULL; 4586 ha->exchoffld_size = 0; 4587 } 4588 } 4589 4590 /* 4591 * qla2x00_free_fw_dump 4592 * Frees fw dump stuff. 4593 * 4594 * Input: 4595 * ha = adapter block pointer 4596 */ 4597 static void 4598 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4599 { 4600 struct fwdt *fwdt = ha->fwdt; 4601 uint j; 4602 4603 if (ha->fce) 4604 dma_free_coherent(&ha->pdev->dev, 4605 FCE_SIZE, ha->fce, ha->fce_dma); 4606 4607 if (ha->eft) 4608 dma_free_coherent(&ha->pdev->dev, 4609 EFT_SIZE, ha->eft, ha->eft_dma); 4610 4611 if (ha->fw_dump) 4612 vfree(ha->fw_dump); 4613 4614 ha->fce = NULL; 4615 ha->fce_dma = 0; 4616 ha->flags.fce_enabled = 0; 4617 ha->eft = NULL; 4618 ha->eft_dma = 0; 4619 ha->fw_dumped = 0; 4620 ha->fw_dump_cap_flags = 0; 4621 ha->fw_dump_reading = 0; 4622 ha->fw_dump = NULL; 4623 ha->fw_dump_len = 0; 4624 4625 for (j = 0; j < 2; j++, fwdt++) { 4626 if (fwdt->template) 4627 vfree(fwdt->template); 4628 fwdt->template = NULL; 4629 fwdt->length = 0; 4630 } 4631 } 4632 4633 /* 4634 * qla2x00_mem_free 4635 * Frees all adapter allocated memory. 4636 * 4637 * Input: 4638 * ha = adapter block pointer. 4639 */ 4640 static void 4641 qla2x00_mem_free(struct qla_hw_data *ha) 4642 { 4643 qla2x00_free_fw_dump(ha); 4644 4645 if (ha->mctp_dump) 4646 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4647 ha->mctp_dump_dma); 4648 ha->mctp_dump = NULL; 4649 4650 mempool_destroy(ha->srb_mempool); 4651 ha->srb_mempool = NULL; 4652 4653 if (ha->dcbx_tlv) 4654 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4655 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4656 ha->dcbx_tlv = NULL; 4657 4658 if (ha->xgmac_data) 4659 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4660 ha->xgmac_data, ha->xgmac_data_dma); 4661 ha->xgmac_data = NULL; 4662 4663 if (ha->sns_cmd) 4664 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4665 ha->sns_cmd, ha->sns_cmd_dma); 4666 ha->sns_cmd = NULL; 4667 ha->sns_cmd_dma = 0; 4668 4669 if (ha->ct_sns) 4670 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4671 ha->ct_sns, ha->ct_sns_dma); 4672 ha->ct_sns = NULL; 4673 ha->ct_sns_dma = 0; 4674 4675 if (ha->sfp_data) 4676 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4677 ha->sfp_data_dma); 4678 ha->sfp_data = NULL; 4679 4680 if (ha->flt) 4681 dma_free_coherent(&ha->pdev->dev, 4682 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4683 ha->flt, ha->flt_dma); 4684 ha->flt = NULL; 4685 ha->flt_dma = 0; 4686 4687 if (ha->ms_iocb) 4688 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4689 ha->ms_iocb = NULL; 4690 ha->ms_iocb_dma = 0; 4691 4692 if (ha->ex_init_cb) 4693 dma_pool_free(ha->s_dma_pool, 4694 ha->ex_init_cb, ha->ex_init_cb_dma); 4695 ha->ex_init_cb = NULL; 4696 ha->ex_init_cb_dma = 0; 4697 4698 if (ha->async_pd) 4699 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4700 ha->async_pd = NULL; 4701 ha->async_pd_dma = 0; 4702 4703 dma_pool_destroy(ha->s_dma_pool); 4704 ha->s_dma_pool = NULL; 4705 4706 if (ha->gid_list) 4707 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4708 ha->gid_list, ha->gid_list_dma); 4709 ha->gid_list = NULL; 4710 ha->gid_list_dma = 0; 4711 4712 if (IS_QLA82XX(ha)) { 4713 if (!list_empty(&ha->gbl_dsd_list)) { 4714 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4715 4716 /* clean up allocated prev pool */ 4717 list_for_each_entry_safe(dsd_ptr, 4718 tdsd_ptr, &ha->gbl_dsd_list, list) { 4719 dma_pool_free(ha->dl_dma_pool, 4720 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4721 list_del(&dsd_ptr->list); 4722 kfree(dsd_ptr); 4723 } 4724 } 4725 } 4726 4727 dma_pool_destroy(ha->dl_dma_pool); 4728 ha->dl_dma_pool = NULL; 4729 4730 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4731 ha->fcp_cmnd_dma_pool = NULL; 4732 4733 mempool_destroy(ha->ctx_mempool); 4734 ha->ctx_mempool = NULL; 4735 4736 if (ql2xenabledif && ha->dif_bundl_pool) { 4737 struct dsd_dma *dsd, *nxt; 4738 4739 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4740 list) { 4741 list_del(&dsd->list); 4742 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4743 dsd->dsd_list_dma); 4744 ha->dif_bundle_dma_allocs--; 4745 kfree(dsd); 4746 ha->dif_bundle_kallocs--; 4747 ha->pool.unusable.count--; 4748 } 4749 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4750 list_del(&dsd->list); 4751 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4752 dsd->dsd_list_dma); 4753 ha->dif_bundle_dma_allocs--; 4754 kfree(dsd); 4755 ha->dif_bundle_kallocs--; 4756 } 4757 } 4758 4759 dma_pool_destroy(ha->dif_bundl_pool); 4760 ha->dif_bundl_pool = NULL; 4761 4762 qlt_mem_free(ha); 4763 4764 if (ha->init_cb) 4765 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4766 ha->init_cb, ha->init_cb_dma); 4767 ha->init_cb = NULL; 4768 ha->init_cb_dma = 0; 4769 4770 vfree(ha->optrom_buffer); 4771 ha->optrom_buffer = NULL; 4772 kfree(ha->nvram); 4773 ha->nvram = NULL; 4774 kfree(ha->npiv_info); 4775 ha->npiv_info = NULL; 4776 kfree(ha->swl); 4777 ha->swl = NULL; 4778 kfree(ha->loop_id_map); 4779 ha->loop_id_map = NULL; 4780 } 4781 4782 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4783 struct qla_hw_data *ha) 4784 { 4785 struct Scsi_Host *host; 4786 struct scsi_qla_host *vha = NULL; 4787 4788 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4789 if (!host) { 4790 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4791 "Failed to allocate host from the scsi layer, aborting.\n"); 4792 return NULL; 4793 } 4794 4795 /* Clear our data area */ 4796 vha = shost_priv(host); 4797 memset(vha, 0, sizeof(scsi_qla_host_t)); 4798 4799 vha->host = host; 4800 vha->host_no = host->host_no; 4801 vha->hw = ha; 4802 4803 vha->qlini_mode = ql2x_ini_mode; 4804 vha->ql2xexchoffld = ql2xexchoffld; 4805 vha->ql2xiniexchg = ql2xiniexchg; 4806 4807 INIT_LIST_HEAD(&vha->vp_fcports); 4808 INIT_LIST_HEAD(&vha->work_list); 4809 INIT_LIST_HEAD(&vha->list); 4810 INIT_LIST_HEAD(&vha->qla_cmd_list); 4811 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4812 INIT_LIST_HEAD(&vha->logo_list); 4813 INIT_LIST_HEAD(&vha->plogi_ack_list); 4814 INIT_LIST_HEAD(&vha->qp_list); 4815 INIT_LIST_HEAD(&vha->gnl.fcports); 4816 INIT_LIST_HEAD(&vha->gpnid_list); 4817 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4818 4819 INIT_LIST_HEAD(&vha->purex_list.head); 4820 spin_lock_init(&vha->purex_list.lock); 4821 4822 spin_lock_init(&vha->work_lock); 4823 spin_lock_init(&vha->cmd_list_lock); 4824 init_waitqueue_head(&vha->fcport_waitQ); 4825 init_waitqueue_head(&vha->vref_waitq); 4826 4827 vha->gnl.size = sizeof(struct get_name_list_extended) * 4828 (ha->max_loop_id + 1); 4829 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4830 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4831 if (!vha->gnl.l) { 4832 ql_log(ql_log_fatal, vha, 0xd04a, 4833 "Alloc failed for name list.\n"); 4834 scsi_host_put(vha->host); 4835 return NULL; 4836 } 4837 4838 /* todo: what about ext login? */ 4839 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4840 vha->scan.l = vmalloc(vha->scan.size); 4841 if (!vha->scan.l) { 4842 ql_log(ql_log_fatal, vha, 0xd04a, 4843 "Alloc failed for scan database.\n"); 4844 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4845 vha->gnl.l, vha->gnl.ldma); 4846 vha->gnl.l = NULL; 4847 scsi_host_put(vha->host); 4848 return NULL; 4849 } 4850 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4851 4852 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4853 ql_dbg(ql_dbg_init, vha, 0x0041, 4854 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4855 vha->host, vha->hw, vha, 4856 dev_name(&(ha->pdev->dev))); 4857 4858 return vha; 4859 } 4860 4861 struct qla_work_evt * 4862 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4863 { 4864 struct qla_work_evt *e; 4865 uint8_t bail; 4866 4867 QLA_VHA_MARK_BUSY(vha, bail); 4868 if (bail) 4869 return NULL; 4870 4871 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4872 if (!e) { 4873 QLA_VHA_MARK_NOT_BUSY(vha); 4874 return NULL; 4875 } 4876 4877 INIT_LIST_HEAD(&e->list); 4878 e->type = type; 4879 e->flags = QLA_EVT_FLAG_FREE; 4880 return e; 4881 } 4882 4883 int 4884 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4885 { 4886 unsigned long flags; 4887 bool q = false; 4888 4889 spin_lock_irqsave(&vha->work_lock, flags); 4890 list_add_tail(&e->list, &vha->work_list); 4891 4892 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4893 q = true; 4894 4895 spin_unlock_irqrestore(&vha->work_lock, flags); 4896 4897 if (q) 4898 queue_work(vha->hw->wq, &vha->iocb_work); 4899 4900 return QLA_SUCCESS; 4901 } 4902 4903 int 4904 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4905 u32 data) 4906 { 4907 struct qla_work_evt *e; 4908 4909 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4910 if (!e) 4911 return QLA_FUNCTION_FAILED; 4912 4913 e->u.aen.code = code; 4914 e->u.aen.data = data; 4915 return qla2x00_post_work(vha, e); 4916 } 4917 4918 int 4919 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4920 { 4921 struct qla_work_evt *e; 4922 4923 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4924 if (!e) 4925 return QLA_FUNCTION_FAILED; 4926 4927 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4928 return qla2x00_post_work(vha, e); 4929 } 4930 4931 #define qla2x00_post_async_work(name, type) \ 4932 int qla2x00_post_async_##name##_work( \ 4933 struct scsi_qla_host *vha, \ 4934 fc_port_t *fcport, uint16_t *data) \ 4935 { \ 4936 struct qla_work_evt *e; \ 4937 \ 4938 e = qla2x00_alloc_work(vha, type); \ 4939 if (!e) \ 4940 return QLA_FUNCTION_FAILED; \ 4941 \ 4942 e->u.logio.fcport = fcport; \ 4943 if (data) { \ 4944 e->u.logio.data[0] = data[0]; \ 4945 e->u.logio.data[1] = data[1]; \ 4946 } \ 4947 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4948 return qla2x00_post_work(vha, e); \ 4949 } 4950 4951 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4952 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4953 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4954 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4955 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4956 4957 int 4958 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4959 { 4960 struct qla_work_evt *e; 4961 4962 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4963 if (!e) 4964 return QLA_FUNCTION_FAILED; 4965 4966 e->u.uevent.code = code; 4967 return qla2x00_post_work(vha, e); 4968 } 4969 4970 static void 4971 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4972 { 4973 char event_string[40]; 4974 char *envp[] = { event_string, NULL }; 4975 4976 switch (code) { 4977 case QLA_UEVENT_CODE_FW_DUMP: 4978 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4979 vha->host_no); 4980 break; 4981 default: 4982 /* do nothing */ 4983 break; 4984 } 4985 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4986 } 4987 4988 int 4989 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4990 uint32_t *data, int cnt) 4991 { 4992 struct qla_work_evt *e; 4993 4994 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4995 if (!e) 4996 return QLA_FUNCTION_FAILED; 4997 4998 e->u.aenfx.evtcode = evtcode; 4999 e->u.aenfx.count = cnt; 5000 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5001 return qla2x00_post_work(vha, e); 5002 } 5003 5004 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5005 { 5006 unsigned long flags; 5007 5008 if (IS_SW_RESV_ADDR(fcport->d_id)) 5009 return; 5010 5011 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5012 if (fcport->disc_state == DSC_UPD_FCPORT) { 5013 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5014 return; 5015 } 5016 fcport->jiffies_at_registration = jiffies; 5017 fcport->sec_since_registration = 0; 5018 fcport->next_disc_state = DSC_DELETED; 5019 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5020 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5021 5022 queue_work(system_unbound_wq, &fcport->reg_work); 5023 } 5024 5025 static 5026 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5027 { 5028 unsigned long flags; 5029 fc_port_t *fcport = NULL, *tfcp; 5030 struct qlt_plogi_ack_t *pla = 5031 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5032 uint8_t free_fcport = 0; 5033 5034 ql_dbg(ql_dbg_disc, vha, 0xffff, 5035 "%s %d %8phC enter\n", 5036 __func__, __LINE__, e->u.new_sess.port_name); 5037 5038 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5039 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5040 if (fcport) { 5041 fcport->d_id = e->u.new_sess.id; 5042 if (pla) { 5043 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5044 memcpy(fcport->node_name, 5045 pla->iocb.u.isp24.u.plogi.node_name, 5046 WWN_SIZE); 5047 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5048 /* we took an extra ref_count to prevent PLOGI ACK when 5049 * fcport/sess has not been created. 5050 */ 5051 pla->ref_count--; 5052 } 5053 } else { 5054 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5055 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5056 if (fcport) { 5057 fcport->d_id = e->u.new_sess.id; 5058 fcport->flags |= FCF_FABRIC_DEVICE; 5059 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5060 5061 memcpy(fcport->port_name, e->u.new_sess.port_name, 5062 WWN_SIZE); 5063 5064 fcport->fc4_type = e->u.new_sess.fc4_type; 5065 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5066 fcport->fc4_type = FS_FC4TYPE_FCP; 5067 fcport->n2n_flag = 1; 5068 if (vha->flags.nvme_enabled) 5069 fcport->fc4_type |= FS_FC4TYPE_NVME; 5070 } 5071 5072 } else { 5073 ql_dbg(ql_dbg_disc, vha, 0xffff, 5074 "%s %8phC mem alloc fail.\n", 5075 __func__, e->u.new_sess.port_name); 5076 5077 if (pla) { 5078 list_del(&pla->list); 5079 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5080 } 5081 return; 5082 } 5083 5084 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5085 /* search again to make sure no one else got ahead */ 5086 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5087 e->u.new_sess.port_name, 1); 5088 if (tfcp) { 5089 /* should rarily happen */ 5090 ql_dbg(ql_dbg_disc, vha, 0xffff, 5091 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5092 __func__, tfcp->port_name, tfcp->disc_state, 5093 tfcp->fw_login_state); 5094 5095 free_fcport = 1; 5096 } else { 5097 list_add_tail(&fcport->list, &vha->vp_fcports); 5098 5099 } 5100 if (pla) { 5101 qlt_plogi_ack_link(vha, pla, fcport, 5102 QLT_PLOGI_LINK_SAME_WWN); 5103 pla->ref_count--; 5104 } 5105 } 5106 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5107 5108 if (fcport) { 5109 fcport->id_changed = 1; 5110 fcport->scan_state = QLA_FCPORT_FOUND; 5111 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5112 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5113 5114 if (pla) { 5115 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5116 u16 wd3_lo; 5117 5118 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5119 fcport->local = 0; 5120 fcport->loop_id = 5121 le16_to_cpu( 5122 pla->iocb.u.isp24.nport_handle); 5123 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5124 wd3_lo = 5125 le16_to_cpu( 5126 pla->iocb.u.isp24.u.prli.wd3_lo); 5127 5128 if (wd3_lo & BIT_7) 5129 fcport->conf_compl_supported = 1; 5130 5131 if ((wd3_lo & BIT_4) == 0) 5132 fcport->port_type = FCT_INITIATOR; 5133 else 5134 fcport->port_type = FCT_TARGET; 5135 } 5136 qlt_plogi_ack_unref(vha, pla); 5137 } else { 5138 fc_port_t *dfcp = NULL; 5139 5140 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5141 tfcp = qla2x00_find_fcport_by_nportid(vha, 5142 &e->u.new_sess.id, 1); 5143 if (tfcp && (tfcp != fcport)) { 5144 /* 5145 * We have a conflict fcport with same NportID. 5146 */ 5147 ql_dbg(ql_dbg_disc, vha, 0xffff, 5148 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5149 __func__, tfcp->port_name, tfcp->disc_state, 5150 tfcp->fw_login_state); 5151 5152 switch (tfcp->disc_state) { 5153 case DSC_DELETED: 5154 break; 5155 case DSC_DELETE_PEND: 5156 fcport->login_pause = 1; 5157 tfcp->conflict = fcport; 5158 break; 5159 default: 5160 fcport->login_pause = 1; 5161 tfcp->conflict = fcport; 5162 dfcp = tfcp; 5163 break; 5164 } 5165 } 5166 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5167 if (dfcp) 5168 qlt_schedule_sess_for_deletion(tfcp); 5169 5170 if (N2N_TOPO(vha->hw)) { 5171 fcport->flags &= ~FCF_FABRIC_DEVICE; 5172 fcport->keep_nport_handle = 1; 5173 if (vha->flags.nvme_enabled) { 5174 fcport->fc4_type = 5175 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5176 fcport->n2n_flag = 1; 5177 } 5178 fcport->fw_login_state = 0; 5179 5180 schedule_delayed_work(&vha->scan.scan_work, 5); 5181 } else { 5182 qla24xx_fcport_handle_login(vha, fcport); 5183 } 5184 } 5185 } 5186 5187 if (free_fcport) { 5188 qla2x00_free_fcport(fcport); 5189 if (pla) { 5190 list_del(&pla->list); 5191 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5192 } 5193 } 5194 } 5195 5196 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5197 { 5198 struct srb *sp = e->u.iosb.sp; 5199 int rval; 5200 5201 rval = qla2x00_start_sp(sp); 5202 if (rval != QLA_SUCCESS) { 5203 ql_dbg(ql_dbg_disc, vha, 0x2043, 5204 "%s: %s: Re-issue IOCB failed (%d).\n", 5205 __func__, sp->name, rval); 5206 qla24xx_sp_unmap(vha, sp); 5207 } 5208 } 5209 5210 void 5211 qla2x00_do_work(struct scsi_qla_host *vha) 5212 { 5213 struct qla_work_evt *e, *tmp; 5214 unsigned long flags; 5215 LIST_HEAD(work); 5216 int rc; 5217 5218 spin_lock_irqsave(&vha->work_lock, flags); 5219 list_splice_init(&vha->work_list, &work); 5220 spin_unlock_irqrestore(&vha->work_lock, flags); 5221 5222 list_for_each_entry_safe(e, tmp, &work, list) { 5223 rc = QLA_SUCCESS; 5224 switch (e->type) { 5225 case QLA_EVT_AEN: 5226 fc_host_post_event(vha->host, fc_get_event_number(), 5227 e->u.aen.code, e->u.aen.data); 5228 break; 5229 case QLA_EVT_IDC_ACK: 5230 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5231 break; 5232 case QLA_EVT_ASYNC_LOGIN: 5233 qla2x00_async_login(vha, e->u.logio.fcport, 5234 e->u.logio.data); 5235 break; 5236 case QLA_EVT_ASYNC_LOGOUT: 5237 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5238 break; 5239 case QLA_EVT_ASYNC_ADISC: 5240 qla2x00_async_adisc(vha, e->u.logio.fcport, 5241 e->u.logio.data); 5242 break; 5243 case QLA_EVT_UEVENT: 5244 qla2x00_uevent_emit(vha, e->u.uevent.code); 5245 break; 5246 case QLA_EVT_AENFX: 5247 qlafx00_process_aen(vha, e); 5248 break; 5249 case QLA_EVT_GPNID: 5250 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5251 break; 5252 case QLA_EVT_UNMAP: 5253 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5254 break; 5255 case QLA_EVT_RELOGIN: 5256 qla2x00_relogin(vha); 5257 break; 5258 case QLA_EVT_NEW_SESS: 5259 qla24xx_create_new_sess(vha, e); 5260 break; 5261 case QLA_EVT_GPDB: 5262 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5263 e->u.fcport.opt); 5264 break; 5265 case QLA_EVT_PRLI: 5266 qla24xx_async_prli(vha, e->u.fcport.fcport); 5267 break; 5268 case QLA_EVT_GPSC: 5269 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5270 break; 5271 case QLA_EVT_GNL: 5272 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5273 break; 5274 case QLA_EVT_NACK: 5275 qla24xx_do_nack_work(vha, e); 5276 break; 5277 case QLA_EVT_ASYNC_PRLO: 5278 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5279 break; 5280 case QLA_EVT_ASYNC_PRLO_DONE: 5281 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5282 e->u.logio.data); 5283 break; 5284 case QLA_EVT_GPNFT: 5285 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5286 e->u.gpnft.sp); 5287 break; 5288 case QLA_EVT_GPNFT_DONE: 5289 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5290 break; 5291 case QLA_EVT_GNNFT_DONE: 5292 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5293 break; 5294 case QLA_EVT_GNNID: 5295 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5296 break; 5297 case QLA_EVT_GFPNID: 5298 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5299 break; 5300 case QLA_EVT_SP_RETRY: 5301 qla_sp_retry(vha, e); 5302 break; 5303 case QLA_EVT_IIDMA: 5304 qla_do_iidma_work(vha, e->u.fcport.fcport); 5305 break; 5306 case QLA_EVT_ELS_PLOGI: 5307 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5308 e->u.fcport.fcport, false); 5309 break; 5310 } 5311 5312 if (rc == EAGAIN) { 5313 /* put 'work' at head of 'vha->work_list' */ 5314 spin_lock_irqsave(&vha->work_lock, flags); 5315 list_splice(&work, &vha->work_list); 5316 spin_unlock_irqrestore(&vha->work_lock, flags); 5317 break; 5318 } 5319 list_del_init(&e->list); 5320 if (e->flags & QLA_EVT_FLAG_FREE) 5321 kfree(e); 5322 5323 /* For each work completed decrement vha ref count */ 5324 QLA_VHA_MARK_NOT_BUSY(vha); 5325 } 5326 } 5327 5328 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5329 { 5330 struct qla_work_evt *e; 5331 5332 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5333 5334 if (!e) { 5335 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5336 return QLA_FUNCTION_FAILED; 5337 } 5338 5339 return qla2x00_post_work(vha, e); 5340 } 5341 5342 /* Relogins all the fcports of a vport 5343 * Context: dpc thread 5344 */ 5345 void qla2x00_relogin(struct scsi_qla_host *vha) 5346 { 5347 fc_port_t *fcport; 5348 int status, relogin_needed = 0; 5349 struct event_arg ea; 5350 5351 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5352 /* 5353 * If the port is not ONLINE then try to login 5354 * to it if we haven't run out of retries. 5355 */ 5356 if (atomic_read(&fcport->state) != FCS_ONLINE && 5357 fcport->login_retry) { 5358 if (fcport->scan_state != QLA_FCPORT_FOUND || 5359 fcport->disc_state == DSC_LOGIN_COMPLETE) 5360 continue; 5361 5362 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5363 fcport->disc_state == DSC_DELETE_PEND) { 5364 relogin_needed = 1; 5365 } else { 5366 if (vha->hw->current_topology != ISP_CFG_NL) { 5367 memset(&ea, 0, sizeof(ea)); 5368 ea.fcport = fcport; 5369 qla24xx_handle_relogin_event(vha, &ea); 5370 } else if (vha->hw->current_topology == 5371 ISP_CFG_NL) { 5372 fcport->login_retry--; 5373 status = 5374 qla2x00_local_device_login(vha, 5375 fcport); 5376 if (status == QLA_SUCCESS) { 5377 fcport->old_loop_id = 5378 fcport->loop_id; 5379 ql_dbg(ql_dbg_disc, vha, 0x2003, 5380 "Port login OK: logged in ID 0x%x.\n", 5381 fcport->loop_id); 5382 qla2x00_update_fcport 5383 (vha, fcport); 5384 } else if (status == 1) { 5385 set_bit(RELOGIN_NEEDED, 5386 &vha->dpc_flags); 5387 /* retry the login again */ 5388 ql_dbg(ql_dbg_disc, vha, 0x2007, 5389 "Retrying %d login again loop_id 0x%x.\n", 5390 fcport->login_retry, 5391 fcport->loop_id); 5392 } else { 5393 fcport->login_retry = 0; 5394 } 5395 5396 if (fcport->login_retry == 0 && 5397 status != QLA_SUCCESS) 5398 qla2x00_clear_loop_id(fcport); 5399 } 5400 } 5401 } 5402 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5403 break; 5404 } 5405 5406 if (relogin_needed) 5407 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5408 5409 ql_dbg(ql_dbg_disc, vha, 0x400e, 5410 "Relogin end.\n"); 5411 } 5412 5413 /* Schedule work on any of the dpc-workqueues */ 5414 void 5415 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5416 { 5417 struct qla_hw_data *ha = base_vha->hw; 5418 5419 switch (work_code) { 5420 case MBA_IDC_AEN: /* 0x8200 */ 5421 if (ha->dpc_lp_wq) 5422 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5423 break; 5424 5425 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5426 if (!ha->flags.nic_core_reset_hdlr_active) { 5427 if (ha->dpc_hp_wq) 5428 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5429 } else 5430 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5431 "NIC Core reset is already active. Skip " 5432 "scheduling it again.\n"); 5433 break; 5434 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5435 if (ha->dpc_hp_wq) 5436 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5437 break; 5438 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5439 if (ha->dpc_hp_wq) 5440 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5441 break; 5442 default: 5443 ql_log(ql_log_warn, base_vha, 0xb05f, 5444 "Unknown work-code=0x%x.\n", work_code); 5445 } 5446 5447 return; 5448 } 5449 5450 /* Work: Perform NIC Core Unrecoverable state handling */ 5451 void 5452 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5453 { 5454 struct qla_hw_data *ha = 5455 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5456 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5457 uint32_t dev_state = 0; 5458 5459 qla83xx_idc_lock(base_vha, 0); 5460 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5461 qla83xx_reset_ownership(base_vha); 5462 if (ha->flags.nic_core_reset_owner) { 5463 ha->flags.nic_core_reset_owner = 0; 5464 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5465 QLA8XXX_DEV_FAILED); 5466 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5467 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5468 } 5469 qla83xx_idc_unlock(base_vha, 0); 5470 } 5471 5472 /* Work: Execute IDC state handler */ 5473 void 5474 qla83xx_idc_state_handler_work(struct work_struct *work) 5475 { 5476 struct qla_hw_data *ha = 5477 container_of(work, struct qla_hw_data, idc_state_handler); 5478 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5479 uint32_t dev_state = 0; 5480 5481 qla83xx_idc_lock(base_vha, 0); 5482 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5483 if (dev_state == QLA8XXX_DEV_FAILED || 5484 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5485 qla83xx_idc_state_handler(base_vha); 5486 qla83xx_idc_unlock(base_vha, 0); 5487 } 5488 5489 static int 5490 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5491 { 5492 int rval = QLA_SUCCESS; 5493 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5494 uint32_t heart_beat_counter1, heart_beat_counter2; 5495 5496 do { 5497 if (time_after(jiffies, heart_beat_wait)) { 5498 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5499 "Nic Core f/w is not alive.\n"); 5500 rval = QLA_FUNCTION_FAILED; 5501 break; 5502 } 5503 5504 qla83xx_idc_lock(base_vha, 0); 5505 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5506 &heart_beat_counter1); 5507 qla83xx_idc_unlock(base_vha, 0); 5508 msleep(100); 5509 qla83xx_idc_lock(base_vha, 0); 5510 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5511 &heart_beat_counter2); 5512 qla83xx_idc_unlock(base_vha, 0); 5513 } while (heart_beat_counter1 == heart_beat_counter2); 5514 5515 return rval; 5516 } 5517 5518 /* Work: Perform NIC Core Reset handling */ 5519 void 5520 qla83xx_nic_core_reset_work(struct work_struct *work) 5521 { 5522 struct qla_hw_data *ha = 5523 container_of(work, struct qla_hw_data, nic_core_reset); 5524 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5525 uint32_t dev_state = 0; 5526 5527 if (IS_QLA2031(ha)) { 5528 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5529 ql_log(ql_log_warn, base_vha, 0xb081, 5530 "Failed to dump mctp\n"); 5531 return; 5532 } 5533 5534 if (!ha->flags.nic_core_reset_hdlr_active) { 5535 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5536 qla83xx_idc_lock(base_vha, 0); 5537 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5538 &dev_state); 5539 qla83xx_idc_unlock(base_vha, 0); 5540 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5541 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5542 "Nic Core f/w is alive.\n"); 5543 return; 5544 } 5545 } 5546 5547 ha->flags.nic_core_reset_hdlr_active = 1; 5548 if (qla83xx_nic_core_reset(base_vha)) { 5549 /* NIC Core reset failed. */ 5550 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5551 "NIC Core reset failed.\n"); 5552 } 5553 ha->flags.nic_core_reset_hdlr_active = 0; 5554 } 5555 } 5556 5557 /* Work: Handle 8200 IDC aens */ 5558 void 5559 qla83xx_service_idc_aen(struct work_struct *work) 5560 { 5561 struct qla_hw_data *ha = 5562 container_of(work, struct qla_hw_data, idc_aen); 5563 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5564 uint32_t dev_state, idc_control; 5565 5566 qla83xx_idc_lock(base_vha, 0); 5567 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5568 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5569 qla83xx_idc_unlock(base_vha, 0); 5570 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5571 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5572 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5573 "Application requested NIC Core Reset.\n"); 5574 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5575 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5576 QLA_SUCCESS) { 5577 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5578 "Other protocol driver requested NIC Core Reset.\n"); 5579 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5580 } 5581 } else if (dev_state == QLA8XXX_DEV_FAILED || 5582 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5583 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5584 } 5585 } 5586 5587 static void 5588 qla83xx_wait_logic(void) 5589 { 5590 int i; 5591 5592 /* Yield CPU */ 5593 if (!in_interrupt()) { 5594 /* 5595 * Wait about 200ms before retrying again. 5596 * This controls the number of retries for single 5597 * lock operation. 5598 */ 5599 msleep(100); 5600 schedule(); 5601 } else { 5602 for (i = 0; i < 20; i++) 5603 cpu_relax(); /* This a nop instr on i386 */ 5604 } 5605 } 5606 5607 static int 5608 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5609 { 5610 int rval; 5611 uint32_t data; 5612 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5613 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5614 struct qla_hw_data *ha = base_vha->hw; 5615 5616 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5617 "Trying force recovery of the IDC lock.\n"); 5618 5619 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5620 if (rval) 5621 return rval; 5622 5623 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5624 return QLA_SUCCESS; 5625 } else { 5626 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5627 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5628 data); 5629 if (rval) 5630 return rval; 5631 5632 msleep(200); 5633 5634 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5635 &data); 5636 if (rval) 5637 return rval; 5638 5639 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5640 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5641 ~(idc_lck_rcvry_stage_mask)); 5642 rval = qla83xx_wr_reg(base_vha, 5643 QLA83XX_IDC_LOCK_RECOVERY, data); 5644 if (rval) 5645 return rval; 5646 5647 /* Forcefully perform IDC UnLock */ 5648 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5649 &data); 5650 if (rval) 5651 return rval; 5652 /* Clear lock-id by setting 0xff */ 5653 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5654 0xff); 5655 if (rval) 5656 return rval; 5657 /* Clear lock-recovery by setting 0x0 */ 5658 rval = qla83xx_wr_reg(base_vha, 5659 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5660 if (rval) 5661 return rval; 5662 } else 5663 return QLA_SUCCESS; 5664 } 5665 5666 return rval; 5667 } 5668 5669 static int 5670 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5671 { 5672 int rval = QLA_SUCCESS; 5673 uint32_t o_drv_lockid, n_drv_lockid; 5674 unsigned long lock_recovery_timeout; 5675 5676 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5677 retry_lockid: 5678 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5679 if (rval) 5680 goto exit; 5681 5682 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5683 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5684 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5685 return QLA_SUCCESS; 5686 else 5687 return QLA_FUNCTION_FAILED; 5688 } 5689 5690 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5691 if (rval) 5692 goto exit; 5693 5694 if (o_drv_lockid == n_drv_lockid) { 5695 qla83xx_wait_logic(); 5696 goto retry_lockid; 5697 } else 5698 return QLA_SUCCESS; 5699 5700 exit: 5701 return rval; 5702 } 5703 5704 void 5705 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5706 { 5707 uint32_t data; 5708 uint32_t lock_owner; 5709 struct qla_hw_data *ha = base_vha->hw; 5710 5711 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5712 retry_lock: 5713 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5714 == QLA_SUCCESS) { 5715 if (data) { 5716 /* Setting lock-id to our function-number */ 5717 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5718 ha->portnum); 5719 } else { 5720 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5721 &lock_owner); 5722 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5723 "Failed to acquire IDC lock, acquired by %d, " 5724 "retrying...\n", lock_owner); 5725 5726 /* Retry/Perform IDC-Lock recovery */ 5727 if (qla83xx_idc_lock_recovery(base_vha) 5728 == QLA_SUCCESS) { 5729 qla83xx_wait_logic(); 5730 goto retry_lock; 5731 } else 5732 ql_log(ql_log_warn, base_vha, 0xb075, 5733 "IDC Lock recovery FAILED.\n"); 5734 } 5735 5736 } 5737 5738 return; 5739 } 5740 5741 static bool 5742 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5743 struct purex_entry_24xx *purex) 5744 { 5745 char fwstr[16]; 5746 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5747 struct port_database_24xx *pdb; 5748 5749 /* Domain Controller is always logged-out. */ 5750 /* if RDP request is not from Domain Controller: */ 5751 if (sid != 0xfffc01) 5752 return false; 5753 5754 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5755 5756 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5757 if (!pdb) { 5758 ql_dbg(ql_dbg_init, vha, 0x0181, 5759 "%s: Failed allocate pdb\n", __func__); 5760 } else if (qla24xx_get_port_database(vha, purex->nport_handle, pdb)) { 5761 ql_dbg(ql_dbg_init, vha, 0x0181, 5762 "%s: Failed get pdb sid=%x\n", __func__, sid); 5763 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 5764 pdb->current_login_state != PDS_PRLI_COMPLETE) { 5765 ql_dbg(ql_dbg_init, vha, 0x0181, 5766 "%s: Port not logged in sid=%#x\n", __func__, sid); 5767 } else { 5768 /* RDP request is from logged in port */ 5769 kfree(pdb); 5770 return false; 5771 } 5772 kfree(pdb); 5773 5774 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 5775 fwstr[strcspn(fwstr, " ")] = 0; 5776 /* if FW version allows RDP response length upto 2048 bytes: */ 5777 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 5778 return false; 5779 5780 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 5781 5782 /* RDP response length is to be reduced to maximum 256 bytes */ 5783 return true; 5784 } 5785 5786 static uint 5787 qla25xx_rdp_port_speed_capability(struct qla_hw_data *ha) 5788 { 5789 if (IS_CNA_CAPABLE(ha)) 5790 return RDP_PORT_SPEED_10GB; 5791 5792 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 5793 unsigned int speeds = 0; 5794 5795 if (ha->max_supported_speed == 2) { 5796 if (ha->min_supported_speed <= 6) 5797 speeds |= RDP_PORT_SPEED_64GB; 5798 } 5799 5800 if (ha->max_supported_speed == 2 || 5801 ha->max_supported_speed == 1) { 5802 if (ha->min_supported_speed <= 5) 5803 speeds |= RDP_PORT_SPEED_32GB; 5804 } 5805 5806 if (ha->max_supported_speed == 2 || 5807 ha->max_supported_speed == 1 || 5808 ha->max_supported_speed == 0) { 5809 if (ha->min_supported_speed <= 4) 5810 speeds |= RDP_PORT_SPEED_16GB; 5811 } 5812 5813 if (ha->max_supported_speed == 1 || 5814 ha->max_supported_speed == 0) { 5815 if (ha->min_supported_speed <= 3) 5816 speeds |= RDP_PORT_SPEED_8GB; 5817 } 5818 5819 if (ha->max_supported_speed == 0) { 5820 if (ha->min_supported_speed <= 2) 5821 speeds |= RDP_PORT_SPEED_4GB; 5822 } 5823 5824 return speeds; 5825 } 5826 5827 if (IS_QLA2031(ha)) 5828 return RDP_PORT_SPEED_16GB|RDP_PORT_SPEED_8GB| 5829 RDP_PORT_SPEED_4GB; 5830 5831 if (IS_QLA25XX(ha)) 5832 return RDP_PORT_SPEED_8GB|RDP_PORT_SPEED_4GB| 5833 RDP_PORT_SPEED_2GB|RDP_PORT_SPEED_1GB; 5834 5835 if (IS_QLA24XX_TYPE(ha)) 5836 return RDP_PORT_SPEED_4GB|RDP_PORT_SPEED_2GB| 5837 RDP_PORT_SPEED_1GB; 5838 5839 if (IS_QLA23XX(ha)) 5840 return RDP_PORT_SPEED_2GB|RDP_PORT_SPEED_1GB; 5841 5842 return RDP_PORT_SPEED_1GB; 5843 } 5844 5845 static uint 5846 qla25xx_rdp_port_speed_currently(struct qla_hw_data *ha) 5847 { 5848 switch (ha->link_data_rate) { 5849 case PORT_SPEED_1GB: 5850 return RDP_PORT_SPEED_1GB; 5851 5852 case PORT_SPEED_2GB: 5853 return RDP_PORT_SPEED_2GB; 5854 5855 case PORT_SPEED_4GB: 5856 return RDP_PORT_SPEED_4GB; 5857 5858 case PORT_SPEED_8GB: 5859 return RDP_PORT_SPEED_8GB; 5860 5861 case PORT_SPEED_10GB: 5862 return RDP_PORT_SPEED_10GB; 5863 5864 case PORT_SPEED_16GB: 5865 return RDP_PORT_SPEED_16GB; 5866 5867 case PORT_SPEED_32GB: 5868 return RDP_PORT_SPEED_32GB; 5869 5870 case PORT_SPEED_64GB: 5871 return RDP_PORT_SPEED_64GB; 5872 5873 default: 5874 return RDP_PORT_SPEED_UNKNOWN; 5875 } 5876 } 5877 5878 /* 5879 * Function Name: qla24xx_process_purex_iocb 5880 * 5881 * Description: 5882 * Prepare a RDP response and send to Fabric switch 5883 * 5884 * PARAMETERS: 5885 * vha: SCSI qla host 5886 * purex: RDP request received by HBA 5887 */ 5888 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, void *pkt) 5889 { 5890 struct qla_hw_data *ha = vha->hw; 5891 struct purex_entry_24xx *purex = pkt; 5892 dma_addr_t rsp_els_dma; 5893 dma_addr_t rsp_payload_dma; 5894 dma_addr_t stat_dma; 5895 dma_addr_t bbc_dma; 5896 dma_addr_t sfp_dma; 5897 struct els_entry_24xx *rsp_els = NULL; 5898 struct rdp_rsp_payload *rsp_payload = NULL; 5899 struct link_statistics *stat = NULL; 5900 struct buffer_credit_24xx *bbc = NULL; 5901 uint8_t *sfp = NULL; 5902 uint16_t sfp_flags = 0; 5903 uint rsp_payload_length = sizeof(*rsp_payload); 5904 int rval; 5905 5906 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 5907 "%s: Enter\n", __func__); 5908 5909 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 5910 "-------- ELS REQ -------\n"); 5911 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 5912 (void *)purex, sizeof(*purex)); 5913 5914 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 5915 rsp_payload_length = 5916 offsetof(typeof(*rsp_payload), optical_elmt_desc); 5917 ql_dbg(ql_dbg_init, vha, 0x0181, 5918 "Reducing RSP payload length to %u bytes...\n", 5919 rsp_payload_length); 5920 } 5921 5922 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 5923 &rsp_els_dma, GFP_KERNEL); 5924 if (!rsp_els) { 5925 ql_log(ql_log_warn, vha, 0x0183, 5926 "Failed allocate dma buffer ELS RSP.\n"); 5927 goto dealloc; 5928 } 5929 5930 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 5931 &rsp_payload_dma, GFP_KERNEL); 5932 if (!rsp_payload) { 5933 ql_log(ql_log_warn, vha, 0x0184, 5934 "Failed allocate dma buffer ELS RSP payload.\n"); 5935 goto dealloc; 5936 } 5937 5938 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 5939 &sfp_dma, GFP_KERNEL); 5940 5941 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 5942 &stat_dma, GFP_KERNEL); 5943 5944 bbc = dma_alloc_coherent(&ha->pdev->dev, sizeof(*bbc), 5945 &bbc_dma, GFP_KERNEL); 5946 5947 /* Prepare Response IOCB */ 5948 rsp_els->entry_type = ELS_IOCB_TYPE; 5949 rsp_els->entry_count = 1; 5950 rsp_els->sys_define = 0; 5951 rsp_els->entry_status = 0; 5952 rsp_els->handle = 0; 5953 rsp_els->nport_handle = purex->nport_handle; 5954 rsp_els->tx_dsd_count = 1; 5955 rsp_els->vp_index = purex->vp_idx; 5956 rsp_els->sof_type = EST_SOFI3; 5957 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 5958 rsp_els->rx_dsd_count = 0; 5959 rsp_els->opcode = purex->els_frame_payload[0]; 5960 5961 rsp_els->d_id[0] = purex->s_id[0]; 5962 rsp_els->d_id[1] = purex->s_id[1]; 5963 rsp_els->d_id[2] = purex->s_id[2]; 5964 5965 rsp_els->control_flags = EPD_ELS_ACC; 5966 rsp_els->rx_byte_count = 0; 5967 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 5968 5969 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 5970 rsp_els->tx_len = rsp_els->tx_byte_count; 5971 5972 rsp_els->rx_address = 0; 5973 rsp_els->rx_len = 0; 5974 5975 /* Prepare Response Payload */ 5976 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 5977 rsp_payload->hdr.len = cpu_to_be32( 5978 rsp_els->tx_byte_count - sizeof(rsp_payload->hdr)); 5979 5980 /* Link service Request Info Descriptor */ 5981 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 5982 rsp_payload->ls_req_info_desc.desc_len = 5983 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 5984 rsp_payload->ls_req_info_desc.req_payload_word_0 = 5985 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 5986 5987 /* Link service Request Info Descriptor 2 */ 5988 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 5989 rsp_payload->ls_req_info_desc2.desc_len = 5990 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 5991 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 5992 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 5993 5994 5995 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 5996 rsp_payload->sfp_diag_desc.desc_len = 5997 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 5998 5999 if (sfp) { 6000 /* SFP Flags */ 6001 memset(sfp, 0, SFP_RTDI_LEN); 6002 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6003 if (!rval) { 6004 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6005 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6006 sfp_flags |= BIT_0; /* short wave */ 6007 else if (sfp[0] & BIT_1) 6008 sfp_flags |= BIT_1; /* long wave 1310nm */ 6009 else if (sfp[1] & BIT_4) 6010 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6011 } 6012 6013 /* SFP Type */ 6014 memset(sfp, 0, SFP_RTDI_LEN); 6015 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6016 if (!rval) { 6017 sfp_flags |= BIT_4; /* optical */ 6018 if (sfp[0] == 0x3) 6019 sfp_flags |= BIT_6; /* sfp+ */ 6020 } 6021 6022 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6023 6024 /* SFP Diagnostics */ 6025 memset(sfp, 0, SFP_RTDI_LEN); 6026 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6027 if (!rval) { 6028 uint16_t *trx = (void *)sfp; /* already be16 */ 6029 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6030 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6031 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6032 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6033 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6034 } 6035 } 6036 6037 /* Port Speed Descriptor */ 6038 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6039 rsp_payload->port_speed_desc.desc_len = 6040 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6041 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6042 qla25xx_rdp_port_speed_capability(ha)); 6043 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6044 qla25xx_rdp_port_speed_currently(ha)); 6045 6046 /* Link Error Status Descriptor */ 6047 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6048 rsp_payload->ls_err_desc.desc_len = 6049 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6050 6051 if (stat) { 6052 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6053 if (!rval) { 6054 rsp_payload->ls_err_desc.link_fail_cnt = 6055 cpu_to_be32(stat->link_fail_cnt); 6056 rsp_payload->ls_err_desc.loss_sync_cnt = 6057 cpu_to_be32(stat->loss_sync_cnt); 6058 rsp_payload->ls_err_desc.loss_sig_cnt = 6059 cpu_to_be32(stat->loss_sig_cnt); 6060 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6061 cpu_to_be32(stat->prim_seq_err_cnt); 6062 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6063 cpu_to_be32(stat->inval_xmit_word_cnt); 6064 rsp_payload->ls_err_desc.inval_crc_cnt = 6065 cpu_to_be32(stat->inval_crc_cnt); 6066 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6067 } 6068 } 6069 6070 /* Portname Descriptor */ 6071 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6072 rsp_payload->port_name_diag_desc.desc_len = 6073 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6074 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6075 vha->node_name, 6076 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6077 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6078 vha->port_name, 6079 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6080 6081 /* F-Port Portname Descriptor */ 6082 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6083 rsp_payload->port_name_direct_desc.desc_len = 6084 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6085 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6086 vha->fabric_node_name, 6087 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6088 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6089 vha->fabric_port_name, 6090 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6091 6092 /* Bufer Credit Descriptor */ 6093 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6094 rsp_payload->buffer_credit_desc.desc_len = 6095 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6096 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6097 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6098 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6099 6100 if (bbc) { 6101 memset(bbc, 0, sizeof(*bbc)); 6102 rval = qla24xx_get_buffer_credits(vha, bbc, bbc_dma); 6103 if (!rval) { 6104 rsp_payload->buffer_credit_desc.fcport_b2b = 6105 cpu_to_be32(LSW(bbc->parameter[0])); 6106 } 6107 } 6108 6109 if (rsp_payload_length < sizeof(*rsp_payload)) 6110 goto send; 6111 6112 /* Optical Element Descriptor, Temperature */ 6113 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6114 rsp_payload->optical_elmt_desc[0].desc_len = 6115 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6116 /* Optical Element Descriptor, Voltage */ 6117 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6118 rsp_payload->optical_elmt_desc[1].desc_len = 6119 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6120 /* Optical Element Descriptor, Tx Bias Current */ 6121 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6122 rsp_payload->optical_elmt_desc[2].desc_len = 6123 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6124 /* Optical Element Descriptor, Tx Power */ 6125 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6126 rsp_payload->optical_elmt_desc[3].desc_len = 6127 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6128 /* Optical Element Descriptor, Rx Power */ 6129 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6130 rsp_payload->optical_elmt_desc[4].desc_len = 6131 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6132 6133 if (sfp) { 6134 memset(sfp, 0, SFP_RTDI_LEN); 6135 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6136 if (!rval) { 6137 uint16_t *trx = (void *)sfp; /* already be16 */ 6138 6139 /* Optical Element Descriptor, Temperature */ 6140 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6141 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6142 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6143 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6144 rsp_payload->optical_elmt_desc[0].element_flags = 6145 cpu_to_be32(1 << 28); 6146 6147 /* Optical Element Descriptor, Voltage */ 6148 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6149 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6150 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6151 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6152 rsp_payload->optical_elmt_desc[1].element_flags = 6153 cpu_to_be32(2 << 28); 6154 6155 /* Optical Element Descriptor, Tx Bias Current */ 6156 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6157 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6158 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6159 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6160 rsp_payload->optical_elmt_desc[2].element_flags = 6161 cpu_to_be32(3 << 28); 6162 6163 /* Optical Element Descriptor, Tx Power */ 6164 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6165 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6166 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6167 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6168 rsp_payload->optical_elmt_desc[3].element_flags = 6169 cpu_to_be32(4 << 28); 6170 6171 /* Optical Element Descriptor, Rx Power */ 6172 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6173 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6174 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6175 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6176 rsp_payload->optical_elmt_desc[4].element_flags = 6177 cpu_to_be32(5 << 28); 6178 } 6179 6180 memset(sfp, 0, SFP_RTDI_LEN); 6181 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6182 if (!rval) { 6183 /* Temperature high/low alarm/warning */ 6184 rsp_payload->optical_elmt_desc[0].element_flags |= 6185 cpu_to_be32( 6186 (sfp[0] >> 7 & 1) << 3 | 6187 (sfp[0] >> 6 & 1) << 2 | 6188 (sfp[4] >> 7 & 1) << 1 | 6189 (sfp[4] >> 6 & 1) << 0); 6190 6191 /* Voltage high/low alarm/warning */ 6192 rsp_payload->optical_elmt_desc[1].element_flags |= 6193 cpu_to_be32( 6194 (sfp[0] >> 5 & 1) << 3 | 6195 (sfp[0] >> 4 & 1) << 2 | 6196 (sfp[4] >> 5 & 1) << 1 | 6197 (sfp[4] >> 4 & 1) << 0); 6198 6199 /* Tx Bias Current high/low alarm/warning */ 6200 rsp_payload->optical_elmt_desc[2].element_flags |= 6201 cpu_to_be32( 6202 (sfp[0] >> 3 & 1) << 3 | 6203 (sfp[0] >> 2 & 1) << 2 | 6204 (sfp[4] >> 3 & 1) << 1 | 6205 (sfp[4] >> 2 & 1) << 0); 6206 6207 /* Tx Power high/low alarm/warning */ 6208 rsp_payload->optical_elmt_desc[3].element_flags |= 6209 cpu_to_be32( 6210 (sfp[0] >> 1 & 1) << 3 | 6211 (sfp[0] >> 0 & 1) << 2 | 6212 (sfp[4] >> 1 & 1) << 1 | 6213 (sfp[4] >> 0 & 1) << 0); 6214 6215 /* Rx Power high/low alarm/warning */ 6216 rsp_payload->optical_elmt_desc[4].element_flags |= 6217 cpu_to_be32( 6218 (sfp[1] >> 7 & 1) << 3 | 6219 (sfp[1] >> 6 & 1) << 2 | 6220 (sfp[5] >> 7 & 1) << 1 | 6221 (sfp[5] >> 6 & 1) << 0); 6222 } 6223 } 6224 6225 /* Optical Product Data Descriptor */ 6226 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6227 rsp_payload->optical_prod_desc.desc_len = 6228 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6229 6230 if (sfp) { 6231 memset(sfp, 0, SFP_RTDI_LEN); 6232 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6233 if (!rval) { 6234 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6235 sfp + 0, 6236 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6237 memcpy(rsp_payload->optical_prod_desc.part_number, 6238 sfp + 20, 6239 sizeof(rsp_payload->optical_prod_desc.part_number)); 6240 memcpy(rsp_payload->optical_prod_desc.revision, 6241 sfp + 36, 6242 sizeof(rsp_payload->optical_prod_desc.revision)); 6243 memcpy(rsp_payload->optical_prod_desc.serial_number, 6244 sfp + 48, 6245 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6246 } 6247 6248 memset(sfp, 0, SFP_RTDI_LEN); 6249 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6250 if (!rval) { 6251 memcpy(rsp_payload->optical_prod_desc.date, 6252 sfp + 0, 6253 sizeof(rsp_payload->optical_prod_desc.date)); 6254 } 6255 } 6256 6257 send: 6258 ql_dbg(ql_dbg_init, vha, 0x0183, 6259 "Sending ELS Response to RDP Request...\n"); 6260 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6261 "-------- ELS RSP -------\n"); 6262 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6263 (void *)rsp_els, sizeof(*rsp_els)); 6264 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6265 "-------- ELS RSP PAYLOAD -------\n"); 6266 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6267 (void *)rsp_payload, rsp_payload_length); 6268 6269 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6270 6271 if (rval) { 6272 ql_log(ql_log_warn, vha, 0x0188, 6273 "%s: iocb failed to execute -> %x\n", __func__, rval); 6274 } else if (rsp_els->comp_status) { 6275 ql_log(ql_log_warn, vha, 0x0189, 6276 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6277 __func__, rsp_els->comp_status, 6278 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6279 } else { 6280 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6281 } 6282 6283 dealloc: 6284 if (bbc) 6285 dma_free_coherent(&ha->pdev->dev, sizeof(*bbc), 6286 bbc, bbc_dma); 6287 if (stat) 6288 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6289 stat, stat_dma); 6290 if (sfp) 6291 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6292 sfp, sfp_dma); 6293 if (rsp_payload) 6294 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6295 rsp_payload, rsp_payload_dma); 6296 if (rsp_els) 6297 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6298 rsp_els, rsp_els_dma); 6299 } 6300 6301 void qla24xx_process_purex_list(struct purex_list *list) 6302 { 6303 struct list_head head = LIST_HEAD_INIT(head); 6304 struct purex_item *item, *next; 6305 ulong flags; 6306 6307 spin_lock_irqsave(&list->lock, flags); 6308 list_splice_init(&list->head, &head); 6309 spin_unlock_irqrestore(&list->lock, flags); 6310 6311 list_for_each_entry_safe(item, next, &head, list) { 6312 list_del(&item->list); 6313 item->process_item(item->vha, &item->iocb); 6314 kfree(item); 6315 } 6316 } 6317 6318 void 6319 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6320 { 6321 #if 0 6322 uint16_t options = (requester_id << 15) | BIT_7; 6323 #endif 6324 uint16_t retry; 6325 uint32_t data; 6326 struct qla_hw_data *ha = base_vha->hw; 6327 6328 /* IDC-unlock implementation using driver-unlock/lock-id 6329 * remote registers 6330 */ 6331 retry = 0; 6332 retry_unlock: 6333 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6334 == QLA_SUCCESS) { 6335 if (data == ha->portnum) { 6336 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6337 /* Clearing lock-id by setting 0xff */ 6338 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6339 } else if (retry < 10) { 6340 /* SV: XXX: IDC unlock retrying needed here? */ 6341 6342 /* Retry for IDC-unlock */ 6343 qla83xx_wait_logic(); 6344 retry++; 6345 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6346 "Failed to release IDC lock, retrying=%d\n", retry); 6347 goto retry_unlock; 6348 } 6349 } else if (retry < 10) { 6350 /* Retry for IDC-unlock */ 6351 qla83xx_wait_logic(); 6352 retry++; 6353 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6354 "Failed to read drv-lockid, retrying=%d\n", retry); 6355 goto retry_unlock; 6356 } 6357 6358 return; 6359 6360 #if 0 6361 /* XXX: IDC-unlock implementation using access-control mbx */ 6362 retry = 0; 6363 retry_unlock2: 6364 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6365 if (retry < 10) { 6366 /* Retry for IDC-unlock */ 6367 qla83xx_wait_logic(); 6368 retry++; 6369 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6370 "Failed to release IDC lock, retrying=%d\n", retry); 6371 goto retry_unlock2; 6372 } 6373 } 6374 6375 return; 6376 #endif 6377 } 6378 6379 int 6380 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6381 { 6382 int rval = QLA_SUCCESS; 6383 struct qla_hw_data *ha = vha->hw; 6384 uint32_t drv_presence; 6385 6386 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6387 if (rval == QLA_SUCCESS) { 6388 drv_presence |= (1 << ha->portnum); 6389 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6390 drv_presence); 6391 } 6392 6393 return rval; 6394 } 6395 6396 int 6397 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6398 { 6399 int rval = QLA_SUCCESS; 6400 6401 qla83xx_idc_lock(vha, 0); 6402 rval = __qla83xx_set_drv_presence(vha); 6403 qla83xx_idc_unlock(vha, 0); 6404 6405 return rval; 6406 } 6407 6408 int 6409 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6410 { 6411 int rval = QLA_SUCCESS; 6412 struct qla_hw_data *ha = vha->hw; 6413 uint32_t drv_presence; 6414 6415 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6416 if (rval == QLA_SUCCESS) { 6417 drv_presence &= ~(1 << ha->portnum); 6418 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6419 drv_presence); 6420 } 6421 6422 return rval; 6423 } 6424 6425 int 6426 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6427 { 6428 int rval = QLA_SUCCESS; 6429 6430 qla83xx_idc_lock(vha, 0); 6431 rval = __qla83xx_clear_drv_presence(vha); 6432 qla83xx_idc_unlock(vha, 0); 6433 6434 return rval; 6435 } 6436 6437 static void 6438 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6439 { 6440 struct qla_hw_data *ha = vha->hw; 6441 uint32_t drv_ack, drv_presence; 6442 unsigned long ack_timeout; 6443 6444 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6445 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6446 while (1) { 6447 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6448 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6449 if ((drv_ack & drv_presence) == drv_presence) 6450 break; 6451 6452 if (time_after_eq(jiffies, ack_timeout)) { 6453 ql_log(ql_log_warn, vha, 0xb067, 6454 "RESET ACK TIMEOUT! drv_presence=0x%x " 6455 "drv_ack=0x%x\n", drv_presence, drv_ack); 6456 /* 6457 * The function(s) which did not ack in time are forced 6458 * to withdraw any further participation in the IDC 6459 * reset. 6460 */ 6461 if (drv_ack != drv_presence) 6462 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6463 drv_ack); 6464 break; 6465 } 6466 6467 qla83xx_idc_unlock(vha, 0); 6468 msleep(1000); 6469 qla83xx_idc_lock(vha, 0); 6470 } 6471 6472 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6473 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6474 } 6475 6476 static int 6477 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6478 { 6479 int rval = QLA_SUCCESS; 6480 uint32_t idc_control; 6481 6482 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6483 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6484 6485 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6486 __qla83xx_get_idc_control(vha, &idc_control); 6487 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6488 __qla83xx_set_idc_control(vha, 0); 6489 6490 qla83xx_idc_unlock(vha, 0); 6491 rval = qla83xx_restart_nic_firmware(vha); 6492 qla83xx_idc_lock(vha, 0); 6493 6494 if (rval != QLA_SUCCESS) { 6495 ql_log(ql_log_fatal, vha, 0xb06a, 6496 "Failed to restart NIC f/w.\n"); 6497 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6498 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6499 } else { 6500 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6501 "Success in restarting nic f/w.\n"); 6502 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6503 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6504 } 6505 6506 return rval; 6507 } 6508 6509 /* Assumes idc_lock always held on entry */ 6510 int 6511 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6512 { 6513 struct qla_hw_data *ha = base_vha->hw; 6514 int rval = QLA_SUCCESS; 6515 unsigned long dev_init_timeout; 6516 uint32_t dev_state; 6517 6518 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6519 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6520 6521 while (1) { 6522 6523 if (time_after_eq(jiffies, dev_init_timeout)) { 6524 ql_log(ql_log_warn, base_vha, 0xb06e, 6525 "Initialization TIMEOUT!\n"); 6526 /* Init timeout. Disable further NIC Core 6527 * communication. 6528 */ 6529 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6530 QLA8XXX_DEV_FAILED); 6531 ql_log(ql_log_info, base_vha, 0xb06f, 6532 "HW State: FAILED.\n"); 6533 } 6534 6535 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6536 switch (dev_state) { 6537 case QLA8XXX_DEV_READY: 6538 if (ha->flags.nic_core_reset_owner) 6539 qla83xx_idc_audit(base_vha, 6540 IDC_AUDIT_COMPLETION); 6541 ha->flags.nic_core_reset_owner = 0; 6542 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6543 "Reset_owner reset by 0x%x.\n", 6544 ha->portnum); 6545 goto exit; 6546 case QLA8XXX_DEV_COLD: 6547 if (ha->flags.nic_core_reset_owner) 6548 rval = qla83xx_device_bootstrap(base_vha); 6549 else { 6550 /* Wait for AEN to change device-state */ 6551 qla83xx_idc_unlock(base_vha, 0); 6552 msleep(1000); 6553 qla83xx_idc_lock(base_vha, 0); 6554 } 6555 break; 6556 case QLA8XXX_DEV_INITIALIZING: 6557 /* Wait for AEN to change device-state */ 6558 qla83xx_idc_unlock(base_vha, 0); 6559 msleep(1000); 6560 qla83xx_idc_lock(base_vha, 0); 6561 break; 6562 case QLA8XXX_DEV_NEED_RESET: 6563 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6564 qla83xx_need_reset_handler(base_vha); 6565 else { 6566 /* Wait for AEN to change device-state */ 6567 qla83xx_idc_unlock(base_vha, 0); 6568 msleep(1000); 6569 qla83xx_idc_lock(base_vha, 0); 6570 } 6571 /* reset timeout value after need reset handler */ 6572 dev_init_timeout = jiffies + 6573 (ha->fcoe_dev_init_timeout * HZ); 6574 break; 6575 case QLA8XXX_DEV_NEED_QUIESCENT: 6576 /* XXX: DEBUG for now */ 6577 qla83xx_idc_unlock(base_vha, 0); 6578 msleep(1000); 6579 qla83xx_idc_lock(base_vha, 0); 6580 break; 6581 case QLA8XXX_DEV_QUIESCENT: 6582 /* XXX: DEBUG for now */ 6583 if (ha->flags.quiesce_owner) 6584 goto exit; 6585 6586 qla83xx_idc_unlock(base_vha, 0); 6587 msleep(1000); 6588 qla83xx_idc_lock(base_vha, 0); 6589 dev_init_timeout = jiffies + 6590 (ha->fcoe_dev_init_timeout * HZ); 6591 break; 6592 case QLA8XXX_DEV_FAILED: 6593 if (ha->flags.nic_core_reset_owner) 6594 qla83xx_idc_audit(base_vha, 6595 IDC_AUDIT_COMPLETION); 6596 ha->flags.nic_core_reset_owner = 0; 6597 __qla83xx_clear_drv_presence(base_vha); 6598 qla83xx_idc_unlock(base_vha, 0); 6599 qla8xxx_dev_failed_handler(base_vha); 6600 rval = QLA_FUNCTION_FAILED; 6601 qla83xx_idc_lock(base_vha, 0); 6602 goto exit; 6603 case QLA8XXX_BAD_VALUE: 6604 qla83xx_idc_unlock(base_vha, 0); 6605 msleep(1000); 6606 qla83xx_idc_lock(base_vha, 0); 6607 break; 6608 default: 6609 ql_log(ql_log_warn, base_vha, 0xb071, 6610 "Unknown Device State: %x.\n", dev_state); 6611 qla83xx_idc_unlock(base_vha, 0); 6612 qla8xxx_dev_failed_handler(base_vha); 6613 rval = QLA_FUNCTION_FAILED; 6614 qla83xx_idc_lock(base_vha, 0); 6615 goto exit; 6616 } 6617 } 6618 6619 exit: 6620 return rval; 6621 } 6622 6623 void 6624 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6625 { 6626 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6627 board_disable); 6628 struct pci_dev *pdev = ha->pdev; 6629 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6630 6631 /* 6632 * if UNLOAD flag is already set, then continue unload, 6633 * where it was set first. 6634 */ 6635 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6636 return; 6637 6638 ql_log(ql_log_warn, base_vha, 0x015b, 6639 "Disabling adapter.\n"); 6640 6641 if (!atomic_read(&pdev->enable_cnt)) { 6642 ql_log(ql_log_info, base_vha, 0xfffc, 6643 "PCI device disabled, no action req for PCI error=%lx\n", 6644 base_vha->pci_flags); 6645 return; 6646 } 6647 6648 qla2x00_wait_for_sess_deletion(base_vha); 6649 6650 set_bit(UNLOADING, &base_vha->dpc_flags); 6651 6652 qla2x00_delete_all_vps(ha, base_vha); 6653 6654 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6655 6656 qla2x00_dfs_remove(base_vha); 6657 6658 qla84xx_put_chip(base_vha); 6659 6660 if (base_vha->timer_active) 6661 qla2x00_stop_timer(base_vha); 6662 6663 base_vha->flags.online = 0; 6664 6665 qla2x00_destroy_deferred_work(ha); 6666 6667 /* 6668 * Do not try to stop beacon blink as it will issue a mailbox 6669 * command. 6670 */ 6671 qla2x00_free_sysfs_attr(base_vha, false); 6672 6673 fc_remove_host(base_vha->host); 6674 6675 scsi_remove_host(base_vha->host); 6676 6677 base_vha->flags.init_done = 0; 6678 qla25xx_delete_queues(base_vha); 6679 qla2x00_free_fcports(base_vha); 6680 qla2x00_free_irqs(base_vha); 6681 qla2x00_mem_free(ha); 6682 qla82xx_md_free(base_vha); 6683 qla2x00_free_queues(ha); 6684 6685 qla2x00_unmap_iobases(ha); 6686 6687 pci_release_selected_regions(ha->pdev, ha->bars); 6688 pci_disable_pcie_error_reporting(pdev); 6689 pci_disable_device(pdev); 6690 6691 /* 6692 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6693 */ 6694 } 6695 6696 /************************************************************************** 6697 * qla2x00_do_dpc 6698 * This kernel thread is a task that is schedule by the interrupt handler 6699 * to perform the background processing for interrupts. 6700 * 6701 * Notes: 6702 * This task always run in the context of a kernel thread. It 6703 * is kick-off by the driver's detect code and starts up 6704 * up one per adapter. It immediately goes to sleep and waits for 6705 * some fibre event. When either the interrupt handler or 6706 * the timer routine detects a event it will one of the task 6707 * bits then wake us up. 6708 **************************************************************************/ 6709 static int 6710 qla2x00_do_dpc(void *data) 6711 { 6712 scsi_qla_host_t *base_vha; 6713 struct qla_hw_data *ha; 6714 uint32_t online; 6715 struct qla_qpair *qpair; 6716 6717 ha = (struct qla_hw_data *)data; 6718 base_vha = pci_get_drvdata(ha->pdev); 6719 6720 set_user_nice(current, MIN_NICE); 6721 6722 set_current_state(TASK_INTERRUPTIBLE); 6723 while (!kthread_should_stop()) { 6724 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6725 "DPC handler sleeping.\n"); 6726 6727 schedule(); 6728 6729 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6730 goto end_loop; 6731 6732 if (ha->flags.eeh_busy) { 6733 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6734 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6735 goto end_loop; 6736 } 6737 6738 ha->dpc_active = 1; 6739 6740 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6741 "DPC handler waking up, dpc_flags=0x%lx.\n", 6742 base_vha->dpc_flags); 6743 6744 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6745 break; 6746 6747 if (IS_P3P_TYPE(ha)) { 6748 if (IS_QLA8044(ha)) { 6749 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6750 &base_vha->dpc_flags)) { 6751 qla8044_idc_lock(ha); 6752 qla8044_wr_direct(base_vha, 6753 QLA8044_CRB_DEV_STATE_INDEX, 6754 QLA8XXX_DEV_FAILED); 6755 qla8044_idc_unlock(ha); 6756 ql_log(ql_log_info, base_vha, 0x4004, 6757 "HW State: FAILED.\n"); 6758 qla8044_device_state_handler(base_vha); 6759 continue; 6760 } 6761 6762 } else { 6763 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6764 &base_vha->dpc_flags)) { 6765 qla82xx_idc_lock(ha); 6766 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6767 QLA8XXX_DEV_FAILED); 6768 qla82xx_idc_unlock(ha); 6769 ql_log(ql_log_info, base_vha, 0x0151, 6770 "HW State: FAILED.\n"); 6771 qla82xx_device_state_handler(base_vha); 6772 continue; 6773 } 6774 } 6775 6776 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6777 &base_vha->dpc_flags)) { 6778 6779 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6780 "FCoE context reset scheduled.\n"); 6781 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6782 &base_vha->dpc_flags))) { 6783 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6784 /* FCoE-ctx reset failed. 6785 * Escalate to chip-reset 6786 */ 6787 set_bit(ISP_ABORT_NEEDED, 6788 &base_vha->dpc_flags); 6789 } 6790 clear_bit(ABORT_ISP_ACTIVE, 6791 &base_vha->dpc_flags); 6792 } 6793 6794 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6795 "FCoE context reset end.\n"); 6796 } 6797 } else if (IS_QLAFX00(ha)) { 6798 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6799 &base_vha->dpc_flags)) { 6800 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6801 "Firmware Reset Recovery\n"); 6802 if (qlafx00_reset_initialize(base_vha)) { 6803 /* Failed. Abort isp later. */ 6804 if (!test_bit(UNLOADING, 6805 &base_vha->dpc_flags)) { 6806 set_bit(ISP_UNRECOVERABLE, 6807 &base_vha->dpc_flags); 6808 ql_dbg(ql_dbg_dpc, base_vha, 6809 0x4021, 6810 "Reset Recovery Failed\n"); 6811 } 6812 } 6813 } 6814 6815 if (test_and_clear_bit(FX00_TARGET_SCAN, 6816 &base_vha->dpc_flags)) { 6817 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6818 "ISPFx00 Target Scan scheduled\n"); 6819 if (qlafx00_rescan_isp(base_vha)) { 6820 if (!test_bit(UNLOADING, 6821 &base_vha->dpc_flags)) 6822 set_bit(ISP_UNRECOVERABLE, 6823 &base_vha->dpc_flags); 6824 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6825 "ISPFx00 Target Scan Failed\n"); 6826 } 6827 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6828 "ISPFx00 Target Scan End\n"); 6829 } 6830 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6831 &base_vha->dpc_flags)) { 6832 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6833 "ISPFx00 Host Info resend scheduled\n"); 6834 qlafx00_fx_disc(base_vha, 6835 &base_vha->hw->mr.fcport, 6836 FXDISC_REG_HOST_INFO); 6837 } 6838 } 6839 6840 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6841 &base_vha->dpc_flags)) { 6842 /* Semantic: 6843 * - NO-OP -- await next ISP-ABORT. Preferred method 6844 * to minimize disruptions that will occur 6845 * when a forced chip-reset occurs. 6846 * - Force -- ISP-ABORT scheduled. 6847 */ 6848 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 6849 } 6850 6851 if (test_and_clear_bit 6852 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6853 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6854 bool do_reset = true; 6855 6856 switch (base_vha->qlini_mode) { 6857 case QLA2XXX_INI_MODE_ENABLED: 6858 break; 6859 case QLA2XXX_INI_MODE_DISABLED: 6860 if (!qla_tgt_mode_enabled(base_vha) && 6861 !ha->flags.fw_started) 6862 do_reset = false; 6863 break; 6864 case QLA2XXX_INI_MODE_DUAL: 6865 if (!qla_dual_mode_enabled(base_vha) && 6866 !ha->flags.fw_started) 6867 do_reset = false; 6868 break; 6869 default: 6870 break; 6871 } 6872 6873 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6874 &base_vha->dpc_flags))) { 6875 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6876 "ISP abort scheduled.\n"); 6877 if (ha->isp_ops->abort_isp(base_vha)) { 6878 /* failed. retry later */ 6879 set_bit(ISP_ABORT_NEEDED, 6880 &base_vha->dpc_flags); 6881 } 6882 clear_bit(ABORT_ISP_ACTIVE, 6883 &base_vha->dpc_flags); 6884 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6885 "ISP abort end.\n"); 6886 } 6887 } 6888 6889 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 6890 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 6891 qla24xx_process_purex_list 6892 (&base_vha->purex_list); 6893 clear_bit(PROCESS_PUREX_IOCB, 6894 &base_vha->dpc_flags); 6895 } 6896 } 6897 6898 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6899 &base_vha->dpc_flags)) { 6900 qla2x00_update_fcports(base_vha); 6901 } 6902 6903 if (IS_QLAFX00(ha)) 6904 goto loop_resync_check; 6905 6906 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6907 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6908 "Quiescence mode scheduled.\n"); 6909 if (IS_P3P_TYPE(ha)) { 6910 if (IS_QLA82XX(ha)) 6911 qla82xx_device_state_handler(base_vha); 6912 if (IS_QLA8044(ha)) 6913 qla8044_device_state_handler(base_vha); 6914 clear_bit(ISP_QUIESCE_NEEDED, 6915 &base_vha->dpc_flags); 6916 if (!ha->flags.quiesce_owner) { 6917 qla2x00_perform_loop_resync(base_vha); 6918 if (IS_QLA82XX(ha)) { 6919 qla82xx_idc_lock(ha); 6920 qla82xx_clear_qsnt_ready( 6921 base_vha); 6922 qla82xx_idc_unlock(ha); 6923 } else if (IS_QLA8044(ha)) { 6924 qla8044_idc_lock(ha); 6925 qla8044_clear_qsnt_ready( 6926 base_vha); 6927 qla8044_idc_unlock(ha); 6928 } 6929 } 6930 } else { 6931 clear_bit(ISP_QUIESCE_NEEDED, 6932 &base_vha->dpc_flags); 6933 qla2x00_quiesce_io(base_vha); 6934 } 6935 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6936 "Quiescence mode end.\n"); 6937 } 6938 6939 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6940 &base_vha->dpc_flags) && 6941 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6942 6943 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6944 "Reset marker scheduled.\n"); 6945 qla2x00_rst_aen(base_vha); 6946 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6947 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6948 "Reset marker end.\n"); 6949 } 6950 6951 /* Retry each device up to login retry count */ 6952 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6953 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6954 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6955 6956 if (!base_vha->relogin_jif || 6957 time_after_eq(jiffies, base_vha->relogin_jif)) { 6958 base_vha->relogin_jif = jiffies + HZ; 6959 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6960 6961 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6962 "Relogin scheduled.\n"); 6963 qla24xx_post_relogin_work(base_vha); 6964 } 6965 } 6966 loop_resync_check: 6967 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6968 &base_vha->dpc_flags)) { 6969 6970 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6971 "Loop resync scheduled.\n"); 6972 6973 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6974 &base_vha->dpc_flags))) { 6975 6976 qla2x00_loop_resync(base_vha); 6977 6978 clear_bit(LOOP_RESYNC_ACTIVE, 6979 &base_vha->dpc_flags); 6980 } 6981 6982 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6983 "Loop resync end.\n"); 6984 } 6985 6986 if (IS_QLAFX00(ha)) 6987 goto intr_on_check; 6988 6989 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6990 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6991 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6992 qla2xxx_flash_npiv_conf(base_vha); 6993 } 6994 6995 intr_on_check: 6996 if (!ha->interrupts_on) 6997 ha->isp_ops->enable_intrs(ha); 6998 6999 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7000 &base_vha->dpc_flags)) { 7001 if (ha->beacon_blink_led == 1) 7002 ha->isp_ops->beacon_blink(base_vha); 7003 } 7004 7005 /* qpair online check */ 7006 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7007 &base_vha->dpc_flags)) { 7008 if (ha->flags.eeh_busy || 7009 ha->flags.pci_channel_io_perm_failure) 7010 online = 0; 7011 else 7012 online = 1; 7013 7014 mutex_lock(&ha->mq_lock); 7015 list_for_each_entry(qpair, &base_vha->qp_list, 7016 qp_list_elem) 7017 qpair->online = online; 7018 mutex_unlock(&ha->mq_lock); 7019 } 7020 7021 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, 7022 &base_vha->dpc_flags)) { 7023 ql_log(ql_log_info, base_vha, 0xffffff, 7024 "nvme: SET ZIO Activity exchange threshold to %d.\n", 7025 ha->nvme_last_rptd_aen); 7026 if (qla27xx_set_zio_threshold(base_vha, 7027 ha->nvme_last_rptd_aen)) { 7028 ql_log(ql_log_info, base_vha, 0xffffff, 7029 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 7030 ha->nvme_last_rptd_aen); 7031 } 7032 } 7033 7034 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7035 &base_vha->dpc_flags)) { 7036 ql_log(ql_log_info, base_vha, 0xffffff, 7037 "SET ZIO Activity exchange threshold to %d.\n", 7038 ha->last_zio_threshold); 7039 qla27xx_set_zio_threshold(base_vha, 7040 ha->last_zio_threshold); 7041 } 7042 7043 if (!IS_QLAFX00(ha)) 7044 qla2x00_do_dpc_all_vps(base_vha); 7045 7046 if (test_and_clear_bit(N2N_LINK_RESET, 7047 &base_vha->dpc_flags)) { 7048 qla2x00_lip_reset(base_vha); 7049 } 7050 7051 ha->dpc_active = 0; 7052 end_loop: 7053 set_current_state(TASK_INTERRUPTIBLE); 7054 } /* End of while(1) */ 7055 __set_current_state(TASK_RUNNING); 7056 7057 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7058 "DPC handler exiting.\n"); 7059 7060 /* 7061 * Make sure that nobody tries to wake us up again. 7062 */ 7063 ha->dpc_active = 0; 7064 7065 /* Cleanup any residual CTX SRBs. */ 7066 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 7067 7068 return 0; 7069 } 7070 7071 void 7072 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7073 { 7074 struct qla_hw_data *ha = vha->hw; 7075 struct task_struct *t = ha->dpc_thread; 7076 7077 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7078 wake_up_process(t); 7079 } 7080 7081 /* 7082 * qla2x00_rst_aen 7083 * Processes asynchronous reset. 7084 * 7085 * Input: 7086 * ha = adapter block pointer. 7087 */ 7088 static void 7089 qla2x00_rst_aen(scsi_qla_host_t *vha) 7090 { 7091 if (vha->flags.online && !vha->flags.reset_active && 7092 !atomic_read(&vha->loop_down_timer) && 7093 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7094 do { 7095 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7096 7097 /* 7098 * Issue marker command only when we are going to start 7099 * the I/O. 7100 */ 7101 vha->marker_needed = 1; 7102 } while (!atomic_read(&vha->loop_down_timer) && 7103 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7104 } 7105 } 7106 7107 /************************************************************************** 7108 * qla2x00_timer 7109 * 7110 * Description: 7111 * One second timer 7112 * 7113 * Context: Interrupt 7114 ***************************************************************************/ 7115 void 7116 qla2x00_timer(struct timer_list *t) 7117 { 7118 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7119 unsigned long cpu_flags = 0; 7120 int start_dpc = 0; 7121 int index; 7122 srb_t *sp; 7123 uint16_t w; 7124 struct qla_hw_data *ha = vha->hw; 7125 struct req_que *req; 7126 7127 if (ha->flags.eeh_busy) { 7128 ql_dbg(ql_dbg_timer, vha, 0x6000, 7129 "EEH = %d, restarting timer.\n", 7130 ha->flags.eeh_busy); 7131 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7132 return; 7133 } 7134 7135 /* 7136 * Hardware read to raise pending EEH errors during mailbox waits. If 7137 * the read returns -1 then disable the board. 7138 */ 7139 if (!pci_channel_offline(ha->pdev)) { 7140 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7141 qla2x00_check_reg16_for_disconnect(vha, w); 7142 } 7143 7144 /* Make sure qla82xx_watchdog is run only for physical port */ 7145 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7146 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7147 start_dpc++; 7148 if (IS_QLA82XX(ha)) 7149 qla82xx_watchdog(vha); 7150 else if (IS_QLA8044(ha)) 7151 qla8044_watchdog(vha); 7152 } 7153 7154 if (!vha->vp_idx && IS_QLAFX00(ha)) 7155 qlafx00_timer_routine(vha); 7156 7157 /* Loop down handler. */ 7158 if (atomic_read(&vha->loop_down_timer) > 0 && 7159 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7160 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7161 && vha->flags.online) { 7162 7163 if (atomic_read(&vha->loop_down_timer) == 7164 vha->loop_down_abort_time) { 7165 7166 ql_log(ql_log_info, vha, 0x6008, 7167 "Loop down - aborting the queues before time expires.\n"); 7168 7169 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7170 atomic_set(&vha->loop_state, LOOP_DEAD); 7171 7172 /* 7173 * Schedule an ISP abort to return any FCP2-device 7174 * commands. 7175 */ 7176 /* NPIV - scan physical port only */ 7177 if (!vha->vp_idx) { 7178 spin_lock_irqsave(&ha->hardware_lock, 7179 cpu_flags); 7180 req = ha->req_q_map[0]; 7181 for (index = 1; 7182 index < req->num_outstanding_cmds; 7183 index++) { 7184 fc_port_t *sfcp; 7185 7186 sp = req->outstanding_cmds[index]; 7187 if (!sp) 7188 continue; 7189 if (sp->cmd_type != TYPE_SRB) 7190 continue; 7191 if (sp->type != SRB_SCSI_CMD) 7192 continue; 7193 sfcp = sp->fcport; 7194 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7195 continue; 7196 7197 if (IS_QLA82XX(ha)) 7198 set_bit(FCOE_CTX_RESET_NEEDED, 7199 &vha->dpc_flags); 7200 else 7201 set_bit(ISP_ABORT_NEEDED, 7202 &vha->dpc_flags); 7203 break; 7204 } 7205 spin_unlock_irqrestore(&ha->hardware_lock, 7206 cpu_flags); 7207 } 7208 start_dpc++; 7209 } 7210 7211 /* if the loop has been down for 4 minutes, reinit adapter */ 7212 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7213 if (!(vha->device_flags & DFLG_NO_CABLE)) { 7214 ql_log(ql_log_warn, vha, 0x6009, 7215 "Loop down - aborting ISP.\n"); 7216 7217 if (IS_QLA82XX(ha)) 7218 set_bit(FCOE_CTX_RESET_NEEDED, 7219 &vha->dpc_flags); 7220 else 7221 set_bit(ISP_ABORT_NEEDED, 7222 &vha->dpc_flags); 7223 } 7224 } 7225 ql_dbg(ql_dbg_timer, vha, 0x600a, 7226 "Loop down - seconds remaining %d.\n", 7227 atomic_read(&vha->loop_down_timer)); 7228 } 7229 /* Check if beacon LED needs to be blinked for physical host only */ 7230 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7231 /* There is no beacon_blink function for ISP82xx */ 7232 if (!IS_P3P_TYPE(ha)) { 7233 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7234 start_dpc++; 7235 } 7236 } 7237 7238 /* Process any deferred work. */ 7239 if (!list_empty(&vha->work_list)) { 7240 unsigned long flags; 7241 bool q = false; 7242 7243 spin_lock_irqsave(&vha->work_lock, flags); 7244 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7245 q = true; 7246 spin_unlock_irqrestore(&vha->work_lock, flags); 7247 if (q) 7248 queue_work(vha->hw->wq, &vha->iocb_work); 7249 } 7250 7251 /* 7252 * FC-NVME 7253 * see if the active AEN count has changed from what was last reported. 7254 */ 7255 if (!vha->vp_idx && 7256 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) && 7257 ha->zio_mode == QLA_ZIO_MODE_6 && 7258 !ha->flags.host_shutting_down) { 7259 ql_log(ql_log_info, vha, 0x3002, 7260 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7261 ha->nvme_last_rptd_aen); 7262 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7263 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7264 start_dpc++; 7265 } 7266 7267 if (!vha->vp_idx && 7268 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) && 7269 (ha->zio_mode == QLA_ZIO_MODE_6) && 7270 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) { 7271 ql_log(ql_log_info, vha, 0x3002, 7272 "Sched: Set ZIO exchange threshold to %d.\n", 7273 ha->last_zio_threshold); 7274 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7275 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7276 start_dpc++; 7277 } 7278 7279 /* Schedule the DPC routine if needed */ 7280 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7281 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7282 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 7283 start_dpc || 7284 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7285 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7286 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7287 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7288 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7289 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7290 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7291 ql_dbg(ql_dbg_timer, vha, 0x600b, 7292 "isp_abort_needed=%d loop_resync_needed=%d " 7293 "fcport_update_needed=%d start_dpc=%d " 7294 "reset_marker_needed=%d", 7295 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7296 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7297 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 7298 start_dpc, 7299 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7300 ql_dbg(ql_dbg_timer, vha, 0x600c, 7301 "beacon_blink_needed=%d isp_unrecoverable=%d " 7302 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7303 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7304 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7305 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7306 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7307 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7308 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7309 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7310 qla2xxx_wake_dpc(vha); 7311 } 7312 7313 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7314 } 7315 7316 /* Firmware interface routines. */ 7317 7318 #define FW_ISP21XX 0 7319 #define FW_ISP22XX 1 7320 #define FW_ISP2300 2 7321 #define FW_ISP2322 3 7322 #define FW_ISP24XX 4 7323 #define FW_ISP25XX 5 7324 #define FW_ISP81XX 6 7325 #define FW_ISP82XX 7 7326 #define FW_ISP2031 8 7327 #define FW_ISP8031 9 7328 #define FW_ISP27XX 10 7329 #define FW_ISP28XX 11 7330 7331 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7332 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7333 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7334 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7335 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7336 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7337 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7338 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7339 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7340 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7341 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7342 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7343 7344 7345 static DEFINE_MUTEX(qla_fw_lock); 7346 7347 static struct fw_blob qla_fw_blobs[] = { 7348 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7349 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7350 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7351 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7352 { .name = FW_FILE_ISP24XX, }, 7353 { .name = FW_FILE_ISP25XX, }, 7354 { .name = FW_FILE_ISP81XX, }, 7355 { .name = FW_FILE_ISP82XX, }, 7356 { .name = FW_FILE_ISP2031, }, 7357 { .name = FW_FILE_ISP8031, }, 7358 { .name = FW_FILE_ISP27XX, }, 7359 { .name = FW_FILE_ISP28XX, }, 7360 { .name = NULL, }, 7361 }; 7362 7363 struct fw_blob * 7364 qla2x00_request_firmware(scsi_qla_host_t *vha) 7365 { 7366 struct qla_hw_data *ha = vha->hw; 7367 struct fw_blob *blob; 7368 7369 if (IS_QLA2100(ha)) { 7370 blob = &qla_fw_blobs[FW_ISP21XX]; 7371 } else if (IS_QLA2200(ha)) { 7372 blob = &qla_fw_blobs[FW_ISP22XX]; 7373 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7374 blob = &qla_fw_blobs[FW_ISP2300]; 7375 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7376 blob = &qla_fw_blobs[FW_ISP2322]; 7377 } else if (IS_QLA24XX_TYPE(ha)) { 7378 blob = &qla_fw_blobs[FW_ISP24XX]; 7379 } else if (IS_QLA25XX(ha)) { 7380 blob = &qla_fw_blobs[FW_ISP25XX]; 7381 } else if (IS_QLA81XX(ha)) { 7382 blob = &qla_fw_blobs[FW_ISP81XX]; 7383 } else if (IS_QLA82XX(ha)) { 7384 blob = &qla_fw_blobs[FW_ISP82XX]; 7385 } else if (IS_QLA2031(ha)) { 7386 blob = &qla_fw_blobs[FW_ISP2031]; 7387 } else if (IS_QLA8031(ha)) { 7388 blob = &qla_fw_blobs[FW_ISP8031]; 7389 } else if (IS_QLA27XX(ha)) { 7390 blob = &qla_fw_blobs[FW_ISP27XX]; 7391 } else if (IS_QLA28XX(ha)) { 7392 blob = &qla_fw_blobs[FW_ISP28XX]; 7393 } else { 7394 return NULL; 7395 } 7396 7397 if (!blob->name) 7398 return NULL; 7399 7400 mutex_lock(&qla_fw_lock); 7401 if (blob->fw) 7402 goto out; 7403 7404 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7405 ql_log(ql_log_warn, vha, 0x0063, 7406 "Failed to load firmware image (%s).\n", blob->name); 7407 blob->fw = NULL; 7408 blob = NULL; 7409 } 7410 7411 out: 7412 mutex_unlock(&qla_fw_lock); 7413 return blob; 7414 } 7415 7416 static void 7417 qla2x00_release_firmware(void) 7418 { 7419 struct fw_blob *blob; 7420 7421 mutex_lock(&qla_fw_lock); 7422 for (blob = qla_fw_blobs; blob->name; blob++) 7423 release_firmware(blob->fw); 7424 mutex_unlock(&qla_fw_lock); 7425 } 7426 7427 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7428 { 7429 struct qla_hw_data *ha = vha->hw; 7430 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7431 struct qla_qpair *qpair = NULL; 7432 struct scsi_qla_host *vp; 7433 fc_port_t *fcport; 7434 int i; 7435 unsigned long flags; 7436 7437 ha->chip_reset++; 7438 7439 ha->base_qpair->chip_reset = ha->chip_reset; 7440 for (i = 0; i < ha->max_qpairs; i++) { 7441 if (ha->queue_pair_map[i]) 7442 ha->queue_pair_map[i]->chip_reset = 7443 ha->base_qpair->chip_reset; 7444 } 7445 7446 /* purge MBox commands */ 7447 if (atomic_read(&ha->num_pend_mbx_stage3)) { 7448 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 7449 complete(&ha->mbx_intr_comp); 7450 } 7451 7452 i = 0; 7453 7454 while (atomic_read(&ha->num_pend_mbx_stage3) || 7455 atomic_read(&ha->num_pend_mbx_stage2) || 7456 atomic_read(&ha->num_pend_mbx_stage1)) { 7457 msleep(20); 7458 i++; 7459 if (i > 50) 7460 break; 7461 } 7462 7463 ha->flags.purge_mbox = 0; 7464 7465 mutex_lock(&ha->mq_lock); 7466 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7467 qpair->online = 0; 7468 mutex_unlock(&ha->mq_lock); 7469 7470 qla2x00_mark_all_devices_lost(vha); 7471 7472 spin_lock_irqsave(&ha->vport_slock, flags); 7473 list_for_each_entry(vp, &ha->vp_list, list) { 7474 atomic_inc(&vp->vref_count); 7475 spin_unlock_irqrestore(&ha->vport_slock, flags); 7476 qla2x00_mark_all_devices_lost(vp); 7477 spin_lock_irqsave(&ha->vport_slock, flags); 7478 atomic_dec(&vp->vref_count); 7479 } 7480 spin_unlock_irqrestore(&ha->vport_slock, flags); 7481 7482 /* Clear all async request states across all VPs. */ 7483 list_for_each_entry(fcport, &vha->vp_fcports, list) 7484 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7485 7486 spin_lock_irqsave(&ha->vport_slock, flags); 7487 list_for_each_entry(vp, &ha->vp_list, list) { 7488 atomic_inc(&vp->vref_count); 7489 spin_unlock_irqrestore(&ha->vport_slock, flags); 7490 list_for_each_entry(fcport, &vp->vp_fcports, list) 7491 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7492 spin_lock_irqsave(&ha->vport_slock, flags); 7493 atomic_dec(&vp->vref_count); 7494 } 7495 spin_unlock_irqrestore(&ha->vport_slock, flags); 7496 } 7497 7498 7499 static pci_ers_result_t 7500 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7501 { 7502 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7503 struct qla_hw_data *ha = vha->hw; 7504 7505 ql_dbg(ql_dbg_aer, vha, 0x9000, 7506 "PCI error detected, state %x.\n", state); 7507 7508 if (!atomic_read(&pdev->enable_cnt)) { 7509 ql_log(ql_log_info, vha, 0xffff, 7510 "PCI device is disabled,state %x\n", state); 7511 return PCI_ERS_RESULT_NEED_RESET; 7512 } 7513 7514 switch (state) { 7515 case pci_channel_io_normal: 7516 ha->flags.eeh_busy = 0; 7517 if (ql2xmqsupport || ql2xnvmeenable) { 7518 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7519 qla2xxx_wake_dpc(vha); 7520 } 7521 return PCI_ERS_RESULT_CAN_RECOVER; 7522 case pci_channel_io_frozen: 7523 ha->flags.eeh_busy = 1; 7524 qla_pci_error_cleanup(vha); 7525 return PCI_ERS_RESULT_NEED_RESET; 7526 case pci_channel_io_perm_failure: 7527 ha->flags.pci_channel_io_perm_failure = 1; 7528 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7529 if (ql2xmqsupport || ql2xnvmeenable) { 7530 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7531 qla2xxx_wake_dpc(vha); 7532 } 7533 return PCI_ERS_RESULT_DISCONNECT; 7534 } 7535 return PCI_ERS_RESULT_NEED_RESET; 7536 } 7537 7538 static pci_ers_result_t 7539 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7540 { 7541 int risc_paused = 0; 7542 uint32_t stat; 7543 unsigned long flags; 7544 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7545 struct qla_hw_data *ha = base_vha->hw; 7546 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7547 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7548 7549 if (IS_QLA82XX(ha)) 7550 return PCI_ERS_RESULT_RECOVERED; 7551 7552 spin_lock_irqsave(&ha->hardware_lock, flags); 7553 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7554 stat = RD_REG_DWORD(®->hccr); 7555 if (stat & HCCR_RISC_PAUSE) 7556 risc_paused = 1; 7557 } else if (IS_QLA23XX(ha)) { 7558 stat = RD_REG_DWORD(®->u.isp2300.host_status); 7559 if (stat & HSR_RISC_PAUSED) 7560 risc_paused = 1; 7561 } else if (IS_FWI2_CAPABLE(ha)) { 7562 stat = RD_REG_DWORD(®24->host_status); 7563 if (stat & HSRX_RISC_PAUSED) 7564 risc_paused = 1; 7565 } 7566 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7567 7568 if (risc_paused) { 7569 ql_log(ql_log_info, base_vha, 0x9003, 7570 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7571 ha->isp_ops->fw_dump(base_vha, 0); 7572 7573 return PCI_ERS_RESULT_NEED_RESET; 7574 } else 7575 return PCI_ERS_RESULT_RECOVERED; 7576 } 7577 7578 static pci_ers_result_t 7579 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7580 { 7581 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7582 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7583 struct qla_hw_data *ha = base_vha->hw; 7584 int rc; 7585 struct qla_qpair *qpair = NULL; 7586 7587 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 7588 "Slot Reset.\n"); 7589 7590 /* Workaround: qla2xxx driver which access hardware earlier 7591 * needs error state to be pci_channel_io_online. 7592 * Otherwise mailbox command timesout. 7593 */ 7594 pdev->error_state = pci_channel_io_normal; 7595 7596 pci_restore_state(pdev); 7597 7598 /* pci_restore_state() clears the saved_state flag of the device 7599 * save restored state which resets saved_state flag 7600 */ 7601 pci_save_state(pdev); 7602 7603 if (ha->mem_only) 7604 rc = pci_enable_device_mem(pdev); 7605 else 7606 rc = pci_enable_device(pdev); 7607 7608 if (rc) { 7609 ql_log(ql_log_warn, base_vha, 0x9005, 7610 "Can't re-enable PCI device after reset.\n"); 7611 goto exit_slot_reset; 7612 } 7613 7614 7615 if (ha->isp_ops->pci_config(base_vha)) 7616 goto exit_slot_reset; 7617 7618 mutex_lock(&ha->mq_lock); 7619 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7620 qpair->online = 1; 7621 mutex_unlock(&ha->mq_lock); 7622 7623 base_vha->flags.online = 1; 7624 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7625 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 7626 ret = PCI_ERS_RESULT_RECOVERED; 7627 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7628 7629 7630 exit_slot_reset: 7631 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7632 "slot_reset return %x.\n", ret); 7633 7634 return ret; 7635 } 7636 7637 static void 7638 qla2xxx_pci_resume(struct pci_dev *pdev) 7639 { 7640 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7641 struct qla_hw_data *ha = base_vha->hw; 7642 int ret; 7643 7644 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 7645 "pci_resume.\n"); 7646 7647 ha->flags.eeh_busy = 0; 7648 7649 ret = qla2x00_wait_for_hba_online(base_vha); 7650 if (ret != QLA_SUCCESS) { 7651 ql_log(ql_log_fatal, base_vha, 0x9002, 7652 "The device failed to resume I/O from slot/link_reset.\n"); 7653 } 7654 } 7655 7656 static void 7657 qla_pci_reset_prepare(struct pci_dev *pdev) 7658 { 7659 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7660 struct qla_hw_data *ha = base_vha->hw; 7661 struct qla_qpair *qpair; 7662 7663 ql_log(ql_log_warn, base_vha, 0xffff, 7664 "%s.\n", __func__); 7665 7666 /* 7667 * PCI FLR/function reset is about to reset the 7668 * slot. Stop the chip to stop all DMA access. 7669 * It is assumed that pci_reset_done will be called 7670 * after FLR to resume Chip operation. 7671 */ 7672 ha->flags.eeh_busy = 1; 7673 mutex_lock(&ha->mq_lock); 7674 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7675 qpair->online = 0; 7676 mutex_unlock(&ha->mq_lock); 7677 7678 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7679 qla2x00_abort_isp_cleanup(base_vha); 7680 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7681 } 7682 7683 static void 7684 qla_pci_reset_done(struct pci_dev *pdev) 7685 { 7686 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7687 struct qla_hw_data *ha = base_vha->hw; 7688 struct qla_qpair *qpair; 7689 7690 ql_log(ql_log_warn, base_vha, 0xffff, 7691 "%s.\n", __func__); 7692 7693 /* 7694 * FLR just completed by PCI layer. Resume adapter 7695 */ 7696 ha->flags.eeh_busy = 0; 7697 mutex_lock(&ha->mq_lock); 7698 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7699 qpair->online = 1; 7700 mutex_unlock(&ha->mq_lock); 7701 7702 base_vha->flags.online = 1; 7703 ha->isp_ops->abort_isp(base_vha); 7704 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7705 } 7706 7707 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7708 { 7709 int rc; 7710 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7711 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7712 7713 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7714 rc = blk_mq_map_queues(qmap); 7715 else 7716 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7717 return rc; 7718 } 7719 7720 struct scsi_host_template qla2xxx_driver_template = { 7721 .module = THIS_MODULE, 7722 .name = QLA2XXX_DRIVER_NAME, 7723 .queuecommand = qla2xxx_queuecommand, 7724 7725 .eh_timed_out = fc_eh_timed_out, 7726 .eh_abort_handler = qla2xxx_eh_abort, 7727 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7728 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7729 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7730 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7731 7732 .slave_configure = qla2xxx_slave_configure, 7733 7734 .slave_alloc = qla2xxx_slave_alloc, 7735 .slave_destroy = qla2xxx_slave_destroy, 7736 .scan_finished = qla2xxx_scan_finished, 7737 .scan_start = qla2xxx_scan_start, 7738 .change_queue_depth = scsi_change_queue_depth, 7739 .map_queues = qla2xxx_map_queues, 7740 .this_id = -1, 7741 .cmd_per_lun = 3, 7742 .sg_tablesize = SG_ALL, 7743 7744 .max_sectors = 0xFFFF, 7745 .shost_attrs = qla2x00_host_attrs, 7746 7747 .supported_mode = MODE_INITIATOR, 7748 .track_queue_depth = 1, 7749 .cmd_size = sizeof(srb_t), 7750 }; 7751 7752 static const struct pci_error_handlers qla2xxx_err_handler = { 7753 .error_detected = qla2xxx_pci_error_detected, 7754 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7755 .slot_reset = qla2xxx_pci_slot_reset, 7756 .resume = qla2xxx_pci_resume, 7757 .reset_prepare = qla_pci_reset_prepare, 7758 .reset_done = qla_pci_reset_done, 7759 }; 7760 7761 static struct pci_device_id qla2xxx_pci_tbl[] = { 7762 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7763 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7764 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7765 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7766 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7767 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7768 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7769 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7770 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7771 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7772 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7773 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7774 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7775 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7776 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7777 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7778 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7779 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7780 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7781 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7782 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7783 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7784 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 7785 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 7786 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 7787 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 7788 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 7789 { 0 }, 7790 }; 7791 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7792 7793 static struct pci_driver qla2xxx_pci_driver = { 7794 .name = QLA2XXX_DRIVER_NAME, 7795 .driver = { 7796 .owner = THIS_MODULE, 7797 }, 7798 .id_table = qla2xxx_pci_tbl, 7799 .probe = qla2x00_probe_one, 7800 .remove = qla2x00_remove_one, 7801 .shutdown = qla2x00_shutdown, 7802 .err_handler = &qla2xxx_err_handler, 7803 }; 7804 7805 static const struct file_operations apidev_fops = { 7806 .owner = THIS_MODULE, 7807 .llseek = noop_llseek, 7808 }; 7809 7810 /** 7811 * qla2x00_module_init - Module initialization. 7812 **/ 7813 static int __init 7814 qla2x00_module_init(void) 7815 { 7816 int ret = 0; 7817 7818 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 7819 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 7820 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 7821 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 7822 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 7823 BUILD_BUG_ON(sizeof(request_t) != 64); 7824 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 7825 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 7826 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 7827 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 7828 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 7829 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 7830 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 7831 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 7832 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 7833 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 7834 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 7835 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 7836 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 7837 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 7838 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 7839 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 7840 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 7841 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 7842 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 7843 7844 /* Allocate cache for SRBs. */ 7845 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 7846 SLAB_HWCACHE_ALIGN, NULL); 7847 if (srb_cachep == NULL) { 7848 ql_log(ql_log_fatal, NULL, 0x0001, 7849 "Unable to allocate SRB cache...Failing load!.\n"); 7850 return -ENOMEM; 7851 } 7852 7853 /* Initialize target kmem_cache and mem_pools */ 7854 ret = qlt_init(); 7855 if (ret < 0) { 7856 goto destroy_cache; 7857 } else if (ret > 0) { 7858 /* 7859 * If initiator mode is explictly disabled by qlt_init(), 7860 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 7861 * performing scsi_scan_target() during LOOP UP event. 7862 */ 7863 qla2xxx_transport_functions.disable_target_scan = 1; 7864 qla2xxx_transport_vport_functions.disable_target_scan = 1; 7865 } 7866 7867 /* Derive version string. */ 7868 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 7869 if (ql2xextended_error_logging) 7870 strcat(qla2x00_version_str, "-debug"); 7871 if (ql2xextended_error_logging == 1) 7872 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 7873 7874 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL) 7875 qla_insert_tgt_attrs(); 7876 7877 qla2xxx_transport_template = 7878 fc_attach_transport(&qla2xxx_transport_functions); 7879 if (!qla2xxx_transport_template) { 7880 ql_log(ql_log_fatal, NULL, 0x0002, 7881 "fc_attach_transport failed...Failing load!.\n"); 7882 ret = -ENODEV; 7883 goto qlt_exit; 7884 } 7885 7886 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 7887 if (apidev_major < 0) { 7888 ql_log(ql_log_fatal, NULL, 0x0003, 7889 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 7890 } 7891 7892 qla2xxx_transport_vport_template = 7893 fc_attach_transport(&qla2xxx_transport_vport_functions); 7894 if (!qla2xxx_transport_vport_template) { 7895 ql_log(ql_log_fatal, NULL, 0x0004, 7896 "fc_attach_transport vport failed...Failing load!.\n"); 7897 ret = -ENODEV; 7898 goto unreg_chrdev; 7899 } 7900 ql_log(ql_log_info, NULL, 0x0005, 7901 "QLogic Fibre Channel HBA Driver: %s.\n", 7902 qla2x00_version_str); 7903 ret = pci_register_driver(&qla2xxx_pci_driver); 7904 if (ret) { 7905 ql_log(ql_log_fatal, NULL, 0x0006, 7906 "pci_register_driver failed...ret=%d Failing load!.\n", 7907 ret); 7908 goto release_vport_transport; 7909 } 7910 return ret; 7911 7912 release_vport_transport: 7913 fc_release_transport(qla2xxx_transport_vport_template); 7914 7915 unreg_chrdev: 7916 if (apidev_major >= 0) 7917 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7918 fc_release_transport(qla2xxx_transport_template); 7919 7920 qlt_exit: 7921 qlt_exit(); 7922 7923 destroy_cache: 7924 kmem_cache_destroy(srb_cachep); 7925 return ret; 7926 } 7927 7928 /** 7929 * qla2x00_module_exit - Module cleanup. 7930 **/ 7931 static void __exit 7932 qla2x00_module_exit(void) 7933 { 7934 pci_unregister_driver(&qla2xxx_pci_driver); 7935 qla2x00_release_firmware(); 7936 kmem_cache_destroy(ctx_cachep); 7937 fc_release_transport(qla2xxx_transport_vport_template); 7938 if (apidev_major >= 0) 7939 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7940 fc_release_transport(qla2xxx_transport_template); 7941 qlt_exit(); 7942 kmem_cache_destroy(srb_cachep); 7943 } 7944 7945 module_init(qla2x00_module_init); 7946 module_exit(qla2x00_module_exit); 7947 7948 MODULE_AUTHOR("QLogic Corporation"); 7949 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 7950 MODULE_LICENSE("GPL"); 7951 MODULE_VERSION(QLA2XXX_VERSION); 7952 MODULE_FIRMWARE(FW_FILE_ISP21XX); 7953 MODULE_FIRMWARE(FW_FILE_ISP22XX); 7954 MODULE_FIRMWARE(FW_FILE_ISP2300); 7955 MODULE_FIRMWARE(FW_FILE_ISP2322); 7956 MODULE_FIRMWARE(FW_FILE_ISP24XX); 7957 MODULE_FIRMWARE(FW_FILE_ISP25XX); 7958