1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #include "qla_def.h" 8 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/blk-mq-pci.h> 17 #include <linux/refcount.h> 18 19 #include <scsi/scsi_tcq.h> 20 #include <scsi/scsicam.h> 21 #include <scsi/scsi_transport.h> 22 #include <scsi/scsi_transport_fc.h> 23 24 #include "qla_target.h" 25 26 /* 27 * Driver version 28 */ 29 char qla2x00_version_str[40]; 30 31 static int apidev_major; 32 33 /* 34 * SRB allocation cache 35 */ 36 struct kmem_cache *srb_cachep; 37 38 /* 39 * CT6 CTX allocation cache 40 */ 41 static struct kmem_cache *ctx_cachep; 42 /* 43 * error level for logging 44 */ 45 uint ql_errlev = 0x8001; 46 47 static int ql2xenableclass2; 48 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 49 MODULE_PARM_DESC(ql2xenableclass2, 50 "Specify if Class 2 operations are supported from the very " 51 "beginning. Default is 0 - class 2 not supported."); 52 53 54 int ql2xlogintimeout = 20; 55 module_param(ql2xlogintimeout, int, S_IRUGO); 56 MODULE_PARM_DESC(ql2xlogintimeout, 57 "Login timeout value in seconds."); 58 59 int qlport_down_retry; 60 module_param(qlport_down_retry, int, S_IRUGO); 61 MODULE_PARM_DESC(qlport_down_retry, 62 "Maximum number of command retries to a port that returns " 63 "a PORT-DOWN status."); 64 65 int ql2xplogiabsentdevice; 66 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 67 MODULE_PARM_DESC(ql2xplogiabsentdevice, 68 "Option to enable PLOGI to devices that are not present after " 69 "a Fabric scan. This is needed for several broken switches. " 70 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 71 72 int ql2xloginretrycount = 0; 73 module_param(ql2xloginretrycount, int, S_IRUGO); 74 MODULE_PARM_DESC(ql2xloginretrycount, 75 "Specify an alternate value for the NVRAM login retry count."); 76 77 int ql2xallocfwdump = 1; 78 module_param(ql2xallocfwdump, int, S_IRUGO); 79 MODULE_PARM_DESC(ql2xallocfwdump, 80 "Option to enable allocation of memory for a firmware dump " 81 "during HBA initialization. Memory allocation requirements " 82 "vary by ISP type. Default is 1 - allocate memory."); 83 84 int ql2xextended_error_logging; 85 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 86 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 87 MODULE_PARM_DESC(ql2xextended_error_logging, 88 "Option to enable extended error logging,\n" 89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 100 "\t\t0x1e400000 - Preferred value for capturing essential " 101 "debug information (equivalent to old " 102 "ql2xextended_error_logging=1).\n" 103 "\t\tDo LOGICAL OR of the value to enable more than one level"); 104 105 int ql2xshiftctondsd = 6; 106 module_param(ql2xshiftctondsd, int, S_IRUGO); 107 MODULE_PARM_DESC(ql2xshiftctondsd, 108 "Set to control shifting of command type processing " 109 "based on total number of SG elements."); 110 111 int ql2xfdmienable = 1; 112 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 113 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 114 MODULE_PARM_DESC(ql2xfdmienable, 115 "Enables FDMI registrations. " 116 "0 - no FDMI. Default is 1 - perform FDMI."); 117 118 #define MAX_Q_DEPTH 64 119 static int ql2xmaxqdepth = MAX_Q_DEPTH; 120 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 121 MODULE_PARM_DESC(ql2xmaxqdepth, 122 "Maximum queue depth to set for each LUN. " 123 "Default is 64."); 124 125 #if (IS_ENABLED(CONFIG_NVME_FC)) 126 int ql2xenabledif; 127 #else 128 int ql2xenabledif = 2; 129 #endif 130 module_param(ql2xenabledif, int, S_IRUGO); 131 MODULE_PARM_DESC(ql2xenabledif, 132 " Enable T10-CRC-DIF:\n" 133 " Default is 2.\n" 134 " 0 -- No DIF Support\n" 135 " 1 -- Enable DIF for all types\n" 136 " 2 -- Enable DIF for all types, except Type 0.\n"); 137 138 #if (IS_ENABLED(CONFIG_NVME_FC)) 139 int ql2xnvmeenable = 1; 140 #else 141 int ql2xnvmeenable; 142 #endif 143 module_param(ql2xnvmeenable, int, 0644); 144 MODULE_PARM_DESC(ql2xnvmeenable, 145 "Enables NVME support. " 146 "0 - no NVMe. Default is Y"); 147 148 int ql2xenablehba_err_chk = 2; 149 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 150 MODULE_PARM_DESC(ql2xenablehba_err_chk, 151 " Enable T10-CRC-DIF Error isolation by HBA:\n" 152 " Default is 2.\n" 153 " 0 -- Error isolation disabled\n" 154 " 1 -- Error isolation enabled only for DIX Type 0\n" 155 " 2 -- Error isolation enabled for all Types\n"); 156 157 int ql2xiidmaenable = 1; 158 module_param(ql2xiidmaenable, int, S_IRUGO); 159 MODULE_PARM_DESC(ql2xiidmaenable, 160 "Enables iIDMA settings " 161 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 162 163 int ql2xmqsupport = 1; 164 module_param(ql2xmqsupport, int, S_IRUGO); 165 MODULE_PARM_DESC(ql2xmqsupport, 166 "Enable on demand multiple queue pairs support " 167 "Default is 1 for supported. " 168 "Set it to 0 to turn off mq qpair support."); 169 170 int ql2xfwloadbin; 171 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 172 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 173 MODULE_PARM_DESC(ql2xfwloadbin, 174 "Option to specify location from which to load ISP firmware:.\n" 175 " 2 -- load firmware via the request_firmware() (hotplug).\n" 176 " interface.\n" 177 " 1 -- load firmware from flash.\n" 178 " 0 -- use default semantics.\n"); 179 180 int ql2xetsenable; 181 module_param(ql2xetsenable, int, S_IRUGO); 182 MODULE_PARM_DESC(ql2xetsenable, 183 "Enables firmware ETS burst." 184 "Default is 0 - skip ETS enablement."); 185 186 int ql2xdbwr = 1; 187 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 188 MODULE_PARM_DESC(ql2xdbwr, 189 "Option to specify scheme for request queue posting.\n" 190 " 0 -- Regular doorbell.\n" 191 " 1 -- CAMRAM doorbell (faster).\n"); 192 193 int ql2xtargetreset = 1; 194 module_param(ql2xtargetreset, int, S_IRUGO); 195 MODULE_PARM_DESC(ql2xtargetreset, 196 "Enable target reset." 197 "Default is 1 - use hw defaults."); 198 199 int ql2xgffidenable; 200 module_param(ql2xgffidenable, int, S_IRUGO); 201 MODULE_PARM_DESC(ql2xgffidenable, 202 "Enables GFF_ID checks of port type. " 203 "Default is 0 - Do not use GFF_ID information."); 204 205 int ql2xasynctmfenable = 1; 206 module_param(ql2xasynctmfenable, int, S_IRUGO); 207 MODULE_PARM_DESC(ql2xasynctmfenable, 208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 210 211 int ql2xdontresethba; 212 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 213 MODULE_PARM_DESC(ql2xdontresethba, 214 "Option to specify reset behaviour.\n" 215 " 0 (Default) -- Reset on failure.\n" 216 " 1 -- Do not reset on failure.\n"); 217 218 uint64_t ql2xmaxlun = MAX_LUNS; 219 module_param(ql2xmaxlun, ullong, S_IRUGO); 220 MODULE_PARM_DESC(ql2xmaxlun, 221 "Defines the maximum LU number to register with the SCSI " 222 "midlayer. Default is 65535."); 223 224 int ql2xmdcapmask = 0x1F; 225 module_param(ql2xmdcapmask, int, S_IRUGO); 226 MODULE_PARM_DESC(ql2xmdcapmask, 227 "Set the Minidump driver capture mask level. " 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 229 230 int ql2xmdenable = 1; 231 module_param(ql2xmdenable, int, S_IRUGO); 232 MODULE_PARM_DESC(ql2xmdenable, 233 "Enable/disable MiniDump. " 234 "0 - MiniDump disabled. " 235 "1 (Default) - MiniDump enabled."); 236 237 int ql2xexlogins = 0; 238 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 239 MODULE_PARM_DESC(ql2xexlogins, 240 "Number of extended Logins. " 241 "0 (Default)- Disabled."); 242 243 int ql2xexchoffld = 1024; 244 module_param(ql2xexchoffld, uint, 0644); 245 MODULE_PARM_DESC(ql2xexchoffld, 246 "Number of target exchanges."); 247 248 int ql2xiniexchg = 1024; 249 module_param(ql2xiniexchg, uint, 0644); 250 MODULE_PARM_DESC(ql2xiniexchg, 251 "Number of initiator exchanges."); 252 253 int ql2xfwholdabts = 0; 254 module_param(ql2xfwholdabts, int, S_IRUGO); 255 MODULE_PARM_DESC(ql2xfwholdabts, 256 "Allow FW to hold status IOCB until ABTS rsp received. " 257 "0 (Default) Do not set fw option. " 258 "1 - Set fw option to hold ABTS."); 259 260 int ql2xmvasynctoatio = 1; 261 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 262 MODULE_PARM_DESC(ql2xmvasynctoatio, 263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 264 "0 (Default). Do not move IOCBs" 265 "1 - Move IOCBs."); 266 267 int ql2xautodetectsfp = 1; 268 module_param(ql2xautodetectsfp, int, 0444); 269 MODULE_PARM_DESC(ql2xautodetectsfp, 270 "Detect SFP range and set appropriate distance.\n" 271 "1 (Default): Enable\n"); 272 273 int ql2xenablemsix = 1; 274 module_param(ql2xenablemsix, int, 0444); 275 MODULE_PARM_DESC(ql2xenablemsix, 276 "Set to enable MSI or MSI-X interrupt mechanism.\n" 277 " Default is 1, enable MSI-X interrupt mechanism.\n" 278 " 0 -- enable traditional pin-based mechanism.\n" 279 " 1 -- enable MSI-X interrupt mechanism.\n" 280 " 2 -- enable MSI interrupt mechanism.\n"); 281 282 int qla2xuseresexchforels; 283 module_param(qla2xuseresexchforels, int, 0444); 284 MODULE_PARM_DESC(qla2xuseresexchforels, 285 "Reserve 1/2 of emergency exchanges for ELS.\n" 286 " 0 (default): disabled"); 287 288 static int ql2xprotmask; 289 module_param(ql2xprotmask, int, 0644); 290 MODULE_PARM_DESC(ql2xprotmask, 291 "Override DIF/DIX protection capabilities mask\n" 292 "Default is 0 which sets protection mask based on " 293 "capabilities reported by HBA firmware.\n"); 294 295 static int ql2xprotguard; 296 module_param(ql2xprotguard, int, 0644); 297 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 298 " 0 -- Let HBA firmware decide\n" 299 " 1 -- Force T10 CRC\n" 300 " 2 -- Force IP checksum\n"); 301 302 int ql2xdifbundlinginternalbuffers; 303 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 304 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 305 "Force using internal buffers for DIF information\n" 306 "0 (Default). Based on check.\n" 307 "1 Force using internal buffers\n"); 308 309 static void qla2x00_clear_drv_active(struct qla_hw_data *); 310 static void qla2x00_free_device(scsi_qla_host_t *); 311 static int qla2xxx_map_queues(struct Scsi_Host *shost); 312 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 313 314 315 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 316 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 317 318 /* TODO Convert to inlines 319 * 320 * Timer routines 321 */ 322 323 __inline__ void 324 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 325 { 326 timer_setup(&vha->timer, qla2x00_timer, 0); 327 vha->timer.expires = jiffies + interval * HZ; 328 add_timer(&vha->timer); 329 vha->timer_active = 1; 330 } 331 332 static inline void 333 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 334 { 335 /* Currently used for 82XX only. */ 336 if (vha->device_flags & DFLG_DEV_FAILED) { 337 ql_dbg(ql_dbg_timer, vha, 0x600d, 338 "Device in a failed state, returning.\n"); 339 return; 340 } 341 342 mod_timer(&vha->timer, jiffies + interval * HZ); 343 } 344 345 static __inline__ void 346 qla2x00_stop_timer(scsi_qla_host_t *vha) 347 { 348 del_timer_sync(&vha->timer); 349 vha->timer_active = 0; 350 } 351 352 static int qla2x00_do_dpc(void *data); 353 354 static void qla2x00_rst_aen(scsi_qla_host_t *); 355 356 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 357 struct req_que **, struct rsp_que **); 358 static void qla2x00_free_fw_dump(struct qla_hw_data *); 359 static void qla2x00_mem_free(struct qla_hw_data *); 360 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 361 struct qla_qpair *qpair); 362 363 /* -------------------------------------------------------------------------- */ 364 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 365 struct rsp_que *rsp) 366 { 367 struct qla_hw_data *ha = vha->hw; 368 369 rsp->qpair = ha->base_qpair; 370 rsp->req = req; 371 ha->base_qpair->hw = ha; 372 ha->base_qpair->req = req; 373 ha->base_qpair->rsp = rsp; 374 ha->base_qpair->vha = vha; 375 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 376 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 377 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 378 ha->base_qpair->srb_mempool = ha->srb_mempool; 379 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 380 ha->base_qpair->enable_class_2 = ql2xenableclass2; 381 /* init qpair to this cpu. Will adjust at run time. */ 382 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 383 ha->base_qpair->pdev = ha->pdev; 384 385 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 386 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 387 } 388 389 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 390 struct rsp_que *rsp) 391 { 392 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 393 394 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 395 GFP_KERNEL); 396 if (!ha->req_q_map) { 397 ql_log(ql_log_fatal, vha, 0x003b, 398 "Unable to allocate memory for request queue ptrs.\n"); 399 goto fail_req_map; 400 } 401 402 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 403 GFP_KERNEL); 404 if (!ha->rsp_q_map) { 405 ql_log(ql_log_fatal, vha, 0x003c, 406 "Unable to allocate memory for response queue ptrs.\n"); 407 goto fail_rsp_map; 408 } 409 410 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 411 if (ha->base_qpair == NULL) { 412 ql_log(ql_log_warn, vha, 0x00e0, 413 "Failed to allocate base queue pair memory.\n"); 414 goto fail_base_qpair; 415 } 416 417 qla_init_base_qpair(vha, req, rsp); 418 419 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 420 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 421 GFP_KERNEL); 422 if (!ha->queue_pair_map) { 423 ql_log(ql_log_fatal, vha, 0x0180, 424 "Unable to allocate memory for queue pair ptrs.\n"); 425 goto fail_qpair_map; 426 } 427 } 428 429 /* 430 * Make sure we record at least the request and response queue zero in 431 * case we need to free them if part of the probe fails. 432 */ 433 ha->rsp_q_map[0] = rsp; 434 ha->req_q_map[0] = req; 435 set_bit(0, ha->rsp_qid_map); 436 set_bit(0, ha->req_qid_map); 437 return 0; 438 439 fail_qpair_map: 440 kfree(ha->base_qpair); 441 ha->base_qpair = NULL; 442 fail_base_qpair: 443 kfree(ha->rsp_q_map); 444 ha->rsp_q_map = NULL; 445 fail_rsp_map: 446 kfree(ha->req_q_map); 447 ha->req_q_map = NULL; 448 fail_req_map: 449 return -ENOMEM; 450 } 451 452 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 453 { 454 if (IS_QLAFX00(ha)) { 455 if (req && req->ring_fx00) 456 dma_free_coherent(&ha->pdev->dev, 457 (req->length_fx00 + 1) * sizeof(request_t), 458 req->ring_fx00, req->dma_fx00); 459 } else if (req && req->ring) 460 dma_free_coherent(&ha->pdev->dev, 461 (req->length + 1) * sizeof(request_t), 462 req->ring, req->dma); 463 464 if (req) 465 kfree(req->outstanding_cmds); 466 467 kfree(req); 468 } 469 470 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 471 { 472 if (IS_QLAFX00(ha)) { 473 if (rsp && rsp->ring_fx00) 474 dma_free_coherent(&ha->pdev->dev, 475 (rsp->length_fx00 + 1) * sizeof(request_t), 476 rsp->ring_fx00, rsp->dma_fx00); 477 } else if (rsp && rsp->ring) { 478 dma_free_coherent(&ha->pdev->dev, 479 (rsp->length + 1) * sizeof(response_t), 480 rsp->ring, rsp->dma); 481 } 482 kfree(rsp); 483 } 484 485 static void qla2x00_free_queues(struct qla_hw_data *ha) 486 { 487 struct req_que *req; 488 struct rsp_que *rsp; 489 int cnt; 490 unsigned long flags; 491 492 if (ha->queue_pair_map) { 493 kfree(ha->queue_pair_map); 494 ha->queue_pair_map = NULL; 495 } 496 if (ha->base_qpair) { 497 kfree(ha->base_qpair); 498 ha->base_qpair = NULL; 499 } 500 501 spin_lock_irqsave(&ha->hardware_lock, flags); 502 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 503 if (!test_bit(cnt, ha->req_qid_map)) 504 continue; 505 506 req = ha->req_q_map[cnt]; 507 clear_bit(cnt, ha->req_qid_map); 508 ha->req_q_map[cnt] = NULL; 509 510 spin_unlock_irqrestore(&ha->hardware_lock, flags); 511 qla2x00_free_req_que(ha, req); 512 spin_lock_irqsave(&ha->hardware_lock, flags); 513 } 514 spin_unlock_irqrestore(&ha->hardware_lock, flags); 515 516 kfree(ha->req_q_map); 517 ha->req_q_map = NULL; 518 519 520 spin_lock_irqsave(&ha->hardware_lock, flags); 521 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 522 if (!test_bit(cnt, ha->rsp_qid_map)) 523 continue; 524 525 rsp = ha->rsp_q_map[cnt]; 526 clear_bit(cnt, ha->rsp_qid_map); 527 ha->rsp_q_map[cnt] = NULL; 528 spin_unlock_irqrestore(&ha->hardware_lock, flags); 529 qla2x00_free_rsp_que(ha, rsp); 530 spin_lock_irqsave(&ha->hardware_lock, flags); 531 } 532 spin_unlock_irqrestore(&ha->hardware_lock, flags); 533 534 kfree(ha->rsp_q_map); 535 ha->rsp_q_map = NULL; 536 } 537 538 static char * 539 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) 540 { 541 struct qla_hw_data *ha = vha->hw; 542 static char *pci_bus_modes[] = { 543 "33", "66", "100", "133", 544 }; 545 uint16_t pci_bus; 546 547 strcpy(str, "PCI"); 548 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 549 if (pci_bus) { 550 strcat(str, "-X ("); 551 strcat(str, pci_bus_modes[pci_bus]); 552 } else { 553 pci_bus = (ha->pci_attr & BIT_8) >> 8; 554 strcat(str, " ("); 555 strcat(str, pci_bus_modes[pci_bus]); 556 } 557 strcat(str, " MHz)"); 558 559 return (str); 560 } 561 562 static char * 563 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) 564 { 565 static char *pci_bus_modes[] = { "33", "66", "100", "133", }; 566 struct qla_hw_data *ha = vha->hw; 567 uint32_t pci_bus; 568 569 if (pci_is_pcie(ha->pdev)) { 570 char lwstr[6]; 571 uint32_t lstat, lspeed, lwidth; 572 573 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 574 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 575 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 576 577 strcpy(str, "PCIe ("); 578 switch (lspeed) { 579 case 1: 580 strcat(str, "2.5GT/s "); 581 break; 582 case 2: 583 strcat(str, "5.0GT/s "); 584 break; 585 case 3: 586 strcat(str, "8.0GT/s "); 587 break; 588 default: 589 strcat(str, "<unknown> "); 590 break; 591 } 592 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); 593 strcat(str, lwstr); 594 595 return str; 596 } 597 598 strcpy(str, "PCI"); 599 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 600 if (pci_bus == 0 || pci_bus == 8) { 601 strcat(str, " ("); 602 strcat(str, pci_bus_modes[pci_bus >> 3]); 603 } else { 604 strcat(str, "-X "); 605 if (pci_bus & BIT_2) 606 strcat(str, "Mode 2"); 607 else 608 strcat(str, "Mode 1"); 609 strcat(str, " ("); 610 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); 611 } 612 strcat(str, " MHz)"); 613 614 return str; 615 } 616 617 static char * 618 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 619 { 620 char un_str[10]; 621 struct qla_hw_data *ha = vha->hw; 622 623 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 624 ha->fw_minor_version, ha->fw_subminor_version); 625 626 if (ha->fw_attributes & BIT_9) { 627 strcat(str, "FLX"); 628 return (str); 629 } 630 631 switch (ha->fw_attributes & 0xFF) { 632 case 0x7: 633 strcat(str, "EF"); 634 break; 635 case 0x17: 636 strcat(str, "TP"); 637 break; 638 case 0x37: 639 strcat(str, "IP"); 640 break; 641 case 0x77: 642 strcat(str, "VI"); 643 break; 644 default: 645 sprintf(un_str, "(%x)", ha->fw_attributes); 646 strcat(str, un_str); 647 break; 648 } 649 if (ha->fw_attributes & 0x100) 650 strcat(str, "X"); 651 652 return (str); 653 } 654 655 static char * 656 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 657 { 658 struct qla_hw_data *ha = vha->hw; 659 660 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 661 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 662 return str; 663 } 664 665 void 666 qla2x00_sp_free_dma(void *ptr) 667 { 668 srb_t *sp = ptr; 669 struct qla_hw_data *ha = sp->vha->hw; 670 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 671 void *ctx = GET_CMD_CTX_SP(sp); 672 673 if (sp->flags & SRB_DMA_VALID) { 674 scsi_dma_unmap(cmd); 675 sp->flags &= ~SRB_DMA_VALID; 676 } 677 678 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 679 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 680 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 681 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 682 } 683 684 if (!ctx) 685 return; 686 687 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 688 /* List assured to be having elements */ 689 qla2x00_clean_dsd_pool(ha, ctx); 690 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 691 } 692 693 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 694 struct crc_context *ctx0 = ctx; 695 696 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 697 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 698 } 699 700 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 701 struct ct6_dsd *ctx1 = ctx; 702 703 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 704 ctx1->fcp_cmnd_dma); 705 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 706 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 707 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 708 mempool_free(ctx1, ha->ctx_mempool); 709 } 710 } 711 712 void 713 qla2x00_sp_compl(void *ptr, int res) 714 { 715 srb_t *sp = ptr; 716 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 717 struct completion *comp = sp->comp; 718 719 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0)) 720 return; 721 722 atomic_dec(&sp->ref_count); 723 724 sp->free(sp); 725 cmd->result = res; 726 CMD_SP(cmd) = NULL; 727 cmd->scsi_done(cmd); 728 if (comp) 729 complete(comp); 730 qla2x00_rel_sp(sp); 731 } 732 733 void 734 qla2xxx_qpair_sp_free_dma(void *ptr) 735 { 736 srb_t *sp = (srb_t *)ptr; 737 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 738 struct qla_hw_data *ha = sp->fcport->vha->hw; 739 void *ctx = GET_CMD_CTX_SP(sp); 740 741 if (sp->flags & SRB_DMA_VALID) { 742 scsi_dma_unmap(cmd); 743 sp->flags &= ~SRB_DMA_VALID; 744 } 745 746 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 747 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 748 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 749 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 750 } 751 752 if (!ctx) 753 return; 754 755 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 756 /* List assured to be having elements */ 757 qla2x00_clean_dsd_pool(ha, ctx); 758 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 759 } 760 761 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 762 struct crc_context *difctx = ctx; 763 struct dsd_dma *dif_dsd, *nxt_dsd; 764 765 list_for_each_entry_safe(dif_dsd, nxt_dsd, 766 &difctx->ldif_dma_hndl_list, list) { 767 list_del(&dif_dsd->list); 768 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 769 dif_dsd->dsd_list_dma); 770 kfree(dif_dsd); 771 difctx->no_dif_bundl--; 772 } 773 774 list_for_each_entry_safe(dif_dsd, nxt_dsd, 775 &difctx->ldif_dsd_list, list) { 776 list_del(&dif_dsd->list); 777 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 778 dif_dsd->dsd_list_dma); 779 kfree(dif_dsd); 780 difctx->no_ldif_dsd--; 781 } 782 783 if (difctx->no_ldif_dsd) { 784 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 785 "%s: difctx->no_ldif_dsd=%x\n", 786 __func__, difctx->no_ldif_dsd); 787 } 788 789 if (difctx->no_dif_bundl) { 790 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 791 "%s: difctx->no_dif_bundl=%x\n", 792 __func__, difctx->no_dif_bundl); 793 } 794 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 795 } 796 797 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 798 struct ct6_dsd *ctx1 = ctx; 799 800 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 801 ctx1->fcp_cmnd_dma); 802 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 803 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 804 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 805 mempool_free(ctx1, ha->ctx_mempool); 806 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 807 } 808 809 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 810 struct crc_context *ctx0 = ctx; 811 812 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma); 813 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 814 } 815 } 816 817 void 818 qla2xxx_qpair_sp_compl(void *ptr, int res) 819 { 820 srb_t *sp = ptr; 821 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 822 struct completion *comp = sp->comp; 823 824 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0)) 825 return; 826 827 atomic_dec(&sp->ref_count); 828 829 sp->free(sp); 830 cmd->result = res; 831 CMD_SP(cmd) = NULL; 832 cmd->scsi_done(cmd); 833 if (comp) 834 complete(comp); 835 qla2xxx_rel_qpair_sp(sp->qpair, sp); 836 } 837 838 static int 839 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 840 { 841 scsi_qla_host_t *vha = shost_priv(host); 842 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 843 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 844 struct qla_hw_data *ha = vha->hw; 845 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 846 srb_t *sp; 847 int rval; 848 struct qla_qpair *qpair = NULL; 849 uint32_t tag; 850 uint16_t hwq; 851 852 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 853 WARN_ON_ONCE(!rport)) { 854 cmd->result = DID_NO_CONNECT << 16; 855 goto qc24_fail_command; 856 } 857 858 if (ha->mqenable) { 859 tag = blk_mq_unique_tag(cmd->request); 860 hwq = blk_mq_unique_tag_to_hwq(tag); 861 qpair = ha->queue_pair_map[hwq]; 862 863 if (qpair) 864 return qla2xxx_mqueuecommand(host, cmd, qpair); 865 } 866 867 if (ha->flags.eeh_busy) { 868 if (ha->flags.pci_channel_io_perm_failure) { 869 ql_dbg(ql_dbg_aer, vha, 0x9010, 870 "PCI Channel IO permanent failure, exiting " 871 "cmd=%p.\n", cmd); 872 cmd->result = DID_NO_CONNECT << 16; 873 } else { 874 ql_dbg(ql_dbg_aer, vha, 0x9011, 875 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 876 cmd->result = DID_REQUEUE << 16; 877 } 878 goto qc24_fail_command; 879 } 880 881 rval = fc_remote_port_chkready(rport); 882 if (rval) { 883 cmd->result = rval; 884 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 885 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 886 cmd, rval); 887 goto qc24_fail_command; 888 } 889 890 if (!vha->flags.difdix_supported && 891 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 892 ql_dbg(ql_dbg_io, vha, 0x3004, 893 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 894 cmd); 895 cmd->result = DID_NO_CONNECT << 16; 896 goto qc24_fail_command; 897 } 898 899 if (!fcport) { 900 cmd->result = DID_NO_CONNECT << 16; 901 goto qc24_fail_command; 902 } 903 904 if (atomic_read(&fcport->state) != FCS_ONLINE) { 905 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 906 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 907 ql_dbg(ql_dbg_io, vha, 0x3005, 908 "Returning DNC, fcport_state=%d loop_state=%d.\n", 909 atomic_read(&fcport->state), 910 atomic_read(&base_vha->loop_state)); 911 cmd->result = DID_NO_CONNECT << 16; 912 goto qc24_fail_command; 913 } 914 goto qc24_target_busy; 915 } 916 917 /* 918 * Return target busy if we've received a non-zero retry_delay_timer 919 * in a FCP_RSP. 920 */ 921 if (fcport->retry_delay_timestamp == 0) { 922 /* retry delay not set */ 923 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 924 fcport->retry_delay_timestamp = 0; 925 else 926 goto qc24_target_busy; 927 928 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); 929 if (!sp) 930 goto qc24_host_busy; 931 932 sp->u.scmd.cmd = cmd; 933 sp->type = SRB_SCSI_CMD; 934 atomic_set(&sp->ref_count, 1); 935 CMD_SP(cmd) = (void *)sp; 936 sp->free = qla2x00_sp_free_dma; 937 sp->done = qla2x00_sp_compl; 938 939 rval = ha->isp_ops->start_scsi(sp); 940 if (rval != QLA_SUCCESS) { 941 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 942 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 943 goto qc24_host_busy_free_sp; 944 } 945 946 return 0; 947 948 qc24_host_busy_free_sp: 949 sp->free(sp); 950 951 qc24_host_busy: 952 return SCSI_MLQUEUE_HOST_BUSY; 953 954 qc24_target_busy: 955 return SCSI_MLQUEUE_TARGET_BUSY; 956 957 qc24_fail_command: 958 cmd->scsi_done(cmd); 959 960 return 0; 961 } 962 963 /* For MQ supported I/O */ 964 int 965 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 966 struct qla_qpair *qpair) 967 { 968 scsi_qla_host_t *vha = shost_priv(host); 969 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 970 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 971 struct qla_hw_data *ha = vha->hw; 972 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 973 srb_t *sp; 974 int rval; 975 976 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE; 977 if (rval) { 978 cmd->result = rval; 979 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 980 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 981 cmd, rval); 982 goto qc24_fail_command; 983 } 984 985 if (!fcport) { 986 cmd->result = DID_NO_CONNECT << 16; 987 goto qc24_fail_command; 988 } 989 990 if (atomic_read(&fcport->state) != FCS_ONLINE) { 991 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 992 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 993 ql_dbg(ql_dbg_io, vha, 0x3077, 994 "Returning DNC, fcport_state=%d loop_state=%d.\n", 995 atomic_read(&fcport->state), 996 atomic_read(&base_vha->loop_state)); 997 cmd->result = DID_NO_CONNECT << 16; 998 goto qc24_fail_command; 999 } 1000 goto qc24_target_busy; 1001 } 1002 1003 /* 1004 * Return target busy if we've received a non-zero retry_delay_timer 1005 * in a FCP_RSP. 1006 */ 1007 if (fcport->retry_delay_timestamp == 0) { 1008 /* retry delay not set */ 1009 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1010 fcport->retry_delay_timestamp = 0; 1011 else 1012 goto qc24_target_busy; 1013 1014 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC); 1015 if (!sp) 1016 goto qc24_host_busy; 1017 1018 sp->u.scmd.cmd = cmd; 1019 sp->type = SRB_SCSI_CMD; 1020 atomic_set(&sp->ref_count, 1); 1021 CMD_SP(cmd) = (void *)sp; 1022 sp->free = qla2xxx_qpair_sp_free_dma; 1023 sp->done = qla2xxx_qpair_sp_compl; 1024 sp->qpair = qpair; 1025 1026 rval = ha->isp_ops->start_scsi_mq(sp); 1027 if (rval != QLA_SUCCESS) { 1028 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1029 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1030 if (rval == QLA_INTERFACE_ERROR) 1031 goto qc24_fail_command; 1032 goto qc24_host_busy_free_sp; 1033 } 1034 1035 return 0; 1036 1037 qc24_host_busy_free_sp: 1038 sp->free(sp); 1039 1040 qc24_host_busy: 1041 return SCSI_MLQUEUE_HOST_BUSY; 1042 1043 qc24_target_busy: 1044 return SCSI_MLQUEUE_TARGET_BUSY; 1045 1046 qc24_fail_command: 1047 cmd->scsi_done(cmd); 1048 1049 return 0; 1050 } 1051 1052 /* 1053 * qla2x00_eh_wait_on_command 1054 * Waits for the command to be returned by the Firmware for some 1055 * max time. 1056 * 1057 * Input: 1058 * cmd = Scsi Command to wait on. 1059 * 1060 * Return: 1061 * Not Found : 0 1062 * Found : 1 1063 */ 1064 static int 1065 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1066 { 1067 #define ABORT_POLLING_PERIOD 1000 1068 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1069 unsigned long wait_iter = ABORT_WAIT_ITER; 1070 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1071 struct qla_hw_data *ha = vha->hw; 1072 int ret = QLA_SUCCESS; 1073 1074 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1075 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1076 "Return:eh_wait.\n"); 1077 return ret; 1078 } 1079 1080 while (CMD_SP(cmd) && wait_iter--) { 1081 msleep(ABORT_POLLING_PERIOD); 1082 } 1083 if (CMD_SP(cmd)) 1084 ret = QLA_FUNCTION_FAILED; 1085 1086 return ret; 1087 } 1088 1089 /* 1090 * qla2x00_wait_for_hba_online 1091 * Wait till the HBA is online after going through 1092 * <= MAX_RETRIES_OF_ISP_ABORT or 1093 * finally HBA is disabled ie marked offline 1094 * 1095 * Input: 1096 * ha - pointer to host adapter structure 1097 * 1098 * Note: 1099 * Does context switching-Release SPIN_LOCK 1100 * (if any) before calling this routine. 1101 * 1102 * Return: 1103 * Success (Adapter is online) : 0 1104 * Failed (Adapter is offline/disabled) : 1 1105 */ 1106 int 1107 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1108 { 1109 int return_status; 1110 unsigned long wait_online; 1111 struct qla_hw_data *ha = vha->hw; 1112 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1113 1114 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1115 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1116 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1117 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1118 ha->dpc_active) && time_before(jiffies, wait_online)) { 1119 1120 msleep(1000); 1121 } 1122 if (base_vha->flags.online) 1123 return_status = QLA_SUCCESS; 1124 else 1125 return_status = QLA_FUNCTION_FAILED; 1126 1127 return (return_status); 1128 } 1129 1130 static inline int test_fcport_count(scsi_qla_host_t *vha) 1131 { 1132 struct qla_hw_data *ha = vha->hw; 1133 unsigned long flags; 1134 int res; 1135 1136 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1137 ql_dbg(ql_dbg_init, vha, 0x00ec, 1138 "tgt %p, fcport_count=%d\n", 1139 vha, vha->fcport_count); 1140 res = (vha->fcport_count == 0); 1141 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1142 1143 return res; 1144 } 1145 1146 /* 1147 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1148 * it has dependency on UNLOADING flag to stop device discovery 1149 */ 1150 void 1151 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1152 { 1153 qla2x00_mark_all_devices_lost(vha, 0); 1154 1155 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ); 1156 } 1157 1158 /* 1159 * qla2x00_wait_for_hba_ready 1160 * Wait till the HBA is ready before doing driver unload 1161 * 1162 * Input: 1163 * ha - pointer to host adapter structure 1164 * 1165 * Note: 1166 * Does context switching-Release SPIN_LOCK 1167 * (if any) before calling this routine. 1168 * 1169 */ 1170 static void 1171 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1172 { 1173 struct qla_hw_data *ha = vha->hw; 1174 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1175 1176 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1177 ha->flags.mbox_busy) || 1178 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1179 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1180 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1181 break; 1182 msleep(1000); 1183 } 1184 } 1185 1186 int 1187 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1188 { 1189 int return_status; 1190 unsigned long wait_reset; 1191 struct qla_hw_data *ha = vha->hw; 1192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1193 1194 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1195 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1196 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1197 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1198 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1199 1200 msleep(1000); 1201 1202 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1203 ha->flags.chip_reset_done) 1204 break; 1205 } 1206 if (ha->flags.chip_reset_done) 1207 return_status = QLA_SUCCESS; 1208 else 1209 return_status = QLA_FUNCTION_FAILED; 1210 1211 return return_status; 1212 } 1213 1214 static int 1215 sp_get(struct srb *sp) 1216 { 1217 if (!refcount_inc_not_zero((refcount_t *)&sp->ref_count)) 1218 /* kref get fail */ 1219 return ENXIO; 1220 else 1221 return 0; 1222 } 1223 1224 #define ISP_REG_DISCONNECT 0xffffffffU 1225 /************************************************************************** 1226 * qla2x00_isp_reg_stat 1227 * 1228 * Description: 1229 * Read the host status register of ISP before aborting the command. 1230 * 1231 * Input: 1232 * ha = pointer to host adapter structure. 1233 * 1234 * 1235 * Returns: 1236 * Either true or false. 1237 * 1238 * Note: Return true if there is register disconnect. 1239 **************************************************************************/ 1240 static inline 1241 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha) 1242 { 1243 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1244 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 1245 1246 if (IS_P3P_TYPE(ha)) 1247 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); 1248 else 1249 return ((RD_REG_DWORD(®->host_status)) == 1250 ISP_REG_DISCONNECT); 1251 } 1252 1253 /************************************************************************** 1254 * qla2xxx_eh_abort 1255 * 1256 * Description: 1257 * The abort function will abort the specified command. 1258 * 1259 * Input: 1260 * cmd = Linux SCSI command packet to be aborted. 1261 * 1262 * Returns: 1263 * Either SUCCESS or FAILED. 1264 * 1265 * Note: 1266 * Only return FAILED if command not returned by firmware. 1267 **************************************************************************/ 1268 static int 1269 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1270 { 1271 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1272 srb_t *sp; 1273 int ret; 1274 unsigned int id; 1275 uint64_t lun; 1276 unsigned long flags; 1277 int rval; 1278 struct qla_hw_data *ha = vha->hw; 1279 struct qla_qpair *qpair; 1280 1281 if (qla2x00_isp_reg_stat(ha)) { 1282 ql_log(ql_log_info, vha, 0x8042, 1283 "PCI/Register disconnect, exiting.\n"); 1284 return FAILED; 1285 } 1286 1287 ret = fc_block_scsi_eh(cmd); 1288 if (ret != 0) 1289 return ret; 1290 1291 sp = (srb_t *) CMD_SP(cmd); 1292 if (!sp) 1293 return SUCCESS; 1294 1295 qpair = sp->qpair; 1296 if (!qpair) 1297 return SUCCESS; 1298 1299 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1300 if (sp->type != SRB_SCSI_CMD || GET_CMD_SP(sp) != cmd) { 1301 /* there's a chance an interrupt could clear 1302 the ptr as part of done & free */ 1303 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1304 return SUCCESS; 1305 } 1306 1307 if (sp_get(sp)){ 1308 /* ref_count is already 0 */ 1309 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1310 return SUCCESS; 1311 } 1312 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1313 1314 id = cmd->device->id; 1315 lun = cmd->device->lun; 1316 1317 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1318 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1319 vha->host_no, id, lun, sp, cmd, sp->handle); 1320 1321 rval = ha->isp_ops->abort_command(sp); 1322 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1323 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1324 1325 switch (rval) { 1326 case QLA_SUCCESS: 1327 /* 1328 * The command has been aborted. That means that the firmware 1329 * won't report a completion. 1330 */ 1331 sp->done(sp, DID_ABORT << 16); 1332 ret = SUCCESS; 1333 break; 1334 default: 1335 /* 1336 * Either abort failed or abort and completion raced. Let 1337 * the SCSI core retry the abort in the former case. 1338 */ 1339 ret = FAILED; 1340 break; 1341 } 1342 1343 ql_log(ql_log_info, vha, 0x801c, 1344 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1345 vha->host_no, id, lun, ret); 1346 1347 return ret; 1348 } 1349 1350 int 1351 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1352 uint64_t l, enum nexus_wait_type type) 1353 { 1354 int cnt, match, status; 1355 unsigned long flags; 1356 struct qla_hw_data *ha = vha->hw; 1357 struct req_que *req; 1358 srb_t *sp; 1359 struct scsi_cmnd *cmd; 1360 1361 status = QLA_SUCCESS; 1362 1363 spin_lock_irqsave(&ha->hardware_lock, flags); 1364 req = vha->req; 1365 for (cnt = 1; status == QLA_SUCCESS && 1366 cnt < req->num_outstanding_cmds; cnt++) { 1367 sp = req->outstanding_cmds[cnt]; 1368 if (!sp) 1369 continue; 1370 if (sp->type != SRB_SCSI_CMD) 1371 continue; 1372 if (vha->vp_idx != sp->vha->vp_idx) 1373 continue; 1374 match = 0; 1375 cmd = GET_CMD_SP(sp); 1376 switch (type) { 1377 case WAIT_HOST: 1378 match = 1; 1379 break; 1380 case WAIT_TARGET: 1381 match = cmd->device->id == t; 1382 break; 1383 case WAIT_LUN: 1384 match = (cmd->device->id == t && 1385 cmd->device->lun == l); 1386 break; 1387 } 1388 if (!match) 1389 continue; 1390 1391 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1392 status = qla2x00_eh_wait_on_command(cmd); 1393 spin_lock_irqsave(&ha->hardware_lock, flags); 1394 } 1395 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1396 1397 return status; 1398 } 1399 1400 static char *reset_errors[] = { 1401 "HBA not online", 1402 "HBA not ready", 1403 "Task management failed", 1404 "Waiting for command completions", 1405 }; 1406 1407 static int 1408 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1409 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1410 { 1411 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1412 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1413 int err; 1414 1415 if (!fcport) { 1416 return FAILED; 1417 } 1418 1419 err = fc_block_scsi_eh(cmd); 1420 if (err != 0) 1421 return err; 1422 1423 ql_log(ql_log_info, vha, 0x8009, 1424 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1425 cmd->device->id, cmd->device->lun, cmd); 1426 1427 err = 0; 1428 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1429 ql_log(ql_log_warn, vha, 0x800a, 1430 "Wait for hba online failed for cmd=%p.\n", cmd); 1431 goto eh_reset_failed; 1432 } 1433 err = 2; 1434 if (do_reset(fcport, cmd->device->lun, 1) 1435 != QLA_SUCCESS) { 1436 ql_log(ql_log_warn, vha, 0x800c, 1437 "do_reset failed for cmd=%p.\n", cmd); 1438 goto eh_reset_failed; 1439 } 1440 err = 3; 1441 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1442 cmd->device->lun, type) != QLA_SUCCESS) { 1443 ql_log(ql_log_warn, vha, 0x800d, 1444 "wait for pending cmds failed for cmd=%p.\n", cmd); 1445 goto eh_reset_failed; 1446 } 1447 1448 ql_log(ql_log_info, vha, 0x800e, 1449 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1450 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1451 1452 return SUCCESS; 1453 1454 eh_reset_failed: 1455 ql_log(ql_log_info, vha, 0x800f, 1456 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1457 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1458 cmd); 1459 return FAILED; 1460 } 1461 1462 static int 1463 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1464 { 1465 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1466 struct qla_hw_data *ha = vha->hw; 1467 1468 if (qla2x00_isp_reg_stat(ha)) { 1469 ql_log(ql_log_info, vha, 0x803e, 1470 "PCI/Register disconnect, exiting.\n"); 1471 return FAILED; 1472 } 1473 1474 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1475 ha->isp_ops->lun_reset); 1476 } 1477 1478 static int 1479 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1480 { 1481 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1482 struct qla_hw_data *ha = vha->hw; 1483 1484 if (qla2x00_isp_reg_stat(ha)) { 1485 ql_log(ql_log_info, vha, 0x803f, 1486 "PCI/Register disconnect, exiting.\n"); 1487 return FAILED; 1488 } 1489 1490 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1491 ha->isp_ops->target_reset); 1492 } 1493 1494 /************************************************************************** 1495 * qla2xxx_eh_bus_reset 1496 * 1497 * Description: 1498 * The bus reset function will reset the bus and abort any executing 1499 * commands. 1500 * 1501 * Input: 1502 * cmd = Linux SCSI command packet of the command that cause the 1503 * bus reset. 1504 * 1505 * Returns: 1506 * SUCCESS/FAILURE (defined as macro in scsi.h). 1507 * 1508 **************************************************************************/ 1509 static int 1510 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1511 { 1512 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1513 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1514 int ret = FAILED; 1515 unsigned int id; 1516 uint64_t lun; 1517 struct qla_hw_data *ha = vha->hw; 1518 1519 if (qla2x00_isp_reg_stat(ha)) { 1520 ql_log(ql_log_info, vha, 0x8040, 1521 "PCI/Register disconnect, exiting.\n"); 1522 return FAILED; 1523 } 1524 1525 id = cmd->device->id; 1526 lun = cmd->device->lun; 1527 1528 if (!fcport) { 1529 return ret; 1530 } 1531 1532 ret = fc_block_scsi_eh(cmd); 1533 if (ret != 0) 1534 return ret; 1535 ret = FAILED; 1536 1537 ql_log(ql_log_info, vha, 0x8012, 1538 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1539 1540 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1541 ql_log(ql_log_fatal, vha, 0x8013, 1542 "Wait for hba online failed board disabled.\n"); 1543 goto eh_bus_reset_done; 1544 } 1545 1546 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1547 ret = SUCCESS; 1548 1549 if (ret == FAILED) 1550 goto eh_bus_reset_done; 1551 1552 /* Flush outstanding commands. */ 1553 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1554 QLA_SUCCESS) { 1555 ql_log(ql_log_warn, vha, 0x8014, 1556 "Wait for pending commands failed.\n"); 1557 ret = FAILED; 1558 } 1559 1560 eh_bus_reset_done: 1561 ql_log(ql_log_warn, vha, 0x802b, 1562 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1563 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1564 1565 return ret; 1566 } 1567 1568 /************************************************************************** 1569 * qla2xxx_eh_host_reset 1570 * 1571 * Description: 1572 * The reset function will reset the Adapter. 1573 * 1574 * Input: 1575 * cmd = Linux SCSI command packet of the command that cause the 1576 * adapter reset. 1577 * 1578 * Returns: 1579 * Either SUCCESS or FAILED. 1580 * 1581 * Note: 1582 **************************************************************************/ 1583 static int 1584 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1585 { 1586 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1587 struct qla_hw_data *ha = vha->hw; 1588 int ret = FAILED; 1589 unsigned int id; 1590 uint64_t lun; 1591 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1592 1593 if (qla2x00_isp_reg_stat(ha)) { 1594 ql_log(ql_log_info, vha, 0x8041, 1595 "PCI/Register disconnect, exiting.\n"); 1596 schedule_work(&ha->board_disable); 1597 return SUCCESS; 1598 } 1599 1600 id = cmd->device->id; 1601 lun = cmd->device->lun; 1602 1603 ql_log(ql_log_info, vha, 0x8018, 1604 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1605 1606 /* 1607 * No point in issuing another reset if one is active. Also do not 1608 * attempt a reset if we are updating flash. 1609 */ 1610 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1611 goto eh_host_reset_lock; 1612 1613 if (vha != base_vha) { 1614 if (qla2x00_vp_abort_isp(vha)) 1615 goto eh_host_reset_lock; 1616 } else { 1617 if (IS_P3P_TYPE(vha->hw)) { 1618 if (!qla82xx_fcoe_ctx_reset(vha)) { 1619 /* Ctx reset success */ 1620 ret = SUCCESS; 1621 goto eh_host_reset_lock; 1622 } 1623 /* fall thru if ctx reset failed */ 1624 } 1625 if (ha->wq) 1626 flush_workqueue(ha->wq); 1627 1628 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1629 if (ha->isp_ops->abort_isp(base_vha)) { 1630 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1631 /* failed. schedule dpc to try */ 1632 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1633 1634 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1635 ql_log(ql_log_warn, vha, 0x802a, 1636 "wait for hba online failed.\n"); 1637 goto eh_host_reset_lock; 1638 } 1639 } 1640 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1641 } 1642 1643 /* Waiting for command to be returned to OS.*/ 1644 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1645 QLA_SUCCESS) 1646 ret = SUCCESS; 1647 1648 eh_host_reset_lock: 1649 ql_log(ql_log_info, vha, 0x8017, 1650 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1651 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1652 1653 return ret; 1654 } 1655 1656 /* 1657 * qla2x00_loop_reset 1658 * Issue loop reset. 1659 * 1660 * Input: 1661 * ha = adapter block pointer. 1662 * 1663 * Returns: 1664 * 0 = success 1665 */ 1666 int 1667 qla2x00_loop_reset(scsi_qla_host_t *vha) 1668 { 1669 int ret; 1670 struct fc_port *fcport; 1671 struct qla_hw_data *ha = vha->hw; 1672 1673 if (IS_QLAFX00(ha)) { 1674 return qlafx00_loop_reset(vha); 1675 } 1676 1677 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1678 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1679 if (fcport->port_type != FCT_TARGET) 1680 continue; 1681 1682 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1683 if (ret != QLA_SUCCESS) { 1684 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1685 "Bus Reset failed: Reset=%d " 1686 "d_id=%x.\n", ret, fcport->d_id.b24); 1687 } 1688 } 1689 } 1690 1691 1692 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1693 atomic_set(&vha->loop_state, LOOP_DOWN); 1694 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1695 qla2x00_mark_all_devices_lost(vha, 0); 1696 ret = qla2x00_full_login_lip(vha); 1697 if (ret != QLA_SUCCESS) { 1698 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1699 "full_login_lip=%d.\n", ret); 1700 } 1701 } 1702 1703 if (ha->flags.enable_lip_reset) { 1704 ret = qla2x00_lip_reset(vha); 1705 if (ret != QLA_SUCCESS) 1706 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1707 "lip_reset failed (%d).\n", ret); 1708 } 1709 1710 /* Issue marker command only when we are going to start the I/O */ 1711 vha->marker_needed = 1; 1712 1713 return QLA_SUCCESS; 1714 } 1715 1716 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1717 unsigned long *flags) 1718 __releases(qp->qp_lock_ptr) 1719 __acquires(qp->qp_lock_ptr) 1720 { 1721 DECLARE_COMPLETION_ONSTACK(comp); 1722 scsi_qla_host_t *vha = qp->vha; 1723 struct qla_hw_data *ha = vha->hw; 1724 int rval; 1725 1726 if (sp_get(sp)) 1727 return; 1728 1729 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1730 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1731 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1732 !qla2x00_isp_reg_stat(ha))) { 1733 sp->comp = ∁ 1734 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1735 rval = ha->isp_ops->abort_command(sp); 1736 1737 switch (rval) { 1738 case QLA_SUCCESS: 1739 sp->done(sp, res); 1740 break; 1741 case QLA_FUNCTION_PARAMETER_ERROR: 1742 wait_for_completion(&comp); 1743 break; 1744 } 1745 1746 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1747 sp->comp = NULL; 1748 } 1749 } 1750 1751 static void 1752 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1753 { 1754 int cnt; 1755 unsigned long flags; 1756 srb_t *sp; 1757 scsi_qla_host_t *vha = qp->vha; 1758 struct qla_hw_data *ha = vha->hw; 1759 struct req_que *req; 1760 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1761 struct qla_tgt_cmd *cmd; 1762 1763 if (!ha->req_q_map) 1764 return; 1765 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1766 req = qp->req; 1767 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1768 sp = req->outstanding_cmds[cnt]; 1769 if (sp) { 1770 req->outstanding_cmds[cnt] = NULL; 1771 switch (sp->cmd_type) { 1772 case TYPE_SRB: 1773 qla2x00_abort_srb(qp, sp, res, &flags); 1774 break; 1775 case TYPE_TGT_CMD: 1776 if (!vha->hw->tgt.tgt_ops || !tgt || 1777 qla_ini_mode_enabled(vha)) { 1778 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1779 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1780 vha->dpc_flags); 1781 continue; 1782 } 1783 cmd = (struct qla_tgt_cmd *)sp; 1784 cmd->aborted = 1; 1785 break; 1786 case TYPE_TGT_TMCMD: 1787 /* Skip task management functions. */ 1788 break; 1789 default: 1790 break; 1791 } 1792 } 1793 } 1794 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1795 } 1796 1797 void 1798 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1799 { 1800 int que; 1801 struct qla_hw_data *ha = vha->hw; 1802 1803 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1804 1805 for (que = 0; que < ha->max_qpairs; que++) { 1806 if (!ha->queue_pair_map[que]) 1807 continue; 1808 1809 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1810 } 1811 } 1812 1813 static int 1814 qla2xxx_slave_alloc(struct scsi_device *sdev) 1815 { 1816 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1817 1818 if (!rport || fc_remote_port_chkready(rport)) 1819 return -ENXIO; 1820 1821 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1822 1823 return 0; 1824 } 1825 1826 static int 1827 qla2xxx_slave_configure(struct scsi_device *sdev) 1828 { 1829 scsi_qla_host_t *vha = shost_priv(sdev->host); 1830 struct req_que *req = vha->req; 1831 1832 if (IS_T10_PI_CAPABLE(vha->hw)) 1833 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1834 1835 scsi_change_queue_depth(sdev, req->max_q_depth); 1836 return 0; 1837 } 1838 1839 static void 1840 qla2xxx_slave_destroy(struct scsi_device *sdev) 1841 { 1842 sdev->hostdata = NULL; 1843 } 1844 1845 /** 1846 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1847 * @ha: HA context 1848 * 1849 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1850 * supported addressing method. 1851 */ 1852 static void 1853 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1854 { 1855 /* Assume a 32bit DMA mask. */ 1856 ha->flags.enable_64bit_addressing = 0; 1857 1858 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1859 /* Any upper-dword bits set? */ 1860 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1861 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { 1862 /* Ok, a 64bit DMA mask is applicable. */ 1863 ha->flags.enable_64bit_addressing = 1; 1864 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1865 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1866 return; 1867 } 1868 } 1869 1870 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1871 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); 1872 } 1873 1874 static void 1875 qla2x00_enable_intrs(struct qla_hw_data *ha) 1876 { 1877 unsigned long flags = 0; 1878 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1879 1880 spin_lock_irqsave(&ha->hardware_lock, flags); 1881 ha->interrupts_on = 1; 1882 /* enable risc and host interrupts */ 1883 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1884 RD_REG_WORD(®->ictrl); 1885 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1886 1887 } 1888 1889 static void 1890 qla2x00_disable_intrs(struct qla_hw_data *ha) 1891 { 1892 unsigned long flags = 0; 1893 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1894 1895 spin_lock_irqsave(&ha->hardware_lock, flags); 1896 ha->interrupts_on = 0; 1897 /* disable risc and host interrupts */ 1898 WRT_REG_WORD(®->ictrl, 0); 1899 RD_REG_WORD(®->ictrl); 1900 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1901 } 1902 1903 static void 1904 qla24xx_enable_intrs(struct qla_hw_data *ha) 1905 { 1906 unsigned long flags = 0; 1907 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1908 1909 spin_lock_irqsave(&ha->hardware_lock, flags); 1910 ha->interrupts_on = 1; 1911 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); 1912 RD_REG_DWORD(®->ictrl); 1913 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1914 } 1915 1916 static void 1917 qla24xx_disable_intrs(struct qla_hw_data *ha) 1918 { 1919 unsigned long flags = 0; 1920 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1921 1922 if (IS_NOPOLLING_TYPE(ha)) 1923 return; 1924 spin_lock_irqsave(&ha->hardware_lock, flags); 1925 ha->interrupts_on = 0; 1926 WRT_REG_DWORD(®->ictrl, 0); 1927 RD_REG_DWORD(®->ictrl); 1928 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1929 } 1930 1931 static int 1932 qla2x00_iospace_config(struct qla_hw_data *ha) 1933 { 1934 resource_size_t pio; 1935 uint16_t msix; 1936 1937 if (pci_request_selected_regions(ha->pdev, ha->bars, 1938 QLA2XXX_DRIVER_NAME)) { 1939 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1940 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1941 pci_name(ha->pdev)); 1942 goto iospace_error_exit; 1943 } 1944 if (!(ha->bars & 1)) 1945 goto skip_pio; 1946 1947 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1948 pio = pci_resource_start(ha->pdev, 0); 1949 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1950 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1951 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1952 "Invalid pci I/O region size (%s).\n", 1953 pci_name(ha->pdev)); 1954 pio = 0; 1955 } 1956 } else { 1957 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1958 "Region #0 no a PIO resource (%s).\n", 1959 pci_name(ha->pdev)); 1960 pio = 0; 1961 } 1962 ha->pio_address = pio; 1963 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1964 "PIO address=%llu.\n", 1965 (unsigned long long)ha->pio_address); 1966 1967 skip_pio: 1968 /* Use MMIO operations for all accesses. */ 1969 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1970 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1971 "Region #1 not an MMIO resource (%s), aborting.\n", 1972 pci_name(ha->pdev)); 1973 goto iospace_error_exit; 1974 } 1975 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1976 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1977 "Invalid PCI mem region size (%s), aborting.\n", 1978 pci_name(ha->pdev)); 1979 goto iospace_error_exit; 1980 } 1981 1982 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1983 if (!ha->iobase) { 1984 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1985 "Cannot remap MMIO (%s), aborting.\n", 1986 pci_name(ha->pdev)); 1987 goto iospace_error_exit; 1988 } 1989 1990 /* Determine queue resources */ 1991 ha->max_req_queues = ha->max_rsp_queues = 1; 1992 ha->msix_count = QLA_BASE_VECTORS; 1993 if (!ql2xmqsupport || !ql2xnvmeenable || 1994 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 1995 goto mqiobase_exit; 1996 1997 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 1998 pci_resource_len(ha->pdev, 3)); 1999 if (ha->mqiobase) { 2000 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2001 "MQIO Base=%p.\n", ha->mqiobase); 2002 /* Read MSIX vector size of the board */ 2003 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2004 ha->msix_count = msix + 1; 2005 /* Max queues are bounded by available msix vectors */ 2006 /* MB interrupt uses 1 vector */ 2007 ha->max_req_queues = ha->msix_count - 1; 2008 ha->max_rsp_queues = ha->max_req_queues; 2009 /* Queue pairs is the max value minus the base queue pair */ 2010 ha->max_qpairs = ha->max_rsp_queues - 1; 2011 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2012 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2013 2014 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2015 "MSI-X vector count: %d.\n", ha->msix_count); 2016 } else 2017 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2018 "BAR 3 not enabled.\n"); 2019 2020 mqiobase_exit: 2021 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2022 "MSIX Count: %d.\n", ha->msix_count); 2023 return (0); 2024 2025 iospace_error_exit: 2026 return (-ENOMEM); 2027 } 2028 2029 2030 static int 2031 qla83xx_iospace_config(struct qla_hw_data *ha) 2032 { 2033 uint16_t msix; 2034 2035 if (pci_request_selected_regions(ha->pdev, ha->bars, 2036 QLA2XXX_DRIVER_NAME)) { 2037 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2038 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2039 pci_name(ha->pdev)); 2040 2041 goto iospace_error_exit; 2042 } 2043 2044 /* Use MMIO operations for all accesses. */ 2045 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2046 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2047 "Invalid pci I/O region size (%s).\n", 2048 pci_name(ha->pdev)); 2049 goto iospace_error_exit; 2050 } 2051 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2052 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2053 "Invalid PCI mem region size (%s), aborting\n", 2054 pci_name(ha->pdev)); 2055 goto iospace_error_exit; 2056 } 2057 2058 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2059 if (!ha->iobase) { 2060 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2061 "Cannot remap MMIO (%s), aborting.\n", 2062 pci_name(ha->pdev)); 2063 goto iospace_error_exit; 2064 } 2065 2066 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2067 /* 83XX 26XX always use MQ type access for queues 2068 * - mbar 2, a.k.a region 4 */ 2069 ha->max_req_queues = ha->max_rsp_queues = 1; 2070 ha->msix_count = QLA_BASE_VECTORS; 2071 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2072 pci_resource_len(ha->pdev, 4)); 2073 2074 if (!ha->mqiobase) { 2075 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2076 "BAR2/region4 not enabled\n"); 2077 goto mqiobase_exit; 2078 } 2079 2080 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2081 pci_resource_len(ha->pdev, 2)); 2082 if (ha->msixbase) { 2083 /* Read MSIX vector size of the board */ 2084 pci_read_config_word(ha->pdev, 2085 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2086 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2087 /* 2088 * By default, driver uses at least two msix vectors 2089 * (default & rspq) 2090 */ 2091 if (ql2xmqsupport || ql2xnvmeenable) { 2092 /* MB interrupt uses 1 vector */ 2093 ha->max_req_queues = ha->msix_count - 1; 2094 2095 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2096 if (QLA_TGT_MODE_ENABLED()) 2097 ha->max_req_queues--; 2098 2099 ha->max_rsp_queues = ha->max_req_queues; 2100 2101 /* Queue pairs is the max value minus 2102 * the base queue pair */ 2103 ha->max_qpairs = ha->max_req_queues - 1; 2104 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2105 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2106 } 2107 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2108 "MSI-X vector count: %d.\n", ha->msix_count); 2109 } else 2110 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2111 "BAR 1 not enabled.\n"); 2112 2113 mqiobase_exit: 2114 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2115 "MSIX Count: %d.\n", ha->msix_count); 2116 return 0; 2117 2118 iospace_error_exit: 2119 return -ENOMEM; 2120 } 2121 2122 static struct isp_operations qla2100_isp_ops = { 2123 .pci_config = qla2100_pci_config, 2124 .reset_chip = qla2x00_reset_chip, 2125 .chip_diag = qla2x00_chip_diag, 2126 .config_rings = qla2x00_config_rings, 2127 .reset_adapter = qla2x00_reset_adapter, 2128 .nvram_config = qla2x00_nvram_config, 2129 .update_fw_options = qla2x00_update_fw_options, 2130 .load_risc = qla2x00_load_risc, 2131 .pci_info_str = qla2x00_pci_info_str, 2132 .fw_version_str = qla2x00_fw_version_str, 2133 .intr_handler = qla2100_intr_handler, 2134 .enable_intrs = qla2x00_enable_intrs, 2135 .disable_intrs = qla2x00_disable_intrs, 2136 .abort_command = qla2x00_abort_command, 2137 .target_reset = qla2x00_abort_target, 2138 .lun_reset = qla2x00_lun_reset, 2139 .fabric_login = qla2x00_login_fabric, 2140 .fabric_logout = qla2x00_fabric_logout, 2141 .calc_req_entries = qla2x00_calc_iocbs_32, 2142 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2143 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2144 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2145 .read_nvram = qla2x00_read_nvram_data, 2146 .write_nvram = qla2x00_write_nvram_data, 2147 .fw_dump = qla2100_fw_dump, 2148 .beacon_on = NULL, 2149 .beacon_off = NULL, 2150 .beacon_blink = NULL, 2151 .read_optrom = qla2x00_read_optrom_data, 2152 .write_optrom = qla2x00_write_optrom_data, 2153 .get_flash_version = qla2x00_get_flash_version, 2154 .start_scsi = qla2x00_start_scsi, 2155 .start_scsi_mq = NULL, 2156 .abort_isp = qla2x00_abort_isp, 2157 .iospace_config = qla2x00_iospace_config, 2158 .initialize_adapter = qla2x00_initialize_adapter, 2159 }; 2160 2161 static struct isp_operations qla2300_isp_ops = { 2162 .pci_config = qla2300_pci_config, 2163 .reset_chip = qla2x00_reset_chip, 2164 .chip_diag = qla2x00_chip_diag, 2165 .config_rings = qla2x00_config_rings, 2166 .reset_adapter = qla2x00_reset_adapter, 2167 .nvram_config = qla2x00_nvram_config, 2168 .update_fw_options = qla2x00_update_fw_options, 2169 .load_risc = qla2x00_load_risc, 2170 .pci_info_str = qla2x00_pci_info_str, 2171 .fw_version_str = qla2x00_fw_version_str, 2172 .intr_handler = qla2300_intr_handler, 2173 .enable_intrs = qla2x00_enable_intrs, 2174 .disable_intrs = qla2x00_disable_intrs, 2175 .abort_command = qla2x00_abort_command, 2176 .target_reset = qla2x00_abort_target, 2177 .lun_reset = qla2x00_lun_reset, 2178 .fabric_login = qla2x00_login_fabric, 2179 .fabric_logout = qla2x00_fabric_logout, 2180 .calc_req_entries = qla2x00_calc_iocbs_32, 2181 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2182 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2183 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2184 .read_nvram = qla2x00_read_nvram_data, 2185 .write_nvram = qla2x00_write_nvram_data, 2186 .fw_dump = qla2300_fw_dump, 2187 .beacon_on = qla2x00_beacon_on, 2188 .beacon_off = qla2x00_beacon_off, 2189 .beacon_blink = qla2x00_beacon_blink, 2190 .read_optrom = qla2x00_read_optrom_data, 2191 .write_optrom = qla2x00_write_optrom_data, 2192 .get_flash_version = qla2x00_get_flash_version, 2193 .start_scsi = qla2x00_start_scsi, 2194 .start_scsi_mq = NULL, 2195 .abort_isp = qla2x00_abort_isp, 2196 .iospace_config = qla2x00_iospace_config, 2197 .initialize_adapter = qla2x00_initialize_adapter, 2198 }; 2199 2200 static struct isp_operations qla24xx_isp_ops = { 2201 .pci_config = qla24xx_pci_config, 2202 .reset_chip = qla24xx_reset_chip, 2203 .chip_diag = qla24xx_chip_diag, 2204 .config_rings = qla24xx_config_rings, 2205 .reset_adapter = qla24xx_reset_adapter, 2206 .nvram_config = qla24xx_nvram_config, 2207 .update_fw_options = qla24xx_update_fw_options, 2208 .load_risc = qla24xx_load_risc, 2209 .pci_info_str = qla24xx_pci_info_str, 2210 .fw_version_str = qla24xx_fw_version_str, 2211 .intr_handler = qla24xx_intr_handler, 2212 .enable_intrs = qla24xx_enable_intrs, 2213 .disable_intrs = qla24xx_disable_intrs, 2214 .abort_command = qla24xx_abort_command, 2215 .target_reset = qla24xx_abort_target, 2216 .lun_reset = qla24xx_lun_reset, 2217 .fabric_login = qla24xx_login_fabric, 2218 .fabric_logout = qla24xx_fabric_logout, 2219 .calc_req_entries = NULL, 2220 .build_iocbs = NULL, 2221 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2222 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2223 .read_nvram = qla24xx_read_nvram_data, 2224 .write_nvram = qla24xx_write_nvram_data, 2225 .fw_dump = qla24xx_fw_dump, 2226 .beacon_on = qla24xx_beacon_on, 2227 .beacon_off = qla24xx_beacon_off, 2228 .beacon_blink = qla24xx_beacon_blink, 2229 .read_optrom = qla24xx_read_optrom_data, 2230 .write_optrom = qla24xx_write_optrom_data, 2231 .get_flash_version = qla24xx_get_flash_version, 2232 .start_scsi = qla24xx_start_scsi, 2233 .start_scsi_mq = NULL, 2234 .abort_isp = qla2x00_abort_isp, 2235 .iospace_config = qla2x00_iospace_config, 2236 .initialize_adapter = qla2x00_initialize_adapter, 2237 }; 2238 2239 static struct isp_operations qla25xx_isp_ops = { 2240 .pci_config = qla25xx_pci_config, 2241 .reset_chip = qla24xx_reset_chip, 2242 .chip_diag = qla24xx_chip_diag, 2243 .config_rings = qla24xx_config_rings, 2244 .reset_adapter = qla24xx_reset_adapter, 2245 .nvram_config = qla24xx_nvram_config, 2246 .update_fw_options = qla24xx_update_fw_options, 2247 .load_risc = qla24xx_load_risc, 2248 .pci_info_str = qla24xx_pci_info_str, 2249 .fw_version_str = qla24xx_fw_version_str, 2250 .intr_handler = qla24xx_intr_handler, 2251 .enable_intrs = qla24xx_enable_intrs, 2252 .disable_intrs = qla24xx_disable_intrs, 2253 .abort_command = qla24xx_abort_command, 2254 .target_reset = qla24xx_abort_target, 2255 .lun_reset = qla24xx_lun_reset, 2256 .fabric_login = qla24xx_login_fabric, 2257 .fabric_logout = qla24xx_fabric_logout, 2258 .calc_req_entries = NULL, 2259 .build_iocbs = NULL, 2260 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2261 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2262 .read_nvram = qla25xx_read_nvram_data, 2263 .write_nvram = qla25xx_write_nvram_data, 2264 .fw_dump = qla25xx_fw_dump, 2265 .beacon_on = qla24xx_beacon_on, 2266 .beacon_off = qla24xx_beacon_off, 2267 .beacon_blink = qla24xx_beacon_blink, 2268 .read_optrom = qla25xx_read_optrom_data, 2269 .write_optrom = qla24xx_write_optrom_data, 2270 .get_flash_version = qla24xx_get_flash_version, 2271 .start_scsi = qla24xx_dif_start_scsi, 2272 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2273 .abort_isp = qla2x00_abort_isp, 2274 .iospace_config = qla2x00_iospace_config, 2275 .initialize_adapter = qla2x00_initialize_adapter, 2276 }; 2277 2278 static struct isp_operations qla81xx_isp_ops = { 2279 .pci_config = qla25xx_pci_config, 2280 .reset_chip = qla24xx_reset_chip, 2281 .chip_diag = qla24xx_chip_diag, 2282 .config_rings = qla24xx_config_rings, 2283 .reset_adapter = qla24xx_reset_adapter, 2284 .nvram_config = qla81xx_nvram_config, 2285 .update_fw_options = qla81xx_update_fw_options, 2286 .load_risc = qla81xx_load_risc, 2287 .pci_info_str = qla24xx_pci_info_str, 2288 .fw_version_str = qla24xx_fw_version_str, 2289 .intr_handler = qla24xx_intr_handler, 2290 .enable_intrs = qla24xx_enable_intrs, 2291 .disable_intrs = qla24xx_disable_intrs, 2292 .abort_command = qla24xx_abort_command, 2293 .target_reset = qla24xx_abort_target, 2294 .lun_reset = qla24xx_lun_reset, 2295 .fabric_login = qla24xx_login_fabric, 2296 .fabric_logout = qla24xx_fabric_logout, 2297 .calc_req_entries = NULL, 2298 .build_iocbs = NULL, 2299 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2300 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2301 .read_nvram = NULL, 2302 .write_nvram = NULL, 2303 .fw_dump = qla81xx_fw_dump, 2304 .beacon_on = qla24xx_beacon_on, 2305 .beacon_off = qla24xx_beacon_off, 2306 .beacon_blink = qla83xx_beacon_blink, 2307 .read_optrom = qla25xx_read_optrom_data, 2308 .write_optrom = qla24xx_write_optrom_data, 2309 .get_flash_version = qla24xx_get_flash_version, 2310 .start_scsi = qla24xx_dif_start_scsi, 2311 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2312 .abort_isp = qla2x00_abort_isp, 2313 .iospace_config = qla2x00_iospace_config, 2314 .initialize_adapter = qla2x00_initialize_adapter, 2315 }; 2316 2317 static struct isp_operations qla82xx_isp_ops = { 2318 .pci_config = qla82xx_pci_config, 2319 .reset_chip = qla82xx_reset_chip, 2320 .chip_diag = qla24xx_chip_diag, 2321 .config_rings = qla82xx_config_rings, 2322 .reset_adapter = qla24xx_reset_adapter, 2323 .nvram_config = qla81xx_nvram_config, 2324 .update_fw_options = qla24xx_update_fw_options, 2325 .load_risc = qla82xx_load_risc, 2326 .pci_info_str = qla24xx_pci_info_str, 2327 .fw_version_str = qla24xx_fw_version_str, 2328 .intr_handler = qla82xx_intr_handler, 2329 .enable_intrs = qla82xx_enable_intrs, 2330 .disable_intrs = qla82xx_disable_intrs, 2331 .abort_command = qla24xx_abort_command, 2332 .target_reset = qla24xx_abort_target, 2333 .lun_reset = qla24xx_lun_reset, 2334 .fabric_login = qla24xx_login_fabric, 2335 .fabric_logout = qla24xx_fabric_logout, 2336 .calc_req_entries = NULL, 2337 .build_iocbs = NULL, 2338 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2339 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2340 .read_nvram = qla24xx_read_nvram_data, 2341 .write_nvram = qla24xx_write_nvram_data, 2342 .fw_dump = qla82xx_fw_dump, 2343 .beacon_on = qla82xx_beacon_on, 2344 .beacon_off = qla82xx_beacon_off, 2345 .beacon_blink = NULL, 2346 .read_optrom = qla82xx_read_optrom_data, 2347 .write_optrom = qla82xx_write_optrom_data, 2348 .get_flash_version = qla82xx_get_flash_version, 2349 .start_scsi = qla82xx_start_scsi, 2350 .start_scsi_mq = NULL, 2351 .abort_isp = qla82xx_abort_isp, 2352 .iospace_config = qla82xx_iospace_config, 2353 .initialize_adapter = qla2x00_initialize_adapter, 2354 }; 2355 2356 static struct isp_operations qla8044_isp_ops = { 2357 .pci_config = qla82xx_pci_config, 2358 .reset_chip = qla82xx_reset_chip, 2359 .chip_diag = qla24xx_chip_diag, 2360 .config_rings = qla82xx_config_rings, 2361 .reset_adapter = qla24xx_reset_adapter, 2362 .nvram_config = qla81xx_nvram_config, 2363 .update_fw_options = qla24xx_update_fw_options, 2364 .load_risc = qla82xx_load_risc, 2365 .pci_info_str = qla24xx_pci_info_str, 2366 .fw_version_str = qla24xx_fw_version_str, 2367 .intr_handler = qla8044_intr_handler, 2368 .enable_intrs = qla82xx_enable_intrs, 2369 .disable_intrs = qla82xx_disable_intrs, 2370 .abort_command = qla24xx_abort_command, 2371 .target_reset = qla24xx_abort_target, 2372 .lun_reset = qla24xx_lun_reset, 2373 .fabric_login = qla24xx_login_fabric, 2374 .fabric_logout = qla24xx_fabric_logout, 2375 .calc_req_entries = NULL, 2376 .build_iocbs = NULL, 2377 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2378 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2379 .read_nvram = NULL, 2380 .write_nvram = NULL, 2381 .fw_dump = qla8044_fw_dump, 2382 .beacon_on = qla82xx_beacon_on, 2383 .beacon_off = qla82xx_beacon_off, 2384 .beacon_blink = NULL, 2385 .read_optrom = qla8044_read_optrom_data, 2386 .write_optrom = qla8044_write_optrom_data, 2387 .get_flash_version = qla82xx_get_flash_version, 2388 .start_scsi = qla82xx_start_scsi, 2389 .start_scsi_mq = NULL, 2390 .abort_isp = qla8044_abort_isp, 2391 .iospace_config = qla82xx_iospace_config, 2392 .initialize_adapter = qla2x00_initialize_adapter, 2393 }; 2394 2395 static struct isp_operations qla83xx_isp_ops = { 2396 .pci_config = qla25xx_pci_config, 2397 .reset_chip = qla24xx_reset_chip, 2398 .chip_diag = qla24xx_chip_diag, 2399 .config_rings = qla24xx_config_rings, 2400 .reset_adapter = qla24xx_reset_adapter, 2401 .nvram_config = qla81xx_nvram_config, 2402 .update_fw_options = qla81xx_update_fw_options, 2403 .load_risc = qla81xx_load_risc, 2404 .pci_info_str = qla24xx_pci_info_str, 2405 .fw_version_str = qla24xx_fw_version_str, 2406 .intr_handler = qla24xx_intr_handler, 2407 .enable_intrs = qla24xx_enable_intrs, 2408 .disable_intrs = qla24xx_disable_intrs, 2409 .abort_command = qla24xx_abort_command, 2410 .target_reset = qla24xx_abort_target, 2411 .lun_reset = qla24xx_lun_reset, 2412 .fabric_login = qla24xx_login_fabric, 2413 .fabric_logout = qla24xx_fabric_logout, 2414 .calc_req_entries = NULL, 2415 .build_iocbs = NULL, 2416 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2417 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2418 .read_nvram = NULL, 2419 .write_nvram = NULL, 2420 .fw_dump = qla83xx_fw_dump, 2421 .beacon_on = qla24xx_beacon_on, 2422 .beacon_off = qla24xx_beacon_off, 2423 .beacon_blink = qla83xx_beacon_blink, 2424 .read_optrom = qla25xx_read_optrom_data, 2425 .write_optrom = qla24xx_write_optrom_data, 2426 .get_flash_version = qla24xx_get_flash_version, 2427 .start_scsi = qla24xx_dif_start_scsi, 2428 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2429 .abort_isp = qla2x00_abort_isp, 2430 .iospace_config = qla83xx_iospace_config, 2431 .initialize_adapter = qla2x00_initialize_adapter, 2432 }; 2433 2434 static struct isp_operations qlafx00_isp_ops = { 2435 .pci_config = qlafx00_pci_config, 2436 .reset_chip = qlafx00_soft_reset, 2437 .chip_diag = qlafx00_chip_diag, 2438 .config_rings = qlafx00_config_rings, 2439 .reset_adapter = qlafx00_soft_reset, 2440 .nvram_config = NULL, 2441 .update_fw_options = NULL, 2442 .load_risc = NULL, 2443 .pci_info_str = qlafx00_pci_info_str, 2444 .fw_version_str = qlafx00_fw_version_str, 2445 .intr_handler = qlafx00_intr_handler, 2446 .enable_intrs = qlafx00_enable_intrs, 2447 .disable_intrs = qlafx00_disable_intrs, 2448 .abort_command = qla24xx_async_abort_command, 2449 .target_reset = qlafx00_abort_target, 2450 .lun_reset = qlafx00_lun_reset, 2451 .fabric_login = NULL, 2452 .fabric_logout = NULL, 2453 .calc_req_entries = NULL, 2454 .build_iocbs = NULL, 2455 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2456 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2457 .read_nvram = qla24xx_read_nvram_data, 2458 .write_nvram = qla24xx_write_nvram_data, 2459 .fw_dump = NULL, 2460 .beacon_on = qla24xx_beacon_on, 2461 .beacon_off = qla24xx_beacon_off, 2462 .beacon_blink = NULL, 2463 .read_optrom = qla24xx_read_optrom_data, 2464 .write_optrom = qla24xx_write_optrom_data, 2465 .get_flash_version = qla24xx_get_flash_version, 2466 .start_scsi = qlafx00_start_scsi, 2467 .start_scsi_mq = NULL, 2468 .abort_isp = qlafx00_abort_isp, 2469 .iospace_config = qlafx00_iospace_config, 2470 .initialize_adapter = qlafx00_initialize_adapter, 2471 }; 2472 2473 static struct isp_operations qla27xx_isp_ops = { 2474 .pci_config = qla25xx_pci_config, 2475 .reset_chip = qla24xx_reset_chip, 2476 .chip_diag = qla24xx_chip_diag, 2477 .config_rings = qla24xx_config_rings, 2478 .reset_adapter = qla24xx_reset_adapter, 2479 .nvram_config = qla81xx_nvram_config, 2480 .update_fw_options = qla81xx_update_fw_options, 2481 .load_risc = qla81xx_load_risc, 2482 .pci_info_str = qla24xx_pci_info_str, 2483 .fw_version_str = qla24xx_fw_version_str, 2484 .intr_handler = qla24xx_intr_handler, 2485 .enable_intrs = qla24xx_enable_intrs, 2486 .disable_intrs = qla24xx_disable_intrs, 2487 .abort_command = qla24xx_abort_command, 2488 .target_reset = qla24xx_abort_target, 2489 .lun_reset = qla24xx_lun_reset, 2490 .fabric_login = qla24xx_login_fabric, 2491 .fabric_logout = qla24xx_fabric_logout, 2492 .calc_req_entries = NULL, 2493 .build_iocbs = NULL, 2494 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2495 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2496 .read_nvram = NULL, 2497 .write_nvram = NULL, 2498 .fw_dump = qla27xx_fwdump, 2499 .beacon_on = qla24xx_beacon_on, 2500 .beacon_off = qla24xx_beacon_off, 2501 .beacon_blink = qla83xx_beacon_blink, 2502 .read_optrom = qla25xx_read_optrom_data, 2503 .write_optrom = qla24xx_write_optrom_data, 2504 .get_flash_version = qla24xx_get_flash_version, 2505 .start_scsi = qla24xx_dif_start_scsi, 2506 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2507 .abort_isp = qla2x00_abort_isp, 2508 .iospace_config = qla83xx_iospace_config, 2509 .initialize_adapter = qla2x00_initialize_adapter, 2510 }; 2511 2512 static inline void 2513 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2514 { 2515 ha->device_type = DT_EXTENDED_IDS; 2516 switch (ha->pdev->device) { 2517 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2518 ha->isp_type |= DT_ISP2100; 2519 ha->device_type &= ~DT_EXTENDED_IDS; 2520 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2521 break; 2522 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2523 ha->isp_type |= DT_ISP2200; 2524 ha->device_type &= ~DT_EXTENDED_IDS; 2525 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2526 break; 2527 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2528 ha->isp_type |= DT_ISP2300; 2529 ha->device_type |= DT_ZIO_SUPPORTED; 2530 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2531 break; 2532 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2533 ha->isp_type |= DT_ISP2312; 2534 ha->device_type |= DT_ZIO_SUPPORTED; 2535 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2536 break; 2537 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2538 ha->isp_type |= DT_ISP2322; 2539 ha->device_type |= DT_ZIO_SUPPORTED; 2540 if (ha->pdev->subsystem_vendor == 0x1028 && 2541 ha->pdev->subsystem_device == 0x0170) 2542 ha->device_type |= DT_OEM_001; 2543 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2544 break; 2545 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2546 ha->isp_type |= DT_ISP6312; 2547 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2548 break; 2549 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2550 ha->isp_type |= DT_ISP6322; 2551 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2552 break; 2553 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2554 ha->isp_type |= DT_ISP2422; 2555 ha->device_type |= DT_ZIO_SUPPORTED; 2556 ha->device_type |= DT_FWI2; 2557 ha->device_type |= DT_IIDMA; 2558 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2559 break; 2560 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2561 ha->isp_type |= DT_ISP2432; 2562 ha->device_type |= DT_ZIO_SUPPORTED; 2563 ha->device_type |= DT_FWI2; 2564 ha->device_type |= DT_IIDMA; 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2566 break; 2567 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2568 ha->isp_type |= DT_ISP8432; 2569 ha->device_type |= DT_ZIO_SUPPORTED; 2570 ha->device_type |= DT_FWI2; 2571 ha->device_type |= DT_IIDMA; 2572 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2573 break; 2574 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2575 ha->isp_type |= DT_ISP5422; 2576 ha->device_type |= DT_FWI2; 2577 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2578 break; 2579 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2580 ha->isp_type |= DT_ISP5432; 2581 ha->device_type |= DT_FWI2; 2582 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2583 break; 2584 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2585 ha->isp_type |= DT_ISP2532; 2586 ha->device_type |= DT_ZIO_SUPPORTED; 2587 ha->device_type |= DT_FWI2; 2588 ha->device_type |= DT_IIDMA; 2589 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2590 break; 2591 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2592 ha->isp_type |= DT_ISP8001; 2593 ha->device_type |= DT_ZIO_SUPPORTED; 2594 ha->device_type |= DT_FWI2; 2595 ha->device_type |= DT_IIDMA; 2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2597 break; 2598 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2599 ha->isp_type |= DT_ISP8021; 2600 ha->device_type |= DT_ZIO_SUPPORTED; 2601 ha->device_type |= DT_FWI2; 2602 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2603 /* Initialize 82XX ISP flags */ 2604 qla82xx_init_flags(ha); 2605 break; 2606 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2607 ha->isp_type |= DT_ISP8044; 2608 ha->device_type |= DT_ZIO_SUPPORTED; 2609 ha->device_type |= DT_FWI2; 2610 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2611 /* Initialize 82XX ISP flags */ 2612 qla82xx_init_flags(ha); 2613 break; 2614 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2615 ha->isp_type |= DT_ISP2031; 2616 ha->device_type |= DT_ZIO_SUPPORTED; 2617 ha->device_type |= DT_FWI2; 2618 ha->device_type |= DT_IIDMA; 2619 ha->device_type |= DT_T10_PI; 2620 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2621 break; 2622 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2623 ha->isp_type |= DT_ISP8031; 2624 ha->device_type |= DT_ZIO_SUPPORTED; 2625 ha->device_type |= DT_FWI2; 2626 ha->device_type |= DT_IIDMA; 2627 ha->device_type |= DT_T10_PI; 2628 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2629 break; 2630 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2631 ha->isp_type |= DT_ISPFX00; 2632 break; 2633 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2634 ha->isp_type |= DT_ISP2071; 2635 ha->device_type |= DT_ZIO_SUPPORTED; 2636 ha->device_type |= DT_FWI2; 2637 ha->device_type |= DT_IIDMA; 2638 ha->device_type |= DT_T10_PI; 2639 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2640 break; 2641 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2642 ha->isp_type |= DT_ISP2271; 2643 ha->device_type |= DT_ZIO_SUPPORTED; 2644 ha->device_type |= DT_FWI2; 2645 ha->device_type |= DT_IIDMA; 2646 ha->device_type |= DT_T10_PI; 2647 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2648 break; 2649 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2650 ha->isp_type |= DT_ISP2261; 2651 ha->device_type |= DT_ZIO_SUPPORTED; 2652 ha->device_type |= DT_FWI2; 2653 ha->device_type |= DT_IIDMA; 2654 ha->device_type |= DT_T10_PI; 2655 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2656 break; 2657 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2658 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2659 ha->isp_type |= DT_ISP2081; 2660 ha->device_type |= DT_ZIO_SUPPORTED; 2661 ha->device_type |= DT_FWI2; 2662 ha->device_type |= DT_IIDMA; 2663 ha->device_type |= DT_T10_PI; 2664 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2665 break; 2666 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2667 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2668 ha->isp_type |= DT_ISP2281; 2669 ha->device_type |= DT_ZIO_SUPPORTED; 2670 ha->device_type |= DT_FWI2; 2671 ha->device_type |= DT_IIDMA; 2672 ha->device_type |= DT_T10_PI; 2673 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2674 break; 2675 } 2676 2677 if (IS_QLA82XX(ha)) 2678 ha->port_no = ha->portnum & 1; 2679 else { 2680 /* Get adapter physical port no from interrupt pin register. */ 2681 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2682 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2683 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2684 ha->port_no--; 2685 else 2686 ha->port_no = !(ha->port_no & 1); 2687 } 2688 2689 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2690 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2691 ha->device_type, ha->port_no, ha->fw_srisc_address); 2692 } 2693 2694 static void 2695 qla2xxx_scan_start(struct Scsi_Host *shost) 2696 { 2697 scsi_qla_host_t *vha = shost_priv(shost); 2698 2699 if (vha->hw->flags.running_gold_fw) 2700 return; 2701 2702 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2703 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2704 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2705 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2706 } 2707 2708 static int 2709 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2710 { 2711 scsi_qla_host_t *vha = shost_priv(shost); 2712 2713 if (test_bit(UNLOADING, &vha->dpc_flags)) 2714 return 1; 2715 if (!vha->host) 2716 return 1; 2717 if (time > vha->hw->loop_reset_delay * HZ) 2718 return 1; 2719 2720 return atomic_read(&vha->loop_state) == LOOP_READY; 2721 } 2722 2723 static void qla2x00_iocb_work_fn(struct work_struct *work) 2724 { 2725 struct scsi_qla_host *vha = container_of(work, 2726 struct scsi_qla_host, iocb_work); 2727 struct qla_hw_data *ha = vha->hw; 2728 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2729 int i = 2; 2730 unsigned long flags; 2731 2732 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2733 return; 2734 2735 while (!list_empty(&vha->work_list) && i > 0) { 2736 qla2x00_do_work(vha); 2737 i--; 2738 } 2739 2740 spin_lock_irqsave(&vha->work_lock, flags); 2741 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2742 spin_unlock_irqrestore(&vha->work_lock, flags); 2743 } 2744 2745 /* 2746 * PCI driver interface 2747 */ 2748 static int 2749 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2750 { 2751 int ret = -ENODEV; 2752 struct Scsi_Host *host; 2753 scsi_qla_host_t *base_vha = NULL; 2754 struct qla_hw_data *ha; 2755 char pci_info[30]; 2756 char fw_str[30], wq_name[30]; 2757 struct scsi_host_template *sht; 2758 int bars, mem_only = 0; 2759 uint16_t req_length = 0, rsp_length = 0; 2760 struct req_que *req = NULL; 2761 struct rsp_que *rsp = NULL; 2762 int i; 2763 2764 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2765 sht = &qla2xxx_driver_template; 2766 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2767 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2768 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2769 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2770 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2771 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2772 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2773 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2774 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2775 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2776 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2777 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2778 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2779 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2780 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2781 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2782 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2783 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2784 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2785 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2786 mem_only = 1; 2787 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2788 "Mem only adapter.\n"); 2789 } 2790 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2791 "Bars=%d.\n", bars); 2792 2793 if (mem_only) { 2794 if (pci_enable_device_mem(pdev)) 2795 return ret; 2796 } else { 2797 if (pci_enable_device(pdev)) 2798 return ret; 2799 } 2800 2801 /* This may fail but that's ok */ 2802 pci_enable_pcie_error_reporting(pdev); 2803 2804 /* Turn off T10-DIF when FC-NVMe is enabled */ 2805 if (ql2xnvmeenable) 2806 ql2xenabledif = 0; 2807 2808 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2809 if (!ha) { 2810 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2811 "Unable to allocate memory for ha.\n"); 2812 goto disable_device; 2813 } 2814 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2815 "Memory allocated for ha=%p.\n", ha); 2816 ha->pdev = pdev; 2817 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2818 spin_lock_init(&ha->tgt.q_full_lock); 2819 spin_lock_init(&ha->tgt.sess_lock); 2820 spin_lock_init(&ha->tgt.atio_lock); 2821 2822 atomic_set(&ha->nvme_active_aen_cnt, 0); 2823 2824 /* Clear our data area */ 2825 ha->bars = bars; 2826 ha->mem_only = mem_only; 2827 spin_lock_init(&ha->hardware_lock); 2828 spin_lock_init(&ha->vport_slock); 2829 mutex_init(&ha->selflogin_lock); 2830 mutex_init(&ha->optrom_mutex); 2831 2832 /* Set ISP-type information. */ 2833 qla2x00_set_isp_flags(ha); 2834 2835 /* Set EEH reset type to fundamental if required by hba */ 2836 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2837 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2838 pdev->needs_freset = 1; 2839 2840 ha->prev_topology = 0; 2841 ha->init_cb_size = sizeof(init_cb_t); 2842 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2843 ha->optrom_size = OPTROM_SIZE_2300; 2844 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2845 atomic_set(&ha->num_pend_mbx_stage1, 0); 2846 atomic_set(&ha->num_pend_mbx_stage2, 0); 2847 atomic_set(&ha->num_pend_mbx_stage3, 0); 2848 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2849 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2850 2851 /* Assign ISP specific operations. */ 2852 if (IS_QLA2100(ha)) { 2853 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2854 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2855 req_length = REQUEST_ENTRY_CNT_2100; 2856 rsp_length = RESPONSE_ENTRY_CNT_2100; 2857 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2858 ha->gid_list_info_size = 4; 2859 ha->flash_conf_off = ~0; 2860 ha->flash_data_off = ~0; 2861 ha->nvram_conf_off = ~0; 2862 ha->nvram_data_off = ~0; 2863 ha->isp_ops = &qla2100_isp_ops; 2864 } else if (IS_QLA2200(ha)) { 2865 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2866 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2867 req_length = REQUEST_ENTRY_CNT_2200; 2868 rsp_length = RESPONSE_ENTRY_CNT_2100; 2869 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2870 ha->gid_list_info_size = 4; 2871 ha->flash_conf_off = ~0; 2872 ha->flash_data_off = ~0; 2873 ha->nvram_conf_off = ~0; 2874 ha->nvram_data_off = ~0; 2875 ha->isp_ops = &qla2100_isp_ops; 2876 } else if (IS_QLA23XX(ha)) { 2877 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2878 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2879 req_length = REQUEST_ENTRY_CNT_2200; 2880 rsp_length = RESPONSE_ENTRY_CNT_2300; 2881 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2882 ha->gid_list_info_size = 6; 2883 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2884 ha->optrom_size = OPTROM_SIZE_2322; 2885 ha->flash_conf_off = ~0; 2886 ha->flash_data_off = ~0; 2887 ha->nvram_conf_off = ~0; 2888 ha->nvram_data_off = ~0; 2889 ha->isp_ops = &qla2300_isp_ops; 2890 } else if (IS_QLA24XX_TYPE(ha)) { 2891 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2892 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2893 req_length = REQUEST_ENTRY_CNT_24XX; 2894 rsp_length = RESPONSE_ENTRY_CNT_2300; 2895 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2896 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2897 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2898 ha->gid_list_info_size = 8; 2899 ha->optrom_size = OPTROM_SIZE_24XX; 2900 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2901 ha->isp_ops = &qla24xx_isp_ops; 2902 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2903 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2904 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2905 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2906 } else if (IS_QLA25XX(ha)) { 2907 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2908 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2909 req_length = REQUEST_ENTRY_CNT_24XX; 2910 rsp_length = RESPONSE_ENTRY_CNT_2300; 2911 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2912 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2913 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2914 ha->gid_list_info_size = 8; 2915 ha->optrom_size = OPTROM_SIZE_25XX; 2916 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2917 ha->isp_ops = &qla25xx_isp_ops; 2918 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2919 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2920 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2921 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2922 } else if (IS_QLA81XX(ha)) { 2923 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2924 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2925 req_length = REQUEST_ENTRY_CNT_24XX; 2926 rsp_length = RESPONSE_ENTRY_CNT_2300; 2927 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2928 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2929 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2930 ha->gid_list_info_size = 8; 2931 ha->optrom_size = OPTROM_SIZE_81XX; 2932 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2933 ha->isp_ops = &qla81xx_isp_ops; 2934 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2935 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2936 ha->nvram_conf_off = ~0; 2937 ha->nvram_data_off = ~0; 2938 } else if (IS_QLA82XX(ha)) { 2939 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2940 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2941 req_length = REQUEST_ENTRY_CNT_82XX; 2942 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2943 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2944 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2945 ha->gid_list_info_size = 8; 2946 ha->optrom_size = OPTROM_SIZE_82XX; 2947 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2948 ha->isp_ops = &qla82xx_isp_ops; 2949 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2950 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2951 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2952 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2953 } else if (IS_QLA8044(ha)) { 2954 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2955 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2956 req_length = REQUEST_ENTRY_CNT_82XX; 2957 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2958 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2959 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2960 ha->gid_list_info_size = 8; 2961 ha->optrom_size = OPTROM_SIZE_83XX; 2962 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2963 ha->isp_ops = &qla8044_isp_ops; 2964 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2965 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2966 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2967 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2968 } else if (IS_QLA83XX(ha)) { 2969 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2970 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2971 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2972 req_length = REQUEST_ENTRY_CNT_83XX; 2973 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2974 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2975 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2976 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2977 ha->gid_list_info_size = 8; 2978 ha->optrom_size = OPTROM_SIZE_83XX; 2979 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2980 ha->isp_ops = &qla83xx_isp_ops; 2981 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2982 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2983 ha->nvram_conf_off = ~0; 2984 ha->nvram_data_off = ~0; 2985 } else if (IS_QLAFX00(ha)) { 2986 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 2987 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 2988 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 2989 req_length = REQUEST_ENTRY_CNT_FX00; 2990 rsp_length = RESPONSE_ENTRY_CNT_FX00; 2991 ha->isp_ops = &qlafx00_isp_ops; 2992 ha->port_down_retry_count = 30; /* default value */ 2993 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 2994 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 2995 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 2996 ha->mr.fw_hbt_en = 1; 2997 ha->mr.host_info_resend = false; 2998 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 2999 } else if (IS_QLA27XX(ha)) { 3000 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3001 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3002 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3003 req_length = REQUEST_ENTRY_CNT_83XX; 3004 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3005 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3006 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3007 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3008 ha->gid_list_info_size = 8; 3009 ha->optrom_size = OPTROM_SIZE_83XX; 3010 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3011 ha->isp_ops = &qla27xx_isp_ops; 3012 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3013 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3014 ha->nvram_conf_off = ~0; 3015 ha->nvram_data_off = ~0; 3016 } else if (IS_QLA28XX(ha)) { 3017 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3018 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3019 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3020 req_length = REQUEST_ENTRY_CNT_24XX; 3021 rsp_length = RESPONSE_ENTRY_CNT_2300; 3022 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3023 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3024 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3025 ha->gid_list_info_size = 8; 3026 ha->optrom_size = OPTROM_SIZE_28XX; 3027 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3028 ha->isp_ops = &qla27xx_isp_ops; 3029 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3030 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3031 ha->nvram_conf_off = ~0; 3032 ha->nvram_data_off = ~0; 3033 } 3034 3035 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3036 "mbx_count=%d, req_length=%d, " 3037 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3038 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3039 "max_fibre_devices=%d.\n", 3040 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3041 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3042 ha->nvram_npiv_size, ha->max_fibre_devices); 3043 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3044 "isp_ops=%p, flash_conf_off=%d, " 3045 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3046 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3047 ha->nvram_conf_off, ha->nvram_data_off); 3048 3049 /* Configure PCI I/O space */ 3050 ret = ha->isp_ops->iospace_config(ha); 3051 if (ret) 3052 goto iospace_config_failed; 3053 3054 ql_log_pci(ql_log_info, pdev, 0x001d, 3055 "Found an ISP%04X irq %d iobase 0x%p.\n", 3056 pdev->device, pdev->irq, ha->iobase); 3057 mutex_init(&ha->vport_lock); 3058 mutex_init(&ha->mq_lock); 3059 init_completion(&ha->mbx_cmd_comp); 3060 complete(&ha->mbx_cmd_comp); 3061 init_completion(&ha->mbx_intr_comp); 3062 init_completion(&ha->dcbx_comp); 3063 init_completion(&ha->lb_portup_comp); 3064 3065 set_bit(0, (unsigned long *) ha->vp_idx_map); 3066 3067 qla2x00_config_dma_addressing(ha); 3068 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3069 "64 Bit addressing is %s.\n", 3070 ha->flags.enable_64bit_addressing ? "enable" : 3071 "disable"); 3072 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3073 if (ret) { 3074 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3075 "Failed to allocate memory for adapter, aborting.\n"); 3076 3077 goto probe_hw_failed; 3078 } 3079 3080 req->max_q_depth = MAX_Q_DEPTH; 3081 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3082 req->max_q_depth = ql2xmaxqdepth; 3083 3084 3085 base_vha = qla2x00_create_host(sht, ha); 3086 if (!base_vha) { 3087 ret = -ENOMEM; 3088 goto probe_hw_failed; 3089 } 3090 3091 pci_set_drvdata(pdev, base_vha); 3092 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3093 3094 host = base_vha->host; 3095 base_vha->req = req; 3096 if (IS_QLA2XXX_MIDTYPE(ha)) 3097 base_vha->mgmt_svr_loop_id = 3098 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3099 else 3100 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3101 base_vha->vp_idx; 3102 3103 /* Setup fcport template structure. */ 3104 ha->mr.fcport.vha = base_vha; 3105 ha->mr.fcport.port_type = FCT_UNKNOWN; 3106 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3107 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3108 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3109 ha->mr.fcport.scan_state = 1; 3110 3111 /* Set the SG table size based on ISP type */ 3112 if (!IS_FWI2_CAPABLE(ha)) { 3113 if (IS_QLA2100(ha)) 3114 host->sg_tablesize = 32; 3115 } else { 3116 if (!IS_QLA82XX(ha)) 3117 host->sg_tablesize = QLA_SG_ALL; 3118 } 3119 host->max_id = ha->max_fibre_devices; 3120 host->cmd_per_lun = 3; 3121 host->unique_id = host->host_no; 3122 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3123 host->max_cmd_len = 32; 3124 else 3125 host->max_cmd_len = MAX_CMDSZ; 3126 host->max_channel = MAX_BUSES - 1; 3127 /* Older HBAs support only 16-bit LUNs */ 3128 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3129 ql2xmaxlun > 0xffff) 3130 host->max_lun = 0xffff; 3131 else 3132 host->max_lun = ql2xmaxlun; 3133 host->transportt = qla2xxx_transport_template; 3134 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3135 3136 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3137 "max_id=%d this_id=%d " 3138 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3139 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3140 host->this_id, host->cmd_per_lun, host->unique_id, 3141 host->max_cmd_len, host->max_channel, host->max_lun, 3142 host->transportt, sht->vendor_id); 3143 3144 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3145 3146 /* Set up the irqs */ 3147 ret = qla2x00_request_irqs(ha, rsp); 3148 if (ret) 3149 goto probe_failed; 3150 3151 /* Alloc arrays of request and response ring ptrs */ 3152 ret = qla2x00_alloc_queues(ha, req, rsp); 3153 if (ret) { 3154 ql_log(ql_log_fatal, base_vha, 0x003d, 3155 "Failed to allocate memory for queue pointers..." 3156 "aborting.\n"); 3157 goto probe_failed; 3158 } 3159 3160 if (ha->mqenable) { 3161 /* number of hardware queues supported by blk/scsi-mq*/ 3162 host->nr_hw_queues = ha->max_qpairs; 3163 3164 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3165 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3166 } else { 3167 if (ql2xnvmeenable) { 3168 host->nr_hw_queues = ha->max_qpairs; 3169 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3170 "FC-NVMe support is enabled, HW queues=%d\n", 3171 host->nr_hw_queues); 3172 } else { 3173 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3174 "blk/scsi-mq disabled.\n"); 3175 } 3176 } 3177 3178 qlt_probe_one_stage1(base_vha, ha); 3179 3180 pci_save_state(pdev); 3181 3182 /* Assign back pointers */ 3183 rsp->req = req; 3184 req->rsp = rsp; 3185 3186 if (IS_QLAFX00(ha)) { 3187 ha->rsp_q_map[0] = rsp; 3188 ha->req_q_map[0] = req; 3189 set_bit(0, ha->req_qid_map); 3190 set_bit(0, ha->rsp_qid_map); 3191 } 3192 3193 /* FWI2-capable only. */ 3194 req->req_q_in = &ha->iobase->isp24.req_q_in; 3195 req->req_q_out = &ha->iobase->isp24.req_q_out; 3196 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3197 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3198 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3199 IS_QLA28XX(ha)) { 3200 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3201 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3202 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3203 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3204 } 3205 3206 if (IS_QLAFX00(ha)) { 3207 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3208 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3209 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3210 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3211 } 3212 3213 if (IS_P3P_TYPE(ha)) { 3214 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3215 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3216 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3217 } 3218 3219 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3220 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3221 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3222 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3223 "req->req_q_in=%p req->req_q_out=%p " 3224 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3225 req->req_q_in, req->req_q_out, 3226 rsp->rsp_q_in, rsp->rsp_q_out); 3227 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3228 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3229 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3230 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3231 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3232 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3233 3234 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0); 3235 3236 if (ha->isp_ops->initialize_adapter(base_vha)) { 3237 ql_log(ql_log_fatal, base_vha, 0x00d6, 3238 "Failed to initialize adapter - Adapter flags %x.\n", 3239 base_vha->device_flags); 3240 3241 if (IS_QLA82XX(ha)) { 3242 qla82xx_idc_lock(ha); 3243 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3244 QLA8XXX_DEV_FAILED); 3245 qla82xx_idc_unlock(ha); 3246 ql_log(ql_log_fatal, base_vha, 0x00d7, 3247 "HW State: FAILED.\n"); 3248 } else if (IS_QLA8044(ha)) { 3249 qla8044_idc_lock(ha); 3250 qla8044_wr_direct(base_vha, 3251 QLA8044_CRB_DEV_STATE_INDEX, 3252 QLA8XXX_DEV_FAILED); 3253 qla8044_idc_unlock(ha); 3254 ql_log(ql_log_fatal, base_vha, 0x0150, 3255 "HW State: FAILED.\n"); 3256 } 3257 3258 ret = -ENODEV; 3259 goto probe_failed; 3260 } 3261 3262 if (IS_QLAFX00(ha)) 3263 host->can_queue = QLAFX00_MAX_CANQUEUE; 3264 else 3265 host->can_queue = req->num_outstanding_cmds - 10; 3266 3267 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3268 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3269 host->can_queue, base_vha->req, 3270 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3271 3272 if (ha->mqenable) { 3273 bool startit = false; 3274 3275 if (QLA_TGT_MODE_ENABLED()) 3276 startit = false; 3277 3278 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3279 startit = true; 3280 3281 /* Create start of day qpairs for Block MQ */ 3282 for (i = 0; i < ha->max_qpairs; i++) 3283 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3284 } 3285 3286 if (ha->flags.running_gold_fw) 3287 goto skip_dpc; 3288 3289 /* 3290 * Startup the kernel thread for this host adapter 3291 */ 3292 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3293 "%s_dpc", base_vha->host_str); 3294 if (IS_ERR(ha->dpc_thread)) { 3295 ql_log(ql_log_fatal, base_vha, 0x00ed, 3296 "Failed to start DPC thread.\n"); 3297 ret = PTR_ERR(ha->dpc_thread); 3298 ha->dpc_thread = NULL; 3299 goto probe_failed; 3300 } 3301 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3302 "DPC thread started successfully.\n"); 3303 3304 /* 3305 * If we're not coming up in initiator mode, we might sit for 3306 * a while without waking up the dpc thread, which leads to a 3307 * stuck process warning. So just kick the dpc once here and 3308 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3309 */ 3310 qla2xxx_wake_dpc(base_vha); 3311 3312 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3313 3314 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3315 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3316 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3317 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3318 3319 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3320 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3321 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3322 INIT_WORK(&ha->idc_state_handler, 3323 qla83xx_idc_state_handler_work); 3324 INIT_WORK(&ha->nic_core_unrecoverable, 3325 qla83xx_nic_core_unrecoverable_work); 3326 } 3327 3328 skip_dpc: 3329 list_add_tail(&base_vha->list, &ha->vp_list); 3330 base_vha->host->irq = ha->pdev->irq; 3331 3332 /* Initialized the timer */ 3333 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3334 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3335 "Started qla2x00_timer with " 3336 "interval=%d.\n", WATCH_INTERVAL); 3337 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3338 "Detected hba at address=%p.\n", 3339 ha); 3340 3341 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3342 if (ha->fw_attributes & BIT_4) { 3343 int prot = 0, guard; 3344 3345 base_vha->flags.difdix_supported = 1; 3346 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3347 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3348 if (ql2xenabledif == 1) 3349 prot = SHOST_DIX_TYPE0_PROTECTION; 3350 if (ql2xprotmask) 3351 scsi_host_set_prot(host, ql2xprotmask); 3352 else 3353 scsi_host_set_prot(host, 3354 prot | SHOST_DIF_TYPE1_PROTECTION 3355 | SHOST_DIF_TYPE2_PROTECTION 3356 | SHOST_DIF_TYPE3_PROTECTION 3357 | SHOST_DIX_TYPE1_PROTECTION 3358 | SHOST_DIX_TYPE2_PROTECTION 3359 | SHOST_DIX_TYPE3_PROTECTION); 3360 3361 guard = SHOST_DIX_GUARD_CRC; 3362 3363 if (IS_PI_IPGUARD_CAPABLE(ha) && 3364 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3365 guard |= SHOST_DIX_GUARD_IP; 3366 3367 if (ql2xprotguard) 3368 scsi_host_set_guard(host, ql2xprotguard); 3369 else 3370 scsi_host_set_guard(host, guard); 3371 } else 3372 base_vha->flags.difdix_supported = 0; 3373 } 3374 3375 ha->isp_ops->enable_intrs(ha); 3376 3377 if (IS_QLAFX00(ha)) { 3378 ret = qlafx00_fx_disc(base_vha, 3379 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3380 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3381 QLA_SG_ALL : 128; 3382 } 3383 3384 ret = scsi_add_host(host, &pdev->dev); 3385 if (ret) 3386 goto probe_failed; 3387 3388 base_vha->flags.init_done = 1; 3389 base_vha->flags.online = 1; 3390 ha->prev_minidump_failed = 0; 3391 3392 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3393 "Init done and hba is online.\n"); 3394 3395 if (qla_ini_mode_enabled(base_vha) || 3396 qla_dual_mode_enabled(base_vha)) 3397 scsi_scan_host(host); 3398 else 3399 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3400 "skipping scsi_scan_host() for non-initiator port\n"); 3401 3402 qla2x00_alloc_sysfs_attr(base_vha); 3403 3404 if (IS_QLAFX00(ha)) { 3405 ret = qlafx00_fx_disc(base_vha, 3406 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3407 3408 /* Register system information */ 3409 ret = qlafx00_fx_disc(base_vha, 3410 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3411 } 3412 3413 qla2x00_init_host_attr(base_vha); 3414 3415 qla2x00_dfs_setup(base_vha); 3416 3417 ql_log(ql_log_info, base_vha, 0x00fb, 3418 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3419 ql_log(ql_log_info, base_vha, 0x00fc, 3420 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3421 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), 3422 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3423 base_vha->host_no, 3424 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3425 3426 qlt_add_target(ha, base_vha); 3427 3428 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3429 3430 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3431 return -ENODEV; 3432 3433 if (ha->flags.detected_lr_sfp) { 3434 ql_log(ql_log_info, base_vha, 0xffff, 3435 "Reset chip to pick up LR SFP setting\n"); 3436 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 3437 qla2xxx_wake_dpc(base_vha); 3438 } 3439 3440 return 0; 3441 3442 probe_failed: 3443 if (base_vha->timer_active) 3444 qla2x00_stop_timer(base_vha); 3445 base_vha->flags.online = 0; 3446 if (ha->dpc_thread) { 3447 struct task_struct *t = ha->dpc_thread; 3448 3449 ha->dpc_thread = NULL; 3450 kthread_stop(t); 3451 } 3452 3453 qla2x00_free_device(base_vha); 3454 scsi_host_put(base_vha->host); 3455 /* 3456 * Need to NULL out local req/rsp after 3457 * qla2x00_free_device => qla2x00_free_queues frees 3458 * what these are pointing to. Or else we'll 3459 * fall over below in qla2x00_free_req/rsp_que. 3460 */ 3461 req = NULL; 3462 rsp = NULL; 3463 3464 probe_hw_failed: 3465 qla2x00_mem_free(ha); 3466 qla2x00_free_req_que(ha, req); 3467 qla2x00_free_rsp_que(ha, rsp); 3468 qla2x00_clear_drv_active(ha); 3469 3470 iospace_config_failed: 3471 if (IS_P3P_TYPE(ha)) { 3472 if (!ha->nx_pcibase) 3473 iounmap((device_reg_t *)ha->nx_pcibase); 3474 if (!ql2xdbwr) 3475 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3476 } else { 3477 if (ha->iobase) 3478 iounmap(ha->iobase); 3479 if (ha->cregbase) 3480 iounmap(ha->cregbase); 3481 } 3482 pci_release_selected_regions(ha->pdev, ha->bars); 3483 kfree(ha); 3484 3485 disable_device: 3486 pci_disable_device(pdev); 3487 return ret; 3488 } 3489 3490 static void 3491 qla2x00_shutdown(struct pci_dev *pdev) 3492 { 3493 scsi_qla_host_t *vha; 3494 struct qla_hw_data *ha; 3495 3496 vha = pci_get_drvdata(pdev); 3497 ha = vha->hw; 3498 3499 ql_log(ql_log_info, vha, 0xfffa, 3500 "Adapter shutdown\n"); 3501 3502 /* 3503 * Prevent future board_disable and wait 3504 * until any pending board_disable has completed. 3505 */ 3506 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags); 3507 cancel_work_sync(&ha->board_disable); 3508 3509 if (!atomic_read(&pdev->enable_cnt)) 3510 return; 3511 3512 /* Notify ISPFX00 firmware */ 3513 if (IS_QLAFX00(ha)) 3514 qlafx00_driver_shutdown(vha, 20); 3515 3516 /* Turn-off FCE trace */ 3517 if (ha->flags.fce_enabled) { 3518 qla2x00_disable_fce_trace(vha, NULL, NULL); 3519 ha->flags.fce_enabled = 0; 3520 } 3521 3522 /* Turn-off EFT trace */ 3523 if (ha->eft) 3524 qla2x00_disable_eft_trace(vha); 3525 3526 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3527 IS_QLA28XX(ha)) { 3528 if (ha->flags.fw_started) 3529 qla2x00_abort_isp_cleanup(vha); 3530 } else { 3531 /* Stop currently executing firmware. */ 3532 qla2x00_try_to_stop_firmware(vha); 3533 } 3534 3535 /* Turn adapter off line */ 3536 vha->flags.online = 0; 3537 3538 /* turn-off interrupts on the card */ 3539 if (ha->interrupts_on) { 3540 vha->flags.init_done = 0; 3541 ha->isp_ops->disable_intrs(ha); 3542 } 3543 3544 qla2x00_free_irqs(vha); 3545 3546 qla2x00_free_fw_dump(ha); 3547 3548 pci_disable_device(pdev); 3549 ql_log(ql_log_info, vha, 0xfffe, 3550 "Adapter shutdown successfully.\n"); 3551 } 3552 3553 /* Deletes all the virtual ports for a given ha */ 3554 static void 3555 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3556 { 3557 scsi_qla_host_t *vha; 3558 unsigned long flags; 3559 3560 mutex_lock(&ha->vport_lock); 3561 while (ha->cur_vport_count) { 3562 spin_lock_irqsave(&ha->vport_slock, flags); 3563 3564 BUG_ON(base_vha->list.next == &ha->vp_list); 3565 /* This assumes first entry in ha->vp_list is always base vha */ 3566 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3567 scsi_host_get(vha->host); 3568 3569 spin_unlock_irqrestore(&ha->vport_slock, flags); 3570 mutex_unlock(&ha->vport_lock); 3571 3572 qla_nvme_delete(vha); 3573 3574 fc_vport_terminate(vha->fc_vport); 3575 scsi_host_put(vha->host); 3576 3577 mutex_lock(&ha->vport_lock); 3578 } 3579 mutex_unlock(&ha->vport_lock); 3580 } 3581 3582 /* Stops all deferred work threads */ 3583 static void 3584 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3585 { 3586 /* Cancel all work and destroy DPC workqueues */ 3587 if (ha->dpc_lp_wq) { 3588 cancel_work_sync(&ha->idc_aen); 3589 destroy_workqueue(ha->dpc_lp_wq); 3590 ha->dpc_lp_wq = NULL; 3591 } 3592 3593 if (ha->dpc_hp_wq) { 3594 cancel_work_sync(&ha->nic_core_reset); 3595 cancel_work_sync(&ha->idc_state_handler); 3596 cancel_work_sync(&ha->nic_core_unrecoverable); 3597 destroy_workqueue(ha->dpc_hp_wq); 3598 ha->dpc_hp_wq = NULL; 3599 } 3600 3601 /* Kill the kernel thread for this host */ 3602 if (ha->dpc_thread) { 3603 struct task_struct *t = ha->dpc_thread; 3604 3605 /* 3606 * qla2xxx_wake_dpc checks for ->dpc_thread 3607 * so we need to zero it out. 3608 */ 3609 ha->dpc_thread = NULL; 3610 kthread_stop(t); 3611 } 3612 } 3613 3614 static void 3615 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3616 { 3617 if (IS_QLA82XX(ha)) { 3618 3619 iounmap((device_reg_t *)ha->nx_pcibase); 3620 if (!ql2xdbwr) 3621 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3622 } else { 3623 if (ha->iobase) 3624 iounmap(ha->iobase); 3625 3626 if (ha->cregbase) 3627 iounmap(ha->cregbase); 3628 3629 if (ha->mqiobase) 3630 iounmap(ha->mqiobase); 3631 3632 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3633 ha->msixbase) 3634 iounmap(ha->msixbase); 3635 } 3636 } 3637 3638 static void 3639 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3640 { 3641 if (IS_QLA8044(ha)) { 3642 qla8044_idc_lock(ha); 3643 qla8044_clear_drv_active(ha); 3644 qla8044_idc_unlock(ha); 3645 } else if (IS_QLA82XX(ha)) { 3646 qla82xx_idc_lock(ha); 3647 qla82xx_clear_drv_active(ha); 3648 qla82xx_idc_unlock(ha); 3649 } 3650 } 3651 3652 static void 3653 qla2x00_remove_one(struct pci_dev *pdev) 3654 { 3655 scsi_qla_host_t *base_vha; 3656 struct qla_hw_data *ha; 3657 3658 base_vha = pci_get_drvdata(pdev); 3659 ha = base_vha->hw; 3660 ql_log(ql_log_info, base_vha, 0xb079, 3661 "Removing driver\n"); 3662 3663 /* Indicate device removal to prevent future board_disable and wait 3664 * until any pending board_disable has completed. */ 3665 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3666 cancel_work_sync(&ha->board_disable); 3667 3668 /* 3669 * If the PCI device is disabled then there was a PCI-disconnect and 3670 * qla2x00_disable_board_on_pci_error has taken care of most of the 3671 * resources. 3672 */ 3673 if (!atomic_read(&pdev->enable_cnt)) { 3674 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3675 base_vha->gnl.l, base_vha->gnl.ldma); 3676 3677 scsi_host_put(base_vha->host); 3678 kfree(ha); 3679 pci_set_drvdata(pdev, NULL); 3680 return; 3681 } 3682 qla2x00_wait_for_hba_ready(base_vha); 3683 3684 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3685 IS_QLA28XX(ha)) { 3686 if (ha->flags.fw_started) 3687 qla2x00_abort_isp_cleanup(base_vha); 3688 } else if (!IS_QLAFX00(ha)) { 3689 if (IS_QLA8031(ha)) { 3690 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3691 "Clearing fcoe driver presence.\n"); 3692 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3693 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3694 "Error while clearing DRV-Presence.\n"); 3695 } 3696 3697 qla2x00_try_to_stop_firmware(base_vha); 3698 } 3699 3700 qla2x00_wait_for_sess_deletion(base_vha); 3701 3702 /* 3703 * if UNLOAD flag is already set, then continue unload, 3704 * where it was set first. 3705 */ 3706 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3707 return; 3708 3709 set_bit(UNLOADING, &base_vha->dpc_flags); 3710 3711 qla_nvme_delete(base_vha); 3712 3713 dma_free_coherent(&ha->pdev->dev, 3714 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3715 3716 vfree(base_vha->scan.l); 3717 3718 if (IS_QLAFX00(ha)) 3719 qlafx00_driver_shutdown(base_vha, 20); 3720 3721 qla2x00_delete_all_vps(ha, base_vha); 3722 3723 qla2x00_dfs_remove(base_vha); 3724 3725 qla84xx_put_chip(base_vha); 3726 3727 /* Disable timer */ 3728 if (base_vha->timer_active) 3729 qla2x00_stop_timer(base_vha); 3730 3731 base_vha->flags.online = 0; 3732 3733 /* free DMA memory */ 3734 if (ha->exlogin_buf) 3735 qla2x00_free_exlogin_buffer(ha); 3736 3737 /* free DMA memory */ 3738 if (ha->exchoffld_buf) 3739 qla2x00_free_exchoffld_buffer(ha); 3740 3741 qla2x00_destroy_deferred_work(ha); 3742 3743 qlt_remove_target(ha, base_vha); 3744 3745 qla2x00_free_sysfs_attr(base_vha, true); 3746 3747 fc_remove_host(base_vha->host); 3748 qlt_remove_target_resources(ha); 3749 3750 scsi_remove_host(base_vha->host); 3751 3752 qla2x00_free_device(base_vha); 3753 3754 qla2x00_clear_drv_active(ha); 3755 3756 scsi_host_put(base_vha->host); 3757 3758 qla2x00_unmap_iobases(ha); 3759 3760 pci_release_selected_regions(ha->pdev, ha->bars); 3761 kfree(ha); 3762 3763 pci_disable_pcie_error_reporting(pdev); 3764 3765 pci_disable_device(pdev); 3766 } 3767 3768 static void 3769 qla2x00_free_device(scsi_qla_host_t *vha) 3770 { 3771 struct qla_hw_data *ha = vha->hw; 3772 3773 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3774 3775 /* Disable timer */ 3776 if (vha->timer_active) 3777 qla2x00_stop_timer(vha); 3778 3779 qla25xx_delete_queues(vha); 3780 vha->flags.online = 0; 3781 3782 /* turn-off interrupts on the card */ 3783 if (ha->interrupts_on) { 3784 vha->flags.init_done = 0; 3785 ha->isp_ops->disable_intrs(ha); 3786 } 3787 3788 qla2x00_free_fcports(vha); 3789 3790 qla2x00_free_irqs(vha); 3791 3792 /* Flush the work queue and remove it */ 3793 if (ha->wq) { 3794 flush_workqueue(ha->wq); 3795 destroy_workqueue(ha->wq); 3796 ha->wq = NULL; 3797 } 3798 3799 3800 qla2x00_mem_free(ha); 3801 3802 qla82xx_md_free(vha); 3803 3804 qla2x00_free_queues(ha); 3805 } 3806 3807 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3808 { 3809 fc_port_t *fcport, *tfcport; 3810 3811 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3812 qla2x00_free_fcport(fcport); 3813 } 3814 3815 static inline void 3816 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, 3817 int defer) 3818 { 3819 struct fc_rport *rport; 3820 scsi_qla_host_t *base_vha; 3821 unsigned long flags; 3822 3823 if (!fcport->rport) 3824 return; 3825 3826 rport = fcport->rport; 3827 if (defer) { 3828 base_vha = pci_get_drvdata(vha->hw->pdev); 3829 spin_lock_irqsave(vha->host->host_lock, flags); 3830 fcport->drport = rport; 3831 spin_unlock_irqrestore(vha->host->host_lock, flags); 3832 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); 3833 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); 3834 qla2xxx_wake_dpc(base_vha); 3835 } else { 3836 int now; 3837 3838 if (rport) { 3839 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3840 "%s %8phN. rport %p roles %x\n", 3841 __func__, fcport->port_name, rport, 3842 rport->roles); 3843 fc_remote_port_delete(rport); 3844 } 3845 qlt_do_generation_tick(vha, &now); 3846 } 3847 } 3848 3849 /* 3850 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3851 * 3852 * Input: ha = adapter block pointer. fcport = port structure pointer. 3853 * 3854 * Return: None. 3855 * 3856 * Context: 3857 */ 3858 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3859 int do_login, int defer) 3860 { 3861 if (IS_QLAFX00(vha->hw)) { 3862 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3863 qla2x00_schedule_rport_del(vha, fcport, defer); 3864 return; 3865 } 3866 3867 if (atomic_read(&fcport->state) == FCS_ONLINE && 3868 vha->vp_idx == fcport->vha->vp_idx) { 3869 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3870 qla2x00_schedule_rport_del(vha, fcport, defer); 3871 } 3872 /* 3873 * We may need to retry the login, so don't change the state of the 3874 * port but do the retries. 3875 */ 3876 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3877 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3878 3879 if (!do_login) 3880 return; 3881 3882 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3883 } 3884 3885 /* 3886 * qla2x00_mark_all_devices_lost 3887 * Updates fcport state when device goes offline. 3888 * 3889 * Input: 3890 * ha = adapter block pointer. 3891 * fcport = port structure pointer. 3892 * 3893 * Return: 3894 * None. 3895 * 3896 * Context: 3897 */ 3898 void 3899 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) 3900 { 3901 fc_port_t *fcport; 3902 3903 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3904 "Mark all dev lost\n"); 3905 3906 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3907 fcport->scan_state = 0; 3908 qlt_schedule_sess_for_deletion(fcport); 3909 3910 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) 3911 continue; 3912 3913 /* 3914 * No point in marking the device as lost, if the device is 3915 * already DEAD. 3916 */ 3917 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) 3918 continue; 3919 if (atomic_read(&fcport->state) == FCS_ONLINE) { 3920 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3921 if (defer) 3922 qla2x00_schedule_rport_del(vha, fcport, defer); 3923 else if (vha->vp_idx == fcport->vha->vp_idx) 3924 qla2x00_schedule_rport_del(vha, fcport, defer); 3925 } 3926 } 3927 } 3928 3929 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 3930 { 3931 int i; 3932 3933 if (IS_FWI2_CAPABLE(ha)) 3934 return; 3935 3936 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 3937 set_bit(i, ha->loop_id_map); 3938 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 3939 set_bit(BROADCAST, ha->loop_id_map); 3940 } 3941 3942 /* 3943 * qla2x00_mem_alloc 3944 * Allocates adapter memory. 3945 * 3946 * Returns: 3947 * 0 = success. 3948 * !0 = failure. 3949 */ 3950 static int 3951 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3952 struct req_que **req, struct rsp_que **rsp) 3953 { 3954 char name[16]; 3955 3956 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3957 &ha->init_cb_dma, GFP_KERNEL); 3958 if (!ha->init_cb) 3959 goto fail; 3960 3961 if (qlt_mem_alloc(ha) < 0) 3962 goto fail_free_init_cb; 3963 3964 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3965 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3966 if (!ha->gid_list) 3967 goto fail_free_tgt_mem; 3968 3969 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3970 if (!ha->srb_mempool) 3971 goto fail_free_gid_list; 3972 3973 if (IS_P3P_TYPE(ha)) { 3974 /* Allocate cache for CT6 Ctx. */ 3975 if (!ctx_cachep) { 3976 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3977 sizeof(struct ct6_dsd), 0, 3978 SLAB_HWCACHE_ALIGN, NULL); 3979 if (!ctx_cachep) 3980 goto fail_free_srb_mempool; 3981 } 3982 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 3983 ctx_cachep); 3984 if (!ha->ctx_mempool) 3985 goto fail_free_srb_mempool; 3986 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 3987 "ctx_cachep=%p ctx_mempool=%p.\n", 3988 ctx_cachep, ha->ctx_mempool); 3989 } 3990 3991 /* Get memory for cached NVRAM */ 3992 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 3993 if (!ha->nvram) 3994 goto fail_free_ctx_mempool; 3995 3996 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 3997 ha->pdev->device); 3998 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 3999 DMA_POOL_SIZE, 8, 0); 4000 if (!ha->s_dma_pool) 4001 goto fail_free_nvram; 4002 4003 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4004 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4005 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4006 4007 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 4008 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4009 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4010 if (!ha->dl_dma_pool) { 4011 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4012 "Failed to allocate memory for dl_dma_pool.\n"); 4013 goto fail_s_dma_pool; 4014 } 4015 4016 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4017 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4018 if (!ha->fcp_cmnd_dma_pool) { 4019 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4020 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4021 goto fail_dl_dma_pool; 4022 } 4023 4024 if (ql2xenabledif) { 4025 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4026 struct dsd_dma *dsd, *nxt; 4027 uint i; 4028 /* Creata a DMA pool of buffers for DIF bundling */ 4029 ha->dif_bundl_pool = dma_pool_create(name, 4030 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4031 if (!ha->dif_bundl_pool) { 4032 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4033 "%s: failed create dif_bundl_pool\n", 4034 __func__); 4035 goto fail_dif_bundl_dma_pool; 4036 } 4037 4038 INIT_LIST_HEAD(&ha->pool.good.head); 4039 INIT_LIST_HEAD(&ha->pool.unusable.head); 4040 ha->pool.good.count = 0; 4041 ha->pool.unusable.count = 0; 4042 for (i = 0; i < 128; i++) { 4043 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4044 if (!dsd) { 4045 ql_dbg_pci(ql_dbg_init, ha->pdev, 4046 0xe0ee, "%s: failed alloc dsd\n", 4047 __func__); 4048 return 1; 4049 } 4050 ha->dif_bundle_kallocs++; 4051 4052 dsd->dsd_addr = dma_pool_alloc( 4053 ha->dif_bundl_pool, GFP_ATOMIC, 4054 &dsd->dsd_list_dma); 4055 if (!dsd->dsd_addr) { 4056 ql_dbg_pci(ql_dbg_init, ha->pdev, 4057 0xe0ee, 4058 "%s: failed alloc ->dsd_addr\n", 4059 __func__); 4060 kfree(dsd); 4061 ha->dif_bundle_kallocs--; 4062 continue; 4063 } 4064 ha->dif_bundle_dma_allocs++; 4065 4066 /* 4067 * if DMA buffer crosses 4G boundary, 4068 * put it on bad list 4069 */ 4070 if (MSD(dsd->dsd_list_dma) ^ 4071 MSD(dsd->dsd_list_dma + bufsize)) { 4072 list_add_tail(&dsd->list, 4073 &ha->pool.unusable.head); 4074 ha->pool.unusable.count++; 4075 } else { 4076 list_add_tail(&dsd->list, 4077 &ha->pool.good.head); 4078 ha->pool.good.count++; 4079 } 4080 } 4081 4082 /* return the good ones back to the pool */ 4083 list_for_each_entry_safe(dsd, nxt, 4084 &ha->pool.good.head, list) { 4085 list_del(&dsd->list); 4086 dma_pool_free(ha->dif_bundl_pool, 4087 dsd->dsd_addr, dsd->dsd_list_dma); 4088 ha->dif_bundle_dma_allocs--; 4089 kfree(dsd); 4090 ha->dif_bundle_kallocs--; 4091 } 4092 4093 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4094 "%s: dif dma pool (good=%u unusable=%u)\n", 4095 __func__, ha->pool.good.count, 4096 ha->pool.unusable.count); 4097 } 4098 4099 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4100 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4101 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4102 ha->dif_bundl_pool); 4103 } 4104 4105 /* Allocate memory for SNS commands */ 4106 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4107 /* Get consistent memory allocated for SNS commands */ 4108 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4109 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4110 if (!ha->sns_cmd) 4111 goto fail_dma_pool; 4112 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4113 "sns_cmd: %p.\n", ha->sns_cmd); 4114 } else { 4115 /* Get consistent memory allocated for MS IOCB */ 4116 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4117 &ha->ms_iocb_dma); 4118 if (!ha->ms_iocb) 4119 goto fail_dma_pool; 4120 /* Get consistent memory allocated for CT SNS commands */ 4121 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4122 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4123 if (!ha->ct_sns) 4124 goto fail_free_ms_iocb; 4125 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4126 "ms_iocb=%p ct_sns=%p.\n", 4127 ha->ms_iocb, ha->ct_sns); 4128 } 4129 4130 /* Allocate memory for request ring */ 4131 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4132 if (!*req) { 4133 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4134 "Failed to allocate memory for req.\n"); 4135 goto fail_req; 4136 } 4137 (*req)->length = req_len; 4138 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4139 ((*req)->length + 1) * sizeof(request_t), 4140 &(*req)->dma, GFP_KERNEL); 4141 if (!(*req)->ring) { 4142 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4143 "Failed to allocate memory for req_ring.\n"); 4144 goto fail_req_ring; 4145 } 4146 /* Allocate memory for response ring */ 4147 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4148 if (!*rsp) { 4149 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4150 "Failed to allocate memory for rsp.\n"); 4151 goto fail_rsp; 4152 } 4153 (*rsp)->hw = ha; 4154 (*rsp)->length = rsp_len; 4155 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4156 ((*rsp)->length + 1) * sizeof(response_t), 4157 &(*rsp)->dma, GFP_KERNEL); 4158 if (!(*rsp)->ring) { 4159 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4160 "Failed to allocate memory for rsp_ring.\n"); 4161 goto fail_rsp_ring; 4162 } 4163 (*req)->rsp = *rsp; 4164 (*rsp)->req = *req; 4165 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4166 "req=%p req->length=%d req->ring=%p rsp=%p " 4167 "rsp->length=%d rsp->ring=%p.\n", 4168 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4169 (*rsp)->ring); 4170 /* Allocate memory for NVRAM data for vports */ 4171 if (ha->nvram_npiv_size) { 4172 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4173 sizeof(struct qla_npiv_entry), 4174 GFP_KERNEL); 4175 if (!ha->npiv_info) { 4176 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4177 "Failed to allocate memory for npiv_info.\n"); 4178 goto fail_npiv_info; 4179 } 4180 } else 4181 ha->npiv_info = NULL; 4182 4183 /* Get consistent memory allocated for EX-INIT-CB. */ 4184 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4185 IS_QLA28XX(ha)) { 4186 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4187 &ha->ex_init_cb_dma); 4188 if (!ha->ex_init_cb) 4189 goto fail_ex_init_cb; 4190 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4191 "ex_init_cb=%p.\n", ha->ex_init_cb); 4192 } 4193 4194 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4195 4196 /* Get consistent memory allocated for Async Port-Database. */ 4197 if (!IS_FWI2_CAPABLE(ha)) { 4198 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4199 &ha->async_pd_dma); 4200 if (!ha->async_pd) 4201 goto fail_async_pd; 4202 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4203 "async_pd=%p.\n", ha->async_pd); 4204 } 4205 4206 INIT_LIST_HEAD(&ha->vp_list); 4207 4208 /* Allocate memory for our loop_id bitmap */ 4209 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4210 sizeof(long), 4211 GFP_KERNEL); 4212 if (!ha->loop_id_map) 4213 goto fail_loop_id_map; 4214 else { 4215 qla2x00_set_reserved_loop_ids(ha); 4216 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4217 "loop_id_map=%p.\n", ha->loop_id_map); 4218 } 4219 4220 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4221 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4222 if (!ha->sfp_data) { 4223 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4224 "Unable to allocate memory for SFP read-data.\n"); 4225 goto fail_sfp_data; 4226 } 4227 4228 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4229 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4230 GFP_KERNEL); 4231 if (!ha->flt) { 4232 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4233 "Unable to allocate memory for FLT.\n"); 4234 goto fail_flt_buffer; 4235 } 4236 4237 return 0; 4238 4239 fail_flt_buffer: 4240 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4241 ha->sfp_data, ha->sfp_data_dma); 4242 fail_sfp_data: 4243 kfree(ha->loop_id_map); 4244 fail_loop_id_map: 4245 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4246 fail_async_pd: 4247 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4248 fail_ex_init_cb: 4249 kfree(ha->npiv_info); 4250 fail_npiv_info: 4251 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4252 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4253 (*rsp)->ring = NULL; 4254 (*rsp)->dma = 0; 4255 fail_rsp_ring: 4256 kfree(*rsp); 4257 *rsp = NULL; 4258 fail_rsp: 4259 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4260 sizeof(request_t), (*req)->ring, (*req)->dma); 4261 (*req)->ring = NULL; 4262 (*req)->dma = 0; 4263 fail_req_ring: 4264 kfree(*req); 4265 *req = NULL; 4266 fail_req: 4267 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4268 ha->ct_sns, ha->ct_sns_dma); 4269 ha->ct_sns = NULL; 4270 ha->ct_sns_dma = 0; 4271 fail_free_ms_iocb: 4272 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4273 ha->ms_iocb = NULL; 4274 ha->ms_iocb_dma = 0; 4275 4276 if (ha->sns_cmd) 4277 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4278 ha->sns_cmd, ha->sns_cmd_dma); 4279 fail_dma_pool: 4280 if (ql2xenabledif) { 4281 struct dsd_dma *dsd, *nxt; 4282 4283 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4284 list) { 4285 list_del(&dsd->list); 4286 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4287 dsd->dsd_list_dma); 4288 ha->dif_bundle_dma_allocs--; 4289 kfree(dsd); 4290 ha->dif_bundle_kallocs--; 4291 ha->pool.unusable.count--; 4292 } 4293 dma_pool_destroy(ha->dif_bundl_pool); 4294 ha->dif_bundl_pool = NULL; 4295 } 4296 4297 fail_dif_bundl_dma_pool: 4298 if (IS_QLA82XX(ha) || ql2xenabledif) { 4299 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4300 ha->fcp_cmnd_dma_pool = NULL; 4301 } 4302 fail_dl_dma_pool: 4303 if (IS_QLA82XX(ha) || ql2xenabledif) { 4304 dma_pool_destroy(ha->dl_dma_pool); 4305 ha->dl_dma_pool = NULL; 4306 } 4307 fail_s_dma_pool: 4308 dma_pool_destroy(ha->s_dma_pool); 4309 ha->s_dma_pool = NULL; 4310 fail_free_nvram: 4311 kfree(ha->nvram); 4312 ha->nvram = NULL; 4313 fail_free_ctx_mempool: 4314 mempool_destroy(ha->ctx_mempool); 4315 ha->ctx_mempool = NULL; 4316 fail_free_srb_mempool: 4317 mempool_destroy(ha->srb_mempool); 4318 ha->srb_mempool = NULL; 4319 fail_free_gid_list: 4320 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4321 ha->gid_list, 4322 ha->gid_list_dma); 4323 ha->gid_list = NULL; 4324 ha->gid_list_dma = 0; 4325 fail_free_tgt_mem: 4326 qlt_mem_free(ha); 4327 fail_free_init_cb: 4328 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4329 ha->init_cb_dma); 4330 ha->init_cb = NULL; 4331 ha->init_cb_dma = 0; 4332 fail: 4333 ql_log(ql_log_fatal, NULL, 0x0030, 4334 "Memory allocation failure.\n"); 4335 return -ENOMEM; 4336 } 4337 4338 int 4339 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4340 { 4341 int rval; 4342 uint16_t size, max_cnt, temp; 4343 struct qla_hw_data *ha = vha->hw; 4344 4345 /* Return if we don't need to alloacate any extended logins */ 4346 if (!ql2xexlogins) 4347 return QLA_SUCCESS; 4348 4349 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4350 return QLA_SUCCESS; 4351 4352 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4353 max_cnt = 0; 4354 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4355 if (rval != QLA_SUCCESS) { 4356 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4357 "Failed to get exlogin status.\n"); 4358 return rval; 4359 } 4360 4361 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4362 temp *= size; 4363 4364 if (temp != ha->exlogin_size) { 4365 qla2x00_free_exlogin_buffer(ha); 4366 ha->exlogin_size = temp; 4367 4368 ql_log(ql_log_info, vha, 0xd024, 4369 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4370 max_cnt, size, temp); 4371 4372 ql_log(ql_log_info, vha, 0xd025, 4373 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4374 4375 /* Get consistent memory for extended logins */ 4376 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4377 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4378 if (!ha->exlogin_buf) { 4379 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4380 "Failed to allocate memory for exlogin_buf_dma.\n"); 4381 return -ENOMEM; 4382 } 4383 } 4384 4385 /* Now configure the dma buffer */ 4386 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4387 if (rval) { 4388 ql_log(ql_log_fatal, vha, 0xd033, 4389 "Setup extended login buffer ****FAILED****.\n"); 4390 qla2x00_free_exlogin_buffer(ha); 4391 } 4392 4393 return rval; 4394 } 4395 4396 /* 4397 * qla2x00_free_exlogin_buffer 4398 * 4399 * Input: 4400 * ha = adapter block pointer 4401 */ 4402 void 4403 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4404 { 4405 if (ha->exlogin_buf) { 4406 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4407 ha->exlogin_buf, ha->exlogin_buf_dma); 4408 ha->exlogin_buf = NULL; 4409 ha->exlogin_size = 0; 4410 } 4411 } 4412 4413 static void 4414 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4415 { 4416 u32 temp; 4417 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4418 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4419 4420 if (max_cnt > vha->hw->max_exchg) 4421 max_cnt = vha->hw->max_exchg; 4422 4423 if (qla_ini_mode_enabled(vha)) { 4424 if (vha->ql2xiniexchg > max_cnt) 4425 vha->ql2xiniexchg = max_cnt; 4426 4427 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4428 *ret_cnt = vha->ql2xiniexchg; 4429 4430 } else if (qla_tgt_mode_enabled(vha)) { 4431 if (vha->ql2xexchoffld > max_cnt) { 4432 vha->ql2xexchoffld = max_cnt; 4433 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4434 } 4435 4436 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4437 *ret_cnt = vha->ql2xexchoffld; 4438 } else if (qla_dual_mode_enabled(vha)) { 4439 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4440 if (temp > max_cnt) { 4441 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4442 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4443 temp = max_cnt; 4444 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4445 } 4446 4447 if (temp > FW_DEF_EXCHANGES_CNT) 4448 *ret_cnt = temp; 4449 } 4450 } 4451 4452 int 4453 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4454 { 4455 int rval; 4456 u16 size, max_cnt; 4457 u32 actual_cnt, totsz; 4458 struct qla_hw_data *ha = vha->hw; 4459 4460 if (!ha->flags.exchoffld_enabled) 4461 return QLA_SUCCESS; 4462 4463 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4464 return QLA_SUCCESS; 4465 4466 max_cnt = 0; 4467 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4468 if (rval != QLA_SUCCESS) { 4469 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4470 "Failed to get exlogin status.\n"); 4471 return rval; 4472 } 4473 4474 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4475 ql_log(ql_log_info, vha, 0xd014, 4476 "Actual exchange offload count: %d.\n", actual_cnt); 4477 4478 totsz = actual_cnt * size; 4479 4480 if (totsz != ha->exchoffld_size) { 4481 qla2x00_free_exchoffld_buffer(ha); 4482 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4483 ha->exchoffld_size = 0; 4484 ha->flags.exchoffld_enabled = 0; 4485 return QLA_SUCCESS; 4486 } 4487 4488 ha->exchoffld_size = totsz; 4489 4490 ql_log(ql_log_info, vha, 0xd016, 4491 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4492 max_cnt, actual_cnt, size, totsz); 4493 4494 ql_log(ql_log_info, vha, 0xd017, 4495 "Exchange Buffers requested size = 0x%x\n", 4496 ha->exchoffld_size); 4497 4498 /* Get consistent memory for extended logins */ 4499 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4500 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4501 if (!ha->exchoffld_buf) { 4502 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4503 "Failed to allocate memory for Exchange Offload.\n"); 4504 4505 if (ha->max_exchg > 4506 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4507 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4508 } else if (ha->max_exchg > 4509 (FW_DEF_EXCHANGES_CNT + 512)) { 4510 ha->max_exchg -= 512; 4511 } else { 4512 ha->flags.exchoffld_enabled = 0; 4513 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4514 "Disabling Exchange offload due to lack of memory\n"); 4515 } 4516 ha->exchoffld_size = 0; 4517 4518 return -ENOMEM; 4519 } 4520 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4521 /* pathological case */ 4522 qla2x00_free_exchoffld_buffer(ha); 4523 ha->exchoffld_size = 0; 4524 ha->flags.exchoffld_enabled = 0; 4525 ql_log(ql_log_info, vha, 0xd016, 4526 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4527 ha->exchoffld_size, actual_cnt, size, totsz); 4528 return 0; 4529 } 4530 4531 /* Now configure the dma buffer */ 4532 rval = qla_set_exchoffld_mem_cfg(vha); 4533 if (rval) { 4534 ql_log(ql_log_fatal, vha, 0xd02e, 4535 "Setup exchange offload buffer ****FAILED****.\n"); 4536 qla2x00_free_exchoffld_buffer(ha); 4537 } else { 4538 /* re-adjust number of target exchange */ 4539 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4540 4541 if (qla_ini_mode_enabled(vha)) 4542 icb->exchange_count = 0; 4543 else 4544 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4545 } 4546 4547 return rval; 4548 } 4549 4550 /* 4551 * qla2x00_free_exchoffld_buffer 4552 * 4553 * Input: 4554 * ha = adapter block pointer 4555 */ 4556 void 4557 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4558 { 4559 if (ha->exchoffld_buf) { 4560 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4561 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4562 ha->exchoffld_buf = NULL; 4563 ha->exchoffld_size = 0; 4564 } 4565 } 4566 4567 /* 4568 * qla2x00_free_fw_dump 4569 * Frees fw dump stuff. 4570 * 4571 * Input: 4572 * ha = adapter block pointer 4573 */ 4574 static void 4575 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4576 { 4577 struct fwdt *fwdt = ha->fwdt; 4578 uint j; 4579 4580 if (ha->fce) 4581 dma_free_coherent(&ha->pdev->dev, 4582 FCE_SIZE, ha->fce, ha->fce_dma); 4583 4584 if (ha->eft) 4585 dma_free_coherent(&ha->pdev->dev, 4586 EFT_SIZE, ha->eft, ha->eft_dma); 4587 4588 if (ha->fw_dump) 4589 vfree(ha->fw_dump); 4590 4591 ha->fce = NULL; 4592 ha->fce_dma = 0; 4593 ha->eft = NULL; 4594 ha->eft_dma = 0; 4595 ha->fw_dumped = 0; 4596 ha->fw_dump_cap_flags = 0; 4597 ha->fw_dump_reading = 0; 4598 ha->fw_dump = NULL; 4599 ha->fw_dump_len = 0; 4600 4601 for (j = 0; j < 2; j++, fwdt++) { 4602 if (fwdt->template) 4603 vfree(fwdt->template); 4604 fwdt->template = NULL; 4605 fwdt->length = 0; 4606 } 4607 } 4608 4609 /* 4610 * qla2x00_mem_free 4611 * Frees all adapter allocated memory. 4612 * 4613 * Input: 4614 * ha = adapter block pointer. 4615 */ 4616 static void 4617 qla2x00_mem_free(struct qla_hw_data *ha) 4618 { 4619 qla2x00_free_fw_dump(ha); 4620 4621 if (ha->mctp_dump) 4622 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4623 ha->mctp_dump_dma); 4624 ha->mctp_dump = NULL; 4625 4626 mempool_destroy(ha->srb_mempool); 4627 ha->srb_mempool = NULL; 4628 4629 if (ha->dcbx_tlv) 4630 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4631 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4632 ha->dcbx_tlv = NULL; 4633 4634 if (ha->xgmac_data) 4635 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4636 ha->xgmac_data, ha->xgmac_data_dma); 4637 ha->xgmac_data = NULL; 4638 4639 if (ha->sns_cmd) 4640 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4641 ha->sns_cmd, ha->sns_cmd_dma); 4642 ha->sns_cmd = NULL; 4643 ha->sns_cmd_dma = 0; 4644 4645 if (ha->ct_sns) 4646 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4647 ha->ct_sns, ha->ct_sns_dma); 4648 ha->ct_sns = NULL; 4649 ha->ct_sns_dma = 0; 4650 4651 if (ha->sfp_data) 4652 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4653 ha->sfp_data_dma); 4654 ha->sfp_data = NULL; 4655 4656 if (ha->flt) 4657 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4658 ha->flt, ha->flt_dma); 4659 ha->flt = NULL; 4660 ha->flt_dma = 0; 4661 4662 if (ha->ms_iocb) 4663 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4664 ha->ms_iocb = NULL; 4665 ha->ms_iocb_dma = 0; 4666 4667 if (ha->ex_init_cb) 4668 dma_pool_free(ha->s_dma_pool, 4669 ha->ex_init_cb, ha->ex_init_cb_dma); 4670 ha->ex_init_cb = NULL; 4671 ha->ex_init_cb_dma = 0; 4672 4673 if (ha->async_pd) 4674 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4675 ha->async_pd = NULL; 4676 ha->async_pd_dma = 0; 4677 4678 dma_pool_destroy(ha->s_dma_pool); 4679 ha->s_dma_pool = NULL; 4680 4681 if (ha->gid_list) 4682 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4683 ha->gid_list, ha->gid_list_dma); 4684 ha->gid_list = NULL; 4685 ha->gid_list_dma = 0; 4686 4687 if (IS_QLA82XX(ha)) { 4688 if (!list_empty(&ha->gbl_dsd_list)) { 4689 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4690 4691 /* clean up allocated prev pool */ 4692 list_for_each_entry_safe(dsd_ptr, 4693 tdsd_ptr, &ha->gbl_dsd_list, list) { 4694 dma_pool_free(ha->dl_dma_pool, 4695 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4696 list_del(&dsd_ptr->list); 4697 kfree(dsd_ptr); 4698 } 4699 } 4700 } 4701 4702 dma_pool_destroy(ha->dl_dma_pool); 4703 ha->dl_dma_pool = NULL; 4704 4705 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4706 ha->fcp_cmnd_dma_pool = NULL; 4707 4708 mempool_destroy(ha->ctx_mempool); 4709 ha->ctx_mempool = NULL; 4710 4711 if (ql2xenabledif) { 4712 struct dsd_dma *dsd, *nxt; 4713 4714 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4715 list) { 4716 list_del(&dsd->list); 4717 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4718 dsd->dsd_list_dma); 4719 ha->dif_bundle_dma_allocs--; 4720 kfree(dsd); 4721 ha->dif_bundle_kallocs--; 4722 ha->pool.unusable.count--; 4723 } 4724 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4725 list_del(&dsd->list); 4726 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4727 dsd->dsd_list_dma); 4728 ha->dif_bundle_dma_allocs--; 4729 kfree(dsd); 4730 ha->dif_bundle_kallocs--; 4731 } 4732 } 4733 4734 if (ha->dif_bundl_pool) 4735 dma_pool_destroy(ha->dif_bundl_pool); 4736 ha->dif_bundl_pool = NULL; 4737 4738 qlt_mem_free(ha); 4739 4740 if (ha->init_cb) 4741 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4742 ha->init_cb, ha->init_cb_dma); 4743 ha->init_cb = NULL; 4744 ha->init_cb_dma = 0; 4745 4746 vfree(ha->optrom_buffer); 4747 ha->optrom_buffer = NULL; 4748 kfree(ha->nvram); 4749 ha->nvram = NULL; 4750 kfree(ha->npiv_info); 4751 ha->npiv_info = NULL; 4752 kfree(ha->swl); 4753 ha->swl = NULL; 4754 kfree(ha->loop_id_map); 4755 ha->loop_id_map = NULL; 4756 } 4757 4758 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4759 struct qla_hw_data *ha) 4760 { 4761 struct Scsi_Host *host; 4762 struct scsi_qla_host *vha = NULL; 4763 4764 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4765 if (!host) { 4766 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4767 "Failed to allocate host from the scsi layer, aborting.\n"); 4768 return NULL; 4769 } 4770 4771 /* Clear our data area */ 4772 vha = shost_priv(host); 4773 memset(vha, 0, sizeof(scsi_qla_host_t)); 4774 4775 vha->host = host; 4776 vha->host_no = host->host_no; 4777 vha->hw = ha; 4778 4779 vha->qlini_mode = ql2x_ini_mode; 4780 vha->ql2xexchoffld = ql2xexchoffld; 4781 vha->ql2xiniexchg = ql2xiniexchg; 4782 4783 INIT_LIST_HEAD(&vha->vp_fcports); 4784 INIT_LIST_HEAD(&vha->work_list); 4785 INIT_LIST_HEAD(&vha->list); 4786 INIT_LIST_HEAD(&vha->qla_cmd_list); 4787 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4788 INIT_LIST_HEAD(&vha->logo_list); 4789 INIT_LIST_HEAD(&vha->plogi_ack_list); 4790 INIT_LIST_HEAD(&vha->qp_list); 4791 INIT_LIST_HEAD(&vha->gnl.fcports); 4792 INIT_LIST_HEAD(&vha->gpnid_list); 4793 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4794 4795 spin_lock_init(&vha->work_lock); 4796 spin_lock_init(&vha->cmd_list_lock); 4797 init_waitqueue_head(&vha->fcport_waitQ); 4798 init_waitqueue_head(&vha->vref_waitq); 4799 4800 vha->gnl.size = sizeof(struct get_name_list_extended) * 4801 (ha->max_loop_id + 1); 4802 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4803 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4804 if (!vha->gnl.l) { 4805 ql_log(ql_log_fatal, vha, 0xd04a, 4806 "Alloc failed for name list.\n"); 4807 scsi_remove_host(vha->host); 4808 return NULL; 4809 } 4810 4811 /* todo: what about ext login? */ 4812 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4813 vha->scan.l = vmalloc(vha->scan.size); 4814 if (!vha->scan.l) { 4815 ql_log(ql_log_fatal, vha, 0xd04a, 4816 "Alloc failed for scan database.\n"); 4817 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4818 vha->gnl.l, vha->gnl.ldma); 4819 scsi_remove_host(vha->host); 4820 return NULL; 4821 } 4822 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4823 4824 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); 4825 ql_dbg(ql_dbg_init, vha, 0x0041, 4826 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4827 vha->host, vha->hw, vha, 4828 dev_name(&(ha->pdev->dev))); 4829 4830 return vha; 4831 } 4832 4833 struct qla_work_evt * 4834 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4835 { 4836 struct qla_work_evt *e; 4837 uint8_t bail; 4838 4839 QLA_VHA_MARK_BUSY(vha, bail); 4840 if (bail) 4841 return NULL; 4842 4843 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4844 if (!e) { 4845 QLA_VHA_MARK_NOT_BUSY(vha); 4846 return NULL; 4847 } 4848 4849 INIT_LIST_HEAD(&e->list); 4850 e->type = type; 4851 e->flags = QLA_EVT_FLAG_FREE; 4852 return e; 4853 } 4854 4855 int 4856 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4857 { 4858 unsigned long flags; 4859 bool q = false; 4860 4861 spin_lock_irqsave(&vha->work_lock, flags); 4862 list_add_tail(&e->list, &vha->work_list); 4863 4864 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4865 q = true; 4866 4867 spin_unlock_irqrestore(&vha->work_lock, flags); 4868 4869 if (q) 4870 queue_work(vha->hw->wq, &vha->iocb_work); 4871 4872 return QLA_SUCCESS; 4873 } 4874 4875 int 4876 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4877 u32 data) 4878 { 4879 struct qla_work_evt *e; 4880 4881 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4882 if (!e) 4883 return QLA_FUNCTION_FAILED; 4884 4885 e->u.aen.code = code; 4886 e->u.aen.data = data; 4887 return qla2x00_post_work(vha, e); 4888 } 4889 4890 int 4891 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4892 { 4893 struct qla_work_evt *e; 4894 4895 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4896 if (!e) 4897 return QLA_FUNCTION_FAILED; 4898 4899 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4900 return qla2x00_post_work(vha, e); 4901 } 4902 4903 #define qla2x00_post_async_work(name, type) \ 4904 int qla2x00_post_async_##name##_work( \ 4905 struct scsi_qla_host *vha, \ 4906 fc_port_t *fcport, uint16_t *data) \ 4907 { \ 4908 struct qla_work_evt *e; \ 4909 \ 4910 e = qla2x00_alloc_work(vha, type); \ 4911 if (!e) \ 4912 return QLA_FUNCTION_FAILED; \ 4913 \ 4914 e->u.logio.fcport = fcport; \ 4915 if (data) { \ 4916 e->u.logio.data[0] = data[0]; \ 4917 e->u.logio.data[1] = data[1]; \ 4918 } \ 4919 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4920 return qla2x00_post_work(vha, e); \ 4921 } 4922 4923 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4924 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4925 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); 4926 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4927 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4928 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4929 4930 int 4931 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4932 { 4933 struct qla_work_evt *e; 4934 4935 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4936 if (!e) 4937 return QLA_FUNCTION_FAILED; 4938 4939 e->u.uevent.code = code; 4940 return qla2x00_post_work(vha, e); 4941 } 4942 4943 static void 4944 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4945 { 4946 char event_string[40]; 4947 char *envp[] = { event_string, NULL }; 4948 4949 switch (code) { 4950 case QLA_UEVENT_CODE_FW_DUMP: 4951 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", 4952 vha->host_no); 4953 break; 4954 default: 4955 /* do nothing */ 4956 break; 4957 } 4958 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 4959 } 4960 4961 int 4962 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 4963 uint32_t *data, int cnt) 4964 { 4965 struct qla_work_evt *e; 4966 4967 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 4968 if (!e) 4969 return QLA_FUNCTION_FAILED; 4970 4971 e->u.aenfx.evtcode = evtcode; 4972 e->u.aenfx.count = cnt; 4973 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 4974 return qla2x00_post_work(vha, e); 4975 } 4976 4977 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 4978 { 4979 unsigned long flags; 4980 4981 if (IS_SW_RESV_ADDR(fcport->d_id)) 4982 return; 4983 4984 spin_lock_irqsave(&fcport->vha->work_lock, flags); 4985 if (fcport->disc_state == DSC_UPD_FCPORT) { 4986 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 4987 return; 4988 } 4989 fcport->jiffies_at_registration = jiffies; 4990 fcport->sec_since_registration = 0; 4991 fcport->next_disc_state = DSC_DELETED; 4992 fcport->disc_state = DSC_UPD_FCPORT; 4993 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 4994 4995 queue_work(system_unbound_wq, &fcport->reg_work); 4996 } 4997 4998 static 4999 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5000 { 5001 unsigned long flags; 5002 fc_port_t *fcport = NULL, *tfcp; 5003 struct qlt_plogi_ack_t *pla = 5004 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5005 uint8_t free_fcport = 0; 5006 5007 ql_dbg(ql_dbg_disc, vha, 0xffff, 5008 "%s %d %8phC enter\n", 5009 __func__, __LINE__, e->u.new_sess.port_name); 5010 5011 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5012 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5013 if (fcport) { 5014 fcport->d_id = e->u.new_sess.id; 5015 if (pla) { 5016 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5017 memcpy(fcport->node_name, 5018 pla->iocb.u.isp24.u.plogi.node_name, 5019 WWN_SIZE); 5020 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5021 /* we took an extra ref_count to prevent PLOGI ACK when 5022 * fcport/sess has not been created. 5023 */ 5024 pla->ref_count--; 5025 } 5026 } else { 5027 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5028 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5029 if (fcport) { 5030 fcport->d_id = e->u.new_sess.id; 5031 fcport->flags |= FCF_FABRIC_DEVICE; 5032 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5033 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP) 5034 fcport->fc4_type = FC4_TYPE_FCP_SCSI; 5035 5036 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) { 5037 fcport->fc4_type = FC4_TYPE_OTHER; 5038 fcport->fc4f_nvme = FC4_TYPE_NVME; 5039 } 5040 5041 memcpy(fcport->port_name, e->u.new_sess.port_name, 5042 WWN_SIZE); 5043 } else { 5044 ql_dbg(ql_dbg_disc, vha, 0xffff, 5045 "%s %8phC mem alloc fail.\n", 5046 __func__, e->u.new_sess.port_name); 5047 5048 if (pla) 5049 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5050 return; 5051 } 5052 5053 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5054 /* search again to make sure no one else got ahead */ 5055 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5056 e->u.new_sess.port_name, 1); 5057 if (tfcp) { 5058 /* should rarily happen */ 5059 ql_dbg(ql_dbg_disc, vha, 0xffff, 5060 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5061 __func__, tfcp->port_name, tfcp->disc_state, 5062 tfcp->fw_login_state); 5063 5064 free_fcport = 1; 5065 } else { 5066 list_add_tail(&fcport->list, &vha->vp_fcports); 5067 5068 } 5069 if (pla) { 5070 qlt_plogi_ack_link(vha, pla, fcport, 5071 QLT_PLOGI_LINK_SAME_WWN); 5072 pla->ref_count--; 5073 } 5074 } 5075 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5076 5077 if (fcport) { 5078 fcport->id_changed = 1; 5079 fcport->scan_state = QLA_FCPORT_FOUND; 5080 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5081 5082 if (pla) { 5083 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5084 u16 wd3_lo; 5085 5086 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5087 fcport->local = 0; 5088 fcport->loop_id = 5089 le16_to_cpu( 5090 pla->iocb.u.isp24.nport_handle); 5091 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5092 wd3_lo = 5093 le16_to_cpu( 5094 pla->iocb.u.isp24.u.prli.wd3_lo); 5095 5096 if (wd3_lo & BIT_7) 5097 fcport->conf_compl_supported = 1; 5098 5099 if ((wd3_lo & BIT_4) == 0) 5100 fcport->port_type = FCT_INITIATOR; 5101 else 5102 fcport->port_type = FCT_TARGET; 5103 } 5104 qlt_plogi_ack_unref(vha, pla); 5105 } else { 5106 fc_port_t *dfcp = NULL; 5107 5108 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5109 tfcp = qla2x00_find_fcport_by_nportid(vha, 5110 &e->u.new_sess.id, 1); 5111 if (tfcp && (tfcp != fcport)) { 5112 /* 5113 * We have a conflict fcport with same NportID. 5114 */ 5115 ql_dbg(ql_dbg_disc, vha, 0xffff, 5116 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5117 __func__, tfcp->port_name, tfcp->disc_state, 5118 tfcp->fw_login_state); 5119 5120 switch (tfcp->disc_state) { 5121 case DSC_DELETED: 5122 break; 5123 case DSC_DELETE_PEND: 5124 fcport->login_pause = 1; 5125 tfcp->conflict = fcport; 5126 break; 5127 default: 5128 fcport->login_pause = 1; 5129 tfcp->conflict = fcport; 5130 dfcp = tfcp; 5131 break; 5132 } 5133 } 5134 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5135 if (dfcp) 5136 qlt_schedule_sess_for_deletion(tfcp); 5137 5138 5139 if (N2N_TOPO(vha->hw)) 5140 fcport->flags &= ~FCF_FABRIC_DEVICE; 5141 5142 if (N2N_TOPO(vha->hw)) { 5143 if (vha->flags.nvme_enabled) { 5144 fcport->fc4f_nvme = 1; 5145 fcport->n2n_flag = 1; 5146 } 5147 fcport->fw_login_state = 0; 5148 /* 5149 * wait link init done before sending login 5150 */ 5151 } else { 5152 qla24xx_fcport_handle_login(vha, fcport); 5153 } 5154 } 5155 } 5156 5157 if (free_fcport) { 5158 qla2x00_free_fcport(fcport); 5159 if (pla) 5160 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5161 } 5162 } 5163 5164 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5165 { 5166 struct srb *sp = e->u.iosb.sp; 5167 int rval; 5168 5169 rval = qla2x00_start_sp(sp); 5170 if (rval != QLA_SUCCESS) { 5171 ql_dbg(ql_dbg_disc, vha, 0x2043, 5172 "%s: %s: Re-issue IOCB failed (%d).\n", 5173 __func__, sp->name, rval); 5174 qla24xx_sp_unmap(vha, sp); 5175 } 5176 } 5177 5178 void 5179 qla2x00_do_work(struct scsi_qla_host *vha) 5180 { 5181 struct qla_work_evt *e, *tmp; 5182 unsigned long flags; 5183 LIST_HEAD(work); 5184 int rc; 5185 5186 spin_lock_irqsave(&vha->work_lock, flags); 5187 list_splice_init(&vha->work_list, &work); 5188 spin_unlock_irqrestore(&vha->work_lock, flags); 5189 5190 list_for_each_entry_safe(e, tmp, &work, list) { 5191 rc = QLA_SUCCESS; 5192 switch (e->type) { 5193 case QLA_EVT_AEN: 5194 fc_host_post_event(vha->host, fc_get_event_number(), 5195 e->u.aen.code, e->u.aen.data); 5196 break; 5197 case QLA_EVT_IDC_ACK: 5198 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5199 break; 5200 case QLA_EVT_ASYNC_LOGIN: 5201 qla2x00_async_login(vha, e->u.logio.fcport, 5202 e->u.logio.data); 5203 break; 5204 case QLA_EVT_ASYNC_LOGOUT: 5205 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5206 break; 5207 case QLA_EVT_ASYNC_LOGOUT_DONE: 5208 qla2x00_async_logout_done(vha, e->u.logio.fcport, 5209 e->u.logio.data); 5210 break; 5211 case QLA_EVT_ASYNC_ADISC: 5212 qla2x00_async_adisc(vha, e->u.logio.fcport, 5213 e->u.logio.data); 5214 break; 5215 case QLA_EVT_UEVENT: 5216 qla2x00_uevent_emit(vha, e->u.uevent.code); 5217 break; 5218 case QLA_EVT_AENFX: 5219 qlafx00_process_aen(vha, e); 5220 break; 5221 case QLA_EVT_GPNID: 5222 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5223 break; 5224 case QLA_EVT_UNMAP: 5225 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5226 break; 5227 case QLA_EVT_RELOGIN: 5228 qla2x00_relogin(vha); 5229 break; 5230 case QLA_EVT_NEW_SESS: 5231 qla24xx_create_new_sess(vha, e); 5232 break; 5233 case QLA_EVT_GPDB: 5234 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5235 e->u.fcport.opt); 5236 break; 5237 case QLA_EVT_PRLI: 5238 qla24xx_async_prli(vha, e->u.fcport.fcport); 5239 break; 5240 case QLA_EVT_GPSC: 5241 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5242 break; 5243 case QLA_EVT_GNL: 5244 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5245 break; 5246 case QLA_EVT_NACK: 5247 qla24xx_do_nack_work(vha, e); 5248 break; 5249 case QLA_EVT_ASYNC_PRLO: 5250 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5251 break; 5252 case QLA_EVT_ASYNC_PRLO_DONE: 5253 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5254 e->u.logio.data); 5255 break; 5256 case QLA_EVT_GPNFT: 5257 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5258 e->u.gpnft.sp); 5259 break; 5260 case QLA_EVT_GPNFT_DONE: 5261 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5262 break; 5263 case QLA_EVT_GNNFT_DONE: 5264 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5265 break; 5266 case QLA_EVT_GNNID: 5267 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5268 break; 5269 case QLA_EVT_GFPNID: 5270 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5271 break; 5272 case QLA_EVT_SP_RETRY: 5273 qla_sp_retry(vha, e); 5274 break; 5275 case QLA_EVT_IIDMA: 5276 qla_do_iidma_work(vha, e->u.fcport.fcport); 5277 break; 5278 case QLA_EVT_ELS_PLOGI: 5279 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5280 e->u.fcport.fcport, false); 5281 break; 5282 } 5283 5284 if (rc == EAGAIN) { 5285 /* put 'work' at head of 'vha->work_list' */ 5286 spin_lock_irqsave(&vha->work_lock, flags); 5287 list_splice(&work, &vha->work_list); 5288 spin_unlock_irqrestore(&vha->work_lock, flags); 5289 break; 5290 } 5291 list_del_init(&e->list); 5292 if (e->flags & QLA_EVT_FLAG_FREE) 5293 kfree(e); 5294 5295 /* For each work completed decrement vha ref count */ 5296 QLA_VHA_MARK_NOT_BUSY(vha); 5297 } 5298 } 5299 5300 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5301 { 5302 struct qla_work_evt *e; 5303 5304 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5305 5306 if (!e) { 5307 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5308 return QLA_FUNCTION_FAILED; 5309 } 5310 5311 return qla2x00_post_work(vha, e); 5312 } 5313 5314 /* Relogins all the fcports of a vport 5315 * Context: dpc thread 5316 */ 5317 void qla2x00_relogin(struct scsi_qla_host *vha) 5318 { 5319 fc_port_t *fcport; 5320 int status, relogin_needed = 0; 5321 struct event_arg ea; 5322 5323 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5324 /* 5325 * If the port is not ONLINE then try to login 5326 * to it if we haven't run out of retries. 5327 */ 5328 if (atomic_read(&fcport->state) != FCS_ONLINE && 5329 fcport->login_retry) { 5330 if (fcport->scan_state != QLA_FCPORT_FOUND || 5331 fcport->disc_state == DSC_LOGIN_COMPLETE) 5332 continue; 5333 5334 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5335 fcport->disc_state == DSC_DELETE_PEND) { 5336 relogin_needed = 1; 5337 } else { 5338 if (vha->hw->current_topology != ISP_CFG_NL) { 5339 memset(&ea, 0, sizeof(ea)); 5340 ea.event = FCME_RELOGIN; 5341 ea.fcport = fcport; 5342 qla2x00_fcport_event_handler(vha, &ea); 5343 } else if (vha->hw->current_topology == 5344 ISP_CFG_NL) { 5345 fcport->login_retry--; 5346 status = 5347 qla2x00_local_device_login(vha, 5348 fcport); 5349 if (status == QLA_SUCCESS) { 5350 fcport->old_loop_id = 5351 fcport->loop_id; 5352 ql_dbg(ql_dbg_disc, vha, 0x2003, 5353 "Port login OK: logged in ID 0x%x.\n", 5354 fcport->loop_id); 5355 qla2x00_update_fcport 5356 (vha, fcport); 5357 } else if (status == 1) { 5358 set_bit(RELOGIN_NEEDED, 5359 &vha->dpc_flags); 5360 /* retry the login again */ 5361 ql_dbg(ql_dbg_disc, vha, 0x2007, 5362 "Retrying %d login again loop_id 0x%x.\n", 5363 fcport->login_retry, 5364 fcport->loop_id); 5365 } else { 5366 fcport->login_retry = 0; 5367 } 5368 5369 if (fcport->login_retry == 0 && 5370 status != QLA_SUCCESS) 5371 qla2x00_clear_loop_id(fcport); 5372 } 5373 } 5374 } 5375 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5376 break; 5377 } 5378 5379 if (relogin_needed) 5380 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5381 5382 ql_dbg(ql_dbg_disc, vha, 0x400e, 5383 "Relogin end.\n"); 5384 } 5385 5386 /* Schedule work on any of the dpc-workqueues */ 5387 void 5388 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5389 { 5390 struct qla_hw_data *ha = base_vha->hw; 5391 5392 switch (work_code) { 5393 case MBA_IDC_AEN: /* 0x8200 */ 5394 if (ha->dpc_lp_wq) 5395 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5396 break; 5397 5398 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5399 if (!ha->flags.nic_core_reset_hdlr_active) { 5400 if (ha->dpc_hp_wq) 5401 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5402 } else 5403 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5404 "NIC Core reset is already active. Skip " 5405 "scheduling it again.\n"); 5406 break; 5407 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5408 if (ha->dpc_hp_wq) 5409 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5410 break; 5411 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5412 if (ha->dpc_hp_wq) 5413 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5414 break; 5415 default: 5416 ql_log(ql_log_warn, base_vha, 0xb05f, 5417 "Unknown work-code=0x%x.\n", work_code); 5418 } 5419 5420 return; 5421 } 5422 5423 /* Work: Perform NIC Core Unrecoverable state handling */ 5424 void 5425 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5426 { 5427 struct qla_hw_data *ha = 5428 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5429 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5430 uint32_t dev_state = 0; 5431 5432 qla83xx_idc_lock(base_vha, 0); 5433 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5434 qla83xx_reset_ownership(base_vha); 5435 if (ha->flags.nic_core_reset_owner) { 5436 ha->flags.nic_core_reset_owner = 0; 5437 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5438 QLA8XXX_DEV_FAILED); 5439 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5440 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5441 } 5442 qla83xx_idc_unlock(base_vha, 0); 5443 } 5444 5445 /* Work: Execute IDC state handler */ 5446 void 5447 qla83xx_idc_state_handler_work(struct work_struct *work) 5448 { 5449 struct qla_hw_data *ha = 5450 container_of(work, struct qla_hw_data, idc_state_handler); 5451 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5452 uint32_t dev_state = 0; 5453 5454 qla83xx_idc_lock(base_vha, 0); 5455 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5456 if (dev_state == QLA8XXX_DEV_FAILED || 5457 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5458 qla83xx_idc_state_handler(base_vha); 5459 qla83xx_idc_unlock(base_vha, 0); 5460 } 5461 5462 static int 5463 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5464 { 5465 int rval = QLA_SUCCESS; 5466 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5467 uint32_t heart_beat_counter1, heart_beat_counter2; 5468 5469 do { 5470 if (time_after(jiffies, heart_beat_wait)) { 5471 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5472 "Nic Core f/w is not alive.\n"); 5473 rval = QLA_FUNCTION_FAILED; 5474 break; 5475 } 5476 5477 qla83xx_idc_lock(base_vha, 0); 5478 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5479 &heart_beat_counter1); 5480 qla83xx_idc_unlock(base_vha, 0); 5481 msleep(100); 5482 qla83xx_idc_lock(base_vha, 0); 5483 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5484 &heart_beat_counter2); 5485 qla83xx_idc_unlock(base_vha, 0); 5486 } while (heart_beat_counter1 == heart_beat_counter2); 5487 5488 return rval; 5489 } 5490 5491 /* Work: Perform NIC Core Reset handling */ 5492 void 5493 qla83xx_nic_core_reset_work(struct work_struct *work) 5494 { 5495 struct qla_hw_data *ha = 5496 container_of(work, struct qla_hw_data, nic_core_reset); 5497 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5498 uint32_t dev_state = 0; 5499 5500 if (IS_QLA2031(ha)) { 5501 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5502 ql_log(ql_log_warn, base_vha, 0xb081, 5503 "Failed to dump mctp\n"); 5504 return; 5505 } 5506 5507 if (!ha->flags.nic_core_reset_hdlr_active) { 5508 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5509 qla83xx_idc_lock(base_vha, 0); 5510 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5511 &dev_state); 5512 qla83xx_idc_unlock(base_vha, 0); 5513 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5514 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5515 "Nic Core f/w is alive.\n"); 5516 return; 5517 } 5518 } 5519 5520 ha->flags.nic_core_reset_hdlr_active = 1; 5521 if (qla83xx_nic_core_reset(base_vha)) { 5522 /* NIC Core reset failed. */ 5523 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5524 "NIC Core reset failed.\n"); 5525 } 5526 ha->flags.nic_core_reset_hdlr_active = 0; 5527 } 5528 } 5529 5530 /* Work: Handle 8200 IDC aens */ 5531 void 5532 qla83xx_service_idc_aen(struct work_struct *work) 5533 { 5534 struct qla_hw_data *ha = 5535 container_of(work, struct qla_hw_data, idc_aen); 5536 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5537 uint32_t dev_state, idc_control; 5538 5539 qla83xx_idc_lock(base_vha, 0); 5540 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5541 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5542 qla83xx_idc_unlock(base_vha, 0); 5543 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5544 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5545 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5546 "Application requested NIC Core Reset.\n"); 5547 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5548 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5549 QLA_SUCCESS) { 5550 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5551 "Other protocol driver requested NIC Core Reset.\n"); 5552 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5553 } 5554 } else if (dev_state == QLA8XXX_DEV_FAILED || 5555 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5556 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5557 } 5558 } 5559 5560 static void 5561 qla83xx_wait_logic(void) 5562 { 5563 int i; 5564 5565 /* Yield CPU */ 5566 if (!in_interrupt()) { 5567 /* 5568 * Wait about 200ms before retrying again. 5569 * This controls the number of retries for single 5570 * lock operation. 5571 */ 5572 msleep(100); 5573 schedule(); 5574 } else { 5575 for (i = 0; i < 20; i++) 5576 cpu_relax(); /* This a nop instr on i386 */ 5577 } 5578 } 5579 5580 static int 5581 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5582 { 5583 int rval; 5584 uint32_t data; 5585 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5586 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5587 struct qla_hw_data *ha = base_vha->hw; 5588 5589 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5590 "Trying force recovery of the IDC lock.\n"); 5591 5592 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5593 if (rval) 5594 return rval; 5595 5596 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5597 return QLA_SUCCESS; 5598 } else { 5599 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5600 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5601 data); 5602 if (rval) 5603 return rval; 5604 5605 msleep(200); 5606 5607 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5608 &data); 5609 if (rval) 5610 return rval; 5611 5612 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5613 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5614 ~(idc_lck_rcvry_stage_mask)); 5615 rval = qla83xx_wr_reg(base_vha, 5616 QLA83XX_IDC_LOCK_RECOVERY, data); 5617 if (rval) 5618 return rval; 5619 5620 /* Forcefully perform IDC UnLock */ 5621 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5622 &data); 5623 if (rval) 5624 return rval; 5625 /* Clear lock-id by setting 0xff */ 5626 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5627 0xff); 5628 if (rval) 5629 return rval; 5630 /* Clear lock-recovery by setting 0x0 */ 5631 rval = qla83xx_wr_reg(base_vha, 5632 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5633 if (rval) 5634 return rval; 5635 } else 5636 return QLA_SUCCESS; 5637 } 5638 5639 return rval; 5640 } 5641 5642 static int 5643 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5644 { 5645 int rval = QLA_SUCCESS; 5646 uint32_t o_drv_lockid, n_drv_lockid; 5647 unsigned long lock_recovery_timeout; 5648 5649 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5650 retry_lockid: 5651 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5652 if (rval) 5653 goto exit; 5654 5655 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5656 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5657 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5658 return QLA_SUCCESS; 5659 else 5660 return QLA_FUNCTION_FAILED; 5661 } 5662 5663 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5664 if (rval) 5665 goto exit; 5666 5667 if (o_drv_lockid == n_drv_lockid) { 5668 qla83xx_wait_logic(); 5669 goto retry_lockid; 5670 } else 5671 return QLA_SUCCESS; 5672 5673 exit: 5674 return rval; 5675 } 5676 5677 void 5678 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5679 { 5680 uint16_t options = (requester_id << 15) | BIT_6; 5681 uint32_t data; 5682 uint32_t lock_owner; 5683 struct qla_hw_data *ha = base_vha->hw; 5684 5685 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5686 retry_lock: 5687 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5688 == QLA_SUCCESS) { 5689 if (data) { 5690 /* Setting lock-id to our function-number */ 5691 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5692 ha->portnum); 5693 } else { 5694 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5695 &lock_owner); 5696 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5697 "Failed to acquire IDC lock, acquired by %d, " 5698 "retrying...\n", lock_owner); 5699 5700 /* Retry/Perform IDC-Lock recovery */ 5701 if (qla83xx_idc_lock_recovery(base_vha) 5702 == QLA_SUCCESS) { 5703 qla83xx_wait_logic(); 5704 goto retry_lock; 5705 } else 5706 ql_log(ql_log_warn, base_vha, 0xb075, 5707 "IDC Lock recovery FAILED.\n"); 5708 } 5709 5710 } 5711 5712 return; 5713 5714 /* XXX: IDC-lock implementation using access-control mbx */ 5715 retry_lock2: 5716 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5717 ql_dbg(ql_dbg_p3p, base_vha, 0xb072, 5718 "Failed to acquire IDC lock. retrying...\n"); 5719 /* Retry/Perform IDC-Lock recovery */ 5720 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { 5721 qla83xx_wait_logic(); 5722 goto retry_lock2; 5723 } else 5724 ql_log(ql_log_warn, base_vha, 0xb076, 5725 "IDC Lock recovery FAILED.\n"); 5726 } 5727 5728 return; 5729 } 5730 5731 void 5732 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5733 { 5734 #if 0 5735 uint16_t options = (requester_id << 15) | BIT_7; 5736 #endif 5737 uint16_t retry; 5738 uint32_t data; 5739 struct qla_hw_data *ha = base_vha->hw; 5740 5741 /* IDC-unlock implementation using driver-unlock/lock-id 5742 * remote registers 5743 */ 5744 retry = 0; 5745 retry_unlock: 5746 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 5747 == QLA_SUCCESS) { 5748 if (data == ha->portnum) { 5749 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 5750 /* Clearing lock-id by setting 0xff */ 5751 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 5752 } else if (retry < 10) { 5753 /* SV: XXX: IDC unlock retrying needed here? */ 5754 5755 /* Retry for IDC-unlock */ 5756 qla83xx_wait_logic(); 5757 retry++; 5758 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 5759 "Failed to release IDC lock, retrying=%d\n", retry); 5760 goto retry_unlock; 5761 } 5762 } else if (retry < 10) { 5763 /* Retry for IDC-unlock */ 5764 qla83xx_wait_logic(); 5765 retry++; 5766 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 5767 "Failed to read drv-lockid, retrying=%d\n", retry); 5768 goto retry_unlock; 5769 } 5770 5771 return; 5772 5773 #if 0 5774 /* XXX: IDC-unlock implementation using access-control mbx */ 5775 retry = 0; 5776 retry_unlock2: 5777 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 5778 if (retry < 10) { 5779 /* Retry for IDC-unlock */ 5780 qla83xx_wait_logic(); 5781 retry++; 5782 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 5783 "Failed to release IDC lock, retrying=%d\n", retry); 5784 goto retry_unlock2; 5785 } 5786 } 5787 5788 return; 5789 #endif 5790 } 5791 5792 int 5793 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5794 { 5795 int rval = QLA_SUCCESS; 5796 struct qla_hw_data *ha = vha->hw; 5797 uint32_t drv_presence; 5798 5799 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5800 if (rval == QLA_SUCCESS) { 5801 drv_presence |= (1 << ha->portnum); 5802 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5803 drv_presence); 5804 } 5805 5806 return rval; 5807 } 5808 5809 int 5810 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 5811 { 5812 int rval = QLA_SUCCESS; 5813 5814 qla83xx_idc_lock(vha, 0); 5815 rval = __qla83xx_set_drv_presence(vha); 5816 qla83xx_idc_unlock(vha, 0); 5817 5818 return rval; 5819 } 5820 5821 int 5822 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5823 { 5824 int rval = QLA_SUCCESS; 5825 struct qla_hw_data *ha = vha->hw; 5826 uint32_t drv_presence; 5827 5828 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5829 if (rval == QLA_SUCCESS) { 5830 drv_presence &= ~(1 << ha->portnum); 5831 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5832 drv_presence); 5833 } 5834 5835 return rval; 5836 } 5837 5838 int 5839 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 5840 { 5841 int rval = QLA_SUCCESS; 5842 5843 qla83xx_idc_lock(vha, 0); 5844 rval = __qla83xx_clear_drv_presence(vha); 5845 qla83xx_idc_unlock(vha, 0); 5846 5847 return rval; 5848 } 5849 5850 static void 5851 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 5852 { 5853 struct qla_hw_data *ha = vha->hw; 5854 uint32_t drv_ack, drv_presence; 5855 unsigned long ack_timeout; 5856 5857 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 5858 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 5859 while (1) { 5860 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 5861 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 5862 if ((drv_ack & drv_presence) == drv_presence) 5863 break; 5864 5865 if (time_after_eq(jiffies, ack_timeout)) { 5866 ql_log(ql_log_warn, vha, 0xb067, 5867 "RESET ACK TIMEOUT! drv_presence=0x%x " 5868 "drv_ack=0x%x\n", drv_presence, drv_ack); 5869 /* 5870 * The function(s) which did not ack in time are forced 5871 * to withdraw any further participation in the IDC 5872 * reset. 5873 */ 5874 if (drv_ack != drv_presence) 5875 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 5876 drv_ack); 5877 break; 5878 } 5879 5880 qla83xx_idc_unlock(vha, 0); 5881 msleep(1000); 5882 qla83xx_idc_lock(vha, 0); 5883 } 5884 5885 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 5886 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 5887 } 5888 5889 static int 5890 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 5891 { 5892 int rval = QLA_SUCCESS; 5893 uint32_t idc_control; 5894 5895 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 5896 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 5897 5898 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 5899 __qla83xx_get_idc_control(vha, &idc_control); 5900 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 5901 __qla83xx_set_idc_control(vha, 0); 5902 5903 qla83xx_idc_unlock(vha, 0); 5904 rval = qla83xx_restart_nic_firmware(vha); 5905 qla83xx_idc_lock(vha, 0); 5906 5907 if (rval != QLA_SUCCESS) { 5908 ql_log(ql_log_fatal, vha, 0xb06a, 5909 "Failed to restart NIC f/w.\n"); 5910 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 5911 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 5912 } else { 5913 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 5914 "Success in restarting nic f/w.\n"); 5915 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 5916 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 5917 } 5918 5919 return rval; 5920 } 5921 5922 /* Assumes idc_lock always held on entry */ 5923 int 5924 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 5925 { 5926 struct qla_hw_data *ha = base_vha->hw; 5927 int rval = QLA_SUCCESS; 5928 unsigned long dev_init_timeout; 5929 uint32_t dev_state; 5930 5931 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 5932 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 5933 5934 while (1) { 5935 5936 if (time_after_eq(jiffies, dev_init_timeout)) { 5937 ql_log(ql_log_warn, base_vha, 0xb06e, 5938 "Initialization TIMEOUT!\n"); 5939 /* Init timeout. Disable further NIC Core 5940 * communication. 5941 */ 5942 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5943 QLA8XXX_DEV_FAILED); 5944 ql_log(ql_log_info, base_vha, 0xb06f, 5945 "HW State: FAILED.\n"); 5946 } 5947 5948 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5949 switch (dev_state) { 5950 case QLA8XXX_DEV_READY: 5951 if (ha->flags.nic_core_reset_owner) 5952 qla83xx_idc_audit(base_vha, 5953 IDC_AUDIT_COMPLETION); 5954 ha->flags.nic_core_reset_owner = 0; 5955 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 5956 "Reset_owner reset by 0x%x.\n", 5957 ha->portnum); 5958 goto exit; 5959 case QLA8XXX_DEV_COLD: 5960 if (ha->flags.nic_core_reset_owner) 5961 rval = qla83xx_device_bootstrap(base_vha); 5962 else { 5963 /* Wait for AEN to change device-state */ 5964 qla83xx_idc_unlock(base_vha, 0); 5965 msleep(1000); 5966 qla83xx_idc_lock(base_vha, 0); 5967 } 5968 break; 5969 case QLA8XXX_DEV_INITIALIZING: 5970 /* Wait for AEN to change device-state */ 5971 qla83xx_idc_unlock(base_vha, 0); 5972 msleep(1000); 5973 qla83xx_idc_lock(base_vha, 0); 5974 break; 5975 case QLA8XXX_DEV_NEED_RESET: 5976 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 5977 qla83xx_need_reset_handler(base_vha); 5978 else { 5979 /* Wait for AEN to change device-state */ 5980 qla83xx_idc_unlock(base_vha, 0); 5981 msleep(1000); 5982 qla83xx_idc_lock(base_vha, 0); 5983 } 5984 /* reset timeout value after need reset handler */ 5985 dev_init_timeout = jiffies + 5986 (ha->fcoe_dev_init_timeout * HZ); 5987 break; 5988 case QLA8XXX_DEV_NEED_QUIESCENT: 5989 /* XXX: DEBUG for now */ 5990 qla83xx_idc_unlock(base_vha, 0); 5991 msleep(1000); 5992 qla83xx_idc_lock(base_vha, 0); 5993 break; 5994 case QLA8XXX_DEV_QUIESCENT: 5995 /* XXX: DEBUG for now */ 5996 if (ha->flags.quiesce_owner) 5997 goto exit; 5998 5999 qla83xx_idc_unlock(base_vha, 0); 6000 msleep(1000); 6001 qla83xx_idc_lock(base_vha, 0); 6002 dev_init_timeout = jiffies + 6003 (ha->fcoe_dev_init_timeout * HZ); 6004 break; 6005 case QLA8XXX_DEV_FAILED: 6006 if (ha->flags.nic_core_reset_owner) 6007 qla83xx_idc_audit(base_vha, 6008 IDC_AUDIT_COMPLETION); 6009 ha->flags.nic_core_reset_owner = 0; 6010 __qla83xx_clear_drv_presence(base_vha); 6011 qla83xx_idc_unlock(base_vha, 0); 6012 qla8xxx_dev_failed_handler(base_vha); 6013 rval = QLA_FUNCTION_FAILED; 6014 qla83xx_idc_lock(base_vha, 0); 6015 goto exit; 6016 case QLA8XXX_BAD_VALUE: 6017 qla83xx_idc_unlock(base_vha, 0); 6018 msleep(1000); 6019 qla83xx_idc_lock(base_vha, 0); 6020 break; 6021 default: 6022 ql_log(ql_log_warn, base_vha, 0xb071, 6023 "Unknown Device State: %x.\n", dev_state); 6024 qla83xx_idc_unlock(base_vha, 0); 6025 qla8xxx_dev_failed_handler(base_vha); 6026 rval = QLA_FUNCTION_FAILED; 6027 qla83xx_idc_lock(base_vha, 0); 6028 goto exit; 6029 } 6030 } 6031 6032 exit: 6033 return rval; 6034 } 6035 6036 void 6037 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6038 { 6039 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6040 board_disable); 6041 struct pci_dev *pdev = ha->pdev; 6042 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6043 6044 /* 6045 * if UNLOAD flag is already set, then continue unload, 6046 * where it was set first. 6047 */ 6048 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6049 return; 6050 6051 ql_log(ql_log_warn, base_vha, 0x015b, 6052 "Disabling adapter.\n"); 6053 6054 if (!atomic_read(&pdev->enable_cnt)) { 6055 ql_log(ql_log_info, base_vha, 0xfffc, 6056 "PCI device disabled, no action req for PCI error=%lx\n", 6057 base_vha->pci_flags); 6058 return; 6059 } 6060 6061 qla2x00_wait_for_sess_deletion(base_vha); 6062 6063 set_bit(UNLOADING, &base_vha->dpc_flags); 6064 6065 qla2x00_delete_all_vps(ha, base_vha); 6066 6067 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6068 6069 qla2x00_dfs_remove(base_vha); 6070 6071 qla84xx_put_chip(base_vha); 6072 6073 if (base_vha->timer_active) 6074 qla2x00_stop_timer(base_vha); 6075 6076 base_vha->flags.online = 0; 6077 6078 qla2x00_destroy_deferred_work(ha); 6079 6080 /* 6081 * Do not try to stop beacon blink as it will issue a mailbox 6082 * command. 6083 */ 6084 qla2x00_free_sysfs_attr(base_vha, false); 6085 6086 fc_remove_host(base_vha->host); 6087 6088 scsi_remove_host(base_vha->host); 6089 6090 base_vha->flags.init_done = 0; 6091 qla25xx_delete_queues(base_vha); 6092 qla2x00_free_fcports(base_vha); 6093 qla2x00_free_irqs(base_vha); 6094 qla2x00_mem_free(ha); 6095 qla82xx_md_free(base_vha); 6096 qla2x00_free_queues(ha); 6097 6098 qla2x00_unmap_iobases(ha); 6099 6100 pci_release_selected_regions(ha->pdev, ha->bars); 6101 pci_disable_pcie_error_reporting(pdev); 6102 pci_disable_device(pdev); 6103 6104 /* 6105 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6106 */ 6107 } 6108 6109 /************************************************************************** 6110 * qla2x00_do_dpc 6111 * This kernel thread is a task that is schedule by the interrupt handler 6112 * to perform the background processing for interrupts. 6113 * 6114 * Notes: 6115 * This task always run in the context of a kernel thread. It 6116 * is kick-off by the driver's detect code and starts up 6117 * up one per adapter. It immediately goes to sleep and waits for 6118 * some fibre event. When either the interrupt handler or 6119 * the timer routine detects a event it will one of the task 6120 * bits then wake us up. 6121 **************************************************************************/ 6122 static int 6123 qla2x00_do_dpc(void *data) 6124 { 6125 scsi_qla_host_t *base_vha; 6126 struct qla_hw_data *ha; 6127 uint32_t online; 6128 struct qla_qpair *qpair; 6129 6130 ha = (struct qla_hw_data *)data; 6131 base_vha = pci_get_drvdata(ha->pdev); 6132 6133 set_user_nice(current, MIN_NICE); 6134 6135 set_current_state(TASK_INTERRUPTIBLE); 6136 while (!kthread_should_stop()) { 6137 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6138 "DPC handler sleeping.\n"); 6139 6140 schedule(); 6141 6142 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6143 goto end_loop; 6144 6145 if (ha->flags.eeh_busy) { 6146 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6147 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6148 goto end_loop; 6149 } 6150 6151 ha->dpc_active = 1; 6152 6153 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6154 "DPC handler waking up, dpc_flags=0x%lx.\n", 6155 base_vha->dpc_flags); 6156 6157 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6158 break; 6159 6160 if (IS_P3P_TYPE(ha)) { 6161 if (IS_QLA8044(ha)) { 6162 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6163 &base_vha->dpc_flags)) { 6164 qla8044_idc_lock(ha); 6165 qla8044_wr_direct(base_vha, 6166 QLA8044_CRB_DEV_STATE_INDEX, 6167 QLA8XXX_DEV_FAILED); 6168 qla8044_idc_unlock(ha); 6169 ql_log(ql_log_info, base_vha, 0x4004, 6170 "HW State: FAILED.\n"); 6171 qla8044_device_state_handler(base_vha); 6172 continue; 6173 } 6174 6175 } else { 6176 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6177 &base_vha->dpc_flags)) { 6178 qla82xx_idc_lock(ha); 6179 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6180 QLA8XXX_DEV_FAILED); 6181 qla82xx_idc_unlock(ha); 6182 ql_log(ql_log_info, base_vha, 0x0151, 6183 "HW State: FAILED.\n"); 6184 qla82xx_device_state_handler(base_vha); 6185 continue; 6186 } 6187 } 6188 6189 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6190 &base_vha->dpc_flags)) { 6191 6192 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6193 "FCoE context reset scheduled.\n"); 6194 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6195 &base_vha->dpc_flags))) { 6196 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6197 /* FCoE-ctx reset failed. 6198 * Escalate to chip-reset 6199 */ 6200 set_bit(ISP_ABORT_NEEDED, 6201 &base_vha->dpc_flags); 6202 } 6203 clear_bit(ABORT_ISP_ACTIVE, 6204 &base_vha->dpc_flags); 6205 } 6206 6207 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6208 "FCoE context reset end.\n"); 6209 } 6210 } else if (IS_QLAFX00(ha)) { 6211 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6212 &base_vha->dpc_flags)) { 6213 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6214 "Firmware Reset Recovery\n"); 6215 if (qlafx00_reset_initialize(base_vha)) { 6216 /* Failed. Abort isp later. */ 6217 if (!test_bit(UNLOADING, 6218 &base_vha->dpc_flags)) { 6219 set_bit(ISP_UNRECOVERABLE, 6220 &base_vha->dpc_flags); 6221 ql_dbg(ql_dbg_dpc, base_vha, 6222 0x4021, 6223 "Reset Recovery Failed\n"); 6224 } 6225 } 6226 } 6227 6228 if (test_and_clear_bit(FX00_TARGET_SCAN, 6229 &base_vha->dpc_flags)) { 6230 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6231 "ISPFx00 Target Scan scheduled\n"); 6232 if (qlafx00_rescan_isp(base_vha)) { 6233 if (!test_bit(UNLOADING, 6234 &base_vha->dpc_flags)) 6235 set_bit(ISP_UNRECOVERABLE, 6236 &base_vha->dpc_flags); 6237 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6238 "ISPFx00 Target Scan Failed\n"); 6239 } 6240 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6241 "ISPFx00 Target Scan End\n"); 6242 } 6243 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6244 &base_vha->dpc_flags)) { 6245 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6246 "ISPFx00 Host Info resend scheduled\n"); 6247 qlafx00_fx_disc(base_vha, 6248 &base_vha->hw->mr.fcport, 6249 FXDISC_REG_HOST_INFO); 6250 } 6251 } 6252 6253 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6254 &base_vha->dpc_flags) && 6255 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) { 6256 qla24xx_detect_sfp(base_vha); 6257 6258 if (ha->flags.detected_lr_sfp != 6259 ha->flags.using_lr_setting) 6260 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 6261 } 6262 6263 if (test_and_clear_bit 6264 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6265 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6266 bool do_reset = true; 6267 6268 switch (base_vha->qlini_mode) { 6269 case QLA2XXX_INI_MODE_ENABLED: 6270 break; 6271 case QLA2XXX_INI_MODE_DISABLED: 6272 if (!qla_tgt_mode_enabled(base_vha) && 6273 !ha->flags.fw_started) 6274 do_reset = false; 6275 break; 6276 case QLA2XXX_INI_MODE_DUAL: 6277 if (!qla_dual_mode_enabled(base_vha) && 6278 !ha->flags.fw_started) 6279 do_reset = false; 6280 break; 6281 default: 6282 break; 6283 } 6284 6285 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6286 &base_vha->dpc_flags))) { 6287 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6288 "ISP abort scheduled.\n"); 6289 if (ha->isp_ops->abort_isp(base_vha)) { 6290 /* failed. retry later */ 6291 set_bit(ISP_ABORT_NEEDED, 6292 &base_vha->dpc_flags); 6293 } 6294 clear_bit(ABORT_ISP_ACTIVE, 6295 &base_vha->dpc_flags); 6296 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6297 "ISP abort end.\n"); 6298 } 6299 } 6300 6301 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6302 &base_vha->dpc_flags)) { 6303 qla2x00_update_fcports(base_vha); 6304 } 6305 6306 if (IS_QLAFX00(ha)) 6307 goto loop_resync_check; 6308 6309 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6310 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6311 "Quiescence mode scheduled.\n"); 6312 if (IS_P3P_TYPE(ha)) { 6313 if (IS_QLA82XX(ha)) 6314 qla82xx_device_state_handler(base_vha); 6315 if (IS_QLA8044(ha)) 6316 qla8044_device_state_handler(base_vha); 6317 clear_bit(ISP_QUIESCE_NEEDED, 6318 &base_vha->dpc_flags); 6319 if (!ha->flags.quiesce_owner) { 6320 qla2x00_perform_loop_resync(base_vha); 6321 if (IS_QLA82XX(ha)) { 6322 qla82xx_idc_lock(ha); 6323 qla82xx_clear_qsnt_ready( 6324 base_vha); 6325 qla82xx_idc_unlock(ha); 6326 } else if (IS_QLA8044(ha)) { 6327 qla8044_idc_lock(ha); 6328 qla8044_clear_qsnt_ready( 6329 base_vha); 6330 qla8044_idc_unlock(ha); 6331 } 6332 } 6333 } else { 6334 clear_bit(ISP_QUIESCE_NEEDED, 6335 &base_vha->dpc_flags); 6336 qla2x00_quiesce_io(base_vha); 6337 } 6338 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6339 "Quiescence mode end.\n"); 6340 } 6341 6342 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6343 &base_vha->dpc_flags) && 6344 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6345 6346 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6347 "Reset marker scheduled.\n"); 6348 qla2x00_rst_aen(base_vha); 6349 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6350 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6351 "Reset marker end.\n"); 6352 } 6353 6354 /* Retry each device up to login retry count */ 6355 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6356 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6357 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6358 6359 if (!base_vha->relogin_jif || 6360 time_after_eq(jiffies, base_vha->relogin_jif)) { 6361 base_vha->relogin_jif = jiffies + HZ; 6362 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6363 6364 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6365 "Relogin scheduled.\n"); 6366 qla24xx_post_relogin_work(base_vha); 6367 } 6368 } 6369 loop_resync_check: 6370 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6371 &base_vha->dpc_flags)) { 6372 6373 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6374 "Loop resync scheduled.\n"); 6375 6376 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6377 &base_vha->dpc_flags))) { 6378 6379 qla2x00_loop_resync(base_vha); 6380 6381 clear_bit(LOOP_RESYNC_ACTIVE, 6382 &base_vha->dpc_flags); 6383 } 6384 6385 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6386 "Loop resync end.\n"); 6387 } 6388 6389 if (IS_QLAFX00(ha)) 6390 goto intr_on_check; 6391 6392 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6393 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6394 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6395 qla2xxx_flash_npiv_conf(base_vha); 6396 } 6397 6398 intr_on_check: 6399 if (!ha->interrupts_on) 6400 ha->isp_ops->enable_intrs(ha); 6401 6402 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6403 &base_vha->dpc_flags)) { 6404 if (ha->beacon_blink_led == 1) 6405 ha->isp_ops->beacon_blink(base_vha); 6406 } 6407 6408 /* qpair online check */ 6409 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6410 &base_vha->dpc_flags)) { 6411 if (ha->flags.eeh_busy || 6412 ha->flags.pci_channel_io_perm_failure) 6413 online = 0; 6414 else 6415 online = 1; 6416 6417 mutex_lock(&ha->mq_lock); 6418 list_for_each_entry(qpair, &base_vha->qp_list, 6419 qp_list_elem) 6420 qpair->online = online; 6421 mutex_unlock(&ha->mq_lock); 6422 } 6423 6424 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, 6425 &base_vha->dpc_flags)) { 6426 ql_log(ql_log_info, base_vha, 0xffffff, 6427 "nvme: SET ZIO Activity exchange threshold to %d.\n", 6428 ha->nvme_last_rptd_aen); 6429 if (qla27xx_set_zio_threshold(base_vha, 6430 ha->nvme_last_rptd_aen)) { 6431 ql_log(ql_log_info, base_vha, 0xffffff, 6432 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n", 6433 ha->nvme_last_rptd_aen); 6434 } 6435 } 6436 6437 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 6438 &base_vha->dpc_flags)) { 6439 ql_log(ql_log_info, base_vha, 0xffffff, 6440 "SET ZIO Activity exchange threshold to %d.\n", 6441 ha->last_zio_threshold); 6442 qla27xx_set_zio_threshold(base_vha, 6443 ha->last_zio_threshold); 6444 } 6445 6446 if (!IS_QLAFX00(ha)) 6447 qla2x00_do_dpc_all_vps(base_vha); 6448 6449 if (test_and_clear_bit(N2N_LINK_RESET, 6450 &base_vha->dpc_flags)) { 6451 qla2x00_lip_reset(base_vha); 6452 } 6453 6454 ha->dpc_active = 0; 6455 end_loop: 6456 set_current_state(TASK_INTERRUPTIBLE); 6457 } /* End of while(1) */ 6458 __set_current_state(TASK_RUNNING); 6459 6460 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6461 "DPC handler exiting.\n"); 6462 6463 /* 6464 * Make sure that nobody tries to wake us up again. 6465 */ 6466 ha->dpc_active = 0; 6467 6468 /* Cleanup any residual CTX SRBs. */ 6469 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6470 6471 return 0; 6472 } 6473 6474 void 6475 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6476 { 6477 struct qla_hw_data *ha = vha->hw; 6478 struct task_struct *t = ha->dpc_thread; 6479 6480 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6481 wake_up_process(t); 6482 } 6483 6484 /* 6485 * qla2x00_rst_aen 6486 * Processes asynchronous reset. 6487 * 6488 * Input: 6489 * ha = adapter block pointer. 6490 */ 6491 static void 6492 qla2x00_rst_aen(scsi_qla_host_t *vha) 6493 { 6494 if (vha->flags.online && !vha->flags.reset_active && 6495 !atomic_read(&vha->loop_down_timer) && 6496 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 6497 do { 6498 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 6499 6500 /* 6501 * Issue marker command only when we are going to start 6502 * the I/O. 6503 */ 6504 vha->marker_needed = 1; 6505 } while (!atomic_read(&vha->loop_down_timer) && 6506 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 6507 } 6508 } 6509 6510 /************************************************************************** 6511 * qla2x00_timer 6512 * 6513 * Description: 6514 * One second timer 6515 * 6516 * Context: Interrupt 6517 ***************************************************************************/ 6518 void 6519 qla2x00_timer(struct timer_list *t) 6520 { 6521 scsi_qla_host_t *vha = from_timer(vha, t, timer); 6522 unsigned long cpu_flags = 0; 6523 int start_dpc = 0; 6524 int index; 6525 srb_t *sp; 6526 uint16_t w; 6527 struct qla_hw_data *ha = vha->hw; 6528 struct req_que *req; 6529 6530 if (ha->flags.eeh_busy) { 6531 ql_dbg(ql_dbg_timer, vha, 0x6000, 6532 "EEH = %d, restarting timer.\n", 6533 ha->flags.eeh_busy); 6534 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6535 return; 6536 } 6537 6538 /* 6539 * Hardware read to raise pending EEH errors during mailbox waits. If 6540 * the read returns -1 then disable the board. 6541 */ 6542 if (!pci_channel_offline(ha->pdev)) { 6543 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 6544 qla2x00_check_reg16_for_disconnect(vha, w); 6545 } 6546 6547 /* Make sure qla82xx_watchdog is run only for physical port */ 6548 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 6549 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 6550 start_dpc++; 6551 if (IS_QLA82XX(ha)) 6552 qla82xx_watchdog(vha); 6553 else if (IS_QLA8044(ha)) 6554 qla8044_watchdog(vha); 6555 } 6556 6557 if (!vha->vp_idx && IS_QLAFX00(ha)) 6558 qlafx00_timer_routine(vha); 6559 6560 /* Loop down handler. */ 6561 if (atomic_read(&vha->loop_down_timer) > 0 && 6562 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 6563 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 6564 && vha->flags.online) { 6565 6566 if (atomic_read(&vha->loop_down_timer) == 6567 vha->loop_down_abort_time) { 6568 6569 ql_log(ql_log_info, vha, 0x6008, 6570 "Loop down - aborting the queues before time expires.\n"); 6571 6572 if (!IS_QLA2100(ha) && vha->link_down_timeout) 6573 atomic_set(&vha->loop_state, LOOP_DEAD); 6574 6575 /* 6576 * Schedule an ISP abort to return any FCP2-device 6577 * commands. 6578 */ 6579 /* NPIV - scan physical port only */ 6580 if (!vha->vp_idx) { 6581 spin_lock_irqsave(&ha->hardware_lock, 6582 cpu_flags); 6583 req = ha->req_q_map[0]; 6584 for (index = 1; 6585 index < req->num_outstanding_cmds; 6586 index++) { 6587 fc_port_t *sfcp; 6588 6589 sp = req->outstanding_cmds[index]; 6590 if (!sp) 6591 continue; 6592 if (sp->cmd_type != TYPE_SRB) 6593 continue; 6594 if (sp->type != SRB_SCSI_CMD) 6595 continue; 6596 sfcp = sp->fcport; 6597 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 6598 continue; 6599 6600 if (IS_QLA82XX(ha)) 6601 set_bit(FCOE_CTX_RESET_NEEDED, 6602 &vha->dpc_flags); 6603 else 6604 set_bit(ISP_ABORT_NEEDED, 6605 &vha->dpc_flags); 6606 break; 6607 } 6608 spin_unlock_irqrestore(&ha->hardware_lock, 6609 cpu_flags); 6610 } 6611 start_dpc++; 6612 } 6613 6614 /* if the loop has been down for 4 minutes, reinit adapter */ 6615 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 6616 if (!(vha->device_flags & DFLG_NO_CABLE)) { 6617 ql_log(ql_log_warn, vha, 0x6009, 6618 "Loop down - aborting ISP.\n"); 6619 6620 if (IS_QLA82XX(ha)) 6621 set_bit(FCOE_CTX_RESET_NEEDED, 6622 &vha->dpc_flags); 6623 else 6624 set_bit(ISP_ABORT_NEEDED, 6625 &vha->dpc_flags); 6626 } 6627 } 6628 ql_dbg(ql_dbg_timer, vha, 0x600a, 6629 "Loop down - seconds remaining %d.\n", 6630 atomic_read(&vha->loop_down_timer)); 6631 } 6632 /* Check if beacon LED needs to be blinked for physical host only */ 6633 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 6634 /* There is no beacon_blink function for ISP82xx */ 6635 if (!IS_P3P_TYPE(ha)) { 6636 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 6637 start_dpc++; 6638 } 6639 } 6640 6641 /* Process any deferred work. */ 6642 if (!list_empty(&vha->work_list)) { 6643 unsigned long flags; 6644 bool q = false; 6645 6646 spin_lock_irqsave(&vha->work_lock, flags); 6647 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 6648 q = true; 6649 spin_unlock_irqrestore(&vha->work_lock, flags); 6650 if (q) 6651 queue_work(vha->hw->wq, &vha->iocb_work); 6652 } 6653 6654 /* 6655 * FC-NVME 6656 * see if the active AEN count has changed from what was last reported. 6657 */ 6658 if (!vha->vp_idx && 6659 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) && 6660 ha->zio_mode == QLA_ZIO_MODE_6 && 6661 !ha->flags.host_shutting_down) { 6662 ql_log(ql_log_info, vha, 0x3002, 6663 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 6664 ha->nvme_last_rptd_aen); 6665 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 6666 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6667 start_dpc++; 6668 } 6669 6670 if (!vha->vp_idx && 6671 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) && 6672 (ha->zio_mode == QLA_ZIO_MODE_6) && 6673 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) { 6674 ql_log(ql_log_info, vha, 0x3002, 6675 "Sched: Set ZIO exchange threshold to %d.\n", 6676 ha->last_zio_threshold); 6677 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 6678 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 6679 start_dpc++; 6680 } 6681 6682 /* Schedule the DPC routine if needed */ 6683 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 6684 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 6685 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 6686 start_dpc || 6687 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 6688 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 6689 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 6690 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 6691 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 6692 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { 6693 ql_dbg(ql_dbg_timer, vha, 0x600b, 6694 "isp_abort_needed=%d loop_resync_needed=%d " 6695 "fcport_update_needed=%d start_dpc=%d " 6696 "reset_marker_needed=%d", 6697 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 6698 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 6699 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 6700 start_dpc, 6701 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 6702 ql_dbg(ql_dbg_timer, vha, 0x600c, 6703 "beacon_blink_needed=%d isp_unrecoverable=%d " 6704 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 6705 "relogin_needed=%d.\n", 6706 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 6707 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 6708 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 6709 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 6710 test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); 6711 qla2xxx_wake_dpc(vha); 6712 } 6713 6714 qla2x00_restart_timer(vha, WATCH_INTERVAL); 6715 } 6716 6717 /* Firmware interface routines. */ 6718 6719 #define FW_ISP21XX 0 6720 #define FW_ISP22XX 1 6721 #define FW_ISP2300 2 6722 #define FW_ISP2322 3 6723 #define FW_ISP24XX 4 6724 #define FW_ISP25XX 5 6725 #define FW_ISP81XX 6 6726 #define FW_ISP82XX 7 6727 #define FW_ISP2031 8 6728 #define FW_ISP8031 9 6729 #define FW_ISP27XX 10 6730 #define FW_ISP28XX 11 6731 6732 #define FW_FILE_ISP21XX "ql2100_fw.bin" 6733 #define FW_FILE_ISP22XX "ql2200_fw.bin" 6734 #define FW_FILE_ISP2300 "ql2300_fw.bin" 6735 #define FW_FILE_ISP2322 "ql2322_fw.bin" 6736 #define FW_FILE_ISP24XX "ql2400_fw.bin" 6737 #define FW_FILE_ISP25XX "ql2500_fw.bin" 6738 #define FW_FILE_ISP81XX "ql8100_fw.bin" 6739 #define FW_FILE_ISP82XX "ql8200_fw.bin" 6740 #define FW_FILE_ISP2031 "ql2600_fw.bin" 6741 #define FW_FILE_ISP8031 "ql8300_fw.bin" 6742 #define FW_FILE_ISP27XX "ql2700_fw.bin" 6743 #define FW_FILE_ISP28XX "ql2800_fw.bin" 6744 6745 6746 static DEFINE_MUTEX(qla_fw_lock); 6747 6748 static struct fw_blob qla_fw_blobs[] = { 6749 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 6750 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 6751 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 6752 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 6753 { .name = FW_FILE_ISP24XX, }, 6754 { .name = FW_FILE_ISP25XX, }, 6755 { .name = FW_FILE_ISP81XX, }, 6756 { .name = FW_FILE_ISP82XX, }, 6757 { .name = FW_FILE_ISP2031, }, 6758 { .name = FW_FILE_ISP8031, }, 6759 { .name = FW_FILE_ISP27XX, }, 6760 { .name = FW_FILE_ISP28XX, }, 6761 { .name = NULL, }, 6762 }; 6763 6764 struct fw_blob * 6765 qla2x00_request_firmware(scsi_qla_host_t *vha) 6766 { 6767 struct qla_hw_data *ha = vha->hw; 6768 struct fw_blob *blob; 6769 6770 if (IS_QLA2100(ha)) { 6771 blob = &qla_fw_blobs[FW_ISP21XX]; 6772 } else if (IS_QLA2200(ha)) { 6773 blob = &qla_fw_blobs[FW_ISP22XX]; 6774 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 6775 blob = &qla_fw_blobs[FW_ISP2300]; 6776 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 6777 blob = &qla_fw_blobs[FW_ISP2322]; 6778 } else if (IS_QLA24XX_TYPE(ha)) { 6779 blob = &qla_fw_blobs[FW_ISP24XX]; 6780 } else if (IS_QLA25XX(ha)) { 6781 blob = &qla_fw_blobs[FW_ISP25XX]; 6782 } else if (IS_QLA81XX(ha)) { 6783 blob = &qla_fw_blobs[FW_ISP81XX]; 6784 } else if (IS_QLA82XX(ha)) { 6785 blob = &qla_fw_blobs[FW_ISP82XX]; 6786 } else if (IS_QLA2031(ha)) { 6787 blob = &qla_fw_blobs[FW_ISP2031]; 6788 } else if (IS_QLA8031(ha)) { 6789 blob = &qla_fw_blobs[FW_ISP8031]; 6790 } else if (IS_QLA27XX(ha)) { 6791 blob = &qla_fw_blobs[FW_ISP27XX]; 6792 } else if (IS_QLA28XX(ha)) { 6793 blob = &qla_fw_blobs[FW_ISP28XX]; 6794 } else { 6795 return NULL; 6796 } 6797 6798 if (!blob->name) 6799 return NULL; 6800 6801 mutex_lock(&qla_fw_lock); 6802 if (blob->fw) 6803 goto out; 6804 6805 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 6806 ql_log(ql_log_warn, vha, 0x0063, 6807 "Failed to load firmware image (%s).\n", blob->name); 6808 blob->fw = NULL; 6809 blob = NULL; 6810 } 6811 6812 out: 6813 mutex_unlock(&qla_fw_lock); 6814 return blob; 6815 } 6816 6817 static void 6818 qla2x00_release_firmware(void) 6819 { 6820 struct fw_blob *blob; 6821 6822 mutex_lock(&qla_fw_lock); 6823 for (blob = qla_fw_blobs; blob->name; blob++) 6824 release_firmware(blob->fw); 6825 mutex_unlock(&qla_fw_lock); 6826 } 6827 6828 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 6829 { 6830 struct qla_hw_data *ha = vha->hw; 6831 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6832 struct qla_qpair *qpair = NULL; 6833 struct scsi_qla_host *vp; 6834 fc_port_t *fcport; 6835 int i; 6836 unsigned long flags; 6837 6838 ha->chip_reset++; 6839 6840 ha->base_qpair->chip_reset = ha->chip_reset; 6841 for (i = 0; i < ha->max_qpairs; i++) { 6842 if (ha->queue_pair_map[i]) 6843 ha->queue_pair_map[i]->chip_reset = 6844 ha->base_qpair->chip_reset; 6845 } 6846 6847 /* purge MBox commands */ 6848 if (atomic_read(&ha->num_pend_mbx_stage3)) { 6849 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 6850 complete(&ha->mbx_intr_comp); 6851 } 6852 6853 i = 0; 6854 6855 while (atomic_read(&ha->num_pend_mbx_stage3) || 6856 atomic_read(&ha->num_pend_mbx_stage2) || 6857 atomic_read(&ha->num_pend_mbx_stage1)) { 6858 msleep(20); 6859 i++; 6860 if (i > 50) 6861 break; 6862 } 6863 6864 ha->flags.purge_mbox = 0; 6865 6866 mutex_lock(&ha->mq_lock); 6867 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 6868 qpair->online = 0; 6869 mutex_unlock(&ha->mq_lock); 6870 6871 qla2x00_mark_all_devices_lost(vha, 0); 6872 6873 spin_lock_irqsave(&ha->vport_slock, flags); 6874 list_for_each_entry(vp, &ha->vp_list, list) { 6875 atomic_inc(&vp->vref_count); 6876 spin_unlock_irqrestore(&ha->vport_slock, flags); 6877 qla2x00_mark_all_devices_lost(vp, 0); 6878 spin_lock_irqsave(&ha->vport_slock, flags); 6879 atomic_dec(&vp->vref_count); 6880 } 6881 spin_unlock_irqrestore(&ha->vport_slock, flags); 6882 6883 /* Clear all async request states across all VPs. */ 6884 list_for_each_entry(fcport, &vha->vp_fcports, list) 6885 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6886 6887 spin_lock_irqsave(&ha->vport_slock, flags); 6888 list_for_each_entry(vp, &ha->vp_list, list) { 6889 atomic_inc(&vp->vref_count); 6890 spin_unlock_irqrestore(&ha->vport_slock, flags); 6891 list_for_each_entry(fcport, &vp->vp_fcports, list) 6892 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6893 spin_lock_irqsave(&ha->vport_slock, flags); 6894 atomic_dec(&vp->vref_count); 6895 } 6896 spin_unlock_irqrestore(&ha->vport_slock, flags); 6897 } 6898 6899 6900 static pci_ers_result_t 6901 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 6902 { 6903 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 6904 struct qla_hw_data *ha = vha->hw; 6905 6906 ql_dbg(ql_dbg_aer, vha, 0x9000, 6907 "PCI error detected, state %x.\n", state); 6908 6909 if (!atomic_read(&pdev->enable_cnt)) { 6910 ql_log(ql_log_info, vha, 0xffff, 6911 "PCI device is disabled,state %x\n", state); 6912 return PCI_ERS_RESULT_NEED_RESET; 6913 } 6914 6915 switch (state) { 6916 case pci_channel_io_normal: 6917 ha->flags.eeh_busy = 0; 6918 if (ql2xmqsupport || ql2xnvmeenable) { 6919 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6920 qla2xxx_wake_dpc(vha); 6921 } 6922 return PCI_ERS_RESULT_CAN_RECOVER; 6923 case pci_channel_io_frozen: 6924 ha->flags.eeh_busy = 1; 6925 qla_pci_error_cleanup(vha); 6926 return PCI_ERS_RESULT_NEED_RESET; 6927 case pci_channel_io_perm_failure: 6928 ha->flags.pci_channel_io_perm_failure = 1; 6929 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 6930 if (ql2xmqsupport || ql2xnvmeenable) { 6931 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 6932 qla2xxx_wake_dpc(vha); 6933 } 6934 return PCI_ERS_RESULT_DISCONNECT; 6935 } 6936 return PCI_ERS_RESULT_NEED_RESET; 6937 } 6938 6939 static pci_ers_result_t 6940 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 6941 { 6942 int risc_paused = 0; 6943 uint32_t stat; 6944 unsigned long flags; 6945 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6946 struct qla_hw_data *ha = base_vha->hw; 6947 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 6948 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 6949 6950 if (IS_QLA82XX(ha)) 6951 return PCI_ERS_RESULT_RECOVERED; 6952 6953 spin_lock_irqsave(&ha->hardware_lock, flags); 6954 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 6955 stat = RD_REG_DWORD(®->hccr); 6956 if (stat & HCCR_RISC_PAUSE) 6957 risc_paused = 1; 6958 } else if (IS_QLA23XX(ha)) { 6959 stat = RD_REG_DWORD(®->u.isp2300.host_status); 6960 if (stat & HSR_RISC_PAUSED) 6961 risc_paused = 1; 6962 } else if (IS_FWI2_CAPABLE(ha)) { 6963 stat = RD_REG_DWORD(®24->host_status); 6964 if (stat & HSRX_RISC_PAUSED) 6965 risc_paused = 1; 6966 } 6967 spin_unlock_irqrestore(&ha->hardware_lock, flags); 6968 6969 if (risc_paused) { 6970 ql_log(ql_log_info, base_vha, 0x9003, 6971 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 6972 ha->isp_ops->fw_dump(base_vha, 0); 6973 6974 return PCI_ERS_RESULT_NEED_RESET; 6975 } else 6976 return PCI_ERS_RESULT_RECOVERED; 6977 } 6978 6979 static pci_ers_result_t 6980 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 6981 { 6982 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 6983 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 6984 struct qla_hw_data *ha = base_vha->hw; 6985 int rc; 6986 struct qla_qpair *qpair = NULL; 6987 6988 ql_dbg(ql_dbg_aer, base_vha, 0x9004, 6989 "Slot Reset.\n"); 6990 6991 /* Workaround: qla2xxx driver which access hardware earlier 6992 * needs error state to be pci_channel_io_online. 6993 * Otherwise mailbox command timesout. 6994 */ 6995 pdev->error_state = pci_channel_io_normal; 6996 6997 pci_restore_state(pdev); 6998 6999 /* pci_restore_state() clears the saved_state flag of the device 7000 * save restored state which resets saved_state flag 7001 */ 7002 pci_save_state(pdev); 7003 7004 if (ha->mem_only) 7005 rc = pci_enable_device_mem(pdev); 7006 else 7007 rc = pci_enable_device(pdev); 7008 7009 if (rc) { 7010 ql_log(ql_log_warn, base_vha, 0x9005, 7011 "Can't re-enable PCI device after reset.\n"); 7012 goto exit_slot_reset; 7013 } 7014 7015 7016 if (ha->isp_ops->pci_config(base_vha)) 7017 goto exit_slot_reset; 7018 7019 mutex_lock(&ha->mq_lock); 7020 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7021 qpair->online = 1; 7022 mutex_unlock(&ha->mq_lock); 7023 7024 base_vha->flags.online = 1; 7025 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7026 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) 7027 ret = PCI_ERS_RESULT_RECOVERED; 7028 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7029 7030 7031 exit_slot_reset: 7032 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7033 "slot_reset return %x.\n", ret); 7034 7035 return ret; 7036 } 7037 7038 static void 7039 qla2xxx_pci_resume(struct pci_dev *pdev) 7040 { 7041 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7042 struct qla_hw_data *ha = base_vha->hw; 7043 int ret; 7044 7045 ql_dbg(ql_dbg_aer, base_vha, 0x900f, 7046 "pci_resume.\n"); 7047 7048 ha->flags.eeh_busy = 0; 7049 7050 ret = qla2x00_wait_for_hba_online(base_vha); 7051 if (ret != QLA_SUCCESS) { 7052 ql_log(ql_log_fatal, base_vha, 0x9002, 7053 "The device failed to resume I/O from slot/link_reset.\n"); 7054 } 7055 } 7056 7057 static void 7058 qla_pci_reset_prepare(struct pci_dev *pdev) 7059 { 7060 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7061 struct qla_hw_data *ha = base_vha->hw; 7062 struct qla_qpair *qpair; 7063 7064 ql_log(ql_log_warn, base_vha, 0xffff, 7065 "%s.\n", __func__); 7066 7067 /* 7068 * PCI FLR/function reset is about to reset the 7069 * slot. Stop the chip to stop all DMA access. 7070 * It is assumed that pci_reset_done will be called 7071 * after FLR to resume Chip operation. 7072 */ 7073 ha->flags.eeh_busy = 1; 7074 mutex_lock(&ha->mq_lock); 7075 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7076 qpair->online = 0; 7077 mutex_unlock(&ha->mq_lock); 7078 7079 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7080 qla2x00_abort_isp_cleanup(base_vha); 7081 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7082 } 7083 7084 static void 7085 qla_pci_reset_done(struct pci_dev *pdev) 7086 { 7087 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7088 struct qla_hw_data *ha = base_vha->hw; 7089 struct qla_qpair *qpair; 7090 7091 ql_log(ql_log_warn, base_vha, 0xffff, 7092 "%s.\n", __func__); 7093 7094 /* 7095 * FLR just completed by PCI layer. Resume adapter 7096 */ 7097 ha->flags.eeh_busy = 0; 7098 mutex_lock(&ha->mq_lock); 7099 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7100 qpair->online = 1; 7101 mutex_unlock(&ha->mq_lock); 7102 7103 base_vha->flags.online = 1; 7104 ha->isp_ops->abort_isp(base_vha); 7105 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7106 } 7107 7108 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7109 { 7110 int rc; 7111 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7112 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7113 7114 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7115 rc = blk_mq_map_queues(qmap); 7116 else 7117 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7118 return rc; 7119 } 7120 7121 struct scsi_host_template qla2xxx_driver_template = { 7122 .module = THIS_MODULE, 7123 .name = QLA2XXX_DRIVER_NAME, 7124 .queuecommand = qla2xxx_queuecommand, 7125 7126 .eh_timed_out = fc_eh_timed_out, 7127 .eh_abort_handler = qla2xxx_eh_abort, 7128 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7129 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7130 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7131 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7132 7133 .slave_configure = qla2xxx_slave_configure, 7134 7135 .slave_alloc = qla2xxx_slave_alloc, 7136 .slave_destroy = qla2xxx_slave_destroy, 7137 .scan_finished = qla2xxx_scan_finished, 7138 .scan_start = qla2xxx_scan_start, 7139 .change_queue_depth = scsi_change_queue_depth, 7140 .map_queues = qla2xxx_map_queues, 7141 .this_id = -1, 7142 .cmd_per_lun = 3, 7143 .sg_tablesize = SG_ALL, 7144 7145 .max_sectors = 0xFFFF, 7146 .shost_attrs = qla2x00_host_attrs, 7147 7148 .supported_mode = MODE_INITIATOR, 7149 .track_queue_depth = 1, 7150 }; 7151 7152 static const struct pci_error_handlers qla2xxx_err_handler = { 7153 .error_detected = qla2xxx_pci_error_detected, 7154 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7155 .slot_reset = qla2xxx_pci_slot_reset, 7156 .resume = qla2xxx_pci_resume, 7157 .reset_prepare = qla_pci_reset_prepare, 7158 .reset_done = qla_pci_reset_done, 7159 }; 7160 7161 static struct pci_device_id qla2xxx_pci_tbl[] = { 7162 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7163 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7164 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7165 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7166 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7167 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7168 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7169 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7170 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7171 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7172 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7173 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7174 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7175 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7176 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7177 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7178 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7179 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7180 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7181 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7182 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7183 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7184 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 7185 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 7186 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 7187 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 7188 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 7189 { 0 }, 7190 }; 7191 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7192 7193 static struct pci_driver qla2xxx_pci_driver = { 7194 .name = QLA2XXX_DRIVER_NAME, 7195 .driver = { 7196 .owner = THIS_MODULE, 7197 }, 7198 .id_table = qla2xxx_pci_tbl, 7199 .probe = qla2x00_probe_one, 7200 .remove = qla2x00_remove_one, 7201 .shutdown = qla2x00_shutdown, 7202 .err_handler = &qla2xxx_err_handler, 7203 }; 7204 7205 static const struct file_operations apidev_fops = { 7206 .owner = THIS_MODULE, 7207 .llseek = noop_llseek, 7208 }; 7209 7210 /** 7211 * qla2x00_module_init - Module initialization. 7212 **/ 7213 static int __init 7214 qla2x00_module_init(void) 7215 { 7216 int ret = 0; 7217 7218 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 7219 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 7220 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 7221 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 7222 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 7223 BUILD_BUG_ON(sizeof(request_t) != 64); 7224 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 7225 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 7226 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 7227 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 7228 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 7229 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 7230 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 7231 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 7232 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 7233 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 7234 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 7235 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 7236 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 7237 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 7238 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 7239 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 7240 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 7241 7242 /* Allocate cache for SRBs. */ 7243 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 7244 SLAB_HWCACHE_ALIGN, NULL); 7245 if (srb_cachep == NULL) { 7246 ql_log(ql_log_fatal, NULL, 0x0001, 7247 "Unable to allocate SRB cache...Failing load!.\n"); 7248 return -ENOMEM; 7249 } 7250 7251 /* Initialize target kmem_cache and mem_pools */ 7252 ret = qlt_init(); 7253 if (ret < 0) { 7254 goto destroy_cache; 7255 } else if (ret > 0) { 7256 /* 7257 * If initiator mode is explictly disabled by qlt_init(), 7258 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 7259 * performing scsi_scan_target() during LOOP UP event. 7260 */ 7261 qla2xxx_transport_functions.disable_target_scan = 1; 7262 qla2xxx_transport_vport_functions.disable_target_scan = 1; 7263 } 7264 7265 /* Derive version string. */ 7266 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 7267 if (ql2xextended_error_logging) 7268 strcat(qla2x00_version_str, "-debug"); 7269 if (ql2xextended_error_logging == 1) 7270 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 7271 7272 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL) 7273 qla_insert_tgt_attrs(); 7274 7275 qla2xxx_transport_template = 7276 fc_attach_transport(&qla2xxx_transport_functions); 7277 if (!qla2xxx_transport_template) { 7278 ql_log(ql_log_fatal, NULL, 0x0002, 7279 "fc_attach_transport failed...Failing load!.\n"); 7280 ret = -ENODEV; 7281 goto qlt_exit; 7282 } 7283 7284 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 7285 if (apidev_major < 0) { 7286 ql_log(ql_log_fatal, NULL, 0x0003, 7287 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 7288 } 7289 7290 qla2xxx_transport_vport_template = 7291 fc_attach_transport(&qla2xxx_transport_vport_functions); 7292 if (!qla2xxx_transport_vport_template) { 7293 ql_log(ql_log_fatal, NULL, 0x0004, 7294 "fc_attach_transport vport failed...Failing load!.\n"); 7295 ret = -ENODEV; 7296 goto unreg_chrdev; 7297 } 7298 ql_log(ql_log_info, NULL, 0x0005, 7299 "QLogic Fibre Channel HBA Driver: %s.\n", 7300 qla2x00_version_str); 7301 ret = pci_register_driver(&qla2xxx_pci_driver); 7302 if (ret) { 7303 ql_log(ql_log_fatal, NULL, 0x0006, 7304 "pci_register_driver failed...ret=%d Failing load!.\n", 7305 ret); 7306 goto release_vport_transport; 7307 } 7308 return ret; 7309 7310 release_vport_transport: 7311 fc_release_transport(qla2xxx_transport_vport_template); 7312 7313 unreg_chrdev: 7314 if (apidev_major >= 0) 7315 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7316 fc_release_transport(qla2xxx_transport_template); 7317 7318 qlt_exit: 7319 qlt_exit(); 7320 7321 destroy_cache: 7322 kmem_cache_destroy(srb_cachep); 7323 return ret; 7324 } 7325 7326 /** 7327 * qla2x00_module_exit - Module cleanup. 7328 **/ 7329 static void __exit 7330 qla2x00_module_exit(void) 7331 { 7332 pci_unregister_driver(&qla2xxx_pci_driver); 7333 qla2x00_release_firmware(); 7334 kmem_cache_destroy(ctx_cachep); 7335 fc_release_transport(qla2xxx_transport_vport_template); 7336 if (apidev_major >= 0) 7337 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7338 fc_release_transport(qla2xxx_transport_template); 7339 qlt_exit(); 7340 kmem_cache_destroy(srb_cachep); 7341 } 7342 7343 module_init(qla2x00_module_init); 7344 module_exit(qla2x00_module_exit); 7345 7346 MODULE_AUTHOR("QLogic Corporation"); 7347 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 7348 MODULE_LICENSE("GPL"); 7349 MODULE_VERSION(QLA2XXX_VERSION); 7350 MODULE_FIRMWARE(FW_FILE_ISP21XX); 7351 MODULE_FIRMWARE(FW_FILE_ISP22XX); 7352 MODULE_FIRMWARE(FW_FILE_ISP2300); 7353 MODULE_FIRMWARE(FW_FILE_ISP2322); 7354 MODULE_FIRMWARE(FW_FILE_ISP24XX); 7355 MODULE_FIRMWARE(FW_FILE_ISP25XX); 7356