1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/moduleparam.h> 9 #include <linux/vmalloc.h> 10 #include <linux/delay.h> 11 #include <linux/kthread.h> 12 #include <linux/mutex.h> 13 #include <linux/kobject.h> 14 #include <linux/slab.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/refcount.h> 17 18 #include <scsi/scsi_tcq.h> 19 #include <scsi/scsicam.h> 20 #include <scsi/scsi_transport.h> 21 #include <scsi/scsi_transport_fc.h> 22 23 #include "qla_target.h" 24 25 /* 26 * Driver version 27 */ 28 char qla2x00_version_str[40]; 29 30 static int apidev_major; 31 32 /* 33 * SRB allocation cache 34 */ 35 struct kmem_cache *srb_cachep; 36 37 int ql2xfulldump_on_mpifail; 38 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 39 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 40 "Set this to take full dump on MPI hang."); 41 42 int ql2xenforce_iocb_limit = 1; 43 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 44 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 45 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)"); 46 47 /* 48 * CT6 CTX allocation cache 49 */ 50 static struct kmem_cache *ctx_cachep; 51 /* 52 * error level for logging 53 */ 54 uint ql_errlev = 0x8001; 55 56 static int ql2xenableclass2; 57 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 58 MODULE_PARM_DESC(ql2xenableclass2, 59 "Specify if Class 2 operations are supported from the very " 60 "beginning. Default is 0 - class 2 not supported."); 61 62 63 int ql2xlogintimeout = 20; 64 module_param(ql2xlogintimeout, int, S_IRUGO); 65 MODULE_PARM_DESC(ql2xlogintimeout, 66 "Login timeout value in seconds."); 67 68 int qlport_down_retry; 69 module_param(qlport_down_retry, int, S_IRUGO); 70 MODULE_PARM_DESC(qlport_down_retry, 71 "Maximum number of command retries to a port that returns " 72 "a PORT-DOWN status."); 73 74 int ql2xplogiabsentdevice; 75 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 76 MODULE_PARM_DESC(ql2xplogiabsentdevice, 77 "Option to enable PLOGI to devices that are not present after " 78 "a Fabric scan. This is needed for several broken switches. " 79 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 80 81 int ql2xloginretrycount; 82 module_param(ql2xloginretrycount, int, S_IRUGO); 83 MODULE_PARM_DESC(ql2xloginretrycount, 84 "Specify an alternate value for the NVRAM login retry count."); 85 86 int ql2xallocfwdump = 1; 87 module_param(ql2xallocfwdump, int, S_IRUGO); 88 MODULE_PARM_DESC(ql2xallocfwdump, 89 "Option to enable allocation of memory for a firmware dump " 90 "during HBA initialization. Memory allocation requirements " 91 "vary by ISP type. Default is 1 - allocate memory."); 92 93 int ql2xextended_error_logging; 94 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 95 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 96 MODULE_PARM_DESC(ql2xextended_error_logging, 97 "Option to enable extended error logging,\n" 98 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 99 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 100 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 101 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 102 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 103 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 104 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 105 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 106 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 107 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 108 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 109 "\t\t0x1e400000 - Preferred value for capturing essential " 110 "debug information (equivalent to old " 111 "ql2xextended_error_logging=1).\n" 112 "\t\tDo LOGICAL OR of the value to enable more than one level"); 113 114 int ql2xshiftctondsd = 6; 115 module_param(ql2xshiftctondsd, int, S_IRUGO); 116 MODULE_PARM_DESC(ql2xshiftctondsd, 117 "Set to control shifting of command type processing " 118 "based on total number of SG elements."); 119 120 int ql2xfdmienable = 1; 121 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 122 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 123 MODULE_PARM_DESC(ql2xfdmienable, 124 "Enables FDMI registrations. " 125 "0 - no FDMI registrations. " 126 "1 - provide FDMI registrations (default)."); 127 128 #define MAX_Q_DEPTH 64 129 static int ql2xmaxqdepth = MAX_Q_DEPTH; 130 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 131 MODULE_PARM_DESC(ql2xmaxqdepth, 132 "Maximum queue depth to set for each LUN. " 133 "Default is 64."); 134 135 int ql2xenabledif = 2; 136 module_param(ql2xenabledif, int, S_IRUGO); 137 MODULE_PARM_DESC(ql2xenabledif, 138 " Enable T10-CRC-DIF:\n" 139 " Default is 2.\n" 140 " 0 -- No DIF Support\n" 141 " 1 -- Enable DIF for all types\n" 142 " 2 -- Enable DIF for all types, except Type 0.\n"); 143 144 #if (IS_ENABLED(CONFIG_NVME_FC)) 145 int ql2xnvmeenable = 1; 146 #else 147 int ql2xnvmeenable; 148 #endif 149 module_param(ql2xnvmeenable, int, 0644); 150 MODULE_PARM_DESC(ql2xnvmeenable, 151 "Enables NVME support. " 152 "0 - no NVMe. Default is Y"); 153 154 int ql2xenablehba_err_chk = 2; 155 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 156 MODULE_PARM_DESC(ql2xenablehba_err_chk, 157 " Enable T10-CRC-DIF Error isolation by HBA:\n" 158 " Default is 2.\n" 159 " 0 -- Error isolation disabled\n" 160 " 1 -- Error isolation enabled only for DIX Type 0\n" 161 " 2 -- Error isolation enabled for all Types\n"); 162 163 int ql2xiidmaenable = 1; 164 module_param(ql2xiidmaenable, int, S_IRUGO); 165 MODULE_PARM_DESC(ql2xiidmaenable, 166 "Enables iIDMA settings " 167 "Default is 1 - perform iIDMA. 0 - no iIDMA."); 168 169 int ql2xmqsupport = 1; 170 module_param(ql2xmqsupport, int, S_IRUGO); 171 MODULE_PARM_DESC(ql2xmqsupport, 172 "Enable on demand multiple queue pairs support " 173 "Default is 1 for supported. " 174 "Set it to 0 to turn off mq qpair support."); 175 176 int ql2xfwloadbin; 177 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 178 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 179 MODULE_PARM_DESC(ql2xfwloadbin, 180 "Option to specify location from which to load ISP firmware:.\n" 181 " 2 -- load firmware via the request_firmware() (hotplug).\n" 182 " interface.\n" 183 " 1 -- load firmware from flash.\n" 184 " 0 -- use default semantics.\n"); 185 186 int ql2xetsenable; 187 module_param(ql2xetsenable, int, S_IRUGO); 188 MODULE_PARM_DESC(ql2xetsenable, 189 "Enables firmware ETS burst." 190 "Default is 0 - skip ETS enablement."); 191 192 int ql2xdbwr = 1; 193 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 194 MODULE_PARM_DESC(ql2xdbwr, 195 "Option to specify scheme for request queue posting.\n" 196 " 0 -- Regular doorbell.\n" 197 " 1 -- CAMRAM doorbell (faster).\n"); 198 199 int ql2xtargetreset = 1; 200 module_param(ql2xtargetreset, int, S_IRUGO); 201 MODULE_PARM_DESC(ql2xtargetreset, 202 "Enable target reset." 203 "Default is 1 - use hw defaults."); 204 205 int ql2xgffidenable; 206 module_param(ql2xgffidenable, int, S_IRUGO); 207 MODULE_PARM_DESC(ql2xgffidenable, 208 "Enables GFF_ID checks of port type. " 209 "Default is 0 - Do not use GFF_ID information."); 210 211 int ql2xasynctmfenable = 1; 212 module_param(ql2xasynctmfenable, int, S_IRUGO); 213 MODULE_PARM_DESC(ql2xasynctmfenable, 214 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 215 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 216 217 int ql2xdontresethba; 218 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 219 MODULE_PARM_DESC(ql2xdontresethba, 220 "Option to specify reset behaviour.\n" 221 " 0 (Default) -- Reset on failure.\n" 222 " 1 -- Do not reset on failure.\n"); 223 224 uint64_t ql2xmaxlun = MAX_LUNS; 225 module_param(ql2xmaxlun, ullong, S_IRUGO); 226 MODULE_PARM_DESC(ql2xmaxlun, 227 "Defines the maximum LU number to register with the SCSI " 228 "midlayer. Default is 65535."); 229 230 int ql2xmdcapmask = 0x1F; 231 module_param(ql2xmdcapmask, int, S_IRUGO); 232 MODULE_PARM_DESC(ql2xmdcapmask, 233 "Set the Minidump driver capture mask level. " 234 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 235 236 int ql2xmdenable = 1; 237 module_param(ql2xmdenable, int, S_IRUGO); 238 MODULE_PARM_DESC(ql2xmdenable, 239 "Enable/disable MiniDump. " 240 "0 - MiniDump disabled. " 241 "1 (Default) - MiniDump enabled."); 242 243 int ql2xexlogins; 244 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 245 MODULE_PARM_DESC(ql2xexlogins, 246 "Number of extended Logins. " 247 "0 (Default)- Disabled."); 248 249 int ql2xexchoffld = 1024; 250 module_param(ql2xexchoffld, uint, 0644); 251 MODULE_PARM_DESC(ql2xexchoffld, 252 "Number of target exchanges."); 253 254 int ql2xiniexchg = 1024; 255 module_param(ql2xiniexchg, uint, 0644); 256 MODULE_PARM_DESC(ql2xiniexchg, 257 "Number of initiator exchanges."); 258 259 int ql2xfwholdabts; 260 module_param(ql2xfwholdabts, int, S_IRUGO); 261 MODULE_PARM_DESC(ql2xfwholdabts, 262 "Allow FW to hold status IOCB until ABTS rsp received. " 263 "0 (Default) Do not set fw option. " 264 "1 - Set fw option to hold ABTS."); 265 266 int ql2xmvasynctoatio = 1; 267 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 268 MODULE_PARM_DESC(ql2xmvasynctoatio, 269 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 270 "0 (Default). Do not move IOCBs" 271 "1 - Move IOCBs."); 272 273 int ql2xautodetectsfp = 1; 274 module_param(ql2xautodetectsfp, int, 0444); 275 MODULE_PARM_DESC(ql2xautodetectsfp, 276 "Detect SFP range and set appropriate distance.\n" 277 "1 (Default): Enable\n"); 278 279 int ql2xenablemsix = 1; 280 module_param(ql2xenablemsix, int, 0444); 281 MODULE_PARM_DESC(ql2xenablemsix, 282 "Set to enable MSI or MSI-X interrupt mechanism.\n" 283 " Default is 1, enable MSI-X interrupt mechanism.\n" 284 " 0 -- enable traditional pin-based mechanism.\n" 285 " 1 -- enable MSI-X interrupt mechanism.\n" 286 " 2 -- enable MSI interrupt mechanism.\n"); 287 288 int qla2xuseresexchforels; 289 module_param(qla2xuseresexchforels, int, 0444); 290 MODULE_PARM_DESC(qla2xuseresexchforels, 291 "Reserve 1/2 of emergency exchanges for ELS.\n" 292 " 0 (default): disabled"); 293 294 static int ql2xprotmask; 295 module_param(ql2xprotmask, int, 0644); 296 MODULE_PARM_DESC(ql2xprotmask, 297 "Override DIF/DIX protection capabilities mask\n" 298 "Default is 0 which sets protection mask based on " 299 "capabilities reported by HBA firmware.\n"); 300 301 static int ql2xprotguard; 302 module_param(ql2xprotguard, int, 0644); 303 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 304 " 0 -- Let HBA firmware decide\n" 305 " 1 -- Force T10 CRC\n" 306 " 2 -- Force IP checksum\n"); 307 308 int ql2xdifbundlinginternalbuffers; 309 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 310 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 311 "Force using internal buffers for DIF information\n" 312 "0 (Default). Based on check.\n" 313 "1 Force using internal buffers\n"); 314 315 int ql2xsmartsan; 316 module_param(ql2xsmartsan, int, 0444); 317 module_param_named(smartsan, ql2xsmartsan, int, 0444); 318 MODULE_PARM_DESC(ql2xsmartsan, 319 "Send SmartSAN Management Attributes for FDMI Registration." 320 " Default is 0 - No SmartSAN registration," 321 " 1 - Register SmartSAN Management Attributes."); 322 323 int ql2xrdpenable; 324 module_param(ql2xrdpenable, int, 0444); 325 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 326 MODULE_PARM_DESC(ql2xrdpenable, 327 "Enables RDP responses. " 328 "0 - no RDP responses (default). " 329 "1 - provide RDP responses."); 330 int ql2xabts_wait_nvme = 1; 331 module_param(ql2xabts_wait_nvme, int, 0444); 332 MODULE_PARM_DESC(ql2xabts_wait_nvme, 333 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 334 335 336 static void qla2x00_clear_drv_active(struct qla_hw_data *); 337 static void qla2x00_free_device(scsi_qla_host_t *); 338 static int qla2xxx_map_queues(struct Scsi_Host *shost); 339 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 340 341 342 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 343 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 344 345 /* TODO Convert to inlines 346 * 347 * Timer routines 348 */ 349 350 __inline__ void 351 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 352 { 353 timer_setup(&vha->timer, qla2x00_timer, 0); 354 vha->timer.expires = jiffies + interval * HZ; 355 add_timer(&vha->timer); 356 vha->timer_active = 1; 357 } 358 359 static inline void 360 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 361 { 362 /* Currently used for 82XX only. */ 363 if (vha->device_flags & DFLG_DEV_FAILED) { 364 ql_dbg(ql_dbg_timer, vha, 0x600d, 365 "Device in a failed state, returning.\n"); 366 return; 367 } 368 369 mod_timer(&vha->timer, jiffies + interval * HZ); 370 } 371 372 static __inline__ void 373 qla2x00_stop_timer(scsi_qla_host_t *vha) 374 { 375 del_timer_sync(&vha->timer); 376 vha->timer_active = 0; 377 } 378 379 static int qla2x00_do_dpc(void *data); 380 381 static void qla2x00_rst_aen(scsi_qla_host_t *); 382 383 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 384 struct req_que **, struct rsp_que **); 385 static void qla2x00_free_fw_dump(struct qla_hw_data *); 386 static void qla2x00_mem_free(struct qla_hw_data *); 387 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 388 struct qla_qpair *qpair); 389 390 /* -------------------------------------------------------------------------- */ 391 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 392 struct rsp_que *rsp) 393 { 394 struct qla_hw_data *ha = vha->hw; 395 396 rsp->qpair = ha->base_qpair; 397 rsp->req = req; 398 ha->base_qpair->hw = ha; 399 ha->base_qpair->req = req; 400 ha->base_qpair->rsp = rsp; 401 ha->base_qpair->vha = vha; 402 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 403 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 404 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 405 ha->base_qpair->srb_mempool = ha->srb_mempool; 406 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 407 ha->base_qpair->enable_class_2 = ql2xenableclass2; 408 /* init qpair to this cpu. Will adjust at run time. */ 409 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 410 ha->base_qpair->pdev = ha->pdev; 411 412 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 413 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 414 } 415 416 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 417 struct rsp_que *rsp) 418 { 419 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 420 421 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 422 GFP_KERNEL); 423 if (!ha->req_q_map) { 424 ql_log(ql_log_fatal, vha, 0x003b, 425 "Unable to allocate memory for request queue ptrs.\n"); 426 goto fail_req_map; 427 } 428 429 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 430 GFP_KERNEL); 431 if (!ha->rsp_q_map) { 432 ql_log(ql_log_fatal, vha, 0x003c, 433 "Unable to allocate memory for response queue ptrs.\n"); 434 goto fail_rsp_map; 435 } 436 437 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 438 if (ha->base_qpair == NULL) { 439 ql_log(ql_log_warn, vha, 0x00e0, 440 "Failed to allocate base queue pair memory.\n"); 441 goto fail_base_qpair; 442 } 443 444 qla_init_base_qpair(vha, req, rsp); 445 446 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 447 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 448 GFP_KERNEL); 449 if (!ha->queue_pair_map) { 450 ql_log(ql_log_fatal, vha, 0x0180, 451 "Unable to allocate memory for queue pair ptrs.\n"); 452 goto fail_qpair_map; 453 } 454 } 455 456 /* 457 * Make sure we record at least the request and response queue zero in 458 * case we need to free them if part of the probe fails. 459 */ 460 ha->rsp_q_map[0] = rsp; 461 ha->req_q_map[0] = req; 462 set_bit(0, ha->rsp_qid_map); 463 set_bit(0, ha->req_qid_map); 464 return 0; 465 466 fail_qpair_map: 467 kfree(ha->base_qpair); 468 ha->base_qpair = NULL; 469 fail_base_qpair: 470 kfree(ha->rsp_q_map); 471 ha->rsp_q_map = NULL; 472 fail_rsp_map: 473 kfree(ha->req_q_map); 474 ha->req_q_map = NULL; 475 fail_req_map: 476 return -ENOMEM; 477 } 478 479 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 480 { 481 if (IS_QLAFX00(ha)) { 482 if (req && req->ring_fx00) 483 dma_free_coherent(&ha->pdev->dev, 484 (req->length_fx00 + 1) * sizeof(request_t), 485 req->ring_fx00, req->dma_fx00); 486 } else if (req && req->ring) 487 dma_free_coherent(&ha->pdev->dev, 488 (req->length + 1) * sizeof(request_t), 489 req->ring, req->dma); 490 491 if (req) 492 kfree(req->outstanding_cmds); 493 494 kfree(req); 495 } 496 497 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 498 { 499 if (IS_QLAFX00(ha)) { 500 if (rsp && rsp->ring_fx00) 501 dma_free_coherent(&ha->pdev->dev, 502 (rsp->length_fx00 + 1) * sizeof(request_t), 503 rsp->ring_fx00, rsp->dma_fx00); 504 } else if (rsp && rsp->ring) { 505 dma_free_coherent(&ha->pdev->dev, 506 (rsp->length + 1) * sizeof(response_t), 507 rsp->ring, rsp->dma); 508 } 509 kfree(rsp); 510 } 511 512 static void qla2x00_free_queues(struct qla_hw_data *ha) 513 { 514 struct req_que *req; 515 struct rsp_que *rsp; 516 int cnt; 517 unsigned long flags; 518 519 if (ha->queue_pair_map) { 520 kfree(ha->queue_pair_map); 521 ha->queue_pair_map = NULL; 522 } 523 if (ha->base_qpair) { 524 kfree(ha->base_qpair); 525 ha->base_qpair = NULL; 526 } 527 528 spin_lock_irqsave(&ha->hardware_lock, flags); 529 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 530 if (!test_bit(cnt, ha->req_qid_map)) 531 continue; 532 533 req = ha->req_q_map[cnt]; 534 clear_bit(cnt, ha->req_qid_map); 535 ha->req_q_map[cnt] = NULL; 536 537 spin_unlock_irqrestore(&ha->hardware_lock, flags); 538 qla2x00_free_req_que(ha, req); 539 spin_lock_irqsave(&ha->hardware_lock, flags); 540 } 541 spin_unlock_irqrestore(&ha->hardware_lock, flags); 542 543 kfree(ha->req_q_map); 544 ha->req_q_map = NULL; 545 546 547 spin_lock_irqsave(&ha->hardware_lock, flags); 548 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 549 if (!test_bit(cnt, ha->rsp_qid_map)) 550 continue; 551 552 rsp = ha->rsp_q_map[cnt]; 553 clear_bit(cnt, ha->rsp_qid_map); 554 ha->rsp_q_map[cnt] = NULL; 555 spin_unlock_irqrestore(&ha->hardware_lock, flags); 556 qla2x00_free_rsp_que(ha, rsp); 557 spin_lock_irqsave(&ha->hardware_lock, flags); 558 } 559 spin_unlock_irqrestore(&ha->hardware_lock, flags); 560 561 kfree(ha->rsp_q_map); 562 ha->rsp_q_map = NULL; 563 } 564 565 static char * 566 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 567 { 568 struct qla_hw_data *ha = vha->hw; 569 static const char *const pci_bus_modes[] = { 570 "33", "66", "100", "133", 571 }; 572 uint16_t pci_bus; 573 574 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 575 if (pci_bus) { 576 snprintf(str, str_len, "PCI-X (%s MHz)", 577 pci_bus_modes[pci_bus]); 578 } else { 579 pci_bus = (ha->pci_attr & BIT_8) >> 8; 580 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 581 } 582 583 return str; 584 } 585 586 static char * 587 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 588 { 589 static const char *const pci_bus_modes[] = { 590 "33", "66", "100", "133", 591 }; 592 struct qla_hw_data *ha = vha->hw; 593 uint32_t pci_bus; 594 595 if (pci_is_pcie(ha->pdev)) { 596 uint32_t lstat, lspeed, lwidth; 597 const char *speed_str; 598 599 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 600 lspeed = lstat & PCI_EXP_LNKCAP_SLS; 601 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; 602 603 switch (lspeed) { 604 case 1: 605 speed_str = "2.5GT/s"; 606 break; 607 case 2: 608 speed_str = "5.0GT/s"; 609 break; 610 case 3: 611 speed_str = "8.0GT/s"; 612 break; 613 case 4: 614 speed_str = "16.0GT/s"; 615 break; 616 default: 617 speed_str = "<unknown>"; 618 break; 619 } 620 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 621 622 return str; 623 } 624 625 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 626 if (pci_bus == 0 || pci_bus == 8) 627 snprintf(str, str_len, "PCI (%s MHz)", 628 pci_bus_modes[pci_bus >> 3]); 629 else 630 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 631 pci_bus & 4 ? 2 : 1, 632 pci_bus_modes[pci_bus & 3]); 633 634 return str; 635 } 636 637 static char * 638 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 639 { 640 char un_str[10]; 641 struct qla_hw_data *ha = vha->hw; 642 643 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 644 ha->fw_minor_version, ha->fw_subminor_version); 645 646 if (ha->fw_attributes & BIT_9) { 647 strcat(str, "FLX"); 648 return (str); 649 } 650 651 switch (ha->fw_attributes & 0xFF) { 652 case 0x7: 653 strcat(str, "EF"); 654 break; 655 case 0x17: 656 strcat(str, "TP"); 657 break; 658 case 0x37: 659 strcat(str, "IP"); 660 break; 661 case 0x77: 662 strcat(str, "VI"); 663 break; 664 default: 665 sprintf(un_str, "(%x)", ha->fw_attributes); 666 strcat(str, un_str); 667 break; 668 } 669 if (ha->fw_attributes & 0x100) 670 strcat(str, "X"); 671 672 return (str); 673 } 674 675 static char * 676 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 677 { 678 struct qla_hw_data *ha = vha->hw; 679 680 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 681 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 682 return str; 683 } 684 685 void qla2x00_sp_free_dma(srb_t *sp) 686 { 687 struct qla_hw_data *ha = sp->vha->hw; 688 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 689 690 if (sp->flags & SRB_DMA_VALID) { 691 scsi_dma_unmap(cmd); 692 sp->flags &= ~SRB_DMA_VALID; 693 } 694 695 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 696 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 697 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 698 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 699 } 700 701 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 702 /* List assured to be having elements */ 703 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 704 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 705 } 706 707 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 708 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 709 710 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 711 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 712 } 713 714 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 715 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 716 717 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 718 ctx1->fcp_cmnd_dma); 719 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 720 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 721 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 722 mempool_free(ctx1, ha->ctx_mempool); 723 } 724 } 725 726 void qla2x00_sp_compl(srb_t *sp, int res) 727 { 728 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 729 struct completion *comp = sp->comp; 730 731 sp->free(sp); 732 cmd->result = res; 733 CMD_SP(cmd) = NULL; 734 cmd->scsi_done(cmd); 735 if (comp) 736 complete(comp); 737 } 738 739 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 740 { 741 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 742 struct qla_hw_data *ha = sp->fcport->vha->hw; 743 744 if (sp->flags & SRB_DMA_VALID) { 745 scsi_dma_unmap(cmd); 746 sp->flags &= ~SRB_DMA_VALID; 747 } 748 749 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 750 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 751 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 752 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 753 } 754 755 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 756 /* List assured to be having elements */ 757 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 758 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 759 } 760 761 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 762 struct crc_context *difctx = sp->u.scmd.crc_ctx; 763 struct dsd_dma *dif_dsd, *nxt_dsd; 764 765 list_for_each_entry_safe(dif_dsd, nxt_dsd, 766 &difctx->ldif_dma_hndl_list, list) { 767 list_del(&dif_dsd->list); 768 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 769 dif_dsd->dsd_list_dma); 770 kfree(dif_dsd); 771 difctx->no_dif_bundl--; 772 } 773 774 list_for_each_entry_safe(dif_dsd, nxt_dsd, 775 &difctx->ldif_dsd_list, list) { 776 list_del(&dif_dsd->list); 777 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 778 dif_dsd->dsd_list_dma); 779 kfree(dif_dsd); 780 difctx->no_ldif_dsd--; 781 } 782 783 if (difctx->no_ldif_dsd) { 784 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 785 "%s: difctx->no_ldif_dsd=%x\n", 786 __func__, difctx->no_ldif_dsd); 787 } 788 789 if (difctx->no_dif_bundl) { 790 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 791 "%s: difctx->no_dif_bundl=%x\n", 792 __func__, difctx->no_dif_bundl); 793 } 794 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 795 } 796 797 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 798 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx; 799 800 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 801 ctx1->fcp_cmnd_dma); 802 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); 803 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; 804 ha->gbl_dsd_avail += ctx1->dsd_use_cnt; 805 mempool_free(ctx1, ha->ctx_mempool); 806 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 807 } 808 809 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 810 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 811 812 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 813 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 814 } 815 } 816 817 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 818 { 819 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 820 struct completion *comp = sp->comp; 821 822 sp->free(sp); 823 cmd->result = res; 824 CMD_SP(cmd) = NULL; 825 cmd->scsi_done(cmd); 826 if (comp) 827 complete(comp); 828 } 829 830 static int 831 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 832 { 833 scsi_qla_host_t *vha = shost_priv(host); 834 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 835 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 836 struct qla_hw_data *ha = vha->hw; 837 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 838 srb_t *sp; 839 int rval; 840 841 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 842 WARN_ON_ONCE(!rport)) { 843 cmd->result = DID_NO_CONNECT << 16; 844 goto qc24_fail_command; 845 } 846 847 if (ha->mqenable) { 848 uint32_t tag; 849 uint16_t hwq; 850 struct qla_qpair *qpair = NULL; 851 852 tag = blk_mq_unique_tag(cmd->request); 853 hwq = blk_mq_unique_tag_to_hwq(tag); 854 qpair = ha->queue_pair_map[hwq]; 855 856 if (qpair) 857 return qla2xxx_mqueuecommand(host, cmd, qpair); 858 } 859 860 if (ha->flags.eeh_busy) { 861 if (ha->flags.pci_channel_io_perm_failure) { 862 ql_dbg(ql_dbg_aer, vha, 0x9010, 863 "PCI Channel IO permanent failure, exiting " 864 "cmd=%p.\n", cmd); 865 cmd->result = DID_NO_CONNECT << 16; 866 } else { 867 ql_dbg(ql_dbg_aer, vha, 0x9011, 868 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 869 cmd->result = DID_REQUEUE << 16; 870 } 871 goto qc24_fail_command; 872 } 873 874 rval = fc_remote_port_chkready(rport); 875 if (rval) { 876 cmd->result = rval; 877 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 878 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 879 cmd, rval); 880 goto qc24_fail_command; 881 } 882 883 if (!vha->flags.difdix_supported && 884 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 885 ql_dbg(ql_dbg_io, vha, 0x3004, 886 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 887 cmd); 888 cmd->result = DID_NO_CONNECT << 16; 889 goto qc24_fail_command; 890 } 891 892 if (!fcport || fcport->deleted) { 893 cmd->result = DID_IMM_RETRY << 16; 894 goto qc24_fail_command; 895 } 896 897 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 898 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 899 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 900 ql_dbg(ql_dbg_io, vha, 0x3005, 901 "Returning DNC, fcport_state=%d loop_state=%d.\n", 902 atomic_read(&fcport->state), 903 atomic_read(&base_vha->loop_state)); 904 cmd->result = DID_NO_CONNECT << 16; 905 goto qc24_fail_command; 906 } 907 goto qc24_target_busy; 908 } 909 910 /* 911 * Return target busy if we've received a non-zero retry_delay_timer 912 * in a FCP_RSP. 913 */ 914 if (fcport->retry_delay_timestamp == 0) { 915 /* retry delay not set */ 916 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 917 fcport->retry_delay_timestamp = 0; 918 else 919 goto qc24_target_busy; 920 921 sp = scsi_cmd_priv(cmd); 922 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 923 924 sp->u.scmd.cmd = cmd; 925 sp->type = SRB_SCSI_CMD; 926 927 CMD_SP(cmd) = (void *)sp; 928 sp->free = qla2x00_sp_free_dma; 929 sp->done = qla2x00_sp_compl; 930 931 rval = ha->isp_ops->start_scsi(sp); 932 if (rval != QLA_SUCCESS) { 933 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 934 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 935 goto qc24_host_busy_free_sp; 936 } 937 938 return 0; 939 940 qc24_host_busy_free_sp: 941 sp->free(sp); 942 943 qc24_target_busy: 944 return SCSI_MLQUEUE_TARGET_BUSY; 945 946 qc24_fail_command: 947 cmd->scsi_done(cmd); 948 949 return 0; 950 } 951 952 /* For MQ supported I/O */ 953 int 954 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 955 struct qla_qpair *qpair) 956 { 957 scsi_qla_host_t *vha = shost_priv(host); 958 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 959 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 960 struct qla_hw_data *ha = vha->hw; 961 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 962 srb_t *sp; 963 int rval; 964 965 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 966 if (rval) { 967 cmd->result = rval; 968 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 969 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 970 cmd, rval); 971 goto qc24_fail_command; 972 } 973 974 if (!qpair->online) { 975 ql_dbg(ql_dbg_io, vha, 0x3077, 976 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 977 cmd->result = DID_NO_CONNECT << 16; 978 goto qc24_fail_command; 979 } 980 981 if (!fcport || fcport->deleted) { 982 cmd->result = DID_IMM_RETRY << 16; 983 goto qc24_fail_command; 984 } 985 986 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 987 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 988 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 989 ql_dbg(ql_dbg_io, vha, 0x3077, 990 "Returning DNC, fcport_state=%d loop_state=%d.\n", 991 atomic_read(&fcport->state), 992 atomic_read(&base_vha->loop_state)); 993 cmd->result = DID_NO_CONNECT << 16; 994 goto qc24_fail_command; 995 } 996 goto qc24_target_busy; 997 } 998 999 /* 1000 * Return target busy if we've received a non-zero retry_delay_timer 1001 * in a FCP_RSP. 1002 */ 1003 if (fcport->retry_delay_timestamp == 0) { 1004 /* retry delay not set */ 1005 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1006 fcport->retry_delay_timestamp = 0; 1007 else 1008 goto qc24_target_busy; 1009 1010 sp = scsi_cmd_priv(cmd); 1011 qla2xxx_init_sp(sp, vha, qpair, fcport); 1012 1013 sp->u.scmd.cmd = cmd; 1014 sp->type = SRB_SCSI_CMD; 1015 CMD_SP(cmd) = (void *)sp; 1016 sp->free = qla2xxx_qpair_sp_free_dma; 1017 sp->done = qla2xxx_qpair_sp_compl; 1018 1019 rval = ha->isp_ops->start_scsi_mq(sp); 1020 if (rval != QLA_SUCCESS) { 1021 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1022 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1023 goto qc24_host_busy_free_sp; 1024 } 1025 1026 return 0; 1027 1028 qc24_host_busy_free_sp: 1029 sp->free(sp); 1030 1031 qc24_target_busy: 1032 return SCSI_MLQUEUE_TARGET_BUSY; 1033 1034 qc24_fail_command: 1035 cmd->scsi_done(cmd); 1036 1037 return 0; 1038 } 1039 1040 /* 1041 * qla2x00_eh_wait_on_command 1042 * Waits for the command to be returned by the Firmware for some 1043 * max time. 1044 * 1045 * Input: 1046 * cmd = Scsi Command to wait on. 1047 * 1048 * Return: 1049 * Completed in time : QLA_SUCCESS 1050 * Did not complete in time : QLA_FUNCTION_FAILED 1051 */ 1052 static int 1053 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) 1054 { 1055 #define ABORT_POLLING_PERIOD 1000 1056 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1057 unsigned long wait_iter = ABORT_WAIT_ITER; 1058 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1059 struct qla_hw_data *ha = vha->hw; 1060 int ret = QLA_SUCCESS; 1061 1062 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { 1063 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1064 "Return:eh_wait.\n"); 1065 return ret; 1066 } 1067 1068 while (CMD_SP(cmd) && wait_iter--) { 1069 msleep(ABORT_POLLING_PERIOD); 1070 } 1071 if (CMD_SP(cmd)) 1072 ret = QLA_FUNCTION_FAILED; 1073 1074 return ret; 1075 } 1076 1077 /* 1078 * qla2x00_wait_for_hba_online 1079 * Wait till the HBA is online after going through 1080 * <= MAX_RETRIES_OF_ISP_ABORT or 1081 * finally HBA is disabled ie marked offline 1082 * 1083 * Input: 1084 * ha - pointer to host adapter structure 1085 * 1086 * Note: 1087 * Does context switching-Release SPIN_LOCK 1088 * (if any) before calling this routine. 1089 * 1090 * Return: 1091 * Success (Adapter is online) : 0 1092 * Failed (Adapter is offline/disabled) : 1 1093 */ 1094 int 1095 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1096 { 1097 int return_status; 1098 unsigned long wait_online; 1099 struct qla_hw_data *ha = vha->hw; 1100 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1101 1102 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1103 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1104 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1105 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1106 ha->dpc_active) && time_before(jiffies, wait_online)) { 1107 1108 msleep(1000); 1109 } 1110 if (base_vha->flags.online) 1111 return_status = QLA_SUCCESS; 1112 else 1113 return_status = QLA_FUNCTION_FAILED; 1114 1115 return (return_status); 1116 } 1117 1118 static inline int test_fcport_count(scsi_qla_host_t *vha) 1119 { 1120 struct qla_hw_data *ha = vha->hw; 1121 unsigned long flags; 1122 int res; 1123 1124 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1125 ql_dbg(ql_dbg_init, vha, 0x00ec, 1126 "tgt %p, fcport_count=%d\n", 1127 vha, vha->fcport_count); 1128 res = (vha->fcport_count == 0); 1129 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1130 1131 return res; 1132 } 1133 1134 /* 1135 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1136 * it has dependency on UNLOADING flag to stop device discovery 1137 */ 1138 void 1139 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1140 { 1141 u8 i; 1142 1143 qla2x00_mark_all_devices_lost(vha); 1144 1145 for (i = 0; i < 10; i++) { 1146 if (wait_event_timeout(vha->fcport_waitQ, 1147 test_fcport_count(vha), HZ) > 0) 1148 break; 1149 } 1150 1151 flush_workqueue(vha->hw->wq); 1152 } 1153 1154 /* 1155 * qla2x00_wait_for_hba_ready 1156 * Wait till the HBA is ready before doing driver unload 1157 * 1158 * Input: 1159 * ha - pointer to host adapter structure 1160 * 1161 * Note: 1162 * Does context switching-Release SPIN_LOCK 1163 * (if any) before calling this routine. 1164 * 1165 */ 1166 static void 1167 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1168 { 1169 struct qla_hw_data *ha = vha->hw; 1170 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1171 1172 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1173 ha->flags.mbox_busy) || 1174 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1175 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) { 1176 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1177 break; 1178 msleep(1000); 1179 } 1180 } 1181 1182 int 1183 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1184 { 1185 int return_status; 1186 unsigned long wait_reset; 1187 struct qla_hw_data *ha = vha->hw; 1188 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1189 1190 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1191 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1192 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1193 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1194 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1195 1196 msleep(1000); 1197 1198 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1199 ha->flags.chip_reset_done) 1200 break; 1201 } 1202 if (ha->flags.chip_reset_done) 1203 return_status = QLA_SUCCESS; 1204 else 1205 return_status = QLA_FUNCTION_FAILED; 1206 1207 return return_status; 1208 } 1209 1210 /************************************************************************** 1211 * qla2xxx_eh_abort 1212 * 1213 * Description: 1214 * The abort function will abort the specified command. 1215 * 1216 * Input: 1217 * cmd = Linux SCSI command packet to be aborted. 1218 * 1219 * Returns: 1220 * Either SUCCESS or FAILED. 1221 * 1222 * Note: 1223 * Only return FAILED if command not returned by firmware. 1224 **************************************************************************/ 1225 static int 1226 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1227 { 1228 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1229 DECLARE_COMPLETION_ONSTACK(comp); 1230 srb_t *sp; 1231 int ret; 1232 unsigned int id; 1233 uint64_t lun; 1234 int rval; 1235 struct qla_hw_data *ha = vha->hw; 1236 uint32_t ratov_j; 1237 struct qla_qpair *qpair; 1238 unsigned long flags; 1239 1240 if (qla2x00_isp_reg_stat(ha)) { 1241 ql_log(ql_log_info, vha, 0x8042, 1242 "PCI/Register disconnect, exiting.\n"); 1243 qla_pci_set_eeh_busy(vha); 1244 return FAILED; 1245 } 1246 1247 ret = fc_block_scsi_eh(cmd); 1248 if (ret != 0) 1249 return ret; 1250 1251 sp = scsi_cmd_priv(cmd); 1252 qpair = sp->qpair; 1253 1254 vha->cmd_timeout_cnt++; 1255 1256 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1257 return SUCCESS; 1258 1259 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1260 sp->comp = ∁ 1261 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1262 1263 1264 id = cmd->device->id; 1265 lun = cmd->device->lun; 1266 1267 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1268 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1269 vha->host_no, id, lun, sp, cmd, sp->handle); 1270 1271 /* 1272 * Abort will release the original Command/sp from FW. Let the 1273 * original command call scsi_done. In return, he will wakeup 1274 * this sleeping thread. 1275 */ 1276 rval = ha->isp_ops->abort_command(sp); 1277 1278 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1279 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1280 1281 /* Wait for the command completion. */ 1282 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1283 ratov_j = msecs_to_jiffies(ratov_j); 1284 switch (rval) { 1285 case QLA_SUCCESS: 1286 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1287 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1288 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1289 __func__, ha->r_a_tov/10); 1290 ret = FAILED; 1291 } else { 1292 ret = SUCCESS; 1293 } 1294 break; 1295 default: 1296 ret = FAILED; 1297 break; 1298 } 1299 1300 sp->comp = NULL; 1301 1302 ql_log(ql_log_info, vha, 0x801c, 1303 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1304 vha->host_no, id, lun, ret); 1305 1306 return ret; 1307 } 1308 1309 /* 1310 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1311 */ 1312 int 1313 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1314 uint64_t l, enum nexus_wait_type type) 1315 { 1316 int cnt, match, status; 1317 unsigned long flags; 1318 struct qla_hw_data *ha = vha->hw; 1319 struct req_que *req; 1320 srb_t *sp; 1321 struct scsi_cmnd *cmd; 1322 1323 status = QLA_SUCCESS; 1324 1325 spin_lock_irqsave(&ha->hardware_lock, flags); 1326 req = vha->req; 1327 for (cnt = 1; status == QLA_SUCCESS && 1328 cnt < req->num_outstanding_cmds; cnt++) { 1329 sp = req->outstanding_cmds[cnt]; 1330 if (!sp) 1331 continue; 1332 if (sp->type != SRB_SCSI_CMD) 1333 continue; 1334 if (vha->vp_idx != sp->vha->vp_idx) 1335 continue; 1336 match = 0; 1337 cmd = GET_CMD_SP(sp); 1338 switch (type) { 1339 case WAIT_HOST: 1340 match = 1; 1341 break; 1342 case WAIT_TARGET: 1343 match = cmd->device->id == t; 1344 break; 1345 case WAIT_LUN: 1346 match = (cmd->device->id == t && 1347 cmd->device->lun == l); 1348 break; 1349 } 1350 if (!match) 1351 continue; 1352 1353 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1354 status = qla2x00_eh_wait_on_command(cmd); 1355 spin_lock_irqsave(&ha->hardware_lock, flags); 1356 } 1357 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1358 1359 return status; 1360 } 1361 1362 static char *reset_errors[] = { 1363 "HBA not online", 1364 "HBA not ready", 1365 "Task management failed", 1366 "Waiting for command completions", 1367 }; 1368 1369 static int 1370 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, 1371 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) 1372 { 1373 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1374 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1375 int err; 1376 1377 if (!fcport) { 1378 return FAILED; 1379 } 1380 1381 err = fc_block_scsi_eh(cmd); 1382 if (err != 0) 1383 return err; 1384 1385 if (fcport->deleted) 1386 return SUCCESS; 1387 1388 ql_log(ql_log_info, vha, 0x8009, 1389 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, 1390 cmd->device->id, cmd->device->lun, cmd); 1391 1392 err = 0; 1393 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1394 ql_log(ql_log_warn, vha, 0x800a, 1395 "Wait for hba online failed for cmd=%p.\n", cmd); 1396 goto eh_reset_failed; 1397 } 1398 err = 2; 1399 if (do_reset(fcport, cmd->device->lun, 1) 1400 != QLA_SUCCESS) { 1401 ql_log(ql_log_warn, vha, 0x800c, 1402 "do_reset failed for cmd=%p.\n", cmd); 1403 goto eh_reset_failed; 1404 } 1405 err = 3; 1406 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, 1407 cmd->device->lun, type) != QLA_SUCCESS) { 1408 ql_log(ql_log_warn, vha, 0x800d, 1409 "wait for pending cmds failed for cmd=%p.\n", cmd); 1410 goto eh_reset_failed; 1411 } 1412 1413 ql_log(ql_log_info, vha, 0x800e, 1414 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, 1415 vha->host_no, cmd->device->id, cmd->device->lun, cmd); 1416 1417 return SUCCESS; 1418 1419 eh_reset_failed: 1420 ql_log(ql_log_info, vha, 0x800f, 1421 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, 1422 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1423 cmd); 1424 vha->reset_cmd_err_cnt++; 1425 return FAILED; 1426 } 1427 1428 static int 1429 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1430 { 1431 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1432 struct qla_hw_data *ha = vha->hw; 1433 1434 if (qla2x00_isp_reg_stat(ha)) { 1435 ql_log(ql_log_info, vha, 0x803e, 1436 "PCI/Register disconnect, exiting.\n"); 1437 qla_pci_set_eeh_busy(vha); 1438 return FAILED; 1439 } 1440 1441 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, 1442 ha->isp_ops->lun_reset); 1443 } 1444 1445 static int 1446 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1447 { 1448 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1449 struct qla_hw_data *ha = vha->hw; 1450 1451 if (qla2x00_isp_reg_stat(ha)) { 1452 ql_log(ql_log_info, vha, 0x803f, 1453 "PCI/Register disconnect, exiting.\n"); 1454 qla_pci_set_eeh_busy(vha); 1455 return FAILED; 1456 } 1457 1458 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, 1459 ha->isp_ops->target_reset); 1460 } 1461 1462 /************************************************************************** 1463 * qla2xxx_eh_bus_reset 1464 * 1465 * Description: 1466 * The bus reset function will reset the bus and abort any executing 1467 * commands. 1468 * 1469 * Input: 1470 * cmd = Linux SCSI command packet of the command that cause the 1471 * bus reset. 1472 * 1473 * Returns: 1474 * SUCCESS/FAILURE (defined as macro in scsi.h). 1475 * 1476 **************************************************************************/ 1477 static int 1478 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1479 { 1480 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1481 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 1482 int ret = FAILED; 1483 unsigned int id; 1484 uint64_t lun; 1485 struct qla_hw_data *ha = vha->hw; 1486 1487 if (qla2x00_isp_reg_stat(ha)) { 1488 ql_log(ql_log_info, vha, 0x8040, 1489 "PCI/Register disconnect, exiting.\n"); 1490 qla_pci_set_eeh_busy(vha); 1491 return FAILED; 1492 } 1493 1494 id = cmd->device->id; 1495 lun = cmd->device->lun; 1496 1497 if (!fcport) { 1498 return ret; 1499 } 1500 1501 ret = fc_block_scsi_eh(cmd); 1502 if (ret != 0) 1503 return ret; 1504 ret = FAILED; 1505 1506 if (qla2x00_chip_is_down(vha)) 1507 return ret; 1508 1509 ql_log(ql_log_info, vha, 0x8012, 1510 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1511 1512 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1513 ql_log(ql_log_fatal, vha, 0x8013, 1514 "Wait for hba online failed board disabled.\n"); 1515 goto eh_bus_reset_done; 1516 } 1517 1518 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1519 ret = SUCCESS; 1520 1521 if (ret == FAILED) 1522 goto eh_bus_reset_done; 1523 1524 /* Flush outstanding commands. */ 1525 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1526 QLA_SUCCESS) { 1527 ql_log(ql_log_warn, vha, 0x8014, 1528 "Wait for pending commands failed.\n"); 1529 ret = FAILED; 1530 } 1531 1532 eh_bus_reset_done: 1533 ql_log(ql_log_warn, vha, 0x802b, 1534 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1535 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1536 1537 return ret; 1538 } 1539 1540 /************************************************************************** 1541 * qla2xxx_eh_host_reset 1542 * 1543 * Description: 1544 * The reset function will reset the Adapter. 1545 * 1546 * Input: 1547 * cmd = Linux SCSI command packet of the command that cause the 1548 * adapter reset. 1549 * 1550 * Returns: 1551 * Either SUCCESS or FAILED. 1552 * 1553 * Note: 1554 **************************************************************************/ 1555 static int 1556 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1557 { 1558 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1559 struct qla_hw_data *ha = vha->hw; 1560 int ret = FAILED; 1561 unsigned int id; 1562 uint64_t lun; 1563 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1564 1565 if (qla2x00_isp_reg_stat(ha)) { 1566 ql_log(ql_log_info, vha, 0x8041, 1567 "PCI/Register disconnect, exiting.\n"); 1568 qla_pci_set_eeh_busy(vha); 1569 return SUCCESS; 1570 } 1571 1572 id = cmd->device->id; 1573 lun = cmd->device->lun; 1574 1575 ql_log(ql_log_info, vha, 0x8018, 1576 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1577 1578 /* 1579 * No point in issuing another reset if one is active. Also do not 1580 * attempt a reset if we are updating flash. 1581 */ 1582 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1583 goto eh_host_reset_lock; 1584 1585 if (vha != base_vha) { 1586 if (qla2x00_vp_abort_isp(vha)) 1587 goto eh_host_reset_lock; 1588 } else { 1589 if (IS_P3P_TYPE(vha->hw)) { 1590 if (!qla82xx_fcoe_ctx_reset(vha)) { 1591 /* Ctx reset success */ 1592 ret = SUCCESS; 1593 goto eh_host_reset_lock; 1594 } 1595 /* fall thru if ctx reset failed */ 1596 } 1597 if (ha->wq) 1598 flush_workqueue(ha->wq); 1599 1600 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1601 if (ha->isp_ops->abort_isp(base_vha)) { 1602 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1603 /* failed. schedule dpc to try */ 1604 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1605 1606 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1607 ql_log(ql_log_warn, vha, 0x802a, 1608 "wait for hba online failed.\n"); 1609 goto eh_host_reset_lock; 1610 } 1611 } 1612 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1613 } 1614 1615 /* Waiting for command to be returned to OS.*/ 1616 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1617 QLA_SUCCESS) 1618 ret = SUCCESS; 1619 1620 eh_host_reset_lock: 1621 ql_log(ql_log_info, vha, 0x8017, 1622 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1623 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1624 1625 return ret; 1626 } 1627 1628 /* 1629 * qla2x00_loop_reset 1630 * Issue loop reset. 1631 * 1632 * Input: 1633 * ha = adapter block pointer. 1634 * 1635 * Returns: 1636 * 0 = success 1637 */ 1638 int 1639 qla2x00_loop_reset(scsi_qla_host_t *vha) 1640 { 1641 int ret; 1642 struct fc_port *fcport; 1643 struct qla_hw_data *ha = vha->hw; 1644 1645 if (IS_QLAFX00(ha)) { 1646 return qlafx00_loop_reset(vha); 1647 } 1648 1649 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { 1650 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1651 if (fcport->port_type != FCT_TARGET) 1652 continue; 1653 1654 ret = ha->isp_ops->target_reset(fcport, 0, 0); 1655 if (ret != QLA_SUCCESS) { 1656 ql_dbg(ql_dbg_taskm, vha, 0x802c, 1657 "Bus Reset failed: Reset=%d " 1658 "d_id=%x.\n", ret, fcport->d_id.b24); 1659 } 1660 } 1661 } 1662 1663 1664 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1665 atomic_set(&vha->loop_state, LOOP_DOWN); 1666 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1667 qla2x00_mark_all_devices_lost(vha); 1668 ret = qla2x00_full_login_lip(vha); 1669 if (ret != QLA_SUCCESS) { 1670 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1671 "full_login_lip=%d.\n", ret); 1672 } 1673 } 1674 1675 if (ha->flags.enable_lip_reset) { 1676 ret = qla2x00_lip_reset(vha); 1677 if (ret != QLA_SUCCESS) 1678 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1679 "lip_reset failed (%d).\n", ret); 1680 } 1681 1682 /* Issue marker command only when we are going to start the I/O */ 1683 vha->marker_needed = 1; 1684 1685 return QLA_SUCCESS; 1686 } 1687 1688 /* 1689 * The caller must ensure that no completion interrupts will happen 1690 * while this function is in progress. 1691 */ 1692 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1693 unsigned long *flags) 1694 __releases(qp->qp_lock_ptr) 1695 __acquires(qp->qp_lock_ptr) 1696 { 1697 DECLARE_COMPLETION_ONSTACK(comp); 1698 scsi_qla_host_t *vha = qp->vha; 1699 struct qla_hw_data *ha = vha->hw; 1700 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1701 int rval; 1702 bool ret_cmd; 1703 uint32_t ratov_j; 1704 1705 lockdep_assert_held(qp->qp_lock_ptr); 1706 1707 if (qla2x00_chip_is_down(vha)) { 1708 sp->done(sp, res); 1709 return; 1710 } 1711 1712 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1713 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1714 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1715 !qla2x00_isp_reg_stat(ha))) { 1716 if (sp->comp) { 1717 sp->done(sp, res); 1718 return; 1719 } 1720 1721 sp->comp = ∁ 1722 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1723 1724 rval = ha->isp_ops->abort_command(sp); 1725 /* Wait for command completion. */ 1726 ret_cmd = false; 1727 ratov_j = ha->r_a_tov/10 * 4 * 1000; 1728 ratov_j = msecs_to_jiffies(ratov_j); 1729 switch (rval) { 1730 case QLA_SUCCESS: 1731 if (wait_for_completion_timeout(&comp, ratov_j)) { 1732 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1733 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1734 __func__, ha->r_a_tov/10); 1735 ret_cmd = true; 1736 } 1737 /* else FW return SP to driver */ 1738 break; 1739 default: 1740 ret_cmd = true; 1741 break; 1742 } 1743 1744 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1745 if (ret_cmd && blk_mq_request_started(cmd->request)) 1746 sp->done(sp, res); 1747 } else { 1748 sp->done(sp, res); 1749 } 1750 } 1751 1752 /* 1753 * The caller must ensure that no completion interrupts will happen 1754 * while this function is in progress. 1755 */ 1756 static void 1757 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1758 { 1759 int cnt; 1760 unsigned long flags; 1761 srb_t *sp; 1762 scsi_qla_host_t *vha = qp->vha; 1763 struct qla_hw_data *ha = vha->hw; 1764 struct req_que *req; 1765 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1766 struct qla_tgt_cmd *cmd; 1767 1768 if (!ha->req_q_map) 1769 return; 1770 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1771 req = qp->req; 1772 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1773 sp = req->outstanding_cmds[cnt]; 1774 if (sp) { 1775 switch (sp->cmd_type) { 1776 case TYPE_SRB: 1777 qla2x00_abort_srb(qp, sp, res, &flags); 1778 break; 1779 case TYPE_TGT_CMD: 1780 if (!vha->hw->tgt.tgt_ops || !tgt || 1781 qla_ini_mode_enabled(vha)) { 1782 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1783 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1784 vha->dpc_flags); 1785 continue; 1786 } 1787 cmd = (struct qla_tgt_cmd *)sp; 1788 cmd->aborted = 1; 1789 break; 1790 case TYPE_TGT_TMCMD: 1791 /* Skip task management functions. */ 1792 break; 1793 default: 1794 break; 1795 } 1796 req->outstanding_cmds[cnt] = NULL; 1797 } 1798 } 1799 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1800 } 1801 1802 /* 1803 * The caller must ensure that no completion interrupts will happen 1804 * while this function is in progress. 1805 */ 1806 void 1807 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1808 { 1809 int que; 1810 struct qla_hw_data *ha = vha->hw; 1811 1812 /* Continue only if initialization complete. */ 1813 if (!ha->base_qpair) 1814 return; 1815 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1816 1817 if (!ha->queue_pair_map) 1818 return; 1819 for (que = 0; que < ha->max_qpairs; que++) { 1820 if (!ha->queue_pair_map[que]) 1821 continue; 1822 1823 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1824 } 1825 } 1826 1827 static int 1828 qla2xxx_slave_alloc(struct scsi_device *sdev) 1829 { 1830 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1831 1832 if (!rport || fc_remote_port_chkready(rport)) 1833 return -ENXIO; 1834 1835 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1836 1837 return 0; 1838 } 1839 1840 static int 1841 qla2xxx_slave_configure(struct scsi_device *sdev) 1842 { 1843 scsi_qla_host_t *vha = shost_priv(sdev->host); 1844 struct req_que *req = vha->req; 1845 1846 if (IS_T10_PI_CAPABLE(vha->hw)) 1847 blk_queue_update_dma_alignment(sdev->request_queue, 0x7); 1848 1849 scsi_change_queue_depth(sdev, req->max_q_depth); 1850 return 0; 1851 } 1852 1853 static void 1854 qla2xxx_slave_destroy(struct scsi_device *sdev) 1855 { 1856 sdev->hostdata = NULL; 1857 } 1858 1859 /** 1860 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1861 * @ha: HA context 1862 * 1863 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1864 * supported addressing method. 1865 */ 1866 static void 1867 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1868 { 1869 /* Assume a 32bit DMA mask. */ 1870 ha->flags.enable_64bit_addressing = 0; 1871 1872 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1873 /* Any upper-dword bits set? */ 1874 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1875 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1876 /* Ok, a 64bit DMA mask is applicable. */ 1877 ha->flags.enable_64bit_addressing = 1; 1878 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1879 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1880 return; 1881 } 1882 } 1883 1884 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1885 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1886 } 1887 1888 static void 1889 qla2x00_enable_intrs(struct qla_hw_data *ha) 1890 { 1891 unsigned long flags = 0; 1892 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1893 1894 spin_lock_irqsave(&ha->hardware_lock, flags); 1895 ha->interrupts_on = 1; 1896 /* enable risc and host interrupts */ 1897 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 1898 rd_reg_word(®->ictrl); 1899 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1900 1901 } 1902 1903 static void 1904 qla2x00_disable_intrs(struct qla_hw_data *ha) 1905 { 1906 unsigned long flags = 0; 1907 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1908 1909 spin_lock_irqsave(&ha->hardware_lock, flags); 1910 ha->interrupts_on = 0; 1911 /* disable risc and host interrupts */ 1912 wrt_reg_word(®->ictrl, 0); 1913 rd_reg_word(®->ictrl); 1914 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1915 } 1916 1917 static void 1918 qla24xx_enable_intrs(struct qla_hw_data *ha) 1919 { 1920 unsigned long flags = 0; 1921 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1922 1923 spin_lock_irqsave(&ha->hardware_lock, flags); 1924 ha->interrupts_on = 1; 1925 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 1926 rd_reg_dword(®->ictrl); 1927 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1928 } 1929 1930 static void 1931 qla24xx_disable_intrs(struct qla_hw_data *ha) 1932 { 1933 unsigned long flags = 0; 1934 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1935 1936 if (IS_NOPOLLING_TYPE(ha)) 1937 return; 1938 spin_lock_irqsave(&ha->hardware_lock, flags); 1939 ha->interrupts_on = 0; 1940 wrt_reg_dword(®->ictrl, 0); 1941 rd_reg_dword(®->ictrl); 1942 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1943 } 1944 1945 static int 1946 qla2x00_iospace_config(struct qla_hw_data *ha) 1947 { 1948 resource_size_t pio; 1949 uint16_t msix; 1950 1951 if (pci_request_selected_regions(ha->pdev, ha->bars, 1952 QLA2XXX_DRIVER_NAME)) { 1953 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 1954 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 1955 pci_name(ha->pdev)); 1956 goto iospace_error_exit; 1957 } 1958 if (!(ha->bars & 1)) 1959 goto skip_pio; 1960 1961 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 1962 pio = pci_resource_start(ha->pdev, 0); 1963 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 1964 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 1965 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 1966 "Invalid pci I/O region size (%s).\n", 1967 pci_name(ha->pdev)); 1968 pio = 0; 1969 } 1970 } else { 1971 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 1972 "Region #0 no a PIO resource (%s).\n", 1973 pci_name(ha->pdev)); 1974 pio = 0; 1975 } 1976 ha->pio_address = pio; 1977 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 1978 "PIO address=%llu.\n", 1979 (unsigned long long)ha->pio_address); 1980 1981 skip_pio: 1982 /* Use MMIO operations for all accesses. */ 1983 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 1984 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 1985 "Region #1 not an MMIO resource (%s), aborting.\n", 1986 pci_name(ha->pdev)); 1987 goto iospace_error_exit; 1988 } 1989 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 1990 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 1991 "Invalid PCI mem region size (%s), aborting.\n", 1992 pci_name(ha->pdev)); 1993 goto iospace_error_exit; 1994 } 1995 1996 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 1997 if (!ha->iobase) { 1998 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 1999 "Cannot remap MMIO (%s), aborting.\n", 2000 pci_name(ha->pdev)); 2001 goto iospace_error_exit; 2002 } 2003 2004 /* Determine queue resources */ 2005 ha->max_req_queues = ha->max_rsp_queues = 1; 2006 ha->msix_count = QLA_BASE_VECTORS; 2007 2008 /* Check if FW supports MQ or not */ 2009 if (!(ha->fw_attributes & BIT_6)) 2010 goto mqiobase_exit; 2011 2012 if (!ql2xmqsupport || !ql2xnvmeenable || 2013 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2014 goto mqiobase_exit; 2015 2016 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2017 pci_resource_len(ha->pdev, 3)); 2018 if (ha->mqiobase) { 2019 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2020 "MQIO Base=%p.\n", ha->mqiobase); 2021 /* Read MSIX vector size of the board */ 2022 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2023 ha->msix_count = msix + 1; 2024 /* Max queues are bounded by available msix vectors */ 2025 /* MB interrupt uses 1 vector */ 2026 ha->max_req_queues = ha->msix_count - 1; 2027 ha->max_rsp_queues = ha->max_req_queues; 2028 /* Queue pairs is the max value minus the base queue pair */ 2029 ha->max_qpairs = ha->max_rsp_queues - 1; 2030 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2031 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2032 2033 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2034 "MSI-X vector count: %d.\n", ha->msix_count); 2035 } else 2036 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2037 "BAR 3 not enabled.\n"); 2038 2039 mqiobase_exit: 2040 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2041 "MSIX Count: %d.\n", ha->msix_count); 2042 return (0); 2043 2044 iospace_error_exit: 2045 return (-ENOMEM); 2046 } 2047 2048 2049 static int 2050 qla83xx_iospace_config(struct qla_hw_data *ha) 2051 { 2052 uint16_t msix; 2053 2054 if (pci_request_selected_regions(ha->pdev, ha->bars, 2055 QLA2XXX_DRIVER_NAME)) { 2056 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2057 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2058 pci_name(ha->pdev)); 2059 2060 goto iospace_error_exit; 2061 } 2062 2063 /* Use MMIO operations for all accesses. */ 2064 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2065 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2066 "Invalid pci I/O region size (%s).\n", 2067 pci_name(ha->pdev)); 2068 goto iospace_error_exit; 2069 } 2070 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2071 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2072 "Invalid PCI mem region size (%s), aborting\n", 2073 pci_name(ha->pdev)); 2074 goto iospace_error_exit; 2075 } 2076 2077 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2078 if (!ha->iobase) { 2079 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2080 "Cannot remap MMIO (%s), aborting.\n", 2081 pci_name(ha->pdev)); 2082 goto iospace_error_exit; 2083 } 2084 2085 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2086 /* 83XX 26XX always use MQ type access for queues 2087 * - mbar 2, a.k.a region 4 */ 2088 ha->max_req_queues = ha->max_rsp_queues = 1; 2089 ha->msix_count = QLA_BASE_VECTORS; 2090 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2091 pci_resource_len(ha->pdev, 4)); 2092 2093 if (!ha->mqiobase) { 2094 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2095 "BAR2/region4 not enabled\n"); 2096 goto mqiobase_exit; 2097 } 2098 2099 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2100 pci_resource_len(ha->pdev, 2)); 2101 if (ha->msixbase) { 2102 /* Read MSIX vector size of the board */ 2103 pci_read_config_word(ha->pdev, 2104 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2105 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2106 /* 2107 * By default, driver uses at least two msix vectors 2108 * (default & rspq) 2109 */ 2110 if (ql2xmqsupport || ql2xnvmeenable) { 2111 /* MB interrupt uses 1 vector */ 2112 ha->max_req_queues = ha->msix_count - 1; 2113 2114 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2115 if (QLA_TGT_MODE_ENABLED()) 2116 ha->max_req_queues--; 2117 2118 ha->max_rsp_queues = ha->max_req_queues; 2119 2120 /* Queue pairs is the max value minus 2121 * the base queue pair */ 2122 ha->max_qpairs = ha->max_req_queues - 1; 2123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2124 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2125 } 2126 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2127 "MSI-X vector count: %d.\n", ha->msix_count); 2128 } else 2129 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2130 "BAR 1 not enabled.\n"); 2131 2132 mqiobase_exit: 2133 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2134 "MSIX Count: %d.\n", ha->msix_count); 2135 return 0; 2136 2137 iospace_error_exit: 2138 return -ENOMEM; 2139 } 2140 2141 static struct isp_operations qla2100_isp_ops = { 2142 .pci_config = qla2100_pci_config, 2143 .reset_chip = qla2x00_reset_chip, 2144 .chip_diag = qla2x00_chip_diag, 2145 .config_rings = qla2x00_config_rings, 2146 .reset_adapter = qla2x00_reset_adapter, 2147 .nvram_config = qla2x00_nvram_config, 2148 .update_fw_options = qla2x00_update_fw_options, 2149 .load_risc = qla2x00_load_risc, 2150 .pci_info_str = qla2x00_pci_info_str, 2151 .fw_version_str = qla2x00_fw_version_str, 2152 .intr_handler = qla2100_intr_handler, 2153 .enable_intrs = qla2x00_enable_intrs, 2154 .disable_intrs = qla2x00_disable_intrs, 2155 .abort_command = qla2x00_abort_command, 2156 .target_reset = qla2x00_abort_target, 2157 .lun_reset = qla2x00_lun_reset, 2158 .fabric_login = qla2x00_login_fabric, 2159 .fabric_logout = qla2x00_fabric_logout, 2160 .calc_req_entries = qla2x00_calc_iocbs_32, 2161 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2162 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2163 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2164 .read_nvram = qla2x00_read_nvram_data, 2165 .write_nvram = qla2x00_write_nvram_data, 2166 .fw_dump = qla2100_fw_dump, 2167 .beacon_on = NULL, 2168 .beacon_off = NULL, 2169 .beacon_blink = NULL, 2170 .read_optrom = qla2x00_read_optrom_data, 2171 .write_optrom = qla2x00_write_optrom_data, 2172 .get_flash_version = qla2x00_get_flash_version, 2173 .start_scsi = qla2x00_start_scsi, 2174 .start_scsi_mq = NULL, 2175 .abort_isp = qla2x00_abort_isp, 2176 .iospace_config = qla2x00_iospace_config, 2177 .initialize_adapter = qla2x00_initialize_adapter, 2178 }; 2179 2180 static struct isp_operations qla2300_isp_ops = { 2181 .pci_config = qla2300_pci_config, 2182 .reset_chip = qla2x00_reset_chip, 2183 .chip_diag = qla2x00_chip_diag, 2184 .config_rings = qla2x00_config_rings, 2185 .reset_adapter = qla2x00_reset_adapter, 2186 .nvram_config = qla2x00_nvram_config, 2187 .update_fw_options = qla2x00_update_fw_options, 2188 .load_risc = qla2x00_load_risc, 2189 .pci_info_str = qla2x00_pci_info_str, 2190 .fw_version_str = qla2x00_fw_version_str, 2191 .intr_handler = qla2300_intr_handler, 2192 .enable_intrs = qla2x00_enable_intrs, 2193 .disable_intrs = qla2x00_disable_intrs, 2194 .abort_command = qla2x00_abort_command, 2195 .target_reset = qla2x00_abort_target, 2196 .lun_reset = qla2x00_lun_reset, 2197 .fabric_login = qla2x00_login_fabric, 2198 .fabric_logout = qla2x00_fabric_logout, 2199 .calc_req_entries = qla2x00_calc_iocbs_32, 2200 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2201 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2202 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2203 .read_nvram = qla2x00_read_nvram_data, 2204 .write_nvram = qla2x00_write_nvram_data, 2205 .fw_dump = qla2300_fw_dump, 2206 .beacon_on = qla2x00_beacon_on, 2207 .beacon_off = qla2x00_beacon_off, 2208 .beacon_blink = qla2x00_beacon_blink, 2209 .read_optrom = qla2x00_read_optrom_data, 2210 .write_optrom = qla2x00_write_optrom_data, 2211 .get_flash_version = qla2x00_get_flash_version, 2212 .start_scsi = qla2x00_start_scsi, 2213 .start_scsi_mq = NULL, 2214 .abort_isp = qla2x00_abort_isp, 2215 .iospace_config = qla2x00_iospace_config, 2216 .initialize_adapter = qla2x00_initialize_adapter, 2217 }; 2218 2219 static struct isp_operations qla24xx_isp_ops = { 2220 .pci_config = qla24xx_pci_config, 2221 .reset_chip = qla24xx_reset_chip, 2222 .chip_diag = qla24xx_chip_diag, 2223 .config_rings = qla24xx_config_rings, 2224 .reset_adapter = qla24xx_reset_adapter, 2225 .nvram_config = qla24xx_nvram_config, 2226 .update_fw_options = qla24xx_update_fw_options, 2227 .load_risc = qla24xx_load_risc, 2228 .pci_info_str = qla24xx_pci_info_str, 2229 .fw_version_str = qla24xx_fw_version_str, 2230 .intr_handler = qla24xx_intr_handler, 2231 .enable_intrs = qla24xx_enable_intrs, 2232 .disable_intrs = qla24xx_disable_intrs, 2233 .abort_command = qla24xx_abort_command, 2234 .target_reset = qla24xx_abort_target, 2235 .lun_reset = qla24xx_lun_reset, 2236 .fabric_login = qla24xx_login_fabric, 2237 .fabric_logout = qla24xx_fabric_logout, 2238 .calc_req_entries = NULL, 2239 .build_iocbs = NULL, 2240 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2241 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2242 .read_nvram = qla24xx_read_nvram_data, 2243 .write_nvram = qla24xx_write_nvram_data, 2244 .fw_dump = qla24xx_fw_dump, 2245 .beacon_on = qla24xx_beacon_on, 2246 .beacon_off = qla24xx_beacon_off, 2247 .beacon_blink = qla24xx_beacon_blink, 2248 .read_optrom = qla24xx_read_optrom_data, 2249 .write_optrom = qla24xx_write_optrom_data, 2250 .get_flash_version = qla24xx_get_flash_version, 2251 .start_scsi = qla24xx_start_scsi, 2252 .start_scsi_mq = NULL, 2253 .abort_isp = qla2x00_abort_isp, 2254 .iospace_config = qla2x00_iospace_config, 2255 .initialize_adapter = qla2x00_initialize_adapter, 2256 }; 2257 2258 static struct isp_operations qla25xx_isp_ops = { 2259 .pci_config = qla25xx_pci_config, 2260 .reset_chip = qla24xx_reset_chip, 2261 .chip_diag = qla24xx_chip_diag, 2262 .config_rings = qla24xx_config_rings, 2263 .reset_adapter = qla24xx_reset_adapter, 2264 .nvram_config = qla24xx_nvram_config, 2265 .update_fw_options = qla24xx_update_fw_options, 2266 .load_risc = qla24xx_load_risc, 2267 .pci_info_str = qla24xx_pci_info_str, 2268 .fw_version_str = qla24xx_fw_version_str, 2269 .intr_handler = qla24xx_intr_handler, 2270 .enable_intrs = qla24xx_enable_intrs, 2271 .disable_intrs = qla24xx_disable_intrs, 2272 .abort_command = qla24xx_abort_command, 2273 .target_reset = qla24xx_abort_target, 2274 .lun_reset = qla24xx_lun_reset, 2275 .fabric_login = qla24xx_login_fabric, 2276 .fabric_logout = qla24xx_fabric_logout, 2277 .calc_req_entries = NULL, 2278 .build_iocbs = NULL, 2279 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2280 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2281 .read_nvram = qla25xx_read_nvram_data, 2282 .write_nvram = qla25xx_write_nvram_data, 2283 .fw_dump = qla25xx_fw_dump, 2284 .beacon_on = qla24xx_beacon_on, 2285 .beacon_off = qla24xx_beacon_off, 2286 .beacon_blink = qla24xx_beacon_blink, 2287 .read_optrom = qla25xx_read_optrom_data, 2288 .write_optrom = qla24xx_write_optrom_data, 2289 .get_flash_version = qla24xx_get_flash_version, 2290 .start_scsi = qla24xx_dif_start_scsi, 2291 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2292 .abort_isp = qla2x00_abort_isp, 2293 .iospace_config = qla2x00_iospace_config, 2294 .initialize_adapter = qla2x00_initialize_adapter, 2295 }; 2296 2297 static struct isp_operations qla81xx_isp_ops = { 2298 .pci_config = qla25xx_pci_config, 2299 .reset_chip = qla24xx_reset_chip, 2300 .chip_diag = qla24xx_chip_diag, 2301 .config_rings = qla24xx_config_rings, 2302 .reset_adapter = qla24xx_reset_adapter, 2303 .nvram_config = qla81xx_nvram_config, 2304 .update_fw_options = qla24xx_update_fw_options, 2305 .load_risc = qla81xx_load_risc, 2306 .pci_info_str = qla24xx_pci_info_str, 2307 .fw_version_str = qla24xx_fw_version_str, 2308 .intr_handler = qla24xx_intr_handler, 2309 .enable_intrs = qla24xx_enable_intrs, 2310 .disable_intrs = qla24xx_disable_intrs, 2311 .abort_command = qla24xx_abort_command, 2312 .target_reset = qla24xx_abort_target, 2313 .lun_reset = qla24xx_lun_reset, 2314 .fabric_login = qla24xx_login_fabric, 2315 .fabric_logout = qla24xx_fabric_logout, 2316 .calc_req_entries = NULL, 2317 .build_iocbs = NULL, 2318 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2319 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2320 .read_nvram = NULL, 2321 .write_nvram = NULL, 2322 .fw_dump = qla81xx_fw_dump, 2323 .beacon_on = qla24xx_beacon_on, 2324 .beacon_off = qla24xx_beacon_off, 2325 .beacon_blink = qla83xx_beacon_blink, 2326 .read_optrom = qla25xx_read_optrom_data, 2327 .write_optrom = qla24xx_write_optrom_data, 2328 .get_flash_version = qla24xx_get_flash_version, 2329 .start_scsi = qla24xx_dif_start_scsi, 2330 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2331 .abort_isp = qla2x00_abort_isp, 2332 .iospace_config = qla2x00_iospace_config, 2333 .initialize_adapter = qla2x00_initialize_adapter, 2334 }; 2335 2336 static struct isp_operations qla82xx_isp_ops = { 2337 .pci_config = qla82xx_pci_config, 2338 .reset_chip = qla82xx_reset_chip, 2339 .chip_diag = qla24xx_chip_diag, 2340 .config_rings = qla82xx_config_rings, 2341 .reset_adapter = qla24xx_reset_adapter, 2342 .nvram_config = qla81xx_nvram_config, 2343 .update_fw_options = qla24xx_update_fw_options, 2344 .load_risc = qla82xx_load_risc, 2345 .pci_info_str = qla24xx_pci_info_str, 2346 .fw_version_str = qla24xx_fw_version_str, 2347 .intr_handler = qla82xx_intr_handler, 2348 .enable_intrs = qla82xx_enable_intrs, 2349 .disable_intrs = qla82xx_disable_intrs, 2350 .abort_command = qla24xx_abort_command, 2351 .target_reset = qla24xx_abort_target, 2352 .lun_reset = qla24xx_lun_reset, 2353 .fabric_login = qla24xx_login_fabric, 2354 .fabric_logout = qla24xx_fabric_logout, 2355 .calc_req_entries = NULL, 2356 .build_iocbs = NULL, 2357 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2358 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2359 .read_nvram = qla24xx_read_nvram_data, 2360 .write_nvram = qla24xx_write_nvram_data, 2361 .fw_dump = qla82xx_fw_dump, 2362 .beacon_on = qla82xx_beacon_on, 2363 .beacon_off = qla82xx_beacon_off, 2364 .beacon_blink = NULL, 2365 .read_optrom = qla82xx_read_optrom_data, 2366 .write_optrom = qla82xx_write_optrom_data, 2367 .get_flash_version = qla82xx_get_flash_version, 2368 .start_scsi = qla82xx_start_scsi, 2369 .start_scsi_mq = NULL, 2370 .abort_isp = qla82xx_abort_isp, 2371 .iospace_config = qla82xx_iospace_config, 2372 .initialize_adapter = qla2x00_initialize_adapter, 2373 }; 2374 2375 static struct isp_operations qla8044_isp_ops = { 2376 .pci_config = qla82xx_pci_config, 2377 .reset_chip = qla82xx_reset_chip, 2378 .chip_diag = qla24xx_chip_diag, 2379 .config_rings = qla82xx_config_rings, 2380 .reset_adapter = qla24xx_reset_adapter, 2381 .nvram_config = qla81xx_nvram_config, 2382 .update_fw_options = qla24xx_update_fw_options, 2383 .load_risc = qla82xx_load_risc, 2384 .pci_info_str = qla24xx_pci_info_str, 2385 .fw_version_str = qla24xx_fw_version_str, 2386 .intr_handler = qla8044_intr_handler, 2387 .enable_intrs = qla82xx_enable_intrs, 2388 .disable_intrs = qla82xx_disable_intrs, 2389 .abort_command = qla24xx_abort_command, 2390 .target_reset = qla24xx_abort_target, 2391 .lun_reset = qla24xx_lun_reset, 2392 .fabric_login = qla24xx_login_fabric, 2393 .fabric_logout = qla24xx_fabric_logout, 2394 .calc_req_entries = NULL, 2395 .build_iocbs = NULL, 2396 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2397 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2398 .read_nvram = NULL, 2399 .write_nvram = NULL, 2400 .fw_dump = qla8044_fw_dump, 2401 .beacon_on = qla82xx_beacon_on, 2402 .beacon_off = qla82xx_beacon_off, 2403 .beacon_blink = NULL, 2404 .read_optrom = qla8044_read_optrom_data, 2405 .write_optrom = qla8044_write_optrom_data, 2406 .get_flash_version = qla82xx_get_flash_version, 2407 .start_scsi = qla82xx_start_scsi, 2408 .start_scsi_mq = NULL, 2409 .abort_isp = qla8044_abort_isp, 2410 .iospace_config = qla82xx_iospace_config, 2411 .initialize_adapter = qla2x00_initialize_adapter, 2412 }; 2413 2414 static struct isp_operations qla83xx_isp_ops = { 2415 .pci_config = qla25xx_pci_config, 2416 .reset_chip = qla24xx_reset_chip, 2417 .chip_diag = qla24xx_chip_diag, 2418 .config_rings = qla24xx_config_rings, 2419 .reset_adapter = qla24xx_reset_adapter, 2420 .nvram_config = qla81xx_nvram_config, 2421 .update_fw_options = qla24xx_update_fw_options, 2422 .load_risc = qla81xx_load_risc, 2423 .pci_info_str = qla24xx_pci_info_str, 2424 .fw_version_str = qla24xx_fw_version_str, 2425 .intr_handler = qla24xx_intr_handler, 2426 .enable_intrs = qla24xx_enable_intrs, 2427 .disable_intrs = qla24xx_disable_intrs, 2428 .abort_command = qla24xx_abort_command, 2429 .target_reset = qla24xx_abort_target, 2430 .lun_reset = qla24xx_lun_reset, 2431 .fabric_login = qla24xx_login_fabric, 2432 .fabric_logout = qla24xx_fabric_logout, 2433 .calc_req_entries = NULL, 2434 .build_iocbs = NULL, 2435 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2436 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2437 .read_nvram = NULL, 2438 .write_nvram = NULL, 2439 .fw_dump = qla83xx_fw_dump, 2440 .beacon_on = qla24xx_beacon_on, 2441 .beacon_off = qla24xx_beacon_off, 2442 .beacon_blink = qla83xx_beacon_blink, 2443 .read_optrom = qla25xx_read_optrom_data, 2444 .write_optrom = qla24xx_write_optrom_data, 2445 .get_flash_version = qla24xx_get_flash_version, 2446 .start_scsi = qla24xx_dif_start_scsi, 2447 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2448 .abort_isp = qla2x00_abort_isp, 2449 .iospace_config = qla83xx_iospace_config, 2450 .initialize_adapter = qla2x00_initialize_adapter, 2451 }; 2452 2453 static struct isp_operations qlafx00_isp_ops = { 2454 .pci_config = qlafx00_pci_config, 2455 .reset_chip = qlafx00_soft_reset, 2456 .chip_diag = qlafx00_chip_diag, 2457 .config_rings = qlafx00_config_rings, 2458 .reset_adapter = qlafx00_soft_reset, 2459 .nvram_config = NULL, 2460 .update_fw_options = NULL, 2461 .load_risc = NULL, 2462 .pci_info_str = qlafx00_pci_info_str, 2463 .fw_version_str = qlafx00_fw_version_str, 2464 .intr_handler = qlafx00_intr_handler, 2465 .enable_intrs = qlafx00_enable_intrs, 2466 .disable_intrs = qlafx00_disable_intrs, 2467 .abort_command = qla24xx_async_abort_command, 2468 .target_reset = qlafx00_abort_target, 2469 .lun_reset = qlafx00_lun_reset, 2470 .fabric_login = NULL, 2471 .fabric_logout = NULL, 2472 .calc_req_entries = NULL, 2473 .build_iocbs = NULL, 2474 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2475 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2476 .read_nvram = qla24xx_read_nvram_data, 2477 .write_nvram = qla24xx_write_nvram_data, 2478 .fw_dump = NULL, 2479 .beacon_on = qla24xx_beacon_on, 2480 .beacon_off = qla24xx_beacon_off, 2481 .beacon_blink = NULL, 2482 .read_optrom = qla24xx_read_optrom_data, 2483 .write_optrom = qla24xx_write_optrom_data, 2484 .get_flash_version = qla24xx_get_flash_version, 2485 .start_scsi = qlafx00_start_scsi, 2486 .start_scsi_mq = NULL, 2487 .abort_isp = qlafx00_abort_isp, 2488 .iospace_config = qlafx00_iospace_config, 2489 .initialize_adapter = qlafx00_initialize_adapter, 2490 }; 2491 2492 static struct isp_operations qla27xx_isp_ops = { 2493 .pci_config = qla25xx_pci_config, 2494 .reset_chip = qla24xx_reset_chip, 2495 .chip_diag = qla24xx_chip_diag, 2496 .config_rings = qla24xx_config_rings, 2497 .reset_adapter = qla24xx_reset_adapter, 2498 .nvram_config = qla81xx_nvram_config, 2499 .update_fw_options = qla24xx_update_fw_options, 2500 .load_risc = qla81xx_load_risc, 2501 .pci_info_str = qla24xx_pci_info_str, 2502 .fw_version_str = qla24xx_fw_version_str, 2503 .intr_handler = qla24xx_intr_handler, 2504 .enable_intrs = qla24xx_enable_intrs, 2505 .disable_intrs = qla24xx_disable_intrs, 2506 .abort_command = qla24xx_abort_command, 2507 .target_reset = qla24xx_abort_target, 2508 .lun_reset = qla24xx_lun_reset, 2509 .fabric_login = qla24xx_login_fabric, 2510 .fabric_logout = qla24xx_fabric_logout, 2511 .calc_req_entries = NULL, 2512 .build_iocbs = NULL, 2513 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2514 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2515 .read_nvram = NULL, 2516 .write_nvram = NULL, 2517 .fw_dump = qla27xx_fwdump, 2518 .mpi_fw_dump = qla27xx_mpi_fwdump, 2519 .beacon_on = qla24xx_beacon_on, 2520 .beacon_off = qla24xx_beacon_off, 2521 .beacon_blink = qla83xx_beacon_blink, 2522 .read_optrom = qla25xx_read_optrom_data, 2523 .write_optrom = qla24xx_write_optrom_data, 2524 .get_flash_version = qla24xx_get_flash_version, 2525 .start_scsi = qla24xx_dif_start_scsi, 2526 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2527 .abort_isp = qla2x00_abort_isp, 2528 .iospace_config = qla83xx_iospace_config, 2529 .initialize_adapter = qla2x00_initialize_adapter, 2530 }; 2531 2532 static inline void 2533 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2534 { 2535 ha->device_type = DT_EXTENDED_IDS; 2536 switch (ha->pdev->device) { 2537 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2538 ha->isp_type |= DT_ISP2100; 2539 ha->device_type &= ~DT_EXTENDED_IDS; 2540 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2541 break; 2542 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2543 ha->isp_type |= DT_ISP2200; 2544 ha->device_type &= ~DT_EXTENDED_IDS; 2545 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2546 break; 2547 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2548 ha->isp_type |= DT_ISP2300; 2549 ha->device_type |= DT_ZIO_SUPPORTED; 2550 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2551 break; 2552 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2553 ha->isp_type |= DT_ISP2312; 2554 ha->device_type |= DT_ZIO_SUPPORTED; 2555 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2556 break; 2557 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2558 ha->isp_type |= DT_ISP2322; 2559 ha->device_type |= DT_ZIO_SUPPORTED; 2560 if (ha->pdev->subsystem_vendor == 0x1028 && 2561 ha->pdev->subsystem_device == 0x0170) 2562 ha->device_type |= DT_OEM_001; 2563 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2564 break; 2565 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2566 ha->isp_type |= DT_ISP6312; 2567 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2568 break; 2569 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2570 ha->isp_type |= DT_ISP6322; 2571 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2572 break; 2573 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2574 ha->isp_type |= DT_ISP2422; 2575 ha->device_type |= DT_ZIO_SUPPORTED; 2576 ha->device_type |= DT_FWI2; 2577 ha->device_type |= DT_IIDMA; 2578 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2579 break; 2580 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2581 ha->isp_type |= DT_ISP2432; 2582 ha->device_type |= DT_ZIO_SUPPORTED; 2583 ha->device_type |= DT_FWI2; 2584 ha->device_type |= DT_IIDMA; 2585 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2586 break; 2587 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2588 ha->isp_type |= DT_ISP8432; 2589 ha->device_type |= DT_ZIO_SUPPORTED; 2590 ha->device_type |= DT_FWI2; 2591 ha->device_type |= DT_IIDMA; 2592 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2593 break; 2594 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2595 ha->isp_type |= DT_ISP5422; 2596 ha->device_type |= DT_FWI2; 2597 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2598 break; 2599 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2600 ha->isp_type |= DT_ISP5432; 2601 ha->device_type |= DT_FWI2; 2602 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2603 break; 2604 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2605 ha->isp_type |= DT_ISP2532; 2606 ha->device_type |= DT_ZIO_SUPPORTED; 2607 ha->device_type |= DT_FWI2; 2608 ha->device_type |= DT_IIDMA; 2609 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2610 break; 2611 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2612 ha->isp_type |= DT_ISP8001; 2613 ha->device_type |= DT_ZIO_SUPPORTED; 2614 ha->device_type |= DT_FWI2; 2615 ha->device_type |= DT_IIDMA; 2616 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2617 break; 2618 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2619 ha->isp_type |= DT_ISP8021; 2620 ha->device_type |= DT_ZIO_SUPPORTED; 2621 ha->device_type |= DT_FWI2; 2622 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2623 /* Initialize 82XX ISP flags */ 2624 qla82xx_init_flags(ha); 2625 break; 2626 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2627 ha->isp_type |= DT_ISP8044; 2628 ha->device_type |= DT_ZIO_SUPPORTED; 2629 ha->device_type |= DT_FWI2; 2630 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2631 /* Initialize 82XX ISP flags */ 2632 qla82xx_init_flags(ha); 2633 break; 2634 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2635 ha->isp_type |= DT_ISP2031; 2636 ha->device_type |= DT_ZIO_SUPPORTED; 2637 ha->device_type |= DT_FWI2; 2638 ha->device_type |= DT_IIDMA; 2639 ha->device_type |= DT_T10_PI; 2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2641 break; 2642 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2643 ha->isp_type |= DT_ISP8031; 2644 ha->device_type |= DT_ZIO_SUPPORTED; 2645 ha->device_type |= DT_FWI2; 2646 ha->device_type |= DT_IIDMA; 2647 ha->device_type |= DT_T10_PI; 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2649 break; 2650 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2651 ha->isp_type |= DT_ISPFX00; 2652 break; 2653 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2654 ha->isp_type |= DT_ISP2071; 2655 ha->device_type |= DT_ZIO_SUPPORTED; 2656 ha->device_type |= DT_FWI2; 2657 ha->device_type |= DT_IIDMA; 2658 ha->device_type |= DT_T10_PI; 2659 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2660 break; 2661 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2662 ha->isp_type |= DT_ISP2271; 2663 ha->device_type |= DT_ZIO_SUPPORTED; 2664 ha->device_type |= DT_FWI2; 2665 ha->device_type |= DT_IIDMA; 2666 ha->device_type |= DT_T10_PI; 2667 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2668 break; 2669 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2670 ha->isp_type |= DT_ISP2261; 2671 ha->device_type |= DT_ZIO_SUPPORTED; 2672 ha->device_type |= DT_FWI2; 2673 ha->device_type |= DT_IIDMA; 2674 ha->device_type |= DT_T10_PI; 2675 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2676 break; 2677 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2678 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2679 ha->isp_type |= DT_ISP2081; 2680 ha->device_type |= DT_ZIO_SUPPORTED; 2681 ha->device_type |= DT_FWI2; 2682 ha->device_type |= DT_IIDMA; 2683 ha->device_type |= DT_T10_PI; 2684 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2685 break; 2686 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2687 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2688 ha->isp_type |= DT_ISP2281; 2689 ha->device_type |= DT_ZIO_SUPPORTED; 2690 ha->device_type |= DT_FWI2; 2691 ha->device_type |= DT_IIDMA; 2692 ha->device_type |= DT_T10_PI; 2693 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2694 break; 2695 } 2696 2697 if (IS_QLA82XX(ha)) 2698 ha->port_no = ha->portnum & 1; 2699 else { 2700 /* Get adapter physical port no from interrupt pin register. */ 2701 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2702 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2703 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2704 ha->port_no--; 2705 else 2706 ha->port_no = !(ha->port_no & 1); 2707 } 2708 2709 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2710 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2711 ha->device_type, ha->port_no, ha->fw_srisc_address); 2712 } 2713 2714 static void 2715 qla2xxx_scan_start(struct Scsi_Host *shost) 2716 { 2717 scsi_qla_host_t *vha = shost_priv(shost); 2718 2719 if (vha->hw->flags.running_gold_fw) 2720 return; 2721 2722 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2723 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2724 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2725 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2726 } 2727 2728 static int 2729 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2730 { 2731 scsi_qla_host_t *vha = shost_priv(shost); 2732 2733 if (test_bit(UNLOADING, &vha->dpc_flags)) 2734 return 1; 2735 if (!vha->host) 2736 return 1; 2737 if (time > vha->hw->loop_reset_delay * HZ) 2738 return 1; 2739 2740 return atomic_read(&vha->loop_state) == LOOP_READY; 2741 } 2742 2743 static void qla2x00_iocb_work_fn(struct work_struct *work) 2744 { 2745 struct scsi_qla_host *vha = container_of(work, 2746 struct scsi_qla_host, iocb_work); 2747 struct qla_hw_data *ha = vha->hw; 2748 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2749 int i = 2; 2750 unsigned long flags; 2751 2752 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2753 return; 2754 2755 while (!list_empty(&vha->work_list) && i > 0) { 2756 qla2x00_do_work(vha); 2757 i--; 2758 } 2759 2760 spin_lock_irqsave(&vha->work_lock, flags); 2761 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2762 spin_unlock_irqrestore(&vha->work_lock, flags); 2763 } 2764 2765 /* 2766 * PCI driver interface 2767 */ 2768 static int 2769 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2770 { 2771 int ret = -ENODEV; 2772 struct Scsi_Host *host; 2773 scsi_qla_host_t *base_vha = NULL; 2774 struct qla_hw_data *ha; 2775 char pci_info[30]; 2776 char fw_str[30], wq_name[30]; 2777 struct scsi_host_template *sht; 2778 int bars, mem_only = 0; 2779 uint16_t req_length = 0, rsp_length = 0; 2780 struct req_que *req = NULL; 2781 struct rsp_que *rsp = NULL; 2782 int i; 2783 2784 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2785 sht = &qla2xxx_driver_template; 2786 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2787 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2788 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2789 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2790 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2791 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2792 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2793 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2794 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2795 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2796 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2797 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2798 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2799 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2800 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2801 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2802 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2803 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2804 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2805 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2806 mem_only = 1; 2807 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2808 "Mem only adapter.\n"); 2809 } 2810 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2811 "Bars=%d.\n", bars); 2812 2813 if (mem_only) { 2814 if (pci_enable_device_mem(pdev)) 2815 return ret; 2816 } else { 2817 if (pci_enable_device(pdev)) 2818 return ret; 2819 } 2820 2821 /* This may fail but that's ok */ 2822 pci_enable_pcie_error_reporting(pdev); 2823 2824 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2825 if (!ha) { 2826 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2827 "Unable to allocate memory for ha.\n"); 2828 goto disable_device; 2829 } 2830 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2831 "Memory allocated for ha=%p.\n", ha); 2832 ha->pdev = pdev; 2833 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2834 spin_lock_init(&ha->tgt.q_full_lock); 2835 spin_lock_init(&ha->tgt.sess_lock); 2836 spin_lock_init(&ha->tgt.atio_lock); 2837 2838 atomic_set(&ha->nvme_active_aen_cnt, 0); 2839 2840 /* Clear our data area */ 2841 ha->bars = bars; 2842 ha->mem_only = mem_only; 2843 spin_lock_init(&ha->hardware_lock); 2844 spin_lock_init(&ha->vport_slock); 2845 mutex_init(&ha->selflogin_lock); 2846 mutex_init(&ha->optrom_mutex); 2847 2848 /* Set ISP-type information. */ 2849 qla2x00_set_isp_flags(ha); 2850 2851 /* Set EEH reset type to fundamental if required by hba */ 2852 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 2853 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2854 pdev->needs_freset = 1; 2855 2856 ha->prev_topology = 0; 2857 ha->init_cb_size = sizeof(init_cb_t); 2858 ha->link_data_rate = PORT_SPEED_UNKNOWN; 2859 ha->optrom_size = OPTROM_SIZE_2300; 2860 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 2861 atomic_set(&ha->num_pend_mbx_stage1, 0); 2862 atomic_set(&ha->num_pend_mbx_stage2, 0); 2863 atomic_set(&ha->num_pend_mbx_stage3, 0); 2864 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 2865 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 2866 2867 /* Assign ISP specific operations. */ 2868 if (IS_QLA2100(ha)) { 2869 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2870 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 2871 req_length = REQUEST_ENTRY_CNT_2100; 2872 rsp_length = RESPONSE_ENTRY_CNT_2100; 2873 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2874 ha->gid_list_info_size = 4; 2875 ha->flash_conf_off = ~0; 2876 ha->flash_data_off = ~0; 2877 ha->nvram_conf_off = ~0; 2878 ha->nvram_data_off = ~0; 2879 ha->isp_ops = &qla2100_isp_ops; 2880 } else if (IS_QLA2200(ha)) { 2881 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2882 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 2883 req_length = REQUEST_ENTRY_CNT_2200; 2884 rsp_length = RESPONSE_ENTRY_CNT_2100; 2885 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 2886 ha->gid_list_info_size = 4; 2887 ha->flash_conf_off = ~0; 2888 ha->flash_data_off = ~0; 2889 ha->nvram_conf_off = ~0; 2890 ha->nvram_data_off = ~0; 2891 ha->isp_ops = &qla2100_isp_ops; 2892 } else if (IS_QLA23XX(ha)) { 2893 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 2894 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2895 req_length = REQUEST_ENTRY_CNT_2200; 2896 rsp_length = RESPONSE_ENTRY_CNT_2300; 2897 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2898 ha->gid_list_info_size = 6; 2899 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2900 ha->optrom_size = OPTROM_SIZE_2322; 2901 ha->flash_conf_off = ~0; 2902 ha->flash_data_off = ~0; 2903 ha->nvram_conf_off = ~0; 2904 ha->nvram_data_off = ~0; 2905 ha->isp_ops = &qla2300_isp_ops; 2906 } else if (IS_QLA24XX_TYPE(ha)) { 2907 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2908 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2909 req_length = REQUEST_ENTRY_CNT_24XX; 2910 rsp_length = RESPONSE_ENTRY_CNT_2300; 2911 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2912 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2913 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2914 ha->gid_list_info_size = 8; 2915 ha->optrom_size = OPTROM_SIZE_24XX; 2916 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 2917 ha->isp_ops = &qla24xx_isp_ops; 2918 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2919 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2920 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2921 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2922 } else if (IS_QLA25XX(ha)) { 2923 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2924 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2925 req_length = REQUEST_ENTRY_CNT_24XX; 2926 rsp_length = RESPONSE_ENTRY_CNT_2300; 2927 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2928 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2929 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 2930 ha->gid_list_info_size = 8; 2931 ha->optrom_size = OPTROM_SIZE_25XX; 2932 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2933 ha->isp_ops = &qla25xx_isp_ops; 2934 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2935 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2936 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2937 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2938 } else if (IS_QLA81XX(ha)) { 2939 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2940 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2941 req_length = REQUEST_ENTRY_CNT_24XX; 2942 rsp_length = RESPONSE_ENTRY_CNT_2300; 2943 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2944 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2945 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2946 ha->gid_list_info_size = 8; 2947 ha->optrom_size = OPTROM_SIZE_81XX; 2948 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2949 ha->isp_ops = &qla81xx_isp_ops; 2950 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2951 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2952 ha->nvram_conf_off = ~0; 2953 ha->nvram_data_off = ~0; 2954 } else if (IS_QLA82XX(ha)) { 2955 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2956 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2957 req_length = REQUEST_ENTRY_CNT_82XX; 2958 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2959 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2960 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2961 ha->gid_list_info_size = 8; 2962 ha->optrom_size = OPTROM_SIZE_82XX; 2963 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2964 ha->isp_ops = &qla82xx_isp_ops; 2965 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2966 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2967 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2968 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2969 } else if (IS_QLA8044(ha)) { 2970 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2971 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2972 req_length = REQUEST_ENTRY_CNT_82XX; 2973 rsp_length = RESPONSE_ENTRY_CNT_82XX; 2974 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2975 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2976 ha->gid_list_info_size = 8; 2977 ha->optrom_size = OPTROM_SIZE_83XX; 2978 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2979 ha->isp_ops = &qla8044_isp_ops; 2980 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2981 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 2982 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 2983 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 2984 } else if (IS_QLA83XX(ha)) { 2985 ha->portnum = PCI_FUNC(ha->pdev->devfn); 2986 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 2987 ha->mbx_count = MAILBOX_REGISTER_COUNT; 2988 req_length = REQUEST_ENTRY_CNT_83XX; 2989 rsp_length = RESPONSE_ENTRY_CNT_83XX; 2990 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 2991 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 2992 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 2993 ha->gid_list_info_size = 8; 2994 ha->optrom_size = OPTROM_SIZE_83XX; 2995 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 2996 ha->isp_ops = &qla83xx_isp_ops; 2997 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 2998 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 2999 ha->nvram_conf_off = ~0; 3000 ha->nvram_data_off = ~0; 3001 } else if (IS_QLAFX00(ha)) { 3002 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3003 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3004 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3005 req_length = REQUEST_ENTRY_CNT_FX00; 3006 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3007 ha->isp_ops = &qlafx00_isp_ops; 3008 ha->port_down_retry_count = 30; /* default value */ 3009 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3010 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3011 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3012 ha->mr.fw_hbt_en = 1; 3013 ha->mr.host_info_resend = false; 3014 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3015 } else if (IS_QLA27XX(ha)) { 3016 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3017 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3018 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3019 req_length = REQUEST_ENTRY_CNT_83XX; 3020 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3021 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3022 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3023 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3024 ha->gid_list_info_size = 8; 3025 ha->optrom_size = OPTROM_SIZE_83XX; 3026 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3027 ha->isp_ops = &qla27xx_isp_ops; 3028 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3029 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3030 ha->nvram_conf_off = ~0; 3031 ha->nvram_data_off = ~0; 3032 } else if (IS_QLA28XX(ha)) { 3033 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3034 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3035 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3036 req_length = REQUEST_ENTRY_CNT_24XX; 3037 rsp_length = RESPONSE_ENTRY_CNT_2300; 3038 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3039 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3040 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3041 ha->gid_list_info_size = 8; 3042 ha->optrom_size = OPTROM_SIZE_28XX; 3043 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3044 ha->isp_ops = &qla27xx_isp_ops; 3045 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3046 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3047 ha->nvram_conf_off = ~0; 3048 ha->nvram_data_off = ~0; 3049 } 3050 3051 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3052 "mbx_count=%d, req_length=%d, " 3053 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3054 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3055 "max_fibre_devices=%d.\n", 3056 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3057 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3058 ha->nvram_npiv_size, ha->max_fibre_devices); 3059 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3060 "isp_ops=%p, flash_conf_off=%d, " 3061 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3062 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3063 ha->nvram_conf_off, ha->nvram_data_off); 3064 3065 /* Configure PCI I/O space */ 3066 ret = ha->isp_ops->iospace_config(ha); 3067 if (ret) 3068 goto iospace_config_failed; 3069 3070 ql_log_pci(ql_log_info, pdev, 0x001d, 3071 "Found an ISP%04X irq %d iobase 0x%p.\n", 3072 pdev->device, pdev->irq, ha->iobase); 3073 mutex_init(&ha->vport_lock); 3074 mutex_init(&ha->mq_lock); 3075 init_completion(&ha->mbx_cmd_comp); 3076 complete(&ha->mbx_cmd_comp); 3077 init_completion(&ha->mbx_intr_comp); 3078 init_completion(&ha->dcbx_comp); 3079 init_completion(&ha->lb_portup_comp); 3080 3081 set_bit(0, (unsigned long *) ha->vp_idx_map); 3082 3083 qla2x00_config_dma_addressing(ha); 3084 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3085 "64 Bit addressing is %s.\n", 3086 ha->flags.enable_64bit_addressing ? "enable" : 3087 "disable"); 3088 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3089 if (ret) { 3090 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3091 "Failed to allocate memory for adapter, aborting.\n"); 3092 3093 goto probe_hw_failed; 3094 } 3095 3096 req->max_q_depth = MAX_Q_DEPTH; 3097 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3098 req->max_q_depth = ql2xmaxqdepth; 3099 3100 3101 base_vha = qla2x00_create_host(sht, ha); 3102 if (!base_vha) { 3103 ret = -ENOMEM; 3104 goto probe_hw_failed; 3105 } 3106 3107 pci_set_drvdata(pdev, base_vha); 3108 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3109 3110 host = base_vha->host; 3111 base_vha->req = req; 3112 if (IS_QLA2XXX_MIDTYPE(ha)) 3113 base_vha->mgmt_svr_loop_id = 3114 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3115 else 3116 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3117 base_vha->vp_idx; 3118 3119 /* Setup fcport template structure. */ 3120 ha->mr.fcport.vha = base_vha; 3121 ha->mr.fcport.port_type = FCT_UNKNOWN; 3122 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3123 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3124 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3125 ha->mr.fcport.scan_state = 1; 3126 3127 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3128 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3129 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3130 3131 /* Set the SG table size based on ISP type */ 3132 if (!IS_FWI2_CAPABLE(ha)) { 3133 if (IS_QLA2100(ha)) 3134 host->sg_tablesize = 32; 3135 } else { 3136 if (!IS_QLA82XX(ha)) 3137 host->sg_tablesize = QLA_SG_ALL; 3138 } 3139 host->max_id = ha->max_fibre_devices; 3140 host->cmd_per_lun = 3; 3141 host->unique_id = host->host_no; 3142 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3143 host->max_cmd_len = 32; 3144 else 3145 host->max_cmd_len = MAX_CMDSZ; 3146 host->max_channel = MAX_BUSES - 1; 3147 /* Older HBAs support only 16-bit LUNs */ 3148 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3149 ql2xmaxlun > 0xffff) 3150 host->max_lun = 0xffff; 3151 else 3152 host->max_lun = ql2xmaxlun; 3153 host->transportt = qla2xxx_transport_template; 3154 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3155 3156 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3157 "max_id=%d this_id=%d " 3158 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3159 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3160 host->this_id, host->cmd_per_lun, host->unique_id, 3161 host->max_cmd_len, host->max_channel, host->max_lun, 3162 host->transportt, sht->vendor_id); 3163 3164 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn); 3165 3166 /* Set up the irqs */ 3167 ret = qla2x00_request_irqs(ha, rsp); 3168 if (ret) 3169 goto probe_failed; 3170 3171 /* Alloc arrays of request and response ring ptrs */ 3172 ret = qla2x00_alloc_queues(ha, req, rsp); 3173 if (ret) { 3174 ql_log(ql_log_fatal, base_vha, 0x003d, 3175 "Failed to allocate memory for queue pointers..." 3176 "aborting.\n"); 3177 ret = -ENODEV; 3178 goto probe_failed; 3179 } 3180 3181 if (ha->mqenable) { 3182 /* number of hardware queues supported by blk/scsi-mq*/ 3183 host->nr_hw_queues = ha->max_qpairs; 3184 3185 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3186 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3187 } else { 3188 if (ql2xnvmeenable) { 3189 host->nr_hw_queues = ha->max_qpairs; 3190 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3191 "FC-NVMe support is enabled, HW queues=%d\n", 3192 host->nr_hw_queues); 3193 } else { 3194 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3195 "blk/scsi-mq disabled.\n"); 3196 } 3197 } 3198 3199 qlt_probe_one_stage1(base_vha, ha); 3200 3201 pci_save_state(pdev); 3202 3203 /* Assign back pointers */ 3204 rsp->req = req; 3205 req->rsp = rsp; 3206 3207 if (IS_QLAFX00(ha)) { 3208 ha->rsp_q_map[0] = rsp; 3209 ha->req_q_map[0] = req; 3210 set_bit(0, ha->req_qid_map); 3211 set_bit(0, ha->rsp_qid_map); 3212 } 3213 3214 /* FWI2-capable only. */ 3215 req->req_q_in = &ha->iobase->isp24.req_q_in; 3216 req->req_q_out = &ha->iobase->isp24.req_q_out; 3217 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3218 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3219 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3220 IS_QLA28XX(ha)) { 3221 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3222 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3223 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3224 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3225 } 3226 3227 if (IS_QLAFX00(ha)) { 3228 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3229 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3230 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3231 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3232 } 3233 3234 if (IS_P3P_TYPE(ha)) { 3235 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3236 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3237 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3238 } 3239 3240 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3241 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3242 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3243 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3244 "req->req_q_in=%p req->req_q_out=%p " 3245 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3246 req->req_q_in, req->req_q_out, 3247 rsp->rsp_q_in, rsp->rsp_q_out); 3248 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3249 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3250 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3251 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3252 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3253 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3254 3255 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0); 3256 if (unlikely(!ha->wq)) { 3257 ret = -ENOMEM; 3258 goto probe_failed; 3259 } 3260 3261 if (ha->isp_ops->initialize_adapter(base_vha)) { 3262 ql_log(ql_log_fatal, base_vha, 0x00d6, 3263 "Failed to initialize adapter - Adapter flags %x.\n", 3264 base_vha->device_flags); 3265 3266 if (IS_QLA82XX(ha)) { 3267 qla82xx_idc_lock(ha); 3268 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3269 QLA8XXX_DEV_FAILED); 3270 qla82xx_idc_unlock(ha); 3271 ql_log(ql_log_fatal, base_vha, 0x00d7, 3272 "HW State: FAILED.\n"); 3273 } else if (IS_QLA8044(ha)) { 3274 qla8044_idc_lock(ha); 3275 qla8044_wr_direct(base_vha, 3276 QLA8044_CRB_DEV_STATE_INDEX, 3277 QLA8XXX_DEV_FAILED); 3278 qla8044_idc_unlock(ha); 3279 ql_log(ql_log_fatal, base_vha, 0x0150, 3280 "HW State: FAILED.\n"); 3281 } 3282 3283 ret = -ENODEV; 3284 goto probe_failed; 3285 } 3286 3287 if (IS_QLAFX00(ha)) 3288 host->can_queue = QLAFX00_MAX_CANQUEUE; 3289 else 3290 host->can_queue = req->num_outstanding_cmds - 10; 3291 3292 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3293 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3294 host->can_queue, base_vha->req, 3295 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3296 3297 if (ha->mqenable) { 3298 bool startit = false; 3299 3300 if (QLA_TGT_MODE_ENABLED()) 3301 startit = false; 3302 3303 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) 3304 startit = true; 3305 3306 /* Create start of day qpairs for Block MQ */ 3307 for (i = 0; i < ha->max_qpairs; i++) 3308 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3309 } 3310 qla_init_iocb_limit(base_vha); 3311 3312 if (ha->flags.running_gold_fw) 3313 goto skip_dpc; 3314 3315 /* 3316 * Startup the kernel thread for this host adapter 3317 */ 3318 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3319 "%s_dpc", base_vha->host_str); 3320 if (IS_ERR(ha->dpc_thread)) { 3321 ql_log(ql_log_fatal, base_vha, 0x00ed, 3322 "Failed to start DPC thread.\n"); 3323 ret = PTR_ERR(ha->dpc_thread); 3324 ha->dpc_thread = NULL; 3325 goto probe_failed; 3326 } 3327 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3328 "DPC thread started successfully.\n"); 3329 3330 /* 3331 * If we're not coming up in initiator mode, we might sit for 3332 * a while without waking up the dpc thread, which leads to a 3333 * stuck process warning. So just kick the dpc once here and 3334 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3335 */ 3336 qla2xxx_wake_dpc(base_vha); 3337 3338 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3339 3340 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3341 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3342 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); 3343 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3344 3345 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3346 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); 3347 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3348 INIT_WORK(&ha->idc_state_handler, 3349 qla83xx_idc_state_handler_work); 3350 INIT_WORK(&ha->nic_core_unrecoverable, 3351 qla83xx_nic_core_unrecoverable_work); 3352 } 3353 3354 skip_dpc: 3355 list_add_tail(&base_vha->list, &ha->vp_list); 3356 base_vha->host->irq = ha->pdev->irq; 3357 3358 /* Initialized the timer */ 3359 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3360 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3361 "Started qla2x00_timer with " 3362 "interval=%d.\n", WATCH_INTERVAL); 3363 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3364 "Detected hba at address=%p.\n", 3365 ha); 3366 3367 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3368 if (ha->fw_attributes & BIT_4) { 3369 int prot = 0, guard; 3370 3371 base_vha->flags.difdix_supported = 1; 3372 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3373 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3374 if (ql2xenabledif == 1) 3375 prot = SHOST_DIX_TYPE0_PROTECTION; 3376 if (ql2xprotmask) 3377 scsi_host_set_prot(host, ql2xprotmask); 3378 else 3379 scsi_host_set_prot(host, 3380 prot | SHOST_DIF_TYPE1_PROTECTION 3381 | SHOST_DIF_TYPE2_PROTECTION 3382 | SHOST_DIF_TYPE3_PROTECTION 3383 | SHOST_DIX_TYPE1_PROTECTION 3384 | SHOST_DIX_TYPE2_PROTECTION 3385 | SHOST_DIX_TYPE3_PROTECTION); 3386 3387 guard = SHOST_DIX_GUARD_CRC; 3388 3389 if (IS_PI_IPGUARD_CAPABLE(ha) && 3390 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3391 guard |= SHOST_DIX_GUARD_IP; 3392 3393 if (ql2xprotguard) 3394 scsi_host_set_guard(host, ql2xprotguard); 3395 else 3396 scsi_host_set_guard(host, guard); 3397 } else 3398 base_vha->flags.difdix_supported = 0; 3399 } 3400 3401 ha->isp_ops->enable_intrs(ha); 3402 3403 if (IS_QLAFX00(ha)) { 3404 ret = qlafx00_fx_disc(base_vha, 3405 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3406 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3407 QLA_SG_ALL : 128; 3408 } 3409 3410 ret = scsi_add_host(host, &pdev->dev); 3411 if (ret) 3412 goto probe_failed; 3413 3414 base_vha->flags.init_done = 1; 3415 base_vha->flags.online = 1; 3416 ha->prev_minidump_failed = 0; 3417 3418 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3419 "Init done and hba is online.\n"); 3420 3421 if (qla_ini_mode_enabled(base_vha) || 3422 qla_dual_mode_enabled(base_vha)) 3423 scsi_scan_host(host); 3424 else 3425 ql_dbg(ql_dbg_init, base_vha, 0x0122, 3426 "skipping scsi_scan_host() for non-initiator port\n"); 3427 3428 qla2x00_alloc_sysfs_attr(base_vha); 3429 3430 if (IS_QLAFX00(ha)) { 3431 ret = qlafx00_fx_disc(base_vha, 3432 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3433 3434 /* Register system information */ 3435 ret = qlafx00_fx_disc(base_vha, 3436 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3437 } 3438 3439 qla2x00_init_host_attr(base_vha); 3440 3441 qla2x00_dfs_setup(base_vha); 3442 3443 ql_log(ql_log_info, base_vha, 0x00fb, 3444 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3445 ql_log(ql_log_info, base_vha, 0x00fc, 3446 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3447 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3448 sizeof(pci_info)), 3449 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3450 base_vha->host_no, 3451 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3452 3453 qlt_add_target(ha, base_vha); 3454 3455 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3456 3457 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3458 return -ENODEV; 3459 3460 return 0; 3461 3462 probe_failed: 3463 if (base_vha->gnl.l) { 3464 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3465 base_vha->gnl.l, base_vha->gnl.ldma); 3466 base_vha->gnl.l = NULL; 3467 } 3468 3469 if (base_vha->timer_active) 3470 qla2x00_stop_timer(base_vha); 3471 base_vha->flags.online = 0; 3472 if (ha->dpc_thread) { 3473 struct task_struct *t = ha->dpc_thread; 3474 3475 ha->dpc_thread = NULL; 3476 kthread_stop(t); 3477 } 3478 3479 qla2x00_free_device(base_vha); 3480 scsi_host_put(base_vha->host); 3481 /* 3482 * Need to NULL out local req/rsp after 3483 * qla2x00_free_device => qla2x00_free_queues frees 3484 * what these are pointing to. Or else we'll 3485 * fall over below in qla2x00_free_req/rsp_que. 3486 */ 3487 req = NULL; 3488 rsp = NULL; 3489 3490 probe_hw_failed: 3491 qla2x00_mem_free(ha); 3492 qla2x00_free_req_que(ha, req); 3493 qla2x00_free_rsp_que(ha, rsp); 3494 qla2x00_clear_drv_active(ha); 3495 3496 iospace_config_failed: 3497 if (IS_P3P_TYPE(ha)) { 3498 if (!ha->nx_pcibase) 3499 iounmap((device_reg_t *)ha->nx_pcibase); 3500 if (!ql2xdbwr) 3501 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3502 } else { 3503 if (ha->iobase) 3504 iounmap(ha->iobase); 3505 if (ha->cregbase) 3506 iounmap(ha->cregbase); 3507 } 3508 pci_release_selected_regions(ha->pdev, ha->bars); 3509 kfree(ha); 3510 3511 disable_device: 3512 pci_disable_device(pdev); 3513 return ret; 3514 } 3515 3516 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3517 { 3518 scsi_qla_host_t *vp; 3519 unsigned long flags; 3520 struct qla_hw_data *ha; 3521 3522 if (!base_vha) 3523 return; 3524 3525 ha = base_vha->hw; 3526 3527 spin_lock_irqsave(&ha->vport_slock, flags); 3528 list_for_each_entry(vp, &ha->vp_list, list) 3529 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3530 3531 /* 3532 * Indicate device removal to prevent future board_disable 3533 * and wait until any pending board_disable has completed. 3534 */ 3535 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3536 spin_unlock_irqrestore(&ha->vport_slock, flags); 3537 } 3538 3539 static void 3540 qla2x00_shutdown(struct pci_dev *pdev) 3541 { 3542 scsi_qla_host_t *vha; 3543 struct qla_hw_data *ha; 3544 3545 vha = pci_get_drvdata(pdev); 3546 ha = vha->hw; 3547 3548 ql_log(ql_log_info, vha, 0xfffa, 3549 "Adapter shutdown\n"); 3550 3551 /* 3552 * Prevent future board_disable and wait 3553 * until any pending board_disable has completed. 3554 */ 3555 __qla_set_remove_flag(vha); 3556 cancel_work_sync(&ha->board_disable); 3557 3558 if (!atomic_read(&pdev->enable_cnt)) 3559 return; 3560 3561 /* Notify ISPFX00 firmware */ 3562 if (IS_QLAFX00(ha)) 3563 qlafx00_driver_shutdown(vha, 20); 3564 3565 /* Turn-off FCE trace */ 3566 if (ha->flags.fce_enabled) { 3567 qla2x00_disable_fce_trace(vha, NULL, NULL); 3568 ha->flags.fce_enabled = 0; 3569 } 3570 3571 /* Turn-off EFT trace */ 3572 if (ha->eft) 3573 qla2x00_disable_eft_trace(vha); 3574 3575 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3576 IS_QLA28XX(ha)) { 3577 if (ha->flags.fw_started) 3578 qla2x00_abort_isp_cleanup(vha); 3579 } else { 3580 /* Stop currently executing firmware. */ 3581 qla2x00_try_to_stop_firmware(vha); 3582 } 3583 3584 /* Disable timer */ 3585 if (vha->timer_active) 3586 qla2x00_stop_timer(vha); 3587 3588 /* Turn adapter off line */ 3589 vha->flags.online = 0; 3590 3591 /* turn-off interrupts on the card */ 3592 if (ha->interrupts_on) { 3593 vha->flags.init_done = 0; 3594 ha->isp_ops->disable_intrs(ha); 3595 } 3596 3597 qla2x00_free_irqs(vha); 3598 3599 qla2x00_free_fw_dump(ha); 3600 3601 pci_disable_device(pdev); 3602 ql_log(ql_log_info, vha, 0xfffe, 3603 "Adapter shutdown successfully.\n"); 3604 } 3605 3606 /* Deletes all the virtual ports for a given ha */ 3607 static void 3608 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3609 { 3610 scsi_qla_host_t *vha; 3611 unsigned long flags; 3612 3613 mutex_lock(&ha->vport_lock); 3614 while (ha->cur_vport_count) { 3615 spin_lock_irqsave(&ha->vport_slock, flags); 3616 3617 BUG_ON(base_vha->list.next == &ha->vp_list); 3618 /* This assumes first entry in ha->vp_list is always base vha */ 3619 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3620 scsi_host_get(vha->host); 3621 3622 spin_unlock_irqrestore(&ha->vport_slock, flags); 3623 mutex_unlock(&ha->vport_lock); 3624 3625 qla_nvme_delete(vha); 3626 3627 fc_vport_terminate(vha->fc_vport); 3628 scsi_host_put(vha->host); 3629 3630 mutex_lock(&ha->vport_lock); 3631 } 3632 mutex_unlock(&ha->vport_lock); 3633 } 3634 3635 /* Stops all deferred work threads */ 3636 static void 3637 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3638 { 3639 /* Cancel all work and destroy DPC workqueues */ 3640 if (ha->dpc_lp_wq) { 3641 cancel_work_sync(&ha->idc_aen); 3642 destroy_workqueue(ha->dpc_lp_wq); 3643 ha->dpc_lp_wq = NULL; 3644 } 3645 3646 if (ha->dpc_hp_wq) { 3647 cancel_work_sync(&ha->nic_core_reset); 3648 cancel_work_sync(&ha->idc_state_handler); 3649 cancel_work_sync(&ha->nic_core_unrecoverable); 3650 destroy_workqueue(ha->dpc_hp_wq); 3651 ha->dpc_hp_wq = NULL; 3652 } 3653 3654 /* Kill the kernel thread for this host */ 3655 if (ha->dpc_thread) { 3656 struct task_struct *t = ha->dpc_thread; 3657 3658 /* 3659 * qla2xxx_wake_dpc checks for ->dpc_thread 3660 * so we need to zero it out. 3661 */ 3662 ha->dpc_thread = NULL; 3663 kthread_stop(t); 3664 } 3665 } 3666 3667 static void 3668 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3669 { 3670 if (IS_QLA82XX(ha)) { 3671 3672 iounmap((device_reg_t *)ha->nx_pcibase); 3673 if (!ql2xdbwr) 3674 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3675 } else { 3676 if (ha->iobase) 3677 iounmap(ha->iobase); 3678 3679 if (ha->cregbase) 3680 iounmap(ha->cregbase); 3681 3682 if (ha->mqiobase) 3683 iounmap(ha->mqiobase); 3684 3685 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) && 3686 ha->msixbase) 3687 iounmap(ha->msixbase); 3688 } 3689 } 3690 3691 static void 3692 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3693 { 3694 if (IS_QLA8044(ha)) { 3695 qla8044_idc_lock(ha); 3696 qla8044_clear_drv_active(ha); 3697 qla8044_idc_unlock(ha); 3698 } else if (IS_QLA82XX(ha)) { 3699 qla82xx_idc_lock(ha); 3700 qla82xx_clear_drv_active(ha); 3701 qla82xx_idc_unlock(ha); 3702 } 3703 } 3704 3705 static void 3706 qla2x00_remove_one(struct pci_dev *pdev) 3707 { 3708 scsi_qla_host_t *base_vha; 3709 struct qla_hw_data *ha; 3710 3711 base_vha = pci_get_drvdata(pdev); 3712 ha = base_vha->hw; 3713 ql_log(ql_log_info, base_vha, 0xb079, 3714 "Removing driver\n"); 3715 __qla_set_remove_flag(base_vha); 3716 cancel_work_sync(&ha->board_disable); 3717 3718 /* 3719 * If the PCI device is disabled then there was a PCI-disconnect and 3720 * qla2x00_disable_board_on_pci_error has taken care of most of the 3721 * resources. 3722 */ 3723 if (!atomic_read(&pdev->enable_cnt)) { 3724 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3725 base_vha->gnl.l, base_vha->gnl.ldma); 3726 base_vha->gnl.l = NULL; 3727 scsi_host_put(base_vha->host); 3728 kfree(ha); 3729 pci_set_drvdata(pdev, NULL); 3730 return; 3731 } 3732 qla2x00_wait_for_hba_ready(base_vha); 3733 3734 /* 3735 * if UNLOADING flag is already set, then continue unload, 3736 * where it was set first. 3737 */ 3738 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3739 return; 3740 3741 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3742 IS_QLA28XX(ha)) { 3743 if (ha->flags.fw_started) 3744 qla2x00_abort_isp_cleanup(base_vha); 3745 } else if (!IS_QLAFX00(ha)) { 3746 if (IS_QLA8031(ha)) { 3747 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3748 "Clearing fcoe driver presence.\n"); 3749 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3750 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3751 "Error while clearing DRV-Presence.\n"); 3752 } 3753 3754 qla2x00_try_to_stop_firmware(base_vha); 3755 } 3756 3757 qla2x00_wait_for_sess_deletion(base_vha); 3758 3759 qla_nvme_delete(base_vha); 3760 3761 dma_free_coherent(&ha->pdev->dev, 3762 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3763 3764 base_vha->gnl.l = NULL; 3765 3766 vfree(base_vha->scan.l); 3767 3768 if (IS_QLAFX00(ha)) 3769 qlafx00_driver_shutdown(base_vha, 20); 3770 3771 qla2x00_delete_all_vps(ha, base_vha); 3772 3773 qla2x00_dfs_remove(base_vha); 3774 3775 qla84xx_put_chip(base_vha); 3776 3777 /* Disable timer */ 3778 if (base_vha->timer_active) 3779 qla2x00_stop_timer(base_vha); 3780 3781 base_vha->flags.online = 0; 3782 3783 /* free DMA memory */ 3784 if (ha->exlogin_buf) 3785 qla2x00_free_exlogin_buffer(ha); 3786 3787 /* free DMA memory */ 3788 if (ha->exchoffld_buf) 3789 qla2x00_free_exchoffld_buffer(ha); 3790 3791 qla2x00_destroy_deferred_work(ha); 3792 3793 qlt_remove_target(ha, base_vha); 3794 3795 qla2x00_free_sysfs_attr(base_vha, true); 3796 3797 fc_remove_host(base_vha->host); 3798 qlt_remove_target_resources(ha); 3799 3800 scsi_remove_host(base_vha->host); 3801 3802 qla2x00_free_device(base_vha); 3803 3804 qla2x00_clear_drv_active(ha); 3805 3806 scsi_host_put(base_vha->host); 3807 3808 qla2x00_unmap_iobases(ha); 3809 3810 pci_release_selected_regions(ha->pdev, ha->bars); 3811 kfree(ha); 3812 3813 pci_disable_pcie_error_reporting(pdev); 3814 3815 pci_disable_device(pdev); 3816 } 3817 3818 static inline void 3819 qla24xx_free_purex_list(struct purex_list *list) 3820 { 3821 struct list_head *item, *next; 3822 ulong flags; 3823 3824 spin_lock_irqsave(&list->lock, flags); 3825 list_for_each_safe(item, next, &list->head) { 3826 list_del(item); 3827 kfree(list_entry(item, struct purex_item, list)); 3828 } 3829 spin_unlock_irqrestore(&list->lock, flags); 3830 } 3831 3832 static void 3833 qla2x00_free_device(scsi_qla_host_t *vha) 3834 { 3835 struct qla_hw_data *ha = vha->hw; 3836 3837 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 3838 3839 /* Disable timer */ 3840 if (vha->timer_active) 3841 qla2x00_stop_timer(vha); 3842 3843 qla25xx_delete_queues(vha); 3844 vha->flags.online = 0; 3845 3846 /* turn-off interrupts on the card */ 3847 if (ha->interrupts_on) { 3848 vha->flags.init_done = 0; 3849 ha->isp_ops->disable_intrs(ha); 3850 } 3851 3852 qla2x00_free_fcports(vha); 3853 3854 qla2x00_free_irqs(vha); 3855 3856 /* Flush the work queue and remove it */ 3857 if (ha->wq) { 3858 flush_workqueue(ha->wq); 3859 destroy_workqueue(ha->wq); 3860 ha->wq = NULL; 3861 } 3862 3863 3864 qla24xx_free_purex_list(&vha->purex_list); 3865 3866 qla2x00_mem_free(ha); 3867 3868 qla82xx_md_free(vha); 3869 3870 qla2x00_free_queues(ha); 3871 } 3872 3873 void qla2x00_free_fcports(struct scsi_qla_host *vha) 3874 { 3875 fc_port_t *fcport, *tfcport; 3876 3877 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 3878 qla2x00_free_fcport(fcport); 3879 } 3880 3881 static inline void 3882 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 3883 { 3884 int now; 3885 3886 if (!fcport->rport) 3887 return; 3888 3889 if (fcport->rport) { 3890 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 3891 "%s %8phN. rport %p roles %x\n", 3892 __func__, fcport->port_name, fcport->rport, 3893 fcport->rport->roles); 3894 fc_remote_port_delete(fcport->rport); 3895 } 3896 qlt_do_generation_tick(vha, &now); 3897 } 3898 3899 /* 3900 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 3901 * 3902 * Input: ha = adapter block pointer. fcport = port structure pointer. 3903 * 3904 * Return: None. 3905 * 3906 * Context: 3907 */ 3908 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 3909 int do_login) 3910 { 3911 if (IS_QLAFX00(vha->hw)) { 3912 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3913 qla2x00_schedule_rport_del(vha, fcport); 3914 return; 3915 } 3916 3917 if (atomic_read(&fcport->state) == FCS_ONLINE && 3918 vha->vp_idx == fcport->vha->vp_idx) { 3919 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3920 qla2x00_schedule_rport_del(vha, fcport); 3921 } 3922 /* 3923 * We may need to retry the login, so don't change the state of the 3924 * port but do the retries. 3925 */ 3926 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 3927 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 3928 3929 if (!do_login) 3930 return; 3931 3932 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 3933 } 3934 3935 void 3936 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 3937 { 3938 fc_port_t *fcport; 3939 3940 ql_dbg(ql_dbg_disc, vha, 0x20f1, 3941 "Mark all dev lost\n"); 3942 3943 list_for_each_entry(fcport, &vha->vp_fcports, list) { 3944 fcport->scan_state = 0; 3945 qlt_schedule_sess_for_deletion(fcport); 3946 } 3947 } 3948 3949 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 3950 { 3951 int i; 3952 3953 if (IS_FWI2_CAPABLE(ha)) 3954 return; 3955 3956 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 3957 set_bit(i, ha->loop_id_map); 3958 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 3959 set_bit(BROADCAST, ha->loop_id_map); 3960 } 3961 3962 /* 3963 * qla2x00_mem_alloc 3964 * Allocates adapter memory. 3965 * 3966 * Returns: 3967 * 0 = success. 3968 * !0 = failure. 3969 */ 3970 static int 3971 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 3972 struct req_que **req, struct rsp_que **rsp) 3973 { 3974 char name[16]; 3975 3976 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 3977 &ha->init_cb_dma, GFP_KERNEL); 3978 if (!ha->init_cb) 3979 goto fail; 3980 3981 if (qlt_mem_alloc(ha) < 0) 3982 goto fail_free_init_cb; 3983 3984 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 3985 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 3986 if (!ha->gid_list) 3987 goto fail_free_tgt_mem; 3988 3989 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 3990 if (!ha->srb_mempool) 3991 goto fail_free_gid_list; 3992 3993 if (IS_P3P_TYPE(ha)) { 3994 /* Allocate cache for CT6 Ctx. */ 3995 if (!ctx_cachep) { 3996 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 3997 sizeof(struct ct6_dsd), 0, 3998 SLAB_HWCACHE_ALIGN, NULL); 3999 if (!ctx_cachep) 4000 goto fail_free_srb_mempool; 4001 } 4002 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4003 ctx_cachep); 4004 if (!ha->ctx_mempool) 4005 goto fail_free_srb_mempool; 4006 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4007 "ctx_cachep=%p ctx_mempool=%p.\n", 4008 ctx_cachep, ha->ctx_mempool); 4009 } 4010 4011 /* Get memory for cached NVRAM */ 4012 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4013 if (!ha->nvram) 4014 goto fail_free_ctx_mempool; 4015 4016 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4017 ha->pdev->device); 4018 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4019 DMA_POOL_SIZE, 8, 0); 4020 if (!ha->s_dma_pool) 4021 goto fail_free_nvram; 4022 4023 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4024 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4025 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4026 4027 if (IS_P3P_TYPE(ha) || ql2xenabledif) { 4028 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4029 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4030 if (!ha->dl_dma_pool) { 4031 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4032 "Failed to allocate memory for dl_dma_pool.\n"); 4033 goto fail_s_dma_pool; 4034 } 4035 4036 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4037 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4038 if (!ha->fcp_cmnd_dma_pool) { 4039 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4040 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4041 goto fail_dl_dma_pool; 4042 } 4043 4044 if (ql2xenabledif) { 4045 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4046 struct dsd_dma *dsd, *nxt; 4047 uint i; 4048 /* Creata a DMA pool of buffers for DIF bundling */ 4049 ha->dif_bundl_pool = dma_pool_create(name, 4050 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4051 if (!ha->dif_bundl_pool) { 4052 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4053 "%s: failed create dif_bundl_pool\n", 4054 __func__); 4055 goto fail_dif_bundl_dma_pool; 4056 } 4057 4058 INIT_LIST_HEAD(&ha->pool.good.head); 4059 INIT_LIST_HEAD(&ha->pool.unusable.head); 4060 ha->pool.good.count = 0; 4061 ha->pool.unusable.count = 0; 4062 for (i = 0; i < 128; i++) { 4063 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4064 if (!dsd) { 4065 ql_dbg_pci(ql_dbg_init, ha->pdev, 4066 0xe0ee, "%s: failed alloc dsd\n", 4067 __func__); 4068 return 1; 4069 } 4070 ha->dif_bundle_kallocs++; 4071 4072 dsd->dsd_addr = dma_pool_alloc( 4073 ha->dif_bundl_pool, GFP_ATOMIC, 4074 &dsd->dsd_list_dma); 4075 if (!dsd->dsd_addr) { 4076 ql_dbg_pci(ql_dbg_init, ha->pdev, 4077 0xe0ee, 4078 "%s: failed alloc ->dsd_addr\n", 4079 __func__); 4080 kfree(dsd); 4081 ha->dif_bundle_kallocs--; 4082 continue; 4083 } 4084 ha->dif_bundle_dma_allocs++; 4085 4086 /* 4087 * if DMA buffer crosses 4G boundary, 4088 * put it on bad list 4089 */ 4090 if (MSD(dsd->dsd_list_dma) ^ 4091 MSD(dsd->dsd_list_dma + bufsize)) { 4092 list_add_tail(&dsd->list, 4093 &ha->pool.unusable.head); 4094 ha->pool.unusable.count++; 4095 } else { 4096 list_add_tail(&dsd->list, 4097 &ha->pool.good.head); 4098 ha->pool.good.count++; 4099 } 4100 } 4101 4102 /* return the good ones back to the pool */ 4103 list_for_each_entry_safe(dsd, nxt, 4104 &ha->pool.good.head, list) { 4105 list_del(&dsd->list); 4106 dma_pool_free(ha->dif_bundl_pool, 4107 dsd->dsd_addr, dsd->dsd_list_dma); 4108 ha->dif_bundle_dma_allocs--; 4109 kfree(dsd); 4110 ha->dif_bundle_kallocs--; 4111 } 4112 4113 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4114 "%s: dif dma pool (good=%u unusable=%u)\n", 4115 __func__, ha->pool.good.count, 4116 ha->pool.unusable.count); 4117 } 4118 4119 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4120 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4121 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4122 ha->dif_bundl_pool); 4123 } 4124 4125 /* Allocate memory for SNS commands */ 4126 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4127 /* Get consistent memory allocated for SNS commands */ 4128 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4129 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4130 if (!ha->sns_cmd) 4131 goto fail_dma_pool; 4132 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4133 "sns_cmd: %p.\n", ha->sns_cmd); 4134 } else { 4135 /* Get consistent memory allocated for MS IOCB */ 4136 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4137 &ha->ms_iocb_dma); 4138 if (!ha->ms_iocb) 4139 goto fail_dma_pool; 4140 /* Get consistent memory allocated for CT SNS commands */ 4141 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4142 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4143 if (!ha->ct_sns) 4144 goto fail_free_ms_iocb; 4145 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4146 "ms_iocb=%p ct_sns=%p.\n", 4147 ha->ms_iocb, ha->ct_sns); 4148 } 4149 4150 /* Allocate memory for request ring */ 4151 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4152 if (!*req) { 4153 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4154 "Failed to allocate memory for req.\n"); 4155 goto fail_req; 4156 } 4157 (*req)->length = req_len; 4158 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4159 ((*req)->length + 1) * sizeof(request_t), 4160 &(*req)->dma, GFP_KERNEL); 4161 if (!(*req)->ring) { 4162 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4163 "Failed to allocate memory for req_ring.\n"); 4164 goto fail_req_ring; 4165 } 4166 /* Allocate memory for response ring */ 4167 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4168 if (!*rsp) { 4169 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4170 "Failed to allocate memory for rsp.\n"); 4171 goto fail_rsp; 4172 } 4173 (*rsp)->hw = ha; 4174 (*rsp)->length = rsp_len; 4175 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4176 ((*rsp)->length + 1) * sizeof(response_t), 4177 &(*rsp)->dma, GFP_KERNEL); 4178 if (!(*rsp)->ring) { 4179 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4180 "Failed to allocate memory for rsp_ring.\n"); 4181 goto fail_rsp_ring; 4182 } 4183 (*req)->rsp = *rsp; 4184 (*rsp)->req = *req; 4185 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4186 "req=%p req->length=%d req->ring=%p rsp=%p " 4187 "rsp->length=%d rsp->ring=%p.\n", 4188 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4189 (*rsp)->ring); 4190 /* Allocate memory for NVRAM data for vports */ 4191 if (ha->nvram_npiv_size) { 4192 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4193 sizeof(struct qla_npiv_entry), 4194 GFP_KERNEL); 4195 if (!ha->npiv_info) { 4196 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4197 "Failed to allocate memory for npiv_info.\n"); 4198 goto fail_npiv_info; 4199 } 4200 } else 4201 ha->npiv_info = NULL; 4202 4203 /* Get consistent memory allocated for EX-INIT-CB. */ 4204 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4205 IS_QLA28XX(ha)) { 4206 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4207 &ha->ex_init_cb_dma); 4208 if (!ha->ex_init_cb) 4209 goto fail_ex_init_cb; 4210 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4211 "ex_init_cb=%p.\n", ha->ex_init_cb); 4212 } 4213 4214 /* Get consistent memory allocated for Special Features-CB. */ 4215 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4216 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4217 &ha->sf_init_cb_dma); 4218 if (!ha->sf_init_cb) 4219 goto fail_sf_init_cb; 4220 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4221 "sf_init_cb=%p.\n", ha->sf_init_cb); 4222 } 4223 4224 INIT_LIST_HEAD(&ha->gbl_dsd_list); 4225 4226 /* Get consistent memory allocated for Async Port-Database. */ 4227 if (!IS_FWI2_CAPABLE(ha)) { 4228 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4229 &ha->async_pd_dma); 4230 if (!ha->async_pd) 4231 goto fail_async_pd; 4232 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4233 "async_pd=%p.\n", ha->async_pd); 4234 } 4235 4236 INIT_LIST_HEAD(&ha->vp_list); 4237 4238 /* Allocate memory for our loop_id bitmap */ 4239 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4240 sizeof(long), 4241 GFP_KERNEL); 4242 if (!ha->loop_id_map) 4243 goto fail_loop_id_map; 4244 else { 4245 qla2x00_set_reserved_loop_ids(ha); 4246 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4247 "loop_id_map=%p.\n", ha->loop_id_map); 4248 } 4249 4250 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4251 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4252 if (!ha->sfp_data) { 4253 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4254 "Unable to allocate memory for SFP read-data.\n"); 4255 goto fail_sfp_data; 4256 } 4257 4258 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4259 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4260 GFP_KERNEL); 4261 if (!ha->flt) { 4262 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4263 "Unable to allocate memory for FLT.\n"); 4264 goto fail_flt_buffer; 4265 } 4266 4267 return 0; 4268 4269 fail_flt_buffer: 4270 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4271 ha->sfp_data, ha->sfp_data_dma); 4272 fail_sfp_data: 4273 kfree(ha->loop_id_map); 4274 fail_loop_id_map: 4275 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4276 fail_async_pd: 4277 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4278 fail_sf_init_cb: 4279 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4280 fail_ex_init_cb: 4281 kfree(ha->npiv_info); 4282 fail_npiv_info: 4283 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4284 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4285 (*rsp)->ring = NULL; 4286 (*rsp)->dma = 0; 4287 fail_rsp_ring: 4288 kfree(*rsp); 4289 *rsp = NULL; 4290 fail_rsp: 4291 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4292 sizeof(request_t), (*req)->ring, (*req)->dma); 4293 (*req)->ring = NULL; 4294 (*req)->dma = 0; 4295 fail_req_ring: 4296 kfree(*req); 4297 *req = NULL; 4298 fail_req: 4299 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4300 ha->ct_sns, ha->ct_sns_dma); 4301 ha->ct_sns = NULL; 4302 ha->ct_sns_dma = 0; 4303 fail_free_ms_iocb: 4304 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4305 ha->ms_iocb = NULL; 4306 ha->ms_iocb_dma = 0; 4307 4308 if (ha->sns_cmd) 4309 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4310 ha->sns_cmd, ha->sns_cmd_dma); 4311 fail_dma_pool: 4312 if (ql2xenabledif) { 4313 struct dsd_dma *dsd, *nxt; 4314 4315 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4316 list) { 4317 list_del(&dsd->list); 4318 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4319 dsd->dsd_list_dma); 4320 ha->dif_bundle_dma_allocs--; 4321 kfree(dsd); 4322 ha->dif_bundle_kallocs--; 4323 ha->pool.unusable.count--; 4324 } 4325 dma_pool_destroy(ha->dif_bundl_pool); 4326 ha->dif_bundl_pool = NULL; 4327 } 4328 4329 fail_dif_bundl_dma_pool: 4330 if (IS_QLA82XX(ha) || ql2xenabledif) { 4331 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4332 ha->fcp_cmnd_dma_pool = NULL; 4333 } 4334 fail_dl_dma_pool: 4335 if (IS_QLA82XX(ha) || ql2xenabledif) { 4336 dma_pool_destroy(ha->dl_dma_pool); 4337 ha->dl_dma_pool = NULL; 4338 } 4339 fail_s_dma_pool: 4340 dma_pool_destroy(ha->s_dma_pool); 4341 ha->s_dma_pool = NULL; 4342 fail_free_nvram: 4343 kfree(ha->nvram); 4344 ha->nvram = NULL; 4345 fail_free_ctx_mempool: 4346 mempool_destroy(ha->ctx_mempool); 4347 ha->ctx_mempool = NULL; 4348 fail_free_srb_mempool: 4349 mempool_destroy(ha->srb_mempool); 4350 ha->srb_mempool = NULL; 4351 fail_free_gid_list: 4352 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4353 ha->gid_list, 4354 ha->gid_list_dma); 4355 ha->gid_list = NULL; 4356 ha->gid_list_dma = 0; 4357 fail_free_tgt_mem: 4358 qlt_mem_free(ha); 4359 fail_free_init_cb: 4360 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4361 ha->init_cb_dma); 4362 ha->init_cb = NULL; 4363 ha->init_cb_dma = 0; 4364 fail: 4365 ql_log(ql_log_fatal, NULL, 0x0030, 4366 "Memory allocation failure.\n"); 4367 return -ENOMEM; 4368 } 4369 4370 int 4371 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4372 { 4373 int rval; 4374 uint16_t size, max_cnt; 4375 uint32_t temp; 4376 struct qla_hw_data *ha = vha->hw; 4377 4378 /* Return if we don't need to alloacate any extended logins */ 4379 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4380 return QLA_SUCCESS; 4381 4382 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4383 return QLA_SUCCESS; 4384 4385 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4386 max_cnt = 0; 4387 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4388 if (rval != QLA_SUCCESS) { 4389 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4390 "Failed to get exlogin status.\n"); 4391 return rval; 4392 } 4393 4394 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4395 temp *= size; 4396 4397 if (temp != ha->exlogin_size) { 4398 qla2x00_free_exlogin_buffer(ha); 4399 ha->exlogin_size = temp; 4400 4401 ql_log(ql_log_info, vha, 0xd024, 4402 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4403 max_cnt, size, temp); 4404 4405 ql_log(ql_log_info, vha, 0xd025, 4406 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4407 4408 /* Get consistent memory for extended logins */ 4409 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4410 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4411 if (!ha->exlogin_buf) { 4412 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4413 "Failed to allocate memory for exlogin_buf_dma.\n"); 4414 return -ENOMEM; 4415 } 4416 } 4417 4418 /* Now configure the dma buffer */ 4419 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4420 if (rval) { 4421 ql_log(ql_log_fatal, vha, 0xd033, 4422 "Setup extended login buffer ****FAILED****.\n"); 4423 qla2x00_free_exlogin_buffer(ha); 4424 } 4425 4426 return rval; 4427 } 4428 4429 /* 4430 * qla2x00_free_exlogin_buffer 4431 * 4432 * Input: 4433 * ha = adapter block pointer 4434 */ 4435 void 4436 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4437 { 4438 if (ha->exlogin_buf) { 4439 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4440 ha->exlogin_buf, ha->exlogin_buf_dma); 4441 ha->exlogin_buf = NULL; 4442 ha->exlogin_size = 0; 4443 } 4444 } 4445 4446 static void 4447 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4448 { 4449 u32 temp; 4450 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb; 4451 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4452 4453 if (max_cnt > vha->hw->max_exchg) 4454 max_cnt = vha->hw->max_exchg; 4455 4456 if (qla_ini_mode_enabled(vha)) { 4457 if (vha->ql2xiniexchg > max_cnt) 4458 vha->ql2xiniexchg = max_cnt; 4459 4460 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4461 *ret_cnt = vha->ql2xiniexchg; 4462 4463 } else if (qla_tgt_mode_enabled(vha)) { 4464 if (vha->ql2xexchoffld > max_cnt) { 4465 vha->ql2xexchoffld = max_cnt; 4466 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4467 } 4468 4469 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4470 *ret_cnt = vha->ql2xexchoffld; 4471 } else if (qla_dual_mode_enabled(vha)) { 4472 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4473 if (temp > max_cnt) { 4474 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4475 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4476 temp = max_cnt; 4477 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4478 } 4479 4480 if (temp > FW_DEF_EXCHANGES_CNT) 4481 *ret_cnt = temp; 4482 } 4483 } 4484 4485 int 4486 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4487 { 4488 int rval; 4489 u16 size, max_cnt; 4490 u32 actual_cnt, totsz; 4491 struct qla_hw_data *ha = vha->hw; 4492 4493 if (!ha->flags.exchoffld_enabled) 4494 return QLA_SUCCESS; 4495 4496 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4497 return QLA_SUCCESS; 4498 4499 max_cnt = 0; 4500 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4501 if (rval != QLA_SUCCESS) { 4502 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4503 "Failed to get exlogin status.\n"); 4504 return rval; 4505 } 4506 4507 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4508 ql_log(ql_log_info, vha, 0xd014, 4509 "Actual exchange offload count: %d.\n", actual_cnt); 4510 4511 totsz = actual_cnt * size; 4512 4513 if (totsz != ha->exchoffld_size) { 4514 qla2x00_free_exchoffld_buffer(ha); 4515 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4516 ha->exchoffld_size = 0; 4517 ha->flags.exchoffld_enabled = 0; 4518 return QLA_SUCCESS; 4519 } 4520 4521 ha->exchoffld_size = totsz; 4522 4523 ql_log(ql_log_info, vha, 0xd016, 4524 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4525 max_cnt, actual_cnt, size, totsz); 4526 4527 ql_log(ql_log_info, vha, 0xd017, 4528 "Exchange Buffers requested size = 0x%x\n", 4529 ha->exchoffld_size); 4530 4531 /* Get consistent memory for extended logins */ 4532 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4533 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4534 if (!ha->exchoffld_buf) { 4535 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4536 "Failed to allocate memory for Exchange Offload.\n"); 4537 4538 if (ha->max_exchg > 4539 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4540 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4541 } else if (ha->max_exchg > 4542 (FW_DEF_EXCHANGES_CNT + 512)) { 4543 ha->max_exchg -= 512; 4544 } else { 4545 ha->flags.exchoffld_enabled = 0; 4546 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4547 "Disabling Exchange offload due to lack of memory\n"); 4548 } 4549 ha->exchoffld_size = 0; 4550 4551 return -ENOMEM; 4552 } 4553 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4554 /* pathological case */ 4555 qla2x00_free_exchoffld_buffer(ha); 4556 ha->exchoffld_size = 0; 4557 ha->flags.exchoffld_enabled = 0; 4558 ql_log(ql_log_info, vha, 0xd016, 4559 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4560 ha->exchoffld_size, actual_cnt, size, totsz); 4561 return 0; 4562 } 4563 4564 /* Now configure the dma buffer */ 4565 rval = qla_set_exchoffld_mem_cfg(vha); 4566 if (rval) { 4567 ql_log(ql_log_fatal, vha, 0xd02e, 4568 "Setup exchange offload buffer ****FAILED****.\n"); 4569 qla2x00_free_exchoffld_buffer(ha); 4570 } else { 4571 /* re-adjust number of target exchange */ 4572 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4573 4574 if (qla_ini_mode_enabled(vha)) 4575 icb->exchange_count = 0; 4576 else 4577 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4578 } 4579 4580 return rval; 4581 } 4582 4583 /* 4584 * qla2x00_free_exchoffld_buffer 4585 * 4586 * Input: 4587 * ha = adapter block pointer 4588 */ 4589 void 4590 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4591 { 4592 if (ha->exchoffld_buf) { 4593 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4594 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4595 ha->exchoffld_buf = NULL; 4596 ha->exchoffld_size = 0; 4597 } 4598 } 4599 4600 /* 4601 * qla2x00_free_fw_dump 4602 * Frees fw dump stuff. 4603 * 4604 * Input: 4605 * ha = adapter block pointer 4606 */ 4607 static void 4608 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4609 { 4610 struct fwdt *fwdt = ha->fwdt; 4611 uint j; 4612 4613 if (ha->fce) 4614 dma_free_coherent(&ha->pdev->dev, 4615 FCE_SIZE, ha->fce, ha->fce_dma); 4616 4617 if (ha->eft) 4618 dma_free_coherent(&ha->pdev->dev, 4619 EFT_SIZE, ha->eft, ha->eft_dma); 4620 4621 vfree(ha->fw_dump); 4622 4623 ha->fce = NULL; 4624 ha->fce_dma = 0; 4625 ha->flags.fce_enabled = 0; 4626 ha->eft = NULL; 4627 ha->eft_dma = 0; 4628 ha->fw_dumped = false; 4629 ha->fw_dump_cap_flags = 0; 4630 ha->fw_dump_reading = 0; 4631 ha->fw_dump = NULL; 4632 ha->fw_dump_len = 0; 4633 4634 for (j = 0; j < 2; j++, fwdt++) { 4635 vfree(fwdt->template); 4636 fwdt->template = NULL; 4637 fwdt->length = 0; 4638 } 4639 } 4640 4641 /* 4642 * qla2x00_mem_free 4643 * Frees all adapter allocated memory. 4644 * 4645 * Input: 4646 * ha = adapter block pointer. 4647 */ 4648 static void 4649 qla2x00_mem_free(struct qla_hw_data *ha) 4650 { 4651 qla2x00_free_fw_dump(ha); 4652 4653 if (ha->mctp_dump) 4654 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4655 ha->mctp_dump_dma); 4656 ha->mctp_dump = NULL; 4657 4658 mempool_destroy(ha->srb_mempool); 4659 ha->srb_mempool = NULL; 4660 4661 if (ha->dcbx_tlv) 4662 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4663 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4664 ha->dcbx_tlv = NULL; 4665 4666 if (ha->xgmac_data) 4667 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4668 ha->xgmac_data, ha->xgmac_data_dma); 4669 ha->xgmac_data = NULL; 4670 4671 if (ha->sns_cmd) 4672 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4673 ha->sns_cmd, ha->sns_cmd_dma); 4674 ha->sns_cmd = NULL; 4675 ha->sns_cmd_dma = 0; 4676 4677 if (ha->ct_sns) 4678 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4679 ha->ct_sns, ha->ct_sns_dma); 4680 ha->ct_sns = NULL; 4681 ha->ct_sns_dma = 0; 4682 4683 if (ha->sfp_data) 4684 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4685 ha->sfp_data_dma); 4686 ha->sfp_data = NULL; 4687 4688 if (ha->flt) 4689 dma_free_coherent(&ha->pdev->dev, 4690 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4691 ha->flt, ha->flt_dma); 4692 ha->flt = NULL; 4693 ha->flt_dma = 0; 4694 4695 if (ha->ms_iocb) 4696 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4697 ha->ms_iocb = NULL; 4698 ha->ms_iocb_dma = 0; 4699 4700 if (ha->sf_init_cb) 4701 dma_pool_free(ha->s_dma_pool, 4702 ha->sf_init_cb, ha->sf_init_cb_dma); 4703 4704 if (ha->ex_init_cb) 4705 dma_pool_free(ha->s_dma_pool, 4706 ha->ex_init_cb, ha->ex_init_cb_dma); 4707 ha->ex_init_cb = NULL; 4708 ha->ex_init_cb_dma = 0; 4709 4710 if (ha->async_pd) 4711 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4712 ha->async_pd = NULL; 4713 ha->async_pd_dma = 0; 4714 4715 dma_pool_destroy(ha->s_dma_pool); 4716 ha->s_dma_pool = NULL; 4717 4718 if (ha->gid_list) 4719 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4720 ha->gid_list, ha->gid_list_dma); 4721 ha->gid_list = NULL; 4722 ha->gid_list_dma = 0; 4723 4724 if (IS_QLA82XX(ha)) { 4725 if (!list_empty(&ha->gbl_dsd_list)) { 4726 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4727 4728 /* clean up allocated prev pool */ 4729 list_for_each_entry_safe(dsd_ptr, 4730 tdsd_ptr, &ha->gbl_dsd_list, list) { 4731 dma_pool_free(ha->dl_dma_pool, 4732 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); 4733 list_del(&dsd_ptr->list); 4734 kfree(dsd_ptr); 4735 } 4736 } 4737 } 4738 4739 dma_pool_destroy(ha->dl_dma_pool); 4740 ha->dl_dma_pool = NULL; 4741 4742 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4743 ha->fcp_cmnd_dma_pool = NULL; 4744 4745 mempool_destroy(ha->ctx_mempool); 4746 ha->ctx_mempool = NULL; 4747 4748 if (ql2xenabledif && ha->dif_bundl_pool) { 4749 struct dsd_dma *dsd, *nxt; 4750 4751 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4752 list) { 4753 list_del(&dsd->list); 4754 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4755 dsd->dsd_list_dma); 4756 ha->dif_bundle_dma_allocs--; 4757 kfree(dsd); 4758 ha->dif_bundle_kallocs--; 4759 ha->pool.unusable.count--; 4760 } 4761 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4762 list_del(&dsd->list); 4763 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4764 dsd->dsd_list_dma); 4765 ha->dif_bundle_dma_allocs--; 4766 kfree(dsd); 4767 ha->dif_bundle_kallocs--; 4768 } 4769 } 4770 4771 dma_pool_destroy(ha->dif_bundl_pool); 4772 ha->dif_bundl_pool = NULL; 4773 4774 qlt_mem_free(ha); 4775 4776 if (ha->init_cb) 4777 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 4778 ha->init_cb, ha->init_cb_dma); 4779 ha->init_cb = NULL; 4780 ha->init_cb_dma = 0; 4781 4782 vfree(ha->optrom_buffer); 4783 ha->optrom_buffer = NULL; 4784 kfree(ha->nvram); 4785 ha->nvram = NULL; 4786 kfree(ha->npiv_info); 4787 ha->npiv_info = NULL; 4788 kfree(ha->swl); 4789 ha->swl = NULL; 4790 kfree(ha->loop_id_map); 4791 ha->sf_init_cb = NULL; 4792 ha->sf_init_cb_dma = 0; 4793 ha->loop_id_map = NULL; 4794 } 4795 4796 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, 4797 struct qla_hw_data *ha) 4798 { 4799 struct Scsi_Host *host; 4800 struct scsi_qla_host *vha = NULL; 4801 4802 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 4803 if (!host) { 4804 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 4805 "Failed to allocate host from the scsi layer, aborting.\n"); 4806 return NULL; 4807 } 4808 4809 /* Clear our data area */ 4810 vha = shost_priv(host); 4811 memset(vha, 0, sizeof(scsi_qla_host_t)); 4812 4813 vha->host = host; 4814 vha->host_no = host->host_no; 4815 vha->hw = ha; 4816 4817 vha->qlini_mode = ql2x_ini_mode; 4818 vha->ql2xexchoffld = ql2xexchoffld; 4819 vha->ql2xiniexchg = ql2xiniexchg; 4820 4821 INIT_LIST_HEAD(&vha->vp_fcports); 4822 INIT_LIST_HEAD(&vha->work_list); 4823 INIT_LIST_HEAD(&vha->list); 4824 INIT_LIST_HEAD(&vha->qla_cmd_list); 4825 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); 4826 INIT_LIST_HEAD(&vha->logo_list); 4827 INIT_LIST_HEAD(&vha->plogi_ack_list); 4828 INIT_LIST_HEAD(&vha->qp_list); 4829 INIT_LIST_HEAD(&vha->gnl.fcports); 4830 INIT_LIST_HEAD(&vha->gpnid_list); 4831 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 4832 4833 INIT_LIST_HEAD(&vha->purex_list.head); 4834 spin_lock_init(&vha->purex_list.lock); 4835 4836 spin_lock_init(&vha->work_lock); 4837 spin_lock_init(&vha->cmd_list_lock); 4838 init_waitqueue_head(&vha->fcport_waitQ); 4839 init_waitqueue_head(&vha->vref_waitq); 4840 4841 vha->gnl.size = sizeof(struct get_name_list_extended) * 4842 (ha->max_loop_id + 1); 4843 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 4844 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 4845 if (!vha->gnl.l) { 4846 ql_log(ql_log_fatal, vha, 0xd04a, 4847 "Alloc failed for name list.\n"); 4848 scsi_host_put(vha->host); 4849 return NULL; 4850 } 4851 4852 /* todo: what about ext login? */ 4853 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 4854 vha->scan.l = vmalloc(vha->scan.size); 4855 if (!vha->scan.l) { 4856 ql_log(ql_log_fatal, vha, 0xd04a, 4857 "Alloc failed for scan database.\n"); 4858 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 4859 vha->gnl.l, vha->gnl.ldma); 4860 vha->gnl.l = NULL; 4861 scsi_host_put(vha->host); 4862 return NULL; 4863 } 4864 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 4865 4866 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); 4867 ql_dbg(ql_dbg_init, vha, 0x0041, 4868 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 4869 vha->host, vha->hw, vha, 4870 dev_name(&(ha->pdev->dev))); 4871 4872 return vha; 4873 } 4874 4875 struct qla_work_evt * 4876 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 4877 { 4878 struct qla_work_evt *e; 4879 uint8_t bail; 4880 4881 if (test_bit(UNLOADING, &vha->dpc_flags)) 4882 return NULL; 4883 4884 QLA_VHA_MARK_BUSY(vha, bail); 4885 if (bail) 4886 return NULL; 4887 4888 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 4889 if (!e) { 4890 QLA_VHA_MARK_NOT_BUSY(vha); 4891 return NULL; 4892 } 4893 4894 INIT_LIST_HEAD(&e->list); 4895 e->type = type; 4896 e->flags = QLA_EVT_FLAG_FREE; 4897 return e; 4898 } 4899 4900 int 4901 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 4902 { 4903 unsigned long flags; 4904 bool q = false; 4905 4906 spin_lock_irqsave(&vha->work_lock, flags); 4907 list_add_tail(&e->list, &vha->work_list); 4908 4909 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 4910 q = true; 4911 4912 spin_unlock_irqrestore(&vha->work_lock, flags); 4913 4914 if (q) 4915 queue_work(vha->hw->wq, &vha->iocb_work); 4916 4917 return QLA_SUCCESS; 4918 } 4919 4920 int 4921 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 4922 u32 data) 4923 { 4924 struct qla_work_evt *e; 4925 4926 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 4927 if (!e) 4928 return QLA_FUNCTION_FAILED; 4929 4930 e->u.aen.code = code; 4931 e->u.aen.data = data; 4932 return qla2x00_post_work(vha, e); 4933 } 4934 4935 int 4936 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 4937 { 4938 struct qla_work_evt *e; 4939 4940 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 4941 if (!e) 4942 return QLA_FUNCTION_FAILED; 4943 4944 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 4945 return qla2x00_post_work(vha, e); 4946 } 4947 4948 #define qla2x00_post_async_work(name, type) \ 4949 int qla2x00_post_async_##name##_work( \ 4950 struct scsi_qla_host *vha, \ 4951 fc_port_t *fcport, uint16_t *data) \ 4952 { \ 4953 struct qla_work_evt *e; \ 4954 \ 4955 e = qla2x00_alloc_work(vha, type); \ 4956 if (!e) \ 4957 return QLA_FUNCTION_FAILED; \ 4958 \ 4959 e->u.logio.fcport = fcport; \ 4960 if (data) { \ 4961 e->u.logio.data[0] = data[0]; \ 4962 e->u.logio.data[1] = data[1]; \ 4963 } \ 4964 fcport->flags |= FCF_ASYNC_ACTIVE; \ 4965 return qla2x00_post_work(vha, e); \ 4966 } 4967 4968 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 4969 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 4970 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 4971 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 4972 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 4973 4974 int 4975 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 4976 { 4977 struct qla_work_evt *e; 4978 4979 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 4980 if (!e) 4981 return QLA_FUNCTION_FAILED; 4982 4983 e->u.uevent.code = code; 4984 return qla2x00_post_work(vha, e); 4985 } 4986 4987 static void 4988 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 4989 { 4990 char event_string[40]; 4991 char *envp[] = { event_string, NULL }; 4992 4993 switch (code) { 4994 case QLA_UEVENT_CODE_FW_DUMP: 4995 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 4996 vha->host_no); 4997 break; 4998 default: 4999 /* do nothing */ 5000 break; 5001 } 5002 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5003 } 5004 5005 int 5006 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5007 uint32_t *data, int cnt) 5008 { 5009 struct qla_work_evt *e; 5010 5011 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5012 if (!e) 5013 return QLA_FUNCTION_FAILED; 5014 5015 e->u.aenfx.evtcode = evtcode; 5016 e->u.aenfx.count = cnt; 5017 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5018 return qla2x00_post_work(vha, e); 5019 } 5020 5021 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5022 { 5023 unsigned long flags; 5024 5025 if (IS_SW_RESV_ADDR(fcport->d_id)) 5026 return; 5027 5028 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5029 if (fcport->disc_state == DSC_UPD_FCPORT) { 5030 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5031 return; 5032 } 5033 fcport->jiffies_at_registration = jiffies; 5034 fcport->sec_since_registration = 0; 5035 fcport->next_disc_state = DSC_DELETED; 5036 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5037 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5038 5039 queue_work(system_unbound_wq, &fcport->reg_work); 5040 } 5041 5042 static 5043 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5044 { 5045 unsigned long flags; 5046 fc_port_t *fcport = NULL, *tfcp; 5047 struct qlt_plogi_ack_t *pla = 5048 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5049 uint8_t free_fcport = 0; 5050 5051 ql_dbg(ql_dbg_disc, vha, 0xffff, 5052 "%s %d %8phC enter\n", 5053 __func__, __LINE__, e->u.new_sess.port_name); 5054 5055 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5056 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5057 if (fcport) { 5058 fcport->d_id = e->u.new_sess.id; 5059 if (pla) { 5060 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5061 memcpy(fcport->node_name, 5062 pla->iocb.u.isp24.u.plogi.node_name, 5063 WWN_SIZE); 5064 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5065 /* we took an extra ref_count to prevent PLOGI ACK when 5066 * fcport/sess has not been created. 5067 */ 5068 pla->ref_count--; 5069 } 5070 } else { 5071 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5072 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5073 if (fcport) { 5074 fcport->d_id = e->u.new_sess.id; 5075 fcport->flags |= FCF_FABRIC_DEVICE; 5076 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5077 fcport->tgt_short_link_down_cnt = 0; 5078 5079 memcpy(fcport->port_name, e->u.new_sess.port_name, 5080 WWN_SIZE); 5081 5082 fcport->fc4_type = e->u.new_sess.fc4_type; 5083 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5084 fcport->dm_login_expire = jiffies + 5085 QLA_N2N_WAIT_TIME * HZ; 5086 fcport->fc4_type = FS_FC4TYPE_FCP; 5087 fcport->n2n_flag = 1; 5088 if (vha->flags.nvme_enabled) 5089 fcport->fc4_type |= FS_FC4TYPE_NVME; 5090 } 5091 5092 } else { 5093 ql_dbg(ql_dbg_disc, vha, 0xffff, 5094 "%s %8phC mem alloc fail.\n", 5095 __func__, e->u.new_sess.port_name); 5096 5097 if (pla) { 5098 list_del(&pla->list); 5099 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5100 } 5101 return; 5102 } 5103 5104 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5105 /* search again to make sure no one else got ahead */ 5106 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5107 e->u.new_sess.port_name, 1); 5108 if (tfcp) { 5109 /* should rarily happen */ 5110 ql_dbg(ql_dbg_disc, vha, 0xffff, 5111 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5112 __func__, tfcp->port_name, tfcp->disc_state, 5113 tfcp->fw_login_state); 5114 5115 free_fcport = 1; 5116 } else { 5117 list_add_tail(&fcport->list, &vha->vp_fcports); 5118 5119 } 5120 if (pla) { 5121 qlt_plogi_ack_link(vha, pla, fcport, 5122 QLT_PLOGI_LINK_SAME_WWN); 5123 pla->ref_count--; 5124 } 5125 } 5126 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5127 5128 if (fcport) { 5129 fcport->id_changed = 1; 5130 fcport->scan_state = QLA_FCPORT_FOUND; 5131 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5132 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5133 5134 if (pla) { 5135 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5136 u16 wd3_lo; 5137 5138 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5139 fcport->local = 0; 5140 fcport->loop_id = 5141 le16_to_cpu( 5142 pla->iocb.u.isp24.nport_handle); 5143 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5144 wd3_lo = 5145 le16_to_cpu( 5146 pla->iocb.u.isp24.u.prli.wd3_lo); 5147 5148 if (wd3_lo & BIT_7) 5149 fcport->conf_compl_supported = 1; 5150 5151 if ((wd3_lo & BIT_4) == 0) 5152 fcport->port_type = FCT_INITIATOR; 5153 else 5154 fcport->port_type = FCT_TARGET; 5155 } 5156 qlt_plogi_ack_unref(vha, pla); 5157 } else { 5158 fc_port_t *dfcp = NULL; 5159 5160 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5161 tfcp = qla2x00_find_fcport_by_nportid(vha, 5162 &e->u.new_sess.id, 1); 5163 if (tfcp && (tfcp != fcport)) { 5164 /* 5165 * We have a conflict fcport with same NportID. 5166 */ 5167 ql_dbg(ql_dbg_disc, vha, 0xffff, 5168 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5169 __func__, tfcp->port_name, tfcp->disc_state, 5170 tfcp->fw_login_state); 5171 5172 switch (tfcp->disc_state) { 5173 case DSC_DELETED: 5174 break; 5175 case DSC_DELETE_PEND: 5176 fcport->login_pause = 1; 5177 tfcp->conflict = fcport; 5178 break; 5179 default: 5180 fcport->login_pause = 1; 5181 tfcp->conflict = fcport; 5182 dfcp = tfcp; 5183 break; 5184 } 5185 } 5186 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5187 if (dfcp) 5188 qlt_schedule_sess_for_deletion(tfcp); 5189 5190 if (N2N_TOPO(vha->hw)) { 5191 fcport->flags &= ~FCF_FABRIC_DEVICE; 5192 fcport->keep_nport_handle = 1; 5193 if (vha->flags.nvme_enabled) { 5194 fcport->fc4_type = 5195 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5196 fcport->n2n_flag = 1; 5197 } 5198 fcport->fw_login_state = 0; 5199 5200 schedule_delayed_work(&vha->scan.scan_work, 5); 5201 } else { 5202 qla24xx_fcport_handle_login(vha, fcport); 5203 } 5204 } 5205 } 5206 5207 if (free_fcport) { 5208 qla2x00_free_fcport(fcport); 5209 if (pla) { 5210 list_del(&pla->list); 5211 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5212 } 5213 } 5214 } 5215 5216 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5217 { 5218 struct srb *sp = e->u.iosb.sp; 5219 int rval; 5220 5221 rval = qla2x00_start_sp(sp); 5222 if (rval != QLA_SUCCESS) { 5223 ql_dbg(ql_dbg_disc, vha, 0x2043, 5224 "%s: %s: Re-issue IOCB failed (%d).\n", 5225 __func__, sp->name, rval); 5226 qla24xx_sp_unmap(vha, sp); 5227 } 5228 } 5229 5230 void 5231 qla2x00_do_work(struct scsi_qla_host *vha) 5232 { 5233 struct qla_work_evt *e, *tmp; 5234 unsigned long flags; 5235 LIST_HEAD(work); 5236 int rc; 5237 5238 spin_lock_irqsave(&vha->work_lock, flags); 5239 list_splice_init(&vha->work_list, &work); 5240 spin_unlock_irqrestore(&vha->work_lock, flags); 5241 5242 list_for_each_entry_safe(e, tmp, &work, list) { 5243 rc = QLA_SUCCESS; 5244 switch (e->type) { 5245 case QLA_EVT_AEN: 5246 fc_host_post_event(vha->host, fc_get_event_number(), 5247 e->u.aen.code, e->u.aen.data); 5248 break; 5249 case QLA_EVT_IDC_ACK: 5250 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5251 break; 5252 case QLA_EVT_ASYNC_LOGIN: 5253 qla2x00_async_login(vha, e->u.logio.fcport, 5254 e->u.logio.data); 5255 break; 5256 case QLA_EVT_ASYNC_LOGOUT: 5257 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5258 break; 5259 case QLA_EVT_ASYNC_ADISC: 5260 qla2x00_async_adisc(vha, e->u.logio.fcport, 5261 e->u.logio.data); 5262 break; 5263 case QLA_EVT_UEVENT: 5264 qla2x00_uevent_emit(vha, e->u.uevent.code); 5265 break; 5266 case QLA_EVT_AENFX: 5267 qlafx00_process_aen(vha, e); 5268 break; 5269 case QLA_EVT_GPNID: 5270 qla24xx_async_gpnid(vha, &e->u.gpnid.id); 5271 break; 5272 case QLA_EVT_UNMAP: 5273 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5274 break; 5275 case QLA_EVT_RELOGIN: 5276 qla2x00_relogin(vha); 5277 break; 5278 case QLA_EVT_NEW_SESS: 5279 qla24xx_create_new_sess(vha, e); 5280 break; 5281 case QLA_EVT_GPDB: 5282 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5283 e->u.fcport.opt); 5284 break; 5285 case QLA_EVT_PRLI: 5286 qla24xx_async_prli(vha, e->u.fcport.fcport); 5287 break; 5288 case QLA_EVT_GPSC: 5289 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5290 break; 5291 case QLA_EVT_GNL: 5292 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5293 break; 5294 case QLA_EVT_NACK: 5295 qla24xx_do_nack_work(vha, e); 5296 break; 5297 case QLA_EVT_ASYNC_PRLO: 5298 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5299 break; 5300 case QLA_EVT_ASYNC_PRLO_DONE: 5301 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5302 e->u.logio.data); 5303 break; 5304 case QLA_EVT_GPNFT: 5305 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type, 5306 e->u.gpnft.sp); 5307 break; 5308 case QLA_EVT_GPNFT_DONE: 5309 qla24xx_async_gpnft_done(vha, e->u.iosb.sp); 5310 break; 5311 case QLA_EVT_GNNFT_DONE: 5312 qla24xx_async_gnnft_done(vha, e->u.iosb.sp); 5313 break; 5314 case QLA_EVT_GNNID: 5315 qla24xx_async_gnnid(vha, e->u.fcport.fcport); 5316 break; 5317 case QLA_EVT_GFPNID: 5318 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5319 break; 5320 case QLA_EVT_SP_RETRY: 5321 qla_sp_retry(vha, e); 5322 break; 5323 case QLA_EVT_IIDMA: 5324 qla_do_iidma_work(vha, e->u.fcport.fcport); 5325 break; 5326 case QLA_EVT_ELS_PLOGI: 5327 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5328 e->u.fcport.fcport, false); 5329 break; 5330 } 5331 5332 if (rc == EAGAIN) { 5333 /* put 'work' at head of 'vha->work_list' */ 5334 spin_lock_irqsave(&vha->work_lock, flags); 5335 list_splice(&work, &vha->work_list); 5336 spin_unlock_irqrestore(&vha->work_lock, flags); 5337 break; 5338 } 5339 list_del_init(&e->list); 5340 if (e->flags & QLA_EVT_FLAG_FREE) 5341 kfree(e); 5342 5343 /* For each work completed decrement vha ref count */ 5344 QLA_VHA_MARK_NOT_BUSY(vha); 5345 } 5346 } 5347 5348 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5349 { 5350 struct qla_work_evt *e; 5351 5352 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5353 5354 if (!e) { 5355 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5356 return QLA_FUNCTION_FAILED; 5357 } 5358 5359 return qla2x00_post_work(vha, e); 5360 } 5361 5362 /* Relogins all the fcports of a vport 5363 * Context: dpc thread 5364 */ 5365 void qla2x00_relogin(struct scsi_qla_host *vha) 5366 { 5367 fc_port_t *fcport; 5368 int status, relogin_needed = 0; 5369 struct event_arg ea; 5370 5371 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5372 /* 5373 * If the port is not ONLINE then try to login 5374 * to it if we haven't run out of retries. 5375 */ 5376 if (atomic_read(&fcport->state) != FCS_ONLINE && 5377 fcport->login_retry) { 5378 if (fcport->scan_state != QLA_FCPORT_FOUND || 5379 fcport->disc_state == DSC_LOGIN_COMPLETE) 5380 continue; 5381 5382 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5383 fcport->disc_state == DSC_DELETE_PEND) { 5384 relogin_needed = 1; 5385 } else { 5386 if (vha->hw->current_topology != ISP_CFG_NL) { 5387 memset(&ea, 0, sizeof(ea)); 5388 ea.fcport = fcport; 5389 qla24xx_handle_relogin_event(vha, &ea); 5390 } else if (vha->hw->current_topology == 5391 ISP_CFG_NL) { 5392 fcport->login_retry--; 5393 status = 5394 qla2x00_local_device_login(vha, 5395 fcport); 5396 if (status == QLA_SUCCESS) { 5397 fcport->old_loop_id = 5398 fcport->loop_id; 5399 ql_dbg(ql_dbg_disc, vha, 0x2003, 5400 "Port login OK: logged in ID 0x%x.\n", 5401 fcport->loop_id); 5402 qla2x00_update_fcport 5403 (vha, fcport); 5404 } else if (status == 1) { 5405 set_bit(RELOGIN_NEEDED, 5406 &vha->dpc_flags); 5407 /* retry the login again */ 5408 ql_dbg(ql_dbg_disc, vha, 0x2007, 5409 "Retrying %d login again loop_id 0x%x.\n", 5410 fcport->login_retry, 5411 fcport->loop_id); 5412 } else { 5413 fcport->login_retry = 0; 5414 } 5415 5416 if (fcport->login_retry == 0 && 5417 status != QLA_SUCCESS) 5418 qla2x00_clear_loop_id(fcport); 5419 } 5420 } 5421 } 5422 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5423 break; 5424 } 5425 5426 if (relogin_needed) 5427 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5428 5429 ql_dbg(ql_dbg_disc, vha, 0x400e, 5430 "Relogin end.\n"); 5431 } 5432 5433 /* Schedule work on any of the dpc-workqueues */ 5434 void 5435 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5436 { 5437 struct qla_hw_data *ha = base_vha->hw; 5438 5439 switch (work_code) { 5440 case MBA_IDC_AEN: /* 0x8200 */ 5441 if (ha->dpc_lp_wq) 5442 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5443 break; 5444 5445 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5446 if (!ha->flags.nic_core_reset_hdlr_active) { 5447 if (ha->dpc_hp_wq) 5448 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5449 } else 5450 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5451 "NIC Core reset is already active. Skip " 5452 "scheduling it again.\n"); 5453 break; 5454 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5455 if (ha->dpc_hp_wq) 5456 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5457 break; 5458 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5459 if (ha->dpc_hp_wq) 5460 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5461 break; 5462 default: 5463 ql_log(ql_log_warn, base_vha, 0xb05f, 5464 "Unknown work-code=0x%x.\n", work_code); 5465 } 5466 5467 return; 5468 } 5469 5470 /* Work: Perform NIC Core Unrecoverable state handling */ 5471 void 5472 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5473 { 5474 struct qla_hw_data *ha = 5475 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5476 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5477 uint32_t dev_state = 0; 5478 5479 qla83xx_idc_lock(base_vha, 0); 5480 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5481 qla83xx_reset_ownership(base_vha); 5482 if (ha->flags.nic_core_reset_owner) { 5483 ha->flags.nic_core_reset_owner = 0; 5484 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5485 QLA8XXX_DEV_FAILED); 5486 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5487 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5488 } 5489 qla83xx_idc_unlock(base_vha, 0); 5490 } 5491 5492 /* Work: Execute IDC state handler */ 5493 void 5494 qla83xx_idc_state_handler_work(struct work_struct *work) 5495 { 5496 struct qla_hw_data *ha = 5497 container_of(work, struct qla_hw_data, idc_state_handler); 5498 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5499 uint32_t dev_state = 0; 5500 5501 qla83xx_idc_lock(base_vha, 0); 5502 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5503 if (dev_state == QLA8XXX_DEV_FAILED || 5504 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5505 qla83xx_idc_state_handler(base_vha); 5506 qla83xx_idc_unlock(base_vha, 0); 5507 } 5508 5509 static int 5510 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5511 { 5512 int rval = QLA_SUCCESS; 5513 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5514 uint32_t heart_beat_counter1, heart_beat_counter2; 5515 5516 do { 5517 if (time_after(jiffies, heart_beat_wait)) { 5518 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5519 "Nic Core f/w is not alive.\n"); 5520 rval = QLA_FUNCTION_FAILED; 5521 break; 5522 } 5523 5524 qla83xx_idc_lock(base_vha, 0); 5525 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5526 &heart_beat_counter1); 5527 qla83xx_idc_unlock(base_vha, 0); 5528 msleep(100); 5529 qla83xx_idc_lock(base_vha, 0); 5530 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5531 &heart_beat_counter2); 5532 qla83xx_idc_unlock(base_vha, 0); 5533 } while (heart_beat_counter1 == heart_beat_counter2); 5534 5535 return rval; 5536 } 5537 5538 /* Work: Perform NIC Core Reset handling */ 5539 void 5540 qla83xx_nic_core_reset_work(struct work_struct *work) 5541 { 5542 struct qla_hw_data *ha = 5543 container_of(work, struct qla_hw_data, nic_core_reset); 5544 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5545 uint32_t dev_state = 0; 5546 5547 if (IS_QLA2031(ha)) { 5548 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5549 ql_log(ql_log_warn, base_vha, 0xb081, 5550 "Failed to dump mctp\n"); 5551 return; 5552 } 5553 5554 if (!ha->flags.nic_core_reset_hdlr_active) { 5555 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5556 qla83xx_idc_lock(base_vha, 0); 5557 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5558 &dev_state); 5559 qla83xx_idc_unlock(base_vha, 0); 5560 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5561 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5562 "Nic Core f/w is alive.\n"); 5563 return; 5564 } 5565 } 5566 5567 ha->flags.nic_core_reset_hdlr_active = 1; 5568 if (qla83xx_nic_core_reset(base_vha)) { 5569 /* NIC Core reset failed. */ 5570 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5571 "NIC Core reset failed.\n"); 5572 } 5573 ha->flags.nic_core_reset_hdlr_active = 0; 5574 } 5575 } 5576 5577 /* Work: Handle 8200 IDC aens */ 5578 void 5579 qla83xx_service_idc_aen(struct work_struct *work) 5580 { 5581 struct qla_hw_data *ha = 5582 container_of(work, struct qla_hw_data, idc_aen); 5583 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5584 uint32_t dev_state, idc_control; 5585 5586 qla83xx_idc_lock(base_vha, 0); 5587 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5588 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5589 qla83xx_idc_unlock(base_vha, 0); 5590 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5591 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5592 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5593 "Application requested NIC Core Reset.\n"); 5594 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5595 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5596 QLA_SUCCESS) { 5597 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5598 "Other protocol driver requested NIC Core Reset.\n"); 5599 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5600 } 5601 } else if (dev_state == QLA8XXX_DEV_FAILED || 5602 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5603 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5604 } 5605 } 5606 5607 /* 5608 * Control the frequency of IDC lock retries 5609 */ 5610 #define QLA83XX_WAIT_LOGIC_MS 100 5611 5612 static int 5613 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5614 { 5615 int rval; 5616 uint32_t data; 5617 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5618 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5619 struct qla_hw_data *ha = base_vha->hw; 5620 5621 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5622 "Trying force recovery of the IDC lock.\n"); 5623 5624 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5625 if (rval) 5626 return rval; 5627 5628 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5629 return QLA_SUCCESS; 5630 } else { 5631 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5632 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5633 data); 5634 if (rval) 5635 return rval; 5636 5637 msleep(200); 5638 5639 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5640 &data); 5641 if (rval) 5642 return rval; 5643 5644 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5645 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5646 ~(idc_lck_rcvry_stage_mask)); 5647 rval = qla83xx_wr_reg(base_vha, 5648 QLA83XX_IDC_LOCK_RECOVERY, data); 5649 if (rval) 5650 return rval; 5651 5652 /* Forcefully perform IDC UnLock */ 5653 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5654 &data); 5655 if (rval) 5656 return rval; 5657 /* Clear lock-id by setting 0xff */ 5658 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5659 0xff); 5660 if (rval) 5661 return rval; 5662 /* Clear lock-recovery by setting 0x0 */ 5663 rval = qla83xx_wr_reg(base_vha, 5664 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5665 if (rval) 5666 return rval; 5667 } else 5668 return QLA_SUCCESS; 5669 } 5670 5671 return rval; 5672 } 5673 5674 static int 5675 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5676 { 5677 int rval = QLA_SUCCESS; 5678 uint32_t o_drv_lockid, n_drv_lockid; 5679 unsigned long lock_recovery_timeout; 5680 5681 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5682 retry_lockid: 5683 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5684 if (rval) 5685 goto exit; 5686 5687 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5688 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5689 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5690 return QLA_SUCCESS; 5691 else 5692 return QLA_FUNCTION_FAILED; 5693 } 5694 5695 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5696 if (rval) 5697 goto exit; 5698 5699 if (o_drv_lockid == n_drv_lockid) { 5700 msleep(QLA83XX_WAIT_LOGIC_MS); 5701 goto retry_lockid; 5702 } else 5703 return QLA_SUCCESS; 5704 5705 exit: 5706 return rval; 5707 } 5708 5709 /* 5710 * Context: task, can sleep 5711 */ 5712 void 5713 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5714 { 5715 uint32_t data; 5716 uint32_t lock_owner; 5717 struct qla_hw_data *ha = base_vha->hw; 5718 5719 might_sleep(); 5720 5721 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5722 retry_lock: 5723 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5724 == QLA_SUCCESS) { 5725 if (data) { 5726 /* Setting lock-id to our function-number */ 5727 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5728 ha->portnum); 5729 } else { 5730 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5731 &lock_owner); 5732 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5733 "Failed to acquire IDC lock, acquired by %d, " 5734 "retrying...\n", lock_owner); 5735 5736 /* Retry/Perform IDC-Lock recovery */ 5737 if (qla83xx_idc_lock_recovery(base_vha) 5738 == QLA_SUCCESS) { 5739 msleep(QLA83XX_WAIT_LOGIC_MS); 5740 goto retry_lock; 5741 } else 5742 ql_log(ql_log_warn, base_vha, 0xb075, 5743 "IDC Lock recovery FAILED.\n"); 5744 } 5745 5746 } 5747 5748 return; 5749 } 5750 5751 static bool 5752 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 5753 struct purex_entry_24xx *purex) 5754 { 5755 char fwstr[16]; 5756 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 5757 struct port_database_24xx *pdb; 5758 5759 /* Domain Controller is always logged-out. */ 5760 /* if RDP request is not from Domain Controller: */ 5761 if (sid != 0xfffc01) 5762 return false; 5763 5764 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 5765 5766 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 5767 if (!pdb) { 5768 ql_dbg(ql_dbg_init, vha, 0x0181, 5769 "%s: Failed allocate pdb\n", __func__); 5770 } else if (qla24xx_get_port_database(vha, 5771 le16_to_cpu(purex->nport_handle), pdb)) { 5772 ql_dbg(ql_dbg_init, vha, 0x0181, 5773 "%s: Failed get pdb sid=%x\n", __func__, sid); 5774 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 5775 pdb->current_login_state != PDS_PRLI_COMPLETE) { 5776 ql_dbg(ql_dbg_init, vha, 0x0181, 5777 "%s: Port not logged in sid=%#x\n", __func__, sid); 5778 } else { 5779 /* RDP request is from logged in port */ 5780 kfree(pdb); 5781 return false; 5782 } 5783 kfree(pdb); 5784 5785 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 5786 fwstr[strcspn(fwstr, " ")] = 0; 5787 /* if FW version allows RDP response length upto 2048 bytes: */ 5788 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 5789 return false; 5790 5791 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 5792 5793 /* RDP response length is to be reduced to maximum 256 bytes */ 5794 return true; 5795 } 5796 5797 /* 5798 * Function Name: qla24xx_process_purex_iocb 5799 * 5800 * Description: 5801 * Prepare a RDP response and send to Fabric switch 5802 * 5803 * PARAMETERS: 5804 * vha: SCSI qla host 5805 * purex: RDP request received by HBA 5806 */ 5807 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 5808 struct purex_item *item) 5809 { 5810 struct qla_hw_data *ha = vha->hw; 5811 struct purex_entry_24xx *purex = 5812 (struct purex_entry_24xx *)&item->iocb; 5813 dma_addr_t rsp_els_dma; 5814 dma_addr_t rsp_payload_dma; 5815 dma_addr_t stat_dma; 5816 dma_addr_t sfp_dma; 5817 struct els_entry_24xx *rsp_els = NULL; 5818 struct rdp_rsp_payload *rsp_payload = NULL; 5819 struct link_statistics *stat = NULL; 5820 uint8_t *sfp = NULL; 5821 uint16_t sfp_flags = 0; 5822 uint rsp_payload_length = sizeof(*rsp_payload); 5823 int rval; 5824 5825 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 5826 "%s: Enter\n", __func__); 5827 5828 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 5829 "-------- ELS REQ -------\n"); 5830 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 5831 purex, sizeof(*purex)); 5832 5833 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 5834 rsp_payload_length = 5835 offsetof(typeof(*rsp_payload), optical_elmt_desc); 5836 ql_dbg(ql_dbg_init, vha, 0x0181, 5837 "Reducing RSP payload length to %u bytes...\n", 5838 rsp_payload_length); 5839 } 5840 5841 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 5842 &rsp_els_dma, GFP_KERNEL); 5843 if (!rsp_els) { 5844 ql_log(ql_log_warn, vha, 0x0183, 5845 "Failed allocate dma buffer ELS RSP.\n"); 5846 goto dealloc; 5847 } 5848 5849 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 5850 &rsp_payload_dma, GFP_KERNEL); 5851 if (!rsp_payload) { 5852 ql_log(ql_log_warn, vha, 0x0184, 5853 "Failed allocate dma buffer ELS RSP payload.\n"); 5854 goto dealloc; 5855 } 5856 5857 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 5858 &sfp_dma, GFP_KERNEL); 5859 5860 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 5861 &stat_dma, GFP_KERNEL); 5862 5863 /* Prepare Response IOCB */ 5864 rsp_els->entry_type = ELS_IOCB_TYPE; 5865 rsp_els->entry_count = 1; 5866 rsp_els->sys_define = 0; 5867 rsp_els->entry_status = 0; 5868 rsp_els->handle = 0; 5869 rsp_els->nport_handle = purex->nport_handle; 5870 rsp_els->tx_dsd_count = cpu_to_le16(1); 5871 rsp_els->vp_index = purex->vp_idx; 5872 rsp_els->sof_type = EST_SOFI3; 5873 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 5874 rsp_els->rx_dsd_count = 0; 5875 rsp_els->opcode = purex->els_frame_payload[0]; 5876 5877 rsp_els->d_id[0] = purex->s_id[0]; 5878 rsp_els->d_id[1] = purex->s_id[1]; 5879 rsp_els->d_id[2] = purex->s_id[2]; 5880 5881 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 5882 rsp_els->rx_byte_count = 0; 5883 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 5884 5885 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 5886 rsp_els->tx_len = rsp_els->tx_byte_count; 5887 5888 rsp_els->rx_address = 0; 5889 rsp_els->rx_len = 0; 5890 5891 /* Prepare Response Payload */ 5892 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 5893 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 5894 sizeof(rsp_payload->hdr)); 5895 5896 /* Link service Request Info Descriptor */ 5897 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 5898 rsp_payload->ls_req_info_desc.desc_len = 5899 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 5900 rsp_payload->ls_req_info_desc.req_payload_word_0 = 5901 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 5902 5903 /* Link service Request Info Descriptor 2 */ 5904 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 5905 rsp_payload->ls_req_info_desc2.desc_len = 5906 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 5907 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 5908 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 5909 5910 5911 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 5912 rsp_payload->sfp_diag_desc.desc_len = 5913 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 5914 5915 if (sfp) { 5916 /* SFP Flags */ 5917 memset(sfp, 0, SFP_RTDI_LEN); 5918 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 5919 if (!rval) { 5920 /* SFP Flags bits 3-0: Port Tx Laser Type */ 5921 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 5922 sfp_flags |= BIT_0; /* short wave */ 5923 else if (sfp[0] & BIT_1) 5924 sfp_flags |= BIT_1; /* long wave 1310nm */ 5925 else if (sfp[1] & BIT_4) 5926 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 5927 } 5928 5929 /* SFP Type */ 5930 memset(sfp, 0, SFP_RTDI_LEN); 5931 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 5932 if (!rval) { 5933 sfp_flags |= BIT_4; /* optical */ 5934 if (sfp[0] == 0x3) 5935 sfp_flags |= BIT_6; /* sfp+ */ 5936 } 5937 5938 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 5939 5940 /* SFP Diagnostics */ 5941 memset(sfp, 0, SFP_RTDI_LEN); 5942 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 5943 if (!rval) { 5944 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 5945 rsp_payload->sfp_diag_desc.temperature = trx[0]; 5946 rsp_payload->sfp_diag_desc.vcc = trx[1]; 5947 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 5948 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 5949 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 5950 } 5951 } 5952 5953 /* Port Speed Descriptor */ 5954 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 5955 rsp_payload->port_speed_desc.desc_len = 5956 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 5957 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 5958 qla25xx_fdmi_port_speed_capability(ha)); 5959 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 5960 qla25xx_fdmi_port_speed_currently(ha)); 5961 5962 /* Link Error Status Descriptor */ 5963 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 5964 rsp_payload->ls_err_desc.desc_len = 5965 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 5966 5967 if (stat) { 5968 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 5969 if (!rval) { 5970 rsp_payload->ls_err_desc.link_fail_cnt = 5971 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 5972 rsp_payload->ls_err_desc.loss_sync_cnt = 5973 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 5974 rsp_payload->ls_err_desc.loss_sig_cnt = 5975 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 5976 rsp_payload->ls_err_desc.prim_seq_err_cnt = 5977 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 5978 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 5979 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 5980 rsp_payload->ls_err_desc.inval_crc_cnt = 5981 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 5982 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 5983 } 5984 } 5985 5986 /* Portname Descriptor */ 5987 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 5988 rsp_payload->port_name_diag_desc.desc_len = 5989 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 5990 memcpy(rsp_payload->port_name_diag_desc.WWNN, 5991 vha->node_name, 5992 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 5993 memcpy(rsp_payload->port_name_diag_desc.WWPN, 5994 vha->port_name, 5995 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 5996 5997 /* F-Port Portname Descriptor */ 5998 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 5999 rsp_payload->port_name_direct_desc.desc_len = 6000 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6001 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6002 vha->fabric_node_name, 6003 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6004 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6005 vha->fabric_port_name, 6006 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6007 6008 /* Bufer Credit Descriptor */ 6009 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6010 rsp_payload->buffer_credit_desc.desc_len = 6011 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6012 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6013 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6014 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6015 6016 if (ha->flags.plogi_template_valid) { 6017 uint32_t tmp = 6018 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6019 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6020 } 6021 6022 if (rsp_payload_length < sizeof(*rsp_payload)) 6023 goto send; 6024 6025 /* Optical Element Descriptor, Temperature */ 6026 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6027 rsp_payload->optical_elmt_desc[0].desc_len = 6028 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6029 /* Optical Element Descriptor, Voltage */ 6030 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6031 rsp_payload->optical_elmt_desc[1].desc_len = 6032 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6033 /* Optical Element Descriptor, Tx Bias Current */ 6034 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6035 rsp_payload->optical_elmt_desc[2].desc_len = 6036 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6037 /* Optical Element Descriptor, Tx Power */ 6038 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6039 rsp_payload->optical_elmt_desc[3].desc_len = 6040 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6041 /* Optical Element Descriptor, Rx Power */ 6042 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6043 rsp_payload->optical_elmt_desc[4].desc_len = 6044 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6045 6046 if (sfp) { 6047 memset(sfp, 0, SFP_RTDI_LEN); 6048 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6049 if (!rval) { 6050 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6051 6052 /* Optical Element Descriptor, Temperature */ 6053 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6054 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6055 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6056 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6057 rsp_payload->optical_elmt_desc[0].element_flags = 6058 cpu_to_be32(1 << 28); 6059 6060 /* Optical Element Descriptor, Voltage */ 6061 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6062 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6063 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6064 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6065 rsp_payload->optical_elmt_desc[1].element_flags = 6066 cpu_to_be32(2 << 28); 6067 6068 /* Optical Element Descriptor, Tx Bias Current */ 6069 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6070 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6071 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6072 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6073 rsp_payload->optical_elmt_desc[2].element_flags = 6074 cpu_to_be32(3 << 28); 6075 6076 /* Optical Element Descriptor, Tx Power */ 6077 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6078 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6079 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6080 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6081 rsp_payload->optical_elmt_desc[3].element_flags = 6082 cpu_to_be32(4 << 28); 6083 6084 /* Optical Element Descriptor, Rx Power */ 6085 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6086 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6087 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6088 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6089 rsp_payload->optical_elmt_desc[4].element_flags = 6090 cpu_to_be32(5 << 28); 6091 } 6092 6093 memset(sfp, 0, SFP_RTDI_LEN); 6094 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6095 if (!rval) { 6096 /* Temperature high/low alarm/warning */ 6097 rsp_payload->optical_elmt_desc[0].element_flags |= 6098 cpu_to_be32( 6099 (sfp[0] >> 7 & 1) << 3 | 6100 (sfp[0] >> 6 & 1) << 2 | 6101 (sfp[4] >> 7 & 1) << 1 | 6102 (sfp[4] >> 6 & 1) << 0); 6103 6104 /* Voltage high/low alarm/warning */ 6105 rsp_payload->optical_elmt_desc[1].element_flags |= 6106 cpu_to_be32( 6107 (sfp[0] >> 5 & 1) << 3 | 6108 (sfp[0] >> 4 & 1) << 2 | 6109 (sfp[4] >> 5 & 1) << 1 | 6110 (sfp[4] >> 4 & 1) << 0); 6111 6112 /* Tx Bias Current high/low alarm/warning */ 6113 rsp_payload->optical_elmt_desc[2].element_flags |= 6114 cpu_to_be32( 6115 (sfp[0] >> 3 & 1) << 3 | 6116 (sfp[0] >> 2 & 1) << 2 | 6117 (sfp[4] >> 3 & 1) << 1 | 6118 (sfp[4] >> 2 & 1) << 0); 6119 6120 /* Tx Power high/low alarm/warning */ 6121 rsp_payload->optical_elmt_desc[3].element_flags |= 6122 cpu_to_be32( 6123 (sfp[0] >> 1 & 1) << 3 | 6124 (sfp[0] >> 0 & 1) << 2 | 6125 (sfp[4] >> 1 & 1) << 1 | 6126 (sfp[4] >> 0 & 1) << 0); 6127 6128 /* Rx Power high/low alarm/warning */ 6129 rsp_payload->optical_elmt_desc[4].element_flags |= 6130 cpu_to_be32( 6131 (sfp[1] >> 7 & 1) << 3 | 6132 (sfp[1] >> 6 & 1) << 2 | 6133 (sfp[5] >> 7 & 1) << 1 | 6134 (sfp[5] >> 6 & 1) << 0); 6135 } 6136 } 6137 6138 /* Optical Product Data Descriptor */ 6139 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6140 rsp_payload->optical_prod_desc.desc_len = 6141 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6142 6143 if (sfp) { 6144 memset(sfp, 0, SFP_RTDI_LEN); 6145 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6146 if (!rval) { 6147 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6148 sfp + 0, 6149 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6150 memcpy(rsp_payload->optical_prod_desc.part_number, 6151 sfp + 20, 6152 sizeof(rsp_payload->optical_prod_desc.part_number)); 6153 memcpy(rsp_payload->optical_prod_desc.revision, 6154 sfp + 36, 6155 sizeof(rsp_payload->optical_prod_desc.revision)); 6156 memcpy(rsp_payload->optical_prod_desc.serial_number, 6157 sfp + 48, 6158 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6159 } 6160 6161 memset(sfp, 0, SFP_RTDI_LEN); 6162 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6163 if (!rval) { 6164 memcpy(rsp_payload->optical_prod_desc.date, 6165 sfp + 0, 6166 sizeof(rsp_payload->optical_prod_desc.date)); 6167 } 6168 } 6169 6170 send: 6171 ql_dbg(ql_dbg_init, vha, 0x0183, 6172 "Sending ELS Response to RDP Request...\n"); 6173 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6174 "-------- ELS RSP -------\n"); 6175 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6176 rsp_els, sizeof(*rsp_els)); 6177 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6178 "-------- ELS RSP PAYLOAD -------\n"); 6179 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6180 rsp_payload, rsp_payload_length); 6181 6182 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6183 6184 if (rval) { 6185 ql_log(ql_log_warn, vha, 0x0188, 6186 "%s: iocb failed to execute -> %x\n", __func__, rval); 6187 } else if (rsp_els->comp_status) { 6188 ql_log(ql_log_warn, vha, 0x0189, 6189 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6190 __func__, rsp_els->comp_status, 6191 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6192 } else { 6193 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6194 } 6195 6196 dealloc: 6197 if (stat) 6198 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6199 stat, stat_dma); 6200 if (sfp) 6201 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6202 sfp, sfp_dma); 6203 if (rsp_payload) 6204 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6205 rsp_payload, rsp_payload_dma); 6206 if (rsp_els) 6207 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6208 rsp_els, rsp_els_dma); 6209 } 6210 6211 void 6212 qla24xx_free_purex_item(struct purex_item *item) 6213 { 6214 if (item == &item->vha->default_item) 6215 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6216 else 6217 kfree(item); 6218 } 6219 6220 void qla24xx_process_purex_list(struct purex_list *list) 6221 { 6222 struct list_head head = LIST_HEAD_INIT(head); 6223 struct purex_item *item, *next; 6224 ulong flags; 6225 6226 spin_lock_irqsave(&list->lock, flags); 6227 list_splice_init(&list->head, &head); 6228 spin_unlock_irqrestore(&list->lock, flags); 6229 6230 list_for_each_entry_safe(item, next, &head, list) { 6231 list_del(&item->list); 6232 item->process_item(item->vha, item); 6233 qla24xx_free_purex_item(item); 6234 } 6235 } 6236 6237 /* 6238 * Context: task, can sleep 6239 */ 6240 void 6241 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6242 { 6243 #if 0 6244 uint16_t options = (requester_id << 15) | BIT_7; 6245 #endif 6246 uint16_t retry; 6247 uint32_t data; 6248 struct qla_hw_data *ha = base_vha->hw; 6249 6250 might_sleep(); 6251 6252 /* IDC-unlock implementation using driver-unlock/lock-id 6253 * remote registers 6254 */ 6255 retry = 0; 6256 retry_unlock: 6257 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6258 == QLA_SUCCESS) { 6259 if (data == ha->portnum) { 6260 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6261 /* Clearing lock-id by setting 0xff */ 6262 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6263 } else if (retry < 10) { 6264 /* SV: XXX: IDC unlock retrying needed here? */ 6265 6266 /* Retry for IDC-unlock */ 6267 msleep(QLA83XX_WAIT_LOGIC_MS); 6268 retry++; 6269 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6270 "Failed to release IDC lock, retrying=%d\n", retry); 6271 goto retry_unlock; 6272 } 6273 } else if (retry < 10) { 6274 /* Retry for IDC-unlock */ 6275 msleep(QLA83XX_WAIT_LOGIC_MS); 6276 retry++; 6277 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6278 "Failed to read drv-lockid, retrying=%d\n", retry); 6279 goto retry_unlock; 6280 } 6281 6282 return; 6283 6284 #if 0 6285 /* XXX: IDC-unlock implementation using access-control mbx */ 6286 retry = 0; 6287 retry_unlock2: 6288 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6289 if (retry < 10) { 6290 /* Retry for IDC-unlock */ 6291 msleep(QLA83XX_WAIT_LOGIC_MS); 6292 retry++; 6293 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6294 "Failed to release IDC lock, retrying=%d\n", retry); 6295 goto retry_unlock2; 6296 } 6297 } 6298 6299 return; 6300 #endif 6301 } 6302 6303 int 6304 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6305 { 6306 int rval = QLA_SUCCESS; 6307 struct qla_hw_data *ha = vha->hw; 6308 uint32_t drv_presence; 6309 6310 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6311 if (rval == QLA_SUCCESS) { 6312 drv_presence |= (1 << ha->portnum); 6313 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6314 drv_presence); 6315 } 6316 6317 return rval; 6318 } 6319 6320 int 6321 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6322 { 6323 int rval = QLA_SUCCESS; 6324 6325 qla83xx_idc_lock(vha, 0); 6326 rval = __qla83xx_set_drv_presence(vha); 6327 qla83xx_idc_unlock(vha, 0); 6328 6329 return rval; 6330 } 6331 6332 int 6333 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6334 { 6335 int rval = QLA_SUCCESS; 6336 struct qla_hw_data *ha = vha->hw; 6337 uint32_t drv_presence; 6338 6339 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6340 if (rval == QLA_SUCCESS) { 6341 drv_presence &= ~(1 << ha->portnum); 6342 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6343 drv_presence); 6344 } 6345 6346 return rval; 6347 } 6348 6349 int 6350 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6351 { 6352 int rval = QLA_SUCCESS; 6353 6354 qla83xx_idc_lock(vha, 0); 6355 rval = __qla83xx_clear_drv_presence(vha); 6356 qla83xx_idc_unlock(vha, 0); 6357 6358 return rval; 6359 } 6360 6361 static void 6362 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6363 { 6364 struct qla_hw_data *ha = vha->hw; 6365 uint32_t drv_ack, drv_presence; 6366 unsigned long ack_timeout; 6367 6368 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6369 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6370 while (1) { 6371 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6372 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6373 if ((drv_ack & drv_presence) == drv_presence) 6374 break; 6375 6376 if (time_after_eq(jiffies, ack_timeout)) { 6377 ql_log(ql_log_warn, vha, 0xb067, 6378 "RESET ACK TIMEOUT! drv_presence=0x%x " 6379 "drv_ack=0x%x\n", drv_presence, drv_ack); 6380 /* 6381 * The function(s) which did not ack in time are forced 6382 * to withdraw any further participation in the IDC 6383 * reset. 6384 */ 6385 if (drv_ack != drv_presence) 6386 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6387 drv_ack); 6388 break; 6389 } 6390 6391 qla83xx_idc_unlock(vha, 0); 6392 msleep(1000); 6393 qla83xx_idc_lock(vha, 0); 6394 } 6395 6396 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6397 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6398 } 6399 6400 static int 6401 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6402 { 6403 int rval = QLA_SUCCESS; 6404 uint32_t idc_control; 6405 6406 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6407 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6408 6409 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6410 __qla83xx_get_idc_control(vha, &idc_control); 6411 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6412 __qla83xx_set_idc_control(vha, 0); 6413 6414 qla83xx_idc_unlock(vha, 0); 6415 rval = qla83xx_restart_nic_firmware(vha); 6416 qla83xx_idc_lock(vha, 0); 6417 6418 if (rval != QLA_SUCCESS) { 6419 ql_log(ql_log_fatal, vha, 0xb06a, 6420 "Failed to restart NIC f/w.\n"); 6421 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6422 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6423 } else { 6424 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6425 "Success in restarting nic f/w.\n"); 6426 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6427 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6428 } 6429 6430 return rval; 6431 } 6432 6433 /* Assumes idc_lock always held on entry */ 6434 int 6435 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6436 { 6437 struct qla_hw_data *ha = base_vha->hw; 6438 int rval = QLA_SUCCESS; 6439 unsigned long dev_init_timeout; 6440 uint32_t dev_state; 6441 6442 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6443 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6444 6445 while (1) { 6446 6447 if (time_after_eq(jiffies, dev_init_timeout)) { 6448 ql_log(ql_log_warn, base_vha, 0xb06e, 6449 "Initialization TIMEOUT!\n"); 6450 /* Init timeout. Disable further NIC Core 6451 * communication. 6452 */ 6453 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6454 QLA8XXX_DEV_FAILED); 6455 ql_log(ql_log_info, base_vha, 0xb06f, 6456 "HW State: FAILED.\n"); 6457 } 6458 6459 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6460 switch (dev_state) { 6461 case QLA8XXX_DEV_READY: 6462 if (ha->flags.nic_core_reset_owner) 6463 qla83xx_idc_audit(base_vha, 6464 IDC_AUDIT_COMPLETION); 6465 ha->flags.nic_core_reset_owner = 0; 6466 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6467 "Reset_owner reset by 0x%x.\n", 6468 ha->portnum); 6469 goto exit; 6470 case QLA8XXX_DEV_COLD: 6471 if (ha->flags.nic_core_reset_owner) 6472 rval = qla83xx_device_bootstrap(base_vha); 6473 else { 6474 /* Wait for AEN to change device-state */ 6475 qla83xx_idc_unlock(base_vha, 0); 6476 msleep(1000); 6477 qla83xx_idc_lock(base_vha, 0); 6478 } 6479 break; 6480 case QLA8XXX_DEV_INITIALIZING: 6481 /* Wait for AEN to change device-state */ 6482 qla83xx_idc_unlock(base_vha, 0); 6483 msleep(1000); 6484 qla83xx_idc_lock(base_vha, 0); 6485 break; 6486 case QLA8XXX_DEV_NEED_RESET: 6487 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6488 qla83xx_need_reset_handler(base_vha); 6489 else { 6490 /* Wait for AEN to change device-state */ 6491 qla83xx_idc_unlock(base_vha, 0); 6492 msleep(1000); 6493 qla83xx_idc_lock(base_vha, 0); 6494 } 6495 /* reset timeout value after need reset handler */ 6496 dev_init_timeout = jiffies + 6497 (ha->fcoe_dev_init_timeout * HZ); 6498 break; 6499 case QLA8XXX_DEV_NEED_QUIESCENT: 6500 /* XXX: DEBUG for now */ 6501 qla83xx_idc_unlock(base_vha, 0); 6502 msleep(1000); 6503 qla83xx_idc_lock(base_vha, 0); 6504 break; 6505 case QLA8XXX_DEV_QUIESCENT: 6506 /* XXX: DEBUG for now */ 6507 if (ha->flags.quiesce_owner) 6508 goto exit; 6509 6510 qla83xx_idc_unlock(base_vha, 0); 6511 msleep(1000); 6512 qla83xx_idc_lock(base_vha, 0); 6513 dev_init_timeout = jiffies + 6514 (ha->fcoe_dev_init_timeout * HZ); 6515 break; 6516 case QLA8XXX_DEV_FAILED: 6517 if (ha->flags.nic_core_reset_owner) 6518 qla83xx_idc_audit(base_vha, 6519 IDC_AUDIT_COMPLETION); 6520 ha->flags.nic_core_reset_owner = 0; 6521 __qla83xx_clear_drv_presence(base_vha); 6522 qla83xx_idc_unlock(base_vha, 0); 6523 qla8xxx_dev_failed_handler(base_vha); 6524 rval = QLA_FUNCTION_FAILED; 6525 qla83xx_idc_lock(base_vha, 0); 6526 goto exit; 6527 case QLA8XXX_BAD_VALUE: 6528 qla83xx_idc_unlock(base_vha, 0); 6529 msleep(1000); 6530 qla83xx_idc_lock(base_vha, 0); 6531 break; 6532 default: 6533 ql_log(ql_log_warn, base_vha, 0xb071, 6534 "Unknown Device State: %x.\n", dev_state); 6535 qla83xx_idc_unlock(base_vha, 0); 6536 qla8xxx_dev_failed_handler(base_vha); 6537 rval = QLA_FUNCTION_FAILED; 6538 qla83xx_idc_lock(base_vha, 0); 6539 goto exit; 6540 } 6541 } 6542 6543 exit: 6544 return rval; 6545 } 6546 6547 void 6548 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6549 { 6550 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6551 board_disable); 6552 struct pci_dev *pdev = ha->pdev; 6553 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6554 6555 ql_log(ql_log_warn, base_vha, 0x015b, 6556 "Disabling adapter.\n"); 6557 6558 if (!atomic_read(&pdev->enable_cnt)) { 6559 ql_log(ql_log_info, base_vha, 0xfffc, 6560 "PCI device disabled, no action req for PCI error=%lx\n", 6561 base_vha->pci_flags); 6562 return; 6563 } 6564 6565 /* 6566 * if UNLOADING flag is already set, then continue unload, 6567 * where it was set first. 6568 */ 6569 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6570 return; 6571 6572 qla2x00_wait_for_sess_deletion(base_vha); 6573 6574 qla2x00_delete_all_vps(ha, base_vha); 6575 6576 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6577 6578 qla2x00_dfs_remove(base_vha); 6579 6580 qla84xx_put_chip(base_vha); 6581 6582 if (base_vha->timer_active) 6583 qla2x00_stop_timer(base_vha); 6584 6585 base_vha->flags.online = 0; 6586 6587 qla2x00_destroy_deferred_work(ha); 6588 6589 /* 6590 * Do not try to stop beacon blink as it will issue a mailbox 6591 * command. 6592 */ 6593 qla2x00_free_sysfs_attr(base_vha, false); 6594 6595 fc_remove_host(base_vha->host); 6596 6597 scsi_remove_host(base_vha->host); 6598 6599 base_vha->flags.init_done = 0; 6600 qla25xx_delete_queues(base_vha); 6601 qla2x00_free_fcports(base_vha); 6602 qla2x00_free_irqs(base_vha); 6603 qla2x00_mem_free(ha); 6604 qla82xx_md_free(base_vha); 6605 qla2x00_free_queues(ha); 6606 6607 qla2x00_unmap_iobases(ha); 6608 6609 pci_release_selected_regions(ha->pdev, ha->bars); 6610 pci_disable_pcie_error_reporting(pdev); 6611 pci_disable_device(pdev); 6612 6613 /* 6614 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6615 */ 6616 } 6617 6618 /************************************************************************** 6619 * qla2x00_do_dpc 6620 * This kernel thread is a task that is schedule by the interrupt handler 6621 * to perform the background processing for interrupts. 6622 * 6623 * Notes: 6624 * This task always run in the context of a kernel thread. It 6625 * is kick-off by the driver's detect code and starts up 6626 * up one per adapter. It immediately goes to sleep and waits for 6627 * some fibre event. When either the interrupt handler or 6628 * the timer routine detects a event it will one of the task 6629 * bits then wake us up. 6630 **************************************************************************/ 6631 static int 6632 qla2x00_do_dpc(void *data) 6633 { 6634 scsi_qla_host_t *base_vha; 6635 struct qla_hw_data *ha; 6636 uint32_t online; 6637 struct qla_qpair *qpair; 6638 6639 ha = (struct qla_hw_data *)data; 6640 base_vha = pci_get_drvdata(ha->pdev); 6641 6642 set_user_nice(current, MIN_NICE); 6643 6644 set_current_state(TASK_INTERRUPTIBLE); 6645 while (!kthread_should_stop()) { 6646 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6647 "DPC handler sleeping.\n"); 6648 6649 schedule(); 6650 6651 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6652 qla_pci_set_eeh_busy(base_vha); 6653 6654 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6655 goto end_loop; 6656 6657 if (ha->flags.eeh_busy) { 6658 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6659 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6660 goto end_loop; 6661 } 6662 6663 ha->dpc_active = 1; 6664 6665 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6666 "DPC handler waking up, dpc_flags=0x%lx.\n", 6667 base_vha->dpc_flags); 6668 6669 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6670 break; 6671 6672 if (IS_P3P_TYPE(ha)) { 6673 if (IS_QLA8044(ha)) { 6674 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6675 &base_vha->dpc_flags)) { 6676 qla8044_idc_lock(ha); 6677 qla8044_wr_direct(base_vha, 6678 QLA8044_CRB_DEV_STATE_INDEX, 6679 QLA8XXX_DEV_FAILED); 6680 qla8044_idc_unlock(ha); 6681 ql_log(ql_log_info, base_vha, 0x4004, 6682 "HW State: FAILED.\n"); 6683 qla8044_device_state_handler(base_vha); 6684 continue; 6685 } 6686 6687 } else { 6688 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6689 &base_vha->dpc_flags)) { 6690 qla82xx_idc_lock(ha); 6691 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6692 QLA8XXX_DEV_FAILED); 6693 qla82xx_idc_unlock(ha); 6694 ql_log(ql_log_info, base_vha, 0x0151, 6695 "HW State: FAILED.\n"); 6696 qla82xx_device_state_handler(base_vha); 6697 continue; 6698 } 6699 } 6700 6701 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6702 &base_vha->dpc_flags)) { 6703 6704 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6705 "FCoE context reset scheduled.\n"); 6706 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6707 &base_vha->dpc_flags))) { 6708 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6709 /* FCoE-ctx reset failed. 6710 * Escalate to chip-reset 6711 */ 6712 set_bit(ISP_ABORT_NEEDED, 6713 &base_vha->dpc_flags); 6714 } 6715 clear_bit(ABORT_ISP_ACTIVE, 6716 &base_vha->dpc_flags); 6717 } 6718 6719 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6720 "FCoE context reset end.\n"); 6721 } 6722 } else if (IS_QLAFX00(ha)) { 6723 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6724 &base_vha->dpc_flags)) { 6725 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6726 "Firmware Reset Recovery\n"); 6727 if (qlafx00_reset_initialize(base_vha)) { 6728 /* Failed. Abort isp later. */ 6729 if (!test_bit(UNLOADING, 6730 &base_vha->dpc_flags)) { 6731 set_bit(ISP_UNRECOVERABLE, 6732 &base_vha->dpc_flags); 6733 ql_dbg(ql_dbg_dpc, base_vha, 6734 0x4021, 6735 "Reset Recovery Failed\n"); 6736 } 6737 } 6738 } 6739 6740 if (test_and_clear_bit(FX00_TARGET_SCAN, 6741 &base_vha->dpc_flags)) { 6742 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 6743 "ISPFx00 Target Scan scheduled\n"); 6744 if (qlafx00_rescan_isp(base_vha)) { 6745 if (!test_bit(UNLOADING, 6746 &base_vha->dpc_flags)) 6747 set_bit(ISP_UNRECOVERABLE, 6748 &base_vha->dpc_flags); 6749 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 6750 "ISPFx00 Target Scan Failed\n"); 6751 } 6752 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 6753 "ISPFx00 Target Scan End\n"); 6754 } 6755 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 6756 &base_vha->dpc_flags)) { 6757 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 6758 "ISPFx00 Host Info resend scheduled\n"); 6759 qlafx00_fx_disc(base_vha, 6760 &base_vha->hw->mr.fcport, 6761 FXDISC_REG_HOST_INFO); 6762 } 6763 } 6764 6765 if (test_and_clear_bit(DETECT_SFP_CHANGE, 6766 &base_vha->dpc_flags)) { 6767 /* Semantic: 6768 * - NO-OP -- await next ISP-ABORT. Preferred method 6769 * to minimize disruptions that will occur 6770 * when a forced chip-reset occurs. 6771 * - Force -- ISP-ABORT scheduled. 6772 */ 6773 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 6774 } 6775 6776 if (test_and_clear_bit 6777 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 6778 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 6779 bool do_reset = true; 6780 6781 switch (base_vha->qlini_mode) { 6782 case QLA2XXX_INI_MODE_ENABLED: 6783 break; 6784 case QLA2XXX_INI_MODE_DISABLED: 6785 if (!qla_tgt_mode_enabled(base_vha) && 6786 !ha->flags.fw_started) 6787 do_reset = false; 6788 break; 6789 case QLA2XXX_INI_MODE_DUAL: 6790 if (!qla_dual_mode_enabled(base_vha) && 6791 !ha->flags.fw_started) 6792 do_reset = false; 6793 break; 6794 default: 6795 break; 6796 } 6797 6798 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 6799 &base_vha->dpc_flags))) { 6800 base_vha->flags.online = 1; 6801 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 6802 "ISP abort scheduled.\n"); 6803 if (ha->isp_ops->abort_isp(base_vha)) { 6804 /* failed. retry later */ 6805 set_bit(ISP_ABORT_NEEDED, 6806 &base_vha->dpc_flags); 6807 } 6808 clear_bit(ABORT_ISP_ACTIVE, 6809 &base_vha->dpc_flags); 6810 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 6811 "ISP abort end.\n"); 6812 } 6813 } 6814 6815 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 6816 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 6817 qla24xx_process_purex_list 6818 (&base_vha->purex_list); 6819 clear_bit(PROCESS_PUREX_IOCB, 6820 &base_vha->dpc_flags); 6821 } 6822 } 6823 6824 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, 6825 &base_vha->dpc_flags)) { 6826 qla2x00_update_fcports(base_vha); 6827 } 6828 6829 if (IS_QLAFX00(ha)) 6830 goto loop_resync_check; 6831 6832 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 6833 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 6834 "Quiescence mode scheduled.\n"); 6835 if (IS_P3P_TYPE(ha)) { 6836 if (IS_QLA82XX(ha)) 6837 qla82xx_device_state_handler(base_vha); 6838 if (IS_QLA8044(ha)) 6839 qla8044_device_state_handler(base_vha); 6840 clear_bit(ISP_QUIESCE_NEEDED, 6841 &base_vha->dpc_flags); 6842 if (!ha->flags.quiesce_owner) { 6843 qla2x00_perform_loop_resync(base_vha); 6844 if (IS_QLA82XX(ha)) { 6845 qla82xx_idc_lock(ha); 6846 qla82xx_clear_qsnt_ready( 6847 base_vha); 6848 qla82xx_idc_unlock(ha); 6849 } else if (IS_QLA8044(ha)) { 6850 qla8044_idc_lock(ha); 6851 qla8044_clear_qsnt_ready( 6852 base_vha); 6853 qla8044_idc_unlock(ha); 6854 } 6855 } 6856 } else { 6857 clear_bit(ISP_QUIESCE_NEEDED, 6858 &base_vha->dpc_flags); 6859 qla2x00_quiesce_io(base_vha); 6860 } 6861 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 6862 "Quiescence mode end.\n"); 6863 } 6864 6865 if (test_and_clear_bit(RESET_MARKER_NEEDED, 6866 &base_vha->dpc_flags) && 6867 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 6868 6869 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 6870 "Reset marker scheduled.\n"); 6871 qla2x00_rst_aen(base_vha); 6872 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 6873 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 6874 "Reset marker end.\n"); 6875 } 6876 6877 /* Retry each device up to login retry count */ 6878 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 6879 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 6880 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 6881 6882 if (!base_vha->relogin_jif || 6883 time_after_eq(jiffies, base_vha->relogin_jif)) { 6884 base_vha->relogin_jif = jiffies + HZ; 6885 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 6886 6887 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 6888 "Relogin scheduled.\n"); 6889 qla24xx_post_relogin_work(base_vha); 6890 } 6891 } 6892 loop_resync_check: 6893 if (test_and_clear_bit(LOOP_RESYNC_NEEDED, 6894 &base_vha->dpc_flags)) { 6895 6896 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 6897 "Loop resync scheduled.\n"); 6898 6899 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 6900 &base_vha->dpc_flags))) { 6901 6902 qla2x00_loop_resync(base_vha); 6903 6904 clear_bit(LOOP_RESYNC_ACTIVE, 6905 &base_vha->dpc_flags); 6906 } 6907 6908 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 6909 "Loop resync end.\n"); 6910 } 6911 6912 if (IS_QLAFX00(ha)) 6913 goto intr_on_check; 6914 6915 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 6916 atomic_read(&base_vha->loop_state) == LOOP_READY) { 6917 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 6918 qla2xxx_flash_npiv_conf(base_vha); 6919 } 6920 6921 intr_on_check: 6922 if (!ha->interrupts_on) 6923 ha->isp_ops->enable_intrs(ha); 6924 6925 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 6926 &base_vha->dpc_flags)) { 6927 if (ha->beacon_blink_led == 1) 6928 ha->isp_ops->beacon_blink(base_vha); 6929 } 6930 6931 /* qpair online check */ 6932 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 6933 &base_vha->dpc_flags)) { 6934 if (ha->flags.eeh_busy || 6935 ha->flags.pci_channel_io_perm_failure) 6936 online = 0; 6937 else 6938 online = 1; 6939 6940 mutex_lock(&ha->mq_lock); 6941 list_for_each_entry(qpair, &base_vha->qp_list, 6942 qp_list_elem) 6943 qpair->online = online; 6944 mutex_unlock(&ha->mq_lock); 6945 } 6946 6947 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 6948 &base_vha->dpc_flags)) { 6949 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 6950 6951 if (threshold > ha->orig_fw_xcb_count) 6952 threshold = ha->orig_fw_xcb_count; 6953 6954 ql_log(ql_log_info, base_vha, 0xffffff, 6955 "SET ZIO Activity exchange threshold to %d.\n", 6956 threshold); 6957 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 6958 ql_log(ql_log_info, base_vha, 0xffffff, 6959 "Unable to SET ZIO Activity exchange threshold to %d.\n", 6960 threshold); 6961 } 6962 } 6963 6964 if (!IS_QLAFX00(ha)) 6965 qla2x00_do_dpc_all_vps(base_vha); 6966 6967 if (test_and_clear_bit(N2N_LINK_RESET, 6968 &base_vha->dpc_flags)) { 6969 qla2x00_lip_reset(base_vha); 6970 } 6971 6972 ha->dpc_active = 0; 6973 end_loop: 6974 set_current_state(TASK_INTERRUPTIBLE); 6975 } /* End of while(1) */ 6976 __set_current_state(TASK_RUNNING); 6977 6978 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 6979 "DPC handler exiting.\n"); 6980 6981 /* 6982 * Make sure that nobody tries to wake us up again. 6983 */ 6984 ha->dpc_active = 0; 6985 6986 /* Cleanup any residual CTX SRBs. */ 6987 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6988 6989 return 0; 6990 } 6991 6992 void 6993 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 6994 { 6995 struct qla_hw_data *ha = vha->hw; 6996 struct task_struct *t = ha->dpc_thread; 6997 6998 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 6999 wake_up_process(t); 7000 } 7001 7002 /* 7003 * qla2x00_rst_aen 7004 * Processes asynchronous reset. 7005 * 7006 * Input: 7007 * ha = adapter block pointer. 7008 */ 7009 static void 7010 qla2x00_rst_aen(scsi_qla_host_t *vha) 7011 { 7012 if (vha->flags.online && !vha->flags.reset_active && 7013 !atomic_read(&vha->loop_down_timer) && 7014 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7015 do { 7016 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7017 7018 /* 7019 * Issue marker command only when we are going to start 7020 * the I/O. 7021 */ 7022 vha->marker_needed = 1; 7023 } while (!atomic_read(&vha->loop_down_timer) && 7024 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7025 } 7026 } 7027 7028 /************************************************************************** 7029 * qla2x00_timer 7030 * 7031 * Description: 7032 * One second timer 7033 * 7034 * Context: Interrupt 7035 ***************************************************************************/ 7036 void 7037 qla2x00_timer(struct timer_list *t) 7038 { 7039 scsi_qla_host_t *vha = from_timer(vha, t, timer); 7040 unsigned long cpu_flags = 0; 7041 int start_dpc = 0; 7042 int index; 7043 srb_t *sp; 7044 uint16_t w; 7045 struct qla_hw_data *ha = vha->hw; 7046 struct req_que *req; 7047 unsigned long flags; 7048 fc_port_t *fcport = NULL; 7049 7050 if (ha->flags.eeh_busy) { 7051 ql_dbg(ql_dbg_timer, vha, 0x6000, 7052 "EEH = %d, restarting timer.\n", 7053 ha->flags.eeh_busy); 7054 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7055 return; 7056 } 7057 7058 /* 7059 * Hardware read to raise pending EEH errors during mailbox waits. If 7060 * the read returns -1 then disable the board. 7061 */ 7062 if (!pci_channel_offline(ha->pdev)) { 7063 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7064 qla2x00_check_reg16_for_disconnect(vha, w); 7065 } 7066 7067 /* Make sure qla82xx_watchdog is run only for physical port */ 7068 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7069 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7070 start_dpc++; 7071 if (IS_QLA82XX(ha)) 7072 qla82xx_watchdog(vha); 7073 else if (IS_QLA8044(ha)) 7074 qla8044_watchdog(vha); 7075 } 7076 7077 if (!vha->vp_idx && IS_QLAFX00(ha)) 7078 qlafx00_timer_routine(vha); 7079 7080 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7081 vha->link_down_time++; 7082 7083 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7084 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7085 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7086 fcport->tgt_link_down_time++; 7087 } 7088 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7089 7090 /* Loop down handler. */ 7091 if (atomic_read(&vha->loop_down_timer) > 0 && 7092 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7093 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7094 && vha->flags.online) { 7095 7096 if (atomic_read(&vha->loop_down_timer) == 7097 vha->loop_down_abort_time) { 7098 7099 ql_log(ql_log_info, vha, 0x6008, 7100 "Loop down - aborting the queues before time expires.\n"); 7101 7102 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7103 atomic_set(&vha->loop_state, LOOP_DEAD); 7104 7105 /* 7106 * Schedule an ISP abort to return any FCP2-device 7107 * commands. 7108 */ 7109 /* NPIV - scan physical port only */ 7110 if (!vha->vp_idx) { 7111 spin_lock_irqsave(&ha->hardware_lock, 7112 cpu_flags); 7113 req = ha->req_q_map[0]; 7114 for (index = 1; 7115 index < req->num_outstanding_cmds; 7116 index++) { 7117 fc_port_t *sfcp; 7118 7119 sp = req->outstanding_cmds[index]; 7120 if (!sp) 7121 continue; 7122 if (sp->cmd_type != TYPE_SRB) 7123 continue; 7124 if (sp->type != SRB_SCSI_CMD) 7125 continue; 7126 sfcp = sp->fcport; 7127 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7128 continue; 7129 7130 if (IS_QLA82XX(ha)) 7131 set_bit(FCOE_CTX_RESET_NEEDED, 7132 &vha->dpc_flags); 7133 else 7134 set_bit(ISP_ABORT_NEEDED, 7135 &vha->dpc_flags); 7136 break; 7137 } 7138 spin_unlock_irqrestore(&ha->hardware_lock, 7139 cpu_flags); 7140 } 7141 start_dpc++; 7142 } 7143 7144 /* if the loop has been down for 4 minutes, reinit adapter */ 7145 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7146 if (!(vha->device_flags & DFLG_NO_CABLE)) { 7147 ql_log(ql_log_warn, vha, 0x6009, 7148 "Loop down - aborting ISP.\n"); 7149 7150 if (IS_QLA82XX(ha)) 7151 set_bit(FCOE_CTX_RESET_NEEDED, 7152 &vha->dpc_flags); 7153 else 7154 set_bit(ISP_ABORT_NEEDED, 7155 &vha->dpc_flags); 7156 } 7157 } 7158 ql_dbg(ql_dbg_timer, vha, 0x600a, 7159 "Loop down - seconds remaining %d.\n", 7160 atomic_read(&vha->loop_down_timer)); 7161 } 7162 /* Check if beacon LED needs to be blinked for physical host only */ 7163 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7164 /* There is no beacon_blink function for ISP82xx */ 7165 if (!IS_P3P_TYPE(ha)) { 7166 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7167 start_dpc++; 7168 } 7169 } 7170 7171 /* Process any deferred work. */ 7172 if (!list_empty(&vha->work_list)) { 7173 unsigned long flags; 7174 bool q = false; 7175 7176 spin_lock_irqsave(&vha->work_lock, flags); 7177 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7178 q = true; 7179 spin_unlock_irqrestore(&vha->work_lock, flags); 7180 if (q) 7181 queue_work(vha->hw->wq, &vha->iocb_work); 7182 } 7183 7184 /* 7185 * FC-NVME 7186 * see if the active AEN count has changed from what was last reported. 7187 */ 7188 index = atomic_read(&ha->nvme_active_aen_cnt); 7189 if (!vha->vp_idx && 7190 (index != ha->nvme_last_rptd_aen) && 7191 ha->zio_mode == QLA_ZIO_MODE_6 && 7192 !ha->flags.host_shutting_down) { 7193 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7194 ql_log(ql_log_info, vha, 0x3002, 7195 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7196 ha->nvme_last_rptd_aen); 7197 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7198 start_dpc++; 7199 } 7200 7201 if (!vha->vp_idx && 7202 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7203 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7204 ql_log(ql_log_info, vha, 0x3002, 7205 "Sched: Set ZIO exchange threshold to %d.\n", 7206 ha->last_zio_threshold); 7207 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7208 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7209 start_dpc++; 7210 } 7211 7212 /* Schedule the DPC routine if needed */ 7213 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7214 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7215 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || 7216 start_dpc || 7217 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7218 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7219 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7220 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7221 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7222 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7223 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7224 ql_dbg(ql_dbg_timer, vha, 0x600b, 7225 "isp_abort_needed=%d loop_resync_needed=%d " 7226 "fcport_update_needed=%d start_dpc=%d " 7227 "reset_marker_needed=%d", 7228 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7229 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7230 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), 7231 start_dpc, 7232 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7233 ql_dbg(ql_dbg_timer, vha, 0x600c, 7234 "beacon_blink_needed=%d isp_unrecoverable=%d " 7235 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7236 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7237 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7238 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7239 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7240 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7241 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7242 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7243 qla2xxx_wake_dpc(vha); 7244 } 7245 7246 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7247 } 7248 7249 /* Firmware interface routines. */ 7250 7251 #define FW_ISP21XX 0 7252 #define FW_ISP22XX 1 7253 #define FW_ISP2300 2 7254 #define FW_ISP2322 3 7255 #define FW_ISP24XX 4 7256 #define FW_ISP25XX 5 7257 #define FW_ISP81XX 6 7258 #define FW_ISP82XX 7 7259 #define FW_ISP2031 8 7260 #define FW_ISP8031 9 7261 #define FW_ISP27XX 10 7262 #define FW_ISP28XX 11 7263 7264 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7265 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7266 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7267 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7268 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7269 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7270 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7271 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7272 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7273 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7274 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7275 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7276 7277 7278 static DEFINE_MUTEX(qla_fw_lock); 7279 7280 static struct fw_blob qla_fw_blobs[] = { 7281 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7282 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7283 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7284 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7285 { .name = FW_FILE_ISP24XX, }, 7286 { .name = FW_FILE_ISP25XX, }, 7287 { .name = FW_FILE_ISP81XX, }, 7288 { .name = FW_FILE_ISP82XX, }, 7289 { .name = FW_FILE_ISP2031, }, 7290 { .name = FW_FILE_ISP8031, }, 7291 { .name = FW_FILE_ISP27XX, }, 7292 { .name = FW_FILE_ISP28XX, }, 7293 { .name = NULL, }, 7294 }; 7295 7296 struct fw_blob * 7297 qla2x00_request_firmware(scsi_qla_host_t *vha) 7298 { 7299 struct qla_hw_data *ha = vha->hw; 7300 struct fw_blob *blob; 7301 7302 if (IS_QLA2100(ha)) { 7303 blob = &qla_fw_blobs[FW_ISP21XX]; 7304 } else if (IS_QLA2200(ha)) { 7305 blob = &qla_fw_blobs[FW_ISP22XX]; 7306 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7307 blob = &qla_fw_blobs[FW_ISP2300]; 7308 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7309 blob = &qla_fw_blobs[FW_ISP2322]; 7310 } else if (IS_QLA24XX_TYPE(ha)) { 7311 blob = &qla_fw_blobs[FW_ISP24XX]; 7312 } else if (IS_QLA25XX(ha)) { 7313 blob = &qla_fw_blobs[FW_ISP25XX]; 7314 } else if (IS_QLA81XX(ha)) { 7315 blob = &qla_fw_blobs[FW_ISP81XX]; 7316 } else if (IS_QLA82XX(ha)) { 7317 blob = &qla_fw_blobs[FW_ISP82XX]; 7318 } else if (IS_QLA2031(ha)) { 7319 blob = &qla_fw_blobs[FW_ISP2031]; 7320 } else if (IS_QLA8031(ha)) { 7321 blob = &qla_fw_blobs[FW_ISP8031]; 7322 } else if (IS_QLA27XX(ha)) { 7323 blob = &qla_fw_blobs[FW_ISP27XX]; 7324 } else if (IS_QLA28XX(ha)) { 7325 blob = &qla_fw_blobs[FW_ISP28XX]; 7326 } else { 7327 return NULL; 7328 } 7329 7330 if (!blob->name) 7331 return NULL; 7332 7333 mutex_lock(&qla_fw_lock); 7334 if (blob->fw) 7335 goto out; 7336 7337 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7338 ql_log(ql_log_warn, vha, 0x0063, 7339 "Failed to load firmware image (%s).\n", blob->name); 7340 blob->fw = NULL; 7341 blob = NULL; 7342 } 7343 7344 out: 7345 mutex_unlock(&qla_fw_lock); 7346 return blob; 7347 } 7348 7349 static void 7350 qla2x00_release_firmware(void) 7351 { 7352 struct fw_blob *blob; 7353 7354 mutex_lock(&qla_fw_lock); 7355 for (blob = qla_fw_blobs; blob->name; blob++) 7356 release_firmware(blob->fw); 7357 mutex_unlock(&qla_fw_lock); 7358 } 7359 7360 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7361 { 7362 struct qla_hw_data *ha = vha->hw; 7363 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7364 struct qla_qpair *qpair = NULL; 7365 struct scsi_qla_host *vp; 7366 fc_port_t *fcport; 7367 int i; 7368 unsigned long flags; 7369 7370 ql_dbg(ql_dbg_aer, vha, 0x9000, 7371 "%s\n", __func__); 7372 ha->chip_reset++; 7373 7374 ha->base_qpair->chip_reset = ha->chip_reset; 7375 for (i = 0; i < ha->max_qpairs; i++) { 7376 if (ha->queue_pair_map[i]) 7377 ha->queue_pair_map[i]->chip_reset = 7378 ha->base_qpair->chip_reset; 7379 } 7380 7381 /* 7382 * purge mailbox might take a while. Slot Reset/chip reset 7383 * will take care of the purge 7384 */ 7385 7386 mutex_lock(&ha->mq_lock); 7387 ha->base_qpair->online = 0; 7388 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7389 qpair->online = 0; 7390 wmb(); 7391 mutex_unlock(&ha->mq_lock); 7392 7393 qla2x00_mark_all_devices_lost(vha); 7394 7395 spin_lock_irqsave(&ha->vport_slock, flags); 7396 list_for_each_entry(vp, &ha->vp_list, list) { 7397 atomic_inc(&vp->vref_count); 7398 spin_unlock_irqrestore(&ha->vport_slock, flags); 7399 qla2x00_mark_all_devices_lost(vp); 7400 spin_lock_irqsave(&ha->vport_slock, flags); 7401 atomic_dec(&vp->vref_count); 7402 } 7403 spin_unlock_irqrestore(&ha->vport_slock, flags); 7404 7405 /* Clear all async request states across all VPs. */ 7406 list_for_each_entry(fcport, &vha->vp_fcports, list) 7407 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7408 7409 spin_lock_irqsave(&ha->vport_slock, flags); 7410 list_for_each_entry(vp, &ha->vp_list, list) { 7411 atomic_inc(&vp->vref_count); 7412 spin_unlock_irqrestore(&ha->vport_slock, flags); 7413 list_for_each_entry(fcport, &vp->vp_fcports, list) 7414 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7415 spin_lock_irqsave(&ha->vport_slock, flags); 7416 atomic_dec(&vp->vref_count); 7417 } 7418 spin_unlock_irqrestore(&ha->vport_slock, flags); 7419 } 7420 7421 7422 static pci_ers_result_t 7423 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7424 { 7425 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7426 struct qla_hw_data *ha = vha->hw; 7427 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7428 7429 ql_log(ql_log_warn, vha, 0x9000, 7430 "PCI error detected, state %x.\n", state); 7431 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7432 7433 if (!atomic_read(&pdev->enable_cnt)) { 7434 ql_log(ql_log_info, vha, 0xffff, 7435 "PCI device is disabled,state %x\n", state); 7436 ret = PCI_ERS_RESULT_NEED_RESET; 7437 goto out; 7438 } 7439 7440 switch (state) { 7441 case pci_channel_io_normal: 7442 ha->flags.eeh_busy = 0; 7443 if (ql2xmqsupport || ql2xnvmeenable) { 7444 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7445 qla2xxx_wake_dpc(vha); 7446 } 7447 ret = PCI_ERS_RESULT_CAN_RECOVER; 7448 break; 7449 case pci_channel_io_frozen: 7450 qla_pci_set_eeh_busy(vha); 7451 ret = PCI_ERS_RESULT_NEED_RESET; 7452 break; 7453 case pci_channel_io_perm_failure: 7454 ha->flags.pci_channel_io_perm_failure = 1; 7455 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7456 if (ql2xmqsupport || ql2xnvmeenable) { 7457 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7458 qla2xxx_wake_dpc(vha); 7459 } 7460 ret = PCI_ERS_RESULT_DISCONNECT; 7461 } 7462 out: 7463 ql_dbg(ql_dbg_aer, vha, 0x600d, 7464 "PCI error detected returning [%x].\n", ret); 7465 return ret; 7466 } 7467 7468 static pci_ers_result_t 7469 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7470 { 7471 int risc_paused = 0; 7472 uint32_t stat; 7473 unsigned long flags; 7474 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7475 struct qla_hw_data *ha = base_vha->hw; 7476 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7477 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7478 7479 ql_log(ql_log_warn, base_vha, 0x9000, 7480 "mmio enabled\n"); 7481 7482 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7483 if (IS_QLA82XX(ha)) 7484 return PCI_ERS_RESULT_RECOVERED; 7485 7486 spin_lock_irqsave(&ha->hardware_lock, flags); 7487 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7488 stat = rd_reg_word(®->hccr); 7489 if (stat & HCCR_RISC_PAUSE) 7490 risc_paused = 1; 7491 } else if (IS_QLA23XX(ha)) { 7492 stat = rd_reg_dword(®->u.isp2300.host_status); 7493 if (stat & HSR_RISC_PAUSED) 7494 risc_paused = 1; 7495 } else if (IS_FWI2_CAPABLE(ha)) { 7496 stat = rd_reg_dword(®24->host_status); 7497 if (stat & HSRX_RISC_PAUSED) 7498 risc_paused = 1; 7499 } 7500 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7501 7502 if (risc_paused) { 7503 ql_log(ql_log_info, base_vha, 0x9003, 7504 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7505 qla2xxx_dump_fw(base_vha); 7506 } 7507 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7508 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7509 "mmio enabled returning.\n"); 7510 return PCI_ERS_RESULT_NEED_RESET; 7511 } 7512 7513 static pci_ers_result_t 7514 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7515 { 7516 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7517 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7518 struct qla_hw_data *ha = base_vha->hw; 7519 int rc; 7520 struct qla_qpair *qpair = NULL; 7521 7522 ql_log(ql_log_warn, base_vha, 0x9004, 7523 "Slot Reset.\n"); 7524 7525 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7526 /* Workaround: qla2xxx driver which access hardware earlier 7527 * needs error state to be pci_channel_io_online. 7528 * Otherwise mailbox command timesout. 7529 */ 7530 pdev->error_state = pci_channel_io_normal; 7531 7532 pci_restore_state(pdev); 7533 7534 /* pci_restore_state() clears the saved_state flag of the device 7535 * save restored state which resets saved_state flag 7536 */ 7537 pci_save_state(pdev); 7538 7539 if (ha->mem_only) 7540 rc = pci_enable_device_mem(pdev); 7541 else 7542 rc = pci_enable_device(pdev); 7543 7544 if (rc) { 7545 ql_log(ql_log_warn, base_vha, 0x9005, 7546 "Can't re-enable PCI device after reset.\n"); 7547 goto exit_slot_reset; 7548 } 7549 7550 7551 if (ha->isp_ops->pci_config(base_vha)) 7552 goto exit_slot_reset; 7553 7554 mutex_lock(&ha->mq_lock); 7555 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7556 qpair->online = 1; 7557 mutex_unlock(&ha->mq_lock); 7558 7559 ha->flags.eeh_busy = 0; 7560 base_vha->flags.online = 1; 7561 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7562 ha->isp_ops->abort_isp(base_vha); 7563 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7564 7565 if (qla2x00_isp_reg_stat(ha)) { 7566 ha->flags.eeh_busy = 1; 7567 qla_pci_error_cleanup(base_vha); 7568 ql_log(ql_log_warn, base_vha, 0x9005, 7569 "Device unable to recover from PCI error.\n"); 7570 } else { 7571 ret = PCI_ERS_RESULT_RECOVERED; 7572 } 7573 7574 exit_slot_reset: 7575 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7576 "Slot Reset returning %x.\n", ret); 7577 7578 return ret; 7579 } 7580 7581 static void 7582 qla2xxx_pci_resume(struct pci_dev *pdev) 7583 { 7584 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7585 struct qla_hw_data *ha = base_vha->hw; 7586 int ret; 7587 7588 ql_log(ql_log_warn, base_vha, 0x900f, 7589 "Pci Resume.\n"); 7590 7591 7592 ret = qla2x00_wait_for_hba_online(base_vha); 7593 if (ret != QLA_SUCCESS) { 7594 ql_log(ql_log_fatal, base_vha, 0x9002, 7595 "The device failed to resume I/O from slot/link_reset.\n"); 7596 } 7597 ha->pci_error_state = QLA_PCI_RESUME; 7598 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7599 "Pci Resume returning.\n"); 7600 } 7601 7602 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7603 { 7604 struct qla_hw_data *ha = vha->hw; 7605 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7606 bool do_cleanup = false; 7607 unsigned long flags; 7608 7609 if (ha->flags.eeh_busy) 7610 return; 7611 7612 spin_lock_irqsave(&base_vha->work_lock, flags); 7613 if (!ha->flags.eeh_busy) { 7614 ha->flags.eeh_busy = 1; 7615 do_cleanup = true; 7616 } 7617 spin_unlock_irqrestore(&base_vha->work_lock, flags); 7618 7619 if (do_cleanup) 7620 qla_pci_error_cleanup(base_vha); 7621 } 7622 7623 /* 7624 * this routine will schedule a task to pause IO from interrupt context 7625 * if caller sees a PCIE error event (register read = 0xf's) 7626 */ 7627 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 7628 { 7629 struct qla_hw_data *ha = vha->hw; 7630 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7631 7632 if (ha->flags.eeh_busy) 7633 return; 7634 7635 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 7636 qla2xxx_wake_dpc(base_vha); 7637 } 7638 7639 static void 7640 qla_pci_reset_prepare(struct pci_dev *pdev) 7641 { 7642 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7643 struct qla_hw_data *ha = base_vha->hw; 7644 struct qla_qpair *qpair; 7645 7646 ql_log(ql_log_warn, base_vha, 0xffff, 7647 "%s.\n", __func__); 7648 7649 /* 7650 * PCI FLR/function reset is about to reset the 7651 * slot. Stop the chip to stop all DMA access. 7652 * It is assumed that pci_reset_done will be called 7653 * after FLR to resume Chip operation. 7654 */ 7655 ha->flags.eeh_busy = 1; 7656 mutex_lock(&ha->mq_lock); 7657 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7658 qpair->online = 0; 7659 mutex_unlock(&ha->mq_lock); 7660 7661 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7662 qla2x00_abort_isp_cleanup(base_vha); 7663 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 7664 } 7665 7666 static void 7667 qla_pci_reset_done(struct pci_dev *pdev) 7668 { 7669 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7670 struct qla_hw_data *ha = base_vha->hw; 7671 struct qla_qpair *qpair; 7672 7673 ql_log(ql_log_warn, base_vha, 0xffff, 7674 "%s.\n", __func__); 7675 7676 /* 7677 * FLR just completed by PCI layer. Resume adapter 7678 */ 7679 ha->flags.eeh_busy = 0; 7680 mutex_lock(&ha->mq_lock); 7681 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7682 qpair->online = 1; 7683 mutex_unlock(&ha->mq_lock); 7684 7685 base_vha->flags.online = 1; 7686 ha->isp_ops->abort_isp(base_vha); 7687 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7688 } 7689 7690 static int qla2xxx_map_queues(struct Scsi_Host *shost) 7691 { 7692 int rc; 7693 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 7694 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 7695 7696 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 7697 rc = blk_mq_map_queues(qmap); 7698 else 7699 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset); 7700 return rc; 7701 } 7702 7703 struct scsi_host_template qla2xxx_driver_template = { 7704 .module = THIS_MODULE, 7705 .name = QLA2XXX_DRIVER_NAME, 7706 .queuecommand = qla2xxx_queuecommand, 7707 7708 .eh_timed_out = fc_eh_timed_out, 7709 .eh_abort_handler = qla2xxx_eh_abort, 7710 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 7711 .eh_device_reset_handler = qla2xxx_eh_device_reset, 7712 .eh_target_reset_handler = qla2xxx_eh_target_reset, 7713 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 7714 .eh_host_reset_handler = qla2xxx_eh_host_reset, 7715 7716 .slave_configure = qla2xxx_slave_configure, 7717 7718 .slave_alloc = qla2xxx_slave_alloc, 7719 .slave_destroy = qla2xxx_slave_destroy, 7720 .scan_finished = qla2xxx_scan_finished, 7721 .scan_start = qla2xxx_scan_start, 7722 .change_queue_depth = scsi_change_queue_depth, 7723 .map_queues = qla2xxx_map_queues, 7724 .this_id = -1, 7725 .cmd_per_lun = 3, 7726 .sg_tablesize = SG_ALL, 7727 7728 .max_sectors = 0xFFFF, 7729 .shost_attrs = qla2x00_host_attrs, 7730 7731 .supported_mode = MODE_INITIATOR, 7732 .track_queue_depth = 1, 7733 .cmd_size = sizeof(srb_t), 7734 }; 7735 7736 static const struct pci_error_handlers qla2xxx_err_handler = { 7737 .error_detected = qla2xxx_pci_error_detected, 7738 .mmio_enabled = qla2xxx_pci_mmio_enabled, 7739 .slot_reset = qla2xxx_pci_slot_reset, 7740 .resume = qla2xxx_pci_resume, 7741 .reset_prepare = qla_pci_reset_prepare, 7742 .reset_done = qla_pci_reset_done, 7743 }; 7744 7745 static struct pci_device_id qla2xxx_pci_tbl[] = { 7746 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 7747 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 7748 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 7749 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 7750 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 7751 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 7752 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 7753 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 7754 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 7755 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 7756 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 7757 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 7758 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 7759 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 7760 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 7761 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 7762 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 7763 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 7764 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 7765 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 7766 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 7767 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 7768 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 7769 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 7770 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 7771 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 7772 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 7773 { 0 }, 7774 }; 7775 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 7776 7777 static struct pci_driver qla2xxx_pci_driver = { 7778 .name = QLA2XXX_DRIVER_NAME, 7779 .driver = { 7780 .owner = THIS_MODULE, 7781 }, 7782 .id_table = qla2xxx_pci_tbl, 7783 .probe = qla2x00_probe_one, 7784 .remove = qla2x00_remove_one, 7785 .shutdown = qla2x00_shutdown, 7786 .err_handler = &qla2xxx_err_handler, 7787 }; 7788 7789 static const struct file_operations apidev_fops = { 7790 .owner = THIS_MODULE, 7791 .llseek = noop_llseek, 7792 }; 7793 7794 /** 7795 * qla2x00_module_init - Module initialization. 7796 **/ 7797 static int __init 7798 qla2x00_module_init(void) 7799 { 7800 int ret = 0; 7801 7802 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 7803 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 7804 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 7805 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 7806 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 7807 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 7808 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 7809 BUILD_BUG_ON(sizeof(request_t) != 64); 7810 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 7811 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 7812 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 7813 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 7814 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 7815 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 7816 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 7817 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 7818 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 7819 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 7820 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 7821 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 7822 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2344); 7823 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 7824 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 7825 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 7826 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 7827 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 7828 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 7829 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 7830 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 7831 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 7832 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 7833 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 7834 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 7835 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 7836 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 7837 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 7838 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 7839 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 7840 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 7841 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 7842 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 7843 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 7844 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 7845 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 7846 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 7847 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 7848 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 7849 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 7850 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 7851 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 7852 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 7853 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 7854 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 7855 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 7856 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 7857 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 7858 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 7859 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 7860 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 7861 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 7862 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 7863 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 7864 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 7865 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 7866 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 7867 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 7868 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 7869 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 7870 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 7871 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 7872 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 7873 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 7874 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 7875 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 7876 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 7877 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 7878 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 7879 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 7880 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 7881 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 7882 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 7883 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 7884 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 7885 BUILD_BUG_ON(sizeof(target_id_t) != 2); 7886 7887 /* Allocate cache for SRBs. */ 7888 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 7889 SLAB_HWCACHE_ALIGN, NULL); 7890 if (srb_cachep == NULL) { 7891 ql_log(ql_log_fatal, NULL, 0x0001, 7892 "Unable to allocate SRB cache...Failing load!.\n"); 7893 return -ENOMEM; 7894 } 7895 7896 /* Initialize target kmem_cache and mem_pools */ 7897 ret = qlt_init(); 7898 if (ret < 0) { 7899 goto destroy_cache; 7900 } else if (ret > 0) { 7901 /* 7902 * If initiator mode is explictly disabled by qlt_init(), 7903 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 7904 * performing scsi_scan_target() during LOOP UP event. 7905 */ 7906 qla2xxx_transport_functions.disable_target_scan = 1; 7907 qla2xxx_transport_vport_functions.disable_target_scan = 1; 7908 } 7909 7910 /* Derive version string. */ 7911 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 7912 if (ql2xextended_error_logging) 7913 strcat(qla2x00_version_str, "-debug"); 7914 if (ql2xextended_error_logging == 1) 7915 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 7916 7917 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL) 7918 qla_insert_tgt_attrs(); 7919 7920 qla2xxx_transport_template = 7921 fc_attach_transport(&qla2xxx_transport_functions); 7922 if (!qla2xxx_transport_template) { 7923 ql_log(ql_log_fatal, NULL, 0x0002, 7924 "fc_attach_transport failed...Failing load!.\n"); 7925 ret = -ENODEV; 7926 goto qlt_exit; 7927 } 7928 7929 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 7930 if (apidev_major < 0) { 7931 ql_log(ql_log_fatal, NULL, 0x0003, 7932 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 7933 } 7934 7935 qla2xxx_transport_vport_template = 7936 fc_attach_transport(&qla2xxx_transport_vport_functions); 7937 if (!qla2xxx_transport_vport_template) { 7938 ql_log(ql_log_fatal, NULL, 0x0004, 7939 "fc_attach_transport vport failed...Failing load!.\n"); 7940 ret = -ENODEV; 7941 goto unreg_chrdev; 7942 } 7943 ql_log(ql_log_info, NULL, 0x0005, 7944 "QLogic Fibre Channel HBA Driver: %s.\n", 7945 qla2x00_version_str); 7946 ret = pci_register_driver(&qla2xxx_pci_driver); 7947 if (ret) { 7948 ql_log(ql_log_fatal, NULL, 0x0006, 7949 "pci_register_driver failed...ret=%d Failing load!.\n", 7950 ret); 7951 goto release_vport_transport; 7952 } 7953 return ret; 7954 7955 release_vport_transport: 7956 fc_release_transport(qla2xxx_transport_vport_template); 7957 7958 unreg_chrdev: 7959 if (apidev_major >= 0) 7960 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7961 fc_release_transport(qla2xxx_transport_template); 7962 7963 qlt_exit: 7964 qlt_exit(); 7965 7966 destroy_cache: 7967 kmem_cache_destroy(srb_cachep); 7968 return ret; 7969 } 7970 7971 /** 7972 * qla2x00_module_exit - Module cleanup. 7973 **/ 7974 static void __exit 7975 qla2x00_module_exit(void) 7976 { 7977 pci_unregister_driver(&qla2xxx_pci_driver); 7978 qla2x00_release_firmware(); 7979 kmem_cache_destroy(ctx_cachep); 7980 fc_release_transport(qla2xxx_transport_vport_template); 7981 if (apidev_major >= 0) 7982 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 7983 fc_release_transport(qla2xxx_transport_template); 7984 qlt_exit(); 7985 kmem_cache_destroy(srb_cachep); 7986 } 7987 7988 module_init(qla2x00_module_init); 7989 module_exit(qla2x00_module_exit); 7990 7991 MODULE_AUTHOR("QLogic Corporation"); 7992 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 7993 MODULE_LICENSE("GPL"); 7994 MODULE_FIRMWARE(FW_FILE_ISP21XX); 7995 MODULE_FIRMWARE(FW_FILE_ISP22XX); 7996 MODULE_FIRMWARE(FW_FILE_ISP2300); 7997 MODULE_FIRMWARE(FW_FILE_ISP2322); 7998 MODULE_FIRMWARE(FW_FILE_ISP24XX); 7999 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8000